17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5ee88d2b9Skchow * Common Development and Distribution License (the "License"). 6ee88d2b9Skchow * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 226e5580c9SFrank Van Der Linden * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. 237c478bd9Sstevel@tonic-gate */ 24cef70d2cSBill Holler /* 25cef70d2cSBill Holler * Copyright (c) 2009, Intel Corporation. 26cef70d2cSBill Holler * All rights reserved. 27cef70d2cSBill Holler */ 288031591dSSrihari Venkatesan /* 298031591dSSrihari Venkatesan * Portions Copyright 2009 Advanced Micro Devices, Inc. 308031591dSSrihari Venkatesan */ 317c478bd9Sstevel@tonic-gate 327c478bd9Sstevel@tonic-gate /* 337c478bd9Sstevel@tonic-gate * Various routines to handle identification 347c478bd9Sstevel@tonic-gate * and classification of x86 processors. 357c478bd9Sstevel@tonic-gate */ 367c478bd9Sstevel@tonic-gate 377c478bd9Sstevel@tonic-gate #include <sys/types.h> 387c478bd9Sstevel@tonic-gate #include <sys/archsystm.h> 397c478bd9Sstevel@tonic-gate #include <sys/x86_archext.h> 407c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 417c478bd9Sstevel@tonic-gate #include <sys/systm.h> 427c478bd9Sstevel@tonic-gate #include <sys/cmn_err.h> 437c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 447c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 457c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 467c478bd9Sstevel@tonic-gate #include <sys/processor.h> 475b8a6efeSbholler #include <sys/sysmacros.h> 48fb2f18f8Sesaxe #include <sys/pg.h> 497c478bd9Sstevel@tonic-gate #include <sys/fp.h> 507c478bd9Sstevel@tonic-gate #include <sys/controlregs.h> 517c478bd9Sstevel@tonic-gate #include <sys/auxv_386.h> 527c478bd9Sstevel@tonic-gate #include <sys/bitmap.h> 537c478bd9Sstevel@tonic-gate #include <sys/memnode.h> 548031591dSSrihari Venkatesan #include <sys/pci_cfgspace.h> 557c478bd9Sstevel@tonic-gate 56e4b86885SCheng Sean Ye #ifdef __xpv 57e4b86885SCheng Sean Ye #include <sys/hypervisor.h> 58e774b42bSBill Holler #else 59e774b42bSBill Holler #include <sys/ontrap.h> 60e4b86885SCheng Sean Ye #endif 61e4b86885SCheng Sean Ye 627c478bd9Sstevel@tonic-gate /* 637c478bd9Sstevel@tonic-gate * Pass 0 of cpuid feature analysis happens in locore. It contains special code 647c478bd9Sstevel@tonic-gate * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 657c478bd9Sstevel@tonic-gate * them accordingly. For most modern processors, feature detection occurs here 667c478bd9Sstevel@tonic-gate * in pass 1. 677c478bd9Sstevel@tonic-gate * 687c478bd9Sstevel@tonic-gate * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 697c478bd9Sstevel@tonic-gate * for the boot CPU and does the basic analysis that the early kernel needs. 707c478bd9Sstevel@tonic-gate * x86_feature is set based on the return value of cpuid_pass1() of the boot 717c478bd9Sstevel@tonic-gate * CPU. 727c478bd9Sstevel@tonic-gate * 737c478bd9Sstevel@tonic-gate * Pass 1 includes: 747c478bd9Sstevel@tonic-gate * 757c478bd9Sstevel@tonic-gate * o Determining vendor/model/family/stepping and setting x86_type and 767c478bd9Sstevel@tonic-gate * x86_vendor accordingly. 777c478bd9Sstevel@tonic-gate * o Processing the feature flags returned by the cpuid instruction while 787c478bd9Sstevel@tonic-gate * applying any workarounds or tricks for the specific processor. 797c478bd9Sstevel@tonic-gate * o Mapping the feature flags into Solaris feature bits (X86_*). 807c478bd9Sstevel@tonic-gate * o Processing extended feature flags if supported by the processor, 817c478bd9Sstevel@tonic-gate * again while applying specific processor knowledge. 827c478bd9Sstevel@tonic-gate * o Determining the CMT characteristics of the system. 837c478bd9Sstevel@tonic-gate * 847c478bd9Sstevel@tonic-gate * Pass 1 is done on non-boot CPUs during their initialization and the results 857c478bd9Sstevel@tonic-gate * are used only as a meager attempt at ensuring that all processors within the 867c478bd9Sstevel@tonic-gate * system support the same features. 877c478bd9Sstevel@tonic-gate * 887c478bd9Sstevel@tonic-gate * Pass 2 of cpuid feature analysis happens just at the beginning 897c478bd9Sstevel@tonic-gate * of startup(). It just copies in and corrects the remainder 907c478bd9Sstevel@tonic-gate * of the cpuid data we depend on: standard cpuid functions that we didn't 917c478bd9Sstevel@tonic-gate * need for pass1 feature analysis, and extended cpuid functions beyond the 927c478bd9Sstevel@tonic-gate * simple feature processing done in pass1. 937c478bd9Sstevel@tonic-gate * 947c478bd9Sstevel@tonic-gate * Pass 3 of cpuid analysis is invoked after basic kernel services; in 957c478bd9Sstevel@tonic-gate * particular kernel memory allocation has been made available. It creates a 967c478bd9Sstevel@tonic-gate * readable brand string based on the data collected in the first two passes. 977c478bd9Sstevel@tonic-gate * 987c478bd9Sstevel@tonic-gate * Pass 4 of cpuid analysis is invoked after post_startup() when all 997c478bd9Sstevel@tonic-gate * the support infrastructure for various hardware features has been 1007c478bd9Sstevel@tonic-gate * initialized. It determines which processor features will be reported 1017c478bd9Sstevel@tonic-gate * to userland via the aux vector. 1027c478bd9Sstevel@tonic-gate * 1037c478bd9Sstevel@tonic-gate * All passes are executed on all CPUs, but only the boot CPU determines what 1047c478bd9Sstevel@tonic-gate * features the kernel will use. 1057c478bd9Sstevel@tonic-gate * 1067c478bd9Sstevel@tonic-gate * Much of the worst junk in this file is for the support of processors 1077c478bd9Sstevel@tonic-gate * that didn't really implement the cpuid instruction properly. 1087c478bd9Sstevel@tonic-gate * 1097c478bd9Sstevel@tonic-gate * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 1107c478bd9Sstevel@tonic-gate * the pass numbers. Accordingly, changes to the pass code may require changes 1117c478bd9Sstevel@tonic-gate * to the accessor code. 1127c478bd9Sstevel@tonic-gate */ 1137c478bd9Sstevel@tonic-gate 1147c478bd9Sstevel@tonic-gate uint_t x86_feature = 0; 1157c478bd9Sstevel@tonic-gate uint_t x86_vendor = X86_VENDOR_IntelClone; 1167c478bd9Sstevel@tonic-gate uint_t x86_type = X86_TYPE_OTHER; 11786c1f4dcSVikram Hegde uint_t x86_clflush_size = 0; 1187c478bd9Sstevel@tonic-gate 1197c478bd9Sstevel@tonic-gate uint_t pentiumpro_bug4046376; 1207c478bd9Sstevel@tonic-gate uint_t pentiumpro_bug4064495; 1217c478bd9Sstevel@tonic-gate 1227c478bd9Sstevel@tonic-gate uint_t enable486; 1237997e108SSurya Prakki /* 124b9bfdccdSStuart Maybee * This is set to platform type Solaris is running on. 1257997e108SSurya Prakki */ 126349b53ddSStuart Maybee static int platform_type = -1; 127349b53ddSStuart Maybee 128349b53ddSStuart Maybee #if !defined(__xpv) 129349b53ddSStuart Maybee /* 130349b53ddSStuart Maybee * Variable to patch if hypervisor platform detection needs to be 131349b53ddSStuart Maybee * disabled (e.g. platform_type will always be HW_NATIVE if this is 0). 132349b53ddSStuart Maybee */ 133349b53ddSStuart Maybee int enable_platform_detection = 1; 134349b53ddSStuart Maybee #endif 1357c478bd9Sstevel@tonic-gate 1367c478bd9Sstevel@tonic-gate /* 137f98fbcecSbholler * monitor/mwait info. 1385b8a6efeSbholler * 1395b8a6efeSbholler * size_actual and buf_actual are the real address and size allocated to get 1405b8a6efeSbholler * proper mwait_buf alignement. buf_actual and size_actual should be passed 1415b8a6efeSbholler * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 1425b8a6efeSbholler * processor cache-line alignment, but this is not guarantied in the furture. 143f98fbcecSbholler */ 144f98fbcecSbholler struct mwait_info { 145f98fbcecSbholler size_t mon_min; /* min size to avoid missed wakeups */ 146f98fbcecSbholler size_t mon_max; /* size to avoid false wakeups */ 1475b8a6efeSbholler size_t size_actual; /* size actually allocated */ 1485b8a6efeSbholler void *buf_actual; /* memory actually allocated */ 149f98fbcecSbholler uint32_t support; /* processor support of monitor/mwait */ 150f98fbcecSbholler }; 151f98fbcecSbholler 152f98fbcecSbholler /* 1537c478bd9Sstevel@tonic-gate * These constants determine how many of the elements of the 1547c478bd9Sstevel@tonic-gate * cpuid we cache in the cpuid_info data structure; the 1557c478bd9Sstevel@tonic-gate * remaining elements are accessible via the cpuid instruction. 1567c478bd9Sstevel@tonic-gate */ 1577c478bd9Sstevel@tonic-gate 1587c478bd9Sstevel@tonic-gate #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 1598031591dSSrihari Venkatesan #define NMAX_CPI_EXTD 0x1c /* eax = 0x80000000 .. 0x8000001b */ 1608031591dSSrihari Venkatesan 1618031591dSSrihari Venkatesan /* 1628031591dSSrihari Venkatesan * Some terminology needs to be explained: 1638031591dSSrihari Venkatesan * - Socket: Something that can be plugged into a motherboard. 1648031591dSSrihari Venkatesan * - Package: Same as socket 1658031591dSSrihari Venkatesan * - Chip: Same as socket. Note that AMD's documentation uses term "chip" 1668031591dSSrihari Venkatesan * differently: there, chip is the same as processor node (below) 1678031591dSSrihari Venkatesan * - Processor node: Some AMD processors have more than one 1688031591dSSrihari Venkatesan * "subprocessor" embedded in a package. These subprocessors (nodes) 1698031591dSSrihari Venkatesan * are fully-functional processors themselves with cores, caches, 1708031591dSSrihari Venkatesan * memory controllers, PCI configuration spaces. They are connected 1718031591dSSrihari Venkatesan * inside the package with Hypertransport links. On single-node 1728031591dSSrihari Venkatesan * processors, processor node is equivalent to chip/socket/package. 1738031591dSSrihari Venkatesan */ 1747c478bd9Sstevel@tonic-gate 1757c478bd9Sstevel@tonic-gate struct cpuid_info { 1767c478bd9Sstevel@tonic-gate uint_t cpi_pass; /* last pass completed */ 1777c478bd9Sstevel@tonic-gate /* 1787c478bd9Sstevel@tonic-gate * standard function information 1797c478bd9Sstevel@tonic-gate */ 1807c478bd9Sstevel@tonic-gate uint_t cpi_maxeax; /* fn 0: %eax */ 1817c478bd9Sstevel@tonic-gate char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 1827c478bd9Sstevel@tonic-gate uint_t cpi_vendor; /* enum of cpi_vendorstr */ 1837c478bd9Sstevel@tonic-gate 1847c478bd9Sstevel@tonic-gate uint_t cpi_family; /* fn 1: extended family */ 1857c478bd9Sstevel@tonic-gate uint_t cpi_model; /* fn 1: extended model */ 1867c478bd9Sstevel@tonic-gate uint_t cpi_step; /* fn 1: stepping */ 1878031591dSSrihari Venkatesan chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */ 1888031591dSSrihari Venkatesan /* AMD: package/socket # */ 1897c478bd9Sstevel@tonic-gate uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 1907c478bd9Sstevel@tonic-gate int cpi_clogid; /* fn 1: %ebx: thread # */ 1918949bcd6Sandrei uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 1927c478bd9Sstevel@tonic-gate uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 1937c478bd9Sstevel@tonic-gate uint_t cpi_ncache; /* fn 2: number of elements */ 194d129bde2Sesaxe uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 195d129bde2Sesaxe id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 196d129bde2Sesaxe uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 197d129bde2Sesaxe struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 1988949bcd6Sandrei struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 1997c478bd9Sstevel@tonic-gate /* 2007c478bd9Sstevel@tonic-gate * extended function information 2017c478bd9Sstevel@tonic-gate */ 2027c478bd9Sstevel@tonic-gate uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 2037c478bd9Sstevel@tonic-gate char cpi_brandstr[49]; /* fn 0x8000000[234] */ 2047c478bd9Sstevel@tonic-gate uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 2057c478bd9Sstevel@tonic-gate uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 2068031591dSSrihari Venkatesan struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */ 2078031591dSSrihari Venkatesan 20810569901Sgavinm id_t cpi_coreid; /* same coreid => strands share core */ 20910569901Sgavinm int cpi_pkgcoreid; /* core number within single package */ 2108949bcd6Sandrei uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 2118949bcd6Sandrei /* Intel: fn 4: %eax[31-26] */ 2127c478bd9Sstevel@tonic-gate /* 2137c478bd9Sstevel@tonic-gate * supported feature information 2147c478bd9Sstevel@tonic-gate */ 215ae115bc7Smrj uint32_t cpi_support[5]; 2167c478bd9Sstevel@tonic-gate #define STD_EDX_FEATURES 0 2177c478bd9Sstevel@tonic-gate #define AMD_EDX_FEATURES 1 2187c478bd9Sstevel@tonic-gate #define TM_EDX_FEATURES 2 2197c478bd9Sstevel@tonic-gate #define STD_ECX_FEATURES 3 220ae115bc7Smrj #define AMD_ECX_FEATURES 4 2218a40a695Sgavinm /* 2228a40a695Sgavinm * Synthesized information, where known. 2238a40a695Sgavinm */ 2248a40a695Sgavinm uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 2258a40a695Sgavinm const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 2268a40a695Sgavinm uint32_t cpi_socket; /* Chip package/socket type */ 227f98fbcecSbholler 228f98fbcecSbholler struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 229b6917abeSmishra uint32_t cpi_apicid; 2308031591dSSrihari Venkatesan uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */ 2318031591dSSrihari Venkatesan uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */ 2328031591dSSrihari Venkatesan /* Intel: 1 */ 2337c478bd9Sstevel@tonic-gate }; 2347c478bd9Sstevel@tonic-gate 2357c478bd9Sstevel@tonic-gate 2367c478bd9Sstevel@tonic-gate static struct cpuid_info cpuid_info0; 2377c478bd9Sstevel@tonic-gate 2387c478bd9Sstevel@tonic-gate /* 2397c478bd9Sstevel@tonic-gate * These bit fields are defined by the Intel Application Note AP-485 2407c478bd9Sstevel@tonic-gate * "Intel Processor Identification and the CPUID Instruction" 2417c478bd9Sstevel@tonic-gate */ 2427c478bd9Sstevel@tonic-gate #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 2437c478bd9Sstevel@tonic-gate #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 2447c478bd9Sstevel@tonic-gate #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 2457c478bd9Sstevel@tonic-gate #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 2467c478bd9Sstevel@tonic-gate #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 2477c478bd9Sstevel@tonic-gate #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 2487c478bd9Sstevel@tonic-gate 2497c478bd9Sstevel@tonic-gate #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 2507c478bd9Sstevel@tonic-gate #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 2517c478bd9Sstevel@tonic-gate #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 2527c478bd9Sstevel@tonic-gate #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 2537c478bd9Sstevel@tonic-gate 2547c478bd9Sstevel@tonic-gate #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 2557c478bd9Sstevel@tonic-gate #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 2567c478bd9Sstevel@tonic-gate #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 2577c478bd9Sstevel@tonic-gate #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 2587c478bd9Sstevel@tonic-gate 2597c478bd9Sstevel@tonic-gate #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 2607c478bd9Sstevel@tonic-gate #define CPI_XMAXEAX_MAX 0x80000100 261d129bde2Sesaxe #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 262b6917abeSmishra #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 263d129bde2Sesaxe 264d129bde2Sesaxe /* 265d129bde2Sesaxe * Function 4 (Deterministic Cache Parameters) macros 266d129bde2Sesaxe * Defined by Intel Application Note AP-485 267d129bde2Sesaxe */ 268d129bde2Sesaxe #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 269d129bde2Sesaxe #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 270d129bde2Sesaxe #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 271d129bde2Sesaxe #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 272d129bde2Sesaxe #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 273d129bde2Sesaxe #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 274b6917abeSmishra #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 275d129bde2Sesaxe 276d129bde2Sesaxe #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 277d129bde2Sesaxe #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 278d129bde2Sesaxe #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 279d129bde2Sesaxe 280d129bde2Sesaxe #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 281d129bde2Sesaxe 282d129bde2Sesaxe #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 283d129bde2Sesaxe 2847c478bd9Sstevel@tonic-gate 2857c478bd9Sstevel@tonic-gate /* 2865ff02082Sdmick * A couple of shorthand macros to identify "later" P6-family chips 2875ff02082Sdmick * like the Pentium M and Core. First, the "older" P6-based stuff 2885ff02082Sdmick * (loosely defined as "pre-Pentium-4"): 2895ff02082Sdmick * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 2905ff02082Sdmick */ 2915ff02082Sdmick 2925ff02082Sdmick #define IS_LEGACY_P6(cpi) ( \ 2935ff02082Sdmick cpi->cpi_family == 6 && \ 2945ff02082Sdmick (cpi->cpi_model == 1 || \ 2955ff02082Sdmick cpi->cpi_model == 3 || \ 2965ff02082Sdmick cpi->cpi_model == 5 || \ 2975ff02082Sdmick cpi->cpi_model == 6 || \ 2985ff02082Sdmick cpi->cpi_model == 7 || \ 2995ff02082Sdmick cpi->cpi_model == 8 || \ 3005ff02082Sdmick cpi->cpi_model == 0xA || \ 3015ff02082Sdmick cpi->cpi_model == 0xB) \ 3025ff02082Sdmick ) 3035ff02082Sdmick 3045ff02082Sdmick /* A "new F6" is everything with family 6 that's not the above */ 3055ff02082Sdmick #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 3065ff02082Sdmick 307bf91205bSksadhukh /* Extended family/model support */ 308bf91205bSksadhukh #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 309bf91205bSksadhukh cpi->cpi_family >= 0xf) 310bf91205bSksadhukh 3115ff02082Sdmick /* 312f98fbcecSbholler * Info for monitor/mwait idle loop. 313f98fbcecSbholler * 314f98fbcecSbholler * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 315f98fbcecSbholler * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 316f98fbcecSbholler * 2006. 317f98fbcecSbholler * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 318f98fbcecSbholler * Documentation Updates" #33633, Rev 2.05, December 2006. 319f98fbcecSbholler */ 320f98fbcecSbholler #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 321f98fbcecSbholler #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 322f98fbcecSbholler #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 323f98fbcecSbholler #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 324f98fbcecSbholler #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 325f98fbcecSbholler #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 326f98fbcecSbholler #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 327f98fbcecSbholler #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 328f98fbcecSbholler /* 329f98fbcecSbholler * Number of sub-cstates for a given c-state. 330f98fbcecSbholler */ 331f98fbcecSbholler #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 332f98fbcecSbholler BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 333f98fbcecSbholler 3348a40a695Sgavinm /* 335e4b86885SCheng Sean Ye * Functions we consune from cpuid_subr.c; don't publish these in a header 336e4b86885SCheng Sean Ye * file to try and keep people using the expected cpuid_* interfaces. 3378a40a695Sgavinm */ 338e4b86885SCheng Sean Ye extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 33989e921d5SKuriakose Kuruvilla extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t); 340e4b86885SCheng Sean Ye extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 341e4b86885SCheng Sean Ye extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 342e4b86885SCheng Sean Ye extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 3438a40a695Sgavinm 3448a40a695Sgavinm /* 345ae115bc7Smrj * Apply up various platform-dependent restrictions where the 346ae115bc7Smrj * underlying platform restrictions mean the CPU can be marked 347ae115bc7Smrj * as less capable than its cpuid instruction would imply. 348ae115bc7Smrj */ 349843e1988Sjohnlev #if defined(__xpv) 350843e1988Sjohnlev static void 351843e1988Sjohnlev platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 352843e1988Sjohnlev { 353843e1988Sjohnlev switch (eax) { 354e4b86885SCheng Sean Ye case 1: { 355e4b86885SCheng Sean Ye uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 356e4b86885SCheng Sean Ye 0 : CPUID_INTC_EDX_MCA; 357843e1988Sjohnlev cp->cp_edx &= 358e4b86885SCheng Sean Ye ~(mcamask | 359e4b86885SCheng Sean Ye CPUID_INTC_EDX_PSE | 360843e1988Sjohnlev CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 361843e1988Sjohnlev CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 362843e1988Sjohnlev CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 363843e1988Sjohnlev CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 364843e1988Sjohnlev CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 365843e1988Sjohnlev break; 366e4b86885SCheng Sean Ye } 367ae115bc7Smrj 368843e1988Sjohnlev case 0x80000001: 369843e1988Sjohnlev cp->cp_edx &= 370843e1988Sjohnlev ~(CPUID_AMD_EDX_PSE | 371843e1988Sjohnlev CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 372843e1988Sjohnlev CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 373843e1988Sjohnlev CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 374843e1988Sjohnlev CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 375843e1988Sjohnlev CPUID_AMD_EDX_TSCP); 376843e1988Sjohnlev cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 377843e1988Sjohnlev break; 378843e1988Sjohnlev default: 379843e1988Sjohnlev break; 380843e1988Sjohnlev } 381843e1988Sjohnlev 382843e1988Sjohnlev switch (vendor) { 383843e1988Sjohnlev case X86_VENDOR_Intel: 384843e1988Sjohnlev switch (eax) { 385843e1988Sjohnlev case 4: 386843e1988Sjohnlev /* 387843e1988Sjohnlev * Zero out the (ncores-per-chip - 1) field 388843e1988Sjohnlev */ 389843e1988Sjohnlev cp->cp_eax &= 0x03fffffff; 390843e1988Sjohnlev break; 391843e1988Sjohnlev default: 392843e1988Sjohnlev break; 393843e1988Sjohnlev } 394843e1988Sjohnlev break; 395843e1988Sjohnlev case X86_VENDOR_AMD: 396843e1988Sjohnlev switch (eax) { 3972ef50f01SJoe Bonasera 3982ef50f01SJoe Bonasera case 0x80000001: 3992ef50f01SJoe Bonasera cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D; 4002ef50f01SJoe Bonasera break; 4012ef50f01SJoe Bonasera 402843e1988Sjohnlev case 0x80000008: 403843e1988Sjohnlev /* 404843e1988Sjohnlev * Zero out the (ncores-per-chip - 1) field 405843e1988Sjohnlev */ 406843e1988Sjohnlev cp->cp_ecx &= 0xffffff00; 407843e1988Sjohnlev break; 408843e1988Sjohnlev default: 409843e1988Sjohnlev break; 410843e1988Sjohnlev } 411843e1988Sjohnlev break; 412843e1988Sjohnlev default: 413843e1988Sjohnlev break; 414843e1988Sjohnlev } 415843e1988Sjohnlev } 416843e1988Sjohnlev #else 417ae115bc7Smrj #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 418843e1988Sjohnlev #endif 419ae115bc7Smrj 420ae115bc7Smrj /* 4217c478bd9Sstevel@tonic-gate * Some undocumented ways of patching the results of the cpuid 4227c478bd9Sstevel@tonic-gate * instruction to permit running Solaris 10 on future cpus that 4237c478bd9Sstevel@tonic-gate * we don't currently support. Could be set to non-zero values 4247c478bd9Sstevel@tonic-gate * via settings in eeprom. 4257c478bd9Sstevel@tonic-gate */ 4267c478bd9Sstevel@tonic-gate 4277c478bd9Sstevel@tonic-gate uint32_t cpuid_feature_ecx_include; 4287c478bd9Sstevel@tonic-gate uint32_t cpuid_feature_ecx_exclude; 4297c478bd9Sstevel@tonic-gate uint32_t cpuid_feature_edx_include; 4307c478bd9Sstevel@tonic-gate uint32_t cpuid_feature_edx_exclude; 4317c478bd9Sstevel@tonic-gate 432a3114836SGerry Liu /* 433a3114836SGerry Liu * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs. 434a3114836SGerry Liu */ 435ae115bc7Smrj void 436ae115bc7Smrj cpuid_alloc_space(cpu_t *cpu) 437ae115bc7Smrj { 438ae115bc7Smrj /* 439ae115bc7Smrj * By convention, cpu0 is the boot cpu, which is set up 440ae115bc7Smrj * before memory allocation is available. All other cpus get 441ae115bc7Smrj * their cpuid_info struct allocated here. 442ae115bc7Smrj */ 443ae115bc7Smrj ASSERT(cpu->cpu_id != 0); 444a3114836SGerry Liu ASSERT(cpu->cpu_m.mcpu_cpi == NULL); 445ae115bc7Smrj cpu->cpu_m.mcpu_cpi = 446ae115bc7Smrj kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 447ae115bc7Smrj } 448ae115bc7Smrj 449ae115bc7Smrj void 450ae115bc7Smrj cpuid_free_space(cpu_t *cpu) 451ae115bc7Smrj { 452d129bde2Sesaxe struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 453d129bde2Sesaxe int i; 454d129bde2Sesaxe 455a3114836SGerry Liu ASSERT(cpi != NULL); 456a3114836SGerry Liu ASSERT(cpi != &cpuid_info0); 457d129bde2Sesaxe 458d129bde2Sesaxe /* 459d129bde2Sesaxe * Free up any function 4 related dynamic storage 460d129bde2Sesaxe */ 461d129bde2Sesaxe for (i = 1; i < cpi->cpi_std_4_size; i++) 462d129bde2Sesaxe kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 463d129bde2Sesaxe if (cpi->cpi_std_4_size > 0) 464d129bde2Sesaxe kmem_free(cpi->cpi_std_4, 465d129bde2Sesaxe cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 466d129bde2Sesaxe 467a3114836SGerry Liu kmem_free(cpi, sizeof (*cpi)); 468a3114836SGerry Liu cpu->cpu_m.mcpu_cpi = NULL; 469ae115bc7Smrj } 470ae115bc7Smrj 471551bc2a6Smrj #if !defined(__xpv) 472551bc2a6Smrj 473551bc2a6Smrj static void 474b9bfdccdSStuart Maybee determine_platform() 475551bc2a6Smrj { 476551bc2a6Smrj struct cpuid_regs cp; 477551bc2a6Smrj char *xen_str; 4786e5580c9SFrank Van Der Linden uint32_t xen_signature[4], base; 479551bc2a6Smrj 480349b53ddSStuart Maybee platform_type = HW_NATIVE; 481349b53ddSStuart Maybee 482349b53ddSStuart Maybee if (!enable_platform_detection) 483349b53ddSStuart Maybee return; 484349b53ddSStuart Maybee 485551bc2a6Smrj /* 486551bc2a6Smrj * In a fully virtualized domain, Xen's pseudo-cpuid function 4876e5580c9SFrank Van Der Linden * returns a string representing the Xen signature in %ebx, %ecx, 4886e5580c9SFrank Van Der Linden * and %edx. %eax contains the maximum supported cpuid function. 4896e5580c9SFrank Van Der Linden * We need at least a (base + 2) leaf value to do what we want 4906e5580c9SFrank Van Der Linden * to do. Try different base values, since the hypervisor might 4916e5580c9SFrank Van Der Linden * use a different one depending on whether hyper-v emulation 4926e5580c9SFrank Van Der Linden * is switched on by default or not. 493551bc2a6Smrj */ 4946e5580c9SFrank Van Der Linden for (base = 0x40000000; base < 0x40010000; base += 0x100) { 4956e5580c9SFrank Van Der Linden cp.cp_eax = base; 496551bc2a6Smrj (void) __cpuid_insn(&cp); 497551bc2a6Smrj xen_signature[0] = cp.cp_ebx; 498551bc2a6Smrj xen_signature[1] = cp.cp_ecx; 499551bc2a6Smrj xen_signature[2] = cp.cp_edx; 500551bc2a6Smrj xen_signature[3] = 0; 501551bc2a6Smrj xen_str = (char *)xen_signature; 5026e5580c9SFrank Van Der Linden if (strcmp("XenVMMXenVMM", xen_str) == 0 && 5036e5580c9SFrank Van Der Linden cp.cp_eax >= (base + 2)) { 504b9bfdccdSStuart Maybee platform_type = HW_XEN_HVM; 5056e5580c9SFrank Van Der Linden return; 506551bc2a6Smrj } 507b9bfdccdSStuart Maybee } 508b9bfdccdSStuart Maybee 5096e5580c9SFrank Van Der Linden if (vmware_platform()) /* running under vmware hypervisor? */ 5106e5580c9SFrank Van Der Linden platform_type = HW_VMWARE; 5116e5580c9SFrank Van Der Linden } 5126e5580c9SFrank Van Der Linden 513b9bfdccdSStuart Maybee int 514b9bfdccdSStuart Maybee get_hwenv(void) 515b9bfdccdSStuart Maybee { 516349b53ddSStuart Maybee if (platform_type == -1) 517349b53ddSStuart Maybee determine_platform(); 518349b53ddSStuart Maybee 519b9bfdccdSStuart Maybee return (platform_type); 520b9bfdccdSStuart Maybee } 521b9bfdccdSStuart Maybee 522b9bfdccdSStuart Maybee int 523b9bfdccdSStuart Maybee is_controldom(void) 524b9bfdccdSStuart Maybee { 525b9bfdccdSStuart Maybee return (0); 526b9bfdccdSStuart Maybee } 527b9bfdccdSStuart Maybee 528b9bfdccdSStuart Maybee #else 529b9bfdccdSStuart Maybee 530b9bfdccdSStuart Maybee int 531b9bfdccdSStuart Maybee get_hwenv(void) 532b9bfdccdSStuart Maybee { 533b9bfdccdSStuart Maybee return (HW_XEN_PV); 534b9bfdccdSStuart Maybee } 535b9bfdccdSStuart Maybee 536b9bfdccdSStuart Maybee int 537b9bfdccdSStuart Maybee is_controldom(void) 538b9bfdccdSStuart Maybee { 539b9bfdccdSStuart Maybee return (DOMAIN_IS_INITDOMAIN(xen_info)); 540b9bfdccdSStuart Maybee } 541b9bfdccdSStuart Maybee 542551bc2a6Smrj #endif /* __xpv */ 543551bc2a6Smrj 5448031591dSSrihari Venkatesan static void 5458031591dSSrihari Venkatesan cpuid_intel_getids(cpu_t *cpu, uint_t feature) 5468031591dSSrihari Venkatesan { 5478031591dSSrihari Venkatesan uint_t i; 5488031591dSSrihari Venkatesan uint_t chipid_shift = 0; 5498031591dSSrihari Venkatesan uint_t coreid_shift = 0; 5508031591dSSrihari Venkatesan struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 5518031591dSSrihari Venkatesan 5528031591dSSrihari Venkatesan for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 5538031591dSSrihari Venkatesan chipid_shift++; 5548031591dSSrihari Venkatesan 5558031591dSSrihari Venkatesan cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift; 5568031591dSSrihari Venkatesan cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1); 5578031591dSSrihari Venkatesan 5588031591dSSrihari Venkatesan if (feature & X86_CMP) { 5598031591dSSrihari Venkatesan /* 5608031591dSSrihari Venkatesan * Multi-core (and possibly multi-threaded) 5618031591dSSrihari Venkatesan * processors. 5628031591dSSrihari Venkatesan */ 5638031591dSSrihari Venkatesan uint_t ncpu_per_core; 5648031591dSSrihari Venkatesan if (cpi->cpi_ncore_per_chip == 1) 5658031591dSSrihari Venkatesan ncpu_per_core = cpi->cpi_ncpu_per_chip; 5668031591dSSrihari Venkatesan else if (cpi->cpi_ncore_per_chip > 1) 5678031591dSSrihari Venkatesan ncpu_per_core = cpi->cpi_ncpu_per_chip / 5688031591dSSrihari Venkatesan cpi->cpi_ncore_per_chip; 5698031591dSSrihari Venkatesan /* 5708031591dSSrihari Venkatesan * 8bit APIC IDs on dual core Pentiums 5718031591dSSrihari Venkatesan * look like this: 5728031591dSSrihari Venkatesan * 5738031591dSSrihari Venkatesan * +-----------------------+------+------+ 5748031591dSSrihari Venkatesan * | Physical Package ID | MC | HT | 5758031591dSSrihari Venkatesan * +-----------------------+------+------+ 5768031591dSSrihari Venkatesan * <------- chipid --------> 5778031591dSSrihari Venkatesan * <------- coreid ---------------> 5788031591dSSrihari Venkatesan * <--- clogid --> 5798031591dSSrihari Venkatesan * <------> 5808031591dSSrihari Venkatesan * pkgcoreid 5818031591dSSrihari Venkatesan * 5828031591dSSrihari Venkatesan * Where the number of bits necessary to 5838031591dSSrihari Venkatesan * represent MC and HT fields together equals 5848031591dSSrihari Venkatesan * to the minimum number of bits necessary to 5858031591dSSrihari Venkatesan * store the value of cpi->cpi_ncpu_per_chip. 5868031591dSSrihari Venkatesan * Of those bits, the MC part uses the number 5878031591dSSrihari Venkatesan * of bits necessary to store the value of 5888031591dSSrihari Venkatesan * cpi->cpi_ncore_per_chip. 5898031591dSSrihari Venkatesan */ 5908031591dSSrihari Venkatesan for (i = 1; i < ncpu_per_core; i <<= 1) 5918031591dSSrihari Venkatesan coreid_shift++; 5928031591dSSrihari Venkatesan cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift; 5938031591dSSrihari Venkatesan cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 5948031591dSSrihari Venkatesan } else if (feature & X86_HTT) { 5958031591dSSrihari Venkatesan /* 5968031591dSSrihari Venkatesan * Single-core multi-threaded processors. 5978031591dSSrihari Venkatesan */ 5988031591dSSrihari Venkatesan cpi->cpi_coreid = cpi->cpi_chipid; 5998031591dSSrihari Venkatesan cpi->cpi_pkgcoreid = 0; 6008031591dSSrihari Venkatesan } 6018031591dSSrihari Venkatesan cpi->cpi_procnodeid = cpi->cpi_chipid; 6028031591dSSrihari Venkatesan } 6038031591dSSrihari Venkatesan 6048031591dSSrihari Venkatesan static void 6058031591dSSrihari Venkatesan cpuid_amd_getids(cpu_t *cpu) 6068031591dSSrihari Venkatesan { 6071fbe4a4fSSrihari Venkatesan int i, first_half, coreidsz; 6088031591dSSrihari Venkatesan uint32_t nb_caps_reg; 6098031591dSSrihari Venkatesan uint_t node2_1; 6108031591dSSrihari Venkatesan struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 6118031591dSSrihari Venkatesan 6128031591dSSrihari Venkatesan /* 6138031591dSSrihari Venkatesan * AMD CMP chips currently have a single thread per core. 6148031591dSSrihari Venkatesan * 6158031591dSSrihari Venkatesan * Since no two cpus share a core we must assign a distinct coreid 6168031591dSSrihari Venkatesan * per cpu, and we do this by using the cpu_id. This scheme does not, 6178031591dSSrihari Venkatesan * however, guarantee that sibling cores of a chip will have sequential 6188031591dSSrihari Venkatesan * coreids starting at a multiple of the number of cores per chip - 6198031591dSSrihari Venkatesan * that is usually the case, but if the ACPI MADT table is presented 6208031591dSSrihari Venkatesan * in a different order then we need to perform a few more gymnastics 6218031591dSSrihari Venkatesan * for the pkgcoreid. 6228031591dSSrihari Venkatesan * 6238031591dSSrihari Venkatesan * All processors in the system have the same number of enabled 6248031591dSSrihari Venkatesan * cores. Cores within a processor are always numbered sequentially 6258031591dSSrihari Venkatesan * from 0 regardless of how many or which are disabled, and there 6268031591dSSrihari Venkatesan * is no way for operating system to discover the real core id when some 6278031591dSSrihari Venkatesan * are disabled. 6288031591dSSrihari Venkatesan */ 6298031591dSSrihari Venkatesan 6308031591dSSrihari Venkatesan cpi->cpi_coreid = cpu->cpu_id; 6318031591dSSrihari Venkatesan 6328031591dSSrihari Venkatesan if (cpi->cpi_xmaxeax >= 0x80000008) { 6338031591dSSrihari Venkatesan 6348031591dSSrihari Venkatesan coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 6358031591dSSrihari Venkatesan 6368031591dSSrihari Venkatesan /* 6378031591dSSrihari Venkatesan * In AMD parlance chip is really a node while Solaris 6388031591dSSrihari Venkatesan * sees chip as equivalent to socket/package. 6398031591dSSrihari Venkatesan */ 6408031591dSSrihari Venkatesan cpi->cpi_ncore_per_chip = 6418031591dSSrihari Venkatesan BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 6421fbe4a4fSSrihari Venkatesan if (coreidsz == 0) { 6438031591dSSrihari Venkatesan /* Use legacy method */ 6441fbe4a4fSSrihari Venkatesan for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1) 6451fbe4a4fSSrihari Venkatesan coreidsz++; 6461fbe4a4fSSrihari Venkatesan if (coreidsz == 0) 6471fbe4a4fSSrihari Venkatesan coreidsz = 1; 6481fbe4a4fSSrihari Venkatesan } 6498031591dSSrihari Venkatesan } else { 6508031591dSSrihari Venkatesan /* Assume single-core part */ 6511fbe4a4fSSrihari Venkatesan cpi->cpi_ncore_per_chip = 1; 6528031591dSSrihari Venkatesan } 6538031591dSSrihari Venkatesan 6541fbe4a4fSSrihari Venkatesan cpi->cpi_clogid = cpi->cpi_pkgcoreid = 6551fbe4a4fSSrihari Venkatesan cpi->cpi_apicid & ((1<<coreidsz) - 1); 6568031591dSSrihari Venkatesan cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip; 6578031591dSSrihari Venkatesan 6588031591dSSrihari Venkatesan /* Get nodeID */ 6598031591dSSrihari Venkatesan if (cpi->cpi_family == 0xf) { 6601fbe4a4fSSrihari Venkatesan cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7; 6618031591dSSrihari Venkatesan cpi->cpi_chipid = cpi->cpi_procnodeid; 6628031591dSSrihari Venkatesan } else if (cpi->cpi_family == 0x10) { 6638031591dSSrihari Venkatesan /* 6648031591dSSrihari Venkatesan * See if we are a multi-node processor. 6658031591dSSrihari Venkatesan * All processors in the system have the same number of nodes 6668031591dSSrihari Venkatesan */ 6678031591dSSrihari Venkatesan nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8); 6688031591dSSrihari Venkatesan if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) { 6698031591dSSrihari Venkatesan /* Single-node */ 6701fbe4a4fSSrihari Venkatesan cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5, 6711fbe4a4fSSrihari Venkatesan coreidsz); 6728031591dSSrihari Venkatesan cpi->cpi_chipid = cpi->cpi_procnodeid; 6738031591dSSrihari Venkatesan } else { 6748031591dSSrihari Venkatesan 6758031591dSSrihari Venkatesan /* 6768031591dSSrihari Venkatesan * Multi-node revision D (2 nodes per package 6778031591dSSrihari Venkatesan * are supported) 6788031591dSSrihari Venkatesan */ 6798031591dSSrihari Venkatesan cpi->cpi_procnodes_per_pkg = 2; 6808031591dSSrihari Venkatesan 6818031591dSSrihari Venkatesan first_half = (cpi->cpi_pkgcoreid <= 6828031591dSSrihari Venkatesan (cpi->cpi_ncore_per_chip/2 - 1)); 6838031591dSSrihari Venkatesan 6848031591dSSrihari Venkatesan if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) { 6858031591dSSrihari Venkatesan /* We are BSP */ 6868031591dSSrihari Venkatesan cpi->cpi_procnodeid = (first_half ? 0 : 1); 6878031591dSSrihari Venkatesan cpi->cpi_chipid = cpi->cpi_procnodeid >> 1; 6888031591dSSrihari Venkatesan } else { 6898031591dSSrihari Venkatesan 6908031591dSSrihari Venkatesan /* We are AP */ 6918031591dSSrihari Venkatesan /* NodeId[2:1] bits to use for reading F3xe8 */ 6928031591dSSrihari Venkatesan node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1; 6938031591dSSrihari Venkatesan 6948031591dSSrihari Venkatesan nb_caps_reg = 6958031591dSSrihari Venkatesan pci_getl_func(0, 24 + node2_1, 3, 0xe8); 6968031591dSSrihari Venkatesan 6978031591dSSrihari Venkatesan /* 6988031591dSSrihari Venkatesan * Check IntNodeNum bit (31:30, but bit 31 is 6998031591dSSrihari Venkatesan * always 0 on dual-node processors) 7008031591dSSrihari Venkatesan */ 7018031591dSSrihari Venkatesan if (BITX(nb_caps_reg, 30, 30) == 0) 7028031591dSSrihari Venkatesan cpi->cpi_procnodeid = node2_1 + 7038031591dSSrihari Venkatesan !first_half; 7048031591dSSrihari Venkatesan else 7058031591dSSrihari Venkatesan cpi->cpi_procnodeid = node2_1 + 7068031591dSSrihari Venkatesan first_half; 7078031591dSSrihari Venkatesan 7088031591dSSrihari Venkatesan cpi->cpi_chipid = cpi->cpi_procnodeid >> 1; 7098031591dSSrihari Venkatesan } 7108031591dSSrihari Venkatesan } 7118031591dSSrihari Venkatesan } else if (cpi->cpi_family >= 0x11) { 7128031591dSSrihari Venkatesan cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7; 7138031591dSSrihari Venkatesan cpi->cpi_chipid = cpi->cpi_procnodeid; 7148031591dSSrihari Venkatesan } else { 7158031591dSSrihari Venkatesan cpi->cpi_procnodeid = 0; 7168031591dSSrihari Venkatesan cpi->cpi_chipid = cpi->cpi_procnodeid; 7178031591dSSrihari Venkatesan } 7188031591dSSrihari Venkatesan } 7198031591dSSrihari Venkatesan 7207c478bd9Sstevel@tonic-gate uint_t 7217c478bd9Sstevel@tonic-gate cpuid_pass1(cpu_t *cpu) 7227c478bd9Sstevel@tonic-gate { 7237c478bd9Sstevel@tonic-gate uint32_t mask_ecx, mask_edx; 7247c478bd9Sstevel@tonic-gate uint_t feature = X86_CPUID; 7257c478bd9Sstevel@tonic-gate struct cpuid_info *cpi; 7268949bcd6Sandrei struct cpuid_regs *cp; 7277c478bd9Sstevel@tonic-gate int xcpuid; 728843e1988Sjohnlev #if !defined(__xpv) 7295b8a6efeSbholler extern int idle_cpu_prefer_mwait; 730843e1988Sjohnlev #endif 731ae115bc7Smrj 73289e921d5SKuriakose Kuruvilla 73389e921d5SKuriakose Kuruvilla #if !defined(__xpv) 73489e921d5SKuriakose Kuruvilla determine_platform(); 73589e921d5SKuriakose Kuruvilla #endif 7367c478bd9Sstevel@tonic-gate /* 737a3114836SGerry Liu * Space statically allocated for BSP, ensure pointer is set 7387c478bd9Sstevel@tonic-gate */ 739a3114836SGerry Liu if (cpu->cpu_id == 0 && cpu->cpu_m.mcpu_cpi == NULL) 740ae115bc7Smrj cpu->cpu_m.mcpu_cpi = &cpuid_info0; 741ae115bc7Smrj cpi = cpu->cpu_m.mcpu_cpi; 742ae115bc7Smrj ASSERT(cpi != NULL); 7437c478bd9Sstevel@tonic-gate cp = &cpi->cpi_std[0]; 7448949bcd6Sandrei cp->cp_eax = 0; 7458949bcd6Sandrei cpi->cpi_maxeax = __cpuid_insn(cp); 7467c478bd9Sstevel@tonic-gate { 7477c478bd9Sstevel@tonic-gate uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 7487c478bd9Sstevel@tonic-gate *iptr++ = cp->cp_ebx; 7497c478bd9Sstevel@tonic-gate *iptr++ = cp->cp_edx; 7507c478bd9Sstevel@tonic-gate *iptr++ = cp->cp_ecx; 7517c478bd9Sstevel@tonic-gate *(char *)&cpi->cpi_vendorstr[12] = '\0'; 7527c478bd9Sstevel@tonic-gate } 7537c478bd9Sstevel@tonic-gate 754e4b86885SCheng Sean Ye cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 7557c478bd9Sstevel@tonic-gate x86_vendor = cpi->cpi_vendor; /* for compatibility */ 7567c478bd9Sstevel@tonic-gate 7577c478bd9Sstevel@tonic-gate /* 7587c478bd9Sstevel@tonic-gate * Limit the range in case of weird hardware 7597c478bd9Sstevel@tonic-gate */ 7607c478bd9Sstevel@tonic-gate if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 7617c478bd9Sstevel@tonic-gate cpi->cpi_maxeax = CPI_MAXEAX_MAX; 7627c478bd9Sstevel@tonic-gate if (cpi->cpi_maxeax < 1) 7637c478bd9Sstevel@tonic-gate goto pass1_done; 7647c478bd9Sstevel@tonic-gate 7657c478bd9Sstevel@tonic-gate cp = &cpi->cpi_std[1]; 7668949bcd6Sandrei cp->cp_eax = 1; 7678949bcd6Sandrei (void) __cpuid_insn(cp); 7687c478bd9Sstevel@tonic-gate 7697c478bd9Sstevel@tonic-gate /* 7707c478bd9Sstevel@tonic-gate * Extract identifying constants for easy access. 7717c478bd9Sstevel@tonic-gate */ 7727c478bd9Sstevel@tonic-gate cpi->cpi_model = CPI_MODEL(cpi); 7737c478bd9Sstevel@tonic-gate cpi->cpi_family = CPI_FAMILY(cpi); 7747c478bd9Sstevel@tonic-gate 7755ff02082Sdmick if (cpi->cpi_family == 0xf) 7767c478bd9Sstevel@tonic-gate cpi->cpi_family += CPI_FAMILY_XTD(cpi); 7775ff02082Sdmick 77868c91426Sdmick /* 779875b116eSkchow * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 78068c91426Sdmick * Intel, and presumably everyone else, uses model == 0xf, as 78168c91426Sdmick * one would expect (max value means possible overflow). Sigh. 78268c91426Sdmick */ 78368c91426Sdmick 78468c91426Sdmick switch (cpi->cpi_vendor) { 785bf91205bSksadhukh case X86_VENDOR_Intel: 786bf91205bSksadhukh if (IS_EXTENDED_MODEL_INTEL(cpi)) 787bf91205bSksadhukh cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 788447af253Sksadhukh break; 78968c91426Sdmick case X86_VENDOR_AMD: 790875b116eSkchow if (CPI_FAMILY(cpi) == 0xf) 79168c91426Sdmick cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 79268c91426Sdmick break; 79368c91426Sdmick default: 7945ff02082Sdmick if (cpi->cpi_model == 0xf) 7957c478bd9Sstevel@tonic-gate cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 79668c91426Sdmick break; 79768c91426Sdmick } 7987c478bd9Sstevel@tonic-gate 7997c478bd9Sstevel@tonic-gate cpi->cpi_step = CPI_STEP(cpi); 8007c478bd9Sstevel@tonic-gate cpi->cpi_brandid = CPI_BRANDID(cpi); 8017c478bd9Sstevel@tonic-gate 8027c478bd9Sstevel@tonic-gate /* 8037c478bd9Sstevel@tonic-gate * *default* assumptions: 8047c478bd9Sstevel@tonic-gate * - believe %edx feature word 8057c478bd9Sstevel@tonic-gate * - ignore %ecx feature word 8067c478bd9Sstevel@tonic-gate * - 32-bit virtual and physical addressing 8077c478bd9Sstevel@tonic-gate */ 8087c478bd9Sstevel@tonic-gate mask_edx = 0xffffffff; 8097c478bd9Sstevel@tonic-gate mask_ecx = 0; 8107c478bd9Sstevel@tonic-gate 8117c478bd9Sstevel@tonic-gate cpi->cpi_pabits = cpi->cpi_vabits = 32; 8127c478bd9Sstevel@tonic-gate 8137c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 8147c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 8157c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 5) 8167c478bd9Sstevel@tonic-gate x86_type = X86_TYPE_P5; 8175ff02082Sdmick else if (IS_LEGACY_P6(cpi)) { 8187c478bd9Sstevel@tonic-gate x86_type = X86_TYPE_P6; 8197c478bd9Sstevel@tonic-gate pentiumpro_bug4046376 = 1; 8207c478bd9Sstevel@tonic-gate pentiumpro_bug4064495 = 1; 8217c478bd9Sstevel@tonic-gate /* 8227c478bd9Sstevel@tonic-gate * Clear the SEP bit when it was set erroneously 8237c478bd9Sstevel@tonic-gate */ 8247c478bd9Sstevel@tonic-gate if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 8257c478bd9Sstevel@tonic-gate cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 8265ff02082Sdmick } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 8277c478bd9Sstevel@tonic-gate x86_type = X86_TYPE_P4; 8287c478bd9Sstevel@tonic-gate /* 8297c478bd9Sstevel@tonic-gate * We don't currently depend on any of the %ecx 8307c478bd9Sstevel@tonic-gate * features until Prescott, so we'll only check 8317c478bd9Sstevel@tonic-gate * this from P4 onwards. We might want to revisit 8327c478bd9Sstevel@tonic-gate * that idea later. 8337c478bd9Sstevel@tonic-gate */ 8347c478bd9Sstevel@tonic-gate mask_ecx = 0xffffffff; 8357c478bd9Sstevel@tonic-gate } else if (cpi->cpi_family > 0xf) 8367c478bd9Sstevel@tonic-gate mask_ecx = 0xffffffff; 8377c622d23Sbholler /* 8387c622d23Sbholler * We don't support MONITOR/MWAIT if leaf 5 is not available 8397c622d23Sbholler * to obtain the monitor linesize. 8407c622d23Sbholler */ 8417c622d23Sbholler if (cpi->cpi_maxeax < 5) 8427c622d23Sbholler mask_ecx &= ~CPUID_INTC_ECX_MON; 8437c478bd9Sstevel@tonic-gate break; 8447c478bd9Sstevel@tonic-gate case X86_VENDOR_IntelClone: 8457c478bd9Sstevel@tonic-gate default: 8467c478bd9Sstevel@tonic-gate break; 8477c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 8487c478bd9Sstevel@tonic-gate #if defined(OPTERON_ERRATUM_108) 8497c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 8507c478bd9Sstevel@tonic-gate cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 8517c478bd9Sstevel@tonic-gate cpi->cpi_model = 0xc; 8527c478bd9Sstevel@tonic-gate } else 8537c478bd9Sstevel@tonic-gate #endif 8547c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 5) { 8557c478bd9Sstevel@tonic-gate /* 8567c478bd9Sstevel@tonic-gate * AMD K5 and K6 8577c478bd9Sstevel@tonic-gate * 8587c478bd9Sstevel@tonic-gate * These CPUs have an incomplete implementation 8597c478bd9Sstevel@tonic-gate * of MCA/MCE which we mask away. 8607c478bd9Sstevel@tonic-gate */ 8618949bcd6Sandrei mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 8628949bcd6Sandrei 8637c478bd9Sstevel@tonic-gate /* 8647c478bd9Sstevel@tonic-gate * Model 0 uses the wrong (APIC) bit 8657c478bd9Sstevel@tonic-gate * to indicate PGE. Fix it here. 8667c478bd9Sstevel@tonic-gate */ 8678949bcd6Sandrei if (cpi->cpi_model == 0) { 8687c478bd9Sstevel@tonic-gate if (cp->cp_edx & 0x200) { 8697c478bd9Sstevel@tonic-gate cp->cp_edx &= ~0x200; 8707c478bd9Sstevel@tonic-gate cp->cp_edx |= CPUID_INTC_EDX_PGE; 8717c478bd9Sstevel@tonic-gate } 8727c478bd9Sstevel@tonic-gate } 8738949bcd6Sandrei 8748949bcd6Sandrei /* 8758949bcd6Sandrei * Early models had problems w/ MMX; disable. 8768949bcd6Sandrei */ 8778949bcd6Sandrei if (cpi->cpi_model < 6) 8788949bcd6Sandrei mask_edx &= ~CPUID_INTC_EDX_MMX; 8798949bcd6Sandrei } 8808949bcd6Sandrei 8818949bcd6Sandrei /* 8828949bcd6Sandrei * For newer families, SSE3 and CX16, at least, are valid; 8838949bcd6Sandrei * enable all 8848949bcd6Sandrei */ 8858949bcd6Sandrei if (cpi->cpi_family >= 0xf) 8868949bcd6Sandrei mask_ecx = 0xffffffff; 8877c622d23Sbholler /* 8887c622d23Sbholler * We don't support MONITOR/MWAIT if leaf 5 is not available 8897c622d23Sbholler * to obtain the monitor linesize. 8907c622d23Sbholler */ 8917c622d23Sbholler if (cpi->cpi_maxeax < 5) 8927c622d23Sbholler mask_ecx &= ~CPUID_INTC_ECX_MON; 8935b8a6efeSbholler 894843e1988Sjohnlev #if !defined(__xpv) 8955b8a6efeSbholler /* 8965b8a6efeSbholler * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 8975b8a6efeSbholler * processors. AMD does not intend MWAIT to be used in the cpu 8985b8a6efeSbholler * idle loop on current and future processors. 10h and future 8995b8a6efeSbholler * AMD processors use more power in MWAIT than HLT. 9005b8a6efeSbholler * Pre-family-10h Opterons do not have the MWAIT instruction. 9015b8a6efeSbholler */ 9025b8a6efeSbholler idle_cpu_prefer_mwait = 0; 903843e1988Sjohnlev #endif 9045b8a6efeSbholler 9057c478bd9Sstevel@tonic-gate break; 9067c478bd9Sstevel@tonic-gate case X86_VENDOR_TM: 9077c478bd9Sstevel@tonic-gate /* 9087c478bd9Sstevel@tonic-gate * workaround the NT workaround in CMS 4.1 9097c478bd9Sstevel@tonic-gate */ 9107c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 9117c478bd9Sstevel@tonic-gate (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 9127c478bd9Sstevel@tonic-gate cp->cp_edx |= CPUID_INTC_EDX_CX8; 9137c478bd9Sstevel@tonic-gate break; 9147c478bd9Sstevel@tonic-gate case X86_VENDOR_Centaur: 9157c478bd9Sstevel@tonic-gate /* 9167c478bd9Sstevel@tonic-gate * workaround the NT workarounds again 9177c478bd9Sstevel@tonic-gate */ 9187c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 6) 9197c478bd9Sstevel@tonic-gate cp->cp_edx |= CPUID_INTC_EDX_CX8; 9207c478bd9Sstevel@tonic-gate break; 9217c478bd9Sstevel@tonic-gate case X86_VENDOR_Cyrix: 9227c478bd9Sstevel@tonic-gate /* 9237c478bd9Sstevel@tonic-gate * We rely heavily on the probing in locore 9247c478bd9Sstevel@tonic-gate * to actually figure out what parts, if any, 9257c478bd9Sstevel@tonic-gate * of the Cyrix cpuid instruction to believe. 9267c478bd9Sstevel@tonic-gate */ 9277c478bd9Sstevel@tonic-gate switch (x86_type) { 9287c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_486: 9297c478bd9Sstevel@tonic-gate mask_edx = 0; 9307c478bd9Sstevel@tonic-gate break; 9317c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_6x86: 9327c478bd9Sstevel@tonic-gate mask_edx = 0; 9337c478bd9Sstevel@tonic-gate break; 9347c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_6x86L: 9357c478bd9Sstevel@tonic-gate mask_edx = 9367c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_DE | 9377c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_CX8; 9387c478bd9Sstevel@tonic-gate break; 9397c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_6x86MX: 9407c478bd9Sstevel@tonic-gate mask_edx = 9417c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_DE | 9427c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_MSR | 9437c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_CX8 | 9447c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_PGE | 9457c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_CMOV | 9467c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_MMX; 9477c478bd9Sstevel@tonic-gate break; 9487c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_GXm: 9497c478bd9Sstevel@tonic-gate mask_edx = 9507c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_MSR | 9517c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_CX8 | 9527c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_CMOV | 9537c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_MMX; 9547c478bd9Sstevel@tonic-gate break; 9557c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_MediaGX: 9567c478bd9Sstevel@tonic-gate break; 9577c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_MII: 9587c478bd9Sstevel@tonic-gate case X86_TYPE_VIA_CYRIX_III: 9597c478bd9Sstevel@tonic-gate mask_edx = 9607c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_DE | 9617c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_TSC | 9627c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_MSR | 9637c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_CX8 | 9647c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_PGE | 9657c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_CMOV | 9667c478bd9Sstevel@tonic-gate CPUID_INTC_EDX_MMX; 9677c478bd9Sstevel@tonic-gate break; 9687c478bd9Sstevel@tonic-gate default: 9697c478bd9Sstevel@tonic-gate break; 9707c478bd9Sstevel@tonic-gate } 9717c478bd9Sstevel@tonic-gate break; 9727c478bd9Sstevel@tonic-gate } 9737c478bd9Sstevel@tonic-gate 974843e1988Sjohnlev #if defined(__xpv) 975843e1988Sjohnlev /* 976843e1988Sjohnlev * Do not support MONITOR/MWAIT under a hypervisor 977843e1988Sjohnlev */ 978843e1988Sjohnlev mask_ecx &= ~CPUID_INTC_ECX_MON; 979843e1988Sjohnlev #endif /* __xpv */ 980843e1988Sjohnlev 9817c478bd9Sstevel@tonic-gate /* 9827c478bd9Sstevel@tonic-gate * Now we've figured out the masks that determine 9837c478bd9Sstevel@tonic-gate * which bits we choose to believe, apply the masks 9847c478bd9Sstevel@tonic-gate * to the feature words, then map the kernel's view 9857c478bd9Sstevel@tonic-gate * of these feature words into its feature word. 9867c478bd9Sstevel@tonic-gate */ 9877c478bd9Sstevel@tonic-gate cp->cp_edx &= mask_edx; 9887c478bd9Sstevel@tonic-gate cp->cp_ecx &= mask_ecx; 9897c478bd9Sstevel@tonic-gate 9907c478bd9Sstevel@tonic-gate /* 991ae115bc7Smrj * apply any platform restrictions (we don't call this 992ae115bc7Smrj * immediately after __cpuid_insn here, because we need the 993ae115bc7Smrj * workarounds applied above first) 9947c478bd9Sstevel@tonic-gate */ 995ae115bc7Smrj platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 9967c478bd9Sstevel@tonic-gate 997ae115bc7Smrj /* 998ae115bc7Smrj * fold in overrides from the "eeprom" mechanism 999ae115bc7Smrj */ 10007c478bd9Sstevel@tonic-gate cp->cp_edx |= cpuid_feature_edx_include; 10017c478bd9Sstevel@tonic-gate cp->cp_edx &= ~cpuid_feature_edx_exclude; 10027c478bd9Sstevel@tonic-gate 10037c478bd9Sstevel@tonic-gate cp->cp_ecx |= cpuid_feature_ecx_include; 10047c478bd9Sstevel@tonic-gate cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 10057c478bd9Sstevel@tonic-gate 10067c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_PSE) 10077c478bd9Sstevel@tonic-gate feature |= X86_LARGEPAGE; 10087c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_TSC) 10097c478bd9Sstevel@tonic-gate feature |= X86_TSC; 10107c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_MSR) 10117c478bd9Sstevel@tonic-gate feature |= X86_MSR; 10127c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 10137c478bd9Sstevel@tonic-gate feature |= X86_MTRR; 10147c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_PGE) 10157c478bd9Sstevel@tonic-gate feature |= X86_PGE; 10167c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 10177c478bd9Sstevel@tonic-gate feature |= X86_CMOV; 10187c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_MMX) 10197c478bd9Sstevel@tonic-gate feature |= X86_MMX; 10207c478bd9Sstevel@tonic-gate if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 10217c478bd9Sstevel@tonic-gate (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 10227c478bd9Sstevel@tonic-gate feature |= X86_MCA; 10237c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_PAE) 10247c478bd9Sstevel@tonic-gate feature |= X86_PAE; 10257c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_CX8) 10267c478bd9Sstevel@tonic-gate feature |= X86_CX8; 10277c478bd9Sstevel@tonic-gate if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 10287c478bd9Sstevel@tonic-gate feature |= X86_CX16; 10297c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_PAT) 10307c478bd9Sstevel@tonic-gate feature |= X86_PAT; 10317c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_SEP) 10327c478bd9Sstevel@tonic-gate feature |= X86_SEP; 10337c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 10347c478bd9Sstevel@tonic-gate /* 10357c478bd9Sstevel@tonic-gate * In our implementation, fxsave/fxrstor 10367c478bd9Sstevel@tonic-gate * are prerequisites before we'll even 10377c478bd9Sstevel@tonic-gate * try and do SSE things. 10387c478bd9Sstevel@tonic-gate */ 10397c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_SSE) 10407c478bd9Sstevel@tonic-gate feature |= X86_SSE; 10417c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 10427c478bd9Sstevel@tonic-gate feature |= X86_SSE2; 10437c478bd9Sstevel@tonic-gate if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 10447c478bd9Sstevel@tonic-gate feature |= X86_SSE3; 1045d0f8ff6eSkk208521 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1046d0f8ff6eSkk208521 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 1047d0f8ff6eSkk208521 feature |= X86_SSSE3; 1048d0f8ff6eSkk208521 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 1049d0f8ff6eSkk208521 feature |= X86_SSE4_1; 1050d0f8ff6eSkk208521 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 1051d0f8ff6eSkk208521 feature |= X86_SSE4_2; 1052a50a8b93SKuriakose Kuruvilla if (cp->cp_ecx & CPUID_INTC_ECX_AES) 1053a50a8b93SKuriakose Kuruvilla feature |= X86_AES; 1054d0f8ff6eSkk208521 } 10557c478bd9Sstevel@tonic-gate } 10567c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_DE) 1057ae115bc7Smrj feature |= X86_DE; 10581d1a3942SBill Holler #if !defined(__xpv) 1059f98fbcecSbholler if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 10601d1a3942SBill Holler 10611d1a3942SBill Holler /* 10621d1a3942SBill Holler * We require the CLFLUSH instruction for erratum workaround 10631d1a3942SBill Holler * to use MONITOR/MWAIT. 10641d1a3942SBill Holler */ 10651d1a3942SBill Holler if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 1066f98fbcecSbholler cpi->cpi_mwait.support |= MWAIT_SUPPORT; 1067f98fbcecSbholler feature |= X86_MWAIT; 10681d1a3942SBill Holler } else { 10691d1a3942SBill Holler extern int idle_cpu_assert_cflush_monitor; 10701d1a3942SBill Holler 10711d1a3942SBill Holler /* 10721d1a3942SBill Holler * All processors we are aware of which have 10731d1a3942SBill Holler * MONITOR/MWAIT also have CLFLUSH. 10741d1a3942SBill Holler */ 10751d1a3942SBill Holler if (idle_cpu_assert_cflush_monitor) { 10761d1a3942SBill Holler ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && 10771d1a3942SBill Holler (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); 1078f98fbcecSbholler } 10791d1a3942SBill Holler } 10801d1a3942SBill Holler } 10811d1a3942SBill Holler #endif /* __xpv */ 10827c478bd9Sstevel@tonic-gate 108386c1f4dcSVikram Hegde /* 108486c1f4dcSVikram Hegde * Only need it first time, rest of the cpus would follow suite. 108586c1f4dcSVikram Hegde * we only capture this for the bootcpu. 108686c1f4dcSVikram Hegde */ 108786c1f4dcSVikram Hegde if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 108886c1f4dcSVikram Hegde feature |= X86_CLFSH; 108986c1f4dcSVikram Hegde x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 109086c1f4dcSVikram Hegde } 109186c1f4dcSVikram Hegde 10927c478bd9Sstevel@tonic-gate if (feature & X86_PAE) 10937c478bd9Sstevel@tonic-gate cpi->cpi_pabits = 36; 10947c478bd9Sstevel@tonic-gate 10957c478bd9Sstevel@tonic-gate /* 10967c478bd9Sstevel@tonic-gate * Hyperthreading configuration is slightly tricky on Intel 10977c478bd9Sstevel@tonic-gate * and pure clones, and even trickier on AMD. 10987c478bd9Sstevel@tonic-gate * 10997c478bd9Sstevel@tonic-gate * (AMD chose to set the HTT bit on their CMP processors, 11007c478bd9Sstevel@tonic-gate * even though they're not actually hyperthreaded. Thus it 11017c478bd9Sstevel@tonic-gate * takes a bit more work to figure out what's really going 1102ae115bc7Smrj * on ... see the handling of the CMP_LGCY bit below) 11037c478bd9Sstevel@tonic-gate */ 11047c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 11057c478bd9Sstevel@tonic-gate cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 11067c478bd9Sstevel@tonic-gate if (cpi->cpi_ncpu_per_chip > 1) 11077c478bd9Sstevel@tonic-gate feature |= X86_HTT; 11088949bcd6Sandrei } else { 11098949bcd6Sandrei cpi->cpi_ncpu_per_chip = 1; 11107c478bd9Sstevel@tonic-gate } 11117c478bd9Sstevel@tonic-gate 11127c478bd9Sstevel@tonic-gate /* 11137c478bd9Sstevel@tonic-gate * Work on the "extended" feature information, doing 11147c478bd9Sstevel@tonic-gate * some basic initialization for cpuid_pass2() 11157c478bd9Sstevel@tonic-gate */ 11167c478bd9Sstevel@tonic-gate xcpuid = 0; 11177c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 11187c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 11195ff02082Sdmick if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 11207c478bd9Sstevel@tonic-gate xcpuid++; 11217c478bd9Sstevel@tonic-gate break; 11227c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 11237c478bd9Sstevel@tonic-gate if (cpi->cpi_family > 5 || 11247c478bd9Sstevel@tonic-gate (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 11257c478bd9Sstevel@tonic-gate xcpuid++; 11267c478bd9Sstevel@tonic-gate break; 11277c478bd9Sstevel@tonic-gate case X86_VENDOR_Cyrix: 11287c478bd9Sstevel@tonic-gate /* 11297c478bd9Sstevel@tonic-gate * Only these Cyrix CPUs are -known- to support 11307c478bd9Sstevel@tonic-gate * extended cpuid operations. 11317c478bd9Sstevel@tonic-gate */ 11327c478bd9Sstevel@tonic-gate if (x86_type == X86_TYPE_VIA_CYRIX_III || 11337c478bd9Sstevel@tonic-gate x86_type == X86_TYPE_CYRIX_GXm) 11347c478bd9Sstevel@tonic-gate xcpuid++; 11357c478bd9Sstevel@tonic-gate break; 11367c478bd9Sstevel@tonic-gate case X86_VENDOR_Centaur: 11377c478bd9Sstevel@tonic-gate case X86_VENDOR_TM: 11387c478bd9Sstevel@tonic-gate default: 11397c478bd9Sstevel@tonic-gate xcpuid++; 11407c478bd9Sstevel@tonic-gate break; 11417c478bd9Sstevel@tonic-gate } 11427c478bd9Sstevel@tonic-gate 11437c478bd9Sstevel@tonic-gate if (xcpuid) { 11447c478bd9Sstevel@tonic-gate cp = &cpi->cpi_extd[0]; 11458949bcd6Sandrei cp->cp_eax = 0x80000000; 11468949bcd6Sandrei cpi->cpi_xmaxeax = __cpuid_insn(cp); 11477c478bd9Sstevel@tonic-gate } 11487c478bd9Sstevel@tonic-gate 11497c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax & 0x80000000) { 11507c478bd9Sstevel@tonic-gate 11517c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 11527c478bd9Sstevel@tonic-gate cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 11537c478bd9Sstevel@tonic-gate 11547c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 11557c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 11567c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 11577c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax < 0x80000001) 11587c478bd9Sstevel@tonic-gate break; 11597c478bd9Sstevel@tonic-gate cp = &cpi->cpi_extd[1]; 11608949bcd6Sandrei cp->cp_eax = 0x80000001; 11618949bcd6Sandrei (void) __cpuid_insn(cp); 1162ae115bc7Smrj 11637c478bd9Sstevel@tonic-gate if (cpi->cpi_vendor == X86_VENDOR_AMD && 11647c478bd9Sstevel@tonic-gate cpi->cpi_family == 5 && 11657c478bd9Sstevel@tonic-gate cpi->cpi_model == 6 && 11667c478bd9Sstevel@tonic-gate cpi->cpi_step == 6) { 11677c478bd9Sstevel@tonic-gate /* 11687c478bd9Sstevel@tonic-gate * K6 model 6 uses bit 10 to indicate SYSC 11697c478bd9Sstevel@tonic-gate * Later models use bit 11. Fix it here. 11707c478bd9Sstevel@tonic-gate */ 11717c478bd9Sstevel@tonic-gate if (cp->cp_edx & 0x400) { 11727c478bd9Sstevel@tonic-gate cp->cp_edx &= ~0x400; 11737c478bd9Sstevel@tonic-gate cp->cp_edx |= CPUID_AMD_EDX_SYSC; 11747c478bd9Sstevel@tonic-gate } 11757c478bd9Sstevel@tonic-gate } 11767c478bd9Sstevel@tonic-gate 1177ae115bc7Smrj platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 1178ae115bc7Smrj 11797c478bd9Sstevel@tonic-gate /* 11807c478bd9Sstevel@tonic-gate * Compute the additions to the kernel's feature word. 11817c478bd9Sstevel@tonic-gate */ 11827c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_AMD_EDX_NX) 11837c478bd9Sstevel@tonic-gate feature |= X86_NX; 11847c478bd9Sstevel@tonic-gate 118519397407SSherry Moore /* 118619397407SSherry Moore * Regardless whether or not we boot 64-bit, 118719397407SSherry Moore * we should have a way to identify whether 118819397407SSherry Moore * the CPU is capable of running 64-bit. 118919397407SSherry Moore */ 119019397407SSherry Moore if (cp->cp_edx & CPUID_AMD_EDX_LM) 119119397407SSherry Moore feature |= X86_64; 119219397407SSherry Moore 119302bc52beSkchow #if defined(__amd64) 119402bc52beSkchow /* 1 GB large page - enable only for 64 bit kernel */ 119502bc52beSkchow if (cp->cp_edx & CPUID_AMD_EDX_1GPG) 119602bc52beSkchow feature |= X86_1GPG; 119702bc52beSkchow #endif 119802bc52beSkchow 1199f8801251Skk208521 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 1200f8801251Skk208521 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 1201f8801251Skk208521 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 1202f8801251Skk208521 feature |= X86_SSE4A; 1203f8801251Skk208521 12047c478bd9Sstevel@tonic-gate /* 1205ae115bc7Smrj * If both the HTT and CMP_LGCY bits are set, 12068949bcd6Sandrei * then we're not actually HyperThreaded. Read 12078949bcd6Sandrei * "AMD CPUID Specification" for more details. 12087c478bd9Sstevel@tonic-gate */ 12097c478bd9Sstevel@tonic-gate if (cpi->cpi_vendor == X86_VENDOR_AMD && 12108949bcd6Sandrei (feature & X86_HTT) && 1211ae115bc7Smrj (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 12127c478bd9Sstevel@tonic-gate feature &= ~X86_HTT; 12138949bcd6Sandrei feature |= X86_CMP; 12148949bcd6Sandrei } 1215ae115bc7Smrj #if defined(__amd64) 12167c478bd9Sstevel@tonic-gate /* 12177c478bd9Sstevel@tonic-gate * It's really tricky to support syscall/sysret in 12187c478bd9Sstevel@tonic-gate * the i386 kernel; we rely on sysenter/sysexit 12197c478bd9Sstevel@tonic-gate * instead. In the amd64 kernel, things are -way- 12207c478bd9Sstevel@tonic-gate * better. 12217c478bd9Sstevel@tonic-gate */ 12227c478bd9Sstevel@tonic-gate if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 12237c478bd9Sstevel@tonic-gate feature |= X86_ASYSC; 12247c478bd9Sstevel@tonic-gate 12257c478bd9Sstevel@tonic-gate /* 12267c478bd9Sstevel@tonic-gate * While we're thinking about system calls, note 12277c478bd9Sstevel@tonic-gate * that AMD processors don't support sysenter 12287c478bd9Sstevel@tonic-gate * in long mode at all, so don't try to program them. 12297c478bd9Sstevel@tonic-gate */ 12307c478bd9Sstevel@tonic-gate if (x86_vendor == X86_VENDOR_AMD) 12317c478bd9Sstevel@tonic-gate feature &= ~X86_SEP; 12327c478bd9Sstevel@tonic-gate #endif 1233d36ea5d8Ssudheer if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 1234ae115bc7Smrj feature |= X86_TSCP; 12357c478bd9Sstevel@tonic-gate break; 12367c478bd9Sstevel@tonic-gate default: 12377c478bd9Sstevel@tonic-gate break; 12387c478bd9Sstevel@tonic-gate } 12397c478bd9Sstevel@tonic-gate 12408949bcd6Sandrei /* 12418949bcd6Sandrei * Get CPUID data about processor cores and hyperthreads. 12428949bcd6Sandrei */ 12437c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 12447c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 12458949bcd6Sandrei if (cpi->cpi_maxeax >= 4) { 12468949bcd6Sandrei cp = &cpi->cpi_std[4]; 12478949bcd6Sandrei cp->cp_eax = 4; 12488949bcd6Sandrei cp->cp_ecx = 0; 12498949bcd6Sandrei (void) __cpuid_insn(cp); 1250ae115bc7Smrj platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 12518949bcd6Sandrei } 12528949bcd6Sandrei /*FALLTHROUGH*/ 12537c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 12547c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax < 0x80000008) 12557c478bd9Sstevel@tonic-gate break; 12567c478bd9Sstevel@tonic-gate cp = &cpi->cpi_extd[8]; 12578949bcd6Sandrei cp->cp_eax = 0x80000008; 12588949bcd6Sandrei (void) __cpuid_insn(cp); 1259ae115bc7Smrj platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1260ae115bc7Smrj 12617c478bd9Sstevel@tonic-gate /* 12627c478bd9Sstevel@tonic-gate * Virtual and physical address limits from 12637c478bd9Sstevel@tonic-gate * cpuid override previously guessed values. 12647c478bd9Sstevel@tonic-gate */ 12657c478bd9Sstevel@tonic-gate cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 12667c478bd9Sstevel@tonic-gate cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 12677c478bd9Sstevel@tonic-gate break; 12687c478bd9Sstevel@tonic-gate default: 12697c478bd9Sstevel@tonic-gate break; 12707c478bd9Sstevel@tonic-gate } 12718949bcd6Sandrei 1272d129bde2Sesaxe /* 1273d129bde2Sesaxe * Derive the number of cores per chip 1274d129bde2Sesaxe */ 12758949bcd6Sandrei switch (cpi->cpi_vendor) { 12768949bcd6Sandrei case X86_VENDOR_Intel: 12778949bcd6Sandrei if (cpi->cpi_maxeax < 4) { 12788949bcd6Sandrei cpi->cpi_ncore_per_chip = 1; 12798949bcd6Sandrei break; 12808949bcd6Sandrei } else { 12818949bcd6Sandrei cpi->cpi_ncore_per_chip = 12828949bcd6Sandrei BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 12838949bcd6Sandrei } 12848949bcd6Sandrei break; 12858949bcd6Sandrei case X86_VENDOR_AMD: 12868949bcd6Sandrei if (cpi->cpi_xmaxeax < 0x80000008) { 12878949bcd6Sandrei cpi->cpi_ncore_per_chip = 1; 12888949bcd6Sandrei break; 12898949bcd6Sandrei } else { 129010569901Sgavinm /* 129110569901Sgavinm * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 129210569901Sgavinm * 1 less than the number of physical cores on 129310569901Sgavinm * the chip. In family 0x10 this value can 129410569901Sgavinm * be affected by "downcoring" - it reflects 129510569901Sgavinm * 1 less than the number of cores actually 129610569901Sgavinm * enabled on this node. 129710569901Sgavinm */ 12988949bcd6Sandrei cpi->cpi_ncore_per_chip = 12998949bcd6Sandrei BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 13008949bcd6Sandrei } 13018949bcd6Sandrei break; 13028949bcd6Sandrei default: 13038949bcd6Sandrei cpi->cpi_ncore_per_chip = 1; 13048949bcd6Sandrei break; 13057c478bd9Sstevel@tonic-gate } 13060e751525SEric Saxe 13070e751525SEric Saxe /* 13080e751525SEric Saxe * Get CPUID data about TSC Invariance in Deep C-State. 13090e751525SEric Saxe */ 13100e751525SEric Saxe switch (cpi->cpi_vendor) { 13110e751525SEric Saxe case X86_VENDOR_Intel: 13120e751525SEric Saxe if (cpi->cpi_maxeax >= 7) { 13130e751525SEric Saxe cp = &cpi->cpi_extd[7]; 13140e751525SEric Saxe cp->cp_eax = 0x80000007; 13150e751525SEric Saxe cp->cp_ecx = 0; 13160e751525SEric Saxe (void) __cpuid_insn(cp); 13170e751525SEric Saxe } 13180e751525SEric Saxe break; 13190e751525SEric Saxe default: 13200e751525SEric Saxe break; 13210e751525SEric Saxe } 1322fa2e767eSgavinm } else { 1323fa2e767eSgavinm cpi->cpi_ncore_per_chip = 1; 13248949bcd6Sandrei } 13258949bcd6Sandrei 13268949bcd6Sandrei /* 13278949bcd6Sandrei * If more than one core, then this processor is CMP. 13288949bcd6Sandrei */ 13298949bcd6Sandrei if (cpi->cpi_ncore_per_chip > 1) 13308949bcd6Sandrei feature |= X86_CMP; 1331ae115bc7Smrj 13328949bcd6Sandrei /* 13338949bcd6Sandrei * If the number of cores is the same as the number 13348949bcd6Sandrei * of CPUs, then we cannot have HyperThreading. 13358949bcd6Sandrei */ 13368949bcd6Sandrei if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 13378949bcd6Sandrei feature &= ~X86_HTT; 13388949bcd6Sandrei 13398031591dSSrihari Venkatesan cpi->cpi_apicid = CPI_APIC_ID(cpi); 13408031591dSSrihari Venkatesan cpi->cpi_procnodes_per_pkg = 1; 13418031591dSSrihari Venkatesan 13427c478bd9Sstevel@tonic-gate if ((feature & (X86_HTT | X86_CMP)) == 0) { 13438949bcd6Sandrei /* 13448949bcd6Sandrei * Single-core single-threaded processors. 13458949bcd6Sandrei */ 13467c478bd9Sstevel@tonic-gate cpi->cpi_chipid = -1; 13477c478bd9Sstevel@tonic-gate cpi->cpi_clogid = 0; 13488949bcd6Sandrei cpi->cpi_coreid = cpu->cpu_id; 134910569901Sgavinm cpi->cpi_pkgcoreid = 0; 13508031591dSSrihari Venkatesan if (cpi->cpi_vendor == X86_VENDOR_AMD) 13518031591dSSrihari Venkatesan cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0); 13528031591dSSrihari Venkatesan else 13538031591dSSrihari Venkatesan cpi->cpi_procnodeid = cpi->cpi_chipid; 13547c478bd9Sstevel@tonic-gate } else if (cpi->cpi_ncpu_per_chip > 1) { 13558031591dSSrihari Venkatesan if (cpi->cpi_vendor == X86_VENDOR_Intel) 13568031591dSSrihari Venkatesan cpuid_intel_getids(cpu, feature); 13578031591dSSrihari Venkatesan else if (cpi->cpi_vendor == X86_VENDOR_AMD) 13588031591dSSrihari Venkatesan cpuid_amd_getids(cpu); 13598031591dSSrihari Venkatesan else { 13608949bcd6Sandrei /* 13618949bcd6Sandrei * All other processors are currently 13628949bcd6Sandrei * assumed to have single cores. 13638949bcd6Sandrei */ 13648949bcd6Sandrei cpi->cpi_coreid = cpi->cpi_chipid; 136510569901Sgavinm cpi->cpi_pkgcoreid = 0; 13668031591dSSrihari Venkatesan cpi->cpi_procnodeid = cpi->cpi_chipid; 13678949bcd6Sandrei } 13687c478bd9Sstevel@tonic-gate } 13697c478bd9Sstevel@tonic-gate 13708a40a695Sgavinm /* 13718a40a695Sgavinm * Synthesize chip "revision" and socket type 13728a40a695Sgavinm */ 1373e4b86885SCheng Sean Ye cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1374e4b86885SCheng Sean Ye cpi->cpi_model, cpi->cpi_step); 1375e4b86885SCheng Sean Ye cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1376e4b86885SCheng Sean Ye cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1377e4b86885SCheng Sean Ye cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1378e4b86885SCheng Sean Ye cpi->cpi_model, cpi->cpi_step); 13798a40a695Sgavinm 13807c478bd9Sstevel@tonic-gate pass1_done: 13817c478bd9Sstevel@tonic-gate cpi->cpi_pass = 1; 13827c478bd9Sstevel@tonic-gate return (feature); 13837c478bd9Sstevel@tonic-gate } 13847c478bd9Sstevel@tonic-gate 13857c478bd9Sstevel@tonic-gate /* 13867c478bd9Sstevel@tonic-gate * Make copies of the cpuid table entries we depend on, in 13877c478bd9Sstevel@tonic-gate * part for ease of parsing now, in part so that we have only 13887c478bd9Sstevel@tonic-gate * one place to correct any of it, in part for ease of 13897c478bd9Sstevel@tonic-gate * later export to userland, and in part so we can look at 13907c478bd9Sstevel@tonic-gate * this stuff in a crash dump. 13917c478bd9Sstevel@tonic-gate */ 13927c478bd9Sstevel@tonic-gate 13937c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 13947c478bd9Sstevel@tonic-gate void 13957c478bd9Sstevel@tonic-gate cpuid_pass2(cpu_t *cpu) 13967c478bd9Sstevel@tonic-gate { 13977c478bd9Sstevel@tonic-gate uint_t n, nmax; 13987c478bd9Sstevel@tonic-gate int i; 13998949bcd6Sandrei struct cpuid_regs *cp; 14007c478bd9Sstevel@tonic-gate uint8_t *dp; 14017c478bd9Sstevel@tonic-gate uint32_t *iptr; 14027c478bd9Sstevel@tonic-gate struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 14037c478bd9Sstevel@tonic-gate 14047c478bd9Sstevel@tonic-gate ASSERT(cpi->cpi_pass == 1); 14057c478bd9Sstevel@tonic-gate 14067c478bd9Sstevel@tonic-gate if (cpi->cpi_maxeax < 1) 14077c478bd9Sstevel@tonic-gate goto pass2_done; 14087c478bd9Sstevel@tonic-gate 14097c478bd9Sstevel@tonic-gate if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 14107c478bd9Sstevel@tonic-gate nmax = NMAX_CPI_STD; 14117c478bd9Sstevel@tonic-gate /* 14127c478bd9Sstevel@tonic-gate * (We already handled n == 0 and n == 1 in pass 1) 14137c478bd9Sstevel@tonic-gate */ 14147c478bd9Sstevel@tonic-gate for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 14158949bcd6Sandrei cp->cp_eax = n; 1416d129bde2Sesaxe 1417d129bde2Sesaxe /* 1418d129bde2Sesaxe * CPUID function 4 expects %ecx to be initialized 1419d129bde2Sesaxe * with an index which indicates which cache to return 1420d129bde2Sesaxe * information about. The OS is expected to call function 4 1421d129bde2Sesaxe * with %ecx set to 0, 1, 2, ... until it returns with 1422d129bde2Sesaxe * EAX[4:0] set to 0, which indicates there are no more 1423d129bde2Sesaxe * caches. 1424d129bde2Sesaxe * 1425d129bde2Sesaxe * Here, populate cpi_std[4] with the information returned by 1426d129bde2Sesaxe * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1427d129bde2Sesaxe * when dynamic memory allocation becomes available. 1428d129bde2Sesaxe * 1429d129bde2Sesaxe * Note: we need to explicitly initialize %ecx here, since 1430d129bde2Sesaxe * function 4 may have been previously invoked. 1431d129bde2Sesaxe */ 1432d129bde2Sesaxe if (n == 4) 1433d129bde2Sesaxe cp->cp_ecx = 0; 1434d129bde2Sesaxe 14358949bcd6Sandrei (void) __cpuid_insn(cp); 1436ae115bc7Smrj platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 14377c478bd9Sstevel@tonic-gate switch (n) { 14387c478bd9Sstevel@tonic-gate case 2: 14397c478bd9Sstevel@tonic-gate /* 14407c478bd9Sstevel@tonic-gate * "the lower 8 bits of the %eax register 14417c478bd9Sstevel@tonic-gate * contain a value that identifies the number 14427c478bd9Sstevel@tonic-gate * of times the cpuid [instruction] has to be 14437c478bd9Sstevel@tonic-gate * executed to obtain a complete image of the 14447c478bd9Sstevel@tonic-gate * processor's caching systems." 14457c478bd9Sstevel@tonic-gate * 14467c478bd9Sstevel@tonic-gate * How *do* they make this stuff up? 14477c478bd9Sstevel@tonic-gate */ 14487c478bd9Sstevel@tonic-gate cpi->cpi_ncache = sizeof (*cp) * 14497c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 7, 0); 14507c478bd9Sstevel@tonic-gate if (cpi->cpi_ncache == 0) 14517c478bd9Sstevel@tonic-gate break; 14527c478bd9Sstevel@tonic-gate cpi->cpi_ncache--; /* skip count byte */ 14537c478bd9Sstevel@tonic-gate 14547c478bd9Sstevel@tonic-gate /* 14557c478bd9Sstevel@tonic-gate * Well, for now, rather than attempt to implement 14567c478bd9Sstevel@tonic-gate * this slightly dubious algorithm, we just look 14577c478bd9Sstevel@tonic-gate * at the first 15 .. 14587c478bd9Sstevel@tonic-gate */ 14597c478bd9Sstevel@tonic-gate if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 14607c478bd9Sstevel@tonic-gate cpi->cpi_ncache = sizeof (*cp) - 1; 14617c478bd9Sstevel@tonic-gate 14627c478bd9Sstevel@tonic-gate dp = cpi->cpi_cacheinfo; 14637c478bd9Sstevel@tonic-gate if (BITX(cp->cp_eax, 31, 31) == 0) { 14647c478bd9Sstevel@tonic-gate uint8_t *p = (void *)&cp->cp_eax; 146563d3f7dfSkk208521 for (i = 1; i < 4; i++) 14667c478bd9Sstevel@tonic-gate if (p[i] != 0) 14677c478bd9Sstevel@tonic-gate *dp++ = p[i]; 14687c478bd9Sstevel@tonic-gate } 14697c478bd9Sstevel@tonic-gate if (BITX(cp->cp_ebx, 31, 31) == 0) { 14707c478bd9Sstevel@tonic-gate uint8_t *p = (void *)&cp->cp_ebx; 14717c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) 14727c478bd9Sstevel@tonic-gate if (p[i] != 0) 14737c478bd9Sstevel@tonic-gate *dp++ = p[i]; 14747c478bd9Sstevel@tonic-gate } 14757c478bd9Sstevel@tonic-gate if (BITX(cp->cp_ecx, 31, 31) == 0) { 14767c478bd9Sstevel@tonic-gate uint8_t *p = (void *)&cp->cp_ecx; 14777c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) 14787c478bd9Sstevel@tonic-gate if (p[i] != 0) 14797c478bd9Sstevel@tonic-gate *dp++ = p[i]; 14807c478bd9Sstevel@tonic-gate } 14817c478bd9Sstevel@tonic-gate if (BITX(cp->cp_edx, 31, 31) == 0) { 14827c478bd9Sstevel@tonic-gate uint8_t *p = (void *)&cp->cp_edx; 14837c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) 14847c478bd9Sstevel@tonic-gate if (p[i] != 0) 14857c478bd9Sstevel@tonic-gate *dp++ = p[i]; 14867c478bd9Sstevel@tonic-gate } 14877c478bd9Sstevel@tonic-gate break; 1488f98fbcecSbholler 14897c478bd9Sstevel@tonic-gate case 3: /* Processor serial number, if PSN supported */ 1490f98fbcecSbholler break; 1491f98fbcecSbholler 14927c478bd9Sstevel@tonic-gate case 4: /* Deterministic cache parameters */ 1493f98fbcecSbholler break; 1494f98fbcecSbholler 14957c478bd9Sstevel@tonic-gate case 5: /* Monitor/Mwait parameters */ 14965b8a6efeSbholler { 14975b8a6efeSbholler size_t mwait_size; 1498f98fbcecSbholler 1499f98fbcecSbholler /* 1500f98fbcecSbholler * check cpi_mwait.support which was set in cpuid_pass1 1501f98fbcecSbholler */ 1502f98fbcecSbholler if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1503f98fbcecSbholler break; 1504f98fbcecSbholler 15055b8a6efeSbholler /* 15065b8a6efeSbholler * Protect ourself from insane mwait line size. 15075b8a6efeSbholler * Workaround for incomplete hardware emulator(s). 15085b8a6efeSbholler */ 15095b8a6efeSbholler mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 15105b8a6efeSbholler if (mwait_size < sizeof (uint32_t) || 15115b8a6efeSbholler !ISP2(mwait_size)) { 15125b8a6efeSbholler #if DEBUG 15135b8a6efeSbholler cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 15145d8efbbcSSaurabh Misra "size %ld", cpu->cpu_id, (long)mwait_size); 15155b8a6efeSbholler #endif 15165b8a6efeSbholler break; 15175b8a6efeSbholler } 15185b8a6efeSbholler 1519f98fbcecSbholler cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 15205b8a6efeSbholler cpi->cpi_mwait.mon_max = mwait_size; 1521f98fbcecSbholler if (MWAIT_EXTENSION(cpi)) { 1522f98fbcecSbholler cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1523f98fbcecSbholler if (MWAIT_INT_ENABLE(cpi)) 1524f98fbcecSbholler cpi->cpi_mwait.support |= 1525f98fbcecSbholler MWAIT_ECX_INT_ENABLE; 1526f98fbcecSbholler } 1527f98fbcecSbholler break; 15285b8a6efeSbholler } 15297c478bd9Sstevel@tonic-gate default: 15307c478bd9Sstevel@tonic-gate break; 15317c478bd9Sstevel@tonic-gate } 15327c478bd9Sstevel@tonic-gate } 15337c478bd9Sstevel@tonic-gate 1534b6917abeSmishra if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 15355d8efbbcSSaurabh Misra struct cpuid_regs regs; 15365d8efbbcSSaurabh Misra 15375d8efbbcSSaurabh Misra cp = ®s; 1538b6917abeSmishra cp->cp_eax = 0xB; 15395d8efbbcSSaurabh Misra cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1540b6917abeSmishra 1541b6917abeSmishra (void) __cpuid_insn(cp); 1542b6917abeSmishra 1543b6917abeSmishra /* 1544b6917abeSmishra * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1545b6917abeSmishra * indicates that the extended topology enumeration leaf is 1546b6917abeSmishra * available. 1547b6917abeSmishra */ 1548b6917abeSmishra if (cp->cp_ebx) { 1549b6917abeSmishra uint32_t x2apic_id; 1550b6917abeSmishra uint_t coreid_shift = 0; 1551b6917abeSmishra uint_t ncpu_per_core = 1; 1552b6917abeSmishra uint_t chipid_shift = 0; 1553b6917abeSmishra uint_t ncpu_per_chip = 1; 1554b6917abeSmishra uint_t i; 1555b6917abeSmishra uint_t level; 1556b6917abeSmishra 1557b6917abeSmishra for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1558b6917abeSmishra cp->cp_eax = 0xB; 1559b6917abeSmishra cp->cp_ecx = i; 1560b6917abeSmishra 1561b6917abeSmishra (void) __cpuid_insn(cp); 1562b6917abeSmishra level = CPI_CPU_LEVEL_TYPE(cp); 1563b6917abeSmishra 1564b6917abeSmishra if (level == 1) { 1565b6917abeSmishra x2apic_id = cp->cp_edx; 1566b6917abeSmishra coreid_shift = BITX(cp->cp_eax, 4, 0); 1567b6917abeSmishra ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1568b6917abeSmishra } else if (level == 2) { 1569b6917abeSmishra x2apic_id = cp->cp_edx; 1570b6917abeSmishra chipid_shift = BITX(cp->cp_eax, 4, 0); 1571b6917abeSmishra ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1572b6917abeSmishra } 1573b6917abeSmishra } 1574b6917abeSmishra 1575b6917abeSmishra cpi->cpi_apicid = x2apic_id; 1576b6917abeSmishra cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1577b6917abeSmishra cpi->cpi_ncore_per_chip = ncpu_per_chip / 1578b6917abeSmishra ncpu_per_core; 1579b6917abeSmishra cpi->cpi_chipid = x2apic_id >> chipid_shift; 1580b6917abeSmishra cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1581b6917abeSmishra cpi->cpi_coreid = x2apic_id >> coreid_shift; 1582b6917abeSmishra cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1583b6917abeSmishra } 15845d8efbbcSSaurabh Misra 15855d8efbbcSSaurabh Misra /* Make cp NULL so that we don't stumble on others */ 15865d8efbbcSSaurabh Misra cp = NULL; 1587b6917abeSmishra } 1588b6917abeSmishra 15897c478bd9Sstevel@tonic-gate if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 15907c478bd9Sstevel@tonic-gate goto pass2_done; 15917c478bd9Sstevel@tonic-gate 15927c478bd9Sstevel@tonic-gate if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 15937c478bd9Sstevel@tonic-gate nmax = NMAX_CPI_EXTD; 15947c478bd9Sstevel@tonic-gate /* 15957c478bd9Sstevel@tonic-gate * Copy the extended properties, fixing them as we go. 15967c478bd9Sstevel@tonic-gate * (We already handled n == 0 and n == 1 in pass 1) 15977c478bd9Sstevel@tonic-gate */ 15987c478bd9Sstevel@tonic-gate iptr = (void *)cpi->cpi_brandstr; 15997c478bd9Sstevel@tonic-gate for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 16008949bcd6Sandrei cp->cp_eax = 0x80000000 + n; 16018949bcd6Sandrei (void) __cpuid_insn(cp); 1602ae115bc7Smrj platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 16037c478bd9Sstevel@tonic-gate switch (n) { 16047c478bd9Sstevel@tonic-gate case 2: 16057c478bd9Sstevel@tonic-gate case 3: 16067c478bd9Sstevel@tonic-gate case 4: 16077c478bd9Sstevel@tonic-gate /* 16087c478bd9Sstevel@tonic-gate * Extract the brand string 16097c478bd9Sstevel@tonic-gate */ 16107c478bd9Sstevel@tonic-gate *iptr++ = cp->cp_eax; 16117c478bd9Sstevel@tonic-gate *iptr++ = cp->cp_ebx; 16127c478bd9Sstevel@tonic-gate *iptr++ = cp->cp_ecx; 16137c478bd9Sstevel@tonic-gate *iptr++ = cp->cp_edx; 16147c478bd9Sstevel@tonic-gate break; 16157c478bd9Sstevel@tonic-gate case 5: 16167c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 16177c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 16187c478bd9Sstevel@tonic-gate /* 16197c478bd9Sstevel@tonic-gate * The Athlon and Duron were the first 16207c478bd9Sstevel@tonic-gate * parts to report the sizes of the 16217c478bd9Sstevel@tonic-gate * TLB for large pages. Before then, 16227c478bd9Sstevel@tonic-gate * we don't trust the data. 16237c478bd9Sstevel@tonic-gate */ 16247c478bd9Sstevel@tonic-gate if (cpi->cpi_family < 6 || 16257c478bd9Sstevel@tonic-gate (cpi->cpi_family == 6 && 16267c478bd9Sstevel@tonic-gate cpi->cpi_model < 1)) 16277c478bd9Sstevel@tonic-gate cp->cp_eax = 0; 16287c478bd9Sstevel@tonic-gate break; 16297c478bd9Sstevel@tonic-gate default: 16307c478bd9Sstevel@tonic-gate break; 16317c478bd9Sstevel@tonic-gate } 16327c478bd9Sstevel@tonic-gate break; 16337c478bd9Sstevel@tonic-gate case 6: 16347c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 16357c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 16367c478bd9Sstevel@tonic-gate /* 16377c478bd9Sstevel@tonic-gate * The Athlon and Duron were the first 16387c478bd9Sstevel@tonic-gate * AMD parts with L2 TLB's. 16397c478bd9Sstevel@tonic-gate * Before then, don't trust the data. 16407c478bd9Sstevel@tonic-gate */ 16417c478bd9Sstevel@tonic-gate if (cpi->cpi_family < 6 || 16427c478bd9Sstevel@tonic-gate cpi->cpi_family == 6 && 16437c478bd9Sstevel@tonic-gate cpi->cpi_model < 1) 16447c478bd9Sstevel@tonic-gate cp->cp_eax = cp->cp_ebx = 0; 16457c478bd9Sstevel@tonic-gate /* 16467c478bd9Sstevel@tonic-gate * AMD Duron rev A0 reports L2 16477c478bd9Sstevel@tonic-gate * cache size incorrectly as 1K 16487c478bd9Sstevel@tonic-gate * when it is really 64K 16497c478bd9Sstevel@tonic-gate */ 16507c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 6 && 16517c478bd9Sstevel@tonic-gate cpi->cpi_model == 3 && 16527c478bd9Sstevel@tonic-gate cpi->cpi_step == 0) { 16537c478bd9Sstevel@tonic-gate cp->cp_ecx &= 0xffff; 16547c478bd9Sstevel@tonic-gate cp->cp_ecx |= 0x400000; 16557c478bd9Sstevel@tonic-gate } 16567c478bd9Sstevel@tonic-gate break; 16577c478bd9Sstevel@tonic-gate case X86_VENDOR_Cyrix: /* VIA C3 */ 16587c478bd9Sstevel@tonic-gate /* 16597c478bd9Sstevel@tonic-gate * VIA C3 processors are a bit messed 16607c478bd9Sstevel@tonic-gate * up w.r.t. encoding cache sizes in %ecx 16617c478bd9Sstevel@tonic-gate */ 16627c478bd9Sstevel@tonic-gate if (cpi->cpi_family != 6) 16637c478bd9Sstevel@tonic-gate break; 16647c478bd9Sstevel@tonic-gate /* 16657c478bd9Sstevel@tonic-gate * model 7 and 8 were incorrectly encoded 16667c478bd9Sstevel@tonic-gate * 16677c478bd9Sstevel@tonic-gate * xxx is model 8 really broken? 16687c478bd9Sstevel@tonic-gate */ 16697c478bd9Sstevel@tonic-gate if (cpi->cpi_model == 7 || 16707c478bd9Sstevel@tonic-gate cpi->cpi_model == 8) 16717c478bd9Sstevel@tonic-gate cp->cp_ecx = 16727c478bd9Sstevel@tonic-gate BITX(cp->cp_ecx, 31, 24) << 16 | 16737c478bd9Sstevel@tonic-gate BITX(cp->cp_ecx, 23, 16) << 12 | 16747c478bd9Sstevel@tonic-gate BITX(cp->cp_ecx, 15, 8) << 8 | 16757c478bd9Sstevel@tonic-gate BITX(cp->cp_ecx, 7, 0); 16767c478bd9Sstevel@tonic-gate /* 16777c478bd9Sstevel@tonic-gate * model 9 stepping 1 has wrong associativity 16787c478bd9Sstevel@tonic-gate */ 16797c478bd9Sstevel@tonic-gate if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 16807c478bd9Sstevel@tonic-gate cp->cp_ecx |= 8 << 12; 16817c478bd9Sstevel@tonic-gate break; 16827c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 16837c478bd9Sstevel@tonic-gate /* 16847c478bd9Sstevel@tonic-gate * Extended L2 Cache features function. 16857c478bd9Sstevel@tonic-gate * First appeared on Prescott. 16867c478bd9Sstevel@tonic-gate */ 16877c478bd9Sstevel@tonic-gate default: 16887c478bd9Sstevel@tonic-gate break; 16897c478bd9Sstevel@tonic-gate } 16907c478bd9Sstevel@tonic-gate break; 16917c478bd9Sstevel@tonic-gate default: 16927c478bd9Sstevel@tonic-gate break; 16937c478bd9Sstevel@tonic-gate } 16947c478bd9Sstevel@tonic-gate } 16957c478bd9Sstevel@tonic-gate 16967c478bd9Sstevel@tonic-gate pass2_done: 16977c478bd9Sstevel@tonic-gate cpi->cpi_pass = 2; 16987c478bd9Sstevel@tonic-gate } 16997c478bd9Sstevel@tonic-gate 17007c478bd9Sstevel@tonic-gate static const char * 17017c478bd9Sstevel@tonic-gate intel_cpubrand(const struct cpuid_info *cpi) 17027c478bd9Sstevel@tonic-gate { 17037c478bd9Sstevel@tonic-gate int i; 17047c478bd9Sstevel@tonic-gate 17057c478bd9Sstevel@tonic-gate if ((x86_feature & X86_CPUID) == 0 || 17067c478bd9Sstevel@tonic-gate cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 17077c478bd9Sstevel@tonic-gate return ("i486"); 17087c478bd9Sstevel@tonic-gate 17097c478bd9Sstevel@tonic-gate switch (cpi->cpi_family) { 17107c478bd9Sstevel@tonic-gate case 5: 17117c478bd9Sstevel@tonic-gate return ("Intel Pentium(r)"); 17127c478bd9Sstevel@tonic-gate case 6: 17137c478bd9Sstevel@tonic-gate switch (cpi->cpi_model) { 17147c478bd9Sstevel@tonic-gate uint_t celeron, xeon; 17158949bcd6Sandrei const struct cpuid_regs *cp; 17167c478bd9Sstevel@tonic-gate case 0: 17177c478bd9Sstevel@tonic-gate case 1: 17187c478bd9Sstevel@tonic-gate case 2: 17197c478bd9Sstevel@tonic-gate return ("Intel Pentium(r) Pro"); 17207c478bd9Sstevel@tonic-gate case 3: 17217c478bd9Sstevel@tonic-gate case 4: 17227c478bd9Sstevel@tonic-gate return ("Intel Pentium(r) II"); 17237c478bd9Sstevel@tonic-gate case 6: 17247c478bd9Sstevel@tonic-gate return ("Intel Celeron(r)"); 17257c478bd9Sstevel@tonic-gate case 5: 17267c478bd9Sstevel@tonic-gate case 7: 17277c478bd9Sstevel@tonic-gate celeron = xeon = 0; 17287c478bd9Sstevel@tonic-gate cp = &cpi->cpi_std[2]; /* cache info */ 17297c478bd9Sstevel@tonic-gate 173063d3f7dfSkk208521 for (i = 1; i < 4; i++) { 17317c478bd9Sstevel@tonic-gate uint_t tmp; 17327c478bd9Sstevel@tonic-gate 17337c478bd9Sstevel@tonic-gate tmp = (cp->cp_eax >> (8 * i)) & 0xff; 17347c478bd9Sstevel@tonic-gate if (tmp == 0x40) 17357c478bd9Sstevel@tonic-gate celeron++; 17367c478bd9Sstevel@tonic-gate if (tmp >= 0x44 && tmp <= 0x45) 17377c478bd9Sstevel@tonic-gate xeon++; 17387c478bd9Sstevel@tonic-gate } 17397c478bd9Sstevel@tonic-gate 17407c478bd9Sstevel@tonic-gate for (i = 0; i < 2; i++) { 17417c478bd9Sstevel@tonic-gate uint_t tmp; 17427c478bd9Sstevel@tonic-gate 17437c478bd9Sstevel@tonic-gate tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 17447c478bd9Sstevel@tonic-gate if (tmp == 0x40) 17457c478bd9Sstevel@tonic-gate celeron++; 17467c478bd9Sstevel@tonic-gate else if (tmp >= 0x44 && tmp <= 0x45) 17477c478bd9Sstevel@tonic-gate xeon++; 17487c478bd9Sstevel@tonic-gate } 17497c478bd9Sstevel@tonic-gate 17507c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 17517c478bd9Sstevel@tonic-gate uint_t tmp; 17527c478bd9Sstevel@tonic-gate 17537c478bd9Sstevel@tonic-gate tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 17547c478bd9Sstevel@tonic-gate if (tmp == 0x40) 17557c478bd9Sstevel@tonic-gate celeron++; 17567c478bd9Sstevel@tonic-gate else if (tmp >= 0x44 && tmp <= 0x45) 17577c478bd9Sstevel@tonic-gate xeon++; 17587c478bd9Sstevel@tonic-gate } 17597c478bd9Sstevel@tonic-gate 17607c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 17617c478bd9Sstevel@tonic-gate uint_t tmp; 17627c478bd9Sstevel@tonic-gate 17637c478bd9Sstevel@tonic-gate tmp = (cp->cp_edx >> (8 * i)) & 0xff; 17647c478bd9Sstevel@tonic-gate if (tmp == 0x40) 17657c478bd9Sstevel@tonic-gate celeron++; 17667c478bd9Sstevel@tonic-gate else if (tmp >= 0x44 && tmp <= 0x45) 17677c478bd9Sstevel@tonic-gate xeon++; 17687c478bd9Sstevel@tonic-gate } 17697c478bd9Sstevel@tonic-gate 17707c478bd9Sstevel@tonic-gate if (celeron) 17717c478bd9Sstevel@tonic-gate return ("Intel Celeron(r)"); 17727c478bd9Sstevel@tonic-gate if (xeon) 17737c478bd9Sstevel@tonic-gate return (cpi->cpi_model == 5 ? 17747c478bd9Sstevel@tonic-gate "Intel Pentium(r) II Xeon(tm)" : 17757c478bd9Sstevel@tonic-gate "Intel Pentium(r) III Xeon(tm)"); 17767c478bd9Sstevel@tonic-gate return (cpi->cpi_model == 5 ? 17777c478bd9Sstevel@tonic-gate "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 17787c478bd9Sstevel@tonic-gate "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 17797c478bd9Sstevel@tonic-gate default: 17807c478bd9Sstevel@tonic-gate break; 17817c478bd9Sstevel@tonic-gate } 17827c478bd9Sstevel@tonic-gate default: 17837c478bd9Sstevel@tonic-gate break; 17847c478bd9Sstevel@tonic-gate } 17857c478bd9Sstevel@tonic-gate 17865ff02082Sdmick /* BrandID is present if the field is nonzero */ 17875ff02082Sdmick if (cpi->cpi_brandid != 0) { 17887c478bd9Sstevel@tonic-gate static const struct { 17897c478bd9Sstevel@tonic-gate uint_t bt_bid; 17907c478bd9Sstevel@tonic-gate const char *bt_str; 17917c478bd9Sstevel@tonic-gate } brand_tbl[] = { 17927c478bd9Sstevel@tonic-gate { 0x1, "Intel(r) Celeron(r)" }, 17937c478bd9Sstevel@tonic-gate { 0x2, "Intel(r) Pentium(r) III" }, 17947c478bd9Sstevel@tonic-gate { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 17957c478bd9Sstevel@tonic-gate { 0x4, "Intel(r) Pentium(r) III" }, 17967c478bd9Sstevel@tonic-gate { 0x6, "Mobile Intel(r) Pentium(r) III" }, 17977c478bd9Sstevel@tonic-gate { 0x7, "Mobile Intel(r) Celeron(r)" }, 17987c478bd9Sstevel@tonic-gate { 0x8, "Intel(r) Pentium(r) 4" }, 17997c478bd9Sstevel@tonic-gate { 0x9, "Intel(r) Pentium(r) 4" }, 18007c478bd9Sstevel@tonic-gate { 0xa, "Intel(r) Celeron(r)" }, 18017c478bd9Sstevel@tonic-gate { 0xb, "Intel(r) Xeon(tm)" }, 18027c478bd9Sstevel@tonic-gate { 0xc, "Intel(r) Xeon(tm) MP" }, 18037c478bd9Sstevel@tonic-gate { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 18045ff02082Sdmick { 0xf, "Mobile Intel(r) Celeron(r)" }, 18055ff02082Sdmick { 0x11, "Mobile Genuine Intel(r)" }, 18065ff02082Sdmick { 0x12, "Intel(r) Celeron(r) M" }, 18075ff02082Sdmick { 0x13, "Mobile Intel(r) Celeron(r)" }, 18085ff02082Sdmick { 0x14, "Intel(r) Celeron(r)" }, 18095ff02082Sdmick { 0x15, "Mobile Genuine Intel(r)" }, 18105ff02082Sdmick { 0x16, "Intel(r) Pentium(r) M" }, 18115ff02082Sdmick { 0x17, "Mobile Intel(r) Celeron(r)" } 18127c478bd9Sstevel@tonic-gate }; 18137c478bd9Sstevel@tonic-gate uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 18147c478bd9Sstevel@tonic-gate uint_t sgn; 18157c478bd9Sstevel@tonic-gate 18167c478bd9Sstevel@tonic-gate sgn = (cpi->cpi_family << 8) | 18177c478bd9Sstevel@tonic-gate (cpi->cpi_model << 4) | cpi->cpi_step; 18187c478bd9Sstevel@tonic-gate 18197c478bd9Sstevel@tonic-gate for (i = 0; i < btblmax; i++) 18207c478bd9Sstevel@tonic-gate if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 18217c478bd9Sstevel@tonic-gate break; 18227c478bd9Sstevel@tonic-gate if (i < btblmax) { 18237c478bd9Sstevel@tonic-gate if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 18247c478bd9Sstevel@tonic-gate return ("Intel(r) Celeron(r)"); 18257c478bd9Sstevel@tonic-gate if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 18267c478bd9Sstevel@tonic-gate return ("Intel(r) Xeon(tm) MP"); 18277c478bd9Sstevel@tonic-gate if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 18287c478bd9Sstevel@tonic-gate return ("Intel(r) Xeon(tm)"); 18297c478bd9Sstevel@tonic-gate return (brand_tbl[i].bt_str); 18307c478bd9Sstevel@tonic-gate } 18317c478bd9Sstevel@tonic-gate } 18327c478bd9Sstevel@tonic-gate 18337c478bd9Sstevel@tonic-gate return (NULL); 18347c478bd9Sstevel@tonic-gate } 18357c478bd9Sstevel@tonic-gate 18367c478bd9Sstevel@tonic-gate static const char * 18377c478bd9Sstevel@tonic-gate amd_cpubrand(const struct cpuid_info *cpi) 18387c478bd9Sstevel@tonic-gate { 18397c478bd9Sstevel@tonic-gate if ((x86_feature & X86_CPUID) == 0 || 18407c478bd9Sstevel@tonic-gate cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 18417c478bd9Sstevel@tonic-gate return ("i486 compatible"); 18427c478bd9Sstevel@tonic-gate 18437c478bd9Sstevel@tonic-gate switch (cpi->cpi_family) { 18447c478bd9Sstevel@tonic-gate case 5: 18457c478bd9Sstevel@tonic-gate switch (cpi->cpi_model) { 18467c478bd9Sstevel@tonic-gate case 0: 18477c478bd9Sstevel@tonic-gate case 1: 18487c478bd9Sstevel@tonic-gate case 2: 18497c478bd9Sstevel@tonic-gate case 3: 18507c478bd9Sstevel@tonic-gate case 4: 18517c478bd9Sstevel@tonic-gate case 5: 18527c478bd9Sstevel@tonic-gate return ("AMD-K5(r)"); 18537c478bd9Sstevel@tonic-gate case 6: 18547c478bd9Sstevel@tonic-gate case 7: 18557c478bd9Sstevel@tonic-gate return ("AMD-K6(r)"); 18567c478bd9Sstevel@tonic-gate case 8: 18577c478bd9Sstevel@tonic-gate return ("AMD-K6(r)-2"); 18587c478bd9Sstevel@tonic-gate case 9: 18597c478bd9Sstevel@tonic-gate return ("AMD-K6(r)-III"); 18607c478bd9Sstevel@tonic-gate default: 18617c478bd9Sstevel@tonic-gate return ("AMD (family 5)"); 18627c478bd9Sstevel@tonic-gate } 18637c478bd9Sstevel@tonic-gate case 6: 18647c478bd9Sstevel@tonic-gate switch (cpi->cpi_model) { 18657c478bd9Sstevel@tonic-gate case 1: 18667c478bd9Sstevel@tonic-gate return ("AMD-K7(tm)"); 18677c478bd9Sstevel@tonic-gate case 0: 18687c478bd9Sstevel@tonic-gate case 2: 18697c478bd9Sstevel@tonic-gate case 4: 18707c478bd9Sstevel@tonic-gate return ("AMD Athlon(tm)"); 18717c478bd9Sstevel@tonic-gate case 3: 18727c478bd9Sstevel@tonic-gate case 7: 18737c478bd9Sstevel@tonic-gate return ("AMD Duron(tm)"); 18747c478bd9Sstevel@tonic-gate case 6: 18757c478bd9Sstevel@tonic-gate case 8: 18767c478bd9Sstevel@tonic-gate case 10: 18777c478bd9Sstevel@tonic-gate /* 18787c478bd9Sstevel@tonic-gate * Use the L2 cache size to distinguish 18797c478bd9Sstevel@tonic-gate */ 18807c478bd9Sstevel@tonic-gate return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 18817c478bd9Sstevel@tonic-gate "AMD Athlon(tm)" : "AMD Duron(tm)"); 18827c478bd9Sstevel@tonic-gate default: 18837c478bd9Sstevel@tonic-gate return ("AMD (family 6)"); 18847c478bd9Sstevel@tonic-gate } 18857c478bd9Sstevel@tonic-gate default: 18867c478bd9Sstevel@tonic-gate break; 18877c478bd9Sstevel@tonic-gate } 18887c478bd9Sstevel@tonic-gate 18897c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 18907c478bd9Sstevel@tonic-gate cpi->cpi_brandid != 0) { 18917c478bd9Sstevel@tonic-gate switch (BITX(cpi->cpi_brandid, 7, 5)) { 18927c478bd9Sstevel@tonic-gate case 3: 18937c478bd9Sstevel@tonic-gate return ("AMD Opteron(tm) UP 1xx"); 18947c478bd9Sstevel@tonic-gate case 4: 18957c478bd9Sstevel@tonic-gate return ("AMD Opteron(tm) DP 2xx"); 18967c478bd9Sstevel@tonic-gate case 5: 18977c478bd9Sstevel@tonic-gate return ("AMD Opteron(tm) MP 8xx"); 18987c478bd9Sstevel@tonic-gate default: 18997c478bd9Sstevel@tonic-gate return ("AMD Opteron(tm)"); 19007c478bd9Sstevel@tonic-gate } 19017c478bd9Sstevel@tonic-gate } 19027c478bd9Sstevel@tonic-gate 19037c478bd9Sstevel@tonic-gate return (NULL); 19047c478bd9Sstevel@tonic-gate } 19057c478bd9Sstevel@tonic-gate 19067c478bd9Sstevel@tonic-gate static const char * 19077c478bd9Sstevel@tonic-gate cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 19087c478bd9Sstevel@tonic-gate { 19097c478bd9Sstevel@tonic-gate if ((x86_feature & X86_CPUID) == 0 || 19107c478bd9Sstevel@tonic-gate cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 19117c478bd9Sstevel@tonic-gate type == X86_TYPE_CYRIX_486) 19127c478bd9Sstevel@tonic-gate return ("i486 compatible"); 19137c478bd9Sstevel@tonic-gate 19147c478bd9Sstevel@tonic-gate switch (type) { 19157c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_6x86: 19167c478bd9Sstevel@tonic-gate return ("Cyrix 6x86"); 19177c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_6x86L: 19187c478bd9Sstevel@tonic-gate return ("Cyrix 6x86L"); 19197c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_6x86MX: 19207c478bd9Sstevel@tonic-gate return ("Cyrix 6x86MX"); 19217c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_GXm: 19227c478bd9Sstevel@tonic-gate return ("Cyrix GXm"); 19237c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_MediaGX: 19247c478bd9Sstevel@tonic-gate return ("Cyrix MediaGX"); 19257c478bd9Sstevel@tonic-gate case X86_TYPE_CYRIX_MII: 19267c478bd9Sstevel@tonic-gate return ("Cyrix M2"); 19277c478bd9Sstevel@tonic-gate case X86_TYPE_VIA_CYRIX_III: 19287c478bd9Sstevel@tonic-gate return ("VIA Cyrix M3"); 19297c478bd9Sstevel@tonic-gate default: 19307c478bd9Sstevel@tonic-gate /* 19317c478bd9Sstevel@tonic-gate * Have another wild guess .. 19327c478bd9Sstevel@tonic-gate */ 19337c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 19347c478bd9Sstevel@tonic-gate return ("Cyrix 5x86"); 19357c478bd9Sstevel@tonic-gate else if (cpi->cpi_family == 5) { 19367c478bd9Sstevel@tonic-gate switch (cpi->cpi_model) { 19377c478bd9Sstevel@tonic-gate case 2: 19387c478bd9Sstevel@tonic-gate return ("Cyrix 6x86"); /* Cyrix M1 */ 19397c478bd9Sstevel@tonic-gate case 4: 19407c478bd9Sstevel@tonic-gate return ("Cyrix MediaGX"); 19417c478bd9Sstevel@tonic-gate default: 19427c478bd9Sstevel@tonic-gate break; 19437c478bd9Sstevel@tonic-gate } 19447c478bd9Sstevel@tonic-gate } else if (cpi->cpi_family == 6) { 19457c478bd9Sstevel@tonic-gate switch (cpi->cpi_model) { 19467c478bd9Sstevel@tonic-gate case 0: 19477c478bd9Sstevel@tonic-gate return ("Cyrix 6x86MX"); /* Cyrix M2? */ 19487c478bd9Sstevel@tonic-gate case 5: 19497c478bd9Sstevel@tonic-gate case 6: 19507c478bd9Sstevel@tonic-gate case 7: 19517c478bd9Sstevel@tonic-gate case 8: 19527c478bd9Sstevel@tonic-gate case 9: 19537c478bd9Sstevel@tonic-gate return ("VIA C3"); 19547c478bd9Sstevel@tonic-gate default: 19557c478bd9Sstevel@tonic-gate break; 19567c478bd9Sstevel@tonic-gate } 19577c478bd9Sstevel@tonic-gate } 19587c478bd9Sstevel@tonic-gate break; 19597c478bd9Sstevel@tonic-gate } 19607c478bd9Sstevel@tonic-gate return (NULL); 19617c478bd9Sstevel@tonic-gate } 19627c478bd9Sstevel@tonic-gate 19637c478bd9Sstevel@tonic-gate /* 19647c478bd9Sstevel@tonic-gate * This only gets called in the case that the CPU extended 19657c478bd9Sstevel@tonic-gate * feature brand string (0x80000002, 0x80000003, 0x80000004) 19667c478bd9Sstevel@tonic-gate * aren't available, or contain null bytes for some reason. 19677c478bd9Sstevel@tonic-gate */ 19687c478bd9Sstevel@tonic-gate static void 19697c478bd9Sstevel@tonic-gate fabricate_brandstr(struct cpuid_info *cpi) 19707c478bd9Sstevel@tonic-gate { 19717c478bd9Sstevel@tonic-gate const char *brand = NULL; 19727c478bd9Sstevel@tonic-gate 19737c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 19747c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 19757c478bd9Sstevel@tonic-gate brand = intel_cpubrand(cpi); 19767c478bd9Sstevel@tonic-gate break; 19777c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 19787c478bd9Sstevel@tonic-gate brand = amd_cpubrand(cpi); 19797c478bd9Sstevel@tonic-gate break; 19807c478bd9Sstevel@tonic-gate case X86_VENDOR_Cyrix: 19817c478bd9Sstevel@tonic-gate brand = cyrix_cpubrand(cpi, x86_type); 19827c478bd9Sstevel@tonic-gate break; 19837c478bd9Sstevel@tonic-gate case X86_VENDOR_NexGen: 19847c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 19857c478bd9Sstevel@tonic-gate brand = "NexGen Nx586"; 19867c478bd9Sstevel@tonic-gate break; 19877c478bd9Sstevel@tonic-gate case X86_VENDOR_Centaur: 19887c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 5) 19897c478bd9Sstevel@tonic-gate switch (cpi->cpi_model) { 19907c478bd9Sstevel@tonic-gate case 4: 19917c478bd9Sstevel@tonic-gate brand = "Centaur C6"; 19927c478bd9Sstevel@tonic-gate break; 19937c478bd9Sstevel@tonic-gate case 8: 19947c478bd9Sstevel@tonic-gate brand = "Centaur C2"; 19957c478bd9Sstevel@tonic-gate break; 19967c478bd9Sstevel@tonic-gate case 9: 19977c478bd9Sstevel@tonic-gate brand = "Centaur C3"; 19987c478bd9Sstevel@tonic-gate break; 19997c478bd9Sstevel@tonic-gate default: 20007c478bd9Sstevel@tonic-gate break; 20017c478bd9Sstevel@tonic-gate } 20027c478bd9Sstevel@tonic-gate break; 20037c478bd9Sstevel@tonic-gate case X86_VENDOR_Rise: 20047c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 5 && 20057c478bd9Sstevel@tonic-gate (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 20067c478bd9Sstevel@tonic-gate brand = "Rise mP6"; 20077c478bd9Sstevel@tonic-gate break; 20087c478bd9Sstevel@tonic-gate case X86_VENDOR_SiS: 20097c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 20107c478bd9Sstevel@tonic-gate brand = "SiS 55x"; 20117c478bd9Sstevel@tonic-gate break; 20127c478bd9Sstevel@tonic-gate case X86_VENDOR_TM: 20137c478bd9Sstevel@tonic-gate if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 20147c478bd9Sstevel@tonic-gate brand = "Transmeta Crusoe TM3x00 or TM5x00"; 20157c478bd9Sstevel@tonic-gate break; 20167c478bd9Sstevel@tonic-gate case X86_VENDOR_NSC: 20177c478bd9Sstevel@tonic-gate case X86_VENDOR_UMC: 20187c478bd9Sstevel@tonic-gate default: 20197c478bd9Sstevel@tonic-gate break; 20207c478bd9Sstevel@tonic-gate } 20217c478bd9Sstevel@tonic-gate if (brand) { 20227c478bd9Sstevel@tonic-gate (void) strcpy((char *)cpi->cpi_brandstr, brand); 20237c478bd9Sstevel@tonic-gate return; 20247c478bd9Sstevel@tonic-gate } 20257c478bd9Sstevel@tonic-gate 20267c478bd9Sstevel@tonic-gate /* 20277c478bd9Sstevel@tonic-gate * If all else fails ... 20287c478bd9Sstevel@tonic-gate */ 20297c478bd9Sstevel@tonic-gate (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 20307c478bd9Sstevel@tonic-gate "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 20317c478bd9Sstevel@tonic-gate cpi->cpi_model, cpi->cpi_step); 20327c478bd9Sstevel@tonic-gate } 20337c478bd9Sstevel@tonic-gate 20347c478bd9Sstevel@tonic-gate /* 20357c478bd9Sstevel@tonic-gate * This routine is called just after kernel memory allocation 20367c478bd9Sstevel@tonic-gate * becomes available on cpu0, and as part of mp_startup() on 20377c478bd9Sstevel@tonic-gate * the other cpus. 20387c478bd9Sstevel@tonic-gate * 2039d129bde2Sesaxe * Fixup the brand string, and collect any information from cpuid 2040d129bde2Sesaxe * that requires dynamicically allocated storage to represent. 20417c478bd9Sstevel@tonic-gate */ 20427c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 20437c478bd9Sstevel@tonic-gate void 20447c478bd9Sstevel@tonic-gate cpuid_pass3(cpu_t *cpu) 20457c478bd9Sstevel@tonic-gate { 2046d129bde2Sesaxe int i, max, shft, level, size; 2047d129bde2Sesaxe struct cpuid_regs regs; 2048d129bde2Sesaxe struct cpuid_regs *cp; 20497c478bd9Sstevel@tonic-gate struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 20507c478bd9Sstevel@tonic-gate 20517c478bd9Sstevel@tonic-gate ASSERT(cpi->cpi_pass == 2); 20527c478bd9Sstevel@tonic-gate 2053d129bde2Sesaxe /* 2054d129bde2Sesaxe * Function 4: Deterministic cache parameters 2055d129bde2Sesaxe * 2056d129bde2Sesaxe * Take this opportunity to detect the number of threads 2057d129bde2Sesaxe * sharing the last level cache, and construct a corresponding 2058d129bde2Sesaxe * cache id. The respective cpuid_info members are initialized 2059d129bde2Sesaxe * to the default case of "no last level cache sharing". 2060d129bde2Sesaxe */ 2061d129bde2Sesaxe cpi->cpi_ncpu_shr_last_cache = 1; 2062d129bde2Sesaxe cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 2063d129bde2Sesaxe 2064d129bde2Sesaxe if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 2065d129bde2Sesaxe 2066d129bde2Sesaxe /* 2067d129bde2Sesaxe * Find the # of elements (size) returned by fn 4, and along 2068d129bde2Sesaxe * the way detect last level cache sharing details. 2069d129bde2Sesaxe */ 2070d129bde2Sesaxe bzero(®s, sizeof (regs)); 2071d129bde2Sesaxe cp = ®s; 2072d129bde2Sesaxe for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 2073d129bde2Sesaxe cp->cp_eax = 4; 2074d129bde2Sesaxe cp->cp_ecx = i; 2075d129bde2Sesaxe 2076d129bde2Sesaxe (void) __cpuid_insn(cp); 2077d129bde2Sesaxe 2078d129bde2Sesaxe if (CPI_CACHE_TYPE(cp) == 0) 2079d129bde2Sesaxe break; 2080d129bde2Sesaxe level = CPI_CACHE_LVL(cp); 2081d129bde2Sesaxe if (level > max) { 2082d129bde2Sesaxe max = level; 2083d129bde2Sesaxe cpi->cpi_ncpu_shr_last_cache = 2084d129bde2Sesaxe CPI_NTHR_SHR_CACHE(cp) + 1; 2085d129bde2Sesaxe } 2086d129bde2Sesaxe } 2087d129bde2Sesaxe cpi->cpi_std_4_size = size = i; 2088d129bde2Sesaxe 2089d129bde2Sesaxe /* 2090d129bde2Sesaxe * Allocate the cpi_std_4 array. The first element 2091d129bde2Sesaxe * references the regs for fn 4, %ecx == 0, which 2092d129bde2Sesaxe * cpuid_pass2() stashed in cpi->cpi_std[4]. 2093d129bde2Sesaxe */ 2094d129bde2Sesaxe if (size > 0) { 2095d129bde2Sesaxe cpi->cpi_std_4 = 2096d129bde2Sesaxe kmem_alloc(size * sizeof (cp), KM_SLEEP); 2097d129bde2Sesaxe cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 2098d129bde2Sesaxe 2099d129bde2Sesaxe /* 2100d129bde2Sesaxe * Allocate storage to hold the additional regs 2101d129bde2Sesaxe * for function 4, %ecx == 1 .. cpi_std_4_size. 2102d129bde2Sesaxe * 2103d129bde2Sesaxe * The regs for fn 4, %ecx == 0 has already 2104d129bde2Sesaxe * been allocated as indicated above. 2105d129bde2Sesaxe */ 2106d129bde2Sesaxe for (i = 1; i < size; i++) { 2107d129bde2Sesaxe cp = cpi->cpi_std_4[i] = 2108d129bde2Sesaxe kmem_zalloc(sizeof (regs), KM_SLEEP); 2109d129bde2Sesaxe cp->cp_eax = 4; 2110d129bde2Sesaxe cp->cp_ecx = i; 2111d129bde2Sesaxe 2112d129bde2Sesaxe (void) __cpuid_insn(cp); 2113d129bde2Sesaxe } 2114d129bde2Sesaxe } 2115d129bde2Sesaxe /* 2116d129bde2Sesaxe * Determine the number of bits needed to represent 2117d129bde2Sesaxe * the number of CPUs sharing the last level cache. 2118d129bde2Sesaxe * 2119d129bde2Sesaxe * Shift off that number of bits from the APIC id to 2120d129bde2Sesaxe * derive the cache id. 2121d129bde2Sesaxe */ 2122d129bde2Sesaxe shft = 0; 2123d129bde2Sesaxe for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 2124d129bde2Sesaxe shft++; 2125b6917abeSmishra cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 2126d129bde2Sesaxe } 2127d129bde2Sesaxe 2128d129bde2Sesaxe /* 2129d129bde2Sesaxe * Now fixup the brand string 2130d129bde2Sesaxe */ 21317c478bd9Sstevel@tonic-gate if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 21327c478bd9Sstevel@tonic-gate fabricate_brandstr(cpi); 2133d129bde2Sesaxe } else { 21347c478bd9Sstevel@tonic-gate 21357c478bd9Sstevel@tonic-gate /* 21367c478bd9Sstevel@tonic-gate * If we successfully extracted a brand string from the cpuid 21377c478bd9Sstevel@tonic-gate * instruction, clean it up by removing leading spaces and 21387c478bd9Sstevel@tonic-gate * similar junk. 21397c478bd9Sstevel@tonic-gate */ 21407c478bd9Sstevel@tonic-gate if (cpi->cpi_brandstr[0]) { 21417c478bd9Sstevel@tonic-gate size_t maxlen = sizeof (cpi->cpi_brandstr); 21427c478bd9Sstevel@tonic-gate char *src, *dst; 21437c478bd9Sstevel@tonic-gate 21447c478bd9Sstevel@tonic-gate dst = src = (char *)cpi->cpi_brandstr; 21457c478bd9Sstevel@tonic-gate src[maxlen - 1] = '\0'; 21467c478bd9Sstevel@tonic-gate /* 21477c478bd9Sstevel@tonic-gate * strip leading spaces 21487c478bd9Sstevel@tonic-gate */ 21497c478bd9Sstevel@tonic-gate while (*src == ' ') 21507c478bd9Sstevel@tonic-gate src++; 21517c478bd9Sstevel@tonic-gate /* 21527c478bd9Sstevel@tonic-gate * Remove any 'Genuine' or "Authentic" prefixes 21537c478bd9Sstevel@tonic-gate */ 21547c478bd9Sstevel@tonic-gate if (strncmp(src, "Genuine ", 8) == 0) 21557c478bd9Sstevel@tonic-gate src += 8; 21567c478bd9Sstevel@tonic-gate if (strncmp(src, "Authentic ", 10) == 0) 21577c478bd9Sstevel@tonic-gate src += 10; 21587c478bd9Sstevel@tonic-gate 21597c478bd9Sstevel@tonic-gate /* 21607c478bd9Sstevel@tonic-gate * Now do an in-place copy. 21617c478bd9Sstevel@tonic-gate * Map (R) to (r) and (TM) to (tm). 21627c478bd9Sstevel@tonic-gate * The era of teletypes is long gone, and there's 21637c478bd9Sstevel@tonic-gate * -really- no need to shout. 21647c478bd9Sstevel@tonic-gate */ 21657c478bd9Sstevel@tonic-gate while (*src != '\0') { 21667c478bd9Sstevel@tonic-gate if (src[0] == '(') { 21677c478bd9Sstevel@tonic-gate if (strncmp(src + 1, "R)", 2) == 0) { 21687c478bd9Sstevel@tonic-gate (void) strncpy(dst, "(r)", 3); 21697c478bd9Sstevel@tonic-gate src += 3; 21707c478bd9Sstevel@tonic-gate dst += 3; 21717c478bd9Sstevel@tonic-gate continue; 21727c478bd9Sstevel@tonic-gate } 21737c478bd9Sstevel@tonic-gate if (strncmp(src + 1, "TM)", 3) == 0) { 21747c478bd9Sstevel@tonic-gate (void) strncpy(dst, "(tm)", 4); 21757c478bd9Sstevel@tonic-gate src += 4; 21767c478bd9Sstevel@tonic-gate dst += 4; 21777c478bd9Sstevel@tonic-gate continue; 21787c478bd9Sstevel@tonic-gate } 21797c478bd9Sstevel@tonic-gate } 21807c478bd9Sstevel@tonic-gate *dst++ = *src++; 21817c478bd9Sstevel@tonic-gate } 21827c478bd9Sstevel@tonic-gate *dst = '\0'; 21837c478bd9Sstevel@tonic-gate 21847c478bd9Sstevel@tonic-gate /* 21857c478bd9Sstevel@tonic-gate * Finally, remove any trailing spaces 21867c478bd9Sstevel@tonic-gate */ 21877c478bd9Sstevel@tonic-gate while (--dst > cpi->cpi_brandstr) 21887c478bd9Sstevel@tonic-gate if (*dst == ' ') 21897c478bd9Sstevel@tonic-gate *dst = '\0'; 21907c478bd9Sstevel@tonic-gate else 21917c478bd9Sstevel@tonic-gate break; 21927c478bd9Sstevel@tonic-gate } else 21937c478bd9Sstevel@tonic-gate fabricate_brandstr(cpi); 2194d129bde2Sesaxe } 21957c478bd9Sstevel@tonic-gate cpi->cpi_pass = 3; 21967c478bd9Sstevel@tonic-gate } 21977c478bd9Sstevel@tonic-gate 21987c478bd9Sstevel@tonic-gate /* 21997c478bd9Sstevel@tonic-gate * This routine is called out of bind_hwcap() much later in the life 22007c478bd9Sstevel@tonic-gate * of the kernel (post_startup()). The job of this routine is to resolve 22017c478bd9Sstevel@tonic-gate * the hardware feature support and kernel support for those features into 22027c478bd9Sstevel@tonic-gate * what we're actually going to tell applications via the aux vector. 22037c478bd9Sstevel@tonic-gate */ 22047c478bd9Sstevel@tonic-gate uint_t 22057c478bd9Sstevel@tonic-gate cpuid_pass4(cpu_t *cpu) 22067c478bd9Sstevel@tonic-gate { 22077c478bd9Sstevel@tonic-gate struct cpuid_info *cpi; 22087c478bd9Sstevel@tonic-gate uint_t hwcap_flags = 0; 22097c478bd9Sstevel@tonic-gate 22107c478bd9Sstevel@tonic-gate if (cpu == NULL) 22117c478bd9Sstevel@tonic-gate cpu = CPU; 22127c478bd9Sstevel@tonic-gate cpi = cpu->cpu_m.mcpu_cpi; 22137c478bd9Sstevel@tonic-gate 22147c478bd9Sstevel@tonic-gate ASSERT(cpi->cpi_pass == 3); 22157c478bd9Sstevel@tonic-gate 22167c478bd9Sstevel@tonic-gate if (cpi->cpi_maxeax >= 1) { 22177c478bd9Sstevel@tonic-gate uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 22187c478bd9Sstevel@tonic-gate uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 22197c478bd9Sstevel@tonic-gate 22207c478bd9Sstevel@tonic-gate *edx = CPI_FEATURES_EDX(cpi); 22217c478bd9Sstevel@tonic-gate *ecx = CPI_FEATURES_ECX(cpi); 22227c478bd9Sstevel@tonic-gate 22237c478bd9Sstevel@tonic-gate /* 22247c478bd9Sstevel@tonic-gate * [these require explicit kernel support] 22257c478bd9Sstevel@tonic-gate */ 22267c478bd9Sstevel@tonic-gate if ((x86_feature & X86_SEP) == 0) 22277c478bd9Sstevel@tonic-gate *edx &= ~CPUID_INTC_EDX_SEP; 22287c478bd9Sstevel@tonic-gate 22297c478bd9Sstevel@tonic-gate if ((x86_feature & X86_SSE) == 0) 22307c478bd9Sstevel@tonic-gate *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 22317c478bd9Sstevel@tonic-gate if ((x86_feature & X86_SSE2) == 0) 22327c478bd9Sstevel@tonic-gate *edx &= ~CPUID_INTC_EDX_SSE2; 22337c478bd9Sstevel@tonic-gate 22347c478bd9Sstevel@tonic-gate if ((x86_feature & X86_HTT) == 0) 22357c478bd9Sstevel@tonic-gate *edx &= ~CPUID_INTC_EDX_HTT; 22367c478bd9Sstevel@tonic-gate 22377c478bd9Sstevel@tonic-gate if ((x86_feature & X86_SSE3) == 0) 22387c478bd9Sstevel@tonic-gate *ecx &= ~CPUID_INTC_ECX_SSE3; 22397c478bd9Sstevel@tonic-gate 2240d0f8ff6eSkk208521 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2241d0f8ff6eSkk208521 if ((x86_feature & X86_SSSE3) == 0) 2242d0f8ff6eSkk208521 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2243d0f8ff6eSkk208521 if ((x86_feature & X86_SSE4_1) == 0) 2244d0f8ff6eSkk208521 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2245d0f8ff6eSkk208521 if ((x86_feature & X86_SSE4_2) == 0) 2246d0f8ff6eSkk208521 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2247a50a8b93SKuriakose Kuruvilla if ((x86_feature & X86_AES) == 0) 2248a50a8b93SKuriakose Kuruvilla *ecx &= ~CPUID_INTC_ECX_AES; 2249d0f8ff6eSkk208521 } 2250d0f8ff6eSkk208521 22517c478bd9Sstevel@tonic-gate /* 22527c478bd9Sstevel@tonic-gate * [no explicit support required beyond x87 fp context] 22537c478bd9Sstevel@tonic-gate */ 22547c478bd9Sstevel@tonic-gate if (!fpu_exists) 22557c478bd9Sstevel@tonic-gate *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 22567c478bd9Sstevel@tonic-gate 22577c478bd9Sstevel@tonic-gate /* 22587c478bd9Sstevel@tonic-gate * Now map the supported feature vector to things that we 22597c478bd9Sstevel@tonic-gate * think userland will care about. 22607c478bd9Sstevel@tonic-gate */ 22617c478bd9Sstevel@tonic-gate if (*edx & CPUID_INTC_EDX_SEP) 22627c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_SEP; 22637c478bd9Sstevel@tonic-gate if (*edx & CPUID_INTC_EDX_SSE) 22647c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_FXSR | AV_386_SSE; 22657c478bd9Sstevel@tonic-gate if (*edx & CPUID_INTC_EDX_SSE2) 22667c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_SSE2; 22677c478bd9Sstevel@tonic-gate if (*ecx & CPUID_INTC_ECX_SSE3) 22687c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_SSE3; 2269d0f8ff6eSkk208521 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2270d0f8ff6eSkk208521 if (*ecx & CPUID_INTC_ECX_SSSE3) 2271d0f8ff6eSkk208521 hwcap_flags |= AV_386_SSSE3; 2272d0f8ff6eSkk208521 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2273d0f8ff6eSkk208521 hwcap_flags |= AV_386_SSE4_1; 2274d0f8ff6eSkk208521 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2275d0f8ff6eSkk208521 hwcap_flags |= AV_386_SSE4_2; 22765087e485SKrishnendu Sadhukhan - Sun Microsystems if (*ecx & CPUID_INTC_ECX_MOVBE) 22775087e485SKrishnendu Sadhukhan - Sun Microsystems hwcap_flags |= AV_386_MOVBE; 2278a50a8b93SKuriakose Kuruvilla if (*ecx & CPUID_INTC_ECX_AES) 2279a50a8b93SKuriakose Kuruvilla hwcap_flags |= AV_386_AES; 2280a50a8b93SKuriakose Kuruvilla if (*ecx & CPUID_INTC_ECX_PCLMULQDQ) 2281a50a8b93SKuriakose Kuruvilla hwcap_flags |= AV_386_PCLMULQDQ; 2282d0f8ff6eSkk208521 } 2283f8801251Skk208521 if (*ecx & CPUID_INTC_ECX_POPCNT) 2284f8801251Skk208521 hwcap_flags |= AV_386_POPCNT; 22857c478bd9Sstevel@tonic-gate if (*edx & CPUID_INTC_EDX_FPU) 22867c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_FPU; 22877c478bd9Sstevel@tonic-gate if (*edx & CPUID_INTC_EDX_MMX) 22887c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_MMX; 22897c478bd9Sstevel@tonic-gate 22907c478bd9Sstevel@tonic-gate if (*edx & CPUID_INTC_EDX_TSC) 22917c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_TSC; 22927c478bd9Sstevel@tonic-gate if (*edx & CPUID_INTC_EDX_CX8) 22937c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_CX8; 22947c478bd9Sstevel@tonic-gate if (*edx & CPUID_INTC_EDX_CMOV) 22957c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_CMOV; 22967c478bd9Sstevel@tonic-gate if (*ecx & CPUID_INTC_ECX_CX16) 22977c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_CX16; 22987c478bd9Sstevel@tonic-gate } 22997c478bd9Sstevel@tonic-gate 23007c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax < 0x80000001) 23017c478bd9Sstevel@tonic-gate goto pass4_done; 23027c478bd9Sstevel@tonic-gate 23037c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 23048949bcd6Sandrei struct cpuid_regs cp; 2305ae115bc7Smrj uint32_t *edx, *ecx; 23067c478bd9Sstevel@tonic-gate 2307ae115bc7Smrj case X86_VENDOR_Intel: 2308ae115bc7Smrj /* 2309ae115bc7Smrj * Seems like Intel duplicated what we necessary 2310ae115bc7Smrj * here to make the initial crop of 64-bit OS's work. 2311ae115bc7Smrj * Hopefully, those are the only "extended" bits 2312ae115bc7Smrj * they'll add. 2313ae115bc7Smrj */ 2314ae115bc7Smrj /*FALLTHROUGH*/ 2315ae115bc7Smrj 23167c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 23177c478bd9Sstevel@tonic-gate edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2318ae115bc7Smrj ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 23197c478bd9Sstevel@tonic-gate 23207c478bd9Sstevel@tonic-gate *edx = CPI_FEATURES_XTD_EDX(cpi); 2321ae115bc7Smrj *ecx = CPI_FEATURES_XTD_ECX(cpi); 2322ae115bc7Smrj 2323ae115bc7Smrj /* 2324ae115bc7Smrj * [these features require explicit kernel support] 2325ae115bc7Smrj */ 2326ae115bc7Smrj switch (cpi->cpi_vendor) { 2327ae115bc7Smrj case X86_VENDOR_Intel: 2328d36ea5d8Ssudheer if ((x86_feature & X86_TSCP) == 0) 2329d36ea5d8Ssudheer *edx &= ~CPUID_AMD_EDX_TSCP; 2330ae115bc7Smrj break; 2331ae115bc7Smrj 2332ae115bc7Smrj case X86_VENDOR_AMD: 2333ae115bc7Smrj if ((x86_feature & X86_TSCP) == 0) 2334ae115bc7Smrj *edx &= ~CPUID_AMD_EDX_TSCP; 2335f8801251Skk208521 if ((x86_feature & X86_SSE4A) == 0) 2336f8801251Skk208521 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2337ae115bc7Smrj break; 2338ae115bc7Smrj 2339ae115bc7Smrj default: 2340ae115bc7Smrj break; 2341ae115bc7Smrj } 23427c478bd9Sstevel@tonic-gate 23437c478bd9Sstevel@tonic-gate /* 23447c478bd9Sstevel@tonic-gate * [no explicit support required beyond 23457c478bd9Sstevel@tonic-gate * x87 fp context and exception handlers] 23467c478bd9Sstevel@tonic-gate */ 23477c478bd9Sstevel@tonic-gate if (!fpu_exists) 23487c478bd9Sstevel@tonic-gate *edx &= ~(CPUID_AMD_EDX_MMXamd | 23497c478bd9Sstevel@tonic-gate CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 23507c478bd9Sstevel@tonic-gate 23517c478bd9Sstevel@tonic-gate if ((x86_feature & X86_NX) == 0) 23527c478bd9Sstevel@tonic-gate *edx &= ~CPUID_AMD_EDX_NX; 2353ae115bc7Smrj #if !defined(__amd64) 23547c478bd9Sstevel@tonic-gate *edx &= ~CPUID_AMD_EDX_LM; 23557c478bd9Sstevel@tonic-gate #endif 23567c478bd9Sstevel@tonic-gate /* 23577c478bd9Sstevel@tonic-gate * Now map the supported feature vector to 23587c478bd9Sstevel@tonic-gate * things that we think userland will care about. 23597c478bd9Sstevel@tonic-gate */ 2360ae115bc7Smrj #if defined(__amd64) 23617c478bd9Sstevel@tonic-gate if (*edx & CPUID_AMD_EDX_SYSC) 23627c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_AMD_SYSC; 2363ae115bc7Smrj #endif 23647c478bd9Sstevel@tonic-gate if (*edx & CPUID_AMD_EDX_MMXamd) 23657c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_AMD_MMX; 23667c478bd9Sstevel@tonic-gate if (*edx & CPUID_AMD_EDX_3DNow) 23677c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_AMD_3DNow; 23687c478bd9Sstevel@tonic-gate if (*edx & CPUID_AMD_EDX_3DNowx) 23697c478bd9Sstevel@tonic-gate hwcap_flags |= AV_386_AMD_3DNowx; 2370ae115bc7Smrj 2371ae115bc7Smrj switch (cpi->cpi_vendor) { 2372ae115bc7Smrj case X86_VENDOR_AMD: 2373ae115bc7Smrj if (*edx & CPUID_AMD_EDX_TSCP) 2374ae115bc7Smrj hwcap_flags |= AV_386_TSCP; 2375ae115bc7Smrj if (*ecx & CPUID_AMD_ECX_AHF64) 2376ae115bc7Smrj hwcap_flags |= AV_386_AHF; 2377f8801251Skk208521 if (*ecx & CPUID_AMD_ECX_SSE4A) 2378f8801251Skk208521 hwcap_flags |= AV_386_AMD_SSE4A; 2379f8801251Skk208521 if (*ecx & CPUID_AMD_ECX_LZCNT) 2380f8801251Skk208521 hwcap_flags |= AV_386_AMD_LZCNT; 2381ae115bc7Smrj break; 2382ae115bc7Smrj 2383ae115bc7Smrj case X86_VENDOR_Intel: 2384d36ea5d8Ssudheer if (*edx & CPUID_AMD_EDX_TSCP) 2385d36ea5d8Ssudheer hwcap_flags |= AV_386_TSCP; 2386ae115bc7Smrj /* 2387ae115bc7Smrj * Aarrgh. 2388ae115bc7Smrj * Intel uses a different bit in the same word. 2389ae115bc7Smrj */ 2390ae115bc7Smrj if (*ecx & CPUID_INTC_ECX_AHF64) 2391ae115bc7Smrj hwcap_flags |= AV_386_AHF; 2392ae115bc7Smrj break; 2393ae115bc7Smrj 2394ae115bc7Smrj default: 2395ae115bc7Smrj break; 2396ae115bc7Smrj } 23977c478bd9Sstevel@tonic-gate break; 23987c478bd9Sstevel@tonic-gate 23997c478bd9Sstevel@tonic-gate case X86_VENDOR_TM: 24008949bcd6Sandrei cp.cp_eax = 0x80860001; 24018949bcd6Sandrei (void) __cpuid_insn(&cp); 24028949bcd6Sandrei cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 24037c478bd9Sstevel@tonic-gate break; 24047c478bd9Sstevel@tonic-gate 24057c478bd9Sstevel@tonic-gate default: 24067c478bd9Sstevel@tonic-gate break; 24077c478bd9Sstevel@tonic-gate } 24087c478bd9Sstevel@tonic-gate 24097c478bd9Sstevel@tonic-gate pass4_done: 24107c478bd9Sstevel@tonic-gate cpi->cpi_pass = 4; 24117c478bd9Sstevel@tonic-gate return (hwcap_flags); 24127c478bd9Sstevel@tonic-gate } 24137c478bd9Sstevel@tonic-gate 24147c478bd9Sstevel@tonic-gate 24157c478bd9Sstevel@tonic-gate /* 24167c478bd9Sstevel@tonic-gate * Simulate the cpuid instruction using the data we previously 24177c478bd9Sstevel@tonic-gate * captured about this CPU. We try our best to return the truth 24187c478bd9Sstevel@tonic-gate * about the hardware, independently of kernel support. 24197c478bd9Sstevel@tonic-gate */ 24207c478bd9Sstevel@tonic-gate uint32_t 24218949bcd6Sandrei cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 24227c478bd9Sstevel@tonic-gate { 24237c478bd9Sstevel@tonic-gate struct cpuid_info *cpi; 24248949bcd6Sandrei struct cpuid_regs *xcp; 24257c478bd9Sstevel@tonic-gate 24267c478bd9Sstevel@tonic-gate if (cpu == NULL) 24277c478bd9Sstevel@tonic-gate cpu = CPU; 24287c478bd9Sstevel@tonic-gate cpi = cpu->cpu_m.mcpu_cpi; 24297c478bd9Sstevel@tonic-gate 24307c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 3)); 24317c478bd9Sstevel@tonic-gate 24327c478bd9Sstevel@tonic-gate /* 24337c478bd9Sstevel@tonic-gate * CPUID data is cached in two separate places: cpi_std for standard 24347c478bd9Sstevel@tonic-gate * CPUID functions, and cpi_extd for extended CPUID functions. 24357c478bd9Sstevel@tonic-gate */ 24368949bcd6Sandrei if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 24378949bcd6Sandrei xcp = &cpi->cpi_std[cp->cp_eax]; 24388949bcd6Sandrei else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 24398949bcd6Sandrei cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 24408949bcd6Sandrei xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 24417c478bd9Sstevel@tonic-gate else 24427c478bd9Sstevel@tonic-gate /* 24437c478bd9Sstevel@tonic-gate * The caller is asking for data from an input parameter which 24447c478bd9Sstevel@tonic-gate * the kernel has not cached. In this case we go fetch from 24457c478bd9Sstevel@tonic-gate * the hardware and return the data directly to the user. 24467c478bd9Sstevel@tonic-gate */ 24478949bcd6Sandrei return (__cpuid_insn(cp)); 24488949bcd6Sandrei 24498949bcd6Sandrei cp->cp_eax = xcp->cp_eax; 24508949bcd6Sandrei cp->cp_ebx = xcp->cp_ebx; 24518949bcd6Sandrei cp->cp_ecx = xcp->cp_ecx; 24528949bcd6Sandrei cp->cp_edx = xcp->cp_edx; 24537c478bd9Sstevel@tonic-gate return (cp->cp_eax); 24547c478bd9Sstevel@tonic-gate } 24557c478bd9Sstevel@tonic-gate 24567c478bd9Sstevel@tonic-gate int 24577c478bd9Sstevel@tonic-gate cpuid_checkpass(cpu_t *cpu, int pass) 24587c478bd9Sstevel@tonic-gate { 24597c478bd9Sstevel@tonic-gate return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 24607c478bd9Sstevel@tonic-gate cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 24617c478bd9Sstevel@tonic-gate } 24627c478bd9Sstevel@tonic-gate 24637c478bd9Sstevel@tonic-gate int 24647c478bd9Sstevel@tonic-gate cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 24657c478bd9Sstevel@tonic-gate { 24667c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 3)); 24677c478bd9Sstevel@tonic-gate 24687c478bd9Sstevel@tonic-gate return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 24697c478bd9Sstevel@tonic-gate } 24707c478bd9Sstevel@tonic-gate 24717c478bd9Sstevel@tonic-gate int 24728949bcd6Sandrei cpuid_is_cmt(cpu_t *cpu) 24737c478bd9Sstevel@tonic-gate { 24747c478bd9Sstevel@tonic-gate if (cpu == NULL) 24757c478bd9Sstevel@tonic-gate cpu = CPU; 24767c478bd9Sstevel@tonic-gate 24777c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 24787c478bd9Sstevel@tonic-gate 24797c478bd9Sstevel@tonic-gate return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 24807c478bd9Sstevel@tonic-gate } 24817c478bd9Sstevel@tonic-gate 24827c478bd9Sstevel@tonic-gate /* 24837c478bd9Sstevel@tonic-gate * AMD and Intel both implement the 64-bit variant of the syscall 24847c478bd9Sstevel@tonic-gate * instruction (syscallq), so if there's -any- support for syscall, 24857c478bd9Sstevel@tonic-gate * cpuid currently says "yes, we support this". 24867c478bd9Sstevel@tonic-gate * 24877c478bd9Sstevel@tonic-gate * However, Intel decided to -not- implement the 32-bit variant of the 24887c478bd9Sstevel@tonic-gate * syscall instruction, so we provide a predicate to allow our caller 24897c478bd9Sstevel@tonic-gate * to test that subtlety here. 2490843e1988Sjohnlev * 2491843e1988Sjohnlev * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2492843e1988Sjohnlev * even in the case where the hardware would in fact support it. 24937c478bd9Sstevel@tonic-gate */ 24947c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 24957c478bd9Sstevel@tonic-gate int 24967c478bd9Sstevel@tonic-gate cpuid_syscall32_insn(cpu_t *cpu) 24977c478bd9Sstevel@tonic-gate { 24987c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 24997c478bd9Sstevel@tonic-gate 2500843e1988Sjohnlev #if !defined(__xpv) 2501ae115bc7Smrj if (cpu == NULL) 2502ae115bc7Smrj cpu = CPU; 2503ae115bc7Smrj 2504ae115bc7Smrj /*CSTYLED*/ 2505ae115bc7Smrj { 2506ae115bc7Smrj struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2507ae115bc7Smrj 2508ae115bc7Smrj if (cpi->cpi_vendor == X86_VENDOR_AMD && 2509ae115bc7Smrj cpi->cpi_xmaxeax >= 0x80000001 && 2510ae115bc7Smrj (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2511ae115bc7Smrj return (1); 2512ae115bc7Smrj } 2513843e1988Sjohnlev #endif 25147c478bd9Sstevel@tonic-gate return (0); 25157c478bd9Sstevel@tonic-gate } 25167c478bd9Sstevel@tonic-gate 25177c478bd9Sstevel@tonic-gate int 25187c478bd9Sstevel@tonic-gate cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 25197c478bd9Sstevel@tonic-gate { 25207c478bd9Sstevel@tonic-gate struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 25217c478bd9Sstevel@tonic-gate 25227c478bd9Sstevel@tonic-gate static const char fmt[] = 2523ecfa43a5Sdmick "x86 (%s %X family %d model %d step %d clock %d MHz)"; 25247c478bd9Sstevel@tonic-gate static const char fmt_ht[] = 2525ecfa43a5Sdmick "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 25267c478bd9Sstevel@tonic-gate 25277c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 25287c478bd9Sstevel@tonic-gate 25298949bcd6Sandrei if (cpuid_is_cmt(cpu)) 25307c478bd9Sstevel@tonic-gate return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2531ecfa43a5Sdmick cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2532ecfa43a5Sdmick cpi->cpi_family, cpi->cpi_model, 25337c478bd9Sstevel@tonic-gate cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 25347c478bd9Sstevel@tonic-gate return (snprintf(s, n, fmt, 2535ecfa43a5Sdmick cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2536ecfa43a5Sdmick cpi->cpi_family, cpi->cpi_model, 25377c478bd9Sstevel@tonic-gate cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 25387c478bd9Sstevel@tonic-gate } 25397c478bd9Sstevel@tonic-gate 25407c478bd9Sstevel@tonic-gate const char * 25417c478bd9Sstevel@tonic-gate cpuid_getvendorstr(cpu_t *cpu) 25427c478bd9Sstevel@tonic-gate { 25437c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 25447c478bd9Sstevel@tonic-gate return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 25457c478bd9Sstevel@tonic-gate } 25467c478bd9Sstevel@tonic-gate 25477c478bd9Sstevel@tonic-gate uint_t 25487c478bd9Sstevel@tonic-gate cpuid_getvendor(cpu_t *cpu) 25497c478bd9Sstevel@tonic-gate { 25507c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 25517c478bd9Sstevel@tonic-gate return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 25527c478bd9Sstevel@tonic-gate } 25537c478bd9Sstevel@tonic-gate 25547c478bd9Sstevel@tonic-gate uint_t 25557c478bd9Sstevel@tonic-gate cpuid_getfamily(cpu_t *cpu) 25567c478bd9Sstevel@tonic-gate { 25577c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 25587c478bd9Sstevel@tonic-gate return (cpu->cpu_m.mcpu_cpi->cpi_family); 25597c478bd9Sstevel@tonic-gate } 25607c478bd9Sstevel@tonic-gate 25617c478bd9Sstevel@tonic-gate uint_t 25627c478bd9Sstevel@tonic-gate cpuid_getmodel(cpu_t *cpu) 25637c478bd9Sstevel@tonic-gate { 25647c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 25657c478bd9Sstevel@tonic-gate return (cpu->cpu_m.mcpu_cpi->cpi_model); 25667c478bd9Sstevel@tonic-gate } 25677c478bd9Sstevel@tonic-gate 25687c478bd9Sstevel@tonic-gate uint_t 25697c478bd9Sstevel@tonic-gate cpuid_get_ncpu_per_chip(cpu_t *cpu) 25707c478bd9Sstevel@tonic-gate { 25717c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 25727c478bd9Sstevel@tonic-gate return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 25737c478bd9Sstevel@tonic-gate } 25747c478bd9Sstevel@tonic-gate 25757c478bd9Sstevel@tonic-gate uint_t 25768949bcd6Sandrei cpuid_get_ncore_per_chip(cpu_t *cpu) 25778949bcd6Sandrei { 25788949bcd6Sandrei ASSERT(cpuid_checkpass(cpu, 1)); 25798949bcd6Sandrei return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 25808949bcd6Sandrei } 25818949bcd6Sandrei 25828949bcd6Sandrei uint_t 2583d129bde2Sesaxe cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2584d129bde2Sesaxe { 2585d129bde2Sesaxe ASSERT(cpuid_checkpass(cpu, 2)); 2586d129bde2Sesaxe return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2587d129bde2Sesaxe } 2588d129bde2Sesaxe 2589d129bde2Sesaxe id_t 2590d129bde2Sesaxe cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2591d129bde2Sesaxe { 2592d129bde2Sesaxe ASSERT(cpuid_checkpass(cpu, 2)); 2593d129bde2Sesaxe return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2594d129bde2Sesaxe } 2595d129bde2Sesaxe 2596d129bde2Sesaxe uint_t 25977c478bd9Sstevel@tonic-gate cpuid_getstep(cpu_t *cpu) 25987c478bd9Sstevel@tonic-gate { 25997c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 26007c478bd9Sstevel@tonic-gate return (cpu->cpu_m.mcpu_cpi->cpi_step); 26017c478bd9Sstevel@tonic-gate } 26027c478bd9Sstevel@tonic-gate 26032449e17fSsherrym uint_t 26042449e17fSsherrym cpuid_getsig(struct cpu *cpu) 26052449e17fSsherrym { 26062449e17fSsherrym ASSERT(cpuid_checkpass(cpu, 1)); 26072449e17fSsherrym return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 26082449e17fSsherrym } 26092449e17fSsherrym 26108a40a695Sgavinm uint32_t 26118a40a695Sgavinm cpuid_getchiprev(struct cpu *cpu) 26128a40a695Sgavinm { 26138a40a695Sgavinm ASSERT(cpuid_checkpass(cpu, 1)); 26148a40a695Sgavinm return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 26158a40a695Sgavinm } 26168a40a695Sgavinm 26178a40a695Sgavinm const char * 26188a40a695Sgavinm cpuid_getchiprevstr(struct cpu *cpu) 26198a40a695Sgavinm { 26208a40a695Sgavinm ASSERT(cpuid_checkpass(cpu, 1)); 26218a40a695Sgavinm return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 26228a40a695Sgavinm } 26238a40a695Sgavinm 26248a40a695Sgavinm uint32_t 26258a40a695Sgavinm cpuid_getsockettype(struct cpu *cpu) 26268a40a695Sgavinm { 26278a40a695Sgavinm ASSERT(cpuid_checkpass(cpu, 1)); 26288a40a695Sgavinm return (cpu->cpu_m.mcpu_cpi->cpi_socket); 26298a40a695Sgavinm } 26308a40a695Sgavinm 263189e921d5SKuriakose Kuruvilla const char * 263289e921d5SKuriakose Kuruvilla cpuid_getsocketstr(cpu_t *cpu) 263389e921d5SKuriakose Kuruvilla { 263489e921d5SKuriakose Kuruvilla static const char *socketstr = NULL; 263589e921d5SKuriakose Kuruvilla struct cpuid_info *cpi; 263689e921d5SKuriakose Kuruvilla 263789e921d5SKuriakose Kuruvilla ASSERT(cpuid_checkpass(cpu, 1)); 263889e921d5SKuriakose Kuruvilla cpi = cpu->cpu_m.mcpu_cpi; 263989e921d5SKuriakose Kuruvilla 264089e921d5SKuriakose Kuruvilla /* Assume that socket types are the same across the system */ 264189e921d5SKuriakose Kuruvilla if (socketstr == NULL) 264289e921d5SKuriakose Kuruvilla socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family, 264389e921d5SKuriakose Kuruvilla cpi->cpi_model, cpi->cpi_step); 264489e921d5SKuriakose Kuruvilla 264589e921d5SKuriakose Kuruvilla 264689e921d5SKuriakose Kuruvilla return (socketstr); 264789e921d5SKuriakose Kuruvilla } 264889e921d5SKuriakose Kuruvilla 2649fb2f18f8Sesaxe int 2650fb2f18f8Sesaxe cpuid_get_chipid(cpu_t *cpu) 26517c478bd9Sstevel@tonic-gate { 26527c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 26537c478bd9Sstevel@tonic-gate 26548949bcd6Sandrei if (cpuid_is_cmt(cpu)) 26557c478bd9Sstevel@tonic-gate return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 26567c478bd9Sstevel@tonic-gate return (cpu->cpu_id); 26577c478bd9Sstevel@tonic-gate } 26587c478bd9Sstevel@tonic-gate 26598949bcd6Sandrei id_t 2660fb2f18f8Sesaxe cpuid_get_coreid(cpu_t *cpu) 26618949bcd6Sandrei { 26628949bcd6Sandrei ASSERT(cpuid_checkpass(cpu, 1)); 26638949bcd6Sandrei return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 26648949bcd6Sandrei } 26658949bcd6Sandrei 26667c478bd9Sstevel@tonic-gate int 266710569901Sgavinm cpuid_get_pkgcoreid(cpu_t *cpu) 266810569901Sgavinm { 266910569901Sgavinm ASSERT(cpuid_checkpass(cpu, 1)); 267010569901Sgavinm return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 267110569901Sgavinm } 267210569901Sgavinm 267310569901Sgavinm int 2674fb2f18f8Sesaxe cpuid_get_clogid(cpu_t *cpu) 26757c478bd9Sstevel@tonic-gate { 26767c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 26777c478bd9Sstevel@tonic-gate return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 26787c478bd9Sstevel@tonic-gate } 26797c478bd9Sstevel@tonic-gate 2680b885580bSAlexander Kolbasov int 2681b885580bSAlexander Kolbasov cpuid_get_cacheid(cpu_t *cpu) 2682b885580bSAlexander Kolbasov { 2683b885580bSAlexander Kolbasov ASSERT(cpuid_checkpass(cpu, 1)); 2684b885580bSAlexander Kolbasov return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2685b885580bSAlexander Kolbasov } 2686b885580bSAlexander Kolbasov 26878031591dSSrihari Venkatesan uint_t 26888031591dSSrihari Venkatesan cpuid_get_procnodeid(cpu_t *cpu) 26898031591dSSrihari Venkatesan { 26908031591dSSrihari Venkatesan ASSERT(cpuid_checkpass(cpu, 1)); 26918031591dSSrihari Venkatesan return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid); 26928031591dSSrihari Venkatesan } 26938031591dSSrihari Venkatesan 26948031591dSSrihari Venkatesan uint_t 26958031591dSSrihari Venkatesan cpuid_get_procnodes_per_pkg(cpu_t *cpu) 26968031591dSSrihari Venkatesan { 26978031591dSSrihari Venkatesan ASSERT(cpuid_checkpass(cpu, 1)); 26988031591dSSrihari Venkatesan return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg); 26998031591dSSrihari Venkatesan } 27008031591dSSrihari Venkatesan 27012ef50f01SJoe Bonasera /*ARGSUSED*/ 27022ef50f01SJoe Bonasera int 27032ef50f01SJoe Bonasera cpuid_have_cr8access(cpu_t *cpu) 27042ef50f01SJoe Bonasera { 27052ef50f01SJoe Bonasera #if defined(__amd64) 27062ef50f01SJoe Bonasera return (1); 27072ef50f01SJoe Bonasera #else 27082ef50f01SJoe Bonasera struct cpuid_info *cpi; 27092ef50f01SJoe Bonasera 27102ef50f01SJoe Bonasera ASSERT(cpu != NULL); 27112ef50f01SJoe Bonasera cpi = cpu->cpu_m.mcpu_cpi; 27122ef50f01SJoe Bonasera if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 && 27132ef50f01SJoe Bonasera (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0) 27142ef50f01SJoe Bonasera return (1); 27152ef50f01SJoe Bonasera return (0); 27162ef50f01SJoe Bonasera #endif 27172ef50f01SJoe Bonasera } 27182ef50f01SJoe Bonasera 2719fa96bd91SMichael Corcoran uint32_t 2720fa96bd91SMichael Corcoran cpuid_get_apicid(cpu_t *cpu) 2721fa96bd91SMichael Corcoran { 2722fa96bd91SMichael Corcoran ASSERT(cpuid_checkpass(cpu, 1)); 2723fa96bd91SMichael Corcoran if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) { 2724fa96bd91SMichael Corcoran return (UINT32_MAX); 2725fa96bd91SMichael Corcoran } else { 2726fa96bd91SMichael Corcoran return (cpu->cpu_m.mcpu_cpi->cpi_apicid); 2727fa96bd91SMichael Corcoran } 2728fa96bd91SMichael Corcoran } 2729fa96bd91SMichael Corcoran 27307c478bd9Sstevel@tonic-gate void 27317c478bd9Sstevel@tonic-gate cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 27327c478bd9Sstevel@tonic-gate { 27337c478bd9Sstevel@tonic-gate struct cpuid_info *cpi; 27347c478bd9Sstevel@tonic-gate 27357c478bd9Sstevel@tonic-gate if (cpu == NULL) 27367c478bd9Sstevel@tonic-gate cpu = CPU; 27377c478bd9Sstevel@tonic-gate cpi = cpu->cpu_m.mcpu_cpi; 27387c478bd9Sstevel@tonic-gate 27397c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 27407c478bd9Sstevel@tonic-gate 27417c478bd9Sstevel@tonic-gate if (pabits) 27427c478bd9Sstevel@tonic-gate *pabits = cpi->cpi_pabits; 27437c478bd9Sstevel@tonic-gate if (vabits) 27447c478bd9Sstevel@tonic-gate *vabits = cpi->cpi_vabits; 27457c478bd9Sstevel@tonic-gate } 27467c478bd9Sstevel@tonic-gate 27477c478bd9Sstevel@tonic-gate /* 27487c478bd9Sstevel@tonic-gate * Returns the number of data TLB entries for a corresponding 27497c478bd9Sstevel@tonic-gate * pagesize. If it can't be computed, or isn't known, the 27507c478bd9Sstevel@tonic-gate * routine returns zero. If you ask about an architecturally 27517c478bd9Sstevel@tonic-gate * impossible pagesize, the routine will panic (so that the 27527c478bd9Sstevel@tonic-gate * hat implementor knows that things are inconsistent.) 27537c478bd9Sstevel@tonic-gate */ 27547c478bd9Sstevel@tonic-gate uint_t 27557c478bd9Sstevel@tonic-gate cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 27567c478bd9Sstevel@tonic-gate { 27577c478bd9Sstevel@tonic-gate struct cpuid_info *cpi; 27587c478bd9Sstevel@tonic-gate uint_t dtlb_nent = 0; 27597c478bd9Sstevel@tonic-gate 27607c478bd9Sstevel@tonic-gate if (cpu == NULL) 27617c478bd9Sstevel@tonic-gate cpu = CPU; 27627c478bd9Sstevel@tonic-gate cpi = cpu->cpu_m.mcpu_cpi; 27637c478bd9Sstevel@tonic-gate 27647c478bd9Sstevel@tonic-gate ASSERT(cpuid_checkpass(cpu, 1)); 27657c478bd9Sstevel@tonic-gate 27667c478bd9Sstevel@tonic-gate /* 27677c478bd9Sstevel@tonic-gate * Check the L2 TLB info 27687c478bd9Sstevel@tonic-gate */ 27697c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax >= 0x80000006) { 27708949bcd6Sandrei struct cpuid_regs *cp = &cpi->cpi_extd[6]; 27717c478bd9Sstevel@tonic-gate 27727c478bd9Sstevel@tonic-gate switch (pagesize) { 27737c478bd9Sstevel@tonic-gate 27747c478bd9Sstevel@tonic-gate case 4 * 1024: 27757c478bd9Sstevel@tonic-gate /* 27767c478bd9Sstevel@tonic-gate * All zero in the top 16 bits of the register 27777c478bd9Sstevel@tonic-gate * indicates a unified TLB. Size is in low 16 bits. 27787c478bd9Sstevel@tonic-gate */ 27797c478bd9Sstevel@tonic-gate if ((cp->cp_ebx & 0xffff0000) == 0) 27807c478bd9Sstevel@tonic-gate dtlb_nent = cp->cp_ebx & 0x0000ffff; 27817c478bd9Sstevel@tonic-gate else 27827c478bd9Sstevel@tonic-gate dtlb_nent = BITX(cp->cp_ebx, 27, 16); 27837c478bd9Sstevel@tonic-gate break; 27847c478bd9Sstevel@tonic-gate 27857c478bd9Sstevel@tonic-gate case 2 * 1024 * 1024: 27867c478bd9Sstevel@tonic-gate if ((cp->cp_eax & 0xffff0000) == 0) 27877c478bd9Sstevel@tonic-gate dtlb_nent = cp->cp_eax & 0x0000ffff; 27887c478bd9Sstevel@tonic-gate else 27897c478bd9Sstevel@tonic-gate dtlb_nent = BITX(cp->cp_eax, 27, 16); 27907c478bd9Sstevel@tonic-gate break; 27917c478bd9Sstevel@tonic-gate 27927c478bd9Sstevel@tonic-gate default: 27937c478bd9Sstevel@tonic-gate panic("unknown L2 pagesize"); 27947c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 27957c478bd9Sstevel@tonic-gate } 27967c478bd9Sstevel@tonic-gate } 27977c478bd9Sstevel@tonic-gate 27987c478bd9Sstevel@tonic-gate if (dtlb_nent != 0) 27997c478bd9Sstevel@tonic-gate return (dtlb_nent); 28007c478bd9Sstevel@tonic-gate 28017c478bd9Sstevel@tonic-gate /* 28027c478bd9Sstevel@tonic-gate * No L2 TLB support for this size, try L1. 28037c478bd9Sstevel@tonic-gate */ 28047c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax >= 0x80000005) { 28058949bcd6Sandrei struct cpuid_regs *cp = &cpi->cpi_extd[5]; 28067c478bd9Sstevel@tonic-gate 28077c478bd9Sstevel@tonic-gate switch (pagesize) { 28087c478bd9Sstevel@tonic-gate case 4 * 1024: 28097c478bd9Sstevel@tonic-gate dtlb_nent = BITX(cp->cp_ebx, 23, 16); 28107c478bd9Sstevel@tonic-gate break; 28117c478bd9Sstevel@tonic-gate case 2 * 1024 * 1024: 28127c478bd9Sstevel@tonic-gate dtlb_nent = BITX(cp->cp_eax, 23, 16); 28137c478bd9Sstevel@tonic-gate break; 28147c478bd9Sstevel@tonic-gate default: 28157c478bd9Sstevel@tonic-gate panic("unknown L1 d-TLB pagesize"); 28167c478bd9Sstevel@tonic-gate /*NOTREACHED*/ 28177c478bd9Sstevel@tonic-gate } 28187c478bd9Sstevel@tonic-gate } 28197c478bd9Sstevel@tonic-gate 28207c478bd9Sstevel@tonic-gate return (dtlb_nent); 28217c478bd9Sstevel@tonic-gate } 28227c478bd9Sstevel@tonic-gate 28237c478bd9Sstevel@tonic-gate /* 28247c478bd9Sstevel@tonic-gate * Return 0 if the erratum is not present or not applicable, positive 28257c478bd9Sstevel@tonic-gate * if it is, and negative if the status of the erratum is unknown. 28267c478bd9Sstevel@tonic-gate * 28277c478bd9Sstevel@tonic-gate * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 28282201b277Skucharsk * Processors" #25759, Rev 3.57, August 2005 28297c478bd9Sstevel@tonic-gate */ 28307c478bd9Sstevel@tonic-gate int 28317c478bd9Sstevel@tonic-gate cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 28327c478bd9Sstevel@tonic-gate { 28337c478bd9Sstevel@tonic-gate struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 28348949bcd6Sandrei uint_t eax; 28357c478bd9Sstevel@tonic-gate 2836ea99987eSsethg /* 2837ea99987eSsethg * Bail out if this CPU isn't an AMD CPU, or if it's 2838ea99987eSsethg * a legacy (32-bit) AMD CPU. 2839ea99987eSsethg */ 2840ea99987eSsethg if (cpi->cpi_vendor != X86_VENDOR_AMD || 2841875b116eSkchow cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2842875b116eSkchow cpi->cpi_family == 6) 28438a40a695Sgavinm 28447c478bd9Sstevel@tonic-gate return (0); 28457c478bd9Sstevel@tonic-gate 28467c478bd9Sstevel@tonic-gate eax = cpi->cpi_std[1].cp_eax; 28477c478bd9Sstevel@tonic-gate 28487c478bd9Sstevel@tonic-gate #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 28497c478bd9Sstevel@tonic-gate #define SH_B3(eax) (eax == 0xf51) 2850ee88d2b9Skchow #define B(eax) (SH_B0(eax) || SH_B3(eax)) 28517c478bd9Sstevel@tonic-gate 28527c478bd9Sstevel@tonic-gate #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 28537c478bd9Sstevel@tonic-gate 28547c478bd9Sstevel@tonic-gate #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 28557c478bd9Sstevel@tonic-gate #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 28567c478bd9Sstevel@tonic-gate #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2857ee88d2b9Skchow #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 28587c478bd9Sstevel@tonic-gate 28597c478bd9Sstevel@tonic-gate #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 28607c478bd9Sstevel@tonic-gate #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 28617c478bd9Sstevel@tonic-gate #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2862ee88d2b9Skchow #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 28637c478bd9Sstevel@tonic-gate 28647c478bd9Sstevel@tonic-gate #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 28657c478bd9Sstevel@tonic-gate #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 28667c478bd9Sstevel@tonic-gate #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 28677c478bd9Sstevel@tonic-gate #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 28687c478bd9Sstevel@tonic-gate #define BH_E4(eax) (eax == 0x20fb1) 28697c478bd9Sstevel@tonic-gate #define SH_E5(eax) (eax == 0x20f42) 28707c478bd9Sstevel@tonic-gate #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 28717c478bd9Sstevel@tonic-gate #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2872ee88d2b9Skchow #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2873ee88d2b9Skchow SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2874ee88d2b9Skchow DH_E6(eax) || JH_E6(eax)) 28757c478bd9Sstevel@tonic-gate 2876512cf780Skchow #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 2877512cf780Skchow #define DR_B0(eax) (eax == 0x100f20) 2878512cf780Skchow #define DR_B1(eax) (eax == 0x100f21) 2879512cf780Skchow #define DR_BA(eax) (eax == 0x100f2a) 2880512cf780Skchow #define DR_B2(eax) (eax == 0x100f22) 2881512cf780Skchow #define DR_B3(eax) (eax == 0x100f23) 2882512cf780Skchow #define RB_C0(eax) (eax == 0x100f40) 2883512cf780Skchow 28847c478bd9Sstevel@tonic-gate switch (erratum) { 28857c478bd9Sstevel@tonic-gate case 1: 2886875b116eSkchow return (cpi->cpi_family < 0x10); 28877c478bd9Sstevel@tonic-gate case 51: /* what does the asterisk mean? */ 28887c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax)); 28897c478bd9Sstevel@tonic-gate case 52: 28907c478bd9Sstevel@tonic-gate return (B(eax)); 28917c478bd9Sstevel@tonic-gate case 57: 2892512cf780Skchow return (cpi->cpi_family <= 0x11); 28937c478bd9Sstevel@tonic-gate case 58: 28947c478bd9Sstevel@tonic-gate return (B(eax)); 28957c478bd9Sstevel@tonic-gate case 60: 2896512cf780Skchow return (cpi->cpi_family <= 0x11); 28977c478bd9Sstevel@tonic-gate case 61: 28987c478bd9Sstevel@tonic-gate case 62: 28997c478bd9Sstevel@tonic-gate case 63: 29007c478bd9Sstevel@tonic-gate case 64: 29017c478bd9Sstevel@tonic-gate case 65: 29027c478bd9Sstevel@tonic-gate case 66: 29037c478bd9Sstevel@tonic-gate case 68: 29047c478bd9Sstevel@tonic-gate case 69: 29057c478bd9Sstevel@tonic-gate case 70: 29067c478bd9Sstevel@tonic-gate case 71: 29077c478bd9Sstevel@tonic-gate return (B(eax)); 29087c478bd9Sstevel@tonic-gate case 72: 29097c478bd9Sstevel@tonic-gate return (SH_B0(eax)); 29107c478bd9Sstevel@tonic-gate case 74: 29117c478bd9Sstevel@tonic-gate return (B(eax)); 29127c478bd9Sstevel@tonic-gate case 75: 2913875b116eSkchow return (cpi->cpi_family < 0x10); 29147c478bd9Sstevel@tonic-gate case 76: 29157c478bd9Sstevel@tonic-gate return (B(eax)); 29167c478bd9Sstevel@tonic-gate case 77: 2917512cf780Skchow return (cpi->cpi_family <= 0x11); 29187c478bd9Sstevel@tonic-gate case 78: 29197c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax)); 29207c478bd9Sstevel@tonic-gate case 79: 29217c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 29227c478bd9Sstevel@tonic-gate case 80: 29237c478bd9Sstevel@tonic-gate case 81: 29247c478bd9Sstevel@tonic-gate case 82: 29257c478bd9Sstevel@tonic-gate return (B(eax)); 29267c478bd9Sstevel@tonic-gate case 83: 29277c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax)); 29287c478bd9Sstevel@tonic-gate case 85: 2929875b116eSkchow return (cpi->cpi_family < 0x10); 29307c478bd9Sstevel@tonic-gate case 86: 29317c478bd9Sstevel@tonic-gate return (SH_C0(eax) || CG(eax)); 29327c478bd9Sstevel@tonic-gate case 88: 29337c478bd9Sstevel@tonic-gate #if !defined(__amd64) 29347c478bd9Sstevel@tonic-gate return (0); 29357c478bd9Sstevel@tonic-gate #else 29367c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax)); 29377c478bd9Sstevel@tonic-gate #endif 29387c478bd9Sstevel@tonic-gate case 89: 2939875b116eSkchow return (cpi->cpi_family < 0x10); 29407c478bd9Sstevel@tonic-gate case 90: 29417c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax)); 29427c478bd9Sstevel@tonic-gate case 91: 29437c478bd9Sstevel@tonic-gate case 92: 29447c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax)); 29457c478bd9Sstevel@tonic-gate case 93: 29467c478bd9Sstevel@tonic-gate return (SH_C0(eax)); 29477c478bd9Sstevel@tonic-gate case 94: 29487c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax)); 29497c478bd9Sstevel@tonic-gate case 95: 29507c478bd9Sstevel@tonic-gate #if !defined(__amd64) 29517c478bd9Sstevel@tonic-gate return (0); 29527c478bd9Sstevel@tonic-gate #else 29537c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax)); 29547c478bd9Sstevel@tonic-gate #endif 29557c478bd9Sstevel@tonic-gate case 96: 29567c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax)); 29577c478bd9Sstevel@tonic-gate case 97: 29587c478bd9Sstevel@tonic-gate case 98: 29597c478bd9Sstevel@tonic-gate return (SH_C0(eax) || CG(eax)); 29607c478bd9Sstevel@tonic-gate case 99: 29617c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 29627c478bd9Sstevel@tonic-gate case 100: 29637c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax)); 29647c478bd9Sstevel@tonic-gate case 101: 29657c478bd9Sstevel@tonic-gate case 103: 29667c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 29677c478bd9Sstevel@tonic-gate case 104: 29687c478bd9Sstevel@tonic-gate return (SH_C0(eax) || CG(eax) || D0(eax)); 29697c478bd9Sstevel@tonic-gate case 105: 29707c478bd9Sstevel@tonic-gate case 106: 29717c478bd9Sstevel@tonic-gate case 107: 29727c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 29737c478bd9Sstevel@tonic-gate case 108: 29747c478bd9Sstevel@tonic-gate return (DH_CG(eax)); 29757c478bd9Sstevel@tonic-gate case 109: 29767c478bd9Sstevel@tonic-gate return (SH_C0(eax) || CG(eax) || D0(eax)); 29777c478bd9Sstevel@tonic-gate case 110: 29787c478bd9Sstevel@tonic-gate return (D0(eax) || EX(eax)); 29797c478bd9Sstevel@tonic-gate case 111: 29807c478bd9Sstevel@tonic-gate return (CG(eax)); 29817c478bd9Sstevel@tonic-gate case 112: 29827c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 29837c478bd9Sstevel@tonic-gate case 113: 29847c478bd9Sstevel@tonic-gate return (eax == 0x20fc0); 29857c478bd9Sstevel@tonic-gate case 114: 29867c478bd9Sstevel@tonic-gate return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 29877c478bd9Sstevel@tonic-gate case 115: 29887c478bd9Sstevel@tonic-gate return (SH_E0(eax) || JH_E1(eax)); 29897c478bd9Sstevel@tonic-gate case 116: 29907c478bd9Sstevel@tonic-gate return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 29917c478bd9Sstevel@tonic-gate case 117: 29927c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 29937c478bd9Sstevel@tonic-gate case 118: 29947c478bd9Sstevel@tonic-gate return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 29957c478bd9Sstevel@tonic-gate JH_E6(eax)); 29967c478bd9Sstevel@tonic-gate case 121: 29977c478bd9Sstevel@tonic-gate return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 29987c478bd9Sstevel@tonic-gate case 122: 2999512cf780Skchow return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 30007c478bd9Sstevel@tonic-gate case 123: 30017c478bd9Sstevel@tonic-gate return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 30022201b277Skucharsk case 131: 3003875b116eSkchow return (cpi->cpi_family < 0x10); 3004ef50d8c0Sesaxe case 6336786: 3005ef50d8c0Sesaxe /* 3006ef50d8c0Sesaxe * Test for AdvPowerMgmtInfo.TscPStateInvariant 3007875b116eSkchow * if this is a K8 family or newer processor 3008ef50d8c0Sesaxe */ 3009ef50d8c0Sesaxe if (CPI_FAMILY(cpi) == 0xf) { 30108949bcd6Sandrei struct cpuid_regs regs; 30118949bcd6Sandrei regs.cp_eax = 0x80000007; 30128949bcd6Sandrei (void) __cpuid_insn(®s); 30138949bcd6Sandrei return (!(regs.cp_edx & 0x100)); 3014ef50d8c0Sesaxe } 3015ef50d8c0Sesaxe return (0); 3016ee88d2b9Skchow case 6323525: 3017ee88d2b9Skchow return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 3018ee88d2b9Skchow (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 3019ee88d2b9Skchow 3020512cf780Skchow case 6671130: 3021512cf780Skchow /* 3022512cf780Skchow * check for processors (pre-Shanghai) that do not provide 3023512cf780Skchow * optimal management of 1gb ptes in its tlb. 3024512cf780Skchow */ 3025512cf780Skchow return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 3026512cf780Skchow 3027512cf780Skchow case 298: 3028512cf780Skchow return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 3029512cf780Skchow DR_B2(eax) || RB_C0(eax)); 3030512cf780Skchow 3031512cf780Skchow default: 3032512cf780Skchow return (-1); 3033512cf780Skchow 3034512cf780Skchow } 3035512cf780Skchow } 3036512cf780Skchow 3037512cf780Skchow /* 3038512cf780Skchow * Determine if specified erratum is present via OSVW (OS Visible Workaround). 3039512cf780Skchow * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 3040512cf780Skchow */ 3041512cf780Skchow int 3042512cf780Skchow osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 3043512cf780Skchow { 3044512cf780Skchow struct cpuid_info *cpi; 3045512cf780Skchow uint_t osvwid; 3046512cf780Skchow static int osvwfeature = -1; 3047512cf780Skchow uint64_t osvwlength; 3048512cf780Skchow 3049512cf780Skchow 3050512cf780Skchow cpi = cpu->cpu_m.mcpu_cpi; 3051512cf780Skchow 3052512cf780Skchow /* confirm OSVW supported */ 3053512cf780Skchow if (osvwfeature == -1) { 3054512cf780Skchow osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 3055512cf780Skchow } else { 3056512cf780Skchow /* assert that osvw feature setting is consistent on all cpus */ 3057512cf780Skchow ASSERT(osvwfeature == 3058512cf780Skchow (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 3059512cf780Skchow } 3060512cf780Skchow if (!osvwfeature) 3061512cf780Skchow return (-1); 3062512cf780Skchow 3063512cf780Skchow osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 3064512cf780Skchow 3065512cf780Skchow switch (erratum) { 3066512cf780Skchow case 298: /* osvwid is 0 */ 3067512cf780Skchow osvwid = 0; 3068512cf780Skchow if (osvwlength <= (uint64_t)osvwid) { 3069512cf780Skchow /* osvwid 0 is unknown */ 3070512cf780Skchow return (-1); 3071512cf780Skchow } 3072512cf780Skchow 3073512cf780Skchow /* 3074512cf780Skchow * Check the OSVW STATUS MSR to determine the state 3075512cf780Skchow * of the erratum where: 3076512cf780Skchow * 0 - fixed by HW 3077512cf780Skchow * 1 - BIOS has applied the workaround when BIOS 3078512cf780Skchow * workaround is available. (Or for other errata, 3079512cf780Skchow * OS workaround is required.) 3080512cf780Skchow * For a value of 1, caller will confirm that the 3081512cf780Skchow * erratum 298 workaround has indeed been applied by BIOS. 3082512cf780Skchow * 3083512cf780Skchow * A 1 may be set in cpus that have a HW fix 3084512cf780Skchow * in a mixed cpu system. Regarding erratum 298: 3085512cf780Skchow * In a multiprocessor platform, the workaround above 3086512cf780Skchow * should be applied to all processors regardless of 3087512cf780Skchow * silicon revision when an affected processor is 3088512cf780Skchow * present. 3089512cf780Skchow */ 3090512cf780Skchow 3091512cf780Skchow return (rdmsr(MSR_AMD_OSVW_STATUS + 3092512cf780Skchow (osvwid / OSVW_ID_CNT_PER_MSR)) & 3093512cf780Skchow (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 3094512cf780Skchow 30957c478bd9Sstevel@tonic-gate default: 30967c478bd9Sstevel@tonic-gate return (-1); 30977c478bd9Sstevel@tonic-gate } 30987c478bd9Sstevel@tonic-gate } 30997c478bd9Sstevel@tonic-gate 31007c478bd9Sstevel@tonic-gate static const char assoc_str[] = "associativity"; 31017c478bd9Sstevel@tonic-gate static const char line_str[] = "line-size"; 31027c478bd9Sstevel@tonic-gate static const char size_str[] = "size"; 31037c478bd9Sstevel@tonic-gate 31047c478bd9Sstevel@tonic-gate static void 31057c478bd9Sstevel@tonic-gate add_cache_prop(dev_info_t *devi, const char *label, const char *type, 31067c478bd9Sstevel@tonic-gate uint32_t val) 31077c478bd9Sstevel@tonic-gate { 31087c478bd9Sstevel@tonic-gate char buf[128]; 31097c478bd9Sstevel@tonic-gate 31107c478bd9Sstevel@tonic-gate /* 31117c478bd9Sstevel@tonic-gate * ndi_prop_update_int() is used because it is desirable for 31127c478bd9Sstevel@tonic-gate * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 31137c478bd9Sstevel@tonic-gate */ 31147c478bd9Sstevel@tonic-gate if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 31157c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 31167c478bd9Sstevel@tonic-gate } 31177c478bd9Sstevel@tonic-gate 31187c478bd9Sstevel@tonic-gate /* 31197c478bd9Sstevel@tonic-gate * Intel-style cache/tlb description 31207c478bd9Sstevel@tonic-gate * 31217c478bd9Sstevel@tonic-gate * Standard cpuid level 2 gives a randomly ordered 31227c478bd9Sstevel@tonic-gate * selection of tags that index into a table that describes 31237c478bd9Sstevel@tonic-gate * cache and tlb properties. 31247c478bd9Sstevel@tonic-gate */ 31257c478bd9Sstevel@tonic-gate 31267c478bd9Sstevel@tonic-gate static const char l1_icache_str[] = "l1-icache"; 31277c478bd9Sstevel@tonic-gate static const char l1_dcache_str[] = "l1-dcache"; 31287c478bd9Sstevel@tonic-gate static const char l2_cache_str[] = "l2-cache"; 3129ae115bc7Smrj static const char l3_cache_str[] = "l3-cache"; 31307c478bd9Sstevel@tonic-gate static const char itlb4k_str[] = "itlb-4K"; 31317c478bd9Sstevel@tonic-gate static const char dtlb4k_str[] = "dtlb-4K"; 3132824e4fecSvd224797 static const char itlb2M_str[] = "itlb-2M"; 31337c478bd9Sstevel@tonic-gate static const char itlb4M_str[] = "itlb-4M"; 31347c478bd9Sstevel@tonic-gate static const char dtlb4M_str[] = "dtlb-4M"; 313525dfb062Sksadhukh static const char dtlb24_str[] = "dtlb0-2M-4M"; 31367c478bd9Sstevel@tonic-gate static const char itlb424_str[] = "itlb-4K-2M-4M"; 313725dfb062Sksadhukh static const char itlb24_str[] = "itlb-2M-4M"; 31387c478bd9Sstevel@tonic-gate static const char dtlb44_str[] = "dtlb-4K-4M"; 31397c478bd9Sstevel@tonic-gate static const char sl1_dcache_str[] = "sectored-l1-dcache"; 31407c478bd9Sstevel@tonic-gate static const char sl2_cache_str[] = "sectored-l2-cache"; 31417c478bd9Sstevel@tonic-gate static const char itrace_str[] = "itrace-cache"; 31427c478bd9Sstevel@tonic-gate static const char sl3_cache_str[] = "sectored-l3-cache"; 314325dfb062Sksadhukh static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 31447c478bd9Sstevel@tonic-gate 31457c478bd9Sstevel@tonic-gate static const struct cachetab { 31467c478bd9Sstevel@tonic-gate uint8_t ct_code; 31477c478bd9Sstevel@tonic-gate uint8_t ct_assoc; 31487c478bd9Sstevel@tonic-gate uint16_t ct_line_size; 31497c478bd9Sstevel@tonic-gate size_t ct_size; 31507c478bd9Sstevel@tonic-gate const char *ct_label; 31517c478bd9Sstevel@tonic-gate } intel_ctab[] = { 3152824e4fecSvd224797 /* 3153824e4fecSvd224797 * maintain descending order! 3154824e4fecSvd224797 * 3155824e4fecSvd224797 * Codes ignored - Reason 3156824e4fecSvd224797 * ---------------------- 3157824e4fecSvd224797 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 3158824e4fecSvd224797 * f0H/f1H - Currently we do not interpret prefetch size by design 3159824e4fecSvd224797 */ 316025dfb062Sksadhukh { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 316125dfb062Sksadhukh { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 316225dfb062Sksadhukh { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 316325dfb062Sksadhukh { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 316425dfb062Sksadhukh { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 316525dfb062Sksadhukh { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 316625dfb062Sksadhukh { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 316725dfb062Sksadhukh { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 316825dfb062Sksadhukh { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 316925dfb062Sksadhukh { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 317025dfb062Sksadhukh { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 317125dfb062Sksadhukh { 0xd0, 4, 64, 512*1024, l3_cache_str}, 317225dfb062Sksadhukh { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 3173824e4fecSvd224797 { 0xc0, 4, 0, 8, dtlb44_str }, 3174824e4fecSvd224797 { 0xba, 4, 0, 64, dtlb4k_str }, 3175ae115bc7Smrj { 0xb4, 4, 0, 256, dtlb4k_str }, 31767c478bd9Sstevel@tonic-gate { 0xb3, 4, 0, 128, dtlb4k_str }, 317725dfb062Sksadhukh { 0xb2, 4, 0, 64, itlb4k_str }, 31787c478bd9Sstevel@tonic-gate { 0xb0, 4, 0, 128, itlb4k_str }, 31797c478bd9Sstevel@tonic-gate { 0x87, 8, 64, 1024*1024, l2_cache_str}, 31807c478bd9Sstevel@tonic-gate { 0x86, 4, 64, 512*1024, l2_cache_str}, 31817c478bd9Sstevel@tonic-gate { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 31827c478bd9Sstevel@tonic-gate { 0x84, 8, 32, 1024*1024, l2_cache_str}, 31837c478bd9Sstevel@tonic-gate { 0x83, 8, 32, 512*1024, l2_cache_str}, 31847c478bd9Sstevel@tonic-gate { 0x82, 8, 32, 256*1024, l2_cache_str}, 3185824e4fecSvd224797 { 0x80, 8, 64, 512*1024, l2_cache_str}, 31867c478bd9Sstevel@tonic-gate { 0x7f, 2, 64, 512*1024, l2_cache_str}, 31877c478bd9Sstevel@tonic-gate { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 31887c478bd9Sstevel@tonic-gate { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 31897c478bd9Sstevel@tonic-gate { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 31907c478bd9Sstevel@tonic-gate { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 31917c478bd9Sstevel@tonic-gate { 0x79, 8, 64, 128*1024, sl2_cache_str}, 31927c478bd9Sstevel@tonic-gate { 0x78, 8, 64, 1024*1024, l2_cache_str}, 3193ae115bc7Smrj { 0x73, 8, 0, 64*1024, itrace_str}, 31947c478bd9Sstevel@tonic-gate { 0x72, 8, 0, 32*1024, itrace_str}, 31957c478bd9Sstevel@tonic-gate { 0x71, 8, 0, 16*1024, itrace_str}, 31967c478bd9Sstevel@tonic-gate { 0x70, 8, 0, 12*1024, itrace_str}, 31977c478bd9Sstevel@tonic-gate { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 31987c478bd9Sstevel@tonic-gate { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 31997c478bd9Sstevel@tonic-gate { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 32007c478bd9Sstevel@tonic-gate { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 32017c478bd9Sstevel@tonic-gate { 0x5d, 0, 0, 256, dtlb44_str}, 32027c478bd9Sstevel@tonic-gate { 0x5c, 0, 0, 128, dtlb44_str}, 32037c478bd9Sstevel@tonic-gate { 0x5b, 0, 0, 64, dtlb44_str}, 320425dfb062Sksadhukh { 0x5a, 4, 0, 32, dtlb24_str}, 3205824e4fecSvd224797 { 0x59, 0, 0, 16, dtlb4k_str}, 3206824e4fecSvd224797 { 0x57, 4, 0, 16, dtlb4k_str}, 3207824e4fecSvd224797 { 0x56, 4, 0, 16, dtlb4M_str}, 320825dfb062Sksadhukh { 0x55, 0, 0, 7, itlb24_str}, 32097c478bd9Sstevel@tonic-gate { 0x52, 0, 0, 256, itlb424_str}, 32107c478bd9Sstevel@tonic-gate { 0x51, 0, 0, 128, itlb424_str}, 32117c478bd9Sstevel@tonic-gate { 0x50, 0, 0, 64, itlb424_str}, 3212824e4fecSvd224797 { 0x4f, 0, 0, 32, itlb4k_str}, 3213824e4fecSvd224797 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 3214ae115bc7Smrj { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 3215ae115bc7Smrj { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 3216ae115bc7Smrj { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 3217ae115bc7Smrj { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 3218ae115bc7Smrj { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 3219824e4fecSvd224797 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 3220ae115bc7Smrj { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 3221ae115bc7Smrj { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 32227c478bd9Sstevel@tonic-gate { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 32237c478bd9Sstevel@tonic-gate { 0x44, 4, 32, 1024*1024, l2_cache_str}, 32247c478bd9Sstevel@tonic-gate { 0x43, 4, 32, 512*1024, l2_cache_str}, 32257c478bd9Sstevel@tonic-gate { 0x42, 4, 32, 256*1024, l2_cache_str}, 32267c478bd9Sstevel@tonic-gate { 0x41, 4, 32, 128*1024, l2_cache_str}, 3227ae115bc7Smrj { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 3228ae115bc7Smrj { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 32297c478bd9Sstevel@tonic-gate { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 32307c478bd9Sstevel@tonic-gate { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 3231ae115bc7Smrj { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 32327c478bd9Sstevel@tonic-gate { 0x39, 4, 64, 128*1024, sl2_cache_str}, 32337c478bd9Sstevel@tonic-gate { 0x30, 8, 64, 32*1024, l1_icache_str}, 32347c478bd9Sstevel@tonic-gate { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 32357c478bd9Sstevel@tonic-gate { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 32367c478bd9Sstevel@tonic-gate { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 32377c478bd9Sstevel@tonic-gate { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 32387c478bd9Sstevel@tonic-gate { 0x22, 4, 64, 512*1024, sl3_cache_str}, 3239824e4fecSvd224797 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 324025dfb062Sksadhukh { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 32417c478bd9Sstevel@tonic-gate { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 3242ae115bc7Smrj { 0x0b, 4, 0, 4, itlb4M_str}, 32437c478bd9Sstevel@tonic-gate { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 32447c478bd9Sstevel@tonic-gate { 0x08, 4, 32, 16*1024, l1_icache_str}, 32457c478bd9Sstevel@tonic-gate { 0x06, 4, 32, 8*1024, l1_icache_str}, 3246824e4fecSvd224797 { 0x05, 4, 0, 32, dtlb4M_str}, 32477c478bd9Sstevel@tonic-gate { 0x04, 4, 0, 8, dtlb4M_str}, 32487c478bd9Sstevel@tonic-gate { 0x03, 4, 0, 64, dtlb4k_str}, 32497c478bd9Sstevel@tonic-gate { 0x02, 4, 0, 2, itlb4M_str}, 32507c478bd9Sstevel@tonic-gate { 0x01, 4, 0, 32, itlb4k_str}, 32517c478bd9Sstevel@tonic-gate { 0 } 32527c478bd9Sstevel@tonic-gate }; 32537c478bd9Sstevel@tonic-gate 32547c478bd9Sstevel@tonic-gate static const struct cachetab cyrix_ctab[] = { 32557c478bd9Sstevel@tonic-gate { 0x70, 4, 0, 32, "tlb-4K" }, 32567c478bd9Sstevel@tonic-gate { 0x80, 4, 16, 16*1024, "l1-cache" }, 32577c478bd9Sstevel@tonic-gate { 0 } 32587c478bd9Sstevel@tonic-gate }; 32597c478bd9Sstevel@tonic-gate 32607c478bd9Sstevel@tonic-gate /* 32617c478bd9Sstevel@tonic-gate * Search a cache table for a matching entry 32627c478bd9Sstevel@tonic-gate */ 32637c478bd9Sstevel@tonic-gate static const struct cachetab * 32647c478bd9Sstevel@tonic-gate find_cacheent(const struct cachetab *ct, uint_t code) 32657c478bd9Sstevel@tonic-gate { 32667c478bd9Sstevel@tonic-gate if (code != 0) { 32677c478bd9Sstevel@tonic-gate for (; ct->ct_code != 0; ct++) 32687c478bd9Sstevel@tonic-gate if (ct->ct_code <= code) 32697c478bd9Sstevel@tonic-gate break; 32707c478bd9Sstevel@tonic-gate if (ct->ct_code == code) 32717c478bd9Sstevel@tonic-gate return (ct); 32727c478bd9Sstevel@tonic-gate } 32737c478bd9Sstevel@tonic-gate return (NULL); 32747c478bd9Sstevel@tonic-gate } 32757c478bd9Sstevel@tonic-gate 32767c478bd9Sstevel@tonic-gate /* 32777dee861bSksadhukh * Populate cachetab entry with L2 or L3 cache-information using 32787dee861bSksadhukh * cpuid function 4. This function is called from intel_walk_cacheinfo() 32797dee861bSksadhukh * when descriptor 0x49 is encountered. It returns 0 if no such cache 32807dee861bSksadhukh * information is found. 32817dee861bSksadhukh */ 32827dee861bSksadhukh static int 32837dee861bSksadhukh intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 32847dee861bSksadhukh { 32857dee861bSksadhukh uint32_t level, i; 32867dee861bSksadhukh int ret = 0; 32877dee861bSksadhukh 32887dee861bSksadhukh for (i = 0; i < cpi->cpi_std_4_size; i++) { 32897dee861bSksadhukh level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 32907dee861bSksadhukh 32917dee861bSksadhukh if (level == 2 || level == 3) { 32927dee861bSksadhukh ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 32937dee861bSksadhukh ct->ct_line_size = 32947dee861bSksadhukh CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 32957dee861bSksadhukh ct->ct_size = ct->ct_assoc * 32967dee861bSksadhukh (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 32977dee861bSksadhukh ct->ct_line_size * 32987dee861bSksadhukh (cpi->cpi_std_4[i]->cp_ecx + 1); 32997dee861bSksadhukh 33007dee861bSksadhukh if (level == 2) { 33017dee861bSksadhukh ct->ct_label = l2_cache_str; 33027dee861bSksadhukh } else if (level == 3) { 33037dee861bSksadhukh ct->ct_label = l3_cache_str; 33047dee861bSksadhukh } 33057dee861bSksadhukh ret = 1; 33067dee861bSksadhukh } 33077dee861bSksadhukh } 33087dee861bSksadhukh 33097dee861bSksadhukh return (ret); 33107dee861bSksadhukh } 33117dee861bSksadhukh 33127dee861bSksadhukh /* 33137c478bd9Sstevel@tonic-gate * Walk the cacheinfo descriptor, applying 'func' to every valid element 33147c478bd9Sstevel@tonic-gate * The walk is terminated if the walker returns non-zero. 33157c478bd9Sstevel@tonic-gate */ 33167c478bd9Sstevel@tonic-gate static void 33177c478bd9Sstevel@tonic-gate intel_walk_cacheinfo(struct cpuid_info *cpi, 33187c478bd9Sstevel@tonic-gate void *arg, int (*func)(void *, const struct cachetab *)) 33197c478bd9Sstevel@tonic-gate { 33207c478bd9Sstevel@tonic-gate const struct cachetab *ct; 3321824e4fecSvd224797 struct cachetab des_49_ct, des_b1_ct; 33227c478bd9Sstevel@tonic-gate uint8_t *dp; 33237c478bd9Sstevel@tonic-gate int i; 33247c478bd9Sstevel@tonic-gate 33257c478bd9Sstevel@tonic-gate if ((dp = cpi->cpi_cacheinfo) == NULL) 33267c478bd9Sstevel@tonic-gate return; 3327f1d742a9Sksadhukh for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3328f1d742a9Sksadhukh /* 3329f1d742a9Sksadhukh * For overloaded descriptor 0x49 we use cpuid function 4 33307dee861bSksadhukh * if supported by the current processor, to create 3331f1d742a9Sksadhukh * cache information. 3332824e4fecSvd224797 * For overloaded descriptor 0xb1 we use X86_PAE flag 3333824e4fecSvd224797 * to disambiguate the cache information. 3334f1d742a9Sksadhukh */ 33357dee861bSksadhukh if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 33367dee861bSksadhukh intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 33377dee861bSksadhukh ct = &des_49_ct; 3338824e4fecSvd224797 } else if (*dp == 0xb1) { 3339824e4fecSvd224797 des_b1_ct.ct_code = 0xb1; 3340824e4fecSvd224797 des_b1_ct.ct_assoc = 4; 3341824e4fecSvd224797 des_b1_ct.ct_line_size = 0; 3342824e4fecSvd224797 if (x86_feature & X86_PAE) { 3343824e4fecSvd224797 des_b1_ct.ct_size = 8; 3344824e4fecSvd224797 des_b1_ct.ct_label = itlb2M_str; 3345824e4fecSvd224797 } else { 3346824e4fecSvd224797 des_b1_ct.ct_size = 4; 3347824e4fecSvd224797 des_b1_ct.ct_label = itlb4M_str; 3348824e4fecSvd224797 } 3349824e4fecSvd224797 ct = &des_b1_ct; 33507dee861bSksadhukh } else { 33517dee861bSksadhukh if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3352f1d742a9Sksadhukh continue; 3353f1d742a9Sksadhukh } 33547dee861bSksadhukh } 3355f1d742a9Sksadhukh 33567dee861bSksadhukh if (func(arg, ct) != 0) { 33577c478bd9Sstevel@tonic-gate break; 33587c478bd9Sstevel@tonic-gate } 33597c478bd9Sstevel@tonic-gate } 3360f1d742a9Sksadhukh } 33617c478bd9Sstevel@tonic-gate 33627c478bd9Sstevel@tonic-gate /* 33637c478bd9Sstevel@tonic-gate * (Like the Intel one, except for Cyrix CPUs) 33647c478bd9Sstevel@tonic-gate */ 33657c478bd9Sstevel@tonic-gate static void 33667c478bd9Sstevel@tonic-gate cyrix_walk_cacheinfo(struct cpuid_info *cpi, 33677c478bd9Sstevel@tonic-gate void *arg, int (*func)(void *, const struct cachetab *)) 33687c478bd9Sstevel@tonic-gate { 33697c478bd9Sstevel@tonic-gate const struct cachetab *ct; 33707c478bd9Sstevel@tonic-gate uint8_t *dp; 33717c478bd9Sstevel@tonic-gate int i; 33727c478bd9Sstevel@tonic-gate 33737c478bd9Sstevel@tonic-gate if ((dp = cpi->cpi_cacheinfo) == NULL) 33747c478bd9Sstevel@tonic-gate return; 33757c478bd9Sstevel@tonic-gate for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 33767c478bd9Sstevel@tonic-gate /* 33777c478bd9Sstevel@tonic-gate * Search Cyrix-specific descriptor table first .. 33787c478bd9Sstevel@tonic-gate */ 33797c478bd9Sstevel@tonic-gate if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 33807c478bd9Sstevel@tonic-gate if (func(arg, ct) != 0) 33817c478bd9Sstevel@tonic-gate break; 33827c478bd9Sstevel@tonic-gate continue; 33837c478bd9Sstevel@tonic-gate } 33847c478bd9Sstevel@tonic-gate /* 33857c478bd9Sstevel@tonic-gate * .. else fall back to the Intel one 33867c478bd9Sstevel@tonic-gate */ 33877c478bd9Sstevel@tonic-gate if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 33887c478bd9Sstevel@tonic-gate if (func(arg, ct) != 0) 33897c478bd9Sstevel@tonic-gate break; 33907c478bd9Sstevel@tonic-gate continue; 33917c478bd9Sstevel@tonic-gate } 33927c478bd9Sstevel@tonic-gate } 33937c478bd9Sstevel@tonic-gate } 33947c478bd9Sstevel@tonic-gate 33957c478bd9Sstevel@tonic-gate /* 33967c478bd9Sstevel@tonic-gate * A cacheinfo walker that adds associativity, line-size, and size properties 33977c478bd9Sstevel@tonic-gate * to the devinfo node it is passed as an argument. 33987c478bd9Sstevel@tonic-gate */ 33997c478bd9Sstevel@tonic-gate static int 34007c478bd9Sstevel@tonic-gate add_cacheent_props(void *arg, const struct cachetab *ct) 34017c478bd9Sstevel@tonic-gate { 34027c478bd9Sstevel@tonic-gate dev_info_t *devi = arg; 34037c478bd9Sstevel@tonic-gate 34047c478bd9Sstevel@tonic-gate add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 34057c478bd9Sstevel@tonic-gate if (ct->ct_line_size != 0) 34067c478bd9Sstevel@tonic-gate add_cache_prop(devi, ct->ct_label, line_str, 34077c478bd9Sstevel@tonic-gate ct->ct_line_size); 34087c478bd9Sstevel@tonic-gate add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 34097c478bd9Sstevel@tonic-gate return (0); 34107c478bd9Sstevel@tonic-gate } 34117c478bd9Sstevel@tonic-gate 3412f1d742a9Sksadhukh 34137c478bd9Sstevel@tonic-gate static const char fully_assoc[] = "fully-associative?"; 34147c478bd9Sstevel@tonic-gate 34157c478bd9Sstevel@tonic-gate /* 34167c478bd9Sstevel@tonic-gate * AMD style cache/tlb description 34177c478bd9Sstevel@tonic-gate * 34187c478bd9Sstevel@tonic-gate * Extended functions 5 and 6 directly describe properties of 34197c478bd9Sstevel@tonic-gate * tlbs and various cache levels. 34207c478bd9Sstevel@tonic-gate */ 34217c478bd9Sstevel@tonic-gate static void 34227c478bd9Sstevel@tonic-gate add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 34237c478bd9Sstevel@tonic-gate { 34247c478bd9Sstevel@tonic-gate switch (assoc) { 34257c478bd9Sstevel@tonic-gate case 0: /* reserved; ignore */ 34267c478bd9Sstevel@tonic-gate break; 34277c478bd9Sstevel@tonic-gate default: 34287c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, assoc_str, assoc); 34297c478bd9Sstevel@tonic-gate break; 34307c478bd9Sstevel@tonic-gate case 0xff: 34317c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, fully_assoc, 1); 34327c478bd9Sstevel@tonic-gate break; 34337c478bd9Sstevel@tonic-gate } 34347c478bd9Sstevel@tonic-gate } 34357c478bd9Sstevel@tonic-gate 34367c478bd9Sstevel@tonic-gate static void 34377c478bd9Sstevel@tonic-gate add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 34387c478bd9Sstevel@tonic-gate { 34397c478bd9Sstevel@tonic-gate if (size == 0) 34407c478bd9Sstevel@tonic-gate return; 34417c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, size_str, size); 34427c478bd9Sstevel@tonic-gate add_amd_assoc(devi, label, assoc); 34437c478bd9Sstevel@tonic-gate } 34447c478bd9Sstevel@tonic-gate 34457c478bd9Sstevel@tonic-gate static void 34467c478bd9Sstevel@tonic-gate add_amd_cache(dev_info_t *devi, const char *label, 34477c478bd9Sstevel@tonic-gate uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 34487c478bd9Sstevel@tonic-gate { 34497c478bd9Sstevel@tonic-gate if (size == 0 || line_size == 0) 34507c478bd9Sstevel@tonic-gate return; 34517c478bd9Sstevel@tonic-gate add_amd_assoc(devi, label, assoc); 34527c478bd9Sstevel@tonic-gate /* 34537c478bd9Sstevel@tonic-gate * Most AMD parts have a sectored cache. Multiple cache lines are 34547c478bd9Sstevel@tonic-gate * associated with each tag. A sector consists of all cache lines 34557c478bd9Sstevel@tonic-gate * associated with a tag. For example, the AMD K6-III has a sector 34567c478bd9Sstevel@tonic-gate * size of 2 cache lines per tag. 34577c478bd9Sstevel@tonic-gate */ 34587c478bd9Sstevel@tonic-gate if (lines_per_tag != 0) 34597c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 34607c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, line_str, line_size); 34617c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, size_str, size * 1024); 34627c478bd9Sstevel@tonic-gate } 34637c478bd9Sstevel@tonic-gate 34647c478bd9Sstevel@tonic-gate static void 34657c478bd9Sstevel@tonic-gate add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 34667c478bd9Sstevel@tonic-gate { 34677c478bd9Sstevel@tonic-gate switch (assoc) { 34687c478bd9Sstevel@tonic-gate case 0: /* off */ 34697c478bd9Sstevel@tonic-gate break; 34707c478bd9Sstevel@tonic-gate case 1: 34717c478bd9Sstevel@tonic-gate case 2: 34727c478bd9Sstevel@tonic-gate case 4: 34737c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, assoc_str, assoc); 34747c478bd9Sstevel@tonic-gate break; 34757c478bd9Sstevel@tonic-gate case 6: 34767c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, assoc_str, 8); 34777c478bd9Sstevel@tonic-gate break; 34787c478bd9Sstevel@tonic-gate case 8: 34797c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, assoc_str, 16); 34807c478bd9Sstevel@tonic-gate break; 34817c478bd9Sstevel@tonic-gate case 0xf: 34827c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, fully_assoc, 1); 34837c478bd9Sstevel@tonic-gate break; 34847c478bd9Sstevel@tonic-gate default: /* reserved; ignore */ 34857c478bd9Sstevel@tonic-gate break; 34867c478bd9Sstevel@tonic-gate } 34877c478bd9Sstevel@tonic-gate } 34887c478bd9Sstevel@tonic-gate 34897c478bd9Sstevel@tonic-gate static void 34907c478bd9Sstevel@tonic-gate add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 34917c478bd9Sstevel@tonic-gate { 34927c478bd9Sstevel@tonic-gate if (size == 0 || assoc == 0) 34937c478bd9Sstevel@tonic-gate return; 34947c478bd9Sstevel@tonic-gate add_amd_l2_assoc(devi, label, assoc); 34957c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, size_str, size); 34967c478bd9Sstevel@tonic-gate } 34977c478bd9Sstevel@tonic-gate 34987c478bd9Sstevel@tonic-gate static void 34997c478bd9Sstevel@tonic-gate add_amd_l2_cache(dev_info_t *devi, const char *label, 35007c478bd9Sstevel@tonic-gate uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 35017c478bd9Sstevel@tonic-gate { 35027c478bd9Sstevel@tonic-gate if (size == 0 || assoc == 0 || line_size == 0) 35037c478bd9Sstevel@tonic-gate return; 35047c478bd9Sstevel@tonic-gate add_amd_l2_assoc(devi, label, assoc); 35057c478bd9Sstevel@tonic-gate if (lines_per_tag != 0) 35067c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 35077c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, line_str, line_size); 35087c478bd9Sstevel@tonic-gate add_cache_prop(devi, label, size_str, size * 1024); 35097c478bd9Sstevel@tonic-gate } 35107c478bd9Sstevel@tonic-gate 35117c478bd9Sstevel@tonic-gate static void 35127c478bd9Sstevel@tonic-gate amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 35137c478bd9Sstevel@tonic-gate { 35148949bcd6Sandrei struct cpuid_regs *cp; 35157c478bd9Sstevel@tonic-gate 35167c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax < 0x80000005) 35177c478bd9Sstevel@tonic-gate return; 35187c478bd9Sstevel@tonic-gate cp = &cpi->cpi_extd[5]; 35197c478bd9Sstevel@tonic-gate 35207c478bd9Sstevel@tonic-gate /* 35217c478bd9Sstevel@tonic-gate * 4M/2M L1 TLB configuration 35227c478bd9Sstevel@tonic-gate * 35237c478bd9Sstevel@tonic-gate * We report the size for 2M pages because AMD uses two 35247c478bd9Sstevel@tonic-gate * TLB entries for one 4M page. 35257c478bd9Sstevel@tonic-gate */ 35267c478bd9Sstevel@tonic-gate add_amd_tlb(devi, "dtlb-2M", 35277c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 35287c478bd9Sstevel@tonic-gate add_amd_tlb(devi, "itlb-2M", 35297c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 35307c478bd9Sstevel@tonic-gate 35317c478bd9Sstevel@tonic-gate /* 35327c478bd9Sstevel@tonic-gate * 4K L1 TLB configuration 35337c478bd9Sstevel@tonic-gate */ 35347c478bd9Sstevel@tonic-gate 35357c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 35367c478bd9Sstevel@tonic-gate uint_t nentries; 35377c478bd9Sstevel@tonic-gate case X86_VENDOR_TM: 35387c478bd9Sstevel@tonic-gate if (cpi->cpi_family >= 5) { 35397c478bd9Sstevel@tonic-gate /* 35407c478bd9Sstevel@tonic-gate * Crusoe processors have 256 TLB entries, but 35417c478bd9Sstevel@tonic-gate * cpuid data format constrains them to only 35427c478bd9Sstevel@tonic-gate * reporting 255 of them. 35437c478bd9Sstevel@tonic-gate */ 35447c478bd9Sstevel@tonic-gate if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 35457c478bd9Sstevel@tonic-gate nentries = 256; 35467c478bd9Sstevel@tonic-gate /* 35477c478bd9Sstevel@tonic-gate * Crusoe processors also have a unified TLB 35487c478bd9Sstevel@tonic-gate */ 35497c478bd9Sstevel@tonic-gate add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 35507c478bd9Sstevel@tonic-gate nentries); 35517c478bd9Sstevel@tonic-gate break; 35527c478bd9Sstevel@tonic-gate } 35537c478bd9Sstevel@tonic-gate /*FALLTHROUGH*/ 35547c478bd9Sstevel@tonic-gate default: 35557c478bd9Sstevel@tonic-gate add_amd_tlb(devi, itlb4k_str, 35567c478bd9Sstevel@tonic-gate BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 35577c478bd9Sstevel@tonic-gate add_amd_tlb(devi, dtlb4k_str, 35587c478bd9Sstevel@tonic-gate BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 35597c478bd9Sstevel@tonic-gate break; 35607c478bd9Sstevel@tonic-gate } 35617c478bd9Sstevel@tonic-gate 35627c478bd9Sstevel@tonic-gate /* 35637c478bd9Sstevel@tonic-gate * data L1 cache configuration 35647c478bd9Sstevel@tonic-gate */ 35657c478bd9Sstevel@tonic-gate 35667c478bd9Sstevel@tonic-gate add_amd_cache(devi, l1_dcache_str, 35677c478bd9Sstevel@tonic-gate BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 35687c478bd9Sstevel@tonic-gate BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 35697c478bd9Sstevel@tonic-gate 35707c478bd9Sstevel@tonic-gate /* 35717c478bd9Sstevel@tonic-gate * code L1 cache configuration 35727c478bd9Sstevel@tonic-gate */ 35737c478bd9Sstevel@tonic-gate 35747c478bd9Sstevel@tonic-gate add_amd_cache(devi, l1_icache_str, 35757c478bd9Sstevel@tonic-gate BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 35767c478bd9Sstevel@tonic-gate BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 35777c478bd9Sstevel@tonic-gate 35787c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax < 0x80000006) 35797c478bd9Sstevel@tonic-gate return; 35807c478bd9Sstevel@tonic-gate cp = &cpi->cpi_extd[6]; 35817c478bd9Sstevel@tonic-gate 35827c478bd9Sstevel@tonic-gate /* Check for a unified L2 TLB for large pages */ 35837c478bd9Sstevel@tonic-gate 35847c478bd9Sstevel@tonic-gate if (BITX(cp->cp_eax, 31, 16) == 0) 35857c478bd9Sstevel@tonic-gate add_amd_l2_tlb(devi, "l2-tlb-2M", 35867c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 35877c478bd9Sstevel@tonic-gate else { 35887c478bd9Sstevel@tonic-gate add_amd_l2_tlb(devi, "l2-dtlb-2M", 35897c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 35907c478bd9Sstevel@tonic-gate add_amd_l2_tlb(devi, "l2-itlb-2M", 35917c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 35927c478bd9Sstevel@tonic-gate } 35937c478bd9Sstevel@tonic-gate 35947c478bd9Sstevel@tonic-gate /* Check for a unified L2 TLB for 4K pages */ 35957c478bd9Sstevel@tonic-gate 35967c478bd9Sstevel@tonic-gate if (BITX(cp->cp_ebx, 31, 16) == 0) { 35977c478bd9Sstevel@tonic-gate add_amd_l2_tlb(devi, "l2-tlb-4K", 35987c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 35997c478bd9Sstevel@tonic-gate } else { 36007c478bd9Sstevel@tonic-gate add_amd_l2_tlb(devi, "l2-dtlb-4K", 36017c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 36027c478bd9Sstevel@tonic-gate add_amd_l2_tlb(devi, "l2-itlb-4K", 36037c478bd9Sstevel@tonic-gate BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 36047c478bd9Sstevel@tonic-gate } 36057c478bd9Sstevel@tonic-gate 36067c478bd9Sstevel@tonic-gate add_amd_l2_cache(devi, l2_cache_str, 36077c478bd9Sstevel@tonic-gate BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 36087c478bd9Sstevel@tonic-gate BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 36097c478bd9Sstevel@tonic-gate } 36107c478bd9Sstevel@tonic-gate 36117c478bd9Sstevel@tonic-gate /* 36127c478bd9Sstevel@tonic-gate * There are two basic ways that the x86 world describes it cache 36137c478bd9Sstevel@tonic-gate * and tlb architecture - Intel's way and AMD's way. 36147c478bd9Sstevel@tonic-gate * 36157c478bd9Sstevel@tonic-gate * Return which flavor of cache architecture we should use 36167c478bd9Sstevel@tonic-gate */ 36177c478bd9Sstevel@tonic-gate static int 36187c478bd9Sstevel@tonic-gate x86_which_cacheinfo(struct cpuid_info *cpi) 36197c478bd9Sstevel@tonic-gate { 36207c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 36217c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 36227c478bd9Sstevel@tonic-gate if (cpi->cpi_maxeax >= 2) 36237c478bd9Sstevel@tonic-gate return (X86_VENDOR_Intel); 36247c478bd9Sstevel@tonic-gate break; 36257c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 36267c478bd9Sstevel@tonic-gate /* 36277c478bd9Sstevel@tonic-gate * The K5 model 1 was the first part from AMD that reported 36287c478bd9Sstevel@tonic-gate * cache sizes via extended cpuid functions. 36297c478bd9Sstevel@tonic-gate */ 36307c478bd9Sstevel@tonic-gate if (cpi->cpi_family > 5 || 36317c478bd9Sstevel@tonic-gate (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 36327c478bd9Sstevel@tonic-gate return (X86_VENDOR_AMD); 36337c478bd9Sstevel@tonic-gate break; 36347c478bd9Sstevel@tonic-gate case X86_VENDOR_TM: 36357c478bd9Sstevel@tonic-gate if (cpi->cpi_family >= 5) 36367c478bd9Sstevel@tonic-gate return (X86_VENDOR_AMD); 36377c478bd9Sstevel@tonic-gate /*FALLTHROUGH*/ 36387c478bd9Sstevel@tonic-gate default: 36397c478bd9Sstevel@tonic-gate /* 36407c478bd9Sstevel@tonic-gate * If they have extended CPU data for 0x80000005 36417c478bd9Sstevel@tonic-gate * then we assume they have AMD-format cache 36427c478bd9Sstevel@tonic-gate * information. 36437c478bd9Sstevel@tonic-gate * 36447c478bd9Sstevel@tonic-gate * If not, and the vendor happens to be Cyrix, 36457c478bd9Sstevel@tonic-gate * then try our-Cyrix specific handler. 36467c478bd9Sstevel@tonic-gate * 36477c478bd9Sstevel@tonic-gate * If we're not Cyrix, then assume we're using Intel's 36487c478bd9Sstevel@tonic-gate * table-driven format instead. 36497c478bd9Sstevel@tonic-gate */ 36507c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax >= 0x80000005) 36517c478bd9Sstevel@tonic-gate return (X86_VENDOR_AMD); 36527c478bd9Sstevel@tonic-gate else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 36537c478bd9Sstevel@tonic-gate return (X86_VENDOR_Cyrix); 36547c478bd9Sstevel@tonic-gate else if (cpi->cpi_maxeax >= 2) 36557c478bd9Sstevel@tonic-gate return (X86_VENDOR_Intel); 36567c478bd9Sstevel@tonic-gate break; 36577c478bd9Sstevel@tonic-gate } 36587c478bd9Sstevel@tonic-gate return (-1); 36597c478bd9Sstevel@tonic-gate } 36607c478bd9Sstevel@tonic-gate 36617c478bd9Sstevel@tonic-gate void 3662fa96bd91SMichael Corcoran cpuid_set_cpu_properties(void *dip, processorid_t cpu_id, 3663fa96bd91SMichael Corcoran struct cpuid_info *cpi) 36647c478bd9Sstevel@tonic-gate { 36657c478bd9Sstevel@tonic-gate dev_info_t *cpu_devi; 36667c478bd9Sstevel@tonic-gate int create; 36677c478bd9Sstevel@tonic-gate 3668fa96bd91SMichael Corcoran cpu_devi = (dev_info_t *)dip; 36697c478bd9Sstevel@tonic-gate 36707c478bd9Sstevel@tonic-gate /* device_type */ 36717c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 36727c478bd9Sstevel@tonic-gate "device_type", "cpu"); 36737c478bd9Sstevel@tonic-gate 36747c478bd9Sstevel@tonic-gate /* reg */ 36757c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 36767c478bd9Sstevel@tonic-gate "reg", cpu_id); 36777c478bd9Sstevel@tonic-gate 36787c478bd9Sstevel@tonic-gate /* cpu-mhz, and clock-frequency */ 36797c478bd9Sstevel@tonic-gate if (cpu_freq > 0) { 36807c478bd9Sstevel@tonic-gate long long mul; 36817c478bd9Sstevel@tonic-gate 36827c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 36837c478bd9Sstevel@tonic-gate "cpu-mhz", cpu_freq); 36847c478bd9Sstevel@tonic-gate if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 36857c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 36867c478bd9Sstevel@tonic-gate "clock-frequency", (int)mul); 36877c478bd9Sstevel@tonic-gate } 36887c478bd9Sstevel@tonic-gate 36897c478bd9Sstevel@tonic-gate if ((x86_feature & X86_CPUID) == 0) { 36907c478bd9Sstevel@tonic-gate return; 36917c478bd9Sstevel@tonic-gate } 36927c478bd9Sstevel@tonic-gate 36937c478bd9Sstevel@tonic-gate /* vendor-id */ 36947c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 36957c478bd9Sstevel@tonic-gate "vendor-id", cpi->cpi_vendorstr); 36967c478bd9Sstevel@tonic-gate 36977c478bd9Sstevel@tonic-gate if (cpi->cpi_maxeax == 0) { 36987c478bd9Sstevel@tonic-gate return; 36997c478bd9Sstevel@tonic-gate } 37007c478bd9Sstevel@tonic-gate 37017c478bd9Sstevel@tonic-gate /* 37027c478bd9Sstevel@tonic-gate * family, model, and step 37037c478bd9Sstevel@tonic-gate */ 37047c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 37057c478bd9Sstevel@tonic-gate "family", CPI_FAMILY(cpi)); 37067c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 37077c478bd9Sstevel@tonic-gate "cpu-model", CPI_MODEL(cpi)); 37087c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 37097c478bd9Sstevel@tonic-gate "stepping-id", CPI_STEP(cpi)); 37107c478bd9Sstevel@tonic-gate 37117c478bd9Sstevel@tonic-gate /* type */ 37127c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 37137c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 37147c478bd9Sstevel@tonic-gate create = 1; 37157c478bd9Sstevel@tonic-gate break; 37167c478bd9Sstevel@tonic-gate default: 37177c478bd9Sstevel@tonic-gate create = 0; 37187c478bd9Sstevel@tonic-gate break; 37197c478bd9Sstevel@tonic-gate } 37207c478bd9Sstevel@tonic-gate if (create) 37217c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 37227c478bd9Sstevel@tonic-gate "type", CPI_TYPE(cpi)); 37237c478bd9Sstevel@tonic-gate 37247c478bd9Sstevel@tonic-gate /* ext-family */ 37257c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 37267c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 37277c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 37287c478bd9Sstevel@tonic-gate create = cpi->cpi_family >= 0xf; 37297c478bd9Sstevel@tonic-gate break; 37307c478bd9Sstevel@tonic-gate default: 37317c478bd9Sstevel@tonic-gate create = 0; 37327c478bd9Sstevel@tonic-gate break; 37337c478bd9Sstevel@tonic-gate } 37347c478bd9Sstevel@tonic-gate if (create) 37357c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 37367c478bd9Sstevel@tonic-gate "ext-family", CPI_FAMILY_XTD(cpi)); 37377c478bd9Sstevel@tonic-gate 37387c478bd9Sstevel@tonic-gate /* ext-model */ 37397c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 37407c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 374163d3f7dfSkk208521 create = IS_EXTENDED_MODEL_INTEL(cpi); 374268c91426Sdmick break; 37437c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 3744ee88d2b9Skchow create = CPI_FAMILY(cpi) == 0xf; 37457c478bd9Sstevel@tonic-gate break; 37467c478bd9Sstevel@tonic-gate default: 37477c478bd9Sstevel@tonic-gate create = 0; 37487c478bd9Sstevel@tonic-gate break; 37497c478bd9Sstevel@tonic-gate } 37507c478bd9Sstevel@tonic-gate if (create) 37517c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 37527c478bd9Sstevel@tonic-gate "ext-model", CPI_MODEL_XTD(cpi)); 37537c478bd9Sstevel@tonic-gate 37547c478bd9Sstevel@tonic-gate /* generation */ 37557c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 37567c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 37577c478bd9Sstevel@tonic-gate /* 37587c478bd9Sstevel@tonic-gate * AMD K5 model 1 was the first part to support this 37597c478bd9Sstevel@tonic-gate */ 37607c478bd9Sstevel@tonic-gate create = cpi->cpi_xmaxeax >= 0x80000001; 37617c478bd9Sstevel@tonic-gate break; 37627c478bd9Sstevel@tonic-gate default: 37637c478bd9Sstevel@tonic-gate create = 0; 37647c478bd9Sstevel@tonic-gate break; 37657c478bd9Sstevel@tonic-gate } 37667c478bd9Sstevel@tonic-gate if (create) 37677c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 37687c478bd9Sstevel@tonic-gate "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 37697c478bd9Sstevel@tonic-gate 37707c478bd9Sstevel@tonic-gate /* brand-id */ 37717c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 37727c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 37737c478bd9Sstevel@tonic-gate /* 37747c478bd9Sstevel@tonic-gate * brand id first appeared on Pentium III Xeon model 8, 37757c478bd9Sstevel@tonic-gate * and Celeron model 8 processors and Opteron 37767c478bd9Sstevel@tonic-gate */ 37777c478bd9Sstevel@tonic-gate create = cpi->cpi_family > 6 || 37787c478bd9Sstevel@tonic-gate (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 37797c478bd9Sstevel@tonic-gate break; 37807c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 37817c478bd9Sstevel@tonic-gate create = cpi->cpi_family >= 0xf; 37827c478bd9Sstevel@tonic-gate break; 37837c478bd9Sstevel@tonic-gate default: 37847c478bd9Sstevel@tonic-gate create = 0; 37857c478bd9Sstevel@tonic-gate break; 37867c478bd9Sstevel@tonic-gate } 37877c478bd9Sstevel@tonic-gate if (create && cpi->cpi_brandid != 0) { 37887c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 37897c478bd9Sstevel@tonic-gate "brand-id", cpi->cpi_brandid); 37907c478bd9Sstevel@tonic-gate } 37917c478bd9Sstevel@tonic-gate 37927c478bd9Sstevel@tonic-gate /* chunks, and apic-id */ 37937c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 37947c478bd9Sstevel@tonic-gate /* 37957c478bd9Sstevel@tonic-gate * first available on Pentium IV and Opteron (K8) 37967c478bd9Sstevel@tonic-gate */ 37975ff02082Sdmick case X86_VENDOR_Intel: 37985ff02082Sdmick create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 37995ff02082Sdmick break; 38005ff02082Sdmick case X86_VENDOR_AMD: 38017c478bd9Sstevel@tonic-gate create = cpi->cpi_family >= 0xf; 38027c478bd9Sstevel@tonic-gate break; 38037c478bd9Sstevel@tonic-gate default: 38047c478bd9Sstevel@tonic-gate create = 0; 38057c478bd9Sstevel@tonic-gate break; 38067c478bd9Sstevel@tonic-gate } 38077c478bd9Sstevel@tonic-gate if (create) { 38087c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 38097c478bd9Sstevel@tonic-gate "chunks", CPI_CHUNKS(cpi)); 38107c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3811b6917abeSmishra "apic-id", cpi->cpi_apicid); 38127aec1d6eScindi if (cpi->cpi_chipid >= 0) { 38137c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 38147c478bd9Sstevel@tonic-gate "chip#", cpi->cpi_chipid); 38157aec1d6eScindi (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 38167aec1d6eScindi "clog#", cpi->cpi_clogid); 38177aec1d6eScindi } 38187c478bd9Sstevel@tonic-gate } 38197c478bd9Sstevel@tonic-gate 38207c478bd9Sstevel@tonic-gate /* cpuid-features */ 38217c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 38227c478bd9Sstevel@tonic-gate "cpuid-features", CPI_FEATURES_EDX(cpi)); 38237c478bd9Sstevel@tonic-gate 38247c478bd9Sstevel@tonic-gate 38257c478bd9Sstevel@tonic-gate /* cpuid-features-ecx */ 38267c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 38277c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 38285ff02082Sdmick create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 38297c478bd9Sstevel@tonic-gate break; 38307c478bd9Sstevel@tonic-gate default: 38317c478bd9Sstevel@tonic-gate create = 0; 38327c478bd9Sstevel@tonic-gate break; 38337c478bd9Sstevel@tonic-gate } 38347c478bd9Sstevel@tonic-gate if (create) 38357c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 38367c478bd9Sstevel@tonic-gate "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 38377c478bd9Sstevel@tonic-gate 38387c478bd9Sstevel@tonic-gate /* ext-cpuid-features */ 38397c478bd9Sstevel@tonic-gate switch (cpi->cpi_vendor) { 38405ff02082Sdmick case X86_VENDOR_Intel: 38417c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 38427c478bd9Sstevel@tonic-gate case X86_VENDOR_Cyrix: 38437c478bd9Sstevel@tonic-gate case X86_VENDOR_TM: 38447c478bd9Sstevel@tonic-gate case X86_VENDOR_Centaur: 38457c478bd9Sstevel@tonic-gate create = cpi->cpi_xmaxeax >= 0x80000001; 38467c478bd9Sstevel@tonic-gate break; 38477c478bd9Sstevel@tonic-gate default: 38487c478bd9Sstevel@tonic-gate create = 0; 38497c478bd9Sstevel@tonic-gate break; 38507c478bd9Sstevel@tonic-gate } 38515ff02082Sdmick if (create) { 38527c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 38537c478bd9Sstevel@tonic-gate "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 38545ff02082Sdmick (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 38555ff02082Sdmick "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 38565ff02082Sdmick } 38577c478bd9Sstevel@tonic-gate 38587c478bd9Sstevel@tonic-gate /* 38597c478bd9Sstevel@tonic-gate * Brand String first appeared in Intel Pentium IV, AMD K5 38607c478bd9Sstevel@tonic-gate * model 1, and Cyrix GXm. On earlier models we try and 38617c478bd9Sstevel@tonic-gate * simulate something similar .. so this string should always 38627c478bd9Sstevel@tonic-gate * same -something- about the processor, however lame. 38637c478bd9Sstevel@tonic-gate */ 38647c478bd9Sstevel@tonic-gate (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 38657c478bd9Sstevel@tonic-gate "brand-string", cpi->cpi_brandstr); 38667c478bd9Sstevel@tonic-gate 38677c478bd9Sstevel@tonic-gate /* 38687c478bd9Sstevel@tonic-gate * Finally, cache and tlb information 38697c478bd9Sstevel@tonic-gate */ 38707c478bd9Sstevel@tonic-gate switch (x86_which_cacheinfo(cpi)) { 38717c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 38727c478bd9Sstevel@tonic-gate intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 38737c478bd9Sstevel@tonic-gate break; 38747c478bd9Sstevel@tonic-gate case X86_VENDOR_Cyrix: 38757c478bd9Sstevel@tonic-gate cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 38767c478bd9Sstevel@tonic-gate break; 38777c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 38787c478bd9Sstevel@tonic-gate amd_cache_info(cpi, cpu_devi); 38797c478bd9Sstevel@tonic-gate break; 38807c478bd9Sstevel@tonic-gate default: 38817c478bd9Sstevel@tonic-gate break; 38827c478bd9Sstevel@tonic-gate } 38837c478bd9Sstevel@tonic-gate } 38847c478bd9Sstevel@tonic-gate 38857c478bd9Sstevel@tonic-gate struct l2info { 38867c478bd9Sstevel@tonic-gate int *l2i_csz; 38877c478bd9Sstevel@tonic-gate int *l2i_lsz; 38887c478bd9Sstevel@tonic-gate int *l2i_assoc; 38897c478bd9Sstevel@tonic-gate int l2i_ret; 38907c478bd9Sstevel@tonic-gate }; 38917c478bd9Sstevel@tonic-gate 38927c478bd9Sstevel@tonic-gate /* 38937c478bd9Sstevel@tonic-gate * A cacheinfo walker that fetches the size, line-size and associativity 38947c478bd9Sstevel@tonic-gate * of the L2 cache 38957c478bd9Sstevel@tonic-gate */ 38967c478bd9Sstevel@tonic-gate static int 38977c478bd9Sstevel@tonic-gate intel_l2cinfo(void *arg, const struct cachetab *ct) 38987c478bd9Sstevel@tonic-gate { 38997c478bd9Sstevel@tonic-gate struct l2info *l2i = arg; 39007c478bd9Sstevel@tonic-gate int *ip; 39017c478bd9Sstevel@tonic-gate 39027c478bd9Sstevel@tonic-gate if (ct->ct_label != l2_cache_str && 39037c478bd9Sstevel@tonic-gate ct->ct_label != sl2_cache_str) 39047c478bd9Sstevel@tonic-gate return (0); /* not an L2 -- keep walking */ 39057c478bd9Sstevel@tonic-gate 39067c478bd9Sstevel@tonic-gate if ((ip = l2i->l2i_csz) != NULL) 39077c478bd9Sstevel@tonic-gate *ip = ct->ct_size; 39087c478bd9Sstevel@tonic-gate if ((ip = l2i->l2i_lsz) != NULL) 39097c478bd9Sstevel@tonic-gate *ip = ct->ct_line_size; 39107c478bd9Sstevel@tonic-gate if ((ip = l2i->l2i_assoc) != NULL) 39117c478bd9Sstevel@tonic-gate *ip = ct->ct_assoc; 39127c478bd9Sstevel@tonic-gate l2i->l2i_ret = ct->ct_size; 39137c478bd9Sstevel@tonic-gate return (1); /* was an L2 -- terminate walk */ 39147c478bd9Sstevel@tonic-gate } 39157c478bd9Sstevel@tonic-gate 3916606303c9Skchow /* 3917606303c9Skchow * AMD L2/L3 Cache and TLB Associativity Field Definition: 3918606303c9Skchow * 3919606303c9Skchow * Unlike the associativity for the L1 cache and tlb where the 8 bit 3920606303c9Skchow * value is the associativity, the associativity for the L2 cache and 3921606303c9Skchow * tlb is encoded in the following table. The 4 bit L2 value serves as 3922606303c9Skchow * an index into the amd_afd[] array to determine the associativity. 3923606303c9Skchow * -1 is undefined. 0 is fully associative. 3924606303c9Skchow */ 3925606303c9Skchow 3926606303c9Skchow static int amd_afd[] = 3927606303c9Skchow {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3928606303c9Skchow 39297c478bd9Sstevel@tonic-gate static void 39307c478bd9Sstevel@tonic-gate amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 39317c478bd9Sstevel@tonic-gate { 39328949bcd6Sandrei struct cpuid_regs *cp; 39337c478bd9Sstevel@tonic-gate uint_t size, assoc; 3934606303c9Skchow int i; 39357c478bd9Sstevel@tonic-gate int *ip; 39367c478bd9Sstevel@tonic-gate 39377c478bd9Sstevel@tonic-gate if (cpi->cpi_xmaxeax < 0x80000006) 39387c478bd9Sstevel@tonic-gate return; 39397c478bd9Sstevel@tonic-gate cp = &cpi->cpi_extd[6]; 39407c478bd9Sstevel@tonic-gate 3941606303c9Skchow if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 39427c478bd9Sstevel@tonic-gate (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 39437c478bd9Sstevel@tonic-gate uint_t cachesz = size * 1024; 3944606303c9Skchow assoc = amd_afd[i]; 39457c478bd9Sstevel@tonic-gate 3946606303c9Skchow ASSERT(assoc != -1); 39477c478bd9Sstevel@tonic-gate 39487c478bd9Sstevel@tonic-gate if ((ip = l2i->l2i_csz) != NULL) 39497c478bd9Sstevel@tonic-gate *ip = cachesz; 39507c478bd9Sstevel@tonic-gate if ((ip = l2i->l2i_lsz) != NULL) 39517c478bd9Sstevel@tonic-gate *ip = BITX(cp->cp_ecx, 7, 0); 39527c478bd9Sstevel@tonic-gate if ((ip = l2i->l2i_assoc) != NULL) 39537c478bd9Sstevel@tonic-gate *ip = assoc; 39547c478bd9Sstevel@tonic-gate l2i->l2i_ret = cachesz; 39557c478bd9Sstevel@tonic-gate } 39567c478bd9Sstevel@tonic-gate } 39577c478bd9Sstevel@tonic-gate 39587c478bd9Sstevel@tonic-gate int 39597c478bd9Sstevel@tonic-gate getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 39607c478bd9Sstevel@tonic-gate { 39617c478bd9Sstevel@tonic-gate struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 39627c478bd9Sstevel@tonic-gate struct l2info __l2info, *l2i = &__l2info; 39637c478bd9Sstevel@tonic-gate 39647c478bd9Sstevel@tonic-gate l2i->l2i_csz = csz; 39657c478bd9Sstevel@tonic-gate l2i->l2i_lsz = lsz; 39667c478bd9Sstevel@tonic-gate l2i->l2i_assoc = assoc; 39677c478bd9Sstevel@tonic-gate l2i->l2i_ret = -1; 39687c478bd9Sstevel@tonic-gate 39697c478bd9Sstevel@tonic-gate switch (x86_which_cacheinfo(cpi)) { 39707c478bd9Sstevel@tonic-gate case X86_VENDOR_Intel: 39717c478bd9Sstevel@tonic-gate intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 39727c478bd9Sstevel@tonic-gate break; 39737c478bd9Sstevel@tonic-gate case X86_VENDOR_Cyrix: 39747c478bd9Sstevel@tonic-gate cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 39757c478bd9Sstevel@tonic-gate break; 39767c478bd9Sstevel@tonic-gate case X86_VENDOR_AMD: 39777c478bd9Sstevel@tonic-gate amd_l2cacheinfo(cpi, l2i); 39787c478bd9Sstevel@tonic-gate break; 39797c478bd9Sstevel@tonic-gate default: 39807c478bd9Sstevel@tonic-gate break; 39817c478bd9Sstevel@tonic-gate } 39827c478bd9Sstevel@tonic-gate return (l2i->l2i_ret); 39837c478bd9Sstevel@tonic-gate } 3984f98fbcecSbholler 3985843e1988Sjohnlev #if !defined(__xpv) 3986843e1988Sjohnlev 39875b8a6efeSbholler uint32_t * 39885b8a6efeSbholler cpuid_mwait_alloc(cpu_t *cpu) 39895b8a6efeSbholler { 39905b8a6efeSbholler uint32_t *ret; 39915b8a6efeSbholler size_t mwait_size; 39925b8a6efeSbholler 3993a3114836SGerry Liu ASSERT(cpuid_checkpass(CPU, 2)); 39945b8a6efeSbholler 3995a3114836SGerry Liu mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 39965b8a6efeSbholler if (mwait_size == 0) 39975b8a6efeSbholler return (NULL); 39985b8a6efeSbholler 39995b8a6efeSbholler /* 40005b8a6efeSbholler * kmem_alloc() returns cache line size aligned data for mwait_size 40015b8a6efeSbholler * allocations. mwait_size is currently cache line sized. Neither 40025b8a6efeSbholler * of these implementation details are guarantied to be true in the 40035b8a6efeSbholler * future. 40045b8a6efeSbholler * 40055b8a6efeSbholler * First try allocating mwait_size as kmem_alloc() currently returns 40065b8a6efeSbholler * correctly aligned memory. If kmem_alloc() does not return 40075b8a6efeSbholler * mwait_size aligned memory, then use mwait_size ROUNDUP. 40085b8a6efeSbholler * 40095b8a6efeSbholler * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 40105b8a6efeSbholler * decide to free this memory. 40115b8a6efeSbholler */ 40125b8a6efeSbholler ret = kmem_zalloc(mwait_size, KM_SLEEP); 40135b8a6efeSbholler if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 40145b8a6efeSbholler cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 40155b8a6efeSbholler cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 40165b8a6efeSbholler *ret = MWAIT_RUNNING; 40175b8a6efeSbholler return (ret); 40185b8a6efeSbholler } else { 40195b8a6efeSbholler kmem_free(ret, mwait_size); 40205b8a6efeSbholler ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 40215b8a6efeSbholler cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 40225b8a6efeSbholler cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 40235b8a6efeSbholler ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 40245b8a6efeSbholler *ret = MWAIT_RUNNING; 40255b8a6efeSbholler return (ret); 40265b8a6efeSbholler } 40275b8a6efeSbholler } 40285b8a6efeSbholler 40295b8a6efeSbholler void 40305b8a6efeSbholler cpuid_mwait_free(cpu_t *cpu) 4031f98fbcecSbholler { 4032a3114836SGerry Liu if (cpu->cpu_m.mcpu_cpi == NULL) { 4033a3114836SGerry Liu return; 4034a3114836SGerry Liu } 40355b8a6efeSbholler 40365b8a6efeSbholler if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 40375b8a6efeSbholler cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 40385b8a6efeSbholler kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 40395b8a6efeSbholler cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 40405b8a6efeSbholler } 40415b8a6efeSbholler 40425b8a6efeSbholler cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 40435b8a6efeSbholler cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 4044f98fbcecSbholler } 4045843e1988Sjohnlev 4046247dbb3dSsudheer void 4047247dbb3dSsudheer patch_tsc_read(int flag) 4048247dbb3dSsudheer { 4049247dbb3dSsudheer size_t cnt; 4050e4b86885SCheng Sean Ye 4051247dbb3dSsudheer switch (flag) { 4052247dbb3dSsudheer case X86_NO_TSC: 4053247dbb3dSsudheer cnt = &_no_rdtsc_end - &_no_rdtsc_start; 40542b0bcb26Ssudheer (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 4055247dbb3dSsudheer break; 4056247dbb3dSsudheer case X86_HAVE_TSCP: 4057247dbb3dSsudheer cnt = &_tscp_end - &_tscp_start; 40582b0bcb26Ssudheer (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 4059247dbb3dSsudheer break; 4060247dbb3dSsudheer case X86_TSC_MFENCE: 4061247dbb3dSsudheer cnt = &_tsc_mfence_end - &_tsc_mfence_start; 40622b0bcb26Ssudheer (void) memcpy((void *)tsc_read, 40632b0bcb26Ssudheer (void *)&_tsc_mfence_start, cnt); 4064247dbb3dSsudheer break; 406515363b27Ssudheer case X86_TSC_LFENCE: 406615363b27Ssudheer cnt = &_tsc_lfence_end - &_tsc_lfence_start; 406715363b27Ssudheer (void) memcpy((void *)tsc_read, 406815363b27Ssudheer (void *)&_tsc_lfence_start, cnt); 406915363b27Ssudheer break; 4070247dbb3dSsudheer default: 4071247dbb3dSsudheer break; 4072247dbb3dSsudheer } 4073247dbb3dSsudheer } 4074247dbb3dSsudheer 40750e751525SEric Saxe int 40760e751525SEric Saxe cpuid_deep_cstates_supported(void) 40770e751525SEric Saxe { 40780e751525SEric Saxe struct cpuid_info *cpi; 40790e751525SEric Saxe struct cpuid_regs regs; 40800e751525SEric Saxe 40810e751525SEric Saxe ASSERT(cpuid_checkpass(CPU, 1)); 40820e751525SEric Saxe 40830e751525SEric Saxe cpi = CPU->cpu_m.mcpu_cpi; 40840e751525SEric Saxe 40850e751525SEric Saxe if (!(x86_feature & X86_CPUID)) 40860e751525SEric Saxe return (0); 40870e751525SEric Saxe 40880e751525SEric Saxe switch (cpi->cpi_vendor) { 40890e751525SEric Saxe case X86_VENDOR_Intel: 40900e751525SEric Saxe if (cpi->cpi_xmaxeax < 0x80000007) 40910e751525SEric Saxe return (0); 40920e751525SEric Saxe 40930e751525SEric Saxe /* 40940e751525SEric Saxe * TSC run at a constant rate in all ACPI C-states? 40950e751525SEric Saxe */ 40960e751525SEric Saxe regs.cp_eax = 0x80000007; 40970e751525SEric Saxe (void) __cpuid_insn(®s); 40980e751525SEric Saxe return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); 40990e751525SEric Saxe 41000e751525SEric Saxe default: 41010e751525SEric Saxe return (0); 41020e751525SEric Saxe } 41030e751525SEric Saxe } 41040e751525SEric Saxe 4105e774b42bSBill Holler #endif /* !__xpv */ 4106e774b42bSBill Holler 4107e774b42bSBill Holler void 4108e774b42bSBill Holler post_startup_cpu_fixups(void) 4109e774b42bSBill Holler { 4110e774b42bSBill Holler #ifndef __xpv 4111e774b42bSBill Holler /* 4112e774b42bSBill Holler * Some AMD processors support C1E state. Entering this state will 4113e774b42bSBill Holler * cause the local APIC timer to stop, which we can't deal with at 4114e774b42bSBill Holler * this time. 4115e774b42bSBill Holler */ 4116e774b42bSBill Holler if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { 4117e774b42bSBill Holler on_trap_data_t otd; 4118e774b42bSBill Holler uint64_t reg; 4119e774b42bSBill Holler 4120e774b42bSBill Holler if (!on_trap(&otd, OT_DATA_ACCESS)) { 4121e774b42bSBill Holler reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); 4122e774b42bSBill Holler /* Disable C1E state if it is enabled by BIOS */ 4123e774b42bSBill Holler if ((reg >> AMD_ACTONCMPHALT_SHIFT) & 4124e774b42bSBill Holler AMD_ACTONCMPHALT_MASK) { 4125e774b42bSBill Holler reg &= ~(AMD_ACTONCMPHALT_MASK << 4126e774b42bSBill Holler AMD_ACTONCMPHALT_SHIFT); 4127e774b42bSBill Holler wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); 4128e774b42bSBill Holler } 4129e774b42bSBill Holler } 4130e774b42bSBill Holler no_trap(); 4131e774b42bSBill Holler } 4132e774b42bSBill Holler #endif /* !__xpv */ 4133e774b42bSBill Holler } 4134e774b42bSBill Holler 4135cef70d2cSBill Holler /* 4136cef70d2cSBill Holler * Starting with the Westmere processor the local 4137cef70d2cSBill Holler * APIC timer will continue running in all C-states, 4138cef70d2cSBill Holler * including the deepest C-states. 4139cef70d2cSBill Holler */ 4140cef70d2cSBill Holler int 4141cef70d2cSBill Holler cpuid_arat_supported(void) 4142cef70d2cSBill Holler { 4143cef70d2cSBill Holler struct cpuid_info *cpi; 4144cef70d2cSBill Holler struct cpuid_regs regs; 4145cef70d2cSBill Holler 4146cef70d2cSBill Holler ASSERT(cpuid_checkpass(CPU, 1)); 4147cef70d2cSBill Holler ASSERT(x86_feature & X86_CPUID); 4148cef70d2cSBill Holler 4149cef70d2cSBill Holler cpi = CPU->cpu_m.mcpu_cpi; 4150cef70d2cSBill Holler 4151cef70d2cSBill Holler switch (cpi->cpi_vendor) { 4152cef70d2cSBill Holler case X86_VENDOR_Intel: 4153cef70d2cSBill Holler /* 4154cef70d2cSBill Holler * Always-running Local APIC Timer is 4155cef70d2cSBill Holler * indicated by CPUID.6.EAX[2]. 4156cef70d2cSBill Holler */ 4157cef70d2cSBill Holler if (cpi->cpi_maxeax >= 6) { 4158cef70d2cSBill Holler regs.cp_eax = 6; 4159cef70d2cSBill Holler (void) cpuid_insn(NULL, ®s); 4160cef70d2cSBill Holler return (regs.cp_eax & CPUID_CSTATE_ARAT); 4161cef70d2cSBill Holler } else { 4162cef70d2cSBill Holler return (0); 4163cef70d2cSBill Holler } 4164cef70d2cSBill Holler default: 4165cef70d2cSBill Holler return (0); 4166cef70d2cSBill Holler } 4167cef70d2cSBill Holler } 4168cef70d2cSBill Holler 4169f21ed392Saubrey.li@intel.com /* 4170f21ed392Saubrey.li@intel.com * Check support for Intel ENERGY_PERF_BIAS feature 4171f21ed392Saubrey.li@intel.com */ 4172f21ed392Saubrey.li@intel.com int 4173f21ed392Saubrey.li@intel.com cpuid_iepb_supported(struct cpu *cp) 4174f21ed392Saubrey.li@intel.com { 4175f21ed392Saubrey.li@intel.com struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi; 4176f21ed392Saubrey.li@intel.com struct cpuid_regs regs; 4177f21ed392Saubrey.li@intel.com 4178f21ed392Saubrey.li@intel.com ASSERT(cpuid_checkpass(cp, 1)); 4179f21ed392Saubrey.li@intel.com 4180f21ed392Saubrey.li@intel.com if (!(x86_feature & X86_CPUID) || !(x86_feature & X86_MSR)) { 4181f21ed392Saubrey.li@intel.com return (0); 4182f21ed392Saubrey.li@intel.com } 4183f21ed392Saubrey.li@intel.com 4184f21ed392Saubrey.li@intel.com /* 4185f21ed392Saubrey.li@intel.com * Intel ENERGY_PERF_BIAS MSR is indicated by 4186f21ed392Saubrey.li@intel.com * capability bit CPUID.6.ECX.3 4187f21ed392Saubrey.li@intel.com */ 4188f21ed392Saubrey.li@intel.com if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6)) 4189f21ed392Saubrey.li@intel.com return (0); 4190f21ed392Saubrey.li@intel.com 4191f21ed392Saubrey.li@intel.com regs.cp_eax = 0x6; 4192f21ed392Saubrey.li@intel.com (void) cpuid_insn(NULL, ®s); 4193f21ed392Saubrey.li@intel.com return (regs.cp_ecx & CPUID_EPB_SUPPORT); 4194f21ed392Saubrey.li@intel.com } 4195f21ed392Saubrey.li@intel.com 419622cc0e45SBill Holler #if defined(__amd64) && !defined(__xpv) 419722cc0e45SBill Holler /* 419822cc0e45SBill Holler * Patch in versions of bcopy for high performance Intel Nhm processors 419922cc0e45SBill Holler * and later... 420022cc0e45SBill Holler */ 420122cc0e45SBill Holler void 420222cc0e45SBill Holler patch_memops(uint_t vendor) 420322cc0e45SBill Holler { 420422cc0e45SBill Holler size_t cnt, i; 420522cc0e45SBill Holler caddr_t to, from; 420622cc0e45SBill Holler 420722cc0e45SBill Holler if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) { 420822cc0e45SBill Holler cnt = &bcopy_patch_end - &bcopy_patch_start; 420922cc0e45SBill Holler to = &bcopy_ck_size; 421022cc0e45SBill Holler from = &bcopy_patch_start; 421122cc0e45SBill Holler for (i = 0; i < cnt; i++) { 421222cc0e45SBill Holler *to++ = *from++; 421322cc0e45SBill Holler } 421422cc0e45SBill Holler } 421522cc0e45SBill Holler } 421622cc0e45SBill Holler #endif /* __amd64 && !__xpv */ 4217*2d2efdc6SVuong Nguyen 4218*2d2efdc6SVuong Nguyen /* 4219*2d2efdc6SVuong Nguyen * This function finds the number of bits to represent the number of cores per 4220*2d2efdc6SVuong Nguyen * chip and the number of strands per core for the Intel platforms. 4221*2d2efdc6SVuong Nguyen * It re-uses the x2APIC cpuid code of the cpuid_pass2(). 4222*2d2efdc6SVuong Nguyen */ 4223*2d2efdc6SVuong Nguyen void 4224*2d2efdc6SVuong Nguyen cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits) 4225*2d2efdc6SVuong Nguyen { 4226*2d2efdc6SVuong Nguyen struct cpuid_regs regs; 4227*2d2efdc6SVuong Nguyen struct cpuid_regs *cp = ®s; 4228*2d2efdc6SVuong Nguyen 4229*2d2efdc6SVuong Nguyen if (vendor != X86_VENDOR_Intel) { 4230*2d2efdc6SVuong Nguyen return; 4231*2d2efdc6SVuong Nguyen } 4232*2d2efdc6SVuong Nguyen 4233*2d2efdc6SVuong Nguyen /* if the cpuid level is 0xB, extended topo is available. */ 4234*2d2efdc6SVuong Nguyen cp->cp_eax = 0; 4235*2d2efdc6SVuong Nguyen if (__cpuid_insn(cp) >= 0xB) { 4236*2d2efdc6SVuong Nguyen 4237*2d2efdc6SVuong Nguyen cp->cp_eax = 0xB; 4238*2d2efdc6SVuong Nguyen cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 4239*2d2efdc6SVuong Nguyen (void) __cpuid_insn(cp); 4240*2d2efdc6SVuong Nguyen 4241*2d2efdc6SVuong Nguyen /* 4242*2d2efdc6SVuong Nguyen * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 4243*2d2efdc6SVuong Nguyen * indicates that the extended topology enumeration leaf is 4244*2d2efdc6SVuong Nguyen * available. 4245*2d2efdc6SVuong Nguyen */ 4246*2d2efdc6SVuong Nguyen if (cp->cp_ebx) { 4247*2d2efdc6SVuong Nguyen uint_t coreid_shift = 0; 4248*2d2efdc6SVuong Nguyen uint_t chipid_shift = 0; 4249*2d2efdc6SVuong Nguyen uint_t i; 4250*2d2efdc6SVuong Nguyen uint_t level; 4251*2d2efdc6SVuong Nguyen 4252*2d2efdc6SVuong Nguyen for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 4253*2d2efdc6SVuong Nguyen cp->cp_eax = 0xB; 4254*2d2efdc6SVuong Nguyen cp->cp_ecx = i; 4255*2d2efdc6SVuong Nguyen 4256*2d2efdc6SVuong Nguyen (void) __cpuid_insn(cp); 4257*2d2efdc6SVuong Nguyen level = CPI_CPU_LEVEL_TYPE(cp); 4258*2d2efdc6SVuong Nguyen 4259*2d2efdc6SVuong Nguyen if (level == 1) { 4260*2d2efdc6SVuong Nguyen /* 4261*2d2efdc6SVuong Nguyen * Thread level processor topology 4262*2d2efdc6SVuong Nguyen * Number of bits shift right APIC ID 4263*2d2efdc6SVuong Nguyen * to get the coreid. 4264*2d2efdc6SVuong Nguyen */ 4265*2d2efdc6SVuong Nguyen coreid_shift = BITX(cp->cp_eax, 4, 0); 4266*2d2efdc6SVuong Nguyen } else if (level == 2) { 4267*2d2efdc6SVuong Nguyen /* 4268*2d2efdc6SVuong Nguyen * Core level processor topology 4269*2d2efdc6SVuong Nguyen * Number of bits shift right APIC ID 4270*2d2efdc6SVuong Nguyen * to get the chipid. 4271*2d2efdc6SVuong Nguyen */ 4272*2d2efdc6SVuong Nguyen chipid_shift = BITX(cp->cp_eax, 4, 0); 4273*2d2efdc6SVuong Nguyen } 4274*2d2efdc6SVuong Nguyen } 4275*2d2efdc6SVuong Nguyen 4276*2d2efdc6SVuong Nguyen if (coreid_shift > 0 && chipid_shift > coreid_shift) { 4277*2d2efdc6SVuong Nguyen *strand_nbits = coreid_shift; 4278*2d2efdc6SVuong Nguyen *core_nbits = chipid_shift - coreid_shift; 4279*2d2efdc6SVuong Nguyen } 4280*2d2efdc6SVuong Nguyen } 4281*2d2efdc6SVuong Nguyen } 4282*2d2efdc6SVuong Nguyen } 4283