xref: /titanic_52/usr/src/uts/i86pc/ml/ia32.il (revision 4e5fbfeda6c7dee3dd62538723087263e6de8e18)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #pragma ident	"%Z%%M%	%I%	%E% SMI"
28 
29 /
30 / Inline functions specific to the i86pc kernel running on bare metal.
31 /
32 
33 /
34 / return value of cr3 register
35 /
36 	.inline	getcr3,0
37 	movl	%cr3, %eax
38 	.end
39 
40 /
41 / reload cr3 register with its current value
42 /
43 	.inline	reload_cr3,0
44 	movl	%cr3, %eax
45 	movl	%eax, %cr3
46 	.end
47 
48 /*
49  * Put a new value into cr3 (page table base register
50  *	void setcr3(void *value)
51  */
52 	.inline	setcr3,4
53 	movl	(%esp), %eax
54 	movl	%eax, %cr3
55 	.end
56 
57 /
58 / enable interrupts
59 /
60 	.inline	sti,0
61 	sti
62 	.end
63 
64 /
65 / disable interrupts
66 /
67 	.inline cli,0
68 	cli
69 	.end
70 
71 /
72 / disable interrupts and return value describing if interrupts were enabled
73 /
74 	.inline	clear_int_flag,0
75 	pushfl
76 	cli
77 	popl	%eax
78 	.end
79 
80 	.inline	intr_clear,0
81 	pushfl
82 	cli
83 	popl	%eax
84 	.end
85 
86 /
87 / return the flags register
88 /
89 	.inline getflags,0
90 	pushfl
91 	popl	%eax
92 	.end
93 
94 /
95 / restore interrupt enable flag to value returned from 'clear_int_flag' above
96 /
97 	.inline restore_int_flag,4
98 	pushl	(%esp)
99 	popfl
100 	.end
101 
102 	.inline intr_restore,4
103 	pushl	(%esp)
104 	popfl
105 	.end
106 
107 /
108 / in and out
109 /
110 	.inline	inb,4
111 	movl	(%esp), %edx
112 	xorl    %eax, %eax
113 	inb	(%dx)
114 	.end
115 
116 	.inline	inw,4
117 	movl	(%esp), %edx
118 	xorl    %eax, %eax
119 	inw	(%dx)
120 	.end
121 
122 	.inline	inl,4
123 	movl	(%esp), %edx
124 	xorl    %eax, %eax
125 	inl	(%dx)
126 	.end
127 
128 	.inline	outb,8
129 	movl	(%esp), %edx
130 	movl    4(%esp), %eax
131 	outb	(%dx)
132 	.end
133 
134 	.inline	outw,8
135 	movl	(%esp), %edx
136 	movl    4(%esp), %eax
137 	outw	(%dx)
138 	.end
139 
140 	.inline	outl,8
141 	movl	(%esp), %edx
142 	movl    4(%esp), %eax
143 	outl	(%dx)
144 	.end
145 
146 /*
147  * Invalidate TLB translation to 1 page.
148  *	void mmu_tlbflush_entry(void *addr)
149  */
150 	.inline	mmu_tlbflush_entry,4
151 	movl	(%esp), %eax
152 	invlpg	(%eax)
153 	.end
154 
155 /*
156  * Read Time Stamp Counter
157  * uint64_t tsc_read();
158  *
159  * usage:
160  * uint64_t cycles = tsc_read();
161  */
162 	.inline	tsc_read, 0
163 	rdtsc				/ %edx:%eax = RDTSC
164 	.end
165 
166 /*
167  * Call the halt instruction. This will put the CPU to sleep until
168  * it is again awoken via an interrupt.
169  * This function should be called with interrupts already disabled
170  * for the CPU.
171  * Note that "sti" will only enable interrupts at the end of the
172  * subsequent instruction...in this case: "hlt".
173  */
174 	.inline i86_halt,0
175 	sti
176 	hlt
177 	.end
178 
179 /*
180  * execute the bsrw instruction
181  *	int bsrw_insn(uint16_t)
182  */
183 	.inline	bsrw_insn,4
184 	xorl	%eax, %eax
185 	movw	(%esp), %cx
186 	bsrw	%cx, %ax
187 	.end
188