1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 /* 26 * Copyright (c) 2010, Intel Corporation. 27 * All rights reserved. 28 */ 29 /* 30 * Copyright (c) 2013, Joyent, Inc. All rights reserved. 31 */ 32 33 /* 34 * To understand how the pcplusmp module interacts with the interrupt subsystem 35 * read the theory statement in uts/i86pc/os/intr.c. 36 */ 37 38 /* 39 * PSMI 1.1 extensions are supported only in 2.6 and later versions. 40 * PSMI 1.2 extensions are supported only in 2.7 and later versions. 41 * PSMI 1.3 and 1.4 extensions are supported in Solaris 10. 42 * PSMI 1.5 extensions are supported in Solaris Nevada. 43 * PSMI 1.6 extensions are supported in Solaris Nevada. 44 * PSMI 1.7 extensions are supported in Solaris Nevada. 45 */ 46 #define PSMI_1_7 47 48 #include <sys/processor.h> 49 #include <sys/time.h> 50 #include <sys/psm.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/cram.h> 53 #include <sys/acpi/acpi.h> 54 #include <sys/acpica.h> 55 #include <sys/psm_common.h> 56 #include <sys/apic.h> 57 #include <sys/pit.h> 58 #include <sys/ddi.h> 59 #include <sys/sunddi.h> 60 #include <sys/ddi_impldefs.h> 61 #include <sys/pci.h> 62 #include <sys/promif.h> 63 #include <sys/x86_archext.h> 64 #include <sys/cpc_impl.h> 65 #include <sys/uadmin.h> 66 #include <sys/panic.h> 67 #include <sys/debug.h> 68 #include <sys/archsystm.h> 69 #include <sys/trap.h> 70 #include <sys/machsystm.h> 71 #include <sys/sysmacros.h> 72 #include <sys/cpuvar.h> 73 #include <sys/rm_platter.h> 74 #include <sys/privregs.h> 75 #include <sys/note.h> 76 #include <sys/pci_intr_lib.h> 77 #include <sys/spl.h> 78 #include <sys/clock.h> 79 #include <sys/cyclic.h> 80 #include <sys/dditypes.h> 81 #include <sys/sunddi.h> 82 #include <sys/x_call.h> 83 #include <sys/reboot.h> 84 #include <sys/hpet.h> 85 #include <sys/apic_common.h> 86 #include <sys/apic_timer.h> 87 88 /* 89 * Local Function Prototypes 90 */ 91 static void apic_init_intr(void); 92 93 /* 94 * standard MP entries 95 */ 96 static int apic_probe(void); 97 static int apic_getclkirq(int ipl); 98 static void apic_init(void); 99 static void apic_picinit(void); 100 static int apic_post_cpu_start(void); 101 static int apic_intr_enter(int ipl, int *vect); 102 static void apic_setspl(int ipl); 103 static void x2apic_setspl(int ipl); 104 static int apic_addspl(int ipl, int vector, int min_ipl, int max_ipl); 105 static int apic_delspl(int ipl, int vector, int min_ipl, int max_ipl); 106 static int apic_disable_intr(processorid_t cpun); 107 static void apic_enable_intr(processorid_t cpun); 108 static int apic_get_ipivect(int ipl, int type); 109 static void apic_post_cyclic_setup(void *arg); 110 111 /* 112 * The following vector assignments influence the value of ipltopri and 113 * vectortoipl. Note that vectors 0 - 0x1f are not used. We can program 114 * idle to 0 and IPL 0 to 0xf to differentiate idle in case 115 * we care to do so in future. Note some IPLs which are rarely used 116 * will share the vector ranges and heavily used IPLs (5 and 6) have 117 * a wide range. 118 * 119 * This array is used to initialize apic_ipls[] (in apic_init()). 120 * 121 * IPL Vector range. as passed to intr_enter 122 * 0 none. 123 * 1,2,3 0x20-0x2f 0x0-0xf 124 * 4 0x30-0x3f 0x10-0x1f 125 * 5 0x40-0x5f 0x20-0x3f 126 * 6 0x60-0x7f 0x40-0x5f 127 * 7,8,9 0x80-0x8f 0x60-0x6f 128 * 10 0x90-0x9f 0x70-0x7f 129 * 11 0xa0-0xaf 0x80-0x8f 130 * ... ... 131 * 15 0xe0-0xef 0xc0-0xcf 132 * 15 0xf0-0xff 0xd0-0xdf 133 */ 134 uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL] = { 135 3, 4, 5, 5, 6, 6, 9, 10, 11, 12, 13, 14, 15, 15 136 }; 137 /* 138 * The ipl of an ISR at vector X is apic_vectortoipl[X>>4] 139 * NOTE that this is vector as passed into intr_enter which is 140 * programmed vector - 0x20 (APIC_BASE_VECT) 141 */ 142 143 uchar_t apic_ipltopri[MAXIPL + 1]; /* unix ipl to apic pri */ 144 /* The taskpri to be programmed into apic to mask given ipl */ 145 146 /* 147 * Correlation of the hardware vector to the IPL in use, initialized 148 * from apic_vectortoipl[] in apic_init(). The final IPLs may not correlate 149 * to the IPLs in apic_vectortoipl on some systems that share interrupt lines 150 * connected to errata-stricken IOAPICs 151 */ 152 uchar_t apic_ipls[APIC_AVAIL_VECTOR]; 153 154 /* 155 * Patchable global variables. 156 */ 157 int apic_enable_hwsoftint = 0; /* 0 - disable, 1 - enable */ 158 int apic_enable_bind_log = 1; /* 1 - display interrupt binding log */ 159 160 /* 161 * Local static data 162 */ 163 static struct psm_ops apic_ops = { 164 apic_probe, 165 166 apic_init, 167 apic_picinit, 168 apic_intr_enter, 169 apic_intr_exit, 170 apic_setspl, 171 apic_addspl, 172 apic_delspl, 173 apic_disable_intr, 174 apic_enable_intr, 175 (int (*)(int))NULL, /* psm_softlvl_to_irq */ 176 (void (*)(int))NULL, /* psm_set_softintr */ 177 178 apic_set_idlecpu, 179 apic_unset_idlecpu, 180 181 apic_clkinit, 182 apic_getclkirq, 183 (void (*)(void))NULL, /* psm_hrtimeinit */ 184 apic_gethrtime, 185 186 apic_get_next_processorid, 187 apic_cpu_start, 188 apic_post_cpu_start, 189 apic_shutdown, 190 apic_get_ipivect, 191 apic_send_ipi, 192 193 (int (*)(dev_info_t *, int))NULL, /* psm_translate_irq */ 194 (void (*)(int, char *))NULL, /* psm_notify_error */ 195 (void (*)(int))NULL, /* psm_notify_func */ 196 apic_timer_reprogram, 197 apic_timer_enable, 198 apic_timer_disable, 199 apic_post_cyclic_setup, 200 apic_preshutdown, 201 apic_intr_ops, /* Advanced DDI Interrupt framework */ 202 apic_state, /* save, restore apic state for S3 */ 203 apic_cpu_ops, /* CPU control interface. */ 204 }; 205 206 struct psm_ops *psmops = &apic_ops; 207 208 static struct psm_info apic_psm_info = { 209 PSM_INFO_VER01_7, /* version */ 210 PSM_OWN_EXCLUSIVE, /* ownership */ 211 (struct psm_ops *)&apic_ops, /* operation */ 212 APIC_PCPLUSMP_NAME, /* machine name */ 213 "pcplusmp v1.4 compatible", 214 }; 215 216 static void *apic_hdlp; 217 218 /* 219 * apic_let_idle_redistribute can have the following values: 220 * 0 - If clock decremented it from 1 to 0, clock has to call redistribute. 221 * apic_redistribute_lock prevents multiple idle cpus from redistributing 222 */ 223 int apic_num_idle_redistributions = 0; 224 static int apic_let_idle_redistribute = 0; 225 226 /* to gather intr data and redistribute */ 227 static void apic_redistribute_compute(void); 228 229 /* 230 * This is the loadable module wrapper 231 */ 232 233 int 234 _init(void) 235 { 236 if (apic_coarse_hrtime) 237 apic_ops.psm_gethrtime = &apic_gettime; 238 return (psm_mod_init(&apic_hdlp, &apic_psm_info)); 239 } 240 241 int 242 _fini(void) 243 { 244 return (psm_mod_fini(&apic_hdlp, &apic_psm_info)); 245 } 246 247 int 248 _info(struct modinfo *modinfop) 249 { 250 return (psm_mod_info(&apic_hdlp, &apic_psm_info, modinfop)); 251 } 252 253 static int 254 apic_probe(void) 255 { 256 /* check if apix is initialized */ 257 if (apix_enable && apix_loaded()) 258 return (PSM_FAILURE); 259 else 260 apix_enable = 0; /* continue using pcplusmp PSM */ 261 262 return (apic_probe_common(apic_psm_info.p_mach_idstring)); 263 } 264 265 static uchar_t 266 apic_xlate_vector_by_irq(uchar_t irq) 267 { 268 if (apic_irq_table[irq] == NULL) 269 return (0); 270 271 return (apic_irq_table[irq]->airq_vector); 272 } 273 274 void 275 apic_init(void) 276 { 277 int i; 278 int j = 1; 279 280 psm_get_ioapicid = apic_get_ioapicid; 281 psm_get_localapicid = apic_get_localapicid; 282 psm_xlate_vector_by_irq = apic_xlate_vector_by_irq; 283 284 apic_ipltopri[0] = APIC_VECTOR_PER_IPL; /* leave 0 for idle */ 285 for (i = 0; i < (APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL); i++) { 286 if ((i < ((APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL) - 1)) && 287 (apic_vectortoipl[i + 1] == apic_vectortoipl[i])) 288 /* get to highest vector at the same ipl */ 289 continue; 290 for (; j <= apic_vectortoipl[i]; j++) { 291 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + 292 APIC_BASE_VECT; 293 } 294 } 295 for (; j < MAXIPL + 1; j++) 296 /* fill up any empty ipltopri slots */ 297 apic_ipltopri[j] = (i << APIC_IPL_SHIFT) + APIC_BASE_VECT; 298 apic_init_common(); 299 300 #if !defined(__amd64) 301 if (cpuid_have_cr8access(CPU)) 302 apic_have_32bit_cr8 = 1; 303 #endif 304 } 305 306 static void 307 apic_init_intr(void) 308 { 309 processorid_t cpun = psm_get_cpu_id(); 310 uint_t nlvt; 311 uint32_t svr = AV_UNIT_ENABLE | APIC_SPUR_INTR; 312 313 apic_reg_ops->apic_write_task_reg(APIC_MASK_ALL); 314 315 if (apic_mode == LOCAL_APIC) { 316 /* 317 * We are running APIC in MMIO mode. 318 */ 319 if (apic_flat_model) { 320 apic_reg_ops->apic_write(APIC_FORMAT_REG, 321 APIC_FLAT_MODEL); 322 } else { 323 apic_reg_ops->apic_write(APIC_FORMAT_REG, 324 APIC_CLUSTER_MODEL); 325 } 326 327 apic_reg_ops->apic_write(APIC_DEST_REG, 328 AV_HIGH_ORDER >> cpun); 329 } 330 331 if (apic_directed_EOI_supported()) { 332 /* 333 * Setting the 12th bit in the Spurious Interrupt Vector 334 * Register suppresses broadcast EOIs generated by the local 335 * APIC. The suppression of broadcast EOIs happens only when 336 * interrupts are level-triggered. 337 */ 338 svr |= APIC_SVR_SUPPRESS_BROADCAST_EOI; 339 } 340 341 /* need to enable APIC before unmasking NMI */ 342 apic_reg_ops->apic_write(APIC_SPUR_INT_REG, svr); 343 344 /* 345 * Presence of an invalid vector with delivery mode AV_FIXED can 346 * cause an error interrupt, even if the entry is masked...so 347 * write a valid vector to LVT entries along with the mask bit 348 */ 349 350 /* All APICs have timer and LINT0/1 */ 351 apic_reg_ops->apic_write(APIC_LOCAL_TIMER, AV_MASK|APIC_RESV_IRQ); 352 apic_reg_ops->apic_write(APIC_INT_VECT0, AV_MASK|APIC_RESV_IRQ); 353 apic_reg_ops->apic_write(APIC_INT_VECT1, AV_NMI); /* enable NMI */ 354 355 /* 356 * On integrated APICs, the number of LVT entries is 357 * 'Max LVT entry' + 1; on 82489DX's (non-integrated 358 * APICs), nlvt is "3" (LINT0, LINT1, and timer) 359 */ 360 361 if (apic_cpus[cpun].aci_local_ver < APIC_INTEGRATED_VERS) { 362 nlvt = 3; 363 } else { 364 nlvt = ((apic_reg_ops->apic_read(APIC_VERS_REG) >> 16) & 365 0xFF) + 1; 366 } 367 368 if (nlvt >= 5) { 369 /* Enable performance counter overflow interrupt */ 370 371 if (!is_x86_feature(x86_featureset, X86FSET_MSR)) 372 apic_enable_cpcovf_intr = 0; 373 if (apic_enable_cpcovf_intr) { 374 if (apic_cpcovf_vect == 0) { 375 int ipl = APIC_PCINT_IPL; 376 int irq = apic_get_ipivect(ipl, -1); 377 378 ASSERT(irq != -1); 379 apic_cpcovf_vect = 380 apic_irq_table[irq]->airq_vector; 381 ASSERT(apic_cpcovf_vect); 382 (void) add_avintr(NULL, ipl, 383 (avfunc)kcpc_hw_overflow_intr, 384 "apic pcint", irq, NULL, NULL, NULL, NULL); 385 kcpc_hw_overflow_intr_installed = 1; 386 kcpc_hw_enable_cpc_intr = 387 apic_cpcovf_mask_clear; 388 } 389 apic_reg_ops->apic_write(APIC_PCINT_VECT, 390 apic_cpcovf_vect); 391 } 392 } 393 394 if (nlvt >= 6) { 395 /* Only mask TM intr if the BIOS apparently doesn't use it */ 396 397 uint32_t lvtval; 398 399 lvtval = apic_reg_ops->apic_read(APIC_THERM_VECT); 400 if (((lvtval & AV_MASK) == AV_MASK) || 401 ((lvtval & AV_DELIV_MODE) != AV_SMI)) { 402 apic_reg_ops->apic_write(APIC_THERM_VECT, 403 AV_MASK|APIC_RESV_IRQ); 404 } 405 } 406 407 /* Enable error interrupt */ 408 409 if (nlvt >= 4 && apic_enable_error_intr) { 410 if (apic_errvect == 0) { 411 int ipl = 0xf; /* get highest priority intr */ 412 int irq = apic_get_ipivect(ipl, -1); 413 414 ASSERT(irq != -1); 415 apic_errvect = apic_irq_table[irq]->airq_vector; 416 ASSERT(apic_errvect); 417 /* 418 * Not PSMI compliant, but we are going to merge 419 * with ON anyway 420 */ 421 (void) add_avintr((void *)NULL, ipl, 422 (avfunc)apic_error_intr, "apic error intr", 423 irq, NULL, NULL, NULL, NULL); 424 } 425 apic_reg_ops->apic_write(APIC_ERR_VECT, apic_errvect); 426 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 427 apic_reg_ops->apic_write(APIC_ERROR_STATUS, 0); 428 } 429 430 /* Enable CMCI interrupt */ 431 if (cmi_enable_cmci) { 432 433 mutex_enter(&cmci_cpu_setup_lock); 434 if (cmci_cpu_setup_registered == 0) { 435 mutex_enter(&cpu_lock); 436 register_cpu_setup_func(cmci_cpu_setup, NULL); 437 mutex_exit(&cpu_lock); 438 cmci_cpu_setup_registered = 1; 439 } 440 mutex_exit(&cmci_cpu_setup_lock); 441 442 if (apic_cmci_vect == 0) { 443 int ipl = 0x2; 444 int irq = apic_get_ipivect(ipl, -1); 445 446 ASSERT(irq != -1); 447 apic_cmci_vect = apic_irq_table[irq]->airq_vector; 448 ASSERT(apic_cmci_vect); 449 450 (void) add_avintr(NULL, ipl, 451 (avfunc)cmi_cmci_trap, 452 "apic cmci intr", irq, NULL, NULL, NULL, NULL); 453 } 454 apic_reg_ops->apic_write(APIC_CMCI_VECT, apic_cmci_vect); 455 } 456 } 457 458 static void 459 apic_picinit(void) 460 { 461 int i, j; 462 uint_t isr; 463 464 /* 465 * Initialize and enable interrupt remapping before apic 466 * hardware initialization 467 */ 468 apic_intrmap_init(apic_mode); 469 470 /* 471 * On UniSys Model 6520, the BIOS leaves vector 0x20 isr 472 * bit on without clearing it with EOI. Since softint 473 * uses vector 0x20 to interrupt itself, so softint will 474 * not work on this machine. In order to fix this problem 475 * a check is made to verify all the isr bits are clear. 476 * If not, EOIs are issued to clear the bits. 477 */ 478 for (i = 7; i >= 1; i--) { 479 isr = apic_reg_ops->apic_read(APIC_ISR_REG + (i * 4)); 480 if (isr != 0) 481 for (j = 0; ((j < 32) && (isr != 0)); j++) 482 if (isr & (1 << j)) { 483 apic_reg_ops->apic_write( 484 APIC_EOI_REG, 0); 485 isr &= ~(1 << j); 486 apic_error |= APIC_ERR_BOOT_EOI; 487 } 488 } 489 490 /* set a flag so we know we have run apic_picinit() */ 491 apic_picinit_called = 1; 492 LOCK_INIT_CLEAR(&apic_gethrtime_lock); 493 LOCK_INIT_CLEAR(&apic_ioapic_lock); 494 LOCK_INIT_CLEAR(&apic_error_lock); 495 LOCK_INIT_CLEAR(&apic_mode_switch_lock); 496 497 picsetup(); /* initialise the 8259 */ 498 499 /* add nmi handler - least priority nmi handler */ 500 LOCK_INIT_CLEAR(&apic_nmi_lock); 501 502 if (!psm_add_nmintr(0, (avfunc) apic_nmi_intr, 503 "pcplusmp NMI handler", (caddr_t)NULL)) 504 cmn_err(CE_WARN, "pcplusmp: Unable to add nmi handler"); 505 506 /* 507 * Check for directed-EOI capability in the local APIC. 508 */ 509 if (apic_directed_EOI_supported() == 1) { 510 apic_set_directed_EOI_handler(); 511 } 512 513 apic_init_intr(); 514 515 /* enable apic mode if imcr present */ 516 if (apic_imcrp) { 517 outb(APIC_IMCR_P1, (uchar_t)APIC_IMCR_SELECT); 518 outb(APIC_IMCR_P2, (uchar_t)APIC_IMCR_APIC); 519 } 520 521 ioapic_init_intr(IOAPIC_MASK); 522 } 523 524 #ifdef DEBUG 525 void 526 apic_break(void) 527 { 528 } 529 #endif /* DEBUG */ 530 531 /* 532 * platform_intr_enter 533 * 534 * Called at the beginning of the interrupt service routine to 535 * mask all level equal to and below the interrupt priority 536 * of the interrupting vector. An EOI should be given to 537 * the interrupt controller to enable other HW interrupts. 538 * 539 * Return -1 for spurious interrupts 540 * 541 */ 542 /*ARGSUSED*/ 543 static int 544 apic_intr_enter(int ipl, int *vectorp) 545 { 546 uchar_t vector; 547 int nipl; 548 int irq; 549 ulong_t iflag; 550 apic_cpus_info_t *cpu_infop; 551 552 /* 553 * The real vector delivered is (*vectorp + 0x20), but our caller 554 * subtracts 0x20 from the vector before passing it to us. 555 * (That's why APIC_BASE_VECT is 0x20.) 556 */ 557 vector = (uchar_t)*vectorp; 558 559 /* if interrupted by the clock, increment apic_nsec_since_boot */ 560 if (vector == apic_clkvect) { 561 if (!apic_oneshot) { 562 /* NOTE: this is not MT aware */ 563 apic_hrtime_stamp++; 564 apic_nsec_since_boot += apic_nsec_per_intr; 565 apic_hrtime_stamp++; 566 last_count_read = apic_hertz_count; 567 apic_redistribute_compute(); 568 } 569 570 /* We will avoid all the book keeping overhead for clock */ 571 nipl = apic_ipls[vector]; 572 573 *vectorp = apic_vector_to_irq[vector + APIC_BASE_VECT]; 574 575 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 576 apic_reg_ops->apic_send_eoi(0); 577 578 return (nipl); 579 } 580 581 cpu_infop = &apic_cpus[psm_get_cpu_id()]; 582 583 if (vector == (APIC_SPUR_INTR - APIC_BASE_VECT)) { 584 cpu_infop->aci_spur_cnt++; 585 return (APIC_INT_SPURIOUS); 586 } 587 588 /* Check if the vector we got is really what we need */ 589 if (apic_revector_pending) { 590 /* 591 * Disable interrupts for the duration of 592 * the vector translation to prevent a self-race for 593 * the apic_revector_lock. This cannot be done 594 * in apic_xlate_vector because it is recursive and 595 * we want the vector translation to be atomic with 596 * respect to other (higher-priority) interrupts. 597 */ 598 iflag = intr_clear(); 599 vector = apic_xlate_vector(vector + APIC_BASE_VECT) - 600 APIC_BASE_VECT; 601 intr_restore(iflag); 602 } 603 604 nipl = apic_ipls[vector]; 605 *vectorp = irq = apic_vector_to_irq[vector + APIC_BASE_VECT]; 606 607 apic_reg_ops->apic_write_task_reg(apic_ipltopri[nipl]); 608 609 cpu_infop->aci_current[nipl] = (uchar_t)irq; 610 cpu_infop->aci_curipl = (uchar_t)nipl; 611 cpu_infop->aci_ISR_in_progress |= 1 << nipl; 612 613 /* 614 * apic_level_intr could have been assimilated into the irq struct. 615 * but, having it as a character array is more efficient in terms of 616 * cache usage. So, we leave it as is. 617 */ 618 if (!apic_level_intr[irq]) { 619 apic_reg_ops->apic_send_eoi(0); 620 } 621 622 #ifdef DEBUG 623 APIC_DEBUG_BUF_PUT(vector); 624 APIC_DEBUG_BUF_PUT(irq); 625 APIC_DEBUG_BUF_PUT(nipl); 626 APIC_DEBUG_BUF_PUT(psm_get_cpu_id()); 627 if ((apic_stretch_interrupts) && (apic_stretch_ISR & (1 << nipl))) 628 drv_usecwait(apic_stretch_interrupts); 629 630 if (apic_break_on_cpu == psm_get_cpu_id()) 631 apic_break(); 632 #endif /* DEBUG */ 633 return (nipl); 634 } 635 636 /* 637 * This macro is a common code used by MMIO local apic and X2APIC 638 * local apic. 639 */ 640 #define APIC_INTR_EXIT() \ 641 { \ 642 cpu_infop = &apic_cpus[psm_get_cpu_id()]; \ 643 if (apic_level_intr[irq]) \ 644 apic_reg_ops->apic_send_eoi(irq); \ 645 cpu_infop->aci_curipl = (uchar_t)prev_ipl; \ 646 /* ISR above current pri could not be in progress */ \ 647 cpu_infop->aci_ISR_in_progress &= (2 << prev_ipl) - 1; \ 648 } 649 650 /* 651 * Any changes made to this function must also change X2APIC 652 * version of intr_exit. 653 */ 654 void 655 apic_intr_exit(int prev_ipl, int irq) 656 { 657 apic_cpus_info_t *cpu_infop; 658 659 apic_reg_ops->apic_write_task_reg(apic_ipltopri[prev_ipl]); 660 661 APIC_INTR_EXIT(); 662 } 663 664 /* 665 * Same as apic_intr_exit() except it uses MSR rather than MMIO 666 * to access local apic registers. 667 */ 668 void 669 x2apic_intr_exit(int prev_ipl, int irq) 670 { 671 apic_cpus_info_t *cpu_infop; 672 673 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[prev_ipl]); 674 APIC_INTR_EXIT(); 675 } 676 677 intr_exit_fn_t 678 psm_intr_exit_fn(void) 679 { 680 if (apic_mode == LOCAL_X2APIC) 681 return (x2apic_intr_exit); 682 683 return (apic_intr_exit); 684 } 685 686 /* 687 * Mask all interrupts below or equal to the given IPL. 688 * Any changes made to this function must also change X2APIC 689 * version of setspl. 690 */ 691 static void 692 apic_setspl(int ipl) 693 { 694 apic_reg_ops->apic_write_task_reg(apic_ipltopri[ipl]); 695 696 /* interrupts at ipl above this cannot be in progress */ 697 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 698 /* 699 * this is a patch fix for the ALR QSMP P5 machine, so that interrupts 700 * have enough time to come in before the priority is raised again 701 * during the idle() loop. 702 */ 703 if (apic_setspl_delay) 704 (void) apic_reg_ops->apic_get_pri(); 705 } 706 707 /* 708 * X2APIC version of setspl. 709 * Mask all interrupts below or equal to the given IPL 710 */ 711 static void 712 x2apic_setspl(int ipl) 713 { 714 X2APIC_WRITE(APIC_TASK_REG, apic_ipltopri[ipl]); 715 716 /* interrupts at ipl above this cannot be in progress */ 717 apic_cpus[psm_get_cpu_id()].aci_ISR_in_progress &= (2 << ipl) - 1; 718 } 719 720 /*ARGSUSED*/ 721 static int 722 apic_addspl(int irqno, int ipl, int min_ipl, int max_ipl) 723 { 724 return (apic_addspl_common(irqno, ipl, min_ipl, max_ipl)); 725 } 726 727 static int 728 apic_delspl(int irqno, int ipl, int min_ipl, int max_ipl) 729 { 730 return (apic_delspl_common(irqno, ipl, min_ipl, max_ipl)); 731 } 732 733 static int 734 apic_post_cpu_start(void) 735 { 736 int cpun; 737 static int cpus_started = 1; 738 739 /* We know this CPU + BSP started successfully. */ 740 cpus_started++; 741 742 /* 743 * On BSP we would have enabled X2APIC, if supported by processor, 744 * in acpi_probe(), but on AP we do it here. 745 * 746 * We enable X2APIC mode only if BSP is running in X2APIC & the 747 * local APIC mode of the current CPU is MMIO (xAPIC). 748 */ 749 if (apic_mode == LOCAL_X2APIC && apic_detect_x2apic() && 750 apic_local_mode() == LOCAL_APIC) { 751 apic_enable_x2apic(); 752 } 753 754 /* 755 * Switch back to x2apic IPI sending method for performance when target 756 * CPU has entered x2apic mode. 757 */ 758 if (apic_mode == LOCAL_X2APIC) { 759 apic_switch_ipi_callback(B_FALSE); 760 } 761 762 splx(ipltospl(LOCK_LEVEL)); 763 apic_init_intr(); 764 765 /* 766 * since some systems don't enable the internal cache on the non-boot 767 * cpus, so we have to enable them here 768 */ 769 setcr0(getcr0() & ~(CR0_CD | CR0_NW)); 770 771 #ifdef DEBUG 772 APIC_AV_PENDING_SET(); 773 #else 774 if (apic_mode == LOCAL_APIC) 775 APIC_AV_PENDING_SET(); 776 #endif /* DEBUG */ 777 778 /* 779 * We may be booting, or resuming from suspend; aci_status will 780 * be APIC_CPU_INTR_ENABLE if coming from suspend, so we add the 781 * APIC_CPU_ONLINE flag here rather than setting aci_status completely. 782 */ 783 cpun = psm_get_cpu_id(); 784 apic_cpus[cpun].aci_status |= APIC_CPU_ONLINE; 785 786 apic_reg_ops->apic_write(APIC_DIVIDE_REG, apic_divide_reg_init); 787 return (PSM_SUCCESS); 788 } 789 790 /* 791 * type == -1 indicates it is an internal request. Do not change 792 * resv_vector for these requests 793 */ 794 static int 795 apic_get_ipivect(int ipl, int type) 796 { 797 uchar_t vector; 798 int irq; 799 800 if ((irq = apic_allocate_irq(APIC_VECTOR(ipl))) != -1) { 801 if (vector = apic_allocate_vector(ipl, irq, 1)) { 802 apic_irq_table[irq]->airq_mps_intr_index = 803 RESERVE_INDEX; 804 apic_irq_table[irq]->airq_vector = vector; 805 if (type != -1) { 806 apic_resv_vector[ipl] = vector; 807 } 808 return (irq); 809 } 810 } 811 apic_error |= APIC_ERR_GET_IPIVECT_FAIL; 812 return (-1); /* shouldn't happen */ 813 } 814 815 static int 816 apic_getclkirq(int ipl) 817 { 818 int irq; 819 820 if ((irq = apic_get_ipivect(ipl, -1)) == -1) 821 return (-1); 822 /* 823 * Note the vector in apic_clkvect for per clock handling. 824 */ 825 apic_clkvect = apic_irq_table[irq]->airq_vector - APIC_BASE_VECT; 826 APIC_VERBOSE_IOAPIC((CE_NOTE, "get_clkirq: vector = %x\n", 827 apic_clkvect)); 828 return (irq); 829 } 830 831 /* 832 * Try and disable all interrupts. We just assign interrupts to other 833 * processors based on policy. If any were bound by user request, we 834 * let them continue and return failure. We do not bother to check 835 * for cache affinity while rebinding. 836 */ 837 838 static int 839 apic_disable_intr(processorid_t cpun) 840 { 841 int bind_cpu = 0, i, hardbound = 0; 842 apic_irq_t *irq_ptr; 843 ulong_t iflag; 844 845 iflag = intr_clear(); 846 lock_set(&apic_ioapic_lock); 847 848 for (i = 0; i <= APIC_MAX_VECTOR; i++) { 849 if (apic_reprogram_info[i].done == B_FALSE) { 850 if (apic_reprogram_info[i].bindcpu == cpun) { 851 /* 852 * CPU is busy -- it's the target of 853 * a pending reprogramming attempt 854 */ 855 lock_clear(&apic_ioapic_lock); 856 intr_restore(iflag); 857 return (PSM_FAILURE); 858 } 859 } 860 } 861 862 apic_cpus[cpun].aci_status &= ~APIC_CPU_INTR_ENABLE; 863 864 apic_cpus[cpun].aci_curipl = 0; 865 866 i = apic_min_device_irq; 867 for (; i <= apic_max_device_irq; i++) { 868 /* 869 * If there are bound interrupts on this cpu, then 870 * rebind them to other processors. 871 */ 872 if ((irq_ptr = apic_irq_table[i]) != NULL) { 873 ASSERT((irq_ptr->airq_temp_cpu == IRQ_UNBOUND) || 874 (irq_ptr->airq_temp_cpu == IRQ_UNINIT) || 875 (apic_cpu_in_range(irq_ptr->airq_temp_cpu))); 876 877 if (irq_ptr->airq_temp_cpu == (cpun | IRQ_USER_BOUND)) { 878 hardbound = 1; 879 continue; 880 } 881 882 if (irq_ptr->airq_temp_cpu == cpun) { 883 do { 884 bind_cpu = 885 apic_find_cpu(APIC_CPU_INTR_ENABLE); 886 } while (apic_rebind_all(irq_ptr, bind_cpu)); 887 } 888 } 889 } 890 891 lock_clear(&apic_ioapic_lock); 892 intr_restore(iflag); 893 894 if (hardbound) { 895 cmn_err(CE_WARN, "Could not disable interrupts on %d" 896 "due to user bound interrupts", cpun); 897 return (PSM_FAILURE); 898 } 899 else 900 return (PSM_SUCCESS); 901 } 902 903 /* 904 * Bind interrupts to the CPU's local APIC. 905 * Interrupts should not be bound to a CPU's local APIC until the CPU 906 * is ready to receive interrupts. 907 */ 908 static void 909 apic_enable_intr(processorid_t cpun) 910 { 911 int i; 912 apic_irq_t *irq_ptr; 913 ulong_t iflag; 914 915 iflag = intr_clear(); 916 lock_set(&apic_ioapic_lock); 917 918 apic_cpus[cpun].aci_status |= APIC_CPU_INTR_ENABLE; 919 920 i = apic_min_device_irq; 921 for (i = apic_min_device_irq; i <= apic_max_device_irq; i++) { 922 if ((irq_ptr = apic_irq_table[i]) != NULL) { 923 if ((irq_ptr->airq_cpu & ~IRQ_USER_BOUND) == cpun) { 924 (void) apic_rebind_all(irq_ptr, 925 irq_ptr->airq_cpu); 926 } 927 } 928 } 929 930 if (apic_cpus[cpun].aci_status & APIC_CPU_SUSPEND) 931 apic_cpus[cpun].aci_status &= ~APIC_CPU_SUSPEND; 932 933 lock_clear(&apic_ioapic_lock); 934 intr_restore(iflag); 935 } 936 937 /* 938 * If this module needs a periodic handler for the interrupt distribution, it 939 * can be added here. The argument to the periodic handler is not currently 940 * used, but is reserved for future. 941 */ 942 static void 943 apic_post_cyclic_setup(void *arg) 944 { 945 _NOTE(ARGUNUSED(arg)) 946 947 cyc_handler_t cyh; 948 cyc_time_t cyt; 949 950 /* cpu_lock is held */ 951 /* set up a periodic handler for intr redistribution */ 952 953 /* 954 * In peridoc mode intr redistribution processing is done in 955 * apic_intr_enter during clk intr processing 956 */ 957 if (!apic_oneshot) 958 return; 959 960 /* 961 * Register a periodical handler for the redistribution processing. 962 * Though we would generally prefer to use the DDI interface for 963 * periodic handler invocation, ddi_periodic_add(9F), we are 964 * unfortunately already holding cpu_lock, which ddi_periodic_add will 965 * attempt to take for us. Thus, we add our own cyclic directly: 966 */ 967 cyh.cyh_func = (void (*)(void *))apic_redistribute_compute; 968 cyh.cyh_arg = NULL; 969 cyh.cyh_level = CY_LOW_LEVEL; 970 971 cyt.cyt_when = 0; 972 cyt.cyt_interval = apic_redistribute_sample_interval; 973 974 apic_cyclic_id = cyclic_add(&cyh, &cyt); 975 } 976 977 static void 978 apic_redistribute_compute(void) 979 { 980 int i, j, max_busy; 981 982 if (apic_enable_dynamic_migration) { 983 if (++apic_nticks == apic_sample_factor_redistribution) { 984 /* 985 * Time to call apic_intr_redistribute(). 986 * reset apic_nticks. This will cause max_busy 987 * to be calculated below and if it is more than 988 * apic_int_busy, we will do the whole thing 989 */ 990 apic_nticks = 0; 991 } 992 max_busy = 0; 993 for (i = 0; i < apic_nproc; i++) { 994 if (!apic_cpu_in_range(i)) 995 continue; 996 997 /* 998 * Check if curipl is non zero & if ISR is in 999 * progress 1000 */ 1001 if (((j = apic_cpus[i].aci_curipl) != 0) && 1002 (apic_cpus[i].aci_ISR_in_progress & (1 << j))) { 1003 1004 int irq; 1005 apic_cpus[i].aci_busy++; 1006 irq = apic_cpus[i].aci_current[j]; 1007 apic_irq_table[irq]->airq_busy++; 1008 } 1009 1010 if (!apic_nticks && 1011 (apic_cpus[i].aci_busy > max_busy)) 1012 max_busy = apic_cpus[i].aci_busy; 1013 } 1014 if (!apic_nticks) { 1015 if (max_busy > apic_int_busy_mark) { 1016 /* 1017 * We could make the following check be 1018 * skipped > 1 in which case, we get a 1019 * redistribution at half the busy mark (due to 1020 * double interval). Need to be able to collect 1021 * more empirical data to decide if that is a 1022 * good strategy. Punt for now. 1023 */ 1024 if (apic_skipped_redistribute) { 1025 apic_cleanup_busy(); 1026 apic_skipped_redistribute = 0; 1027 } else { 1028 apic_intr_redistribute(); 1029 } 1030 } else 1031 apic_skipped_redistribute++; 1032 } 1033 } 1034 } 1035 1036 1037 /* 1038 * The following functions are in the platform specific file so that they 1039 * can be different functions depending on whether we are running on 1040 * bare metal or a hypervisor. 1041 */ 1042 1043 /* 1044 * Check to make sure there are enough irq slots 1045 */ 1046 int 1047 apic_check_free_irqs(int count) 1048 { 1049 int i, avail; 1050 1051 avail = 0; 1052 for (i = APIC_FIRST_FREE_IRQ; i < APIC_RESV_IRQ; i++) { 1053 if ((apic_irq_table[i] == NULL) || 1054 apic_irq_table[i]->airq_mps_intr_index == FREE_INDEX) { 1055 if (++avail >= count) 1056 return (PSM_SUCCESS); 1057 } 1058 } 1059 return (PSM_FAILURE); 1060 } 1061 1062 /* 1063 * This function allocates "count" MSI vector(s) for the given "dip/pri/type" 1064 */ 1065 int 1066 apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, int pri, 1067 int behavior) 1068 { 1069 int rcount, i; 1070 uchar_t start, irqno; 1071 uint32_t cpu; 1072 major_t major; 1073 apic_irq_t *irqptr; 1074 1075 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: dip=0x%p " 1076 "inum=0x%x pri=0x%x count=0x%x behavior=%d\n", 1077 (void *)dip, inum, pri, count, behavior)); 1078 1079 if (count > 1) { 1080 if (behavior == DDI_INTR_ALLOC_STRICT && 1081 apic_multi_msi_enable == 0) 1082 return (0); 1083 if (apic_multi_msi_enable == 0) 1084 count = 1; 1085 } 1086 1087 if ((rcount = apic_navail_vector(dip, pri)) > count) 1088 rcount = count; 1089 else if (rcount == 0 || (rcount < count && 1090 behavior == DDI_INTR_ALLOC_STRICT)) 1091 return (0); 1092 1093 /* if not ISP2, then round it down */ 1094 if (!ISP2(rcount)) 1095 rcount = 1 << (highbit(rcount) - 1); 1096 1097 mutex_enter(&airq_mutex); 1098 1099 for (start = 0; rcount > 0; rcount >>= 1) { 1100 if ((start = apic_find_multi_vectors(pri, rcount)) != 0 || 1101 behavior == DDI_INTR_ALLOC_STRICT) 1102 break; 1103 } 1104 1105 if (start == 0) { 1106 /* no vector available */ 1107 mutex_exit(&airq_mutex); 1108 return (0); 1109 } 1110 1111 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1112 /* not enough free irq slots available */ 1113 mutex_exit(&airq_mutex); 1114 return (0); 1115 } 1116 1117 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1118 for (i = 0; i < rcount; i++) { 1119 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1120 (uchar_t)-1) { 1121 /* 1122 * shouldn't happen because of the 1123 * apic_check_free_irqs() check earlier 1124 */ 1125 mutex_exit(&airq_mutex); 1126 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1127 "apic_allocate_irq failed\n")); 1128 return (i); 1129 } 1130 apic_max_device_irq = max(irqno, apic_max_device_irq); 1131 apic_min_device_irq = min(irqno, apic_min_device_irq); 1132 irqptr = apic_irq_table[irqno]; 1133 #ifdef DEBUG 1134 if (apic_vector_to_irq[start + i] != APIC_RESV_IRQ) 1135 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: " 1136 "apic_vector_to_irq is not APIC_RESV_IRQ\n")); 1137 #endif 1138 apic_vector_to_irq[start + i] = (uchar_t)irqno; 1139 1140 irqptr->airq_vector = (uchar_t)(start + i); 1141 irqptr->airq_ioapicindex = (uchar_t)inum; /* start */ 1142 irqptr->airq_intin_no = (uchar_t)rcount; 1143 irqptr->airq_ipl = pri; 1144 irqptr->airq_vector = start + i; 1145 irqptr->airq_origirq = (uchar_t)(inum + i); 1146 irqptr->airq_share_id = 0; 1147 irqptr->airq_mps_intr_index = MSI_INDEX; 1148 irqptr->airq_dip = dip; 1149 irqptr->airq_major = major; 1150 if (i == 0) /* they all bound to the same cpu */ 1151 cpu = irqptr->airq_cpu = apic_bind_intr(dip, irqno, 1152 0xff, 0xff); 1153 else 1154 irqptr->airq_cpu = cpu; 1155 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msi_vectors: irq=0x%x " 1156 "dip=0x%p vector=0x%x origirq=0x%x pri=0x%x\n", irqno, 1157 (void *)irqptr->airq_dip, irqptr->airq_vector, 1158 irqptr->airq_origirq, pri)); 1159 } 1160 mutex_exit(&airq_mutex); 1161 return (rcount); 1162 } 1163 1164 /* 1165 * This function allocates "count" MSI-X vector(s) for the given "dip/pri/type" 1166 */ 1167 int 1168 apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, int pri, 1169 int behavior) 1170 { 1171 int rcount, i; 1172 major_t major; 1173 1174 mutex_enter(&airq_mutex); 1175 1176 if ((rcount = apic_navail_vector(dip, pri)) > count) 1177 rcount = count; 1178 else if (rcount == 0 || (rcount < count && 1179 behavior == DDI_INTR_ALLOC_STRICT)) { 1180 rcount = 0; 1181 goto out; 1182 } 1183 1184 if (apic_check_free_irqs(rcount) == PSM_FAILURE) { 1185 /* not enough free irq slots available */ 1186 rcount = 0; 1187 goto out; 1188 } 1189 1190 major = (dip != NULL) ? ddi_driver_major(dip) : 0; 1191 for (i = 0; i < rcount; i++) { 1192 uchar_t vector, irqno; 1193 apic_irq_t *irqptr; 1194 1195 if ((irqno = apic_allocate_irq(apic_first_avail_irq)) == 1196 (uchar_t)-1) { 1197 /* 1198 * shouldn't happen because of the 1199 * apic_check_free_irqs() check earlier 1200 */ 1201 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1202 "apic_allocate_irq failed\n")); 1203 rcount = i; 1204 goto out; 1205 } 1206 if ((vector = apic_allocate_vector(pri, irqno, 1)) == 0) { 1207 /* 1208 * shouldn't happen because of the 1209 * apic_navail_vector() call earlier 1210 */ 1211 DDI_INTR_IMPLDBG((CE_CONT, "apic_alloc_msix_vectors: " 1212 "apic_allocate_vector failed\n")); 1213 rcount = i; 1214 goto out; 1215 } 1216 apic_max_device_irq = max(irqno, apic_max_device_irq); 1217 apic_min_device_irq = min(irqno, apic_min_device_irq); 1218 irqptr = apic_irq_table[irqno]; 1219 irqptr->airq_vector = (uchar_t)vector; 1220 irqptr->airq_ipl = pri; 1221 irqptr->airq_origirq = (uchar_t)(inum + i); 1222 irqptr->airq_share_id = 0; 1223 irqptr->airq_mps_intr_index = MSIX_INDEX; 1224 irqptr->airq_dip = dip; 1225 irqptr->airq_major = major; 1226 irqptr->airq_cpu = apic_bind_intr(dip, irqno, 0xff, 0xff); 1227 } 1228 out: 1229 mutex_exit(&airq_mutex); 1230 return (rcount); 1231 } 1232 1233 /* 1234 * Allocate a free vector for irq at ipl. Takes care of merging of multiple 1235 * IPLs into a single APIC level as well as stretching some IPLs onto multiple 1236 * levels. APIC_HI_PRI_VECTS interrupts are reserved for high priority 1237 * requests and allocated only when pri is set. 1238 */ 1239 uchar_t 1240 apic_allocate_vector(int ipl, int irq, int pri) 1241 { 1242 int lowest, highest, i; 1243 1244 highest = apic_ipltopri[ipl] + APIC_VECTOR_MASK; 1245 lowest = apic_ipltopri[ipl - 1] + APIC_VECTOR_PER_IPL; 1246 1247 if (highest < lowest) /* Both ipl and ipl - 1 map to same pri */ 1248 lowest -= APIC_VECTOR_PER_IPL; 1249 1250 #ifdef DEBUG 1251 if (apic_restrict_vector) /* for testing shared interrupt logic */ 1252 highest = lowest + apic_restrict_vector + APIC_HI_PRI_VECTS; 1253 #endif /* DEBUG */ 1254 if (pri == 0) 1255 highest -= APIC_HI_PRI_VECTS; 1256 1257 for (i = lowest; i <= highest; i++) { 1258 if (APIC_CHECK_RESERVE_VECTORS(i)) 1259 continue; 1260 if (apic_vector_to_irq[i] == APIC_RESV_IRQ) { 1261 apic_vector_to_irq[i] = (uchar_t)irq; 1262 return (i); 1263 } 1264 } 1265 1266 return (0); 1267 } 1268 1269 /* Mark vector as not being used by any irq */ 1270 void 1271 apic_free_vector(uchar_t vector) 1272 { 1273 apic_vector_to_irq[vector] = APIC_RESV_IRQ; 1274 } 1275 1276 /* 1277 * Call rebind to do the actual programming. 1278 * Must be called with interrupts disabled and apic_ioapic_lock held 1279 * 'p' is polymorphic -- if this function is called to process a deferred 1280 * reprogramming, p is of type 'struct ioapic_reprogram_data *', from which 1281 * the irq pointer is retrieved. If not doing deferred reprogramming, 1282 * p is of the type 'apic_irq_t *'. 1283 * 1284 * apic_ioapic_lock must be held across this call, as it protects apic_rebind 1285 * and it protects apic_get_next_bind_cpu() from a race in which a CPU can be 1286 * taken offline after a cpu is selected, but before apic_rebind is called to 1287 * bind interrupts to it. 1288 */ 1289 int 1290 apic_setup_io_intr(void *p, int irq, boolean_t deferred) 1291 { 1292 apic_irq_t *irqptr; 1293 struct ioapic_reprogram_data *drep = NULL; 1294 int rv; 1295 1296 if (deferred) { 1297 drep = (struct ioapic_reprogram_data *)p; 1298 ASSERT(drep != NULL); 1299 irqptr = drep->irqp; 1300 } else 1301 irqptr = (apic_irq_t *)p; 1302 1303 ASSERT(irqptr != NULL); 1304 1305 rv = apic_rebind(irqptr, apic_irq_table[irq]->airq_cpu, drep); 1306 if (rv) { 1307 /* 1308 * CPU is not up or interrupts are disabled. Fall back to 1309 * the first available CPU 1310 */ 1311 rv = apic_rebind(irqptr, apic_find_cpu(APIC_CPU_INTR_ENABLE), 1312 drep); 1313 } 1314 1315 return (rv); 1316 } 1317 1318 1319 uchar_t 1320 apic_modify_vector(uchar_t vector, int irq) 1321 { 1322 apic_vector_to_irq[vector] = (uchar_t)irq; 1323 return (vector); 1324 } 1325 1326 char * 1327 apic_get_apic_type(void) 1328 { 1329 return (apic_psm_info.p_mach_idstring); 1330 } 1331 1332 void 1333 x2apic_update_psm(void) 1334 { 1335 struct psm_ops *pops = &apic_ops; 1336 1337 ASSERT(pops != NULL); 1338 1339 pops->psm_intr_exit = x2apic_intr_exit; 1340 pops->psm_setspl = x2apic_setspl; 1341 1342 pops->psm_send_ipi = x2apic_send_ipi; 1343 send_dirintf = pops->psm_send_ipi; 1344 1345 apic_mode = LOCAL_X2APIC; 1346 apic_change_ops(); 1347 } 1348