1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/mkdev.h> 30 #include <sys/stat.h> 31 #include <sys/sunddi.h> 32 #include <vm/seg_kmem.h> 33 #include <sys/machparam.h> 34 #include <sys/sunndi.h> 35 #include <sys/ontrap.h> 36 #include <sys/psm.h> 37 #include <sys/pcie.h> 38 #include <sys/hotplug/pci/pcihp.h> 39 #include <sys/pci_cfgspace.h> 40 #include <sys/pci_tools.h> 41 #include <io/pci/pci_tools_ext.h> 42 #include <sys/apic.h> 43 #include <io/pci/pci_var.h> 44 #include <sys/promif.h> 45 #include <sys/x86_archext.h> 46 #include <sys/cpuvar.h> 47 48 #define PCIEX_BDF_OFFSET_DELTA 4 49 #define PCIEX_REG_FUNC_SHIFT (PCI_REG_FUNC_SHIFT + PCIEX_BDF_OFFSET_DELTA) 50 #define PCIEX_REG_DEV_SHIFT (PCI_REG_DEV_SHIFT + PCIEX_BDF_OFFSET_DELTA) 51 #define PCIEX_REG_BUS_SHIFT (PCI_REG_BUS_SHIFT + PCIEX_BDF_OFFSET_DELTA) 52 53 #define SUCCESS 0 54 55 int pcitool_debug = 0; 56 57 /* 58 * Offsets of BARS in config space. First entry of 0 means config space. 59 * Entries here correlate to pcitool_bars_t enumerated type. 60 */ 61 static uint8_t pci_bars[] = { 62 0x0, 63 PCI_CONF_BASE0, 64 PCI_CONF_BASE1, 65 PCI_CONF_BASE2, 66 PCI_CONF_BASE3, 67 PCI_CONF_BASE4, 68 PCI_CONF_BASE5, 69 PCI_CONF_ROM 70 }; 71 72 /* Max offset allowed into config space for a particular device. */ 73 static uint64_t max_cfg_size = PCI_CONF_HDR_SIZE; 74 75 static uint64_t pcitool_swap_endian(uint64_t data, int size); 76 static int pcitool_pciex_cfg_access(dev_info_t *dip, pcitool_reg_t *prg, 77 boolean_t write_flag); 78 static int pcitool_cfg_access(dev_info_t *dip, pcitool_reg_t *prg, 79 boolean_t write_flag); 80 static int pcitool_io_access(dev_info_t *dip, pcitool_reg_t *prg, 81 boolean_t write_flag); 82 static int pcitool_mem_access(dev_info_t *dip, pcitool_reg_t *prg, 83 uint64_t virt_addr, boolean_t write_flag); 84 static uint64_t pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages); 85 static void pcitool_unmap(uint64_t virt_addr, size_t num_pages); 86 87 /* Extern declarations */ 88 extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, 89 psm_intr_op_t, int *); 90 91 int 92 pcitool_init(dev_info_t *dip, boolean_t is_pciex) 93 { 94 int instance = ddi_get_instance(dip); 95 96 /* Create pcitool nodes for register access and interrupt routing. */ 97 98 if (ddi_create_minor_node(dip, PCI_MINOR_REG, S_IFCHR, 99 PCIHP_AP_MINOR_NUM(instance, PCI_TOOL_REG_MINOR_NUM), 100 DDI_NT_REGACC, 0) != DDI_SUCCESS) { 101 return (DDI_FAILURE); 102 } 103 104 if (ddi_create_minor_node(dip, PCI_MINOR_INTR, S_IFCHR, 105 PCIHP_AP_MINOR_NUM(instance, PCI_TOOL_INTR_MINOR_NUM), 106 DDI_NT_INTRCTL, 0) != DDI_SUCCESS) { 107 ddi_remove_minor_node(dip, PCI_MINOR_REG); 108 return (DDI_FAILURE); 109 } 110 111 if (is_pciex) 112 max_cfg_size = PCIE_CONF_HDR_SIZE; 113 114 return (DDI_SUCCESS); 115 } 116 117 void 118 pcitool_uninit(dev_info_t *dip) 119 { 120 ddi_remove_minor_node(dip, PCI_MINOR_INTR); 121 ddi_remove_minor_node(dip, PCI_MINOR_REG); 122 } 123 124 /*ARGSUSED*/ 125 static int 126 pcitool_set_intr(dev_info_t *dip, void *arg, int mode) 127 { 128 ddi_intr_handle_impl_t info_hdl; 129 pcitool_intr_set_t iset; 130 uint32_t old_cpu; 131 int ret, result; 132 size_t copyinout_size; 133 int rval = SUCCESS; 134 135 /* Version 1 of pcitool_intr_set_t doesn't have flags. */ 136 copyinout_size = (size_t)&iset.flags - (size_t)&iset; 137 138 if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS) 139 return (EFAULT); 140 141 switch (iset.user_version) { 142 case PCITOOL_V1: 143 break; 144 145 case PCITOOL_V2: 146 copyinout_size = sizeof (pcitool_intr_set_t); 147 if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS) 148 return (EFAULT); 149 break; 150 151 default: 152 iset.status = PCITOOL_OUT_OF_RANGE; 153 rval = ENOTSUP; 154 goto done_set_intr; 155 } 156 157 if (iset.ino > APIC_MAX_VECTOR) { 158 rval = EINVAL; 159 iset.status = PCITOOL_INVALID_INO; 160 goto done_set_intr; 161 } 162 163 iset.status = PCITOOL_SUCCESS; 164 165 if ((old_cpu = pci_get_cpu_from_vecirq(iset.ino, IS_VEC)) == -1) { 166 iset.status = PCITOOL_IO_ERROR; 167 rval = EINVAL; 168 goto done_set_intr; 169 } 170 171 172 old_cpu &= ~PSMGI_CPU_USER_BOUND; 173 174 /* 175 * For this locally-declared and used handle, ih_private will contain a 176 * CPU value, not an ihdl_plat_t as used for global interrupt handling. 177 */ 178 info_hdl.ih_vector = iset.ino; 179 info_hdl.ih_private = (void *)(uintptr_t)iset.cpu_id; 180 if (pcitool_debug) 181 prom_printf("user version:%d, flags:0x%x\n", 182 iset.user_version, iset.flags); 183 184 result = ENOTSUP; 185 if ((iset.user_version >= PCITOOL_V2) && 186 (iset.flags & PCITOOL_INTR_SET_FLAG_GROUP)) { 187 ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_GRP_SET_CPU, 188 &result); 189 } else { 190 ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_SET_CPU, 191 &result); 192 } 193 194 if (ret != PSM_SUCCESS) { 195 switch (result) { 196 case EIO: /* Error making the change */ 197 rval = EIO; 198 iset.status = PCITOOL_IO_ERROR; 199 break; 200 case ENXIO: /* Couldn't convert vector to irq */ 201 rval = EINVAL; 202 iset.status = PCITOOL_INVALID_INO; 203 break; 204 case EINVAL: /* CPU out of range */ 205 rval = EINVAL; 206 iset.status = PCITOOL_INVALID_CPUID; 207 break; 208 case ENOTSUP: /* Requested PSM intr ops missing */ 209 rval = ENOTSUP; 210 iset.status = PCITOOL_IO_ERROR; 211 break; 212 } 213 } 214 215 /* Return original CPU. */ 216 iset.cpu_id = old_cpu; 217 218 done_set_intr: 219 iset.drvr_version = PCITOOL_VERSION; 220 if (ddi_copyout(&iset, arg, copyinout_size, mode) != DDI_SUCCESS) 221 rval = EFAULT; 222 return (rval); 223 } 224 225 226 /* It is assumed that dip != NULL */ 227 static void 228 pcitool_get_intr_dev_info(dev_info_t *dip, pcitool_intr_dev_t *devs) 229 { 230 (void) strncpy(devs->driver_name, 231 ddi_driver_name(dip), MAXMODCONFNAME-1); 232 devs->driver_name[MAXMODCONFNAME] = '\0'; 233 (void) ddi_pathname(dip, devs->path); 234 devs->dev_inst = ddi_get_instance(dip); 235 } 236 237 238 /*ARGSUSED*/ 239 static int 240 pcitool_get_intr(dev_info_t *dip, void *arg, int mode) 241 { 242 /* Array part isn't used here, but oh well... */ 243 pcitool_intr_get_t partial_iget; 244 pcitool_intr_get_t *iget = &partial_iget; 245 size_t iget_kmem_alloc_size = 0; 246 uint8_t num_devs_ret; 247 int copyout_rval; 248 int rval = SUCCESS; 249 int circ; 250 int i; 251 252 ddi_intr_handle_impl_t info_hdl; 253 apic_get_intr_t intr_info; 254 255 /* Read in just the header part, no array section. */ 256 if (ddi_copyin(arg, &partial_iget, PCITOOL_IGET_SIZE(0), mode) != 257 DDI_SUCCESS) 258 return (EFAULT); 259 260 /* Validate argument. */ 261 if (partial_iget.ino > APIC_MAX_VECTOR) { 262 partial_iget.status = PCITOOL_INVALID_INO; 263 partial_iget.num_devs_ret = 0; 264 rval = EINVAL; 265 goto done_get_intr; 266 } 267 268 num_devs_ret = partial_iget.num_devs_ret; 269 intr_info.avgi_dip_list = NULL; 270 intr_info.avgi_req_flags = 271 PSMGI_REQ_CPUID | PSMGI_REQ_NUM_DEVS | PSMGI_INTRBY_VEC; 272 /* 273 * For this locally-declared and used handle, ih_private will contain a 274 * pointer to apic_get_intr_t, not an ihdl_plat_t as used for 275 * global interrupt handling. 276 */ 277 info_hdl.ih_private = &intr_info; 278 info_hdl.ih_vector = partial_iget.ino; 279 280 /* Caller wants device information returned. */ 281 if (num_devs_ret > 0) { 282 283 intr_info.avgi_req_flags |= PSMGI_REQ_GET_DEVS; 284 285 /* 286 * Allocate room. 287 * If num_devs_ret == 0 iget remains pointing to partial_iget. 288 */ 289 iget_kmem_alloc_size = PCITOOL_IGET_SIZE(num_devs_ret); 290 iget = kmem_alloc(iget_kmem_alloc_size, KM_SLEEP); 291 292 /* Read in whole structure to verify there's room. */ 293 if (ddi_copyin(arg, iget, iget_kmem_alloc_size, mode) != 294 SUCCESS) { 295 296 /* Be consistent and just return EFAULT here. */ 297 kmem_free(iget, iget_kmem_alloc_size); 298 299 return (EFAULT); 300 } 301 } 302 303 bzero(iget, PCITOOL_IGET_SIZE(num_devs_ret)); 304 iget->ino = info_hdl.ih_vector; 305 306 /* 307 * Lock device tree branch from the pci root nexus on down if info will 308 * be extracted from dips returned from the tree. 309 */ 310 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 311 ndi_devi_enter(dip, &circ); 312 } 313 314 /* Call psm_intr_ops(PSM_INTR_OP_GET_INTR) to get information. */ 315 if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 316 PSM_INTR_OP_GET_INTR, NULL)) != PSM_SUCCESS) { 317 iget->status = PCITOOL_IO_ERROR; 318 iget->num_devs_ret = 0; 319 rval = EINVAL; 320 goto done_get_intr; 321 } 322 323 /* 324 * Fill in the pcitool_intr_get_t to be returned, 325 * with the CPU, num_devs_ret and num_devs. 326 */ 327 iget->cpu_id = intr_info.avgi_cpu_id & ~PSMGI_CPU_USER_BOUND; 328 329 /* Number of devices returned by apic. */ 330 iget->num_devs = intr_info.avgi_num_devs; 331 332 /* Device info was returned. */ 333 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 334 335 /* 336 * num devs returned is num devs ret by apic, 337 * space permitting. 338 */ 339 iget->num_devs_ret = min(num_devs_ret, intr_info.avgi_num_devs); 340 341 /* 342 * Loop thru list of dips and extract driver, name and instance. 343 * Fill in the pcitool_intr_dev_t's with this info. 344 */ 345 for (i = 0; i < iget->num_devs_ret; i++) 346 pcitool_get_intr_dev_info(intr_info.avgi_dip_list[i], 347 &iget->dev[i]); 348 349 /* Free kmem_alloc'ed memory of the apic_get_intr_t */ 350 kmem_free(intr_info.avgi_dip_list, 351 intr_info.avgi_num_devs * sizeof (dev_info_t *)); 352 } 353 354 done_get_intr: 355 356 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 357 ndi_devi_exit(dip, circ); 358 } 359 360 iget->drvr_version = PCITOOL_VERSION; 361 copyout_rval = ddi_copyout(iget, arg, 362 PCITOOL_IGET_SIZE(num_devs_ret), mode); 363 364 if (iget_kmem_alloc_size > 0) 365 kmem_free(iget, iget_kmem_alloc_size); 366 367 if (copyout_rval != DDI_SUCCESS) 368 rval = EFAULT; 369 370 return (rval); 371 } 372 373 /*ARGSUSED*/ 374 static int 375 pcitool_intr_info(dev_info_t *dip, void *arg, int mode) 376 { 377 pcitool_intr_info_t intr_info; 378 ddi_intr_handle_impl_t info_hdl; 379 int rval = SUCCESS; 380 381 /* If we need user_version, and to ret same user version as passed in */ 382 if (ddi_copyin(arg, &intr_info, sizeof (pcitool_intr_info_t), mode) != 383 DDI_SUCCESS) { 384 if (pcitool_debug) 385 prom_printf("Error reading arguments\n"); 386 return (EFAULT); 387 } 388 389 /* For UPPC systems, psm_intr_ops has no entry for APIC_TYPE. */ 390 if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 391 PSM_INTR_OP_APIC_TYPE, NULL)) != PSM_SUCCESS) { 392 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UPPC; 393 intr_info.ctlr_version = 0; 394 395 } else { 396 intr_info.ctlr_version = (uint32_t)info_hdl.ih_ver; 397 if (strcmp((char *)info_hdl.ih_private, 398 APIC_PCPLUSMP_NAME) == 0) 399 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_PCPLUSMP; 400 else 401 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UNKNOWN; 402 } 403 404 intr_info.num_intr = APIC_MAX_VECTOR; 405 intr_info.drvr_version = PCITOOL_VERSION; 406 if (ddi_copyout(&intr_info, arg, sizeof (pcitool_intr_info_t), mode) != 407 DDI_SUCCESS) { 408 if (pcitool_debug) 409 prom_printf("Error returning arguments.\n"); 410 rval = EFAULT; 411 } 412 413 return (rval); 414 } 415 416 417 418 /* 419 * Main function for handling interrupt CPU binding requests and queries. 420 * Need to implement later 421 */ 422 /*ARGSUSED*/ 423 int 424 pcitool_intr_admn(dev_info_t *dip, void *arg, int cmd, int mode) 425 { 426 int rval; 427 428 switch (cmd) { 429 430 /* Associate a new CPU with a given vector */ 431 case PCITOOL_DEVICE_SET_INTR: 432 rval = pcitool_set_intr(dip, arg, mode); 433 break; 434 435 case PCITOOL_DEVICE_GET_INTR: 436 rval = pcitool_get_intr(dip, arg, mode); 437 break; 438 439 case PCITOOL_SYSTEM_INTR_INFO: 440 rval = pcitool_intr_info(dip, arg, mode); 441 break; 442 443 default: 444 rval = ENOTSUP; 445 } 446 447 return (rval); 448 } 449 450 451 /* 452 * A note about ontrap handling: 453 * 454 * X86 systems on which this module was tested return FFs instead of bus errors 455 * when accessing devices with invalid addresses. Ontrap handling, which 456 * gracefully handles kernel bus errors, is installed anyway, in case future 457 * X86 platforms require it. 458 */ 459 460 /* 461 * Perform register accesses on the nexus device itself. 462 * No explicit PCI nexus device for X86, so not applicable. 463 */ 464 465 /*ARGSUSED*/ 466 int 467 pcitool_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 468 { 469 return (ENOTSUP); 470 } 471 472 /* Swap endianness. */ 473 static uint64_t 474 pcitool_swap_endian(uint64_t data, int size) 475 { 476 typedef union { 477 uint64_t data64; 478 uint8_t data8[8]; 479 } data_split_t; 480 481 data_split_t orig_data; 482 data_split_t returned_data; 483 int i; 484 485 orig_data.data64 = data; 486 returned_data.data64 = 0; 487 488 for (i = 0; i < size; i++) { 489 returned_data.data8[i] = orig_data.data8[size - 1 - i]; 490 } 491 492 return (returned_data.data64); 493 } 494 495 496 /* 497 * Access device. prg is modified. 498 * 499 * Extended config space is available only through memory-mapped access. 500 * Standard config space on pci express devices is available either way, 501 * so do it memory-mapped here too, for simplicity. 502 */ 503 /*ARGSUSED*/ 504 static int 505 pcitool_pciex_cfg_access(dev_info_t *dip, pcitool_reg_t *prg, 506 boolean_t write_flag) 507 { 508 int rval = SUCCESS; 509 uint64_t virt_addr; 510 size_t num_virt_pages; 511 512 prg->status = PCITOOL_SUCCESS; 513 514 prg->phys_addr = ddi_prop_get_int64(DDI_DEV_T_ANY, dip, 0, 515 "ecfga-base-address", 0); 516 if (prg->phys_addr == 0) { 517 prg->status = PCITOOL_IO_ERROR; 518 return (EIO); 519 } 520 521 prg->phys_addr += prg->offset + 522 ((prg->bus_no << PCIEX_REG_BUS_SHIFT) | 523 (prg->dev_no << PCIEX_REG_DEV_SHIFT) | 524 (prg->func_no << PCIEX_REG_FUNC_SHIFT)); 525 526 virt_addr = pcitool_map(prg->phys_addr, 527 PCITOOL_ACC_ATTR_SIZE(prg->acc_attr), &num_virt_pages); 528 if (virt_addr == NULL) { 529 prg->status = PCITOOL_IO_ERROR; 530 return (EIO); 531 } 532 533 rval = pcitool_mem_access(dip, prg, virt_addr, write_flag); 534 pcitool_unmap(virt_addr, num_virt_pages); 535 return (rval); 536 } 537 538 /* Access device. prg is modified. */ 539 /*ARGSUSED*/ 540 static int 541 pcitool_cfg_access(dev_info_t *dip, pcitool_reg_t *prg, boolean_t write_flag) 542 { 543 int size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 544 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 545 int rval = SUCCESS; 546 uint64_t local_data; 547 548 /* 549 * NOTE: there is no way to verify whether or not the address is valid. 550 * The put functions return void and the get functions return ff on 551 * error. 552 */ 553 prg->status = PCITOOL_SUCCESS; 554 555 if (write_flag) { 556 557 if (big_endian) { 558 local_data = pcitool_swap_endian(prg->data, size); 559 } else { 560 local_data = prg->data; 561 } 562 563 switch (size) { 564 case 1: 565 (*pci_putb_func)(prg->bus_no, prg->dev_no, 566 prg->func_no, prg->offset, local_data); 567 break; 568 case 2: 569 (*pci_putw_func)(prg->bus_no, prg->dev_no, 570 prg->func_no, prg->offset, local_data); 571 break; 572 case 4: 573 (*pci_putl_func)(prg->bus_no, prg->dev_no, 574 prg->func_no, prg->offset, local_data); 575 break; 576 default: 577 rval = ENOTSUP; 578 prg->status = PCITOOL_INVALID_SIZE; 579 break; 580 } 581 } else { 582 switch (size) { 583 case 1: 584 local_data = (*pci_getb_func)(prg->bus_no, prg->dev_no, 585 prg->func_no, prg->offset); 586 break; 587 case 2: 588 local_data = (*pci_getw_func)(prg->bus_no, prg->dev_no, 589 prg->func_no, prg->offset); 590 break; 591 case 4: 592 local_data = (*pci_getl_func)(prg->bus_no, prg->dev_no, 593 prg->func_no, prg->offset); 594 break; 595 default: 596 rval = ENOTSUP; 597 prg->status = PCITOOL_INVALID_SIZE; 598 break; 599 } 600 601 if (rval == SUCCESS) { 602 if (big_endian) { 603 prg->data = 604 pcitool_swap_endian(local_data, size); 605 } else { 606 prg->data = local_data; 607 } 608 } 609 } 610 prg->phys_addr = 0; /* Config space is not memory mapped on X86. */ 611 return (rval); 612 } 613 614 615 /*ARGSUSED*/ 616 static int 617 pcitool_io_access(dev_info_t *dip, pcitool_reg_t *prg, boolean_t write_flag) 618 { 619 int port = (int)prg->phys_addr; 620 size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 621 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 622 int rval = SUCCESS; 623 on_trap_data_t otd; 624 uint64_t local_data; 625 626 627 /* 628 * on_trap works like setjmp. 629 * 630 * A non-zero return here means on_trap has returned from an error. 631 * 632 * A zero return here means that on_trap has just returned from setup. 633 */ 634 if (on_trap(&otd, OT_DATA_ACCESS)) { 635 no_trap(); 636 if (pcitool_debug) 637 prom_printf( 638 "pcitool_io_access: on_trap caught an error...\n"); 639 prg->status = PCITOOL_INVALID_ADDRESS; 640 return (EFAULT); 641 } 642 643 if (write_flag) { 644 645 if (big_endian) { 646 local_data = pcitool_swap_endian(prg->data, size); 647 } else { 648 local_data = prg->data; 649 } 650 651 if (pcitool_debug) 652 prom_printf("Writing %ld byte(s) to port 0x%x\n", 653 size, port); 654 655 switch (size) { 656 case 1: 657 outb(port, (uint8_t)local_data); 658 break; 659 case 2: 660 outw(port, (uint16_t)local_data); 661 break; 662 case 4: 663 outl(port, (uint32_t)local_data); 664 break; 665 default: 666 rval = ENOTSUP; 667 prg->status = PCITOOL_INVALID_SIZE; 668 break; 669 } 670 } else { 671 if (pcitool_debug) 672 prom_printf("Reading %ld byte(s) from port 0x%x\n", 673 size, port); 674 675 switch (size) { 676 case 1: 677 local_data = inb(port); 678 break; 679 case 2: 680 local_data = inw(port); 681 break; 682 case 4: 683 local_data = inl(port); 684 break; 685 default: 686 rval = ENOTSUP; 687 prg->status = PCITOOL_INVALID_SIZE; 688 break; 689 } 690 691 if (rval == SUCCESS) { 692 if (big_endian) { 693 prg->data = 694 pcitool_swap_endian(local_data, size); 695 } else { 696 prg->data = local_data; 697 } 698 } 699 } 700 701 no_trap(); 702 return (rval); 703 } 704 705 /*ARGSUSED*/ 706 static int 707 pcitool_mem_access(dev_info_t *dip, pcitool_reg_t *prg, uint64_t virt_addr, 708 boolean_t write_flag) 709 { 710 size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 711 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 712 int rval = DDI_SUCCESS; 713 on_trap_data_t otd; 714 uint64_t local_data; 715 716 /* 717 * on_trap works like setjmp. 718 * 719 * A non-zero return here means on_trap has returned from an error. 720 * 721 * A zero return here means that on_trap has just returned from setup. 722 */ 723 if (on_trap(&otd, OT_DATA_ACCESS)) { 724 no_trap(); 725 if (pcitool_debug) 726 prom_printf( 727 "pcitool_mem_access: on_trap caught an error...\n"); 728 prg->status = PCITOOL_INVALID_ADDRESS; 729 return (EFAULT); 730 } 731 732 if (write_flag) { 733 734 if (big_endian) { 735 local_data = pcitool_swap_endian(prg->data, size); 736 } else { 737 local_data = prg->data; 738 } 739 740 switch (size) { 741 case 1: 742 *((uint8_t *)(uintptr_t)virt_addr) = local_data; 743 break; 744 case 2: 745 *((uint16_t *)(uintptr_t)virt_addr) = local_data; 746 break; 747 case 4: 748 *((uint32_t *)(uintptr_t)virt_addr) = local_data; 749 break; 750 case 8: 751 *((uint64_t *)(uintptr_t)virt_addr) = local_data; 752 break; 753 default: 754 rval = ENOTSUP; 755 prg->status = PCITOOL_INVALID_SIZE; 756 break; 757 } 758 } else { 759 switch (size) { 760 case 1: 761 local_data = *((uint8_t *)(uintptr_t)virt_addr); 762 break; 763 case 2: 764 local_data = *((uint16_t *)(uintptr_t)virt_addr); 765 break; 766 case 4: 767 local_data = *((uint32_t *)(uintptr_t)virt_addr); 768 break; 769 case 8: 770 local_data = *((uint64_t *)(uintptr_t)virt_addr); 771 break; 772 default: 773 rval = ENOTSUP; 774 prg->status = PCITOOL_INVALID_SIZE; 775 break; 776 } 777 778 if (rval == SUCCESS) { 779 if (big_endian) { 780 prg->data = 781 pcitool_swap_endian(local_data, size); 782 } else { 783 prg->data = local_data; 784 } 785 } 786 } 787 788 no_trap(); 789 return (rval); 790 } 791 792 /* 793 * Map up to 2 pages which contain the address we want to access. 794 * 795 * Mapping should span no more than 8 bytes. With X86 it is possible for an 796 * 8 byte value to start on a 4 byte boundary, so it can cross a page boundary. 797 * We'll never have to map more than two pages. 798 */ 799 800 static uint64_t 801 pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages) 802 { 803 804 uint64_t page_base = phys_addr & ~MMU_PAGEOFFSET; 805 uint64_t offset = phys_addr & MMU_PAGEOFFSET; 806 void *virt_base; 807 uint64_t returned_addr; 808 pfn_t pfn; 809 810 if (pcitool_debug) 811 prom_printf("pcitool_map: Called with PA:0x%p\n", 812 (uint8_t *)(uintptr_t)phys_addr); 813 814 *num_pages = 1; 815 816 /* Desired mapping would span more than two pages. */ 817 if ((offset + size) > (MMU_PAGESIZE * 2)) { 818 if (pcitool_debug) 819 prom_printf("boundary violation: " 820 "offset:0x%" PRIx64 ", size:%ld, pagesize:0x%lx\n", 821 offset, (uintptr_t)size, (uintptr_t)MMU_PAGESIZE); 822 return (NULL); 823 824 } else if ((offset + size) > MMU_PAGESIZE) { 825 (*num_pages)++; 826 } 827 828 /* Get page(s) of virtual space. */ 829 virt_base = vmem_alloc(heap_arena, ptob(*num_pages), VM_NOSLEEP); 830 if (virt_base == NULL) { 831 if (pcitool_debug) 832 prom_printf("Couldn't get virtual base address.\n"); 833 return (NULL); 834 } 835 836 if (pcitool_debug) 837 prom_printf("Got base virtual address:0x%p\n", virt_base); 838 839 pfn = btop(page_base); 840 841 /* Now map the allocated virtual space to the physical address. */ 842 hat_devload(kas.a_hat, virt_base, mmu_ptob(*num_pages), pfn, 843 PROT_READ | PROT_WRITE | HAT_STRICTORDER, 844 HAT_LOAD_LOCK); 845 846 returned_addr = ((uintptr_t)(virt_base)) + offset; 847 848 if (pcitool_debug) 849 prom_printf("pcitool_map: returning VA:0x%p\n", 850 (void *)(uintptr_t)returned_addr); 851 852 return (returned_addr); 853 } 854 855 /* Unmap the mapped page(s). */ 856 static void 857 pcitool_unmap(uint64_t virt_addr, size_t num_pages) 858 { 859 void *base_virt_addr = (void *)(uintptr_t)(virt_addr & ~MMU_PAGEOFFSET); 860 861 hat_unload(kas.a_hat, base_virt_addr, ptob(num_pages), 862 HAT_UNLOAD_UNLOCK); 863 vmem_free(heap_arena, base_virt_addr, ptob(num_pages)); 864 } 865 866 867 /* Perform register accesses on PCI leaf devices. */ 868 int 869 pcitool_dev_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 870 { 871 boolean_t write_flag = B_FALSE; 872 int rval = 0; 873 pcitool_reg_t prg; 874 uint8_t size; 875 876 uint64_t base_addr; 877 uint64_t virt_addr; 878 size_t num_virt_pages; 879 880 switch (cmd) { 881 case (PCITOOL_DEVICE_SET_REG): 882 write_flag = B_TRUE; 883 884 /*FALLTHRU*/ 885 case (PCITOOL_DEVICE_GET_REG): 886 if (pcitool_debug) 887 prom_printf("pci_dev_reg_ops set/get reg\n"); 888 if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) != 889 DDI_SUCCESS) { 890 if (pcitool_debug) 891 prom_printf("Error reading arguments\n"); 892 return (EFAULT); 893 } 894 895 if (prg.barnum >= (sizeof (pci_bars) / sizeof (pci_bars[0]))) { 896 prg.status = PCITOOL_OUT_OF_RANGE; 897 rval = EINVAL; 898 goto done_reg; 899 } 900 901 if (pcitool_debug) 902 prom_printf("raw bus:0x%x, dev:0x%x, func:0x%x\n", 903 prg.bus_no, prg.dev_no, prg.func_no); 904 /* Validate address arguments of bus / dev / func */ 905 if (((prg.bus_no & 906 (PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT)) != 907 prg.bus_no) || 908 ((prg.dev_no & 909 (PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) != 910 prg.dev_no) || 911 ((prg.func_no & 912 (PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT)) != 913 prg.func_no)) { 914 prg.status = PCITOOL_INVALID_ADDRESS; 915 rval = EINVAL; 916 goto done_reg; 917 } 918 919 size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr); 920 921 /* Proper config space desired. */ 922 if (prg.barnum == 0) { 923 924 if (pcitool_debug) 925 prom_printf( 926 "config access: offset:0x%" PRIx64 ", " 927 "phys_addr:0x%" PRIx64 "\n", 928 prg.offset, prg.phys_addr); 929 930 if (prg.offset >= max_cfg_size) { 931 prg.status = PCITOOL_OUT_OF_RANGE; 932 rval = EINVAL; 933 goto done_reg; 934 } 935 936 /* 937 * Access device. prg is modified. 938 * First, check for AMD northbridges for I/O access 939 * (This fix will move in future to pcitool user-land) 940 * Next, check for PCIe devices and do 941 * memory-mapped access 942 * Lastly, check for PCI devices and do I/O access 943 */ 944 if ((prg.bus_no == 0) && 945 (prg.dev_no >= 0x18) && 946 (prg.dev_no < (0x18 + ncpus))) { 947 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) 948 rval = pcitool_cfg_access(dip, &prg, 949 write_flag); 950 } else if (max_cfg_size == PCIE_CONF_HDR_SIZE) 951 rval = pcitool_pciex_cfg_access(dip, &prg, 952 write_flag); 953 else 954 rval = pcitool_cfg_access(dip, &prg, 955 write_flag); 956 957 if (pcitool_debug) 958 prom_printf( 959 "config access: data:0x%" PRIx64 "\n", 960 prg.data); 961 962 /* IO/ MEM/ MEM64 space. */ 963 } else { 964 965 pcitool_reg_t prg2; 966 bcopy(&prg, &prg2, sizeof (pcitool_reg_t)); 967 968 /* 969 * Translate BAR number into offset of the BAR in 970 * the device's config space. 971 */ 972 prg2.offset = pci_bars[prg2.barnum]; 973 prg2.acc_attr = 974 PCITOOL_ACC_ATTR_SIZE_4 | PCITOOL_ACC_ATTR_ENDN_LTL; 975 976 if (pcitool_debug) 977 prom_printf( 978 "barnum:%d, bar_offset:0x%" PRIx64 "\n", 979 prg2.barnum, prg2.offset); 980 /* 981 * Get Bus Address Register (BAR) from config space. 982 * prg2.offset is the offset into config space of the 983 * BAR desired. prg.status is modified on error. 984 */ 985 rval = pcitool_cfg_access(dip, &prg2, B_FALSE); 986 if (rval != SUCCESS) { 987 if (pcitool_debug) 988 prom_printf("BAR access failed\n"); 989 prg.status = prg2.status; 990 goto done_reg; 991 } 992 /* 993 * Reference proper PCI space based on the BAR. 994 * If 64 bit MEM space, need to load other half of the 995 * BAR first. 996 */ 997 998 if (pcitool_debug) 999 prom_printf("bar returned is 0x%" PRIx64 "\n", 1000 prg2.data); 1001 if (!prg2.data) { 1002 if (pcitool_debug) 1003 prom_printf("BAR data == 0\n"); 1004 rval = EINVAL; 1005 prg.status = PCITOOL_INVALID_ADDRESS; 1006 goto done_reg; 1007 } 1008 if (prg2.data == 0xffffffff) { 1009 if (pcitool_debug) 1010 prom_printf("BAR data == -1\n"); 1011 rval = EINVAL; 1012 prg.status = PCITOOL_INVALID_ADDRESS; 1013 goto done_reg; 1014 } 1015 1016 /* 1017 * BAR has bits saying this space is IO space, unless 1018 * this is the ROM address register. 1019 */ 1020 if (((PCI_BASE_SPACE_M & prg2.data) == 1021 PCI_BASE_SPACE_IO) && 1022 (prg2.offset != PCI_CONF_ROM)) { 1023 if (pcitool_debug) 1024 prom_printf("IO space\n"); 1025 1026 prg2.data &= PCI_BASE_IO_ADDR_M; 1027 prg.phys_addr = prg2.data + prg.offset; 1028 1029 rval = pcitool_io_access(dip, &prg, write_flag); 1030 if ((rval != SUCCESS) && (pcitool_debug)) 1031 prom_printf("IO access failed\n"); 1032 1033 goto done_reg; 1034 1035 1036 /* 1037 * BAR has bits saying this space is 64 bit memory 1038 * space, unless this is the ROM address register. 1039 * 1040 * The 64 bit address stored in two BAR cells is not 1041 * necessarily aligned on an 8-byte boundary. 1042 * Need to keep the first 4 bytes read, 1043 * and do a separate read of the high 4 bytes. 1044 */ 1045 1046 } else if ((PCI_BASE_TYPE_ALL & prg2.data) && 1047 (prg2.offset != PCI_CONF_ROM)) { 1048 1049 uint32_t low_bytes = 1050 (uint32_t)(prg2.data & ~PCI_BASE_TYPE_ALL); 1051 1052 /* 1053 * Don't try to read the next 4 bytes 1054 * past the end of BARs. 1055 */ 1056 if (prg2.offset >= PCI_CONF_BASE5) { 1057 prg.status = PCITOOL_OUT_OF_RANGE; 1058 rval = EIO; 1059 goto done_reg; 1060 } 1061 1062 /* 1063 * Access device. 1064 * prg2.status is modified on error. 1065 */ 1066 prg2.offset += 4; 1067 rval = pcitool_cfg_access(dip, &prg2, B_FALSE); 1068 if (rval != SUCCESS) { 1069 prg.status = prg2.status; 1070 goto done_reg; 1071 } 1072 1073 if (prg2.data == 0xffffffff) { 1074 prg.status = PCITOOL_INVALID_ADDRESS; 1075 prg.status = EFAULT; 1076 goto done_reg; 1077 } 1078 1079 prg2.data = (prg2.data << 32) + low_bytes; 1080 if (pcitool_debug) 1081 prom_printf( 1082 "64 bit mem space. " 1083 "64-bit bar is 0x%" PRIx64 "\n", 1084 prg2.data); 1085 1086 /* Mem32 space, including ROM */ 1087 } else { 1088 1089 if (prg2.offset == PCI_CONF_ROM) { 1090 if (pcitool_debug) 1091 prom_printf( 1092 "Additional ROM " 1093 "checking\n"); 1094 /* Can't write to ROM */ 1095 if (write_flag) { 1096 prg.status = PCITOOL_ROM_WRITE; 1097 rval = EIO; 1098 goto done_reg; 1099 1100 /* ROM disabled for reading */ 1101 } else if (!(prg2.data & 0x00000001)) { 1102 prg.status = 1103 PCITOOL_ROM_DISABLED; 1104 rval = EIO; 1105 goto done_reg; 1106 } 1107 } 1108 1109 if (pcitool_debug) 1110 prom_printf("32 bit mem space\n"); 1111 } 1112 1113 /* Common code for all IO/MEM range spaces. */ 1114 1115 base_addr = prg2.data; 1116 if (pcitool_debug) 1117 prom_printf( 1118 "addr portion of bar is 0x%" PRIx64 ", " 1119 "base=0x%" PRIx64 ", " 1120 "offset:0x%" PRIx64 "\n", 1121 prg2.data, base_addr, prg.offset); 1122 /* 1123 * Use offset provided by caller to index into 1124 * desired space, then access. 1125 * Note that prg.status is modified on error. 1126 */ 1127 prg.phys_addr = base_addr + prg.offset; 1128 1129 virt_addr = pcitool_map(prg.phys_addr, size, 1130 &num_virt_pages); 1131 if (virt_addr == NULL) { 1132 prg.status = PCITOOL_IO_ERROR; 1133 rval = EIO; 1134 goto done_reg; 1135 } 1136 1137 rval = pcitool_mem_access(dip, &prg, virt_addr, 1138 write_flag); 1139 pcitool_unmap(virt_addr, num_virt_pages); 1140 } 1141 done_reg: 1142 prg.drvr_version = PCITOOL_VERSION; 1143 if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t), mode) != 1144 DDI_SUCCESS) { 1145 if (pcitool_debug) 1146 prom_printf("Error returning arguments.\n"); 1147 rval = EFAULT; 1148 } 1149 break; 1150 default: 1151 rval = ENOTTY; 1152 break; 1153 } 1154 return (rval); 1155 } 1156