1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 #include <sys/types.h> 26 #include <sys/mkdev.h> 27 #include <sys/stat.h> 28 #include <sys/sunddi.h> 29 #include <vm/seg_kmem.h> 30 #include <sys/machparam.h> 31 #include <sys/sunndi.h> 32 #include <sys/ontrap.h> 33 #include <sys/psm.h> 34 #include <sys/pcie.h> 35 #include <sys/pci_cfgspace.h> 36 #include <sys/pci_tools.h> 37 #include <io/pci/pci_tools_ext.h> 38 #include <sys/apic.h> 39 #include <io/pci/pci_var.h> 40 #include <sys/pci_impl.h> 41 #include <sys/promif.h> 42 #include <sys/x86_archext.h> 43 #include <sys/cpuvar.h> 44 #include <sys/pci_cfgacc.h> 45 46 #ifdef __xpv 47 #include <sys/hypervisor.h> 48 #endif 49 50 #define PCIEX_BDF_OFFSET_DELTA 4 51 #define PCIEX_REG_FUNC_SHIFT (PCI_REG_FUNC_SHIFT + PCIEX_BDF_OFFSET_DELTA) 52 #define PCIEX_REG_DEV_SHIFT (PCI_REG_DEV_SHIFT + PCIEX_BDF_OFFSET_DELTA) 53 #define PCIEX_REG_BUS_SHIFT (PCI_REG_BUS_SHIFT + PCIEX_BDF_OFFSET_DELTA) 54 55 #define SUCCESS 0 56 57 extern uint64_t mcfg_mem_base; 58 int pcitool_debug = 0; 59 60 /* 61 * Offsets of BARS in config space. First entry of 0 means config space. 62 * Entries here correlate to pcitool_bars_t enumerated type. 63 */ 64 static uint8_t pci_bars[] = { 65 0x0, 66 PCI_CONF_BASE0, 67 PCI_CONF_BASE1, 68 PCI_CONF_BASE2, 69 PCI_CONF_BASE3, 70 PCI_CONF_BASE4, 71 PCI_CONF_BASE5, 72 PCI_CONF_ROM 73 }; 74 75 /* Max offset allowed into config space for a particular device. */ 76 static uint64_t max_cfg_size = PCI_CONF_HDR_SIZE; 77 78 static uint64_t pcitool_swap_endian(uint64_t data, int size); 79 static int pcitool_cfg_access(pcitool_reg_t *prg, boolean_t write_flag, 80 boolean_t io_access); 81 static int pcitool_io_access(pcitool_reg_t *prg, boolean_t write_flag); 82 static int pcitool_mem_access(pcitool_reg_t *prg, uint64_t virt_addr, 83 boolean_t write_flag); 84 static uint64_t pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages); 85 static void pcitool_unmap(uint64_t virt_addr, size_t num_pages); 86 87 /* Extern declarations */ 88 extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, 89 psm_intr_op_t, int *); 90 91 int 92 pcitool_init(dev_info_t *dip, boolean_t is_pciex) 93 { 94 int instance = ddi_get_instance(dip); 95 96 /* Create pcitool nodes for register access and interrupt routing. */ 97 98 if (ddi_create_minor_node(dip, PCI_MINOR_REG, S_IFCHR, 99 PCI_MINOR_NUM(instance, PCI_TOOL_REG_MINOR_NUM), 100 DDI_NT_REGACC, 0) != DDI_SUCCESS) { 101 return (DDI_FAILURE); 102 } 103 104 if (ddi_create_minor_node(dip, PCI_MINOR_INTR, S_IFCHR, 105 PCI_MINOR_NUM(instance, PCI_TOOL_INTR_MINOR_NUM), 106 DDI_NT_INTRCTL, 0) != DDI_SUCCESS) { 107 ddi_remove_minor_node(dip, PCI_MINOR_REG); 108 return (DDI_FAILURE); 109 } 110 111 if (is_pciex) 112 max_cfg_size = PCIE_CONF_HDR_SIZE; 113 114 return (DDI_SUCCESS); 115 } 116 117 void 118 pcitool_uninit(dev_info_t *dip) 119 { 120 ddi_remove_minor_node(dip, PCI_MINOR_INTR); 121 ddi_remove_minor_node(dip, PCI_MINOR_REG); 122 } 123 124 /*ARGSUSED*/ 125 static int 126 pcitool_set_intr(dev_info_t *dip, void *arg, int mode) 127 { 128 ddi_intr_handle_impl_t info_hdl; 129 pcitool_intr_set_t iset; 130 uint32_t old_cpu; 131 int ret, result; 132 size_t copyinout_size; 133 int rval = SUCCESS; 134 135 /* Version 1 of pcitool_intr_set_t doesn't have flags. */ 136 copyinout_size = (size_t)&iset.flags - (size_t)&iset; 137 138 if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS) 139 return (EFAULT); 140 141 switch (iset.user_version) { 142 case PCITOOL_V1: 143 break; 144 145 case PCITOOL_V2: 146 copyinout_size = sizeof (pcitool_intr_set_t); 147 if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS) 148 return (EFAULT); 149 break; 150 151 default: 152 iset.status = PCITOOL_OUT_OF_RANGE; 153 rval = ENOTSUP; 154 goto done_set_intr; 155 } 156 157 if (iset.flags & PCITOOL_INTR_FLAG_SET_MSI) { 158 rval = ENOTSUP; 159 iset.status = PCITOOL_IO_ERROR; 160 goto done_set_intr; 161 } 162 163 if (iset.ino > APIC_MAX_VECTOR) { 164 rval = EINVAL; 165 iset.status = PCITOOL_INVALID_INO; 166 goto done_set_intr; 167 } 168 169 iset.status = PCITOOL_SUCCESS; 170 171 if ((old_cpu = pci_get_cpu_from_vecirq(iset.ino, IS_VEC)) == -1) { 172 iset.status = PCITOOL_IO_ERROR; 173 rval = EINVAL; 174 goto done_set_intr; 175 } 176 177 178 old_cpu &= ~PSMGI_CPU_USER_BOUND; 179 180 /* 181 * For this locally-declared and used handle, ih_private will contain a 182 * CPU value, not an ihdl_plat_t as used for global interrupt handling. 183 */ 184 info_hdl.ih_vector = iset.ino; 185 info_hdl.ih_private = (void *)(uintptr_t)iset.cpu_id; 186 info_hdl.ih_flags = PSMGI_INTRBY_VEC; 187 if (pcitool_debug) 188 prom_printf("user version:%d, flags:0x%x\n", 189 iset.user_version, iset.flags); 190 191 result = ENOTSUP; 192 if ((iset.user_version >= PCITOOL_V2) && 193 (iset.flags & PCITOOL_INTR_FLAG_SET_GROUP)) { 194 ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_GRP_SET_CPU, 195 &result); 196 } else { 197 ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_SET_CPU, 198 &result); 199 } 200 201 if (ret != PSM_SUCCESS) { 202 switch (result) { 203 case EIO: /* Error making the change */ 204 rval = EIO; 205 iset.status = PCITOOL_IO_ERROR; 206 break; 207 case ENXIO: /* Couldn't convert vector to irq */ 208 rval = EINVAL; 209 iset.status = PCITOOL_INVALID_INO; 210 break; 211 case EINVAL: /* CPU out of range */ 212 rval = EINVAL; 213 iset.status = PCITOOL_INVALID_CPUID; 214 break; 215 case ENOTSUP: /* Requested PSM intr ops missing */ 216 rval = ENOTSUP; 217 iset.status = PCITOOL_IO_ERROR; 218 break; 219 } 220 } 221 222 /* Return original CPU. */ 223 iset.cpu_id = old_cpu; 224 225 done_set_intr: 226 iset.drvr_version = PCITOOL_VERSION; 227 if (ddi_copyout(&iset, arg, copyinout_size, mode) != DDI_SUCCESS) 228 rval = EFAULT; 229 return (rval); 230 } 231 232 233 /* It is assumed that dip != NULL */ 234 static void 235 pcitool_get_intr_dev_info(dev_info_t *dip, pcitool_intr_dev_t *devs) 236 { 237 (void) strncpy(devs->driver_name, 238 ddi_driver_name(dip), MAXMODCONFNAME-2); 239 devs->driver_name[MAXMODCONFNAME-1] = '\0'; 240 (void) ddi_pathname(dip, devs->path); 241 devs->dev_inst = ddi_get_instance(dip); 242 } 243 244 static int 245 pcitool_get_intr(dev_info_t *dip, void *arg, int mode) 246 { 247 /* Array part isn't used here, but oh well... */ 248 pcitool_intr_get_t partial_iget; 249 pcitool_intr_get_t *iget = &partial_iget; 250 size_t iget_kmem_alloc_size = 0; 251 uint8_t num_devs_ret; 252 int copyout_rval; 253 int rval = SUCCESS; 254 int circ; 255 int i; 256 257 ddi_intr_handle_impl_t info_hdl; 258 apic_get_intr_t intr_info; 259 260 /* Read in just the header part, no array section. */ 261 if (ddi_copyin(arg, &partial_iget, PCITOOL_IGET_SIZE(0), mode) != 262 DDI_SUCCESS) 263 return (EFAULT); 264 265 if (partial_iget.flags & PCITOOL_INTR_FLAG_GET_MSI) { 266 partial_iget.status = PCITOOL_IO_ERROR; 267 partial_iget.num_devs_ret = 0; 268 rval = ENOTSUP; 269 goto done_get_intr; 270 } 271 272 /* Validate argument. */ 273 if (partial_iget.ino > APIC_MAX_VECTOR) { 274 partial_iget.status = PCITOOL_INVALID_INO; 275 partial_iget.num_devs_ret = 0; 276 rval = EINVAL; 277 goto done_get_intr; 278 } 279 280 num_devs_ret = partial_iget.num_devs_ret; 281 intr_info.avgi_dip_list = NULL; 282 intr_info.avgi_req_flags = 283 PSMGI_REQ_CPUID | PSMGI_REQ_NUM_DEVS | PSMGI_INTRBY_VEC; 284 /* 285 * For this locally-declared and used handle, ih_private will contain a 286 * pointer to apic_get_intr_t, not an ihdl_plat_t as used for 287 * global interrupt handling. 288 */ 289 info_hdl.ih_private = &intr_info; 290 info_hdl.ih_vector = partial_iget.ino; 291 292 /* Caller wants device information returned. */ 293 if (num_devs_ret > 0) { 294 295 intr_info.avgi_req_flags |= PSMGI_REQ_GET_DEVS; 296 297 /* 298 * Allocate room. 299 * If num_devs_ret == 0 iget remains pointing to partial_iget. 300 */ 301 iget_kmem_alloc_size = PCITOOL_IGET_SIZE(num_devs_ret); 302 iget = kmem_alloc(iget_kmem_alloc_size, KM_SLEEP); 303 304 /* Read in whole structure to verify there's room. */ 305 if (ddi_copyin(arg, iget, iget_kmem_alloc_size, mode) != 306 SUCCESS) { 307 308 /* Be consistent and just return EFAULT here. */ 309 kmem_free(iget, iget_kmem_alloc_size); 310 311 return (EFAULT); 312 } 313 } 314 315 bzero(iget, PCITOOL_IGET_SIZE(num_devs_ret)); 316 iget->ino = info_hdl.ih_vector; 317 318 /* 319 * Lock device tree branch from the pci root nexus on down if info will 320 * be extracted from dips returned from the tree. 321 */ 322 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 323 ndi_devi_enter(dip, &circ); 324 } 325 326 /* Call psm_intr_ops(PSM_INTR_OP_GET_INTR) to get information. */ 327 if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 328 PSM_INTR_OP_GET_INTR, NULL)) != PSM_SUCCESS) { 329 iget->status = PCITOOL_IO_ERROR; 330 iget->num_devs_ret = 0; 331 rval = EINVAL; 332 goto done_get_intr; 333 } 334 335 /* 336 * Fill in the pcitool_intr_get_t to be returned, 337 * with the CPU, num_devs_ret and num_devs. 338 */ 339 iget->cpu_id = intr_info.avgi_cpu_id & ~PSMGI_CPU_USER_BOUND; 340 341 /* Number of devices returned by apic. */ 342 iget->num_devs = intr_info.avgi_num_devs; 343 344 /* Device info was returned. */ 345 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 346 347 /* 348 * num devs returned is num devs ret by apic, 349 * space permitting. 350 */ 351 iget->num_devs_ret = min(num_devs_ret, intr_info.avgi_num_devs); 352 353 /* 354 * Loop thru list of dips and extract driver, name and instance. 355 * Fill in the pcitool_intr_dev_t's with this info. 356 */ 357 for (i = 0; i < iget->num_devs_ret; i++) 358 pcitool_get_intr_dev_info(intr_info.avgi_dip_list[i], 359 &iget->dev[i]); 360 361 /* Free kmem_alloc'ed memory of the apic_get_intr_t */ 362 kmem_free(intr_info.avgi_dip_list, 363 intr_info.avgi_num_devs * sizeof (dev_info_t *)); 364 } 365 366 done_get_intr: 367 368 if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 369 ndi_devi_exit(dip, circ); 370 } 371 372 iget->drvr_version = PCITOOL_VERSION; 373 copyout_rval = ddi_copyout(iget, arg, 374 PCITOOL_IGET_SIZE(num_devs_ret), mode); 375 376 if (iget_kmem_alloc_size > 0) 377 kmem_free(iget, iget_kmem_alloc_size); 378 379 if (copyout_rval != DDI_SUCCESS) 380 rval = EFAULT; 381 382 return (rval); 383 } 384 385 /*ARGSUSED*/ 386 static int 387 pcitool_intr_info(dev_info_t *dip, void *arg, int mode) 388 { 389 pcitool_intr_info_t intr_info; 390 ddi_intr_handle_impl_t info_hdl; 391 int rval = SUCCESS; 392 393 /* If we need user_version, and to ret same user version as passed in */ 394 if (ddi_copyin(arg, &intr_info, sizeof (pcitool_intr_info_t), mode) != 395 DDI_SUCCESS) { 396 if (pcitool_debug) 397 prom_printf("Error reading arguments\n"); 398 return (EFAULT); 399 } 400 401 if (intr_info.flags & PCITOOL_INTR_FLAG_GET_MSI) 402 return (ENOTSUP); 403 404 /* For UPPC systems, psm_intr_ops has no entry for APIC_TYPE. */ 405 if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 406 PSM_INTR_OP_APIC_TYPE, NULL)) != PSM_SUCCESS) { 407 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UPPC; 408 intr_info.ctlr_version = 0; 409 410 } else { 411 intr_info.ctlr_version = (uint32_t)info_hdl.ih_ver; 412 if (strcmp((char *)info_hdl.ih_private, 413 APIC_PCPLUSMP_NAME) == 0) 414 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_PCPLUSMP; 415 else 416 intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UNKNOWN; 417 } 418 419 intr_info.num_intr = APIC_MAX_VECTOR; 420 intr_info.drvr_version = PCITOOL_VERSION; 421 if (ddi_copyout(&intr_info, arg, sizeof (pcitool_intr_info_t), mode) != 422 DDI_SUCCESS) { 423 if (pcitool_debug) 424 prom_printf("Error returning arguments.\n"); 425 rval = EFAULT; 426 } 427 428 return (rval); 429 } 430 431 432 433 /* 434 * Main function for handling interrupt CPU binding requests and queries. 435 * Need to implement later 436 */ 437 int 438 pcitool_intr_admn(dev_info_t *dip, void *arg, int cmd, int mode) 439 { 440 int rval; 441 442 switch (cmd) { 443 444 /* Associate a new CPU with a given vector */ 445 case PCITOOL_DEVICE_SET_INTR: 446 rval = pcitool_set_intr(dip, arg, mode); 447 break; 448 449 case PCITOOL_DEVICE_GET_INTR: 450 rval = pcitool_get_intr(dip, arg, mode); 451 break; 452 453 case PCITOOL_SYSTEM_INTR_INFO: 454 rval = pcitool_intr_info(dip, arg, mode); 455 break; 456 457 default: 458 rval = ENOTSUP; 459 } 460 461 return (rval); 462 } 463 464 /* 465 * Perform register accesses on the nexus device itself. 466 * No explicit PCI nexus device for X86, so not applicable. 467 */ 468 469 /*ARGSUSED*/ 470 int 471 pcitool_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 472 { 473 return (ENOTSUP); 474 } 475 476 /* Swap endianness. */ 477 static uint64_t 478 pcitool_swap_endian(uint64_t data, int size) 479 { 480 typedef union { 481 uint64_t data64; 482 uint8_t data8[8]; 483 } data_split_t; 484 485 data_split_t orig_data; 486 data_split_t returned_data; 487 int i; 488 489 orig_data.data64 = data; 490 returned_data.data64 = 0; 491 492 for (i = 0; i < size; i++) { 493 returned_data.data8[i] = orig_data.data8[size - 1 - i]; 494 } 495 496 return (returned_data.data64); 497 } 498 499 /* 500 * A note about ontrap handling: 501 * 502 * X86 systems on which this module was tested return FFs instead of bus errors 503 * when accessing devices with invalid addresses. Ontrap handling, which 504 * gracefully handles kernel bus errors, is installed anyway for I/O and mem 505 * space accessing (not for pci config space), in case future X86 platforms 506 * require it. 507 */ 508 509 /* Access device. prg is modified. */ 510 static int 511 pcitool_cfg_access(pcitool_reg_t *prg, boolean_t write_flag, 512 boolean_t io_access) 513 { 514 int size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 515 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 516 int rval = SUCCESS; 517 uint64_t local_data; 518 pci_cfgacc_req_t req; 519 uint32_t max_offset; 520 521 if ((size <= 0) || (size > 8) || ((size & (size - 1)) != 0)) { 522 prg->status = PCITOOL_INVALID_SIZE; 523 return (ENOTSUP); 524 } 525 526 /* 527 * NOTE: there is no way to verify whether or not the address is 528 * valid other than that it is within the maximum offset. The 529 * put functions return void and the get functions return -1 on error. 530 */ 531 532 if (io_access) 533 max_offset = 0xFF; 534 else 535 max_offset = 0xFFF; 536 if (prg->offset + size - 1 > max_offset) { 537 prg->status = PCITOOL_INVALID_ADDRESS; 538 return (ENOTSUP); 539 } 540 541 prg->status = PCITOOL_SUCCESS; 542 543 req.rcdip = NULL; 544 req.bdf = PCI_GETBDF(prg->bus_no, prg->dev_no, prg->func_no); 545 req.offset = prg->offset; 546 req.size = size; 547 req.write = write_flag; 548 req.ioacc = io_access; 549 if (write_flag) { 550 if (big_endian) { 551 local_data = pcitool_swap_endian(prg->data, size); 552 } else { 553 local_data = prg->data; 554 } 555 VAL64(&req) = local_data; 556 pci_cfgacc_acc(&req); 557 } else { 558 pci_cfgacc_acc(&req); 559 switch (size) { 560 case 1: 561 local_data = VAL8(&req); 562 break; 563 case 2: 564 local_data = VAL16(&req); 565 break; 566 case 4: 567 local_data = VAL32(&req); 568 break; 569 case 8: 570 local_data = VAL64(&req); 571 break; 572 } 573 if (big_endian) { 574 prg->data = 575 pcitool_swap_endian(local_data, size); 576 } else { 577 prg->data = local_data; 578 } 579 } 580 /* 581 * Check if legacy IO config access is used, in which case 582 * only first 256 bytes are valid. 583 */ 584 if (req.ioacc && (prg->offset + size - 1 > 0xFF)) { 585 prg->status = PCITOOL_INVALID_ADDRESS; 586 return (ENOTSUP); 587 } 588 589 /* Set phys_addr only if MMIO is used */ 590 prg->phys_addr = 0; 591 if (!req.ioacc && mcfg_mem_base != 0) { 592 prg->phys_addr = mcfg_mem_base + prg->offset + 593 ((prg->bus_no << PCIEX_REG_BUS_SHIFT) | 594 (prg->dev_no << PCIEX_REG_DEV_SHIFT) | 595 (prg->func_no << PCIEX_REG_FUNC_SHIFT)); 596 } 597 598 return (rval); 599 } 600 601 static int 602 pcitool_io_access(pcitool_reg_t *prg, boolean_t write_flag) 603 { 604 int port = (int)prg->phys_addr; 605 size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 606 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 607 int rval = SUCCESS; 608 on_trap_data_t otd; 609 uint64_t local_data; 610 611 612 /* 613 * on_trap works like setjmp. 614 * 615 * A non-zero return here means on_trap has returned from an error. 616 * 617 * A zero return here means that on_trap has just returned from setup. 618 */ 619 if (on_trap(&otd, OT_DATA_ACCESS)) { 620 no_trap(); 621 if (pcitool_debug) 622 prom_printf( 623 "pcitool_io_access: on_trap caught an error...\n"); 624 prg->status = PCITOOL_INVALID_ADDRESS; 625 return (EFAULT); 626 } 627 628 if (write_flag) { 629 630 if (big_endian) { 631 local_data = pcitool_swap_endian(prg->data, size); 632 } else { 633 local_data = prg->data; 634 } 635 636 if (pcitool_debug) 637 prom_printf("Writing %ld byte(s) to port 0x%x\n", 638 size, port); 639 640 switch (size) { 641 case 1: 642 outb(port, (uint8_t)local_data); 643 break; 644 case 2: 645 outw(port, (uint16_t)local_data); 646 break; 647 case 4: 648 outl(port, (uint32_t)local_data); 649 break; 650 default: 651 rval = ENOTSUP; 652 prg->status = PCITOOL_INVALID_SIZE; 653 break; 654 } 655 } else { 656 if (pcitool_debug) 657 prom_printf("Reading %ld byte(s) from port 0x%x\n", 658 size, port); 659 660 switch (size) { 661 case 1: 662 local_data = inb(port); 663 break; 664 case 2: 665 local_data = inw(port); 666 break; 667 case 4: 668 local_data = inl(port); 669 break; 670 default: 671 rval = ENOTSUP; 672 prg->status = PCITOOL_INVALID_SIZE; 673 break; 674 } 675 676 if (rval == SUCCESS) { 677 if (big_endian) { 678 prg->data = 679 pcitool_swap_endian(local_data, size); 680 } else { 681 prg->data = local_data; 682 } 683 } 684 } 685 686 no_trap(); 687 return (rval); 688 } 689 690 static int 691 pcitool_mem_access(pcitool_reg_t *prg, uint64_t virt_addr, boolean_t write_flag) 692 { 693 size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 694 boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 695 int rval = DDI_SUCCESS; 696 on_trap_data_t otd; 697 uint64_t local_data; 698 699 /* 700 * on_trap works like setjmp. 701 * 702 * A non-zero return here means on_trap has returned from an error. 703 * 704 * A zero return here means that on_trap has just returned from setup. 705 */ 706 if (on_trap(&otd, OT_DATA_ACCESS)) { 707 no_trap(); 708 if (pcitool_debug) 709 prom_printf( 710 "pcitool_mem_access: on_trap caught an error...\n"); 711 prg->status = PCITOOL_INVALID_ADDRESS; 712 return (EFAULT); 713 } 714 715 if (write_flag) { 716 717 if (big_endian) { 718 local_data = pcitool_swap_endian(prg->data, size); 719 } else { 720 local_data = prg->data; 721 } 722 723 switch (size) { 724 case 1: 725 *((uint8_t *)(uintptr_t)virt_addr) = local_data; 726 break; 727 case 2: 728 *((uint16_t *)(uintptr_t)virt_addr) = local_data; 729 break; 730 case 4: 731 *((uint32_t *)(uintptr_t)virt_addr) = local_data; 732 break; 733 case 8: 734 *((uint64_t *)(uintptr_t)virt_addr) = local_data; 735 break; 736 default: 737 rval = ENOTSUP; 738 prg->status = PCITOOL_INVALID_SIZE; 739 break; 740 } 741 } else { 742 switch (size) { 743 case 1: 744 local_data = *((uint8_t *)(uintptr_t)virt_addr); 745 break; 746 case 2: 747 local_data = *((uint16_t *)(uintptr_t)virt_addr); 748 break; 749 case 4: 750 local_data = *((uint32_t *)(uintptr_t)virt_addr); 751 break; 752 case 8: 753 local_data = *((uint64_t *)(uintptr_t)virt_addr); 754 break; 755 default: 756 rval = ENOTSUP; 757 prg->status = PCITOOL_INVALID_SIZE; 758 break; 759 } 760 761 if (rval == SUCCESS) { 762 if (big_endian) { 763 prg->data = 764 pcitool_swap_endian(local_data, size); 765 } else { 766 prg->data = local_data; 767 } 768 } 769 } 770 771 no_trap(); 772 return (rval); 773 } 774 775 /* 776 * Map up to 2 pages which contain the address we want to access. 777 * 778 * Mapping should span no more than 8 bytes. With X86 it is possible for an 779 * 8 byte value to start on a 4 byte boundary, so it can cross a page boundary. 780 * We'll never have to map more than two pages. 781 */ 782 783 static uint64_t 784 pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages) 785 { 786 787 uint64_t page_base = phys_addr & ~MMU_PAGEOFFSET; 788 uint64_t offset = phys_addr & MMU_PAGEOFFSET; 789 void *virt_base; 790 uint64_t returned_addr; 791 pfn_t pfn; 792 793 if (pcitool_debug) 794 prom_printf("pcitool_map: Called with PA:0x%p\n", 795 (void *)(uintptr_t)phys_addr); 796 797 *num_pages = 1; 798 799 /* Desired mapping would span more than two pages. */ 800 if ((offset + size) > (MMU_PAGESIZE * 2)) { 801 if (pcitool_debug) 802 prom_printf("boundary violation: " 803 "offset:0x%" PRIx64 ", size:%ld, pagesize:0x%lx\n", 804 offset, (uintptr_t)size, (uintptr_t)MMU_PAGESIZE); 805 return (NULL); 806 807 } else if ((offset + size) > MMU_PAGESIZE) { 808 (*num_pages)++; 809 } 810 811 /* Get page(s) of virtual space. */ 812 virt_base = vmem_alloc(heap_arena, ptob(*num_pages), VM_NOSLEEP); 813 if (virt_base == NULL) { 814 if (pcitool_debug) 815 prom_printf("Couldn't get virtual base address.\n"); 816 return (NULL); 817 } 818 819 if (pcitool_debug) 820 prom_printf("Got base virtual address:0x%p\n", virt_base); 821 822 #ifdef __xpv 823 /* 824 * We should only get here if we are dom0. 825 * We're using a real device so we need to translate the MA to a PFN. 826 */ 827 ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); 828 pfn = xen_assign_pfn(mmu_btop(page_base)); 829 #else 830 pfn = btop(page_base); 831 #endif 832 833 /* Now map the allocated virtual space to the physical address. */ 834 hat_devload(kas.a_hat, virt_base, mmu_ptob(*num_pages), pfn, 835 PROT_READ | PROT_WRITE | HAT_STRICTORDER, 836 HAT_LOAD_LOCK); 837 838 returned_addr = ((uintptr_t)(virt_base)) + offset; 839 840 if (pcitool_debug) 841 prom_printf("pcitool_map: returning VA:0x%p\n", 842 (void *)(uintptr_t)returned_addr); 843 844 return (returned_addr); 845 } 846 847 /* Unmap the mapped page(s). */ 848 static void 849 pcitool_unmap(uint64_t virt_addr, size_t num_pages) 850 { 851 void *base_virt_addr = (void *)(uintptr_t)(virt_addr & ~MMU_PAGEOFFSET); 852 853 hat_unload(kas.a_hat, base_virt_addr, ptob(num_pages), 854 HAT_UNLOAD_UNLOCK); 855 vmem_free(heap_arena, base_virt_addr, ptob(num_pages)); 856 } 857 858 859 /* Perform register accesses on PCI leaf devices. */ 860 /*ARGSUSED*/ 861 int 862 pcitool_dev_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 863 { 864 boolean_t write_flag = B_FALSE; 865 boolean_t io_access = B_TRUE; 866 int rval = 0; 867 pcitool_reg_t prg; 868 uint8_t size; 869 870 uint64_t base_addr; 871 uint64_t virt_addr; 872 size_t num_virt_pages; 873 874 switch (cmd) { 875 case (PCITOOL_DEVICE_SET_REG): 876 write_flag = B_TRUE; 877 878 /*FALLTHRU*/ 879 case (PCITOOL_DEVICE_GET_REG): 880 if (pcitool_debug) 881 prom_printf("pci_dev_reg_ops set/get reg\n"); 882 if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) != 883 DDI_SUCCESS) { 884 if (pcitool_debug) 885 prom_printf("Error reading arguments\n"); 886 return (EFAULT); 887 } 888 889 if (prg.barnum >= (sizeof (pci_bars) / sizeof (pci_bars[0]))) { 890 prg.status = PCITOOL_OUT_OF_RANGE; 891 rval = EINVAL; 892 goto done_reg; 893 } 894 895 if (pcitool_debug) 896 prom_printf("raw bus:0x%x, dev:0x%x, func:0x%x\n", 897 prg.bus_no, prg.dev_no, prg.func_no); 898 /* Validate address arguments of bus / dev / func */ 899 if (((prg.bus_no & 900 (PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT)) != 901 prg.bus_no) || 902 ((prg.dev_no & 903 (PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) != 904 prg.dev_no) || 905 ((prg.func_no & 906 (PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT)) != 907 prg.func_no)) { 908 prg.status = PCITOOL_INVALID_ADDRESS; 909 rval = EINVAL; 910 goto done_reg; 911 } 912 913 size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr); 914 915 /* Proper config space desired. */ 916 if (prg.barnum == 0) { 917 918 if (pcitool_debug) 919 prom_printf( 920 "config access: offset:0x%" PRIx64 ", " 921 "phys_addr:0x%" PRIx64 "\n", 922 prg.offset, prg.phys_addr); 923 924 if (prg.offset >= max_cfg_size) { 925 prg.status = PCITOOL_OUT_OF_RANGE; 926 rval = EINVAL; 927 goto done_reg; 928 } 929 if (max_cfg_size == PCIE_CONF_HDR_SIZE) 930 io_access = B_FALSE; 931 932 rval = pcitool_cfg_access(&prg, write_flag, io_access); 933 if (pcitool_debug) 934 prom_printf( 935 "config access: data:0x%" PRIx64 "\n", 936 prg.data); 937 938 /* IO/ MEM/ MEM64 space. */ 939 } else { 940 941 pcitool_reg_t prg2; 942 bcopy(&prg, &prg2, sizeof (pcitool_reg_t)); 943 944 /* 945 * Translate BAR number into offset of the BAR in 946 * the device's config space. 947 */ 948 prg2.offset = pci_bars[prg2.barnum]; 949 prg2.acc_attr = 950 PCITOOL_ACC_ATTR_SIZE_4 | PCITOOL_ACC_ATTR_ENDN_LTL; 951 952 if (pcitool_debug) 953 prom_printf( 954 "barnum:%d, bar_offset:0x%" PRIx64 "\n", 955 prg2.barnum, prg2.offset); 956 /* 957 * Get Bus Address Register (BAR) from config space. 958 * prg2.offset is the offset into config space of the 959 * BAR desired. prg.status is modified on error. 960 */ 961 rval = pcitool_cfg_access(&prg2, B_FALSE, B_TRUE); 962 if (rval != SUCCESS) { 963 if (pcitool_debug) 964 prom_printf("BAR access failed\n"); 965 prg.status = prg2.status; 966 goto done_reg; 967 } 968 /* 969 * Reference proper PCI space based on the BAR. 970 * If 64 bit MEM space, need to load other half of the 971 * BAR first. 972 */ 973 974 if (pcitool_debug) 975 prom_printf("bar returned is 0x%" PRIx64 "\n", 976 prg2.data); 977 if (!prg2.data) { 978 if (pcitool_debug) 979 prom_printf("BAR data == 0\n"); 980 rval = EINVAL; 981 prg.status = PCITOOL_INVALID_ADDRESS; 982 goto done_reg; 983 } 984 if (prg2.data == 0xffffffff) { 985 if (pcitool_debug) 986 prom_printf("BAR data == -1\n"); 987 rval = EINVAL; 988 prg.status = PCITOOL_INVALID_ADDRESS; 989 goto done_reg; 990 } 991 992 /* 993 * BAR has bits saying this space is IO space, unless 994 * this is the ROM address register. 995 */ 996 if (((PCI_BASE_SPACE_M & prg2.data) == 997 PCI_BASE_SPACE_IO) && 998 (prg2.offset != PCI_CONF_ROM)) { 999 if (pcitool_debug) 1000 prom_printf("IO space\n"); 1001 1002 prg2.data &= PCI_BASE_IO_ADDR_M; 1003 prg.phys_addr = prg2.data + prg.offset; 1004 1005 rval = pcitool_io_access(&prg, write_flag); 1006 if ((rval != SUCCESS) && (pcitool_debug)) 1007 prom_printf("IO access failed\n"); 1008 1009 goto done_reg; 1010 1011 1012 /* 1013 * BAR has bits saying this space is 64 bit memory 1014 * space, unless this is the ROM address register. 1015 * 1016 * The 64 bit address stored in two BAR cells is not 1017 * necessarily aligned on an 8-byte boundary. 1018 * Need to keep the first 4 bytes read, 1019 * and do a separate read of the high 4 bytes. 1020 */ 1021 1022 } else if ((PCI_BASE_TYPE_ALL & prg2.data) && 1023 (prg2.offset != PCI_CONF_ROM)) { 1024 1025 uint32_t low_bytes = 1026 (uint32_t)(prg2.data & ~PCI_BASE_TYPE_ALL); 1027 1028 /* 1029 * Don't try to read the next 4 bytes 1030 * past the end of BARs. 1031 */ 1032 if (prg2.offset >= PCI_CONF_BASE5) { 1033 prg.status = PCITOOL_OUT_OF_RANGE; 1034 rval = EIO; 1035 goto done_reg; 1036 } 1037 1038 /* 1039 * Access device. 1040 * prg2.status is modified on error. 1041 */ 1042 prg2.offset += 4; 1043 rval = pcitool_cfg_access(&prg2, 1044 B_FALSE, B_TRUE); 1045 if (rval != SUCCESS) { 1046 prg.status = prg2.status; 1047 goto done_reg; 1048 } 1049 1050 if (prg2.data == 0xffffffff) { 1051 prg.status = PCITOOL_INVALID_ADDRESS; 1052 prg.status = EFAULT; 1053 goto done_reg; 1054 } 1055 1056 prg2.data = (prg2.data << 32) + low_bytes; 1057 if (pcitool_debug) 1058 prom_printf( 1059 "64 bit mem space. " 1060 "64-bit bar is 0x%" PRIx64 "\n", 1061 prg2.data); 1062 1063 /* Mem32 space, including ROM */ 1064 } else { 1065 1066 if (prg2.offset == PCI_CONF_ROM) { 1067 if (pcitool_debug) 1068 prom_printf( 1069 "Additional ROM " 1070 "checking\n"); 1071 /* Can't write to ROM */ 1072 if (write_flag) { 1073 prg.status = PCITOOL_ROM_WRITE; 1074 rval = EIO; 1075 goto done_reg; 1076 1077 /* ROM disabled for reading */ 1078 } else if (!(prg2.data & 0x00000001)) { 1079 prg.status = 1080 PCITOOL_ROM_DISABLED; 1081 rval = EIO; 1082 goto done_reg; 1083 } 1084 } 1085 1086 if (pcitool_debug) 1087 prom_printf("32 bit mem space\n"); 1088 } 1089 1090 /* Common code for all IO/MEM range spaces. */ 1091 1092 base_addr = prg2.data; 1093 if (pcitool_debug) 1094 prom_printf( 1095 "addr portion of bar is 0x%" PRIx64 ", " 1096 "base=0x%" PRIx64 ", " 1097 "offset:0x%" PRIx64 "\n", 1098 prg2.data, base_addr, prg.offset); 1099 /* 1100 * Use offset provided by caller to index into 1101 * desired space, then access. 1102 * Note that prg.status is modified on error. 1103 */ 1104 prg.phys_addr = base_addr + prg.offset; 1105 1106 virt_addr = pcitool_map(prg.phys_addr, size, 1107 &num_virt_pages); 1108 if (virt_addr == NULL) { 1109 prg.status = PCITOOL_IO_ERROR; 1110 rval = EIO; 1111 goto done_reg; 1112 } 1113 1114 rval = pcitool_mem_access(&prg, virt_addr, write_flag); 1115 pcitool_unmap(virt_addr, num_virt_pages); 1116 } 1117 done_reg: 1118 prg.drvr_version = PCITOOL_VERSION; 1119 if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t), mode) != 1120 DDI_SUCCESS) { 1121 if (pcitool_debug) 1122 prom_printf("Error returning arguments.\n"); 1123 rval = EFAULT; 1124 } 1125 break; 1126 default: 1127 rval = ENOTTY; 1128 break; 1129 } 1130 return (rval); 1131 } 1132