xref: /titanic_52/usr/src/uts/common/sys/pghw.h (revision 0e7515250c8395f368aa45fb9acae7c4f8f8b786)
1fb2f18f8Sesaxe /*
2fb2f18f8Sesaxe  * CDDL HEADER START
3fb2f18f8Sesaxe  *
4fb2f18f8Sesaxe  * The contents of this file are subject to the terms of the
5fb2f18f8Sesaxe  * Common Development and Distribution License (the "License").
6fb2f18f8Sesaxe  * You may not use this file except in compliance with the License.
7fb2f18f8Sesaxe  *
8fb2f18f8Sesaxe  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9fb2f18f8Sesaxe  * or http://www.opensolaris.org/os/licensing.
10fb2f18f8Sesaxe  * See the License for the specific language governing permissions
11fb2f18f8Sesaxe  * and limitations under the License.
12fb2f18f8Sesaxe  *
13fb2f18f8Sesaxe  * When distributing Covered Code, include this CDDL HEADER in each
14fb2f18f8Sesaxe  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15fb2f18f8Sesaxe  * If applicable, add the following below this CDDL HEADER, with the
16fb2f18f8Sesaxe  * fields enclosed by brackets "[]" replaced with your own identifying
17fb2f18f8Sesaxe  * information: Portions Copyright [yyyy] [name of copyright owner]
18fb2f18f8Sesaxe  *
19fb2f18f8Sesaxe  * CDDL HEADER END
20fb2f18f8Sesaxe  */
21fb2f18f8Sesaxe /*
22*0e751525SEric Saxe  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23fb2f18f8Sesaxe  * Use is subject to license terms.
24fb2f18f8Sesaxe  */
25fb2f18f8Sesaxe 
26fb2f18f8Sesaxe #ifndef	_PGHW_H
27fb2f18f8Sesaxe #define	_PGHW_H
28fb2f18f8Sesaxe 
29fb2f18f8Sesaxe #ifdef	__cplusplus
30fb2f18f8Sesaxe extern "C" {
31fb2f18f8Sesaxe #endif
32fb2f18f8Sesaxe 
33fb2f18f8Sesaxe #if (defined(_KERNEL) || defined(_KMEMUSER))
34fb2f18f8Sesaxe #include <sys/cpuvar.h>
35fb2f18f8Sesaxe #include <sys/group.h>
36fb2f18f8Sesaxe #include <sys/processor.h>
37fb2f18f8Sesaxe #include <sys/bitmap.h>
38fb2f18f8Sesaxe #include <sys/atomic.h>
39fb2f18f8Sesaxe #include <sys/types.h>
40fb2f18f8Sesaxe #include <sys/kstat.h>
41fb2f18f8Sesaxe #include <sys/pg.h>
42fb2f18f8Sesaxe 
43fb2f18f8Sesaxe /*
44fb2f18f8Sesaxe  * Hardware that may be shared by a group of processors
45fb2f18f8Sesaxe  */
46fb2f18f8Sesaxe typedef enum pghw_type {
47fb2f18f8Sesaxe 	PGHW_START,
48*0e751525SEric Saxe 	PGHW_IPIPE,	/* Instruction Pipeline */
49*0e751525SEric Saxe 	PGHW_CACHE,	/* Cache (generally last level) */
50*0e751525SEric Saxe 	PGHW_FPU,	/* Floating Point Unit / Pipeline */
51*0e751525SEric Saxe 	PGHW_MPIPE,	/* Pipe to Memory */
52*0e751525SEric Saxe 	PGHW_CHIP,	/* Socket */
53fb2f18f8Sesaxe 	PGHW_MEMORY,
54*0e751525SEric Saxe 	PGHW_POW_ACTIVE,	/* Active Power Management Domain */
55*0e751525SEric Saxe 	PGHW_POW_IDLE,		/* Idle Power Management Domain */
56fb2f18f8Sesaxe 	PGHW_NUM_COMPONENTS
57fb2f18f8Sesaxe } pghw_type_t;
58fb2f18f8Sesaxe 
59fb2f18f8Sesaxe /*
60*0e751525SEric Saxe  * Returns true if the hardware is a type of power management domain
61*0e751525SEric Saxe  */
62*0e751525SEric Saxe #define	PGHW_IS_PM_DOMAIN(hw)	\
63*0e751525SEric Saxe 	(hw == PGHW_POW_ACTIVE || hw == PGHW_POW_IDLE)
64*0e751525SEric Saxe 
65*0e751525SEric Saxe /*
66fb2f18f8Sesaxe  * Anonymous instance id
67fb2f18f8Sesaxe  */
68fb2f18f8Sesaxe #define	PGHW_INSTANCE_ANON ((id_t)0xdecafbad)
69fb2f18f8Sesaxe 
70fb2f18f8Sesaxe /*
71*0e751525SEric Saxe  * Max length of PGHW kstat strings
72*0e751525SEric Saxe  */
73*0e751525SEric Saxe #define	PGHW_KSTAT_STR_LEN_MAX	32
74*0e751525SEric Saxe 
75*0e751525SEric Saxe 
76*0e751525SEric Saxe /*
77*0e751525SEric Saxe  * Platform specific handle
78*0e751525SEric Saxe  */
79*0e751525SEric Saxe typedef uintptr_t pghw_handle_t;
80*0e751525SEric Saxe 
81*0e751525SEric Saxe /*
82fb2f18f8Sesaxe  * Processor Group (physical sharing relationship)
83fb2f18f8Sesaxe  */
84fb2f18f8Sesaxe typedef struct pghw {
85fb2f18f8Sesaxe 	pg_t		pghw_pg;	/* processor group */
86fb2f18f8Sesaxe 	pghw_type_t	pghw_hw;	/* HW sharing relationship */
87fb2f18f8Sesaxe 	id_t		pghw_instance;	/* sharing instance identifier */
88*0e751525SEric Saxe 	pghw_handle_t	pghw_handle;	/* hw specific opaque handle */
89fb2f18f8Sesaxe 	kstat_t		*pghw_kstat;	/* physical kstats exported */
90fb2f18f8Sesaxe } pghw_t;
91fb2f18f8Sesaxe 
92fb2f18f8Sesaxe /*
93fb2f18f8Sesaxe  * IDs associating a CPU with various physical hardware
94fb2f18f8Sesaxe  */
95fb2f18f8Sesaxe typedef struct cpu_physid {
96fb2f18f8Sesaxe 	id_t		cpu_chipid;	/* CPU's physical processor */
97fb2f18f8Sesaxe 	id_t		cpu_coreid;	/* CPU's physical core */
98fb2f18f8Sesaxe 	id_t		cpu_cacheid;	/* CPU's cache id */
99fb2f18f8Sesaxe } cpu_physid_t;
100fb2f18f8Sesaxe 
101fb2f18f8Sesaxe /*
102fb2f18f8Sesaxe  * Physical PG initialization / CPU service hooks
103fb2f18f8Sesaxe  */
104fb2f18f8Sesaxe void		pghw_init(pghw_t *, cpu_t *, pghw_type_t);
105fb2f18f8Sesaxe void		pghw_fini(pghw_t *);
106fb2f18f8Sesaxe void		pghw_cpu_add(pghw_t *, cpu_t *);
107fb2f18f8Sesaxe pghw_t		*pghw_place_cpu(cpu_t *, pghw_type_t);
108fb2f18f8Sesaxe 
109fb2f18f8Sesaxe /*
110fb2f18f8Sesaxe  * Physical ID cache creation / destruction
111fb2f18f8Sesaxe  */
112fb2f18f8Sesaxe void		pghw_physid_create(cpu_t *);
113fb2f18f8Sesaxe void		pghw_physid_destroy(cpu_t *);
114fb2f18f8Sesaxe 
115fb2f18f8Sesaxe /*
116fb2f18f8Sesaxe  * CPU / PG hardware related seach operations
117fb2f18f8Sesaxe  */
118fb2f18f8Sesaxe pghw_t		*pghw_find_pg(cpu_t *, pghw_type_t);
119fb2f18f8Sesaxe pghw_t		*pghw_find_by_instance(id_t, pghw_type_t);
120fb2f18f8Sesaxe group_t		*pghw_set_lookup(pghw_type_t);
121fb2f18f8Sesaxe 
122fb2f18f8Sesaxe void		pghw_kstat_create(pghw_t *);
123fb2f18f8Sesaxe int		pghw_kstat_update(kstat_t *, int);
124fb2f18f8Sesaxe 
125fb2f18f8Sesaxe /* Hardware sharing relationship platform interfaces */
126fb2f18f8Sesaxe int		pg_plat_hw_shared(cpu_t *, pghw_type_t);
127fb2f18f8Sesaxe int		pg_plat_cpus_share(cpu_t *, cpu_t *, pghw_type_t);
128fb2f18f8Sesaxe id_t		pg_plat_hw_instance_id(cpu_t *, pghw_type_t);
129*0e751525SEric Saxe pghw_type_t	pg_plat_hw_rank(pghw_type_t, pghw_type_t);
130fb2f18f8Sesaxe 
131fb2f18f8Sesaxe /*
132fb2f18f8Sesaxe  * What comprises a "core" may vary across processor implementations,
133fb2f18f8Sesaxe  * and so the term itself is somewhat unstable. For this reason, there
134fb2f18f8Sesaxe  * is no PGHW_CORE type, but we provide an interface here to allow platforms
135fb2f18f8Sesaxe  * to express cpu <=> core mappings.
136fb2f18f8Sesaxe  */
137fb2f18f8Sesaxe id_t		pg_plat_get_core_id(cpu_t *);
138fb2f18f8Sesaxe 
139fb2f18f8Sesaxe #endif	/* !_KERNEL && !_KMEMUSER */
140fb2f18f8Sesaxe 
141fb2f18f8Sesaxe #ifdef	__cplusplus
142fb2f18f8Sesaxe }
143fb2f18f8Sesaxe #endif
144fb2f18f8Sesaxe 
145fb2f18f8Sesaxe #endif /* _PGHW_H */
146