1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PCIE_IMPL_H 27 #define _SYS_PCIE_IMPL_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/pcie.h> 36 37 /* PCI-E config space data for error handling and ereport */ 38 typedef struct pf_data { 39 dev_info_t *dip; 40 pcie_req_id_t bdf; 41 pcie_req_id_t rp_bdf; 42 uint32_t severity_flags; 43 int parent_index; 44 pcie_req_id_t fault_bdf; 45 uint32_t fault_addr; 46 int send_erpt; 47 48 /* 0-3Fh. PCI */ 49 uint16_t vendor_id; 50 uint16_t device_id; 51 uint8_t hdr_type; 52 uint16_t command; /* command */ 53 uint16_t status; /* status */ 54 uint8_t rev_id; 55 uint16_t s_status; /* Bridge secondary status */ 56 pcie_req_id_t bdg_secbus; /* Bridge secondary bus num */ 57 58 /* 40h-FFh. PCI-X Capability */ 59 uint16_t pcix_s_status; /* PCI-X Secondary status */ 60 uint32_t pcix_bdg_status; /* PCI-X Bridge status */ 61 62 /* 40h-FFh. PCI-E Capability */ 63 uint16_t pcie_off; /* PCI-E capability offset */ 64 uint8_t dev_type; /* device/port type */ 65 uint16_t dev_status; /* device status */ 66 67 /* 100h-FFFh. Extended PCI-E */ 68 uint16_t aer_off; /* AER offset */ 69 70 uint32_t aer_ce_status; /* AER Correctable Errors */ 71 72 uint32_t aer_ue_status; /* AER Uncorrectable Errors */ 73 uint32_t aer_severity; 74 uint32_t aer_control; 75 uint32_t aer_h0; 76 uint32_t aer_h1; 77 uint32_t aer_h2; 78 uint32_t aer_h3; 79 80 uint32_t s_aer_ue_status; /* Secondary AER UEs */ 81 uint32_t s_aer_control; 82 uint32_t s_aer_severity; 83 uint32_t s_aer_h0; 84 uint32_t s_aer_h1; 85 uint32_t s_aer_h2; 86 uint32_t s_aer_h3; 87 } pf_data_t; 88 89 /* Information used while handling errors in the fabric. */ 90 typedef struct pf_impl { 91 dev_info_t *pf_rpdip; 92 pcie_req_id_t pf_fbdf; /* captured fault bdf to scan */ 93 uint32_t pf_faddr; /* captured fault addr to scan */ 94 ddi_fm_error_t *pf_derr; 95 pf_data_t *pf_dq_p; /* ptr to pcie fault data queue */ 96 int *pf_dq_tail_p; /* last valid index of fault data q */ 97 } pf_impl_t; 98 99 /* Parent Private data of PCI/PCIe devices in a PCIe system */ 100 typedef struct pcie_ppd { 101 dev_info_t *ppd_dip; 102 ddi_acc_handle_t ppd_cfg_hdl; /* error handling acc handle */ 103 kmutex_t ppd_fm_lock; /* error handling lock */ 104 uint_t ppd_fm_flags; 105 106 /* Static PCI/PCIe information */ 107 pcie_req_id_t ppd_bdf; 108 uint32_t ppd_dev_ven_id; /* device/vendor ID */ 109 uint8_t ppd_hdr_type; /* pci header type, see pci.h */ 110 uint8_t ppd_dev_type; /* PCI-E dev type, see pcie.h */ 111 uint8_t ppd_bdg_secbus; /* Bridge secondary bus num */ 112 pcie_req_id_t ppd_pcie2pci_secbus; /* PCIe2PCI Bridge secbus num */ 113 uint16_t ppd_pcie_off; /* PCIe Capability Offset */ 114 uint16_t ppd_aer_off; /* PCIe Advanced Error Offset */ 115 uint16_t ppd_pcix_off; /* PCIx Capability Offset */ 116 pci_bus_range_t ppd_bus_range; /* pci bus-range property */ 117 ppb_ranges_t *ppd_addr_ranges; /* pci range property */ 118 int ppd_addr_entries; /* number of range prop */ 119 pci_regspec_t *ppd_assigned_addr; /* "assigned-address" prop */ 120 int ppd_assigned_entries; /* number of prop entries */ 121 } pcie_ppd_t; 122 123 #define PCI_GET_BDF(dip) \ 124 ((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_bdf 125 #define PCI_GET_BDG_SECBUS(dip) \ 126 ((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_bdg_secbus 127 #define PCI_GET_PCIE2PCI_SECBUS(dip) \ 128 ((pcie_ppd_t *)pcie_get_ppd(dip))->ppd_pcie2pci_secbus 129 130 /* 131 * The following flag is used for Broadcom 5714/5715 bridge prefetch issue. 132 * This flag will be used both by px and px_pci nexus drivers. 133 */ 134 #define PX_DMAI_FLAGS_MAP_BUFZONE 0x40000 135 136 /* ppd_fm_flags field */ 137 #define PF_FM_READY (1 << 0) /* ppd_fm_lock initialized */ 138 #define PF_IS_NH (1 << 1) /* known as non-hardened */ 139 140 /* PCIe fabric error handling return codes */ 141 #define PF_NO_ERROR (1 << 0) /* No error seen */ 142 #define PF_CE (1 << 1) /* Correctable Error */ 143 #define PF_NO_PANIC (1 << 2) /* Error should not panic sys */ 144 #define PF_MATCHED_DEVICE (1 << 3) /* Error Handled By Device */ 145 #define PF_MATCHED_RC (1 << 4) /* Error Handled By RC */ 146 #define PF_MATCHED_PARENT (1 << 5) /* Error Handled By Parent */ 147 #define PF_PANIC (1 << 6) /* Error should panic system */ 148 149 /* PCIe fabric handle lookup return codes */ 150 #define PF_HDL_FOUND 0 151 #define PF_HDL_NOTFOUND 1 152 153 /* PCIe fabric handle lookup address flags */ 154 #define PF_DMA_ADDR (1 << 0) 155 #define PF_PIO_ADDR (1 << 1) 156 #define PF_CFG_ADDR (1 << 2) 157 #define PF_IO_ADDR (1 << 3) 158 159 #define PF_SEND_ERPT_YES 1 160 #define PF_SEND_ERPT_UNKNOWN 0 161 #define PF_SEND_ERPT_NO -1 162 163 #define PF_SUCCESS (1 << 0) 164 #define PF_FAILURE (1 << 1) 165 #define PF_DO_NOT_SCAN (1 << 2) 166 167 /* PCIe helper functions */ 168 extern pcie_ppd_t *pcie_get_ppd(dev_info_t *dip); 169 170 /* PCIe Friendly Functions */ 171 extern int pcie_initchild(dev_info_t *dip); 172 extern void pcie_uninitchild(dev_info_t *dip); 173 extern void pcie_clear_errors(dev_info_t *dip, ddi_acc_handle_t cfg_hdl); 174 extern int pcie_postattach_child(dev_info_t *dip); 175 extern void pcie_enable_errors(dev_info_t *dip, ddi_acc_handle_t cfg_hdl); 176 extern void pcie_disable_errors(dev_info_t *dip, ddi_acc_handle_t cfg_hdl); 177 extern int pcie_enable_ce(dev_info_t *dip, ddi_acc_handle_t cfg_hdl); 178 extern dev_info_t *pcie_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip); 179 extern uint32_t pcie_get_bdf_for_dma_xfer(dev_info_t *dip, dev_info_t *rdip); 180 181 extern pcie_ppd_t *pcie_init_ppd(dev_info_t *cdip); 182 extern void pcie_uninit_ppd(dev_info_t *cdip); 183 extern boolean_t pcie_is_child(dev_info_t *dip, dev_info_t *rdip); 184 extern int pcie_get_bdf_from_dip(dev_info_t *dip, pcie_req_id_t *bdf); 185 186 /* PCIe error handling functions */ 187 extern int pf_en_dq(pf_data_t *pf_data_p, pf_data_t *dq_p, int *dq_tail_p, 188 pcie_req_id_t pbdf); 189 extern int pf_get_dq_size(void); 190 extern int pf_tlp_decode(dev_info_t *rpdip, pf_data_t *pf_data_p, 191 pcie_req_id_t *bdf, uint32_t *addr, uint32_t *trans_type); 192 extern int pf_tlp_hdl_lookup(dev_info_t *rpdip, ddi_fm_error_t *derr, 193 pf_data_t *pf_data_p); 194 extern int pf_hdl_lookup(dev_info_t *rpdip, uint64_t ena, 195 uint32_t flag, uint32_t addr, pcie_req_id_t bdf); 196 extern int pf_scan_fabric(dev_info_t *rpdip, ddi_fm_error_t *derr, 197 pf_data_t *dq_p, int *dq_tail_p); 198 extern void pf_init(dev_info_t *dip, ddi_iblock_cookie_t ibc, 199 ddi_attach_cmd_t cmd); 200 extern void pf_fini(dev_info_t *dip, ddi_detach_cmd_t cmd); 201 extern boolean_t pf_ready(dev_info_t *dip); 202 203 204 #ifdef __cplusplus 205 } 206 #endif 207 208 #endif /* _SYS_PCIE_IMPL_H */ 209