1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_IMPL_H 28 #define _SYS_PCI_IMPL_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/dditypes.h> 33 #include <sys/memlist.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #if defined(__i386) || defined(__amd64) 40 41 /* 42 * There are two ways to access the PCI configuration space on X86 43 * Access method 2 is the older method 44 * Access method 1 is the newer method and is preferred because 45 * of the problems in trying to lock the configuration space 46 * for MP machines using method 2. See PCI Local BUS Specification 47 * Revision 2.0 section 3.6.4.1 for more details. 48 * 49 * In addition, on IBM Sandalfoot and a few related machines there's 50 * still another mechanism. See PReP 1.1 section 6.1.7. 51 */ 52 53 #define PCI_MECHANISM_UNKNOWN -1 54 #define PCI_MECHANISM_NONE 0 55 #if defined(__i386) || defined(__ia64) || defined(__amd64) 56 #define PCI_MECHANISM_1 1 57 #define PCI_MECHANISM_2 2 58 #else 59 #error "Unknown processor type" 60 #endif 61 62 63 #ifndef FALSE 64 #define FALSE 0 65 #endif 66 67 #ifndef TRUE 68 #define TRUE 1 69 #endif 70 71 #define PCI_FUNC_MASK 0x07 72 73 /* these macros apply to Configuration Mechanism #1 */ 74 #define PCI_CONFADD 0xcf8 75 #define PCI_PMC 0xcfb 76 #define PCI_CONFDATA 0xcfc 77 #define PCI_CONE 0x80000000 78 #define PCI_CADDR1(bus, device, function, reg) \ 79 (PCI_CONE | (((bus) & 0xff) << 16) | (((device & 0x1f)) << 11) \ 80 | (((function) & 0x7) << 8) | ((reg) & 0xfc)) 81 82 /* these macros apply to Configuration Mechanism #2 */ 83 #define PCI_CSE_PORT 0xcf8 84 #define PCI_FORW_PORT 0xcfa 85 #define PCI_CADDR2(device, indx) \ 86 (0xc000 | (((device) & 0xf) << 8) | (indx)) 87 88 typedef struct pci_acc_cfblk { 89 uchar_t c_busnum; /* bus number */ 90 uchar_t c_devnum; /* device number */ 91 uchar_t c_funcnum; /* function number */ 92 uchar_t c_fill; /* reserve field */ 93 } pci_acc_cfblk_t; 94 95 struct pci_bus_resource { 96 struct memlist *io_ports; 97 struct memlist *mem_space; 98 struct memlist *pmem_space; 99 dev_info_t *dip; /* devinfo node */ 100 void *privdata; /* private data for configuration */ 101 uchar_t par_bus; /* parent bus number */ 102 uchar_t sub_bus; /* highest bus number beyond this bridge */ 103 uchar_t root_addr; /* legacy peer bus address assignment */ 104 uchar_t padding1; 105 #ifdef _LP64 106 uint32_t padding2; 107 #endif 108 }; 109 110 extern struct pci_bus_resource *pci_bus_res; 111 112 /* 113 * For now, x86-only to avoid conflicts with <sys/memlist_impl.h> 114 */ 115 extern struct memlist *memlist_alloc(void); 116 extern void memlist_free(struct memlist *); 117 extern void memlist_insert(struct memlist **, uint64_t, uint64_t); 118 extern int memlist_remove(struct memlist **, uint64_t, uint64_t); 119 extern uint64_t memlist_find(struct memlist **, uint64_t, int); 120 extern void memlist_dump(struct memlist *); 121 extern struct memlist *memlist_dup(struct memlist *); 122 extern int memlist_count(struct memlist *); 123 124 #endif /* __i386 || __amd64 */ 125 126 /* 127 * PCI capability related definitions. 128 */ 129 130 /* 131 * Minimum number of dwords to be saved. 132 */ 133 #define PCI_MSI_MIN_WORDS 3 134 #define PCI_PCIX_MIN_WORDS 2 135 #define PCI_PCIE_MIN_WORDS 5 136 137 /* 138 * Total number of dwords to be saved. 139 */ 140 #define PCI_PMCAP_NDWORDS 2 141 #define PCI_AGP_NDWORDS 3 142 #define PCI_SLOTID_NDWORDS 1 143 #define PCI_MSIX_NDWORDS 3 144 #define PCI_CAP_SZUNKNOWN 0 145 146 #define CAP_ID(confhdl, cap_ptr, xspace) \ 147 ((xspace) ? 0 : pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_ID)) 148 149 #define NEXT_CAP(confhdl, cap_ptr, xspace) \ 150 ((xspace) ? 0 : \ 151 pci_config_get8((confhdl), (cap_ptr) + PCI_CAP_NEXT_PTR)) 152 153 extern int pci_resource_setup(dev_info_t *); 154 extern void pci_resource_destroy(dev_info_t *); 155 156 #ifdef __cplusplus 157 } 158 #endif 159 160 #endif /* _SYS_PCI_IMPL_H */ 161