1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_TXDMA_H 27 #define _SYS_NXGE_NXGE_TXDMA_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <sys/nxge/nxge_txdma_hw.h> 36 #include <npi_txdma.h> 37 38 #define TXDMA_PORT_BITMAP(nxgep) (nxgep->pt_config.tx_dma_map) 39 40 #define TXDMA_RECLAIM_PENDING_DEFAULT 64 41 #define TX_FULL_MARK 3 42 43 /* 44 * Transmit load balancing definitions. 45 */ 46 #define NXGE_TX_LB_TCPUDP 0 /* default policy */ 47 #define NXGE_TX_LB_HASH 1 /* from the hint data */ 48 #define NXGE_TX_LB_DEST_MAC 2 /* Dest. MAC */ 49 50 /* 51 * Descriptor ring empty: 52 * (1) head index is equal to tail index. 53 * (2) wrapped around bits are the same. 54 * Descriptor ring full: 55 * (1) head index is equal to tail index. 56 * (2) wrapped around bits are different. 57 * 58 */ 59 #define TXDMA_RING_EMPTY(head, head_wrap, tail, tail_wrap) \ 60 ((head == tail && head_wrap == tail_wrap) ? B_TRUE : B_FALSE) 61 62 #define TXDMA_RING_FULL(head, head_wrap, tail, tail_wrap) \ 63 ((head == tail && head_wrap != tail_wrap) ? B_TRUE : B_FALSE) 64 65 #define TXDMA_DESC_NEXT_INDEX(index, entries, wrap_mask) \ 66 ((index + entries) & wrap_mask) 67 68 #define TXDMA_DRR_WEIGHT_DEFAULT 0x001f 69 70 typedef struct _tx_msg_t { 71 nxge_os_block_mv_t flags; /* DMA, BCOPY, DVMA (?) */ 72 nxge_os_dma_common_t buf_dma; /* premapped buffer blocks */ 73 nxge_os_dma_handle_t buf_dma_handle; /* premapped buffer handle */ 74 nxge_os_dma_handle_t dma_handle; /* DMA handle for normal send */ 75 nxge_os_dma_handle_t dvma_handle; /* Fast DVMA handle */ 76 77 p_mblk_t tx_message; 78 uint32_t tx_msg_size; 79 size_t bytes_used; 80 int head; 81 int tail; 82 } tx_msg_t, *p_tx_msg_t; 83 84 /* 85 * TX Statistics. 86 */ 87 typedef struct _nxge_tx_ring_stats_t { 88 uint64_t opackets; 89 uint64_t obytes; 90 uint64_t oerrors; 91 92 uint32_t tx_inits; 93 uint32_t tx_no_buf; 94 95 uint32_t mbox_err; 96 uint32_t pkt_size_err; 97 uint32_t tx_ring_oflow; 98 uint32_t pre_buf_par_err; 99 uint32_t nack_pref; 100 uint32_t nack_pkt_rd; 101 uint32_t conf_part_err; 102 uint32_t pkt_part_err; 103 uint32_t tx_starts; 104 uint32_t tx_nocanput; 105 uint32_t tx_msgdup_fail; 106 uint32_t tx_allocb_fail; 107 uint32_t tx_no_desc; 108 uint32_t tx_dma_bind_fail; 109 uint32_t tx_uflo; 110 111 uint32_t tx_hdr_pkts; 112 uint32_t tx_ddi_pkts; 113 uint32_t tx_dvma_pkts; 114 115 uint32_t tx_max_pend; 116 uint32_t tx_jumbo_pkts; 117 118 txdma_ring_errlog_t errlog; 119 } nxge_tx_ring_stats_t, *p_nxge_tx_ring_stats_t; 120 121 typedef struct _tx_ring_t { 122 nxge_os_dma_common_t tdc_desc; 123 struct _nxge_t *nxgep; 124 p_tx_msg_t tx_msg_ring; 125 uint32_t tnblocks; 126 tx_rng_cfig_t tx_ring_cfig; 127 tx_ring_hdl_t tx_ring_hdl; 128 tx_ring_kick_t tx_ring_kick; 129 tx_cs_t tx_cs; 130 tx_dma_ent_msk_t tx_evmask; 131 txdma_mbh_t tx_mbox_mbh; 132 txdma_mbl_t tx_mbox_mbl; 133 log_page_vld_t page_valid; 134 log_page_mask_t page_mask_1; 135 log_page_mask_t page_mask_2; 136 log_page_value_t page_value_1; 137 log_page_value_t page_value_2; 138 log_page_relo_t page_reloc_1; 139 log_page_relo_t page_reloc_2; 140 log_page_hdl_t page_hdl; 141 txc_dma_max_burst_t max_burst; 142 boolean_t cfg_set; 143 uint32_t tx_ring_state; 144 145 nxge_os_mutex_t lock; 146 uint16_t index; 147 uint16_t tdc; 148 struct nxge_tdc_cfg *tdc_p; 149 uint_t tx_ring_size; 150 uint32_t num_chunks; 151 152 uint_t tx_wrap_mask; 153 uint_t rd_index; 154 uint_t wr_index; 155 boolean_t wr_index_wrap; 156 uint_t head_index; 157 boolean_t head_wrap; 158 tx_ring_hdl_t ring_head; 159 tx_ring_kick_t ring_kick_tail; 160 txdma_mailbox_t tx_mbox; 161 162 uint_t descs_pending; 163 boolean_t queueing; 164 165 nxge_os_mutex_t sq_lock; 166 167 p_mblk_t head; 168 p_mblk_t tail; 169 170 uint16_t ldg_group_id; 171 p_nxge_tx_ring_stats_t tdc_stats; 172 173 nxge_os_mutex_t dvma_lock; 174 uint_t dvma_wr_index; 175 uint_t dvma_rd_index; 176 uint_t dvma_pending; 177 uint_t dvma_available; 178 uint_t dvma_wrap_mask; 179 180 nxge_os_dma_handle_t *dvma_ring; 181 182 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 183 uint64_t hv_tx_buf_base_ioaddr_pp; 184 uint64_t hv_tx_buf_ioaddr_size; 185 uint64_t hv_tx_cntl_base_ioaddr_pp; 186 uint64_t hv_tx_cntl_ioaddr_size; 187 boolean_t hv_set; 188 #endif 189 } tx_ring_t, *p_tx_ring_t; 190 191 192 /* Transmit Mailbox */ 193 typedef struct _tx_mbox_t { 194 nxge_os_mutex_t lock; 195 uint16_t index; 196 struct _nxge_t *nxgep; 197 uint16_t tdc; 198 nxge_os_dma_common_t tx_mbox; 199 txdma_mbl_t tx_mbox_l; 200 txdma_mbh_t tx_mbox_h; 201 } tx_mbox_t, *p_tx_mbox_t; 202 203 typedef struct _tx_rings_t { 204 p_tx_ring_t *rings; 205 boolean_t txdesc_allocated; 206 uint32_t ndmas; 207 nxge_os_dma_common_t tdc_dma; 208 nxge_os_dma_common_t tdc_mbox; 209 } tx_rings_t, *p_tx_rings_t; 210 211 212 #if defined(_KERNEL) || (defined(COSIM) && !defined(IODIAG)) 213 214 typedef struct _tx_buf_rings_t { 215 struct _tx_buf_ring_t *txbuf_rings; 216 boolean_t txbuf_allocated; 217 } tx_buf_rings_t, *p_tx_buf_rings_t; 218 219 #endif 220 221 typedef struct _tx_mbox_areas_t { 222 p_tx_mbox_t *txmbox_areas_p; 223 boolean_t txmbox_allocated; 224 } tx_mbox_areas_t, *p_tx_mbox_areas_t; 225 226 typedef struct _tx_param_t { 227 nxge_logical_page_t tx_logical_pages[NXGE_MAX_LOGICAL_PAGES]; 228 } tx_param_t, *p_tx_param_t; 229 230 typedef struct _tx_params { 231 struct _tx_param_t *tx_param_p; 232 } tx_params_t, *p_tx_params_t; 233 234 /* 235 * Global register definitions per chip and they are initialized 236 * using the function zero control registers. 237 * . 238 */ 239 typedef struct _txdma_globals { 240 boolean_t mode32; 241 } txdma_globals_t, *p_txdma_globals; 242 243 244 #if defined(SOLARIS) && (defined(_KERNEL) || \ 245 (defined(COSIM) && !defined(IODIAG))) 246 247 /* 248 * Transmit prototypes. 249 */ 250 nxge_status_t nxge_init_txdma_channels(p_nxge_t); 251 void nxge_uninit_txdma_channels(p_nxge_t); 252 void nxge_setup_dma_common(p_nxge_dma_common_t, p_nxge_dma_common_t, 253 uint32_t, uint32_t); 254 nxge_status_t nxge_reset_txdma_channel(p_nxge_t, uint16_t, 255 uint64_t); 256 nxge_status_t nxge_init_txdma_channel_event_mask(p_nxge_t, 257 uint16_t, p_tx_dma_ent_msk_t); 258 nxge_status_t nxge_init_txdma_channel_cntl_stat(p_nxge_t, 259 uint16_t, uint64_t); 260 nxge_status_t nxge_enable_txdma_channel(p_nxge_t, uint16_t, 261 p_tx_ring_t, p_tx_mbox_t); 262 263 p_mblk_t nxge_tx_pkt_header_reserve(p_mblk_t, uint8_t *); 264 int nxge_tx_pkt_nmblocks(p_mblk_t, int *); 265 boolean_t nxge_txdma_reclaim(p_nxge_t, p_tx_ring_t, int); 266 267 void nxge_fill_tx_hdr(p_mblk_t, boolean_t, boolean_t, 268 int, uint8_t, p_tx_pkt_hdr_all_t); 269 270 nxge_status_t nxge_txdma_hw_mode(p_nxge_t, boolean_t); 271 void nxge_hw_start_tx(p_nxge_t); 272 void nxge_txdma_stop(p_nxge_t); 273 void nxge_txdma_stop_start(p_nxge_t); 274 void nxge_fixup_txdma_rings(p_nxge_t); 275 void nxge_txdma_hw_kick(p_nxge_t); 276 void nxge_txdma_fix_channel(p_nxge_t, uint16_t); 277 void nxge_txdma_fixup_channel(p_nxge_t, p_tx_ring_t, 278 uint16_t); 279 void nxge_txdma_hw_kick_channel(p_nxge_t, p_tx_ring_t, 280 uint16_t); 281 282 void nxge_txdma_regs_dump(p_nxge_t, int); 283 void nxge_txdma_regs_dump_channels(p_nxge_t); 284 285 void nxge_check_tx_hang(p_nxge_t); 286 void nxge_fixup_hung_txdma_rings(p_nxge_t); 287 void nxge_txdma_fix_hung_channel(p_nxge_t, uint16_t); 288 void nxge_txdma_fixup_hung_channel(p_nxge_t, p_tx_ring_t, 289 uint16_t); 290 291 void nxge_reclaim_rings(p_nxge_t); 292 int nxge_txdma_channel_hung(p_nxge_t, 293 p_tx_ring_t tx_ring_p, uint16_t); 294 int nxge_txdma_hung(p_nxge_t); 295 int nxge_txdma_stop_inj_err(p_nxge_t, int); 296 void nxge_txdma_inject_err(p_nxge_t, uint32_t, uint8_t); 297 298 #endif 299 300 #ifdef __cplusplus 301 } 302 #endif 303 304 #endif /* _SYS_NXGE_NXGE_TXDMA_H */ 305