1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_MII_H_ 27 #define _SYS_NXGE_NXGE_MII_H_ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Configuration Register space. 37 */ 38 39 #define MII_BMCR 0 40 #define MII_BMSR 1 41 #define MII_IDR1 2 42 #define MII_IDR2 3 43 #define MII_ANAR 4 44 #define MII_ANLPAR 5 45 #define MII_ANER 6 46 #define MII_NPTXR 7 47 #define MII_LPRXNPR 8 48 #define MII_GCR 9 49 #define MII_GSR 10 50 #define MII_RES0 11 51 #define MII_RES1 12 52 #define MII_RES2 13 53 #define MII_RES3 14 54 #define MII_ESR 15 55 56 #define NXGE_MAX_MII_REGS 32 57 58 /* 59 * Configuration Register space. 60 */ 61 typedef struct _mii_regs { 62 uchar_t bmcr; /* Basic mode control register */ 63 uchar_t bmsr; /* Basic mode status register */ 64 uchar_t idr1; /* Phy identifier register 1 */ 65 uchar_t idr2; /* Phy identifier register 2 */ 66 uchar_t anar; /* Auto-Negotiation advertisement register */ 67 uchar_t anlpar; /* Auto-Negotiation link Partner ability reg */ 68 uchar_t aner; /* Auto-Negotiation expansion register */ 69 uchar_t nptxr; /* Next page transmit register */ 70 uchar_t lprxnpr; /* Link partner received next page register */ 71 uchar_t gcr; /* Gigabit basic mode control register. */ 72 uchar_t gsr; /* Gigabit basic mode status register */ 73 uchar_t mii_res1[4]; /* For future use by MII working group */ 74 uchar_t esr; /* Extended status register. */ 75 uchar_t vendor_res[16]; /* For future use by Phy Vendors */ 76 } mii_regs_t, *p_mii_regs_t; 77 78 /* 79 * MII Register 0: Basic mode control register. 80 */ 81 #define BMCR_RES 0x003f /* Unused... */ 82 #define BMCR_SSEL_MSB 0x0040 /* Used to manually select speed */ 83 /* (with * bit 6) when auto-neg */ 84 /* disabled */ 85 #define BMCR_COL_TEST 0x0080 /* Collision test */ 86 #define BMCR_DPLX_MD 0x0100 /* Full duplex */ 87 #define BMCR_RESTART_AN 0x0200 /* Auto negotiation restart */ 88 #define BMCR_ISOLATE 0x0400 /* Disconnect BCM5464R from MII */ 89 #define BMCR_PDOWN 0x0800 /* Powerdown the BCM5464R */ 90 #define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ 91 #define BMCR_SSEL_LSB 0x2000 /* Used to manually select speed */ 92 /* (with bit 13) when auto-neg */ 93 /* disabled */ 94 #define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ 95 #define BMCR_RESET 0x8000 /* Reset the BCM5464R */ 96 97 typedef union _mii_bmcr { 98 uint16_t value; 99 struct { 100 #if defined(_BIT_FIELDS_HTOL) 101 uint16_t reset:1; 102 uint16_t loopback:1; 103 uint16_t speed_sel:1; 104 uint16_t enable_autoneg:1; 105 uint16_t power_down:1; 106 uint16_t isolate:1; 107 uint16_t restart_autoneg:1; 108 uint16_t duplex_mode:1; 109 uint16_t col_test:1; 110 uint16_t speed_1000_sel:1; 111 uint16_t res1:6; 112 #elif defined(_BIT_FIELDS_LTOH) 113 uint16_t res1:6; 114 uint16_t speed_1000_sel:1; 115 uint16_t col_test:1; 116 uint16_t duplex_mode:1; 117 uint16_t restart_autoneg:1; 118 uint16_t isolate:1; 119 uint16_t power_down:1; 120 uint16_t enable_autoneg:1; 121 uint16_t speed_sel:1; 122 uint16_t loopback:1; 123 uint16_t reset:1; 124 #endif 125 } bits; 126 } mii_bmcr_t, *p_mii_bmcr_t; 127 128 /* 129 * MII Register 1: Basic mode status register. 130 */ 131 #define BMSR_ERCAP 0x0001 /* Ext-reg capability */ 132 #define BMSR_JCD 0x0002 /* Jabber detected */ 133 #define BMSR_LSTATUS 0x0004 /* Link status */ 134 #define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ 135 #define BMSR_RFAULT 0x0010 /* Remote fault detected */ 136 #define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ 137 #define BMSR_MF_PRE_SUP 0x0040 /* Preamble for MIF frame suppressed, */ 138 /* always 1 for BCM5464R */ 139 #define BMSR_RESV 0x0080 /* Unused... */ 140 #define BMSR_ESTAT 0x0100 /* Contains IEEE extended status reg */ 141 #define BMSR_100BASE2HALF 0x0200 /* Can do 100mbps, 2k pkts half-dplx */ 142 #define BMSR_100BASE2FULL 0x0400 /* Can do 100mbps, 2k pkts full-dplx */ 143 #define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ 144 #define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ 145 #define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ 146 #define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ 147 #define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ 148 149 typedef union _mii_bmsr { 150 uint16_t value; 151 struct { 152 #if defined(_BIT_FIELDS_HTOL) 153 uint16_t link_100T4:1; 154 uint16_t link_100fdx:1; 155 uint16_t link_100hdx:1; 156 uint16_t link_10fdx:1; 157 uint16_t link_10hdx:1; 158 uint16_t res2:2; 159 uint16_t extend_status:1; 160 uint16_t res1:1; 161 uint16_t preamble_supress:1; 162 uint16_t auto_neg_complete:1; 163 uint16_t remote_fault:1; 164 uint16_t auto_neg_able:1; 165 uint16_t link_status:1; 166 uint16_t jabber_detect:1; 167 uint16_t ext_cap:1; 168 #elif defined(_BIT_FIELDS_LTOH) 169 int16_t ext_cap:1; 170 uint16_t jabber_detect:1; 171 uint16_t link_status:1; 172 uint16_t auto_neg_able:1; 173 uint16_t remote_fault:1; 174 uint16_t auto_neg_complete:1; 175 uint16_t preamble_supress:1; 176 uint16_t res1:1; 177 uint16_t extend_status:1; 178 uint16_t res2:2; 179 uint16_t link_10hdx:1; 180 uint16_t link_10fdx:1; 181 uint16_t link_100hdx:1; 182 uint16_t link_100fdx:1; 183 uint16_t link_100T4:1; 184 #endif 185 } bits; 186 } mii_bmsr_t, *p_mii_bmsr_t; 187 188 /* 189 * MII Register 2: Physical Identifier 1. 190 */ 191 /* contains BCM OUI bits [3:18] */ 192 typedef union _mii_idr1 { 193 uint16_t value; 194 struct { 195 uint16_t ieee_address:16; 196 } bits; 197 } mii_idr1_t, *p_mii_idr1_t; 198 199 /* 200 * MII Register 3: Physical Identifier 2. 201 */ 202 typedef union _mii_idr2 { 203 uint16_t value; 204 struct { 205 #if defined(_BIT_FIELDS_HTOL) 206 uint16_t ieee_address:6; 207 uint16_t model_no:6; 208 uint16_t rev_no:4; 209 #elif defined(_BIT_FIELDS_LTOH) 210 uint16_t rev_no:4; 211 uint16_t model_no:6; 212 uint16_t ieee_address:6; 213 #endif 214 } bits; 215 } mii_idr2_t, *p_mii_idr2_t; 216 217 /* 218 * MII Register 4: Auto-negotiation advertisement register. 219 */ 220 #define ADVERTISE_SLCT 0x001f /* Selector bits for proto, 0x01 */ 221 /* indicates IEEE 802.3 CSMA/CD phy */ 222 #define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 223 #define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 224 #define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 225 #define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 226 #define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 227 #define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets. set to */ 228 /* 0, BCM5464R not 100BASE-T4 capable */ 229 #define ADVERTISE_RES1 0x0400 /* Unused... */ 230 #define ADVERTISE_ASM_PAUS 0x0800 /* advertise asymmetric pause */ 231 #define ADVERTISE_PAUS 0x1000 /* can do full dplx pause */ 232 #define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ 233 #define ADVERTISE_RES0 0x4000 /* Unused... */ 234 #define ADVERTISE_NPAGE 0x8000 /* Next page bit */ 235 236 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ 237 ADVERTISE_CSMA) 238 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ 239 ADVERTISE_100HALF | ADVERTISE_100FULL) 240 241 typedef union _mii_anar { 242 uint16_t value; 243 struct { 244 #if defined(_BIT_FIELDS_HTOL) 245 uint16_t np_indication:1; 246 uint16_t acknowledge:1; 247 uint16_t remote_fault:1; 248 uint16_t res1:1; 249 uint16_t cap_asmpause:1; 250 uint16_t cap_pause:1; 251 uint16_t cap_100T4:1; 252 uint16_t cap_100fdx:1; 253 uint16_t cap_100hdx:1; 254 uint16_t cap_10fdx:1; 255 uint16_t cap_10hdx:1; 256 uint16_t selector:5; 257 #elif defined(_BIT_FIELDS_LTOH) 258 uint16_t selector:5; 259 uint16_t cap_10hdx:1; 260 uint16_t cap_10fdx:1; 261 uint16_t cap_100hdx:1; 262 uint16_t cap_100fdx:1; 263 uint16_t cap_100T4:1; 264 uint16_t cap_pause:1; 265 uint16_t cap_asmpause:1; 266 uint16_t res1:1; 267 uint16_t remote_fault:1; 268 uint16_t acknowledge:1; 269 uint16_t np_indication:1; 270 #endif 271 } bits; 272 } mii_anar_t, *p_mii_anar_t; 273 274 /* 275 * MII Register 5: Auto-negotiation link partner ability register. 276 */ 277 #define LPA_SLCT 0x001f /* Same as advertise selector */ 278 #define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 279 #define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 280 #define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 281 #define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 282 #define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 283 #define LPA_RES1 0x0400 /* Unused... */ 284 #define LPA_ASM_PAUS 0x0800 /* advertise asymmetric pause */ 285 #define LPA__PAUS 0x1000 /* can do full dplx pause */ 286 #define LPA_RFAULT 0x2000 /* Link partner faulted */ 287 #define LPA_LPACK 0x4000 /* Link partner acked us */ 288 #define LPA_NPAGE 0x8000 /* Next page bit */ 289 290 #define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) 291 #define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) 292 293 typedef mii_anar_t mii_anlpar_t, *pmii_anlpar_t; 294 295 /* 296 * MII Register 6: Auto-negotiation expansion register. 297 */ 298 #define EXPANSION_LP_AN_ABLE 0x0001 /* Link partner has auto-neg cap */ 299 #define EXPANSION_PG_RX 0x0002 /* Got new RX page code word */ 300 #define EXPANSION_NP_ABLE 0x0004 /* This enables npage words */ 301 #define EXPANSION_LPNP_ABLE 0x0008 /* Link partner supports npage */ 302 #define EXPANSION_MFAULTS 0x0010 /* Multiple link faults detected */ 303 #define EXPANSION_RESV 0xffe0 /* Unused... */ 304 305 typedef union _mii_aner { 306 uint16_t value; 307 struct { 308 #if defined(_BIT_FIELDS_HTOL) 309 uint16_t res:11; 310 uint16_t mlf:1; 311 uint16_t lp_np_able:1; 312 uint16_t np_able:1; 313 uint16_t page_rx:1; 314 uint16_t lp_an_able:1; 315 #else 316 uint16_t lp_an_able:1; 317 uint16_t page_rx:1; 318 uint16_t np_able:1; 319 uint16_t lp_np_able:1; 320 uint16_t mlf:1; 321 uint16_t res:11; 322 #endif 323 } bits; 324 } mii_aner_t, *p_mii_aner_t; 325 326 /* 327 * MII Register 7: Next page transmit register. 328 */ 329 typedef union _mii_nptxr { 330 uint16_t value; 331 struct { 332 #if defined(_BIT_FIELDS_HTOL) 333 uint16_t np:1; 334 uint16_t res:1; 335 uint16_t msgp:1; 336 uint16_t ack2:1; 337 uint16_t toggle:1; 338 uint16_t res1:11; 339 #else 340 uint16_t res1:11; 341 uint16_t toggle:1; 342 uint16_t ack2:1; 343 uint16_t msgp:1; 344 uint16_t res:1; 345 uint16_t np:1; 346 #endif 347 } bits; 348 } mii_nptxr_t, *p_mii_nptxr_t; 349 350 /* 351 * MII Register 8: Link partner received next page register. 352 */ 353 typedef union _mii_lprxnpr { 354 uint16_t value; 355 struct { 356 #if defined(_BIT_FIELDS_HTOL) 357 uint16_t np:1; 358 uint16_t ack:1; 359 uint16_t msgp:1; 360 uint16_t ack2:1; 361 uint16_t toggle:1; 362 uint16_t mcf:11; 363 #else 364 uint16_t mcf:11; 365 uint16_t toggle:1; 366 uint16_t ack2:1; 367 uint16_t msgp:1; 368 uint16_t ack:1; 369 uint16_t np:1; 370 #endif 371 } bits; 372 } mii_lprxnpr_t, *p_mii_lprxnpr_t; 373 374 /* 375 * MII Register 9: 1000BaseT control register. 376 */ 377 typedef union _mii_gcr { 378 uint16_t value; 379 struct { 380 #if defined(_BIT_FIELDS_HTOL) 381 uint16_t test_mode:3; 382 uint16_t ms_mode_en:1; 383 uint16_t master:1; 384 uint16_t dte_or_repeater:1; 385 uint16_t link_1000fdx:1; 386 uint16_t link_1000hdx:1; 387 uint16_t res:8; 388 #else 389 uint16_t res:8; 390 uint16_t link_1000hdx:1; 391 uint16_t link_1000fdx:1; 392 uint16_t dte_or_repeater:1; 393 uint16_t master:1; 394 uint16_t ms_mode_en:1; 395 uint16_t test_mode:3; 396 #endif 397 } bits; 398 } mii_gcr_t, *p_mii_gcr_t; 399 400 /* 401 * MII Register 10: 1000BaseT status register. 402 */ 403 typedef union _mii_gsr { 404 uint16_t value; 405 struct { 406 #if defined(_BIT_FIELDS_HTOL) 407 uint16_t ms_config_fault:1; 408 uint16_t ms_resolve:1; 409 uint16_t local_rx_status:1; 410 uint16_t remote_rx_status:1; 411 uint16_t link_1000fdx:1; 412 uint16_t link_1000hdx:1; 413 uint16_t res:2; 414 uint16_t idle_err_cnt:8; 415 #else 416 uint16_t idle_err_cnt:8; 417 uint16_t res:2; 418 uint16_t link_1000hdx:1; 419 uint16_t link_1000fdx:1; 420 uint16_t remote_rx_status:1; 421 uint16_t local_rx_status:1; 422 uint16_t ms_resolve:1; 423 uint16_t ms_config_fault:1; 424 #endif 425 } bits; 426 } mii_gsr_t, *p_mii_gsr_t; 427 428 /* 429 * MII Register 15: Extended status register. 430 */ 431 typedef union _mii_esr { 432 uint16_t value; 433 struct { 434 #if defined(_BIT_FIELDS_HTOL) 435 uint16_t link_1000Xfdx:1; 436 uint16_t link_1000Xhdx:1; 437 uint16_t link_1000fdx:1; 438 uint16_t link_1000hdx:1; 439 uint16_t res:12; 440 #else 441 uint16_t res:12; 442 uint16_t link_1000hdx:1; 443 uint16_t link_1000fdx:1; 444 uint16_t link_1000Xhdx:1; 445 uint16_t link_1000Xfdx:1; 446 #endif 447 } bits; 448 } mii_esr_t, *p_mii_esr_t; 449 450 #ifdef __cplusplus 451 } 452 #endif 453 454 #endif /* _SYS_NXGE_NXGE_MII_H_ */ 455