1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #if defined(_KERNEL) || defined(COSIM) 36 #include <nxge_mac.h> 37 #include <nxge_ipp.h> 38 #include <nxge_fflp.h> 39 #endif 40 41 /* 42 * NXGE diagnostics IOCTLS. 43 */ 44 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 45 46 #define NXGE_GET64 (NXGE_IOC|1) 47 #define NXGE_PUT64 (NXGE_IOC|2) 48 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 49 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 50 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 51 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 52 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 53 #define NXGE_RESET_MAC (NXGE_IOC|8) 54 55 #define NXGE_GET_MII (NXGE_IOC|11) 56 #define NXGE_PUT_MII (NXGE_IOC|12) 57 #define NXGE_RTRACE (NXGE_IOC|13) 58 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 59 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 60 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 61 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 62 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 63 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 64 #define NXGE_RDUMP (NXGE_IOC|26) 65 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 66 #define NXGE_PIO_TEST (NXGE_IOC|28) 67 68 #define NXGE_GET_TCAM (NXGE_IOC|29) 69 #define NXGE_PUT_TCAM (NXGE_IOC|30) 70 #define NXGE_INJECT_ERR (NXGE_IOC|40) 71 72 #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM) 73 #define NXGE_OK 0 74 #define NXGE_ERROR 0x40000000 75 #define NXGE_DDI_FAILED 0x20000000 76 #define NXGE_GET_PORT_NUM(n) n 77 78 /* 79 * Definitions for module_info. 80 */ 81 #define NXGE_IDNUM (0) /* module ID number */ 82 #define NXGE_DRIVER_NAME "nxge" /* module name */ 83 84 #define NXGE_MINPSZ (0) /* min packet size */ 85 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 86 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 87 #define NXGE_LOWAT (1) /* lo-water mark */ 88 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 89 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 90 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 91 #define NXGE_LOWAT_MIN (1) 92 93 #ifndef D_HOTPLUG 94 #define D_HOTPLUG 0x00 95 #endif 96 97 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 98 99 #define NXGE_CHECK_TIMER (5000) 100 101 typedef enum { 102 param_instance, 103 param_main_instance, 104 param_function_number, 105 param_partition_id, 106 param_read_write_mode, 107 param_fw_version, 108 param_port_mode, 109 param_niu_cfg_type, 110 param_tx_quick_cfg, 111 param_rx_quick_cfg, 112 param_master_cfg_enable, 113 param_master_cfg_value, 114 115 param_autoneg, 116 param_anar_10gfdx, 117 param_anar_10ghdx, 118 param_anar_1000fdx, 119 param_anar_1000hdx, 120 param_anar_100T4, 121 param_anar_100fdx, 122 param_anar_100hdx, 123 param_anar_10fdx, 124 param_anar_10hdx, 125 126 param_anar_asmpause, 127 param_anar_pause, 128 param_use_int_xcvr, 129 param_enable_ipg0, 130 param_ipg0, 131 param_ipg1, 132 param_ipg2, 133 param_accept_jumbo, 134 param_txdma_weight, 135 param_txdma_channels_begin, 136 137 param_txdma_channels, 138 param_txdma_info, 139 param_rxdma_channels_begin, 140 param_rxdma_channels, 141 param_rxdma_drr_weight, 142 param_rxdma_full_header, 143 param_rxdma_info, 144 param_rxdma_rbr_size, 145 param_rxdma_rcr_size, 146 param_default_port_rdc, 147 param_rxdma_intr_time, 148 param_rxdma_intr_pkts, 149 150 param_rdc_grps_start, 151 param_rx_rdc_grps, 152 param_default_grp0_rdc, 153 param_default_grp1_rdc, 154 param_default_grp2_rdc, 155 param_default_grp3_rdc, 156 param_default_grp4_rdc, 157 param_default_grp5_rdc, 158 param_default_grp6_rdc, 159 param_default_grp7_rdc, 160 161 param_info_rdc_groups, 162 param_start_ldg, 163 param_max_ldg, 164 param_mac_2rdc_grp, 165 param_vlan_2rdc_grp, 166 param_fcram_part_cfg, 167 param_fcram_access_ratio, 168 param_tcam_access_ratio, 169 param_tcam_enable, 170 param_hash_lookup_enable, 171 param_llc_snap_enable, 172 173 param_h1_init_value, 174 param_h2_init_value, 175 param_class_cfg_ether_usr1, 176 param_class_cfg_ether_usr2, 177 param_class_cfg_ip_usr4, 178 param_class_cfg_ip_usr5, 179 param_class_cfg_ip_usr6, 180 param_class_cfg_ip_usr7, 181 param_class_opt_ip_usr4, 182 param_class_opt_ip_usr5, 183 param_class_opt_ip_usr6, 184 param_class_opt_ip_usr7, 185 param_class_opt_ipv4_tcp, 186 param_class_opt_ipv4_udp, 187 param_class_opt_ipv4_ah, 188 param_class_opt_ipv4_sctp, 189 param_class_opt_ipv6_tcp, 190 param_class_opt_ipv6_udp, 191 param_class_opt_ipv6_ah, 192 param_class_opt_ipv6_sctp, 193 param_nxge_debug_flag, 194 param_npi_debug_flag, 195 param_dump_rdc, 196 param_dump_tdc, 197 param_dump_mac_regs, 198 param_dump_ipp_regs, 199 param_dump_fflp_regs, 200 param_dump_vlan_table, 201 param_dump_rdc_table, 202 param_dump_ptrs, 203 param_end 204 } nxge_param_index_t; 205 206 typedef enum { 207 SOLARIS_DOMAIN, 208 SOLARIS_SERVICE_DOMAIN, 209 SOLARIS_GUEST_DOMAIN, 210 LINUX_SERVICE_DOMAIN, 211 LINUX_GUEST_DOMAIN 212 } nxge_environs_t; 213 214 /* 215 * Named Dispatch Parameter Management Structure 216 */ 217 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 218 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 219 MBLKP, char *, caddr_t, cred_t *); 220 221 #define NXGE_PARAM_READ 0x00000001ULL 222 #define NXGE_PARAM_WRITE 0x00000002ULL 223 #define NXGE_PARAM_SHARED 0x00000004ULL 224 #define NXGE_PARAM_PRIV 0x00000008ULL 225 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 226 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 227 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 228 229 #define NXGE_PARAM_RXDMA 0x00000010ULL 230 #define NXGE_PARAM_TXDMA 0x00000020ULL 231 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 232 #define NXGE_PARAM_MAC 0x00000080ULL 233 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 234 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 235 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 236 237 #define NXGE_PARAM_CMPLX 0x00010000ULL 238 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 239 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 240 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 241 242 #define NXGE_PARAM_READ_PROP 0x00100000ULL 243 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 244 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 245 #define NXGE_PARAM_PROP_STR 0x00800000ULL 246 247 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 248 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 249 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 250 #define NXGE_PARAM_BASE_STR 0x40000000ULL 251 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 252 253 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 254 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 255 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 256 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 257 258 typedef struct _nxge_param_t { 259 int (*getf)(); 260 int (*setf)(); /* null for read only */ 261 uint64_t type; /* R/W/ Common/Port/ .... */ 262 uint64_t minimum; 263 uint64_t maximum; 264 uint64_t value; /* for array params, pointer to value array */ 265 uint64_t old_value; /* for array params, pointer to old_value array */ 266 char *fcode_name; 267 char *name; 268 } nxge_param_t, *p_nxge_param_t; 269 270 271 /* 272 * Do not change the order of the elements of this enum as that will 273 * break the driver code. 274 */ 275 typedef enum { 276 nxge_lb_normal, 277 nxge_lb_ext10g, 278 nxge_lb_ext1000, 279 nxge_lb_ext100, 280 nxge_lb_ext10, 281 nxge_lb_phy10g, 282 nxge_lb_phy1000, 283 nxge_lb_phy, 284 nxge_lb_serdes10g, 285 nxge_lb_serdes1000, 286 nxge_lb_serdes, 287 nxge_lb_mac10g, 288 nxge_lb_mac1000, 289 nxge_lb_mac 290 } nxge_lb_t; 291 292 enum nxge_mac_state { 293 NXGE_MAC_STOPPED = 0, 294 NXGE_MAC_STARTED, 295 NXGE_MAC_STOPPING 296 }; 297 298 /* 299 * Private DLPI full dlsap address format. 300 */ 301 typedef struct _nxge_dladdr_t { 302 ether_addr_st dl_phys; 303 uint16_t dl_sap; 304 } nxge_dladdr_t, *p_nxge_dladdr_t; 305 306 typedef struct _mc_addr_t { 307 ether_addr_st multcast_addr; 308 uint_t mc_addr_cnt; 309 } mc_addr_t, *p_mc_addr_t; 310 311 typedef struct _mc_bucket_t { 312 p_mc_addr_t addr_list; 313 uint_t list_size; 314 } mc_bucket_t, *p_mc_bucket_t; 315 316 typedef struct _mc_table_t { 317 p_mc_bucket_t bucket_list; 318 uint_t buckets_used; 319 } mc_table_t, *p_mc_table_t; 320 321 typedef struct _filter_t { 322 uint32_t all_phys_cnt; 323 uint32_t all_multicast_cnt; 324 uint32_t all_sap_cnt; 325 } filter_t, *p_filter_t; 326 327 #if defined(_KERNEL) || defined(COSIM) 328 329 330 typedef struct _nxge_port_stats_t { 331 /* 332 * Overall structure size 333 */ 334 size_t stats_size; 335 336 /* 337 * Link Input/Output stats 338 */ 339 uint64_t ipackets; 340 uint64_t ierrors; 341 uint64_t opackets; 342 uint64_t oerrors; 343 uint64_t collisions; 344 345 /* 346 * MIB II variables 347 */ 348 uint64_t rbytes; /* # bytes received */ 349 uint64_t obytes; /* # bytes transmitted */ 350 uint32_t multircv; /* # multicast packets received */ 351 uint32_t multixmt; /* # multicast packets for xmit */ 352 uint32_t brdcstrcv; /* # broadcast packets received */ 353 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 354 uint32_t norcvbuf; /* # rcv packets discarded */ 355 uint32_t noxmtbuf; /* # xmit packets discarded */ 356 357 /* 358 * Lets the user know the MTU currently in use by 359 * the physical MAC port. 360 */ 361 nxge_lb_t lb_mode; 362 uint32_t qos_mode; 363 uint32_t trunk_mode; 364 uint32_t poll_mode; 365 366 /* 367 * Tx Statistics. 368 */ 369 uint32_t tx_inits; 370 uint32_t tx_starts; 371 uint32_t tx_nocanput; 372 uint32_t tx_msgdup_fail; 373 uint32_t tx_allocb_fail; 374 uint32_t tx_no_desc; 375 uint32_t tx_dma_bind_fail; 376 uint32_t tx_uflo; 377 uint32_t tx_hdr_pkts; 378 uint32_t tx_ddi_pkts; 379 uint32_t tx_dvma_pkts; 380 381 uint32_t tx_max_pend; 382 383 /* 384 * Rx Statistics. 385 */ 386 uint32_t rx_inits; 387 uint32_t rx_hdr_pkts; 388 uint32_t rx_mtu_pkts; 389 uint32_t rx_split_pkts; 390 uint32_t rx_no_buf; 391 uint32_t rx_no_comp_wb; 392 uint32_t rx_ov_flow; 393 uint32_t rx_len_mm; 394 uint32_t rx_tag_err; 395 uint32_t rx_nocanput; 396 uint32_t rx_msgdup_fail; 397 uint32_t rx_allocb_fail; 398 399 /* 400 * Receive buffer management statistics. 401 */ 402 uint32_t rx_new_pages; 403 uint32_t rx_new_hdr_pgs; 404 uint32_t rx_new_mtu_pgs; 405 uint32_t rx_new_nxt_pgs; 406 uint32_t rx_reused_pgs; 407 uint32_t rx_hdr_drops; 408 uint32_t rx_mtu_drops; 409 uint32_t rx_nxt_drops; 410 411 /* 412 * Receive flow statistics 413 */ 414 uint32_t rx_rel_flow; 415 uint32_t rx_rel_bit; 416 417 uint32_t rx_pkts_dropped; 418 419 /* 420 * PCI-E Bus Statistics. 421 */ 422 uint32_t pci_bus_speed; 423 uint32_t pci_err; 424 uint32_t pci_rta_err; 425 uint32_t pci_rma_err; 426 uint32_t pci_parity_err; 427 uint32_t pci_bad_ack_err; 428 uint32_t pci_drto_err; 429 uint32_t pci_dmawz_err; 430 uint32_t pci_dmarz_err; 431 432 uint32_t rx_taskq_waits; 433 434 uint32_t tx_jumbo_pkts; 435 436 /* 437 * Some statistics added to support bringup, these 438 * should be removed. 439 */ 440 uint32_t user_defined; 441 } nxge_port_stats_t, *p_nxge_port_stats_t; 442 443 444 typedef struct _nxge_stats_t { 445 /* 446 * Overall structure size 447 */ 448 size_t stats_size; 449 450 kstat_t *ksp; 451 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 452 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 453 kstat_t *rdc_sys_ksp; 454 kstat_t *fflp_ksp[1]; 455 kstat_t *ipp_ksp; 456 kstat_t *txc_ksp; 457 kstat_t *mac_ksp; 458 kstat_t *zcp_ksp; 459 kstat_t *port_ksp; 460 kstat_t *mmac_ksp; 461 462 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 463 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 464 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 465 466 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 467 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 468 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 469 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 470 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 471 472 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 473 nxge_txc_stats_t txc_stats; /* per port TX stats */ 474 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 475 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 476 nxge_port_stats_t port_stats; /* fflp stats */ 477 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 478 479 } nxge_stats_t, *p_nxge_stats_t; 480 481 482 483 typedef struct _nxge_intr_t { 484 boolean_t intr_registered; /* interrupts are registered */ 485 boolean_t intr_enabled; /* interrupts are enabled */ 486 boolean_t niu_msi_enable; /* debug or configurable? */ 487 int intr_types; /* interrupt types supported */ 488 int intr_type; /* interrupt type to add */ 489 int max_int_cnt; /* max MSIX/INT HW supports */ 490 int start_inum; /* start inum (in sequence?) */ 491 int msi_intx_cnt; /* # msi/intx ints returned */ 492 int intr_added; /* # ints actually needed */ 493 int intr_cap; /* interrupt capabilities */ 494 size_t intr_size; /* size of array to allocate */ 495 ddi_intr_handle_t *htable; /* For array of interrupts */ 496 /* Add interrupt number for each interrupt vector */ 497 int pri; 498 } nxge_intr_t, *p_nxge_intr_t; 499 500 typedef struct _nxge_ldgv_t { 501 uint8_t ndma_ldvs; 502 uint8_t nldvs; 503 uint8_t maxldgs; 504 uint8_t maxldvs; 505 uint8_t ldg_intrs; 506 boolean_t own_sys_err; 507 boolean_t own_max_ldv; 508 uint32_t tmres; 509 p_nxge_ldg_t ldgp; 510 p_nxge_ldv_t ldvp; 511 p_nxge_ldv_t ldvp_syserr; 512 } nxge_ldgv_t, *p_nxge_ldgv_t; 513 514 typedef enum { 515 NXGE_TRANSMIT_GROUP, /* Legacy transmit group */ 516 NXGE_RECEIVE_GROUP, /* Legacy receive group */ 517 NXGE_VR_GROUP, /* Virtualization Region group */ 518 EXT_TRANSMIT_GROUP, /* External (Crossbow) transmit group */ 519 EXT_RECEIVE_GROUP /* External (Crossbow) receive group */ 520 } nxge_grp_type_t; 521 522 #define NXGE_ILLEGAL_CHANNEL (NXGE_MAX_TDCS + 1) 523 524 typedef uint8_t nxge_channel_t; 525 526 typedef struct nxge_grp { 527 nxge_t *nxge; 528 nxge_grp_type_t type; /* Tx or Rx */ 529 530 int sequence; /* When it was created. */ 531 int index; /* nxge_grp_set_t.group[index] */ 532 533 struct nx_dc *dc; /* Linked list of DMA channels. */ 534 size_t count; /* A count of <dc> above. */ 535 536 boolean_t active; /* Is it being used? */ 537 538 dc_map_t map; /* A bitmap of the channels in <dc>. */ 539 nxge_channel_t legend[NXGE_MAX_TDCS]; 540 541 } nxge_grp_t; 542 543 typedef struct { 544 lg_map_t map; 545 size_t count; 546 } lg_data_t; 547 548 typedef struct { 549 dc_map_t map; 550 size_t count; 551 } dc_data_t; 552 553 #define NXGE_DC_SET(map, channel) map |= (1 << channel) 554 #define NXGE_DC_RESET(map, channel) map &= (~(1 << channel)) 555 556 #define NXGE_LOGICAL_GROUP_MAX NXGE_MAX_TDCS 557 558 typedef struct { 559 int sequence; /* To order groups in time. */ 560 561 /* These are this instance's logical groups. */ 562 nxge_grp_t *group[NXGE_LOGICAL_GROUP_MAX]; 563 lg_data_t lg; 564 565 dc_data_t shared; /* These DCs are being shared. */ 566 dc_data_t owned; /* These DCs belong to me. */ 567 dc_data_t dead; /* These DCs are in an error state. */ 568 569 } nxge_grp_set_t; 570 571 /* 572 * Receive Ring Group 573 * One of the advanced virtualization features is the ability to bundle 574 * multiple Receive Rings in a single group. One or more MAC addresses may 575 * be assigned to a group. Incoming packets destined to the group's MAC 576 * address(es) are delivered to any ring member, according to a programmable 577 * or predefined RTS policy. Member rings can be polled individually. 578 * RX ring groups can come with a predefined set of member rings, or they 579 * are programmable by adding and removing rings to/from them. 580 */ 581 typedef struct _nxge_rx_ring_group_t { 582 mac_group_handle_t ghandle; 583 p_nxge_t nxgep; 584 int gindex; 585 int sindex; 586 } nxge_rx_ring_group_t; 587 588 /* 589 * Ring Handle 590 */ 591 typedef struct _nxge_ring_handle_t { 592 p_nxge_t nxgep; 593 int index; /* port-wise */ 594 mac_ring_handle_t ring_handle; 595 } nxge_ring_handle_t; 596 597 /* 598 * Share Handle 599 */ 600 typedef struct _nxge_share_handle_t { 601 p_nxge_t nxgep; /* Driver Handle */ 602 int index; 603 void *vrp; 604 uint64_t tmap; 605 uint64_t rmap; 606 int rxgroup; 607 boolean_t active; 608 } nxge_share_handle_t; 609 610 /* 611 * Neptune Device instance state information. 612 * 613 * Each instance is dynamically allocated on first attach. 614 */ 615 struct _nxge_t { 616 dev_info_t *dip; /* device instance */ 617 dev_info_t *p_dip; /* Parent's device instance */ 618 int instance; /* instance number */ 619 int function_num; /* device function number */ 620 int nports; /* # of ports on this device */ 621 int board_ver; /* Board Version */ 622 int partition_id; /* partition ID */ 623 int use_partition; /* partition is enabled */ 624 uint32_t drv_state; /* driver state bit flags */ 625 uint64_t nxge_debug_level; /* driver state bit flags */ 626 kmutex_t genlock[1]; 627 enum nxge_mac_state nxge_mac_state; 628 ddi_softintr_t resched_id; /* reschedule callback */ 629 boolean_t resched_needed; 630 boolean_t resched_running; 631 632 p_dev_regs_t dev_regs; 633 npi_handle_t npi_handle; 634 npi_handle_t npi_pci_handle; 635 npi_handle_t npi_reg_handle; 636 npi_handle_t npi_msi_handle; 637 npi_handle_t npi_vreg_handle; 638 npi_handle_t npi_v2reg_handle; 639 640 nxge_xcvr_table_t xcvr; 641 boolean_t hot_swappable_phy; 642 boolean_t phy_absent; 643 uint32_t xcvr_addr; 644 uint16_t chip_id; 645 nxge_mac_t mac; 646 nxge_ipp_t ipp; 647 nxge_txc_t txc; 648 nxge_classify_t classifier; 649 650 mac_handle_t mach; /* mac module handle */ 651 p_nxge_stats_t statsp; 652 uint32_t param_count; 653 p_nxge_param_t param_arr; 654 655 uint32_t param_en_pause:1, 656 param_en_asym_pause:1, 657 param_en_1000fdx:1, 658 param_en_100fdx:1, 659 param_en_10fdx:1, 660 param_pad_to_32:27; 661 662 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 663 niu_type_t niu_type; 664 platform_type_t platform_type; 665 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 666 667 uint8_t def_rdc; 668 669 nxge_intr_t nxge_intr_type; 670 nxge_dma_pt_cfg_t pt_config; 671 nxge_class_pt_cfg_t class_config; 672 673 /* Logical device and group data structures. */ 674 p_nxge_ldgv_t ldgvp; 675 676 npi_vpd_info_t vpd_info; 677 caddr_t param_list; /* Parameter list */ 678 679 ether_addr_st factaddr; /* factory mac address */ 680 ether_addr_st ouraddr; /* individual address */ 681 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 682 683 ddi_iblock_cookie_t interrupt_cookie; 684 685 /* 686 * Blocks of memory may be pre-allocated by the 687 * partition manager or the driver. They may include 688 * blocks for configuration and buffers. The idea is 689 * to preallocate big blocks of contiguous areas in 690 * system memory (i.e. with IOMMU). These blocks then 691 * will be broken up to a fixed number of blocks with 692 * each block having the same block size (4K, 8K, 16K or 693 * 32K) in the case of buffer blocks. For systems that 694 * do not support DVMA, more than one big block will be 695 * allocated. 696 */ 697 uint32_t rx_default_block_size; 698 nxge_rx_block_size_t rx_bksize_code; 699 700 p_nxge_dma_pool_t rx_buf_pool_p; 701 p_nxge_dma_pool_t rx_cntl_pool_p; 702 703 p_nxge_dma_pool_t tx_buf_pool_p; 704 p_nxge_dma_pool_t tx_cntl_pool_p; 705 706 /* Receive buffer block ring and completion ring. */ 707 p_rx_rbr_rings_t rx_rbr_rings; 708 p_rx_rcr_rings_t rx_rcr_rings; 709 p_rx_mbox_areas_t rx_mbox_areas_p; 710 711 p_rx_tx_params_t rx_params; 712 uint32_t start_rdc; 713 uint32_t max_rdcs; 714 uint32_t rdc_mask; 715 716 /* Transmit descriptors rings */ 717 p_tx_rings_t tx_rings; 718 p_tx_mbox_areas_t tx_mbox_areas_p; 719 720 uint32_t start_tdc; 721 uint32_t max_tdcs; 722 723 p_rx_tx_params_t tx_params; 724 725 ddi_dma_handle_t dmasparehandle; 726 727 ulong_t sys_page_sz; 728 ulong_t sys_page_mask; 729 int suspended; 730 731 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 732 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 733 734 kmutex_t mif_lock; /* Lock to protect the list. */ 735 736 void (*mii_read)(); 737 void (*mii_write)(); 738 void (*mii_poll)(); 739 filter_t filter; /* Current instance filter */ 740 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 741 krwlock_t filter_lock; /* Lock to protect filters. */ 742 743 ulong_t sys_burst_sz; 744 745 uint8_t cache_line; 746 747 timeout_id_t nxge_link_poll_timerid; 748 timeout_id_t nxge_timerid; 749 750 uint_t need_periodic_reclaim; 751 timeout_id_t reclaim_timer; 752 753 uint8_t msg_min; 754 uint8_t crc_size; 755 756 boolean_t hard_props_read; 757 758 boolean_t nxge_htraffic; 759 uint32_t nxge_ncpus; 760 uint32_t nxge_cpumask; 761 uint16_t intr_timeout; 762 uint16_t intr_threshold; 763 uchar_t nxge_rxmode; 764 uint32_t active_threads; 765 766 rtrace_t rtrace; 767 int fm_capabilities; /* FMA capabilities */ 768 769 uint32_t nxge_port_rbr_size; 770 uint32_t nxge_port_rbr_spare_size; 771 uint32_t nxge_port_rcr_size; 772 uint32_t nxge_port_rx_cntl_alloc_size; 773 uint32_t nxge_port_tx_ring_size; 774 nxge_mmac_t nxge_mmac_info; 775 #if defined(sun4v) 776 boolean_t niu_hsvc_available; 777 hsvc_info_t niu_hsvc; 778 uint64_t niu_min_ver; 779 #endif 780 boolean_t link_notify; 781 782 kmutex_t poll_lock; 783 kcondvar_t poll_cv; 784 link_mon_enable_t poll_state; 785 #define NXGE_MAGIC 0x3ab434e3 786 uint32_t nxge_magic; 787 788 int soft_lso_enable; 789 /* The following fields are LDOMs-specific additions. */ 790 nxge_environs_t environs; 791 ether_addr_t hio_mac_addr; 792 uint32_t niu_cfg_hdl; 793 kmutex_t group_lock; 794 795 struct nxge_hio_vr *hio_vr; 796 797 nxge_grp_set_t rx_set; 798 nxge_grp_set_t tx_set; 799 800 nxge_rx_ring_group_t rx_hio_groups[NXGE_MAX_RDC_GROUPS]; 801 nxge_share_handle_t shares[NXGE_MAX_VRS]; 802 }; 803 804 /* 805 * Driver state flags. 806 */ 807 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 808 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 809 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 810 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 811 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 812 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 813 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 814 815 #define STOP_POLL_THRESH 9 816 #define START_POLL_THRESH 2 817 818 typedef struct _nxge_port_kstat_t { 819 /* 820 * Transciever state informations. 821 */ 822 kstat_named_t xcvr_inits; 823 kstat_named_t xcvr_inuse; 824 kstat_named_t xcvr_addr; 825 kstat_named_t xcvr_id; 826 kstat_named_t cap_autoneg; 827 kstat_named_t cap_10gfdx; 828 kstat_named_t cap_10ghdx; 829 kstat_named_t cap_1000fdx; 830 kstat_named_t cap_1000hdx; 831 kstat_named_t cap_100T4; 832 kstat_named_t cap_100fdx; 833 kstat_named_t cap_100hdx; 834 kstat_named_t cap_10fdx; 835 kstat_named_t cap_10hdx; 836 kstat_named_t cap_asmpause; 837 kstat_named_t cap_pause; 838 839 /* 840 * Link partner capabilities. 841 */ 842 kstat_named_t lp_cap_autoneg; 843 kstat_named_t lp_cap_10gfdx; 844 kstat_named_t lp_cap_10ghdx; 845 kstat_named_t lp_cap_1000fdx; 846 kstat_named_t lp_cap_1000hdx; 847 kstat_named_t lp_cap_100T4; 848 kstat_named_t lp_cap_100fdx; 849 kstat_named_t lp_cap_100hdx; 850 kstat_named_t lp_cap_10fdx; 851 kstat_named_t lp_cap_10hdx; 852 kstat_named_t lp_cap_asmpause; 853 kstat_named_t lp_cap_pause; 854 855 /* 856 * Shared link setup. 857 */ 858 kstat_named_t link_T4; 859 kstat_named_t link_speed; 860 kstat_named_t link_duplex; 861 kstat_named_t link_asmpause; 862 kstat_named_t link_pause; 863 kstat_named_t link_up; 864 865 /* 866 * Lets the user know the MTU currently in use by 867 * the physical MAC port. 868 */ 869 kstat_named_t mac_mtu; 870 kstat_named_t lb_mode; 871 kstat_named_t qos_mode; 872 kstat_named_t trunk_mode; 873 874 /* 875 * Misc MAC statistics. 876 */ 877 kstat_named_t ifspeed; 878 kstat_named_t promisc; 879 kstat_named_t rev_id; 880 881 /* 882 * Some statistics added to support bringup, these 883 * should be removed. 884 */ 885 kstat_named_t user_defined; 886 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 887 888 typedef struct _nxge_rdc_kstat { 889 /* 890 * Receive DMA channel statistics. 891 */ 892 kstat_named_t ipackets; 893 kstat_named_t rbytes; 894 kstat_named_t errors; 895 kstat_named_t dcf_err; 896 kstat_named_t rcr_ack_err; 897 898 kstat_named_t dc_fifoflow_err; 899 kstat_named_t rcr_sha_par_err; 900 kstat_named_t rbr_pre_par_err; 901 kstat_named_t wred_drop; 902 kstat_named_t rbr_pre_emty; 903 904 kstat_named_t rcr_shadow_full; 905 kstat_named_t rbr_tmout; 906 kstat_named_t rsp_cnt_err; 907 kstat_named_t byte_en_bus; 908 kstat_named_t rsp_dat_err; 909 910 kstat_named_t pkt_too_long_err; 911 kstat_named_t compl_l2_err; 912 kstat_named_t compl_l4_cksum_err; 913 kstat_named_t compl_zcp_soft_err; 914 kstat_named_t compl_fflp_soft_err; 915 kstat_named_t config_err; 916 917 kstat_named_t rcrincon; 918 kstat_named_t rcrfull; 919 kstat_named_t rbr_empty; 920 kstat_named_t rbrfull; 921 kstat_named_t rbrlogpage; 922 923 kstat_named_t cfiglogpage; 924 kstat_named_t port_drop_pkt; 925 kstat_named_t rcr_to; 926 kstat_named_t rcr_thresh; 927 kstat_named_t rcr_mex; 928 kstat_named_t id_mismatch; 929 kstat_named_t zcp_eop_err; 930 kstat_named_t ipp_eop_err; 931 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 932 933 typedef struct _nxge_rdc_sys_kstat { 934 /* 935 * Receive DMA system statistics. 936 */ 937 kstat_named_t pre_par; 938 kstat_named_t sha_par; 939 kstat_named_t id_mismatch; 940 kstat_named_t ipp_eop_err; 941 kstat_named_t zcp_eop_err; 942 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 943 944 typedef struct _nxge_tdc_kstat { 945 /* 946 * Transmit DMA channel statistics. 947 */ 948 kstat_named_t opackets; 949 kstat_named_t obytes; 950 kstat_named_t oerrors; 951 kstat_named_t tx_inits; 952 kstat_named_t tx_no_buf; 953 954 kstat_named_t mbox_err; 955 kstat_named_t pkt_size_err; 956 kstat_named_t tx_ring_oflow; 957 kstat_named_t pref_buf_ecc_err; 958 kstat_named_t nack_pref; 959 kstat_named_t nack_pkt_rd; 960 kstat_named_t conf_part_err; 961 kstat_named_t pkt_prt_err; 962 kstat_named_t reset_fail; 963 /* used to in the common (per port) counter */ 964 965 kstat_named_t tx_starts; 966 kstat_named_t tx_nocanput; 967 kstat_named_t tx_msgdup_fail; 968 kstat_named_t tx_allocb_fail; 969 kstat_named_t tx_no_desc; 970 kstat_named_t tx_dma_bind_fail; 971 kstat_named_t tx_uflo; 972 kstat_named_t tx_hdr_pkts; 973 kstat_named_t tx_ddi_pkts; 974 kstat_named_t tx_dvma_pkts; 975 kstat_named_t tx_max_pend; 976 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 977 978 typedef struct _nxge_txc_kstat { 979 /* 980 * Transmit port TXC block statistics. 981 */ 982 kstat_named_t pkt_stuffed; 983 kstat_named_t pkt_xmit; 984 kstat_named_t ro_correct_err; 985 kstat_named_t ro_uncorrect_err; 986 kstat_named_t sf_correct_err; 987 kstat_named_t sf_uncorrect_err; 988 kstat_named_t address_failed; 989 kstat_named_t dma_failed; 990 kstat_named_t length_failed; 991 kstat_named_t pkt_assy_dead; 992 kstat_named_t reorder_err; 993 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 994 995 typedef struct _nxge_ipp_kstat { 996 /* 997 * Receive port IPP block statistics. 998 */ 999 kstat_named_t eop_miss; 1000 kstat_named_t sop_miss; 1001 kstat_named_t dfifo_ue; 1002 kstat_named_t ecc_err_cnt; 1003 kstat_named_t pfifo_perr; 1004 kstat_named_t pfifo_over; 1005 kstat_named_t pfifo_und; 1006 kstat_named_t bad_cs_cnt; 1007 kstat_named_t pkt_dis_cnt; 1008 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 1009 1010 typedef struct _nxge_zcp_kstat { 1011 /* 1012 * ZCP statistics. 1013 */ 1014 kstat_named_t errors; 1015 kstat_named_t inits; 1016 kstat_named_t rrfifo_underrun; 1017 kstat_named_t rrfifo_overrun; 1018 kstat_named_t rspfifo_uncorr_err; 1019 kstat_named_t buffer_overflow; 1020 kstat_named_t stat_tbl_perr; 1021 kstat_named_t dyn_tbl_perr; 1022 kstat_named_t buf_tbl_perr; 1023 kstat_named_t tt_program_err; 1024 kstat_named_t rsp_tt_index_err; 1025 kstat_named_t slv_tt_index_err; 1026 kstat_named_t zcp_tt_index_err; 1027 kstat_named_t access_fail; 1028 kstat_named_t cfifo_ecc; 1029 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 1030 1031 typedef struct _nxge_mac_kstat { 1032 /* 1033 * Transmit MAC statistics. 1034 */ 1035 kstat_named_t tx_frame_cnt; 1036 kstat_named_t tx_underflow_err; 1037 kstat_named_t tx_overflow_err; 1038 kstat_named_t tx_maxpktsize_err; 1039 kstat_named_t tx_fifo_xfr_err; 1040 kstat_named_t tx_byte_cnt; 1041 1042 /* 1043 * Receive MAC statistics. 1044 */ 1045 kstat_named_t rx_frame_cnt; 1046 kstat_named_t rx_underflow_err; 1047 kstat_named_t rx_overflow_err; 1048 kstat_named_t rx_len_err_cnt; 1049 kstat_named_t rx_crc_err_cnt; 1050 kstat_named_t rx_viol_err_cnt; 1051 kstat_named_t rx_byte_cnt; 1052 kstat_named_t rx_hist1_cnt; 1053 kstat_named_t rx_hist2_cnt; 1054 kstat_named_t rx_hist3_cnt; 1055 kstat_named_t rx_hist4_cnt; 1056 kstat_named_t rx_hist5_cnt; 1057 kstat_named_t rx_hist6_cnt; 1058 kstat_named_t rx_hist7_cnt; 1059 kstat_named_t rx_broadcast_cnt; 1060 kstat_named_t rx_mult_cnt; 1061 kstat_named_t rx_frag_cnt; 1062 kstat_named_t rx_frame_align_err_cnt; 1063 kstat_named_t rx_linkfault_err_cnt; 1064 kstat_named_t rx_local_fault_err_cnt; 1065 kstat_named_t rx_remote_fault_err_cnt; 1066 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 1067 1068 typedef struct _nxge_xmac_kstat { 1069 /* 1070 * XMAC statistics. 1071 */ 1072 kstat_named_t tx_frame_cnt; 1073 kstat_named_t tx_underflow_err; 1074 kstat_named_t tx_maxpktsize_err; 1075 kstat_named_t tx_overflow_err; 1076 kstat_named_t tx_fifo_xfr_err; 1077 kstat_named_t tx_byte_cnt; 1078 kstat_named_t rx_frame_cnt; 1079 kstat_named_t rx_underflow_err; 1080 kstat_named_t rx_overflow_err; 1081 kstat_named_t rx_crc_err_cnt; 1082 kstat_named_t rx_len_err_cnt; 1083 kstat_named_t rx_viol_err_cnt; 1084 kstat_named_t rx_byte_cnt; 1085 kstat_named_t rx_hist1_cnt; 1086 kstat_named_t rx_hist2_cnt; 1087 kstat_named_t rx_hist3_cnt; 1088 kstat_named_t rx_hist4_cnt; 1089 kstat_named_t rx_hist5_cnt; 1090 kstat_named_t rx_hist6_cnt; 1091 kstat_named_t rx_hist7_cnt; 1092 kstat_named_t rx_broadcast_cnt; 1093 kstat_named_t rx_mult_cnt; 1094 kstat_named_t rx_frag_cnt; 1095 kstat_named_t rx_frame_align_err_cnt; 1096 kstat_named_t rx_linkfault_err_cnt; 1097 kstat_named_t rx_remote_fault_err_cnt; 1098 kstat_named_t rx_local_fault_err_cnt; 1099 kstat_named_t rx_pause_cnt; 1100 kstat_named_t xpcs_deskew_err_cnt; 1101 kstat_named_t xpcs_ln0_symbol_err_cnt; 1102 kstat_named_t xpcs_ln1_symbol_err_cnt; 1103 kstat_named_t xpcs_ln2_symbol_err_cnt; 1104 kstat_named_t xpcs_ln3_symbol_err_cnt; 1105 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 1106 1107 typedef struct _nxge_bmac_kstat { 1108 /* 1109 * BMAC statistics. 1110 */ 1111 kstat_named_t tx_frame_cnt; 1112 kstat_named_t tx_underrun_err; 1113 kstat_named_t tx_max_pkt_err; 1114 kstat_named_t tx_byte_cnt; 1115 kstat_named_t rx_frame_cnt; 1116 kstat_named_t rx_byte_cnt; 1117 kstat_named_t rx_overflow_err; 1118 kstat_named_t rx_align_err_cnt; 1119 kstat_named_t rx_crc_err_cnt; 1120 kstat_named_t rx_len_err_cnt; 1121 kstat_named_t rx_viol_err_cnt; 1122 kstat_named_t rx_pause_cnt; 1123 kstat_named_t tx_pause_state; 1124 kstat_named_t tx_nopause_state; 1125 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 1126 1127 1128 typedef struct _nxge_fflp_kstat { 1129 /* 1130 * FFLP statistics. 1131 */ 1132 1133 kstat_named_t fflp_tcam_perr; 1134 kstat_named_t fflp_tcam_ecc_err; 1135 kstat_named_t fflp_vlan_perr; 1136 kstat_named_t fflp_hasht_lookup_err; 1137 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 1138 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1139 1140 typedef struct _nxge_mmac_kstat { 1141 kstat_named_t mmac_max_addr_cnt; 1142 kstat_named_t mmac_avail_addr_cnt; 1143 kstat_named_t mmac_addr1; 1144 kstat_named_t mmac_addr2; 1145 kstat_named_t mmac_addr3; 1146 kstat_named_t mmac_addr4; 1147 kstat_named_t mmac_addr5; 1148 kstat_named_t mmac_addr6; 1149 kstat_named_t mmac_addr7; 1150 kstat_named_t mmac_addr8; 1151 kstat_named_t mmac_addr9; 1152 kstat_named_t mmac_addr10; 1153 kstat_named_t mmac_addr11; 1154 kstat_named_t mmac_addr12; 1155 kstat_named_t mmac_addr13; 1156 kstat_named_t mmac_addr14; 1157 kstat_named_t mmac_addr15; 1158 kstat_named_t mmac_addr16; 1159 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1160 1161 #endif /* _KERNEL */ 1162 1163 /* 1164 * Prototype definitions. 1165 */ 1166 nxge_status_t nxge_init(p_nxge_t); 1167 void nxge_uninit(p_nxge_t); 1168 void nxge_get64(p_nxge_t, p_mblk_t); 1169 void nxge_put64(p_nxge_t, p_mblk_t); 1170 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1171 1172 #ifndef COSIM 1173 typedef void (*fptrv_t)(); 1174 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1175 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1176 #endif 1177 #endif 1178 1179 #ifdef __cplusplus 1180 } 1181 #endif 1182 1183 #endif /* _SYS_NXGE_NXGE_H */ 1184