1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <nxge_mac.h> 34 #include <nxge_ipp.h> 35 #include <nxge_fflp.h> 36 37 /* 38 * NXGE diagnostics IOCTLS. 39 */ 40 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 41 42 #define NXGE_GET64 (NXGE_IOC|1) 43 #define NXGE_PUT64 (NXGE_IOC|2) 44 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 45 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 46 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 47 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 48 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 49 #define NXGE_RESET_MAC (NXGE_IOC|8) 50 51 #define NXGE_GET_MII (NXGE_IOC|11) 52 #define NXGE_PUT_MII (NXGE_IOC|12) 53 #define NXGE_RTRACE (NXGE_IOC|13) 54 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 55 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 56 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 57 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 58 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 59 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 60 #define NXGE_RDUMP (NXGE_IOC|26) 61 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 62 #define NXGE_PIO_TEST (NXGE_IOC|28) 63 64 #define NXGE_GET_TCAM (NXGE_IOC|29) 65 #define NXGE_PUT_TCAM (NXGE_IOC|30) 66 #define NXGE_INJECT_ERR (NXGE_IOC|40) 67 68 #define NXGE_OK 0 69 #define NXGE_ERROR 0x40000000 70 #define NXGE_DDI_FAILED 0x20000000 71 #define NXGE_GET_PORT_NUM(n) n 72 73 /* 74 * Definitions for module_info. 75 */ 76 #define NXGE_IDNUM (0) /* module ID number */ 77 #define NXGE_DRIVER_NAME "nxge" /* module name */ 78 79 #define NXGE_MINPSZ (0) /* min packet size */ 80 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 81 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 82 #define NXGE_LOWAT (1) /* lo-water mark */ 83 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 84 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 85 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 86 #define NXGE_LOWAT_MIN (1) 87 88 #ifndef D_HOTPLUG 89 #define D_HOTPLUG 0x00 90 #endif 91 92 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 93 94 #define NXGE_CHECK_TIMER (5000) 95 96 typedef enum { 97 param_instance, 98 param_main_instance, 99 param_function_number, 100 param_partition_id, 101 param_read_write_mode, 102 param_fw_version, 103 param_port_mode, 104 param_niu_cfg_type, 105 param_tx_quick_cfg, 106 param_rx_quick_cfg, 107 param_master_cfg_enable, 108 param_master_cfg_value, 109 110 param_autoneg, 111 param_anar_10gfdx, 112 param_anar_10ghdx, 113 param_anar_1000fdx, 114 param_anar_1000hdx, 115 param_anar_100T4, 116 param_anar_100fdx, 117 param_anar_100hdx, 118 param_anar_10fdx, 119 param_anar_10hdx, 120 121 param_anar_asmpause, 122 param_anar_pause, 123 param_use_int_xcvr, 124 param_enable_ipg0, 125 param_ipg0, 126 param_ipg1, 127 param_ipg2, 128 param_accept_jumbo, 129 param_txdma_weight, 130 param_txdma_channels_begin, 131 132 param_txdma_channels, 133 param_txdma_info, 134 param_rxdma_channels_begin, 135 param_rxdma_channels, 136 param_rxdma_drr_weight, 137 param_rxdma_full_header, 138 param_rxdma_info, 139 param_rxdma_rbr_size, 140 param_rxdma_rcr_size, 141 param_default_port_rdc, 142 param_rxdma_intr_time, 143 param_rxdma_intr_pkts, 144 145 param_rdc_grps_start, 146 param_rx_rdc_grps, 147 param_default_grp0_rdc, 148 param_default_grp1_rdc, 149 param_default_grp2_rdc, 150 param_default_grp3_rdc, 151 param_default_grp4_rdc, 152 param_default_grp5_rdc, 153 param_default_grp6_rdc, 154 param_default_grp7_rdc, 155 156 param_info_rdc_groups, 157 param_start_ldg, 158 param_max_ldg, 159 param_mac_2rdc_grp, 160 param_vlan_2rdc_grp, 161 param_fcram_part_cfg, 162 param_fcram_access_ratio, 163 param_tcam_access_ratio, 164 param_tcam_enable, 165 param_hash_lookup_enable, 166 param_llc_snap_enable, 167 168 param_h1_init_value, 169 param_h2_init_value, 170 param_class_cfg_ether_usr1, 171 param_class_cfg_ether_usr2, 172 param_class_cfg_ip_usr4, 173 param_class_cfg_ip_usr5, 174 param_class_cfg_ip_usr6, 175 param_class_cfg_ip_usr7, 176 param_class_opt_ip_usr4, 177 param_class_opt_ip_usr5, 178 param_class_opt_ip_usr6, 179 param_class_opt_ip_usr7, 180 param_class_opt_ipv4_tcp, 181 param_class_opt_ipv4_udp, 182 param_class_opt_ipv4_ah, 183 param_class_opt_ipv4_sctp, 184 param_class_opt_ipv6_tcp, 185 param_class_opt_ipv6_udp, 186 param_class_opt_ipv6_ah, 187 param_class_opt_ipv6_sctp, 188 param_nxge_debug_flag, 189 param_npi_debug_flag, 190 param_dump_rdc, 191 param_dump_tdc, 192 param_dump_mac_regs, 193 param_dump_ipp_regs, 194 param_dump_fflp_regs, 195 param_dump_vlan_table, 196 param_dump_rdc_table, 197 param_dump_ptrs, 198 param_end 199 } nxge_param_index_t; 200 201 typedef enum { 202 SOLARIS_DOMAIN, 203 SOLARIS_SERVICE_DOMAIN, 204 SOLARIS_GUEST_DOMAIN, 205 LINUX_SERVICE_DOMAIN, 206 LINUX_GUEST_DOMAIN 207 } nxge_environs_t; 208 209 /* 210 * Named Dispatch Parameter Management Structure 211 */ 212 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 213 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 214 MBLKP, char *, caddr_t, cred_t *); 215 216 #define NXGE_PARAM_READ 0x00000001ULL 217 #define NXGE_PARAM_WRITE 0x00000002ULL 218 #define NXGE_PARAM_SHARED 0x00000004ULL 219 #define NXGE_PARAM_PRIV 0x00000008ULL 220 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 221 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 222 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 223 224 #define NXGE_PARAM_RXDMA 0x00000010ULL 225 #define NXGE_PARAM_TXDMA 0x00000020ULL 226 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 227 #define NXGE_PARAM_MAC 0x00000080ULL 228 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 229 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 230 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 231 232 #define NXGE_PARAM_CMPLX 0x00010000ULL 233 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 234 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 235 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 236 237 #define NXGE_PARAM_READ_PROP 0x00100000ULL 238 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 239 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 240 #define NXGE_PARAM_PROP_STR 0x00800000ULL 241 242 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 243 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 244 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 245 #define NXGE_PARAM_BASE_STR 0x40000000ULL 246 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 247 248 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 249 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 250 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 251 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 252 253 typedef struct _nxge_param_t { 254 int (*getf)(); 255 int (*setf)(); /* null for read only */ 256 uint64_t type; /* R/W/ Common/Port/ .... */ 257 uint64_t minimum; 258 uint64_t maximum; 259 uint64_t value; /* for array params, pointer to value array */ 260 uint64_t old_value; /* for array params, pointer to old_value array */ 261 char *fcode_name; 262 char *name; 263 } nxge_param_t, *p_nxge_param_t; 264 265 266 /* 267 * Do not change the order of the elements of this enum as that will 268 * break the driver code. 269 */ 270 typedef enum { 271 nxge_lb_normal, 272 nxge_lb_ext10g, 273 nxge_lb_ext1000, 274 nxge_lb_ext100, 275 nxge_lb_ext10, 276 nxge_lb_phy10g, 277 nxge_lb_phy1000, 278 nxge_lb_phy, 279 nxge_lb_serdes10g, 280 nxge_lb_serdes1000, 281 nxge_lb_serdes, 282 nxge_lb_mac10g, 283 nxge_lb_mac1000, 284 nxge_lb_mac 285 } nxge_lb_t; 286 287 enum nxge_mac_state { 288 NXGE_MAC_STOPPED = 0, 289 NXGE_MAC_STARTED, 290 NXGE_MAC_STOPPING 291 }; 292 293 /* 294 * Private DLPI full dlsap address format. 295 */ 296 typedef struct _nxge_dladdr_t { 297 ether_addr_st dl_phys; 298 uint16_t dl_sap; 299 } nxge_dladdr_t, *p_nxge_dladdr_t; 300 301 typedef struct _mc_addr_t { 302 ether_addr_st multcast_addr; 303 uint_t mc_addr_cnt; 304 } mc_addr_t, *p_mc_addr_t; 305 306 typedef struct _mc_bucket_t { 307 p_mc_addr_t addr_list; 308 uint_t list_size; 309 } mc_bucket_t, *p_mc_bucket_t; 310 311 typedef struct _mc_table_t { 312 p_mc_bucket_t bucket_list; 313 uint_t buckets_used; 314 } mc_table_t, *p_mc_table_t; 315 316 typedef struct _filter_t { 317 uint32_t all_phys_cnt; 318 uint32_t all_multicast_cnt; 319 uint32_t all_sap_cnt; 320 } filter_t, *p_filter_t; 321 322 323 typedef struct _nxge_port_stats_t { 324 /* 325 * Overall structure size 326 */ 327 size_t stats_size; 328 329 /* 330 * Link Input/Output stats 331 */ 332 uint64_t ipackets; 333 uint64_t ierrors; 334 uint64_t opackets; 335 uint64_t oerrors; 336 uint64_t collisions; 337 338 /* 339 * MIB II variables 340 */ 341 uint64_t rbytes; /* # bytes received */ 342 uint64_t obytes; /* # bytes transmitted */ 343 uint32_t multircv; /* # multicast packets received */ 344 uint32_t multixmt; /* # multicast packets for xmit */ 345 uint32_t brdcstrcv; /* # broadcast packets received */ 346 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 347 uint32_t norcvbuf; /* # rcv packets discarded */ 348 uint32_t noxmtbuf; /* # xmit packets discarded */ 349 350 /* 351 * Lets the user know the MTU currently in use by 352 * the physical MAC port. 353 */ 354 nxge_lb_t lb_mode; 355 uint32_t qos_mode; 356 uint32_t trunk_mode; 357 uint32_t poll_mode; 358 359 /* 360 * Tx Statistics. 361 */ 362 uint32_t tx_inits; 363 uint32_t tx_starts; 364 uint32_t tx_nocanput; 365 uint32_t tx_msgdup_fail; 366 uint32_t tx_allocb_fail; 367 uint32_t tx_no_desc; 368 uint32_t tx_dma_bind_fail; 369 uint32_t tx_uflo; 370 uint32_t tx_hdr_pkts; 371 uint32_t tx_ddi_pkts; 372 uint32_t tx_dvma_pkts; 373 374 uint32_t tx_max_pend; 375 376 /* 377 * Rx Statistics. 378 */ 379 uint32_t rx_inits; 380 uint32_t rx_hdr_pkts; 381 uint32_t rx_mtu_pkts; 382 uint32_t rx_split_pkts; 383 uint32_t rx_no_buf; 384 uint32_t rx_no_comp_wb; 385 uint32_t rx_ov_flow; 386 uint32_t rx_len_mm; 387 uint32_t rx_tag_err; 388 uint32_t rx_nocanput; 389 uint32_t rx_msgdup_fail; 390 uint32_t rx_allocb_fail; 391 392 /* 393 * Receive buffer management statistics. 394 */ 395 uint32_t rx_new_pages; 396 uint32_t rx_new_hdr_pgs; 397 uint32_t rx_new_mtu_pgs; 398 uint32_t rx_new_nxt_pgs; 399 uint32_t rx_reused_pgs; 400 uint32_t rx_hdr_drops; 401 uint32_t rx_mtu_drops; 402 uint32_t rx_nxt_drops; 403 404 /* 405 * Receive flow statistics 406 */ 407 uint32_t rx_rel_flow; 408 uint32_t rx_rel_bit; 409 410 uint32_t rx_pkts_dropped; 411 412 /* 413 * PCI-E Bus Statistics. 414 */ 415 uint32_t pci_bus_speed; 416 uint32_t pci_err; 417 uint32_t pci_rta_err; 418 uint32_t pci_rma_err; 419 uint32_t pci_parity_err; 420 uint32_t pci_bad_ack_err; 421 uint32_t pci_drto_err; 422 uint32_t pci_dmawz_err; 423 uint32_t pci_dmarz_err; 424 425 uint32_t rx_taskq_waits; 426 427 uint32_t tx_jumbo_pkts; 428 429 /* 430 * Some statistics added to support bringup, these 431 * should be removed. 432 */ 433 uint32_t user_defined; 434 } nxge_port_stats_t, *p_nxge_port_stats_t; 435 436 437 typedef struct _nxge_stats_t { 438 /* 439 * Overall structure size 440 */ 441 size_t stats_size; 442 443 kstat_t *ksp; 444 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 445 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 446 kstat_t *rdc_sys_ksp; 447 kstat_t *fflp_ksp[1]; 448 kstat_t *ipp_ksp; 449 kstat_t *txc_ksp; 450 kstat_t *mac_ksp; 451 kstat_t *zcp_ksp; 452 kstat_t *port_ksp; 453 kstat_t *mmac_ksp; 454 455 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 456 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 457 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 458 459 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 460 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 461 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 462 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 463 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 464 465 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 466 nxge_txc_stats_t txc_stats; /* per port TX stats */ 467 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 468 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 469 nxge_port_stats_t port_stats; /* fflp stats */ 470 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 471 472 } nxge_stats_t, *p_nxge_stats_t; 473 474 475 476 typedef struct _nxge_intr_t { 477 boolean_t intr_registered; /* interrupts are registered */ 478 boolean_t intr_enabled; /* interrupts are enabled */ 479 boolean_t niu_msi_enable; /* debug or configurable? */ 480 int intr_types; /* interrupt types supported */ 481 int intr_type; /* interrupt type to add */ 482 int max_int_cnt; /* max MSIX/INT HW supports */ 483 int start_inum; /* start inum (in sequence?) */ 484 int msi_intx_cnt; /* # msi/intx ints returned */ 485 int intr_added; /* # ints actually needed */ 486 int intr_cap; /* interrupt capabilities */ 487 size_t intr_size; /* size of array to allocate */ 488 ddi_intr_handle_t *htable; /* For array of interrupts */ 489 /* Add interrupt number for each interrupt vector */ 490 int pri; 491 } nxge_intr_t, *p_nxge_intr_t; 492 493 typedef struct _nxge_ldgv_t { 494 uint8_t ndma_ldvs; 495 uint8_t nldvs; 496 uint8_t maxldgs; 497 uint8_t maxldvs; 498 uint8_t ldg_intrs; 499 uint32_t tmres; 500 p_nxge_ldg_t ldgp; 501 p_nxge_ldv_t ldvp; 502 p_nxge_ldv_t ldvp_syserr; 503 boolean_t ldvp_syserr_alloced; 504 } nxge_ldgv_t, *p_nxge_ldgv_t; 505 506 typedef enum { 507 NXGE_TRANSMIT_GROUP, /* Legacy transmit group */ 508 NXGE_RECEIVE_GROUP, /* Legacy receive group */ 509 NXGE_VR_GROUP, /* Virtualization Region group */ 510 EXT_TRANSMIT_GROUP, /* External (Crossbow) transmit group */ 511 EXT_RECEIVE_GROUP /* External (Crossbow) receive group */ 512 } nxge_grp_type_t; 513 514 #define NXGE_ILLEGAL_CHANNEL (NXGE_MAX_TDCS + 1) 515 516 typedef uint8_t nxge_channel_t; 517 518 typedef struct nxge_grp { 519 nxge_t *nxge; 520 nxge_grp_type_t type; /* Tx or Rx */ 521 522 int sequence; /* When it was created. */ 523 int index; /* nxge_grp_set_t.group[index] */ 524 525 struct nx_dc *dc; /* Linked list of DMA channels. */ 526 size_t count; /* A count of <dc> above. */ 527 528 boolean_t active; /* Is it being used? */ 529 530 dc_map_t map; /* A bitmap of the channels in <dc>. */ 531 nxge_channel_t legend[NXGE_MAX_TDCS]; 532 533 } nxge_grp_t; 534 535 typedef struct { 536 lg_map_t map; 537 size_t count; 538 } lg_data_t; 539 540 typedef struct { 541 dc_map_t map; 542 size_t count; 543 } dc_data_t; 544 545 #define NXGE_DC_SET(map, channel) map |= (1 << channel) 546 #define NXGE_DC_RESET(map, channel) map &= (~(1 << channel)) 547 548 /* For now, we only support up to 8 RDC/TDC groups */ 549 #define NXGE_LOGICAL_GROUP_MAX NXGE_MAX_RDC_GROUPS 550 551 typedef struct { 552 int sequence; /* To order groups in time. */ 553 554 /* These are this instance's logical groups. */ 555 nxge_grp_t *group[NXGE_LOGICAL_GROUP_MAX]; 556 lg_data_t lg; 557 558 dc_data_t shared; /* These DCs are being shared. */ 559 dc_data_t owned; /* These DCs belong to me. */ 560 dc_data_t dead; /* These DCs are in an error state. */ 561 562 } nxge_grp_set_t; 563 564 /* 565 * Transmit Ring Group 566 * TX groups will be used exclusively for the purpose of Hybrid I/O. From 567 * the point of view of the nxge driver, the groups will be software 568 * constructs which will be used to establish the relationship between TX 569 * rings and shares. 570 * 571 * Receive Ring Group 572 * One of the advanced virtualization features is the ability to bundle 573 * multiple Receive Rings in a single group. One or more MAC addresses may 574 * be assigned to a group. Incoming packets destined to the group's MAC 575 * address(es) are delivered to any ring member, according to a programmable 576 * or predefined RTS policy. Member rings can be polled individually. 577 * RX ring groups can come with a predefined set of member rings, or they 578 * are programmable by adding and removing rings to/from them. 579 */ 580 typedef struct _nxge_ring_group_t { 581 mac_group_handle_t ghandle; 582 p_nxge_t nxgep; 583 boolean_t started; 584 mac_ring_type_t type; 585 int gindex; 586 int sindex; 587 int rdctbl; 588 int n_mac_addrs; 589 } nxge_ring_group_t; 590 591 /* 592 * Ring Handle 593 */ 594 typedef struct _nxge_ring_handle_t { 595 p_nxge_t nxgep; 596 int index; /* port-wise */ 597 mac_ring_handle_t ring_handle; 598 } nxge_ring_handle_t, *p_nxge_ring_handle_t; 599 600 /* 601 * Share Handle 602 */ 603 typedef struct _nxge_share_handle_t { 604 p_nxge_t nxgep; /* Driver Handle */ 605 int index; 606 void *vrp; 607 uint64_t tmap; 608 uint64_t rmap; 609 int rxgroup; 610 boolean_t active; 611 } nxge_share_handle_t; 612 613 /* 614 * Neptune Device instance state information. 615 * 616 * Each instance is dynamically allocated on first attach. 617 */ 618 struct _nxge_t { 619 dev_info_t *dip; /* device instance */ 620 dev_info_t *p_dip; /* Parent's device instance */ 621 int instance; /* instance number */ 622 int function_num; /* device function number */ 623 int nports; /* # of ports on this device */ 624 int board_ver; /* Board Version */ 625 int use_partition; /* partition is enabled */ 626 uint32_t drv_state; /* driver state bit flags */ 627 uint64_t nxge_debug_level; /* driver state bit flags */ 628 kmutex_t genlock[1]; 629 enum nxge_mac_state nxge_mac_state; 630 631 p_dev_regs_t dev_regs; 632 npi_handle_t npi_handle; 633 npi_handle_t npi_pci_handle; 634 npi_handle_t npi_reg_handle; 635 npi_handle_t npi_msi_handle; 636 npi_handle_t npi_vreg_handle; 637 npi_handle_t npi_v2reg_handle; 638 639 nxge_xcvr_table_t xcvr; 640 boolean_t hot_swappable_phy; 641 boolean_t phy_absent; 642 uint32_t xcvr_addr; 643 uint16_t chip_id; 644 nxge_mac_t mac; 645 nxge_ipp_t ipp; 646 nxge_txc_t txc; 647 nxge_classify_t classifier; 648 649 mac_handle_t mach; /* mac module handle */ 650 p_nxge_stats_t statsp; 651 uint32_t param_count; 652 p_nxge_param_t param_arr; 653 654 uint32_t param_en_pause:1, 655 param_en_asym_pause:1, 656 param_en_1000fdx:1, 657 param_en_100fdx:1, 658 param_en_10fdx:1, 659 param_pad_to_32:27; 660 661 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 662 niu_type_t niu_type; 663 platform_type_t platform_type; 664 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 665 666 uint8_t def_rdc; 667 668 nxge_intr_t nxge_intr_type; 669 nxge_dma_pt_cfg_t pt_config; 670 nxge_class_pt_cfg_t class_config; 671 672 /* Logical device and group data structures. */ 673 p_nxge_ldgv_t ldgvp; 674 675 npi_vpd_info_t vpd_info; 676 677 ether_addr_st factaddr; /* factory mac address */ 678 ether_addr_st ouraddr; /* individual address */ 679 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 680 681 ddi_iblock_cookie_t interrupt_cookie; 682 683 /* 684 * Blocks of memory may be pre-allocated by the 685 * partition manager or the driver. They may include 686 * blocks for configuration and buffers. The idea is 687 * to preallocate big blocks of contiguous areas in 688 * system memory (i.e. with IOMMU). These blocks then 689 * will be broken up to a fixed number of blocks with 690 * each block having the same block size (4K, 8K, 16K or 691 * 32K) in the case of buffer blocks. For systems that 692 * do not support DVMA, more than one big block will be 693 * allocated. 694 */ 695 uint32_t rx_default_block_size; 696 nxge_rx_block_size_t rx_bksize_code; 697 698 p_nxge_dma_pool_t rx_buf_pool_p; 699 p_nxge_dma_pool_t rx_cntl_pool_p; 700 701 p_nxge_dma_pool_t tx_buf_pool_p; 702 p_nxge_dma_pool_t tx_cntl_pool_p; 703 704 /* Receive buffer block ring and completion ring. */ 705 p_rx_rbr_rings_t rx_rbr_rings; 706 p_rx_rcr_rings_t rx_rcr_rings; 707 p_rx_mbox_areas_t rx_mbox_areas_p; 708 709 uint32_t rdc_mask; 710 711 /* Transmit descriptors rings */ 712 p_tx_rings_t tx_rings; 713 p_tx_mbox_areas_t tx_mbox_areas_p; 714 715 ddi_dma_handle_t dmasparehandle; 716 717 ulong_t sys_page_sz; 718 ulong_t sys_page_mask; 719 int suspended; 720 721 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 722 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 723 724 kmutex_t mif_lock; /* Lock to protect the list. */ 725 726 void (*mii_read)(); 727 void (*mii_write)(); 728 void (*mii_poll)(); 729 filter_t filter; /* Current instance filter */ 730 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 731 krwlock_t filter_lock; /* Lock to protect filters. */ 732 733 ulong_t sys_burst_sz; 734 735 uint8_t cache_line; 736 737 timeout_id_t nxge_link_poll_timerid; 738 timeout_id_t nxge_timerid; 739 740 uint_t need_periodic_reclaim; 741 timeout_id_t reclaim_timer; 742 743 uint8_t msg_min; 744 uint8_t crc_size; 745 746 boolean_t hard_props_read; 747 748 uint32_t nxge_ncpus; 749 uint16_t intr_timeout; 750 uint16_t intr_threshold; 751 752 int fm_capabilities; /* FMA capabilities */ 753 754 uint32_t nxge_port_rbr_size; 755 uint32_t nxge_port_rbr_spare_size; 756 uint32_t nxge_port_rcr_size; 757 uint32_t nxge_port_rx_cntl_alloc_size; 758 uint32_t nxge_port_tx_ring_size; 759 nxge_mmac_t nxge_mmac_info; 760 #if defined(sun4v) 761 boolean_t niu_hsvc_available; 762 hsvc_info_t niu_hsvc; 763 uint64_t niu_min_ver; 764 #endif 765 boolean_t link_notify; 766 767 kmutex_t poll_lock; 768 kcondvar_t poll_cv; 769 link_mon_enable_t poll_state; 770 #define NXGE_MAGIC 0x3ab434e3 771 uint32_t nxge_magic; 772 773 int soft_lso_enable; 774 /* The following fields are LDOMs-specific additions. */ 775 nxge_environs_t environs; 776 ether_addr_t hio_mac_addr; 777 uint32_t niu_cfg_hdl; 778 kmutex_t group_lock; 779 780 struct nxge_hio_vr *hio_vr; 781 782 nxge_grp_set_t rx_set; 783 nxge_grp_set_t tx_set; 784 boolean_t tdc_is_shared[NXGE_MAX_TDCS]; 785 786 boolean_t rx_channel_started[NXGE_MAX_RDCS]; 787 788 /* Ring Handles */ 789 nxge_ring_handle_t tx_ring_handles[NXGE_MAX_TDCS]; 790 nxge_ring_handle_t rx_ring_handles[NXGE_MAX_RDCS]; 791 792 nxge_ring_group_t tx_hio_groups[NXGE_MAX_TDC_GROUPS]; 793 nxge_ring_group_t rx_hio_groups[NXGE_MAX_RDC_GROUPS]; 794 795 nxge_share_handle_t shares[NXGE_MAX_VRS]; 796 }; 797 798 /* 799 * Driver state flags. 800 */ 801 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 802 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 803 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 804 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 805 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 806 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 807 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 808 809 #define STOP_POLL_THRESH 9 810 #define START_POLL_THRESH 2 811 812 typedef struct _nxge_port_kstat_t { 813 /* 814 * Transciever state informations. 815 */ 816 kstat_named_t xcvr_inits; 817 kstat_named_t xcvr_inuse; 818 kstat_named_t xcvr_addr; 819 kstat_named_t xcvr_id; 820 kstat_named_t cap_autoneg; 821 kstat_named_t cap_10gfdx; 822 kstat_named_t cap_10ghdx; 823 kstat_named_t cap_1000fdx; 824 kstat_named_t cap_1000hdx; 825 kstat_named_t cap_100T4; 826 kstat_named_t cap_100fdx; 827 kstat_named_t cap_100hdx; 828 kstat_named_t cap_10fdx; 829 kstat_named_t cap_10hdx; 830 kstat_named_t cap_asmpause; 831 kstat_named_t cap_pause; 832 833 /* 834 * Link partner capabilities. 835 */ 836 kstat_named_t lp_cap_autoneg; 837 kstat_named_t lp_cap_10gfdx; 838 kstat_named_t lp_cap_10ghdx; 839 kstat_named_t lp_cap_1000fdx; 840 kstat_named_t lp_cap_1000hdx; 841 kstat_named_t lp_cap_100T4; 842 kstat_named_t lp_cap_100fdx; 843 kstat_named_t lp_cap_100hdx; 844 kstat_named_t lp_cap_10fdx; 845 kstat_named_t lp_cap_10hdx; 846 kstat_named_t lp_cap_asmpause; 847 kstat_named_t lp_cap_pause; 848 849 /* 850 * Shared link setup. 851 */ 852 kstat_named_t link_T4; 853 kstat_named_t link_speed; 854 kstat_named_t link_duplex; 855 kstat_named_t link_asmpause; 856 kstat_named_t link_pause; 857 kstat_named_t link_up; 858 859 /* 860 * Lets the user know the MTU currently in use by 861 * the physical MAC port. 862 */ 863 kstat_named_t mac_mtu; 864 kstat_named_t lb_mode; 865 kstat_named_t qos_mode; 866 kstat_named_t trunk_mode; 867 868 /* 869 * Misc MAC statistics. 870 */ 871 kstat_named_t ifspeed; 872 kstat_named_t promisc; 873 kstat_named_t rev_id; 874 875 /* 876 * Some statistics added to support bringup, these 877 * should be removed. 878 */ 879 kstat_named_t user_defined; 880 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 881 882 typedef struct _nxge_rdc_kstat { 883 /* 884 * Receive DMA channel statistics. 885 */ 886 kstat_named_t ipackets; 887 kstat_named_t rbytes; 888 kstat_named_t errors; 889 kstat_named_t dcf_err; 890 kstat_named_t rcr_ack_err; 891 892 kstat_named_t dc_fifoflow_err; 893 kstat_named_t rcr_sha_par_err; 894 kstat_named_t rbr_pre_par_err; 895 kstat_named_t wred_drop; 896 kstat_named_t rbr_pre_emty; 897 898 kstat_named_t rcr_shadow_full; 899 kstat_named_t rbr_tmout; 900 kstat_named_t rsp_cnt_err; 901 kstat_named_t byte_en_bus; 902 kstat_named_t rsp_dat_err; 903 904 kstat_named_t pkt_too_long_err; 905 kstat_named_t compl_l2_err; 906 kstat_named_t compl_l4_cksum_err; 907 kstat_named_t compl_zcp_soft_err; 908 kstat_named_t compl_fflp_soft_err; 909 kstat_named_t config_err; 910 911 kstat_named_t rcrincon; 912 kstat_named_t rcrfull; 913 kstat_named_t rbr_empty; 914 kstat_named_t rbrfull; 915 kstat_named_t rbrlogpage; 916 917 kstat_named_t cfiglogpage; 918 kstat_named_t port_drop_pkt; 919 kstat_named_t rcr_to; 920 kstat_named_t rcr_thresh; 921 kstat_named_t rcr_mex; 922 kstat_named_t id_mismatch; 923 kstat_named_t zcp_eop_err; 924 kstat_named_t ipp_eop_err; 925 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 926 927 typedef struct _nxge_rdc_sys_kstat { 928 /* 929 * Receive DMA system statistics. 930 */ 931 kstat_named_t pre_par; 932 kstat_named_t sha_par; 933 kstat_named_t id_mismatch; 934 kstat_named_t ipp_eop_err; 935 kstat_named_t zcp_eop_err; 936 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 937 938 typedef struct _nxge_tdc_kstat { 939 /* 940 * Transmit DMA channel statistics. 941 */ 942 kstat_named_t opackets; 943 kstat_named_t obytes; 944 kstat_named_t oerrors; 945 kstat_named_t tx_inits; 946 kstat_named_t tx_no_buf; 947 948 kstat_named_t mbox_err; 949 kstat_named_t pkt_size_err; 950 kstat_named_t tx_ring_oflow; 951 kstat_named_t pref_buf_ecc_err; 952 kstat_named_t nack_pref; 953 kstat_named_t nack_pkt_rd; 954 kstat_named_t conf_part_err; 955 kstat_named_t pkt_prt_err; 956 kstat_named_t reset_fail; 957 /* used to in the common (per port) counter */ 958 959 kstat_named_t tx_starts; 960 kstat_named_t tx_nocanput; 961 kstat_named_t tx_msgdup_fail; 962 kstat_named_t tx_allocb_fail; 963 kstat_named_t tx_no_desc; 964 kstat_named_t tx_dma_bind_fail; 965 kstat_named_t tx_uflo; 966 kstat_named_t tx_hdr_pkts; 967 kstat_named_t tx_ddi_pkts; 968 kstat_named_t tx_dvma_pkts; 969 kstat_named_t tx_max_pend; 970 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 971 972 typedef struct _nxge_txc_kstat { 973 /* 974 * Transmit port TXC block statistics. 975 */ 976 kstat_named_t pkt_stuffed; 977 kstat_named_t pkt_xmit; 978 kstat_named_t ro_correct_err; 979 kstat_named_t ro_uncorrect_err; 980 kstat_named_t sf_correct_err; 981 kstat_named_t sf_uncorrect_err; 982 kstat_named_t address_failed; 983 kstat_named_t dma_failed; 984 kstat_named_t length_failed; 985 kstat_named_t pkt_assy_dead; 986 kstat_named_t reorder_err; 987 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 988 989 typedef struct _nxge_ipp_kstat { 990 /* 991 * Receive port IPP block statistics. 992 */ 993 kstat_named_t eop_miss; 994 kstat_named_t sop_miss; 995 kstat_named_t dfifo_ue; 996 kstat_named_t ecc_err_cnt; 997 kstat_named_t pfifo_perr; 998 kstat_named_t pfifo_over; 999 kstat_named_t pfifo_und; 1000 kstat_named_t bad_cs_cnt; 1001 kstat_named_t pkt_dis_cnt; 1002 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 1003 1004 typedef struct _nxge_zcp_kstat { 1005 /* 1006 * ZCP statistics. 1007 */ 1008 kstat_named_t errors; 1009 kstat_named_t inits; 1010 kstat_named_t rrfifo_underrun; 1011 kstat_named_t rrfifo_overrun; 1012 kstat_named_t rspfifo_uncorr_err; 1013 kstat_named_t buffer_overflow; 1014 kstat_named_t stat_tbl_perr; 1015 kstat_named_t dyn_tbl_perr; 1016 kstat_named_t buf_tbl_perr; 1017 kstat_named_t tt_program_err; 1018 kstat_named_t rsp_tt_index_err; 1019 kstat_named_t slv_tt_index_err; 1020 kstat_named_t zcp_tt_index_err; 1021 kstat_named_t access_fail; 1022 kstat_named_t cfifo_ecc; 1023 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 1024 1025 typedef struct _nxge_mac_kstat { 1026 /* 1027 * Transmit MAC statistics. 1028 */ 1029 kstat_named_t tx_frame_cnt; 1030 kstat_named_t tx_underflow_err; 1031 kstat_named_t tx_overflow_err; 1032 kstat_named_t tx_maxpktsize_err; 1033 kstat_named_t tx_fifo_xfr_err; 1034 kstat_named_t tx_byte_cnt; 1035 1036 /* 1037 * Receive MAC statistics. 1038 */ 1039 kstat_named_t rx_frame_cnt; 1040 kstat_named_t rx_underflow_err; 1041 kstat_named_t rx_overflow_err; 1042 kstat_named_t rx_len_err_cnt; 1043 kstat_named_t rx_crc_err_cnt; 1044 kstat_named_t rx_viol_err_cnt; 1045 kstat_named_t rx_byte_cnt; 1046 kstat_named_t rx_hist1_cnt; 1047 kstat_named_t rx_hist2_cnt; 1048 kstat_named_t rx_hist3_cnt; 1049 kstat_named_t rx_hist4_cnt; 1050 kstat_named_t rx_hist5_cnt; 1051 kstat_named_t rx_hist6_cnt; 1052 kstat_named_t rx_hist7_cnt; 1053 kstat_named_t rx_broadcast_cnt; 1054 kstat_named_t rx_mult_cnt; 1055 kstat_named_t rx_frag_cnt; 1056 kstat_named_t rx_frame_align_err_cnt; 1057 kstat_named_t rx_linkfault_err_cnt; 1058 kstat_named_t rx_local_fault_err_cnt; 1059 kstat_named_t rx_remote_fault_err_cnt; 1060 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 1061 1062 typedef struct _nxge_xmac_kstat { 1063 /* 1064 * XMAC statistics. 1065 */ 1066 kstat_named_t tx_frame_cnt; 1067 kstat_named_t tx_underflow_err; 1068 kstat_named_t tx_maxpktsize_err; 1069 kstat_named_t tx_overflow_err; 1070 kstat_named_t tx_fifo_xfr_err; 1071 kstat_named_t tx_byte_cnt; 1072 kstat_named_t rx_frame_cnt; 1073 kstat_named_t rx_underflow_err; 1074 kstat_named_t rx_overflow_err; 1075 kstat_named_t rx_crc_err_cnt; 1076 kstat_named_t rx_len_err_cnt; 1077 kstat_named_t rx_viol_err_cnt; 1078 kstat_named_t rx_byte_cnt; 1079 kstat_named_t rx_hist1_cnt; 1080 kstat_named_t rx_hist2_cnt; 1081 kstat_named_t rx_hist3_cnt; 1082 kstat_named_t rx_hist4_cnt; 1083 kstat_named_t rx_hist5_cnt; 1084 kstat_named_t rx_hist6_cnt; 1085 kstat_named_t rx_hist7_cnt; 1086 kstat_named_t rx_broadcast_cnt; 1087 kstat_named_t rx_mult_cnt; 1088 kstat_named_t rx_frag_cnt; 1089 kstat_named_t rx_frame_align_err_cnt; 1090 kstat_named_t rx_linkfault_err_cnt; 1091 kstat_named_t rx_remote_fault_err_cnt; 1092 kstat_named_t rx_local_fault_err_cnt; 1093 kstat_named_t rx_pause_cnt; 1094 kstat_named_t xpcs_deskew_err_cnt; 1095 kstat_named_t xpcs_ln0_symbol_err_cnt; 1096 kstat_named_t xpcs_ln1_symbol_err_cnt; 1097 kstat_named_t xpcs_ln2_symbol_err_cnt; 1098 kstat_named_t xpcs_ln3_symbol_err_cnt; 1099 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 1100 1101 typedef struct _nxge_bmac_kstat { 1102 /* 1103 * BMAC statistics. 1104 */ 1105 kstat_named_t tx_frame_cnt; 1106 kstat_named_t tx_underrun_err; 1107 kstat_named_t tx_max_pkt_err; 1108 kstat_named_t tx_byte_cnt; 1109 kstat_named_t rx_frame_cnt; 1110 kstat_named_t rx_byte_cnt; 1111 kstat_named_t rx_overflow_err; 1112 kstat_named_t rx_align_err_cnt; 1113 kstat_named_t rx_crc_err_cnt; 1114 kstat_named_t rx_len_err_cnt; 1115 kstat_named_t rx_viol_err_cnt; 1116 kstat_named_t rx_pause_cnt; 1117 kstat_named_t tx_pause_state; 1118 kstat_named_t tx_nopause_state; 1119 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 1120 1121 1122 typedef struct _nxge_fflp_kstat { 1123 /* 1124 * FFLP statistics. 1125 */ 1126 1127 kstat_named_t fflp_tcam_perr; 1128 kstat_named_t fflp_tcam_ecc_err; 1129 kstat_named_t fflp_vlan_perr; 1130 kstat_named_t fflp_hasht_lookup_err; 1131 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 1132 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1133 1134 typedef struct _nxge_mmac_kstat { 1135 kstat_named_t mmac_max_addr_cnt; 1136 kstat_named_t mmac_avail_addr_cnt; 1137 kstat_named_t mmac_addr1; 1138 kstat_named_t mmac_addr2; 1139 kstat_named_t mmac_addr3; 1140 kstat_named_t mmac_addr4; 1141 kstat_named_t mmac_addr5; 1142 kstat_named_t mmac_addr6; 1143 kstat_named_t mmac_addr7; 1144 kstat_named_t mmac_addr8; 1145 kstat_named_t mmac_addr9; 1146 kstat_named_t mmac_addr10; 1147 kstat_named_t mmac_addr11; 1148 kstat_named_t mmac_addr12; 1149 kstat_named_t mmac_addr13; 1150 kstat_named_t mmac_addr14; 1151 kstat_named_t mmac_addr15; 1152 kstat_named_t mmac_addr16; 1153 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1154 1155 /* 1156 * Prototype definitions. 1157 */ 1158 nxge_status_t nxge_init(p_nxge_t); 1159 void nxge_uninit(p_nxge_t); 1160 void nxge_get64(p_nxge_t, p_mblk_t); 1161 void nxge_put64(p_nxge_t, p_mblk_t); 1162 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1163 1164 typedef void (*fptrv_t)(); 1165 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1166 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1167 1168 #ifdef __cplusplus 1169 } 1170 #endif 1171 1172 #endif /* _SYS_NXGE_NXGE_H */ 1173