1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_H 27 #define _SYS_NXGE_NXGE_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #if defined(_KERNEL) || defined(COSIM) 34 #include <nxge_mac.h> 35 #include <nxge_ipp.h> 36 #include <nxge_fflp.h> 37 #endif 38 39 /* 40 * NXGE diagnostics IOCTLS. 41 */ 42 #define NXGE_IOC ((((('N' << 8) + 'X') << 8) + 'G') << 8) 43 44 #define NXGE_GET64 (NXGE_IOC|1) 45 #define NXGE_PUT64 (NXGE_IOC|2) 46 #define NXGE_GET_TX_RING_SZ (NXGE_IOC|3) 47 #define NXGE_GET_TX_DESC (NXGE_IOC|4) 48 #define NXGE_GLOBAL_RESET (NXGE_IOC|5) 49 #define NXGE_TX_SIDE_RESET (NXGE_IOC|6) 50 #define NXGE_RX_SIDE_RESET (NXGE_IOC|7) 51 #define NXGE_RESET_MAC (NXGE_IOC|8) 52 53 #define NXGE_GET_MII (NXGE_IOC|11) 54 #define NXGE_PUT_MII (NXGE_IOC|12) 55 #define NXGE_RTRACE (NXGE_IOC|13) 56 #define NXGE_RTRACE_TEST (NXGE_IOC|20) 57 #define NXGE_TX_REGS_DUMP (NXGE_IOC|21) 58 #define NXGE_RX_REGS_DUMP (NXGE_IOC|22) 59 #define NXGE_INT_REGS_DUMP (NXGE_IOC|23) 60 #define NXGE_VIR_REGS_DUMP (NXGE_IOC|24) 61 #define NXGE_VIR_INT_REGS_DUMP (NXGE_IOC|25) 62 #define NXGE_RDUMP (NXGE_IOC|26) 63 #define NXGE_RDC_GRPS_DUMP (NXGE_IOC|27) 64 #define NXGE_PIO_TEST (NXGE_IOC|28) 65 66 #define NXGE_GET_TCAM (NXGE_IOC|29) 67 #define NXGE_PUT_TCAM (NXGE_IOC|30) 68 #define NXGE_INJECT_ERR (NXGE_IOC|40) 69 70 #if (defined(SOLARIS) && defined(_KERNEL)) || defined(COSIM) 71 #define NXGE_OK 0 72 #define NXGE_ERROR 0x40000000 73 #define NXGE_DDI_FAILED 0x20000000 74 #define NXGE_GET_PORT_NUM(n) n 75 76 /* 77 * Definitions for module_info. 78 */ 79 #define NXGE_IDNUM (0) /* module ID number */ 80 #define NXGE_DRIVER_NAME "nxge" /* module name */ 81 82 #define NXGE_MINPSZ (0) /* min packet size */ 83 #define NXGE_MAXPSZ (ETHERMTU) /* max packet size */ 84 #define NXGE_HIWAT (2048 * NXGE_MAXPSZ) /* hi-water mark */ 85 #define NXGE_LOWAT (1) /* lo-water mark */ 86 #define NXGE_HIWAT_MAX (192000 * NXGE_MAXPSZ) 87 #define NXGE_HIWAT_MIN (2 * NXGE_MAXPSZ) 88 #define NXGE_LOWAT_MAX (192000 * NXGE_MAXPSZ) 89 #define NXGE_LOWAT_MIN (1) 90 91 #ifndef D_HOTPLUG 92 #define D_HOTPLUG 0x00 93 #endif 94 95 #define INIT_BUCKET_SIZE 16 /* Initial Hash Bucket Size */ 96 97 #define NXGE_CHECK_TIMER (5000) 98 99 typedef enum { 100 param_instance, 101 param_main_instance, 102 param_function_number, 103 param_partition_id, 104 param_read_write_mode, 105 param_fw_version, 106 param_port_mode, 107 param_niu_cfg_type, 108 param_tx_quick_cfg, 109 param_rx_quick_cfg, 110 param_master_cfg_enable, 111 param_master_cfg_value, 112 113 param_autoneg, 114 param_anar_10gfdx, 115 param_anar_10ghdx, 116 param_anar_1000fdx, 117 param_anar_1000hdx, 118 param_anar_100T4, 119 param_anar_100fdx, 120 param_anar_100hdx, 121 param_anar_10fdx, 122 param_anar_10hdx, 123 124 param_anar_asmpause, 125 param_anar_pause, 126 param_use_int_xcvr, 127 param_enable_ipg0, 128 param_ipg0, 129 param_ipg1, 130 param_ipg2, 131 param_accept_jumbo, 132 param_txdma_weight, 133 param_txdma_channels_begin, 134 135 param_txdma_channels, 136 param_txdma_info, 137 param_rxdma_channels_begin, 138 param_rxdma_channels, 139 param_rxdma_drr_weight, 140 param_rxdma_full_header, 141 param_rxdma_info, 142 param_rxdma_rbr_size, 143 param_rxdma_rcr_size, 144 param_default_port_rdc, 145 param_rxdma_intr_time, 146 param_rxdma_intr_pkts, 147 148 param_rdc_grps_start, 149 param_rx_rdc_grps, 150 param_default_grp0_rdc, 151 param_default_grp1_rdc, 152 param_default_grp2_rdc, 153 param_default_grp3_rdc, 154 param_default_grp4_rdc, 155 param_default_grp5_rdc, 156 param_default_grp6_rdc, 157 param_default_grp7_rdc, 158 159 param_info_rdc_groups, 160 param_start_ldg, 161 param_max_ldg, 162 param_mac_2rdc_grp, 163 param_vlan_2rdc_grp, 164 param_fcram_part_cfg, 165 param_fcram_access_ratio, 166 param_tcam_access_ratio, 167 param_tcam_enable, 168 param_hash_lookup_enable, 169 param_llc_snap_enable, 170 171 param_h1_init_value, 172 param_h2_init_value, 173 param_class_cfg_ether_usr1, 174 param_class_cfg_ether_usr2, 175 param_class_cfg_ip_usr4, 176 param_class_cfg_ip_usr5, 177 param_class_cfg_ip_usr6, 178 param_class_cfg_ip_usr7, 179 param_class_opt_ip_usr4, 180 param_class_opt_ip_usr5, 181 param_class_opt_ip_usr6, 182 param_class_opt_ip_usr7, 183 param_class_opt_ipv4_tcp, 184 param_class_opt_ipv4_udp, 185 param_class_opt_ipv4_ah, 186 param_class_opt_ipv4_sctp, 187 param_class_opt_ipv6_tcp, 188 param_class_opt_ipv6_udp, 189 param_class_opt_ipv6_ah, 190 param_class_opt_ipv6_sctp, 191 param_nxge_debug_flag, 192 param_npi_debug_flag, 193 param_dump_rdc, 194 param_dump_tdc, 195 param_dump_mac_regs, 196 param_dump_ipp_regs, 197 param_dump_fflp_regs, 198 param_dump_vlan_table, 199 param_dump_rdc_table, 200 param_dump_ptrs, 201 param_end 202 } nxge_param_index_t; 203 204 typedef enum { 205 SOLARIS_DOMAIN, 206 SOLARIS_SERVICE_DOMAIN, 207 SOLARIS_GUEST_DOMAIN, 208 LINUX_SERVICE_DOMAIN, 209 LINUX_GUEST_DOMAIN 210 } nxge_environs_t; 211 212 /* 213 * Named Dispatch Parameter Management Structure 214 */ 215 typedef int (*nxge_ndgetf_t)(p_nxge_t, queue_t *, MBLKP, caddr_t, cred_t *); 216 typedef int (*nxge_ndsetf_t)(p_nxge_t, queue_t *, 217 MBLKP, char *, caddr_t, cred_t *); 218 219 #define NXGE_PARAM_READ 0x00000001ULL 220 #define NXGE_PARAM_WRITE 0x00000002ULL 221 #define NXGE_PARAM_SHARED 0x00000004ULL 222 #define NXGE_PARAM_PRIV 0x00000008ULL 223 #define NXGE_PARAM_RW NXGE_PARAM_READ | NXGE_PARAM_WRITE 224 #define NXGE_PARAM_RWS NXGE_PARAM_RW | NXGE_PARAM_SHARED 225 #define NXGE_PARAM_RWP NXGE_PARAM_RW | NXGE_PARAM_PRIV 226 227 #define NXGE_PARAM_RXDMA 0x00000010ULL 228 #define NXGE_PARAM_TXDMA 0x00000020ULL 229 #define NXGE_PARAM_CLASS_GEN 0x00000040ULL 230 #define NXGE_PARAM_MAC 0x00000080ULL 231 #define NXGE_PARAM_CLASS_BIN NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_BIN 232 #define NXGE_PARAM_CLASS_HEX NXGE_PARAM_CLASS_GEN | NXGE_PARAM_BASE_HEX 233 #define NXGE_PARAM_CLASS NXGE_PARAM_CLASS_HEX 234 235 #define NXGE_PARAM_CMPLX 0x00010000ULL 236 #define NXGE_PARAM_NDD_WR_OK 0x00020000ULL 237 #define NXGE_PARAM_INIT_ONLY 0x00040000ULL 238 #define NXGE_PARAM_INIT_CONFIG 0x00080000ULL 239 240 #define NXGE_PARAM_READ_PROP 0x00100000ULL 241 #define NXGE_PARAM_PROP_ARR32 0x00200000ULL 242 #define NXGE_PARAM_PROP_ARR64 0x00400000ULL 243 #define NXGE_PARAM_PROP_STR 0x00800000ULL 244 245 #define NXGE_PARAM_BASE_DEC 0x00000000ULL 246 #define NXGE_PARAM_BASE_BIN 0x10000000ULL 247 #define NXGE_PARAM_BASE_HEX 0x20000000ULL 248 #define NXGE_PARAM_BASE_STR 0x40000000ULL 249 #define NXGE_PARAM_DONT_SHOW 0x80000000ULL 250 251 #define NXGE_PARAM_ARRAY_CNT_MASK 0x0000ffff00000000ULL 252 #define NXGE_PARAM_ARRAY_CNT_SHIFT 32ULL 253 #define NXGE_PARAM_ARRAY_ALLOC_MASK 0xffff000000000000ULL 254 #define NXGE_PARAM_ARRAY_ALLOC_SHIFT 48ULL 255 256 typedef struct _nxge_param_t { 257 int (*getf)(); 258 int (*setf)(); /* null for read only */ 259 uint64_t type; /* R/W/ Common/Port/ .... */ 260 uint64_t minimum; 261 uint64_t maximum; 262 uint64_t value; /* for array params, pointer to value array */ 263 uint64_t old_value; /* for array params, pointer to old_value array */ 264 char *fcode_name; 265 char *name; 266 } nxge_param_t, *p_nxge_param_t; 267 268 269 /* 270 * Do not change the order of the elements of this enum as that will 271 * break the driver code. 272 */ 273 typedef enum { 274 nxge_lb_normal, 275 nxge_lb_ext10g, 276 nxge_lb_ext1000, 277 nxge_lb_ext100, 278 nxge_lb_ext10, 279 nxge_lb_phy10g, 280 nxge_lb_phy1000, 281 nxge_lb_phy, 282 nxge_lb_serdes10g, 283 nxge_lb_serdes1000, 284 nxge_lb_serdes, 285 nxge_lb_mac10g, 286 nxge_lb_mac1000, 287 nxge_lb_mac 288 } nxge_lb_t; 289 290 enum nxge_mac_state { 291 NXGE_MAC_STOPPED = 0, 292 NXGE_MAC_STARTED, 293 NXGE_MAC_STOPPING 294 }; 295 296 /* 297 * Private DLPI full dlsap address format. 298 */ 299 typedef struct _nxge_dladdr_t { 300 ether_addr_st dl_phys; 301 uint16_t dl_sap; 302 } nxge_dladdr_t, *p_nxge_dladdr_t; 303 304 typedef struct _mc_addr_t { 305 ether_addr_st multcast_addr; 306 uint_t mc_addr_cnt; 307 } mc_addr_t, *p_mc_addr_t; 308 309 typedef struct _mc_bucket_t { 310 p_mc_addr_t addr_list; 311 uint_t list_size; 312 } mc_bucket_t, *p_mc_bucket_t; 313 314 typedef struct _mc_table_t { 315 p_mc_bucket_t bucket_list; 316 uint_t buckets_used; 317 } mc_table_t, *p_mc_table_t; 318 319 typedef struct _filter_t { 320 uint32_t all_phys_cnt; 321 uint32_t all_multicast_cnt; 322 uint32_t all_sap_cnt; 323 } filter_t, *p_filter_t; 324 325 #if defined(_KERNEL) || defined(COSIM) 326 327 328 typedef struct _nxge_port_stats_t { 329 /* 330 * Overall structure size 331 */ 332 size_t stats_size; 333 334 /* 335 * Link Input/Output stats 336 */ 337 uint64_t ipackets; 338 uint64_t ierrors; 339 uint64_t opackets; 340 uint64_t oerrors; 341 uint64_t collisions; 342 343 /* 344 * MIB II variables 345 */ 346 uint64_t rbytes; /* # bytes received */ 347 uint64_t obytes; /* # bytes transmitted */ 348 uint32_t multircv; /* # multicast packets received */ 349 uint32_t multixmt; /* # multicast packets for xmit */ 350 uint32_t brdcstrcv; /* # broadcast packets received */ 351 uint32_t brdcstxmt; /* # broadcast packets for xmit */ 352 uint32_t norcvbuf; /* # rcv packets discarded */ 353 uint32_t noxmtbuf; /* # xmit packets discarded */ 354 355 /* 356 * Lets the user know the MTU currently in use by 357 * the physical MAC port. 358 */ 359 nxge_lb_t lb_mode; 360 uint32_t qos_mode; 361 uint32_t trunk_mode; 362 uint32_t poll_mode; 363 364 /* 365 * Tx Statistics. 366 */ 367 uint32_t tx_inits; 368 uint32_t tx_starts; 369 uint32_t tx_nocanput; 370 uint32_t tx_msgdup_fail; 371 uint32_t tx_allocb_fail; 372 uint32_t tx_no_desc; 373 uint32_t tx_dma_bind_fail; 374 uint32_t tx_uflo; 375 uint32_t tx_hdr_pkts; 376 uint32_t tx_ddi_pkts; 377 uint32_t tx_dvma_pkts; 378 379 uint32_t tx_max_pend; 380 381 /* 382 * Rx Statistics. 383 */ 384 uint32_t rx_inits; 385 uint32_t rx_hdr_pkts; 386 uint32_t rx_mtu_pkts; 387 uint32_t rx_split_pkts; 388 uint32_t rx_no_buf; 389 uint32_t rx_no_comp_wb; 390 uint32_t rx_ov_flow; 391 uint32_t rx_len_mm; 392 uint32_t rx_tag_err; 393 uint32_t rx_nocanput; 394 uint32_t rx_msgdup_fail; 395 uint32_t rx_allocb_fail; 396 397 /* 398 * Receive buffer management statistics. 399 */ 400 uint32_t rx_new_pages; 401 uint32_t rx_new_hdr_pgs; 402 uint32_t rx_new_mtu_pgs; 403 uint32_t rx_new_nxt_pgs; 404 uint32_t rx_reused_pgs; 405 uint32_t rx_hdr_drops; 406 uint32_t rx_mtu_drops; 407 uint32_t rx_nxt_drops; 408 409 /* 410 * Receive flow statistics 411 */ 412 uint32_t rx_rel_flow; 413 uint32_t rx_rel_bit; 414 415 uint32_t rx_pkts_dropped; 416 417 /* 418 * PCI-E Bus Statistics. 419 */ 420 uint32_t pci_bus_speed; 421 uint32_t pci_err; 422 uint32_t pci_rta_err; 423 uint32_t pci_rma_err; 424 uint32_t pci_parity_err; 425 uint32_t pci_bad_ack_err; 426 uint32_t pci_drto_err; 427 uint32_t pci_dmawz_err; 428 uint32_t pci_dmarz_err; 429 430 uint32_t rx_taskq_waits; 431 432 uint32_t tx_jumbo_pkts; 433 434 /* 435 * Some statistics added to support bringup, these 436 * should be removed. 437 */ 438 uint32_t user_defined; 439 } nxge_port_stats_t, *p_nxge_port_stats_t; 440 441 442 typedef struct _nxge_stats_t { 443 /* 444 * Overall structure size 445 */ 446 size_t stats_size; 447 448 kstat_t *ksp; 449 kstat_t *rdc_ksp[NXGE_MAX_RDCS]; 450 kstat_t *tdc_ksp[NXGE_MAX_TDCS]; 451 kstat_t *rdc_sys_ksp; 452 kstat_t *fflp_ksp[1]; 453 kstat_t *ipp_ksp; 454 kstat_t *txc_ksp; 455 kstat_t *mac_ksp; 456 kstat_t *zcp_ksp; 457 kstat_t *port_ksp; 458 kstat_t *mmac_ksp; 459 460 nxge_mac_stats_t mac_stats; /* Common MAC Statistics */ 461 nxge_xmac_stats_t xmac_stats; /* XMAC Statistics */ 462 nxge_bmac_stats_t bmac_stats; /* BMAC Statistics */ 463 464 nxge_rx_ring_stats_t rx_stats; /* per port RX stats */ 465 nxge_ipp_stats_t ipp_stats; /* per port IPP stats */ 466 nxge_zcp_stats_t zcp_stats; /* per port IPP stats */ 467 nxge_rx_ring_stats_t rdc_stats[NXGE_MAX_RDCS]; /* per rdc stats */ 468 nxge_rdc_sys_stats_t rdc_sys_stats; /* per port RDC stats */ 469 470 nxge_tx_ring_stats_t tx_stats; /* per port TX stats */ 471 nxge_txc_stats_t txc_stats; /* per port TX stats */ 472 nxge_tx_ring_stats_t tdc_stats[NXGE_MAX_TDCS]; /* per tdc stats */ 473 nxge_fflp_stats_t fflp_stats; /* fflp stats */ 474 nxge_port_stats_t port_stats; /* fflp stats */ 475 nxge_mmac_stats_t mmac_stats; /* Multi mac. stats */ 476 477 } nxge_stats_t, *p_nxge_stats_t; 478 479 480 481 typedef struct _nxge_intr_t { 482 boolean_t intr_registered; /* interrupts are registered */ 483 boolean_t intr_enabled; /* interrupts are enabled */ 484 boolean_t niu_msi_enable; /* debug or configurable? */ 485 int intr_types; /* interrupt types supported */ 486 int intr_type; /* interrupt type to add */ 487 int max_int_cnt; /* max MSIX/INT HW supports */ 488 int start_inum; /* start inum (in sequence?) */ 489 int msi_intx_cnt; /* # msi/intx ints returned */ 490 int intr_added; /* # ints actually needed */ 491 int intr_cap; /* interrupt capabilities */ 492 size_t intr_size; /* size of array to allocate */ 493 ddi_intr_handle_t *htable; /* For array of interrupts */ 494 /* Add interrupt number for each interrupt vector */ 495 int pri; 496 } nxge_intr_t, *p_nxge_intr_t; 497 498 typedef struct _nxge_ldgv_t { 499 uint8_t ndma_ldvs; 500 uint8_t nldvs; 501 uint8_t maxldgs; 502 uint8_t maxldvs; 503 uint8_t ldg_intrs; 504 boolean_t own_sys_err; 505 boolean_t own_max_ldv; 506 uint32_t tmres; 507 p_nxge_ldg_t ldgp; 508 p_nxge_ldv_t ldvp; 509 p_nxge_ldv_t ldvp_syserr; 510 int ldvp_syserr_allocated; 511 } nxge_ldgv_t, *p_nxge_ldgv_t; 512 513 typedef enum { 514 NXGE_TRANSMIT_GROUP, /* Legacy transmit group */ 515 NXGE_RECEIVE_GROUP, /* Legacy receive group */ 516 NXGE_VR_GROUP, /* Virtualization Region group */ 517 EXT_TRANSMIT_GROUP, /* External (Crossbow) transmit group */ 518 EXT_RECEIVE_GROUP /* External (Crossbow) receive group */ 519 } nxge_grp_type_t; 520 521 #define NXGE_ILLEGAL_CHANNEL (NXGE_MAX_TDCS + 1) 522 523 typedef uint8_t nxge_channel_t; 524 525 typedef struct nxge_grp { 526 nxge_t *nxge; 527 nxge_grp_type_t type; /* Tx or Rx */ 528 529 int sequence; /* When it was created. */ 530 int index; /* nxge_grp_set_t.group[index] */ 531 532 struct nx_dc *dc; /* Linked list of DMA channels. */ 533 size_t count; /* A count of <dc> above. */ 534 535 boolean_t active; /* Is it being used? */ 536 537 dc_map_t map; /* A bitmap of the channels in <dc>. */ 538 nxge_channel_t legend[NXGE_MAX_TDCS]; 539 540 } nxge_grp_t; 541 542 typedef struct { 543 lg_map_t map; 544 size_t count; 545 } lg_data_t; 546 547 typedef struct { 548 dc_map_t map; 549 size_t count; 550 } dc_data_t; 551 552 #define NXGE_DC_SET(map, channel) map |= (1 << channel) 553 #define NXGE_DC_RESET(map, channel) map &= (~(1 << channel)) 554 555 #define NXGE_LOGICAL_GROUP_MAX NXGE_MAX_TDCS 556 557 typedef struct { 558 int sequence; /* To order groups in time. */ 559 560 /* These are this instance's logical groups. */ 561 nxge_grp_t *group[NXGE_LOGICAL_GROUP_MAX]; 562 lg_data_t lg; 563 564 dc_data_t shared; /* These DCs are being shared. */ 565 dc_data_t owned; /* These DCs belong to me. */ 566 dc_data_t dead; /* These DCs are in an error state. */ 567 568 } nxge_grp_set_t; 569 570 /* 571 * Receive Ring Group 572 * One of the advanced virtualization features is the ability to bundle 573 * multiple Receive Rings in a single group. One or more MAC addresses may 574 * be assigned to a group. Incoming packets destined to the group's MAC 575 * address(es) are delivered to any ring member, according to a programmable 576 * or predefined RTS policy. Member rings can be polled individually. 577 * RX ring groups can come with a predefined set of member rings, or they 578 * are programmable by adding and removing rings to/from them. 579 */ 580 typedef struct _nxge_rx_ring_group_t { 581 mac_group_handle_t ghandle; 582 p_nxge_t nxgep; 583 int gindex; 584 int sindex; 585 } nxge_rx_ring_group_t; 586 587 /* 588 * Ring Handle 589 */ 590 typedef struct _nxge_ring_handle_t { 591 p_nxge_t nxgep; 592 int index; /* port-wise */ 593 mac_ring_handle_t ring_handle; 594 } nxge_ring_handle_t; 595 596 /* 597 * Share Handle 598 */ 599 typedef struct _nxge_share_handle_t { 600 p_nxge_t nxgep; /* Driver Handle */ 601 int index; 602 void *vrp; 603 uint64_t tmap; 604 uint64_t rmap; 605 int rxgroup; 606 boolean_t active; 607 } nxge_share_handle_t; 608 609 /* 610 * Neptune Device instance state information. 611 * 612 * Each instance is dynamically allocated on first attach. 613 */ 614 struct _nxge_t { 615 dev_info_t *dip; /* device instance */ 616 dev_info_t *p_dip; /* Parent's device instance */ 617 int instance; /* instance number */ 618 int function_num; /* device function number */ 619 int nports; /* # of ports on this device */ 620 int board_ver; /* Board Version */ 621 int partition_id; /* partition ID */ 622 int use_partition; /* partition is enabled */ 623 uint32_t drv_state; /* driver state bit flags */ 624 uint64_t nxge_debug_level; /* driver state bit flags */ 625 kmutex_t genlock[1]; 626 enum nxge_mac_state nxge_mac_state; 627 ddi_softintr_t resched_id; /* reschedule callback */ 628 boolean_t resched_needed; 629 boolean_t resched_running; 630 631 p_dev_regs_t dev_regs; 632 npi_handle_t npi_handle; 633 npi_handle_t npi_pci_handle; 634 npi_handle_t npi_reg_handle; 635 npi_handle_t npi_msi_handle; 636 npi_handle_t npi_vreg_handle; 637 npi_handle_t npi_v2reg_handle; 638 639 nxge_xcvr_table_t xcvr; 640 boolean_t hot_swappable_phy; 641 boolean_t phy_absent; 642 uint32_t xcvr_addr; 643 uint16_t chip_id; 644 nxge_mac_t mac; 645 nxge_ipp_t ipp; 646 nxge_txc_t txc; 647 nxge_classify_t classifier; 648 649 mac_handle_t mach; /* mac module handle */ 650 p_nxge_stats_t statsp; 651 uint32_t param_count; 652 p_nxge_param_t param_arr; 653 654 uint32_t param_en_pause:1, 655 param_en_asym_pause:1, 656 param_en_1000fdx:1, 657 param_en_100fdx:1, 658 param_en_10fdx:1, 659 param_pad_to_32:27; 660 661 nxge_hw_list_t *nxge_hw_p; /* pointer to per Neptune */ 662 niu_type_t niu_type; 663 platform_type_t platform_type; 664 boolean_t os_addr_mode32; /* set to 1 for 32 bit mode */ 665 666 uint8_t def_rdc; 667 668 nxge_intr_t nxge_intr_type; 669 nxge_dma_pt_cfg_t pt_config; 670 nxge_class_pt_cfg_t class_config; 671 672 /* Logical device and group data structures. */ 673 p_nxge_ldgv_t ldgvp; 674 675 npi_vpd_info_t vpd_info; 676 caddr_t param_list; /* Parameter list */ 677 678 ether_addr_st factaddr; /* factory mac address */ 679 ether_addr_st ouraddr; /* individual address */ 680 kmutex_t ouraddr_lock; /* lock to protect to uradd */ 681 682 ddi_iblock_cookie_t interrupt_cookie; 683 684 /* 685 * Blocks of memory may be pre-allocated by the 686 * partition manager or the driver. They may include 687 * blocks for configuration and buffers. The idea is 688 * to preallocate big blocks of contiguous areas in 689 * system memory (i.e. with IOMMU). These blocks then 690 * will be broken up to a fixed number of blocks with 691 * each block having the same block size (4K, 8K, 16K or 692 * 32K) in the case of buffer blocks. For systems that 693 * do not support DVMA, more than one big block will be 694 * allocated. 695 */ 696 uint32_t rx_default_block_size; 697 nxge_rx_block_size_t rx_bksize_code; 698 699 p_nxge_dma_pool_t rx_buf_pool_p; 700 p_nxge_dma_pool_t rx_cntl_pool_p; 701 702 p_nxge_dma_pool_t tx_buf_pool_p; 703 p_nxge_dma_pool_t tx_cntl_pool_p; 704 705 /* Receive buffer block ring and completion ring. */ 706 p_rx_rbr_rings_t rx_rbr_rings; 707 p_rx_rcr_rings_t rx_rcr_rings; 708 p_rx_mbox_areas_t rx_mbox_areas_p; 709 710 p_rx_tx_params_t rx_params; 711 uint32_t start_rdc; 712 uint32_t max_rdcs; 713 uint32_t rdc_mask; 714 715 /* Transmit descriptors rings */ 716 p_tx_rings_t tx_rings; 717 p_tx_mbox_areas_t tx_mbox_areas_p; 718 719 uint32_t start_tdc; 720 uint32_t max_tdcs; 721 722 p_rx_tx_params_t tx_params; 723 724 ddi_dma_handle_t dmasparehandle; 725 726 ulong_t sys_page_sz; 727 ulong_t sys_page_mask; 728 int suspended; 729 730 mii_bmsr_t bmsr; /* xcvr status at last poll. */ 731 mii_bmsr_t soft_bmsr; /* xcvr status kept by SW. */ 732 733 kmutex_t mif_lock; /* Lock to protect the list. */ 734 735 void (*mii_read)(); 736 void (*mii_write)(); 737 void (*mii_poll)(); 738 filter_t filter; /* Current instance filter */ 739 p_hash_filter_t hash_filter; /* Multicast hash filter. */ 740 krwlock_t filter_lock; /* Lock to protect filters. */ 741 742 ulong_t sys_burst_sz; 743 744 uint8_t cache_line; 745 746 timeout_id_t nxge_link_poll_timerid; 747 timeout_id_t nxge_timerid; 748 749 uint_t need_periodic_reclaim; 750 timeout_id_t reclaim_timer; 751 752 uint8_t msg_min; 753 uint8_t crc_size; 754 755 boolean_t hard_props_read; 756 757 boolean_t nxge_htraffic; 758 uint32_t nxge_ncpus; 759 uint32_t nxge_cpumask; 760 uint16_t intr_timeout; 761 uint16_t intr_threshold; 762 uchar_t nxge_rxmode; 763 uint32_t active_threads; 764 765 rtrace_t rtrace; 766 int fm_capabilities; /* FMA capabilities */ 767 768 uint32_t nxge_port_rbr_size; 769 uint32_t nxge_port_rbr_spare_size; 770 uint32_t nxge_port_rcr_size; 771 uint32_t nxge_port_rx_cntl_alloc_size; 772 uint32_t nxge_port_tx_ring_size; 773 nxge_mmac_t nxge_mmac_info; 774 #if defined(sun4v) 775 boolean_t niu_hsvc_available; 776 hsvc_info_t niu_hsvc; 777 uint64_t niu_min_ver; 778 #endif 779 boolean_t link_notify; 780 781 kmutex_t poll_lock; 782 kcondvar_t poll_cv; 783 link_mon_enable_t poll_state; 784 #define NXGE_MAGIC 0x3ab434e3 785 uint32_t nxge_magic; 786 787 int soft_lso_enable; 788 /* The following fields are LDOMs-specific additions. */ 789 nxge_environs_t environs; 790 ether_addr_t hio_mac_addr; 791 uint32_t niu_cfg_hdl; 792 kmutex_t group_lock; 793 794 struct nxge_hio_vr *hio_vr; 795 796 nxge_grp_set_t rx_set; 797 nxge_grp_set_t tx_set; 798 799 nxge_rx_ring_group_t rx_hio_groups[NXGE_MAX_RDC_GROUPS]; 800 nxge_share_handle_t shares[NXGE_MAX_VRS]; 801 }; 802 803 /* 804 * Driver state flags. 805 */ 806 #define STATE_REGS_MAPPED 0x000000001 /* device registers mapped */ 807 #define STATE_KSTATS_SETUP 0x000000002 /* kstats allocated */ 808 #define STATE_NODE_CREATED 0x000000004 /* device node created */ 809 #define STATE_HW_CONFIG_CREATED 0x000000008 /* hardware properties */ 810 #define STATE_HW_INITIALIZED 0x000000010 /* hardware initialized */ 811 #define STATE_MDIO_LOCK_INIT 0x000000020 /* mdio lock initialized */ 812 #define STATE_MII_LOCK_INIT 0x000000040 /* mii lock initialized */ 813 814 #define STOP_POLL_THRESH 9 815 #define START_POLL_THRESH 2 816 817 typedef struct _nxge_port_kstat_t { 818 /* 819 * Transciever state informations. 820 */ 821 kstat_named_t xcvr_inits; 822 kstat_named_t xcvr_inuse; 823 kstat_named_t xcvr_addr; 824 kstat_named_t xcvr_id; 825 kstat_named_t cap_autoneg; 826 kstat_named_t cap_10gfdx; 827 kstat_named_t cap_10ghdx; 828 kstat_named_t cap_1000fdx; 829 kstat_named_t cap_1000hdx; 830 kstat_named_t cap_100T4; 831 kstat_named_t cap_100fdx; 832 kstat_named_t cap_100hdx; 833 kstat_named_t cap_10fdx; 834 kstat_named_t cap_10hdx; 835 kstat_named_t cap_asmpause; 836 kstat_named_t cap_pause; 837 838 /* 839 * Link partner capabilities. 840 */ 841 kstat_named_t lp_cap_autoneg; 842 kstat_named_t lp_cap_10gfdx; 843 kstat_named_t lp_cap_10ghdx; 844 kstat_named_t lp_cap_1000fdx; 845 kstat_named_t lp_cap_1000hdx; 846 kstat_named_t lp_cap_100T4; 847 kstat_named_t lp_cap_100fdx; 848 kstat_named_t lp_cap_100hdx; 849 kstat_named_t lp_cap_10fdx; 850 kstat_named_t lp_cap_10hdx; 851 kstat_named_t lp_cap_asmpause; 852 kstat_named_t lp_cap_pause; 853 854 /* 855 * Shared link setup. 856 */ 857 kstat_named_t link_T4; 858 kstat_named_t link_speed; 859 kstat_named_t link_duplex; 860 kstat_named_t link_asmpause; 861 kstat_named_t link_pause; 862 kstat_named_t link_up; 863 864 /* 865 * Lets the user know the MTU currently in use by 866 * the physical MAC port. 867 */ 868 kstat_named_t mac_mtu; 869 kstat_named_t lb_mode; 870 kstat_named_t qos_mode; 871 kstat_named_t trunk_mode; 872 873 /* 874 * Misc MAC statistics. 875 */ 876 kstat_named_t ifspeed; 877 kstat_named_t promisc; 878 kstat_named_t rev_id; 879 880 /* 881 * Some statistics added to support bringup, these 882 * should be removed. 883 */ 884 kstat_named_t user_defined; 885 } nxge_port_kstat_t, *p_nxge_port_kstat_t; 886 887 typedef struct _nxge_rdc_kstat { 888 /* 889 * Receive DMA channel statistics. 890 */ 891 kstat_named_t ipackets; 892 kstat_named_t rbytes; 893 kstat_named_t errors; 894 kstat_named_t dcf_err; 895 kstat_named_t rcr_ack_err; 896 897 kstat_named_t dc_fifoflow_err; 898 kstat_named_t rcr_sha_par_err; 899 kstat_named_t rbr_pre_par_err; 900 kstat_named_t wred_drop; 901 kstat_named_t rbr_pre_emty; 902 903 kstat_named_t rcr_shadow_full; 904 kstat_named_t rbr_tmout; 905 kstat_named_t rsp_cnt_err; 906 kstat_named_t byte_en_bus; 907 kstat_named_t rsp_dat_err; 908 909 kstat_named_t pkt_too_long_err; 910 kstat_named_t compl_l2_err; 911 kstat_named_t compl_l4_cksum_err; 912 kstat_named_t compl_zcp_soft_err; 913 kstat_named_t compl_fflp_soft_err; 914 kstat_named_t config_err; 915 916 kstat_named_t rcrincon; 917 kstat_named_t rcrfull; 918 kstat_named_t rbr_empty; 919 kstat_named_t rbrfull; 920 kstat_named_t rbrlogpage; 921 922 kstat_named_t cfiglogpage; 923 kstat_named_t port_drop_pkt; 924 kstat_named_t rcr_to; 925 kstat_named_t rcr_thresh; 926 kstat_named_t rcr_mex; 927 kstat_named_t id_mismatch; 928 kstat_named_t zcp_eop_err; 929 kstat_named_t ipp_eop_err; 930 } nxge_rdc_kstat_t, *p_nxge_rdc_kstat_t; 931 932 typedef struct _nxge_rdc_sys_kstat { 933 /* 934 * Receive DMA system statistics. 935 */ 936 kstat_named_t pre_par; 937 kstat_named_t sha_par; 938 kstat_named_t id_mismatch; 939 kstat_named_t ipp_eop_err; 940 kstat_named_t zcp_eop_err; 941 } nxge_rdc_sys_kstat_t, *p_nxge_rdc_sys_kstat_t; 942 943 typedef struct _nxge_tdc_kstat { 944 /* 945 * Transmit DMA channel statistics. 946 */ 947 kstat_named_t opackets; 948 kstat_named_t obytes; 949 kstat_named_t oerrors; 950 kstat_named_t tx_inits; 951 kstat_named_t tx_no_buf; 952 953 kstat_named_t mbox_err; 954 kstat_named_t pkt_size_err; 955 kstat_named_t tx_ring_oflow; 956 kstat_named_t pref_buf_ecc_err; 957 kstat_named_t nack_pref; 958 kstat_named_t nack_pkt_rd; 959 kstat_named_t conf_part_err; 960 kstat_named_t pkt_prt_err; 961 kstat_named_t reset_fail; 962 /* used to in the common (per port) counter */ 963 964 kstat_named_t tx_starts; 965 kstat_named_t tx_nocanput; 966 kstat_named_t tx_msgdup_fail; 967 kstat_named_t tx_allocb_fail; 968 kstat_named_t tx_no_desc; 969 kstat_named_t tx_dma_bind_fail; 970 kstat_named_t tx_uflo; 971 kstat_named_t tx_hdr_pkts; 972 kstat_named_t tx_ddi_pkts; 973 kstat_named_t tx_dvma_pkts; 974 kstat_named_t tx_max_pend; 975 } nxge_tdc_kstat_t, *p_nxge_tdc_kstat_t; 976 977 typedef struct _nxge_txc_kstat { 978 /* 979 * Transmit port TXC block statistics. 980 */ 981 kstat_named_t pkt_stuffed; 982 kstat_named_t pkt_xmit; 983 kstat_named_t ro_correct_err; 984 kstat_named_t ro_uncorrect_err; 985 kstat_named_t sf_correct_err; 986 kstat_named_t sf_uncorrect_err; 987 kstat_named_t address_failed; 988 kstat_named_t dma_failed; 989 kstat_named_t length_failed; 990 kstat_named_t pkt_assy_dead; 991 kstat_named_t reorder_err; 992 } nxge_txc_kstat_t, *p_nxge_txc_kstat_t; 993 994 typedef struct _nxge_ipp_kstat { 995 /* 996 * Receive port IPP block statistics. 997 */ 998 kstat_named_t eop_miss; 999 kstat_named_t sop_miss; 1000 kstat_named_t dfifo_ue; 1001 kstat_named_t ecc_err_cnt; 1002 kstat_named_t pfifo_perr; 1003 kstat_named_t pfifo_over; 1004 kstat_named_t pfifo_und; 1005 kstat_named_t bad_cs_cnt; 1006 kstat_named_t pkt_dis_cnt; 1007 } nxge_ipp_kstat_t, *p_nxge_ipp_kstat_t; 1008 1009 typedef struct _nxge_zcp_kstat { 1010 /* 1011 * ZCP statistics. 1012 */ 1013 kstat_named_t errors; 1014 kstat_named_t inits; 1015 kstat_named_t rrfifo_underrun; 1016 kstat_named_t rrfifo_overrun; 1017 kstat_named_t rspfifo_uncorr_err; 1018 kstat_named_t buffer_overflow; 1019 kstat_named_t stat_tbl_perr; 1020 kstat_named_t dyn_tbl_perr; 1021 kstat_named_t buf_tbl_perr; 1022 kstat_named_t tt_program_err; 1023 kstat_named_t rsp_tt_index_err; 1024 kstat_named_t slv_tt_index_err; 1025 kstat_named_t zcp_tt_index_err; 1026 kstat_named_t access_fail; 1027 kstat_named_t cfifo_ecc; 1028 } nxge_zcp_kstat_t, *p_nxge_zcp_kstat_t; 1029 1030 typedef struct _nxge_mac_kstat { 1031 /* 1032 * Transmit MAC statistics. 1033 */ 1034 kstat_named_t tx_frame_cnt; 1035 kstat_named_t tx_underflow_err; 1036 kstat_named_t tx_overflow_err; 1037 kstat_named_t tx_maxpktsize_err; 1038 kstat_named_t tx_fifo_xfr_err; 1039 kstat_named_t tx_byte_cnt; 1040 1041 /* 1042 * Receive MAC statistics. 1043 */ 1044 kstat_named_t rx_frame_cnt; 1045 kstat_named_t rx_underflow_err; 1046 kstat_named_t rx_overflow_err; 1047 kstat_named_t rx_len_err_cnt; 1048 kstat_named_t rx_crc_err_cnt; 1049 kstat_named_t rx_viol_err_cnt; 1050 kstat_named_t rx_byte_cnt; 1051 kstat_named_t rx_hist1_cnt; 1052 kstat_named_t rx_hist2_cnt; 1053 kstat_named_t rx_hist3_cnt; 1054 kstat_named_t rx_hist4_cnt; 1055 kstat_named_t rx_hist5_cnt; 1056 kstat_named_t rx_hist6_cnt; 1057 kstat_named_t rx_hist7_cnt; 1058 kstat_named_t rx_broadcast_cnt; 1059 kstat_named_t rx_mult_cnt; 1060 kstat_named_t rx_frag_cnt; 1061 kstat_named_t rx_frame_align_err_cnt; 1062 kstat_named_t rx_linkfault_err_cnt; 1063 kstat_named_t rx_local_fault_err_cnt; 1064 kstat_named_t rx_remote_fault_err_cnt; 1065 } nxge_mac_kstat_t, *p_nxge_mac_kstat_t; 1066 1067 typedef struct _nxge_xmac_kstat { 1068 /* 1069 * XMAC statistics. 1070 */ 1071 kstat_named_t tx_frame_cnt; 1072 kstat_named_t tx_underflow_err; 1073 kstat_named_t tx_maxpktsize_err; 1074 kstat_named_t tx_overflow_err; 1075 kstat_named_t tx_fifo_xfr_err; 1076 kstat_named_t tx_byte_cnt; 1077 kstat_named_t rx_frame_cnt; 1078 kstat_named_t rx_underflow_err; 1079 kstat_named_t rx_overflow_err; 1080 kstat_named_t rx_crc_err_cnt; 1081 kstat_named_t rx_len_err_cnt; 1082 kstat_named_t rx_viol_err_cnt; 1083 kstat_named_t rx_byte_cnt; 1084 kstat_named_t rx_hist1_cnt; 1085 kstat_named_t rx_hist2_cnt; 1086 kstat_named_t rx_hist3_cnt; 1087 kstat_named_t rx_hist4_cnt; 1088 kstat_named_t rx_hist5_cnt; 1089 kstat_named_t rx_hist6_cnt; 1090 kstat_named_t rx_hist7_cnt; 1091 kstat_named_t rx_broadcast_cnt; 1092 kstat_named_t rx_mult_cnt; 1093 kstat_named_t rx_frag_cnt; 1094 kstat_named_t rx_frame_align_err_cnt; 1095 kstat_named_t rx_linkfault_err_cnt; 1096 kstat_named_t rx_remote_fault_err_cnt; 1097 kstat_named_t rx_local_fault_err_cnt; 1098 kstat_named_t rx_pause_cnt; 1099 kstat_named_t xpcs_deskew_err_cnt; 1100 kstat_named_t xpcs_ln0_symbol_err_cnt; 1101 kstat_named_t xpcs_ln1_symbol_err_cnt; 1102 kstat_named_t xpcs_ln2_symbol_err_cnt; 1103 kstat_named_t xpcs_ln3_symbol_err_cnt; 1104 } nxge_xmac_kstat_t, *p_nxge_xmac_kstat_t; 1105 1106 typedef struct _nxge_bmac_kstat { 1107 /* 1108 * BMAC statistics. 1109 */ 1110 kstat_named_t tx_frame_cnt; 1111 kstat_named_t tx_underrun_err; 1112 kstat_named_t tx_max_pkt_err; 1113 kstat_named_t tx_byte_cnt; 1114 kstat_named_t rx_frame_cnt; 1115 kstat_named_t rx_byte_cnt; 1116 kstat_named_t rx_overflow_err; 1117 kstat_named_t rx_align_err_cnt; 1118 kstat_named_t rx_crc_err_cnt; 1119 kstat_named_t rx_len_err_cnt; 1120 kstat_named_t rx_viol_err_cnt; 1121 kstat_named_t rx_pause_cnt; 1122 kstat_named_t tx_pause_state; 1123 kstat_named_t tx_nopause_state; 1124 } nxge_bmac_kstat_t, *p_nxge_bmac_kstat_t; 1125 1126 1127 typedef struct _nxge_fflp_kstat { 1128 /* 1129 * FFLP statistics. 1130 */ 1131 1132 kstat_named_t fflp_tcam_perr; 1133 kstat_named_t fflp_tcam_ecc_err; 1134 kstat_named_t fflp_vlan_perr; 1135 kstat_named_t fflp_hasht_lookup_err; 1136 kstat_named_t fflp_hasht_data_err[MAX_PARTITION]; 1137 } nxge_fflp_kstat_t, *p_nxge_fflp_kstat_t; 1138 1139 typedef struct _nxge_mmac_kstat { 1140 kstat_named_t mmac_max_addr_cnt; 1141 kstat_named_t mmac_avail_addr_cnt; 1142 kstat_named_t mmac_addr1; 1143 kstat_named_t mmac_addr2; 1144 kstat_named_t mmac_addr3; 1145 kstat_named_t mmac_addr4; 1146 kstat_named_t mmac_addr5; 1147 kstat_named_t mmac_addr6; 1148 kstat_named_t mmac_addr7; 1149 kstat_named_t mmac_addr8; 1150 kstat_named_t mmac_addr9; 1151 kstat_named_t mmac_addr10; 1152 kstat_named_t mmac_addr11; 1153 kstat_named_t mmac_addr12; 1154 kstat_named_t mmac_addr13; 1155 kstat_named_t mmac_addr14; 1156 kstat_named_t mmac_addr15; 1157 kstat_named_t mmac_addr16; 1158 } nxge_mmac_kstat_t, *p_nxge_mmac_kstat_t; 1159 1160 #endif /* _KERNEL */ 1161 1162 /* 1163 * Prototype definitions. 1164 */ 1165 nxge_status_t nxge_init(p_nxge_t); 1166 void nxge_uninit(p_nxge_t); 1167 void nxge_get64(p_nxge_t, p_mblk_t); 1168 void nxge_put64(p_nxge_t, p_mblk_t); 1169 void nxge_pio_loop(p_nxge_t, p_mblk_t); 1170 1171 #ifndef COSIM 1172 typedef void (*fptrv_t)(); 1173 timeout_id_t nxge_start_timer(p_nxge_t, fptrv_t, int); 1174 void nxge_stop_timer(p_nxge_t, timeout_id_t); 1175 #endif 1176 #endif 1177 1178 #ifdef __cplusplus 1179 } 1180 #endif 1181 1182 #endif /* _SYS_NXGE_NXGE_H */ 1183