1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 1997-2003 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Definitions for MII registers from 802.3u and vendor documentation 29 */ 30 31 #ifndef _MIIREGS_H 32 #define _MIIREGS_H 33 34 #pragma ident "%Z%%M% %I% %E% SMI" 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 /* Register addresses: Section 22.2.4 */ 41 #define MII_CONTROL 0 42 #define MII_STATUS 1 43 #define MII_PHYIDH 2 44 #define MII_PHYIDL 3 45 #define MII_AN_ADVERT 4 /* Auto negotiation advertisement. */ 46 #define MII_AN_LPABLE 5 /* Auto neg. Link Partner Ability */ 47 #define MII_AN_EXPANSION 6 /* Auto neg. Expansion. */ 48 #define MII_AN_NXTPGXMIT 7 /* Auto neg. Next Page Transmit */ 49 #define MII_RESERVED 8 /* Reserved up to 16 */ 50 #define MII_VENDOR(x) (16+(x)) /* Vendor specific */ 51 52 /* Control register: 22.2.4.1 */ 53 #define MII_CONTROL_RESET (1<<15) 54 #define MII_CONTROL_LOOPBACK (1<<14) 55 #define MII_CONTROL_100MB (1<<13) 56 #define MII_CONTROL_ANE (1<<12) 57 #define MII_CONTROL_PWRDN (1<<11) 58 #define MII_CONTROL_ISOLATE (1<<10) 59 #define MII_CONTROL_RSAN (1<<9) 60 #define MII_CONTROL_FDUPLEX (1<<8) 61 #define MII_CONTROL_COLTST (1<<7) 62 #define MII_CONTROL_RESERVED 0x7f 63 64 /* Status register: 22.2.4.2 */ 65 #define MII_STATUS_100_BASE_T4 (1<<15) 66 #define MII_STATUS_100_BASEX_FD (1<<14) 67 #define MII_STATUS_100_BASEX (1<<13) 68 #define MII_STATUS_10_FD (1<<12) 69 #define MII_STATUS_10 (1<<11) 70 #define MII_STATUS_RESERVED (0xf<<7) 71 #define MII_STATUS_MFPRMBLSUPR (1<<6) 72 #define MII_STATUS_ANDONE (1<<5) 73 #define MII_STATUS_REMFAULT (1<<4) 74 #define MII_STATUS_CANAUTONEG (1<<3) 75 #define MII_STATUS_LINKUP (1<<2) 76 #define MII_STATUS_JABBERING (1<<1) 77 #define MII_STATUS_EXTENDED (1<<0) 78 79 /* Advertisement/Partner ability registers: 28.2.4.1.3/4 */ 80 81 #define MII_AN_ADVERT_NP (1<<15) 82 #define MII_AN_ADVERT_ACK (1<<14) 83 #define MII_AN_ADVERT_REMFAULT (1<<13) 84 #define MII_AN_ADVERT_RESERVED (3<<11) 85 #define MII_AN_ADVERT_FCS (1<<10) 86 #define MII_AN_ADVERT_TECHABLE (0xff<<5) 87 #define MII_AN_ADVERT_SELECTOR (0x1f) 88 89 /* Technology field bits (above). From Annex 28B */ 90 #define MII_ABILITY_10BASE_T (1<<5) 91 #define MII_ABILITY_10BASE_T_FD (1<<6) 92 #define MII_ABILITY_100BASE_TX (1<<7) 93 #define MII_ABILITY_100BASE_TX_FD (1<<8) 94 #define MII_ABILITY_100BASE_T4 (1<<9) 95 96 /* Expansion register 28.2.4.1.5 */ 97 #define MII_AN_EXP_PARFAULT (1<<4) /* fault detected */ 98 #define MII_AN_EXP_LPCANNXTP (1<<3) /* Link partner is Next Page able */ 99 #define MII_AN_EXP_CANNXTPP (1<<2) /* Local is next page able */ 100 #define MII_AN_EXP_PAGERCVD (1<<1) /* A new page has been recvd. */ 101 #define MII_AN_EXP_LPCANAN (1<<0) /* LP can auto-negotiate */ 102 103 /* 104 * Truncated OUIs as found in the PHY Identifier ( 22.2.4.3.1 ), 105 * and known models (and their registers) from those manufacturers 106 */ 107 108 #define PHY_MANUFACTURER(x) (((x) >> 10) & 0x3fffff) /* 22 bits, 10-31 */ 109 #define PHY_MODEL(x) (((x) >> 4) & 0x3f) /* 6 bits,4-9 */ 110 #define PHY_REVISION(x) ((x) & 0xf) /* 4 bits, 0-3 */ 111 112 #define OUI_NATIONAL_SEMICONDUCTOR 0x80017 113 #define NS_DP83840 0x00 114 #define MII_83840_ADDR 25 115 #define NS83840_ADDR_SPEED10 (1<<6) 116 #define NS83840_ADDR_CONSTAT (1<<5) 117 #define NS83840_ADDR_ADDR (0x1f<<0) 118 119 #define OUI_INTEL 0x0aa00 120 #define INTEL_82553_CSTEP 0x35 /* A and B steps are non-standard */ 121 #define MII_82553_EX0 16 122 #define I82553_EX0_FDUPLEX (1<<0) 123 #define I82553_EX0_100MB (1<<1) 124 #define I82553_EX0_WAKE (1<<2) 125 #define I82553_EX0_SQUELCH (3<<3) /* 3:4 */ 126 #define I82553_EX0_REVCNTR (7<<5) /* 5:7 */ 127 #define I82553_EX0_FRCFAIL (1<<8) 128 #define I82553_EX0_TEST (0x1f<<9) /* 13:9 */ 129 #define I82553_EX0_LINKDIS (1<<14) 130 #define I82553_EX0_JABDIS (1<<15) 131 132 #define MII_82553_EX1 133 #define I82553_EX1_RESERVE (0x1ff<<0) /* 0:8 */ 134 #define I82553_EX1_CH2EOF (1<<9) 135 #define I82553_EX1_MNCHSTR (1<<10) 136 #define I82553_EX1_EOP (1<<11) 137 #define I82553_EX1_BADCODE (1<<12) 138 #define I82553_EX1_INVALCODE (1<<13) 139 #define I82553_EX1_DCBALANCE (1<<14) 140 #define I82553_EX1_PAIRSKEW (1<<15) 141 142 #define INTEL_82555 0x15 143 #define INTEL_82562_EH 0x33 144 #define INTEL_82562_ET 0x32 145 146 #define OUI_ICS 0x57d 147 #define ICS_1890 2 148 #define ICS_1889 1 149 #define ICS_EXCTRL 16 150 #define ICS_EXCTRL_CMDOVRD (1<<15) 151 #define ICS_EXCTRL_PHYADDR (0x1f<<6) 152 #define ICS_EXCTRL_SCSTEST (1<<5) 153 #define ICS_EXCTRL_INVECTEST (1<<2) 154 #define ICS_EXCTRL_SCDISABLE (1<<0) 155 156 #define ICS_QUICKPOLL 17 157 #define ICS_QUICKPOLL_100MB (1<<15) 158 #define ICS_QUICKPOLL_FDUPLEX (1<<14) 159 #define ICS_QUICKPOLL_ANPROG (7<<11) 160 #define ICS_QUICKPOLL_RSE (1<<10) 161 #define ICS_QUICKPOLL_PLLLOCK (1<<9) 162 #define ICS_QUICKPOLL_FALSECD (1<<8) 163 #define ICS_QUICKPOLL_SYMINVAL (1<<7) 164 #define ICS_QUICKPOLL_SYMHALT (1<<6) 165 #define ICS_QUICKPOLL_PREMEND (1<<5) 166 #define ICS_QUICKPOLL_ANDONE (1<<4) 167 #define ICS_QUICKPOLL_RESERVED (1<<3) 168 #define ICS_QUICKPOLL_JABBER (1<<2) 169 #define ICS_QUICKPOLL_REMFAULT (1<<1) 170 #define ICS_QUICKPOLL_LINKSTAT (1<<0) 171 172 #define ICS_10BASET 18 173 #define ICS_10BASET_REMJABBER (1<<15) 174 #define ICS_10BASET_REVPOLARITY (1<<14) 175 #define ICS_10BASET_RESERVED (0xff<<6) 176 #define ICS_10BASET_NOJABBER (1<<5) 177 #define ICS_10BASET_NORMLOOP (1<<4) 178 #define ICS_10BASET_NOAUTOPOLL (1<<3) 179 #define ICS_10BASET_NOSQE (1<<2) 180 #define ICS_10BASET_NOLINKLOSS (1<<1) 181 #define ICS_10BASET_NOSQUELCH (1<<0) 182 183 #define ICS_EXCTRL2 19 184 #define ICS_EXCTRL2_ISREPEATER (1<<15) 185 #define ICS_EXCTRL2_SOFTPRI (1<<14) 186 #define ICS_EXCTRL2_LPCANREMF (1<<13) 187 #define ICS_EXCTRL2_RMFSXMITED (1<<10) 188 #define ICS_EXCTRL2_ANPWRREMF (1<<4) 189 #define ICS_EXCTRL2_10BASETQUAL (1<<2) 190 #define ICS_EXCTRL2_AUTOPWRDN (1<<0) 191 192 #define OUI_DAVICOM 0x0606e 193 194 #define DM_SCR 16 195 #define DM_SCR_F_TX (1<<10) 196 #define DM_SCR_UTP (1<<9) 197 #define DM_SCR_F_LINK_100 (1<<7) 198 #define DM_SCR_LED_CTL (1<<5) 199 #define DM_SCR_SMRST (1<<3) 200 #define DM_SCR_MFPSC (1<<2) 201 #define DM_SCR_SLEEP (1<<1) 202 #define DM_SCR_RLOUT (1<<0) 203 204 #define DM_SCSR 17 205 #define DM_SCSR_100FDX (1<<15) 206 #define DM_SCSR_100HDX (1<<14) 207 #define DM_SCSR_10FDX (1<<13) 208 #define DM_SCSR_10HDX (1<<12) 209 #define DM_SCSR_PHYAD (0x1f<<4) 210 #define DM_SCSR_ANMB (0x0f) 211 212 #define DM_10BT 18 213 #define DM_10BT_LB_EN (1<<14) 214 #define DM_10BT_HBE (1<<13) 215 #define DM_10BT_JABEN (1<<11) 216 217 #ifdef __cplusplus 218 } 219 #endif 220 221 #endif /* _MIIREGS_H */ 222