1 /* 2 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 3 */ 4 5 /* 6 * This driver was derived from the FreeBSD if_msk.c driver, which 7 * bears the following copyright attributions and licenses. 8 */ 9 10 /* 11 * 12 * LICENSE: 13 * Copyright (C) Marvell International Ltd. and/or its affiliates 14 * 15 * The computer program files contained in this folder ("Files") 16 * are provided to you under the BSD-type license terms provided 17 * below, and any use of such Files and any derivative works 18 * thereof created by you shall be governed by the following terms 19 * and conditions: 20 * 21 * - Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * - Redistributions in binary form must reproduce the above 24 * copyright notice, this list of conditions and the following 25 * disclaimer in the documentation and/or other materials provided 26 * with the distribution. 27 * - Neither the name of Marvell nor the names of its contributors 28 * may be used to endorse or promote products derived from this 29 * software without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 34 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 35 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 37 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 40 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 41 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 42 * OF THE POSSIBILITY OF SUCH DAMAGE. 43 * /LICENSE 44 * 45 */ 46 /* 47 * Copyright (c) 1997, 1998, 1999, 2000 48 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 49 * 50 * Redistribution and use in source and binary forms, with or without 51 * modification, are permitted provided that the following conditions 52 * are met: 53 * 1. Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * 2. Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in the 57 * documentation and/or other materials provided with the distribution. 58 * 3. All advertising materials mentioning features or use of this software 59 * must display the following acknowledgement: 60 * This product includes software developed by Bill Paul. 61 * 4. Neither the name of the author nor the names of any co-contributors 62 * may be used to endorse or promote products derived from this software 63 * without specific prior written permission. 64 * 65 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 66 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 67 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 68 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 69 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 70 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 71 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 72 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 73 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 74 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 75 * THE POSSIBILITY OF SUCH DAMAGE. 76 */ 77 /* 78 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 79 * 80 * Permission to use, copy, modify, and distribute this software for any 81 * purpose with or without fee is hereby granted, provided that the above 82 * copyright notice and this permission notice appear in all copies. 83 * 84 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 85 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 86 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 87 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 88 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 89 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 90 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 91 */ 92 93 #include <sys/varargs.h> 94 #include <sys/types.h> 95 #include <sys/modctl.h> 96 #include <sys/conf.h> 97 #include <sys/devops.h> 98 #include <sys/stream.h> 99 #include <sys/strsun.h> 100 #include <sys/cmn_err.h> 101 #include <sys/ethernet.h> 102 #include <sys/kmem.h> 103 #include <sys/time.h> 104 #include <sys/pci.h> 105 #include <sys/mii.h> 106 #include <sys/miiregs.h> 107 #include <sys/mac.h> 108 #include <sys/mac_ether.h> 109 #include <sys/mac_provider.h> 110 #include <sys/debug.h> 111 #include <sys/note.h> 112 #include <sys/ddi.h> 113 #include <sys/sunddi.h> 114 #include <sys/vlan.h> 115 116 #include "yge.h" 117 118 static struct ddi_device_acc_attr yge_regs_attr = { 119 DDI_DEVICE_ATTR_V0, 120 DDI_STRUCTURE_LE_ACC, 121 DDI_STRICTORDER_ACC 122 }; 123 124 static struct ddi_device_acc_attr yge_ring_attr = { 125 DDI_DEVICE_ATTR_V0, 126 DDI_STRUCTURE_LE_ACC, 127 DDI_STRICTORDER_ACC 128 }; 129 130 static struct ddi_device_acc_attr yge_buf_attr = { 131 DDI_DEVICE_ATTR_V0, 132 DDI_NEVERSWAP_ACC, 133 DDI_STRICTORDER_ACC 134 }; 135 136 #define DESC_ALIGN 0x1000 137 138 static ddi_dma_attr_t yge_ring_dma_attr = { 139 DMA_ATTR_V0, /* dma_attr_version */ 140 0, /* dma_attr_addr_lo */ 141 0x00000000ffffffffull, /* dma_attr_addr_hi */ 142 0x00000000ffffffffull, /* dma_attr_count_max */ 143 DESC_ALIGN, /* dma_attr_align */ 144 0x000007fc, /* dma_attr_burstsizes */ 145 1, /* dma_attr_minxfer */ 146 0x00000000ffffffffull, /* dma_attr_maxxfer */ 147 0x00000000ffffffffull, /* dma_attr_seg */ 148 1, /* dma_attr_sgllen */ 149 1, /* dma_attr_granular */ 150 0 /* dma_attr_flags */ 151 }; 152 153 static ddi_dma_attr_t yge_buf_dma_attr = { 154 DMA_ATTR_V0, /* dma_attr_version */ 155 0, /* dma_attr_addr_lo */ 156 0x00000000ffffffffull, /* dma_attr_addr_hi */ 157 0x00000000ffffffffull, /* dma_attr_count_max */ 158 1, /* dma_attr_align */ 159 0x0000fffc, /* dma_attr_burstsizes */ 160 1, /* dma_attr_minxfer */ 161 0x000000000000ffffull, /* dma_attr_maxxfer */ 162 0x00000000ffffffffull, /* dma_attr_seg */ 163 8, /* dma_attr_sgllen */ 164 1, /* dma_attr_granular */ 165 0 /* dma_attr_flags */ 166 }; 167 168 169 static int yge_attach(yge_dev_t *); 170 static void yge_detach(yge_dev_t *); 171 static int yge_suspend(yge_dev_t *); 172 static int yge_resume(yge_dev_t *); 173 174 static void yge_reset(yge_dev_t *); 175 static void yge_setup_rambuffer(yge_dev_t *); 176 177 static int yge_init_port(yge_port_t *); 178 static void yge_uninit_port(yge_port_t *); 179 static int yge_register_port(yge_port_t *); 180 181 static void yge_tick(void *); 182 static uint_t yge_intr(caddr_t, caddr_t); 183 static int yge_intr_gmac(yge_port_t *); 184 static void yge_intr_enable(yge_dev_t *); 185 static void yge_intr_disable(yge_dev_t *); 186 static boolean_t yge_handle_events(yge_dev_t *, mblk_t **, mblk_t **, int *); 187 static void yge_handle_hwerr(yge_port_t *, uint32_t); 188 static void yge_intr_hwerr(yge_dev_t *); 189 static mblk_t *yge_rxeof(yge_port_t *, uint32_t, int); 190 static void yge_txeof(yge_port_t *, int); 191 static boolean_t yge_send(yge_port_t *, mblk_t *); 192 static void yge_set_prefetch(yge_dev_t *, int, yge_ring_t *); 193 static void yge_set_rambuffer(yge_port_t *); 194 static void yge_start_port(yge_port_t *); 195 static void yge_stop_port(yge_port_t *); 196 static void yge_phy_power(yge_dev_t *, boolean_t); 197 static int yge_alloc_ring(yge_port_t *, yge_dev_t *, yge_ring_t *, uint32_t); 198 static void yge_free_ring(yge_ring_t *); 199 static uint8_t yge_find_capability(yge_dev_t *, uint8_t); 200 201 static int yge_txrx_dma_alloc(yge_port_t *); 202 static void yge_txrx_dma_free(yge_port_t *); 203 static void yge_init_rx_ring(yge_port_t *); 204 static void yge_init_tx_ring(yge_port_t *); 205 206 static uint16_t yge_mii_readreg(yge_port_t *, uint8_t, uint8_t); 207 static void yge_mii_writereg(yge_port_t *, uint8_t, uint8_t, uint16_t); 208 209 static uint16_t yge_mii_read(void *, uint8_t, uint8_t); 210 static void yge_mii_write(void *, uint8_t, uint8_t, uint16_t); 211 static void yge_mii_notify(void *, link_state_t); 212 213 static void yge_setrxfilt(yge_port_t *); 214 static void yge_restart_task(yge_dev_t *); 215 static void yge_task(void *); 216 static void yge_dispatch(yge_dev_t *, int); 217 218 static void yge_stats_clear(yge_port_t *); 219 static void yge_stats_update(yge_port_t *); 220 static uint32_t yge_hashbit(const uint8_t *); 221 222 static int yge_m_unicst(void *, const uint8_t *); 223 static int yge_m_multicst(void *, boolean_t, const uint8_t *); 224 static int yge_m_promisc(void *, boolean_t); 225 static mblk_t *yge_m_tx(void *, mblk_t *); 226 static int yge_m_stat(void *, uint_t, uint64_t *); 227 static int yge_m_start(void *); 228 static void yge_m_stop(void *); 229 static int yge_m_getprop(void *, const char *, mac_prop_id_t, uint_t, void *); 230 static void yge_m_propinfo(void *, const char *, mac_prop_id_t, 231 mac_prop_info_handle_t); 232 static int yge_m_setprop(void *, const char *, mac_prop_id_t, uint_t, 233 const void *); 234 static void yge_m_ioctl(void *, queue_t *, mblk_t *); 235 236 void yge_error(yge_dev_t *, yge_port_t *, char *, ...); 237 extern void yge_phys_update(yge_port_t *); 238 extern int yge_phys_restart(yge_port_t *, boolean_t); 239 extern int yge_phys_init(yge_port_t *, phy_readreg_t, phy_writereg_t); 240 241 static mac_callbacks_t yge_m_callbacks = { 242 MC_IOCTL | MC_SETPROP | MC_GETPROP | MC_PROPINFO, 243 yge_m_stat, 244 yge_m_start, 245 yge_m_stop, 246 yge_m_promisc, 247 yge_m_multicst, 248 yge_m_unicst, 249 yge_m_tx, 250 NULL, 251 yge_m_ioctl, 252 NULL, /* mc_getcapab */ 253 NULL, /* mc_open */ 254 NULL, /* mc_close */ 255 yge_m_setprop, 256 yge_m_getprop, 257 yge_m_propinfo 258 }; 259 260 static mii_ops_t yge_mii_ops = { 261 MII_OPS_VERSION, 262 yge_mii_read, 263 yge_mii_write, 264 yge_mii_notify, 265 NULL /* reset */ 266 }; 267 268 /* 269 * This is the low level interface routine to read from the PHY 270 * MII registers. There is multiple steps to these accesses. First 271 * the register number is written to an address register. Then after 272 * a specified delay status is checked until the data is present. 273 */ 274 static uint16_t 275 yge_mii_readreg(yge_port_t *port, uint8_t phy, uint8_t reg) 276 { 277 yge_dev_t *dev = port->p_dev; 278 int pnum = port->p_port; 279 uint16_t val; 280 281 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL, 282 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 283 284 for (int i = 0; i < YGE_TIMEOUT; i += 10) { 285 drv_usecwait(10); 286 val = GMAC_READ_2(dev, pnum, GM_SMI_CTRL); 287 if ((val & GM_SMI_CT_RD_VAL) != 0) { 288 val = GMAC_READ_2(dev, pnum, GM_SMI_DATA); 289 return (val); 290 } 291 } 292 293 return (0xffff); 294 } 295 296 /* 297 * This is the low level interface routine to write to the PHY 298 * MII registers. There is multiple steps to these accesses. The 299 * data and the target registers address are written to the PHY. 300 * Then the PHY is polled until it is done with the write. Note 301 * that the delays are specified and required! 302 */ 303 static void 304 yge_mii_writereg(yge_port_t *port, uint8_t phy, uint8_t reg, uint16_t val) 305 { 306 yge_dev_t *dev = port->p_dev; 307 int pnum = port->p_port; 308 309 GMAC_WRITE_2(dev, pnum, GM_SMI_DATA, val); 310 GMAC_WRITE_2(dev, pnum, GM_SMI_CTRL, 311 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 312 313 for (int i = 0; i < YGE_TIMEOUT; i += 10) { 314 drv_usecwait(10); 315 if ((GMAC_READ_2(dev, pnum, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) 316 return; 317 } 318 319 yge_error(NULL, port, "phy write timeout"); 320 } 321 322 static uint16_t 323 yge_mii_read(void *arg, uint8_t phy, uint8_t reg) 324 { 325 yge_port_t *port = arg; 326 uint16_t rv; 327 328 PHY_LOCK(port->p_dev); 329 rv = yge_mii_readreg(port, phy, reg); 330 PHY_UNLOCK(port->p_dev); 331 return (rv); 332 } 333 334 static void 335 yge_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) 336 { 337 yge_port_t *port = arg; 338 339 PHY_LOCK(port->p_dev); 340 yge_mii_writereg(port, phy, reg, val); 341 PHY_UNLOCK(port->p_dev); 342 } 343 344 /* 345 * The MII common code calls this function to let the MAC driver 346 * know when there has been a change in status. 347 */ 348 void 349 yge_mii_notify(void *arg, link_state_t link) 350 { 351 yge_port_t *port = arg; 352 yge_dev_t *dev = port->p_dev; 353 uint32_t gmac; 354 uint32_t gpcr; 355 link_flowctrl_t fc; 356 link_duplex_t duplex; 357 int speed; 358 359 fc = mii_get_flowctrl(port->p_mii); 360 duplex = mii_get_duplex(port->p_mii); 361 speed = mii_get_speed(port->p_mii); 362 363 DEV_LOCK(dev); 364 365 if (link == LINK_STATE_UP) { 366 367 /* Enable Tx FIFO Underrun. */ 368 CSR_WRITE_1(dev, MR_ADDR(port->p_port, GMAC_IRQ_MSK), 369 GM_IS_TX_FF_UR | /* TX FIFO underflow */ 370 GM_IS_RX_FF_OR); /* RX FIFO overflow */ 371 372 gpcr = GM_GPCR_AU_ALL_DIS; 373 374 switch (fc) { 375 case LINK_FLOWCTRL_BI: 376 gmac = GMC_PAUSE_ON; 377 gpcr &= ~(GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS); 378 break; 379 case LINK_FLOWCTRL_TX: 380 gmac = GMC_PAUSE_ON; 381 gpcr |= GM_GPCR_FC_RX_DIS; 382 break; 383 case LINK_FLOWCTRL_RX: 384 gmac = GMC_PAUSE_ON; 385 gpcr |= GM_GPCR_FC_TX_DIS; 386 break; 387 case LINK_FLOWCTRL_NONE: 388 default: 389 gmac = GMC_PAUSE_OFF; 390 gpcr |= GM_GPCR_FC_RX_DIS; 391 gpcr |= GM_GPCR_FC_TX_DIS; 392 break; 393 } 394 395 gpcr &= ~((GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100)); 396 switch (speed) { 397 case 1000: 398 gpcr |= GM_GPCR_SPEED_1000; 399 break; 400 case 100: 401 gpcr |= GM_GPCR_SPEED_100; 402 break; 403 case 10: 404 default: 405 break; 406 } 407 408 if (duplex == LINK_DUPLEX_FULL) { 409 gpcr |= GM_GPCR_DUP_FULL; 410 } else { 411 gpcr &= ~(GM_GPCR_DUP_FULL); 412 gmac = GMC_PAUSE_OFF; 413 gpcr |= GM_GPCR_FC_RX_DIS; 414 gpcr |= GM_GPCR_FC_TX_DIS; 415 } 416 417 gpcr |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 418 GMAC_WRITE_2(dev, port->p_port, GM_GP_CTRL, gpcr); 419 420 /* Read again to ensure writing. */ 421 (void) GMAC_READ_2(dev, port->p_port, GM_GP_CTRL); 422 423 /* write out the flow control gmac setting */ 424 CSR_WRITE_4(dev, MR_ADDR(port->p_port, GMAC_CTRL), gmac); 425 426 } else { 427 /* Disable Rx/Tx MAC. */ 428 gpcr = GMAC_READ_2(dev, port->p_port, GM_GP_CTRL); 429 gpcr &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 430 GMAC_WRITE_2(dev, port->p_port, GM_GP_CTRL, gpcr); 431 432 /* Read again to ensure writing. */ 433 (void) GMAC_READ_2(dev, port->p_port, GM_GP_CTRL); 434 } 435 436 DEV_UNLOCK(dev); 437 438 mac_link_update(port->p_mh, link); 439 440 if (port->p_running && (link == LINK_STATE_UP)) { 441 mac_tx_update(port->p_mh); 442 } 443 } 444 445 static void 446 yge_setrxfilt(yge_port_t *port) 447 { 448 yge_dev_t *dev; 449 uint16_t mode; 450 uint8_t *ea; 451 uint32_t *mchash; 452 int pnum; 453 454 dev = port->p_dev; 455 pnum = port->p_port; 456 ea = port->p_curraddr; 457 mchash = port->p_mchash; 458 459 if (dev->d_suspended) 460 return; 461 462 /* Set station address. */ 463 for (int i = 0; i < (ETHERADDRL / 2); i++) { 464 GMAC_WRITE_2(dev, pnum, GM_SRC_ADDR_1L + i * 4, 465 ((uint16_t)ea[i * 2] | ((uint16_t)ea[(i * 2) + 1] << 8))); 466 } 467 for (int i = 0; i < (ETHERADDRL / 2); i++) { 468 GMAC_WRITE_2(dev, pnum, GM_SRC_ADDR_2L + i * 4, 469 ((uint16_t)ea[i * 2] | ((uint16_t)ea[(i * 2) + 1] << 8))); 470 } 471 472 /* Figure out receive filtering mode. */ 473 mode = GMAC_READ_2(dev, pnum, GM_RX_CTRL); 474 if (port->p_promisc) { 475 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 476 } else { 477 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 478 } 479 /* Write the multicast filter. */ 480 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H1, mchash[0] & 0xffff); 481 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H2, (mchash[0] >> 16) & 0xffff); 482 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H3, mchash[1] & 0xffff); 483 GMAC_WRITE_2(dev, pnum, GM_MC_ADDR_H4, (mchash[1] >> 16) & 0xffff); 484 /* Write the receive filtering mode. */ 485 GMAC_WRITE_2(dev, pnum, GM_RX_CTRL, mode); 486 } 487 488 static void 489 yge_init_rx_ring(yge_port_t *port) 490 { 491 yge_buf_t *rxb; 492 yge_ring_t *ring; 493 int prod; 494 495 port->p_rx_cons = 0; 496 port->p_rx_putwm = YGE_PUT_WM; 497 ring = &port->p_rx_ring; 498 499 /* ala bzero, but uses safer acch access */ 500 CLEARRING(ring); 501 502 for (prod = 0; prod < YGE_RX_RING_CNT; prod++) { 503 /* Hang out receive buffers. */ 504 rxb = &port->p_rx_buf[prod]; 505 506 PUTADDR(ring, prod, rxb->b_paddr); 507 PUTCTRL(ring, prod, port->p_framesize | OP_PACKET | HW_OWNER); 508 } 509 510 SYNCRING(ring, DDI_DMA_SYNC_FORDEV); 511 512 yge_set_prefetch(port->p_dev, port->p_rxq, ring); 513 514 /* Update prefetch unit. */ 515 CSR_WRITE_2(port->p_dev, 516 Y2_PREF_Q_ADDR(port->p_rxq, PREF_UNIT_PUT_IDX_REG), 517 YGE_RX_RING_CNT - 1); 518 } 519 520 static void 521 yge_init_tx_ring(yge_port_t *port) 522 { 523 yge_ring_t *ring = &port->p_tx_ring; 524 525 port->p_tx_prod = 0; 526 port->p_tx_cons = 0; 527 port->p_tx_cnt = 0; 528 529 CLEARRING(ring); 530 SYNCRING(ring, DDI_DMA_SYNC_FORDEV); 531 532 yge_set_prefetch(port->p_dev, port->p_txq, ring); 533 } 534 535 static void 536 yge_setup_rambuffer(yge_dev_t *dev) 537 { 538 int next; 539 int i; 540 541 /* Get adapter SRAM size. */ 542 dev->d_ramsize = CSR_READ_1(dev, B2_E_0) * 4; 543 if (dev->d_ramsize == 0) 544 return; 545 546 dev->d_pflags |= PORT_FLAG_RAMBUF; 547 /* 548 * Give receiver 2/3 of memory and round down to the multiple 549 * of 1024. Tx/Rx RAM buffer size of Yukon 2 should be multiple 550 * of 1024. 551 */ 552 dev->d_rxqsize = (((dev->d_ramsize * 1024 * 2) / 3) & ~(1024 - 1)); 553 dev->d_txqsize = (dev->d_ramsize * 1024) - dev->d_rxqsize; 554 555 for (i = 0, next = 0; i < dev->d_num_port; i++) { 556 dev->d_rxqstart[i] = next; 557 dev->d_rxqend[i] = next + dev->d_rxqsize - 1; 558 next = dev->d_rxqend[i] + 1; 559 dev->d_txqstart[i] = next; 560 dev->d_txqend[i] = next + dev->d_txqsize - 1; 561 next = dev->d_txqend[i] + 1; 562 } 563 } 564 565 static void 566 yge_phy_power(yge_dev_t *dev, boolean_t powerup) 567 { 568 uint32_t val; 569 int i; 570 571 if (powerup) { 572 /* Switch power to VCC (WA for VAUX problem). */ 573 CSR_WRITE_1(dev, B0_POWER_CTRL, 574 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 575 /* Disable Core Clock Division, set Clock Select to 0. */ 576 CSR_WRITE_4(dev, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 577 578 val = 0; 579 if (dev->d_hw_id == CHIP_ID_YUKON_XL && 580 dev->d_hw_rev > CHIP_REV_YU_XL_A1) { 581 /* Enable bits are inverted. */ 582 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 583 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 584 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 585 } 586 /* 587 * Enable PCI & Core Clock, enable clock gating for both Links. 588 */ 589 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val); 590 591 val = pci_config_get32(dev->d_pcih, PCI_OUR_REG_1); 592 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 593 if (dev->d_hw_id == CHIP_ID_YUKON_XL && 594 dev->d_hw_rev > CHIP_REV_YU_XL_A1) { 595 /* Deassert Low Power for 1st PHY. */ 596 val |= PCI_Y2_PHY1_COMA; 597 if (dev->d_num_port > 1) 598 val |= PCI_Y2_PHY2_COMA; 599 } 600 601 /* Release PHY from PowerDown/COMA mode. */ 602 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val); 603 604 switch (dev->d_hw_id) { 605 case CHIP_ID_YUKON_EC_U: 606 case CHIP_ID_YUKON_EX: 607 case CHIP_ID_YUKON_FE_P: { 608 uint32_t our; 609 610 CSR_WRITE_2(dev, B0_CTST, Y2_HW_WOL_OFF); 611 612 /* Enable all clocks. */ 613 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); 614 615 our = pci_config_get32(dev->d_pcih, PCI_OUR_REG_4); 616 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 617 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 618 /* Set all bits to 0 except bits 15..12. */ 619 pci_config_put32(dev->d_pcih, PCI_OUR_REG_4, our); 620 621 /* Set to default value. */ 622 our = pci_config_get32(dev->d_pcih, PCI_OUR_REG_5); 623 our &= P_CTL_TIM_VMAIN_AV_MSK; 624 pci_config_put32(dev->d_pcih, PCI_OUR_REG_5, our); 625 626 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, 0); 627 628 /* 629 * Enable workaround for dev 4.107 on Yukon-Ultra 630 * and Extreme 631 */ 632 our = CSR_READ_4(dev, B2_GP_IO); 633 our |= GLB_GPIO_STAT_RACE_DIS; 634 CSR_WRITE_4(dev, B2_GP_IO, our); 635 636 (void) CSR_READ_4(dev, B2_GP_IO); 637 break; 638 } 639 default: 640 break; 641 } 642 643 for (i = 0; i < dev->d_num_port; i++) { 644 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL), 645 GMLC_RST_SET); 646 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_LINK_CTRL), 647 GMLC_RST_CLR); 648 } 649 } else { 650 val = pci_config_get32(dev->d_pcih, PCI_OUR_REG_1); 651 if (dev->d_hw_id == CHIP_ID_YUKON_XL && 652 dev->d_hw_rev > CHIP_REV_YU_XL_A1) { 653 val &= ~PCI_Y2_PHY1_COMA; 654 if (dev->d_num_port > 1) 655 val &= ~PCI_Y2_PHY2_COMA; 656 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 657 } else { 658 val |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 659 } 660 pci_config_put32(dev->d_pcih, PCI_OUR_REG_1, val); 661 662 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 663 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 664 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 665 if (dev->d_hw_id == CHIP_ID_YUKON_XL && 666 dev->d_hw_rev > CHIP_REV_YU_XL_A1) { 667 /* Enable bits are inverted. */ 668 val = 0; 669 } 670 /* 671 * Disable PCI & Core Clock, disable clock gating for 672 * both Links. 673 */ 674 CSR_WRITE_1(dev, B2_Y2_CLK_GATE, val); 675 CSR_WRITE_1(dev, B0_POWER_CTRL, 676 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 677 } 678 } 679 680 static void 681 yge_reset(yge_dev_t *dev) 682 { 683 uint64_t addr; 684 uint16_t status; 685 uint32_t val; 686 int i; 687 ddi_acc_handle_t pcih = dev->d_pcih; 688 689 /* Turn off ASF */ 690 if (dev->d_hw_id == CHIP_ID_YUKON_EX) { 691 status = CSR_READ_2(dev, B28_Y2_ASF_STAT_CMD); 692 /* Clear AHB bridge & microcontroller reset */ 693 status &= ~Y2_ASF_CPU_MODE; 694 status &= ~Y2_ASF_AHB_RST; 695 /* Clear ASF microcontroller state */ 696 status &= ~Y2_ASF_STAT_MSK; 697 CSR_WRITE_2(dev, B28_Y2_ASF_STAT_CMD, status); 698 } else { 699 CSR_WRITE_1(dev, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 700 } 701 CSR_WRITE_2(dev, B0_CTST, Y2_ASF_DISABLE); 702 703 /* 704 * Since we disabled ASF, S/W reset is required for Power Management. 705 */ 706 CSR_WRITE_1(dev, B0_CTST, CS_RST_SET); 707 CSR_WRITE_1(dev, B0_CTST, CS_RST_CLR); 708 709 /* Allow writes to PCI config space */ 710 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); 711 712 /* Clear all error bits in the PCI status register. */ 713 status = pci_config_get16(pcih, PCI_CONF_STAT); 714 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); 715 716 status |= (PCI_STAT_S_PERROR | PCI_STAT_S_SYSERR | PCI_STAT_R_MAST_AB | 717 PCI_STAT_R_TARG_AB | PCI_STAT_PERROR); 718 pci_config_put16(pcih, PCI_CONF_STAT, status); 719 720 CSR_WRITE_1(dev, B0_CTST, CS_MRST_CLR); 721 722 switch (dev->d_bustype) { 723 case PEX_BUS: 724 /* Clear all PEX errors. */ 725 CSR_PCI_WRITE_4(dev, Y2_CFG_AER + AER_UNCOR_ERR, 0xffffffff); 726 727 /* is error bit status stuck? */ 728 val = CSR_PCI_READ_4(dev, PEX_UNC_ERR_STAT); 729 if ((val & PEX_RX_OV) != 0) { 730 dev->d_intrmask &= ~Y2_IS_HW_ERR; 731 dev->d_intrhwemask &= ~Y2_IS_PCI_EXP; 732 } 733 break; 734 case PCI_BUS: 735 /* Set Cache Line Size to 2 (8 bytes) if configured to 0. */ 736 if (pci_config_get8(pcih, PCI_CONF_CACHE_LINESZ) == 0) 737 pci_config_put16(pcih, PCI_CONF_CACHE_LINESZ, 2); 738 break; 739 case PCIX_BUS: 740 /* Set Cache Line Size to 2 (8 bytes) if configured to 0. */ 741 if (pci_config_get8(pcih, PCI_CONF_CACHE_LINESZ) == 0) 742 pci_config_put16(pcih, PCI_CONF_CACHE_LINESZ, 2); 743 744 /* Set Cache Line Size opt. */ 745 val = pci_config_get32(pcih, PCI_OUR_REG_1); 746 val |= PCI_CLS_OPT; 747 pci_config_put32(pcih, PCI_OUR_REG_1, val); 748 break; 749 } 750 751 /* Set PHY power state. */ 752 yge_phy_power(dev, B_TRUE); 753 754 /* Reset GPHY/GMAC Control */ 755 for (i = 0; i < dev->d_num_port; i++) { 756 /* GPHY Control reset. */ 757 CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 758 CSR_WRITE_4(dev, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 759 /* GMAC Control reset. */ 760 CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 761 CSR_WRITE_4(dev, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 762 if (dev->d_hw_id == CHIP_ID_YUKON_EX || 763 dev->d_hw_id == CHIP_ID_YUKON_SUPR) { 764 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), 765 (GMC_BYP_RETR_ON | GMC_BYP_MACSECRX_ON | 766 GMC_BYP_MACSECTX_ON)); 767 } 768 CSR_WRITE_2(dev, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 769 770 } 771 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 772 773 /* LED On. */ 774 CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_ON); 775 776 /* Clear TWSI IRQ. */ 777 CSR_WRITE_4(dev, B2_I2C_IRQ, I2C_CLR_IRQ); 778 779 /* Turn off hardware timer. */ 780 CSR_WRITE_1(dev, B2_TI_CTRL, TIM_STOP); 781 CSR_WRITE_1(dev, B2_TI_CTRL, TIM_CLR_IRQ); 782 783 /* Turn off descriptor polling. */ 784 CSR_WRITE_1(dev, B28_DPT_CTRL, DPT_STOP); 785 786 /* Turn off time stamps. */ 787 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_STOP); 788 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 789 790 /* Don't permit config space writing */ 791 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 792 793 /* enable TX Arbiters */ 794 for (i = 0; i < dev->d_num_port; i++) 795 CSR_WRITE_1(dev, MR_ADDR(i, TXA_CTRL), TXA_ENA_ARB); 796 797 /* Configure timeout values. */ 798 for (i = 0; i < dev->d_num_port; i++) { 799 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 800 801 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), RI_TO_53); 802 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), RI_TO_53); 803 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), RI_TO_53); 804 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), RI_TO_53); 805 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), RI_TO_53); 806 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), RI_TO_53); 807 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), RI_TO_53); 808 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), RI_TO_53); 809 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), RI_TO_53); 810 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), RI_TO_53); 811 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), RI_TO_53); 812 CSR_WRITE_1(dev, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), RI_TO_53); 813 } 814 815 /* Disable all interrupts. */ 816 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); 817 (void) CSR_READ_4(dev, B0_HWE_IMSK); 818 CSR_WRITE_4(dev, B0_IMSK, 0); 819 (void) CSR_READ_4(dev, B0_IMSK); 820 821 /* 822 * On dual port PCI-X card, there is an problem where status 823 * can be received out of order due to split transactions. 824 */ 825 if (dev->d_bustype == PCIX_BUS && dev->d_num_port > 1) { 826 int pcix; 827 uint16_t pcix_cmd; 828 829 if ((pcix = yge_find_capability(dev, PCI_CAP_ID_PCIX)) != 0) { 830 pcix_cmd = pci_config_get16(pcih, pcix + 2); 831 /* Clear Max Outstanding Split Transactions. */ 832 pcix_cmd &= ~0x70; 833 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); 834 pci_config_put16(pcih, pcix + 2, pcix_cmd); 835 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 836 } 837 } 838 if (dev->d_bustype == PEX_BUS) { 839 uint16_t v, width; 840 841 v = pci_config_get16(pcih, PEX_DEV_CTRL); 842 /* Change Max. Read Request Size to 4096 bytes. */ 843 v &= ~PEX_DC_MAX_RRS_MSK; 844 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 845 pci_config_put16(pcih, PEX_DEV_CTRL, v); 846 width = pci_config_get16(pcih, PEX_LNK_STAT); 847 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 848 v = pci_config_get16(pcih, PEX_LNK_CAP); 849 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 850 if (v != width) 851 yge_error(dev, NULL, 852 "Negotiated width of PCIe link(x%d) != " 853 "max. width of link(x%d)\n", width, v); 854 } 855 856 /* Clear status list. */ 857 CLEARRING(&dev->d_status_ring); 858 SYNCRING(&dev->d_status_ring, DDI_DMA_SYNC_FORDEV); 859 860 dev->d_stat_cons = 0; 861 862 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_RST_SET); 863 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_RST_CLR); 864 865 /* Set the status list base address. */ 866 addr = dev->d_status_ring.r_paddr; 867 CSR_WRITE_4(dev, STAT_LIST_ADDR_LO, YGE_ADDR_LO(addr)); 868 CSR_WRITE_4(dev, STAT_LIST_ADDR_HI, YGE_ADDR_HI(addr)); 869 870 /* Set the status list last index. */ 871 CSR_WRITE_2(dev, STAT_LAST_IDX, YGE_STAT_RING_CNT - 1); 872 CSR_WRITE_2(dev, STAT_PUT_IDX, 0); 873 874 if (dev->d_hw_id == CHIP_ID_YUKON_EC && 875 dev->d_hw_rev == CHIP_REV_YU_EC_A1) { 876 /* WA for dev. #4.3 */ 877 CSR_WRITE_2(dev, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 878 /* WA for dev #4.18 */ 879 CSR_WRITE_1(dev, STAT_FIFO_WM, 0x21); 880 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 7); 881 } else { 882 CSR_WRITE_2(dev, STAT_TX_IDX_TH, 10); 883 CSR_WRITE_1(dev, STAT_FIFO_WM, 16); 884 885 /* ISR status FIFO watermark */ 886 if (dev->d_hw_id == CHIP_ID_YUKON_XL && 887 dev->d_hw_rev == CHIP_REV_YU_XL_A0) 888 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 4); 889 else 890 CSR_WRITE_1(dev, STAT_FIFO_ISR_WM, 16); 891 892 CSR_WRITE_4(dev, STAT_ISR_TIMER_INI, 0x0190); 893 } 894 895 /* 896 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 897 */ 898 CSR_WRITE_4(dev, STAT_TX_TIMER_INI, YGE_USECS(dev, 1000)); 899 900 /* Enable status unit. */ 901 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_OP_ON); 902 903 CSR_WRITE_1(dev, STAT_TX_TIMER_CTRL, TIM_START); 904 CSR_WRITE_1(dev, STAT_LEV_TIMER_CTRL, TIM_START); 905 CSR_WRITE_1(dev, STAT_ISR_TIMER_CTRL, TIM_START); 906 } 907 908 static int 909 yge_init_port(yge_port_t *port) 910 { 911 yge_dev_t *dev = port->p_dev; 912 int i; 913 mac_register_t *macp; 914 915 port->p_flags = dev->d_pflags; 916 port->p_ppa = ddi_get_instance(dev->d_dip) + (port->p_port * 100); 917 918 port->p_tx_buf = kmem_zalloc(sizeof (yge_buf_t) * YGE_TX_RING_CNT, 919 KM_SLEEP); 920 port->p_rx_buf = kmem_zalloc(sizeof (yge_buf_t) * YGE_RX_RING_CNT, 921 KM_SLEEP); 922 923 /* Setup Tx/Rx queue register offsets. */ 924 if (port->p_port == YGE_PORT_A) { 925 port->p_txq = Q_XA1; 926 port->p_txsq = Q_XS1; 927 port->p_rxq = Q_R1; 928 } else { 929 port->p_txq = Q_XA2; 930 port->p_txsq = Q_XS2; 931 port->p_rxq = Q_R2; 932 } 933 934 /* Disable jumbo frame for Yukon FE. */ 935 if (dev->d_hw_id == CHIP_ID_YUKON_FE) 936 port->p_flags |= PORT_FLAG_NOJUMBO; 937 938 /* 939 * Start out assuming a regular MTU. Users can change this 940 * with dladm. The dladm daemon is supposed to issue commands 941 * to change the default MTU using m_setprop during early boot 942 * (before the interface is plumbed) if the user has so 943 * requested. 944 */ 945 port->p_mtu = ETHERMTU; 946 947 port->p_mii = mii_alloc(port, dev->d_dip, &yge_mii_ops); 948 if (port->p_mii == NULL) { 949 yge_error(NULL, port, "MII handle allocation failed"); 950 return (DDI_FAILURE); 951 } 952 /* We assume all parts support asymmetric pause */ 953 mii_set_pauseable(port->p_mii, B_TRUE, B_TRUE); 954 955 /* 956 * Get station address for this interface. Note that 957 * dual port cards actually come with three station 958 * addresses: one for each port, plus an extra. The 959 * extra one is used by the SysKonnect driver software 960 * as a 'virtual' station address for when both ports 961 * are operating in failover mode. Currently we don't 962 * use this extra address. 963 */ 964 for (i = 0; i < ETHERADDRL; i++) { 965 port->p_curraddr[i] = 966 CSR_READ_1(dev, B2_MAC_1 + (port->p_port * 8) + i); 967 } 968 969 /* Register with Nemo. */ 970 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 971 yge_error(NULL, port, "MAC handle allocation failed"); 972 return (DDI_FAILURE); 973 } 974 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 975 macp->m_driver = port; 976 macp->m_dip = dev->d_dip; 977 macp->m_src_addr = port->p_curraddr; 978 macp->m_callbacks = &yge_m_callbacks; 979 macp->m_min_sdu = 0; 980 macp->m_max_sdu = port->p_mtu; 981 macp->m_instance = port->p_ppa; 982 macp->m_margin = VLAN_TAGSZ; 983 984 port->p_mreg = macp; 985 986 return (DDI_SUCCESS); 987 } 988 989 static int 990 yge_add_intr(yge_dev_t *dev, int intr_type) 991 { 992 dev_info_t *dip; 993 int count; 994 int actual; 995 int rv; 996 int i, j; 997 998 dip = dev->d_dip; 999 1000 rv = ddi_intr_get_nintrs(dip, intr_type, &count); 1001 if ((rv != DDI_SUCCESS) || (count == 0)) { 1002 yge_error(dev, NULL, 1003 "ddi_intr_get_nintrs failed, rv %d, count %d", rv, count); 1004 return (DDI_FAILURE); 1005 } 1006 1007 /* 1008 * Allocate the interrupt. Note that we only bother with a single 1009 * interrupt. One could argue that for MSI devices with dual ports, 1010 * it would be nice to have a separate interrupt per port. But right 1011 * now I don't know how to configure that, so we'll just settle for 1012 * a single interrupt. 1013 */ 1014 dev->d_intrcnt = 1; 1015 1016 dev->d_intrsize = count * sizeof (ddi_intr_handle_t); 1017 dev->d_intrh = kmem_zalloc(dev->d_intrsize, KM_SLEEP); 1018 if (dev->d_intrh == NULL) { 1019 yge_error(dev, NULL, "Unable to allocate interrupt handle"); 1020 return (DDI_FAILURE); 1021 } 1022 1023 rv = ddi_intr_alloc(dip, dev->d_intrh, intr_type, 0, dev->d_intrcnt, 1024 &actual, DDI_INTR_ALLOC_STRICT); 1025 if ((rv != DDI_SUCCESS) || (actual == 0)) { 1026 yge_error(dev, NULL, 1027 "Unable to allocate interrupt, %d, count %d", 1028 rv, actual); 1029 kmem_free(dev->d_intrh, dev->d_intrsize); 1030 return (DDI_FAILURE); 1031 } 1032 1033 if ((rv = ddi_intr_get_pri(dev->d_intrh[0], &dev->d_intrpri)) != 1034 DDI_SUCCESS) { 1035 for (i = 0; i < dev->d_intrcnt; i++) 1036 (void) ddi_intr_free(dev->d_intrh[i]); 1037 yge_error(dev, NULL, 1038 "Unable to get interrupt priority, %d", rv); 1039 kmem_free(dev->d_intrh, dev->d_intrsize); 1040 return (DDI_FAILURE); 1041 } 1042 1043 if ((rv = ddi_intr_get_cap(dev->d_intrh[0], &dev->d_intrcap)) != 1044 DDI_SUCCESS) { 1045 yge_error(dev, NULL, 1046 "Unable to get interrupt capabilities, %d", rv); 1047 for (i = 0; i < dev->d_intrcnt; i++) 1048 (void) ddi_intr_free(dev->d_intrh[i]); 1049 kmem_free(dev->d_intrh, dev->d_intrsize); 1050 return (DDI_FAILURE); 1051 } 1052 1053 /* register interrupt handler to kernel */ 1054 for (i = 0; i < dev->d_intrcnt; i++) { 1055 if ((rv = ddi_intr_add_handler(dev->d_intrh[i], yge_intr, 1056 dev, NULL)) != DDI_SUCCESS) { 1057 yge_error(dev, NULL, 1058 "Unable to add interrupt handler, %d", rv); 1059 for (j = 0; j < i; j++) 1060 (void) ddi_intr_remove_handler(dev->d_intrh[j]); 1061 for (i = 0; i < dev->d_intrcnt; i++) 1062 (void) ddi_intr_free(dev->d_intrh[i]); 1063 kmem_free(dev->d_intrh, dev->d_intrsize); 1064 return (DDI_FAILURE); 1065 } 1066 } 1067 1068 mutex_init(&dev->d_rxlock, NULL, MUTEX_DRIVER, 1069 DDI_INTR_PRI(dev->d_intrpri)); 1070 mutex_init(&dev->d_txlock, NULL, MUTEX_DRIVER, 1071 DDI_INTR_PRI(dev->d_intrpri)); 1072 mutex_init(&dev->d_phylock, NULL, MUTEX_DRIVER, 1073 DDI_INTR_PRI(dev->d_intrpri)); 1074 mutex_init(&dev->d_task_mtx, NULL, MUTEX_DRIVER, 1075 DDI_INTR_PRI(dev->d_intrpri)); 1076 1077 return (DDI_SUCCESS); 1078 } 1079 1080 static int 1081 yge_attach_intr(yge_dev_t *dev) 1082 { 1083 dev_info_t *dip = dev->d_dip; 1084 int intr_types; 1085 int rv; 1086 1087 /* Allocate IRQ resources. */ 1088 rv = ddi_intr_get_supported_types(dip, &intr_types); 1089 if (rv != DDI_SUCCESS) { 1090 yge_error(dev, NULL, 1091 "Unable to determine supported interrupt types, %d", rv); 1092 return (DDI_FAILURE); 1093 } 1094 1095 /* 1096 * We default to not supporting MSI. We've found some device 1097 * and motherboard combinations don't always work well with 1098 * MSI interrupts. Users may override this if they choose. 1099 */ 1100 if (ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, "msi_enable", 0) == 0) { 1101 /* If msi disable property present, disable both msix/msi. */ 1102 if (intr_types & DDI_INTR_TYPE_FIXED) { 1103 intr_types &= ~(DDI_INTR_TYPE_MSI | DDI_INTR_TYPE_MSIX); 1104 } 1105 } 1106 1107 if (intr_types & DDI_INTR_TYPE_MSIX) { 1108 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_MSIX)) == 1109 DDI_SUCCESS) 1110 return (DDI_SUCCESS); 1111 } 1112 1113 if (intr_types & DDI_INTR_TYPE_MSI) { 1114 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_MSI)) == 1115 DDI_SUCCESS) 1116 return (DDI_SUCCESS); 1117 } 1118 1119 if (intr_types & DDI_INTR_TYPE_FIXED) { 1120 if ((rv = yge_add_intr(dev, DDI_INTR_TYPE_FIXED)) == 1121 DDI_SUCCESS) 1122 return (DDI_SUCCESS); 1123 } 1124 1125 yge_error(dev, NULL, "Unable to configure any interrupts"); 1126 return (DDI_FAILURE); 1127 } 1128 1129 static void 1130 yge_intr_enable(yge_dev_t *dev) 1131 { 1132 int i; 1133 if (dev->d_intrcap & DDI_INTR_FLAG_BLOCK) { 1134 /* Call ddi_intr_block_enable() for MSI interrupts */ 1135 (void) ddi_intr_block_enable(dev->d_intrh, dev->d_intrcnt); 1136 } else { 1137 /* Call ddi_intr_enable for FIXED interrupts */ 1138 for (i = 0; i < dev->d_intrcnt; i++) 1139 (void) ddi_intr_enable(dev->d_intrh[i]); 1140 } 1141 } 1142 1143 void 1144 yge_intr_disable(yge_dev_t *dev) 1145 { 1146 int i; 1147 1148 if (dev->d_intrcap & DDI_INTR_FLAG_BLOCK) { 1149 (void) ddi_intr_block_disable(dev->d_intrh, dev->d_intrcnt); 1150 } else { 1151 for (i = 0; i < dev->d_intrcnt; i++) 1152 (void) ddi_intr_disable(dev->d_intrh[i]); 1153 } 1154 } 1155 1156 static uint8_t 1157 yge_find_capability(yge_dev_t *dev, uint8_t cap) 1158 { 1159 uint8_t ptr; 1160 uint16_t capit; 1161 ddi_acc_handle_t pcih = dev->d_pcih; 1162 1163 if ((pci_config_get16(pcih, PCI_CONF_STAT) & PCI_STAT_CAP) == 0) { 1164 return (0); 1165 } 1166 /* This assumes PCI, and not CardBus. */ 1167 ptr = pci_config_get8(pcih, PCI_CONF_CAP_PTR); 1168 while (ptr != 0) { 1169 capit = pci_config_get8(pcih, ptr + PCI_CAP_ID); 1170 if (capit == cap) { 1171 return (ptr); 1172 } 1173 ptr = pci_config_get8(pcih, ptr + PCI_CAP_NEXT_PTR); 1174 } 1175 return (0); 1176 } 1177 1178 static int 1179 yge_attach(yge_dev_t *dev) 1180 { 1181 dev_info_t *dip = dev->d_dip; 1182 int rv; 1183 int nattached; 1184 uint8_t pm_cap; 1185 1186 if (pci_config_setup(dip, &dev->d_pcih) != DDI_SUCCESS) { 1187 yge_error(dev, NULL, "Unable to map PCI configuration space"); 1188 goto fail; 1189 } 1190 1191 /* 1192 * Map control/status registers. 1193 */ 1194 1195 /* ensure the pmcsr status is D0 state */ 1196 pm_cap = yge_find_capability(dev, PCI_CAP_ID_PM); 1197 if (pm_cap != 0) { 1198 uint16_t pmcsr; 1199 pmcsr = pci_config_get16(dev->d_pcih, pm_cap + PCI_PMCSR); 1200 pmcsr &= ~PCI_PMCSR_STATE_MASK; 1201 pci_config_put16(dev->d_pcih, pm_cap + PCI_PMCSR, 1202 pmcsr | PCI_PMCSR_D0); 1203 } 1204 1205 /* Enable PCI access and bus master. */ 1206 pci_config_put16(dev->d_pcih, PCI_CONF_COMM, 1207 pci_config_get16(dev->d_pcih, PCI_CONF_COMM) | 1208 PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME); 1209 1210 1211 /* Allocate I/O resource */ 1212 rv = ddi_regs_map_setup(dip, 1, &dev->d_regs, 0, 0, &yge_regs_attr, 1213 &dev->d_regsh); 1214 if (rv != DDI_SUCCESS) { 1215 yge_error(dev, NULL, "Unable to map device registers"); 1216 goto fail; 1217 } 1218 1219 1220 /* Enable all clocks. */ 1221 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1222 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); 1223 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1224 1225 CSR_WRITE_2(dev, B0_CTST, CS_RST_CLR); 1226 dev->d_hw_id = CSR_READ_1(dev, B2_CHIP_ID); 1227 dev->d_hw_rev = (CSR_READ_1(dev, B2_MAC_CFG) >> 4) & 0x0f; 1228 1229 1230 /* 1231 * Bail out if chip is not recognized. Note that we only enforce 1232 * this in production builds. The Ultra-2 (88e8057) has a problem 1233 * right now where TX works fine, but RX seems not to. So we've 1234 * disabled that for now. 1235 */ 1236 if (dev->d_hw_id < CHIP_ID_YUKON_XL || 1237 dev->d_hw_id >= CHIP_ID_YUKON_UL_2) { 1238 yge_error(dev, NULL, "Unknown device: id=0x%02x, rev=0x%02x", 1239 dev->d_hw_id, dev->d_hw_rev); 1240 #ifndef DEBUG 1241 goto fail; 1242 #endif 1243 } 1244 1245 /* Soft reset. */ 1246 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET); 1247 CSR_WRITE_2(dev, B0_CTST, CS_RST_CLR); 1248 dev->d_pmd = CSR_READ_1(dev, B2_PMD_TYP); 1249 if (dev->d_pmd == 'L' || dev->d_pmd == 'S' || dev->d_pmd == 'P') 1250 dev->d_coppertype = 0; 1251 else 1252 dev->d_coppertype = 1; 1253 /* Check number of MACs. */ 1254 dev->d_num_port = 1; 1255 if ((CSR_READ_1(dev, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1256 CFG_DUAL_MAC_MSK) { 1257 if (!(CSR_READ_1(dev, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1258 dev->d_num_port++; 1259 } 1260 1261 /* Check bus type. */ 1262 if (yge_find_capability(dev, PCI_CAP_ID_PCI_E) != 0) { 1263 dev->d_bustype = PEX_BUS; 1264 } else if (yge_find_capability(dev, PCI_CAP_ID_PCIX) != 0) { 1265 dev->d_bustype = PCIX_BUS; 1266 } else { 1267 dev->d_bustype = PCI_BUS; 1268 } 1269 1270 switch (dev->d_hw_id) { 1271 case CHIP_ID_YUKON_EC: 1272 dev->d_clock = 125; /* 125 Mhz */ 1273 break; 1274 case CHIP_ID_YUKON_UL_2: 1275 dev->d_clock = 125; /* 125 Mhz */ 1276 break; 1277 case CHIP_ID_YUKON_SUPR: 1278 dev->d_clock = 125; /* 125 Mhz */ 1279 break; 1280 case CHIP_ID_YUKON_EC_U: 1281 dev->d_clock = 125; /* 125 Mhz */ 1282 break; 1283 case CHIP_ID_YUKON_EX: 1284 dev->d_clock = 125; /* 125 Mhz */ 1285 break; 1286 case CHIP_ID_YUKON_FE: 1287 dev->d_clock = 100; /* 100 Mhz */ 1288 break; 1289 case CHIP_ID_YUKON_FE_P: 1290 dev->d_clock = 50; /* 50 Mhz */ 1291 break; 1292 case CHIP_ID_YUKON_XL: 1293 dev->d_clock = 156; /* 156 Mhz */ 1294 break; 1295 default: 1296 dev->d_clock = 156; /* 156 Mhz */ 1297 break; 1298 } 1299 1300 dev->d_process_limit = YGE_RX_RING_CNT/2; 1301 1302 rv = yge_alloc_ring(NULL, dev, &dev->d_status_ring, YGE_STAT_RING_CNT); 1303 if (rv != DDI_SUCCESS) 1304 goto fail; 1305 1306 /* Setup event taskq. */ 1307 dev->d_task_q = ddi_taskq_create(dip, "tq", 1, TASKQ_DEFAULTPRI, 0); 1308 if (dev->d_task_q == NULL) { 1309 yge_error(dev, NULL, "failed to create taskq"); 1310 goto fail; 1311 } 1312 1313 /* Init the condition variable */ 1314 cv_init(&dev->d_task_cv, NULL, CV_DRIVER, NULL); 1315 1316 /* Allocate IRQ resources. */ 1317 if ((rv = yge_attach_intr(dev)) != DDI_SUCCESS) { 1318 goto fail; 1319 } 1320 1321 /* Set base interrupt mask. */ 1322 dev->d_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1323 dev->d_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1324 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1325 1326 /* Reset the adapter. */ 1327 yge_reset(dev); 1328 1329 yge_setup_rambuffer(dev); 1330 1331 nattached = 0; 1332 for (int i = 0; i < dev->d_num_port; i++) { 1333 yge_port_t *port = dev->d_port[i]; 1334 if (yge_init_port(port) != DDI_SUCCESS) { 1335 goto fail; 1336 } 1337 } 1338 1339 yge_intr_enable(dev); 1340 1341 /* set up the periodic to run once per second */ 1342 dev->d_periodic = ddi_periodic_add(yge_tick, dev, 1000000000, 0); 1343 1344 for (int i = 0; i < dev->d_num_port; i++) { 1345 yge_port_t *port = dev->d_port[i]; 1346 if (yge_register_port(port) == DDI_SUCCESS) { 1347 nattached++; 1348 } 1349 } 1350 1351 if (nattached == 0) { 1352 goto fail; 1353 } 1354 1355 /* Dispatch the taskq */ 1356 if (ddi_taskq_dispatch(dev->d_task_q, yge_task, dev, DDI_SLEEP) != 1357 DDI_SUCCESS) { 1358 yge_error(dev, NULL, "failed to start taskq"); 1359 goto fail; 1360 } 1361 1362 ddi_report_dev(dip); 1363 1364 return (DDI_SUCCESS); 1365 1366 fail: 1367 yge_detach(dev); 1368 return (DDI_FAILURE); 1369 } 1370 1371 static int 1372 yge_register_port(yge_port_t *port) 1373 { 1374 if (mac_register(port->p_mreg, &port->p_mh) != DDI_SUCCESS) { 1375 yge_error(NULL, port, "MAC registration failed"); 1376 return (DDI_FAILURE); 1377 } 1378 1379 return (DDI_SUCCESS); 1380 } 1381 1382 /* 1383 * Free up port specific resources. This is called only when the 1384 * port is not registered (and hence not running). 1385 */ 1386 static void 1387 yge_uninit_port(yge_port_t *port) 1388 { 1389 ASSERT(!port->p_running); 1390 1391 if (port->p_mreg) 1392 mac_free(port->p_mreg); 1393 1394 if (port->p_mii) 1395 mii_free(port->p_mii); 1396 1397 yge_txrx_dma_free(port); 1398 1399 if (port->p_tx_buf) 1400 kmem_free(port->p_tx_buf, 1401 sizeof (yge_buf_t) * YGE_TX_RING_CNT); 1402 if (port->p_rx_buf) 1403 kmem_free(port->p_rx_buf, 1404 sizeof (yge_buf_t) * YGE_RX_RING_CNT); 1405 } 1406 1407 static void 1408 yge_detach(yge_dev_t *dev) 1409 { 1410 /* 1411 * Turn off the periodic. 1412 */ 1413 if (dev->d_periodic) 1414 ddi_periodic_delete(dev->d_periodic); 1415 1416 for (int i = 0; i < dev->d_num_port; i++) { 1417 yge_uninit_port(dev->d_port[i]); 1418 } 1419 1420 /* 1421 * Make sure all interrupts are disabled. 1422 */ 1423 CSR_WRITE_4(dev, B0_IMSK, 0); 1424 (void) CSR_READ_4(dev, B0_IMSK); 1425 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); 1426 (void) CSR_READ_4(dev, B0_HWE_IMSK); 1427 1428 /* LED Off. */ 1429 CSR_WRITE_2(dev, B0_CTST, Y2_LED_STAT_OFF); 1430 1431 /* Put hardware reset. */ 1432 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET); 1433 1434 yge_free_ring(&dev->d_status_ring); 1435 1436 if (dev->d_task_q != NULL) { 1437 yge_dispatch(dev, YGE_TASK_EXIT); 1438 ddi_taskq_destroy(dev->d_task_q); 1439 dev->d_task_q = NULL; 1440 } 1441 1442 cv_destroy(&dev->d_task_cv); 1443 1444 yge_intr_disable(dev); 1445 1446 if (dev->d_intrh != NULL) { 1447 for (int i = 0; i < dev->d_intrcnt; i++) { 1448 (void) ddi_intr_remove_handler(dev->d_intrh[i]); 1449 (void) ddi_intr_free(dev->d_intrh[i]); 1450 } 1451 kmem_free(dev->d_intrh, dev->d_intrsize); 1452 mutex_destroy(&dev->d_phylock); 1453 mutex_destroy(&dev->d_txlock); 1454 mutex_destroy(&dev->d_rxlock); 1455 mutex_destroy(&dev->d_task_mtx); 1456 } 1457 if (dev->d_regsh != NULL) 1458 ddi_regs_map_free(&dev->d_regsh); 1459 1460 if (dev->d_pcih != NULL) 1461 pci_config_teardown(&dev->d_pcih); 1462 } 1463 1464 static int 1465 yge_alloc_ring(yge_port_t *port, yge_dev_t *dev, yge_ring_t *ring, uint32_t num) 1466 { 1467 dev_info_t *dip; 1468 caddr_t kaddr; 1469 size_t len; 1470 int rv; 1471 ddi_dma_cookie_t dmac; 1472 unsigned ndmac; 1473 1474 if (port && !dev) 1475 dev = port->p_dev; 1476 dip = dev->d_dip; 1477 1478 ring->r_num = num; 1479 1480 rv = ddi_dma_alloc_handle(dip, &yge_ring_dma_attr, DDI_DMA_DONTWAIT, 1481 NULL, &ring->r_dmah); 1482 if (rv != DDI_SUCCESS) { 1483 yge_error(dev, port, "Unable to allocate ring DMA handle"); 1484 return (DDI_FAILURE); 1485 } 1486 1487 rv = ddi_dma_mem_alloc(ring->r_dmah, num * sizeof (yge_desc_t), 1488 &yge_ring_attr, DDI_DMA_CONSISTENT, DDI_DMA_DONTWAIT, NULL, 1489 &kaddr, &len, &ring->r_acch); 1490 if (rv != DDI_SUCCESS) { 1491 yge_error(dev, port, "Unable to allocate ring DMA memory"); 1492 return (DDI_FAILURE); 1493 } 1494 ring->r_size = len; 1495 ring->r_kaddr = (void *)kaddr; 1496 1497 bzero(kaddr, len); 1498 1499 rv = ddi_dma_addr_bind_handle(ring->r_dmah, NULL, kaddr, 1500 len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 1501 &dmac, &ndmac); 1502 if (rv != DDI_DMA_MAPPED) { 1503 yge_error(dev, port, "Unable to bind ring DMA handle"); 1504 return (DDI_FAILURE); 1505 } 1506 ASSERT(ndmac == 1); 1507 ring->r_paddr = dmac.dmac_address; 1508 1509 return (DDI_SUCCESS); 1510 } 1511 1512 static void 1513 yge_free_ring(yge_ring_t *ring) 1514 { 1515 if (ring->r_paddr) 1516 (void) ddi_dma_unbind_handle(ring->r_dmah); 1517 ring->r_paddr = 0; 1518 if (ring->r_acch) 1519 ddi_dma_mem_free(&ring->r_acch); 1520 ring->r_kaddr = NULL; 1521 ring->r_acch = NULL; 1522 if (ring->r_dmah) 1523 ddi_dma_free_handle(&ring->r_dmah); 1524 ring->r_dmah = NULL; 1525 } 1526 1527 static int 1528 yge_alloc_buf(yge_port_t *port, yge_buf_t *b, size_t bufsz, int flag) 1529 { 1530 yge_dev_t *dev = port->p_dev; 1531 size_t l; 1532 int sflag; 1533 int rv; 1534 ddi_dma_cookie_t dmac; 1535 unsigned ndmac; 1536 1537 sflag = flag & (DDI_DMA_STREAMING | DDI_DMA_CONSISTENT); 1538 1539 /* Now allocate Tx buffers. */ 1540 rv = ddi_dma_alloc_handle(dev->d_dip, &yge_buf_dma_attr, 1541 DDI_DMA_DONTWAIT, NULL, &b->b_dmah); 1542 if (rv != DDI_SUCCESS) { 1543 yge_error(NULL, port, "Unable to alloc DMA handle for buffer"); 1544 return (DDI_FAILURE); 1545 } 1546 1547 rv = ddi_dma_mem_alloc(b->b_dmah, bufsz, &yge_buf_attr, 1548 sflag, DDI_DMA_DONTWAIT, NULL, &b->b_buf, &l, &b->b_acch); 1549 if (rv != DDI_SUCCESS) { 1550 yge_error(NULL, port, "Unable to alloc DMA memory for buffer"); 1551 return (DDI_FAILURE); 1552 } 1553 1554 rv = ddi_dma_addr_bind_handle(b->b_dmah, NULL, b->b_buf, l, flag, 1555 DDI_DMA_DONTWAIT, NULL, &dmac, &ndmac); 1556 if (rv != DDI_DMA_MAPPED) { 1557 yge_error(NULL, port, "Unable to bind DMA handle for buffer"); 1558 return (DDI_FAILURE); 1559 } 1560 ASSERT(ndmac == 1); 1561 b->b_paddr = dmac.dmac_address; 1562 return (DDI_SUCCESS); 1563 } 1564 1565 static void 1566 yge_free_buf(yge_buf_t *b) 1567 { 1568 if (b->b_paddr) 1569 (void) ddi_dma_unbind_handle(b->b_dmah); 1570 b->b_paddr = 0; 1571 if (b->b_acch) 1572 ddi_dma_mem_free(&b->b_acch); 1573 b->b_buf = NULL; 1574 b->b_acch = NULL; 1575 if (b->b_dmah) 1576 ddi_dma_free_handle(&b->b_dmah); 1577 b->b_dmah = NULL; 1578 } 1579 1580 static int 1581 yge_txrx_dma_alloc(yge_port_t *port) 1582 { 1583 uint32_t bufsz; 1584 int rv; 1585 int i; 1586 yge_buf_t *b; 1587 1588 /* 1589 * It seems that Yukon II supports full 64 bit DMA operations. 1590 * But we limit it to 32 bits only for now. The 64 bit 1591 * operation would require substantially more complex 1592 * descriptor handling, since in such a case we would need two 1593 * LEs to represent a single physical address. 1594 * 1595 * If we find that this is limiting us, then we should go back 1596 * and re-examine it. 1597 */ 1598 1599 /* Note our preferred buffer size. */ 1600 bufsz = port->p_mtu; 1601 1602 /* Allocate Tx ring. */ 1603 rv = yge_alloc_ring(port, NULL, &port->p_tx_ring, YGE_TX_RING_CNT); 1604 if (rv != DDI_SUCCESS) { 1605 return (DDI_FAILURE); 1606 } 1607 1608 /* Now allocate Tx buffers. */ 1609 b = port->p_tx_buf; 1610 for (i = 0; i < YGE_TX_RING_CNT; i++) { 1611 rv = yge_alloc_buf(port, b, bufsz, 1612 DDI_DMA_STREAMING | DDI_DMA_WRITE); 1613 if (rv != DDI_SUCCESS) { 1614 return (DDI_FAILURE); 1615 } 1616 b++; 1617 } 1618 1619 /* Allocate Rx ring. */ 1620 rv = yge_alloc_ring(port, NULL, &port->p_rx_ring, YGE_RX_RING_CNT); 1621 if (rv != DDI_SUCCESS) { 1622 return (DDI_FAILURE); 1623 } 1624 1625 /* Now allocate Rx buffers. */ 1626 b = port->p_rx_buf; 1627 for (i = 0; i < YGE_RX_RING_CNT; i++) { 1628 rv = yge_alloc_buf(port, b, bufsz, 1629 DDI_DMA_STREAMING | DDI_DMA_READ); 1630 if (rv != DDI_SUCCESS) { 1631 return (DDI_FAILURE); 1632 } 1633 b++; 1634 } 1635 1636 return (DDI_SUCCESS); 1637 } 1638 1639 static void 1640 yge_txrx_dma_free(yge_port_t *port) 1641 { 1642 yge_buf_t *b; 1643 1644 /* Tx ring. */ 1645 yge_free_ring(&port->p_tx_ring); 1646 1647 /* Rx ring. */ 1648 yge_free_ring(&port->p_rx_ring); 1649 1650 /* Tx buffers. */ 1651 b = port->p_tx_buf; 1652 for (int i = 0; i < YGE_TX_RING_CNT; i++, b++) { 1653 yge_free_buf(b); 1654 } 1655 /* Rx buffers. */ 1656 b = port->p_rx_buf; 1657 for (int i = 0; i < YGE_RX_RING_CNT; i++, b++) { 1658 yge_free_buf(b); 1659 } 1660 } 1661 1662 boolean_t 1663 yge_send(yge_port_t *port, mblk_t *mp) 1664 { 1665 yge_ring_t *ring = &port->p_tx_ring; 1666 yge_buf_t *txb; 1667 int16_t prod; 1668 size_t len; 1669 1670 /* 1671 * For now we're not going to support checksum offload or LSO. 1672 */ 1673 1674 len = msgsize(mp); 1675 if (len > port->p_framesize) { 1676 /* too big! */ 1677 freemsg(mp); 1678 return (B_TRUE); 1679 } 1680 1681 /* Check number of available descriptors. */ 1682 if (port->p_tx_cnt + 1 >= 1683 (YGE_TX_RING_CNT - YGE_RESERVED_TX_DESC_CNT)) { 1684 port->p_wantw = B_TRUE; 1685 return (B_FALSE); 1686 } 1687 1688 prod = port->p_tx_prod; 1689 1690 txb = &port->p_tx_buf[prod]; 1691 mcopymsg(mp, txb->b_buf); 1692 SYNCBUF(txb, DDI_DMA_SYNC_FORDEV); 1693 1694 PUTADDR(ring, prod, txb->b_paddr); 1695 PUTCTRL(ring, prod, len | OP_PACKET | HW_OWNER | EOP); 1696 SYNCENTRY(ring, prod, DDI_DMA_SYNC_FORDEV); 1697 port->p_tx_cnt++; 1698 1699 YGE_INC(prod, YGE_TX_RING_CNT); 1700 1701 /* Update producer index. */ 1702 port->p_tx_prod = prod; 1703 1704 return (B_TRUE); 1705 } 1706 1707 static int 1708 yge_suspend(yge_dev_t *dev) 1709 { 1710 for (int i = 0; i < dev->d_num_port; i++) { 1711 yge_port_t *port = dev->d_port[i]; 1712 mii_suspend(port->p_mii); 1713 } 1714 1715 1716 DEV_LOCK(dev); 1717 1718 for (int i = 0; i < dev->d_num_port; i++) { 1719 yge_port_t *port = dev->d_port[i]; 1720 1721 if (port->p_running) { 1722 yge_stop_port(port); 1723 } 1724 } 1725 1726 /* Disable all interrupts. */ 1727 CSR_WRITE_4(dev, B0_IMSK, 0); 1728 (void) CSR_READ_4(dev, B0_IMSK); 1729 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); 1730 (void) CSR_READ_4(dev, B0_HWE_IMSK); 1731 1732 yge_phy_power(dev, B_FALSE); 1733 1734 /* Put hardware reset. */ 1735 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET); 1736 dev->d_suspended = B_TRUE; 1737 1738 DEV_UNLOCK(dev); 1739 1740 return (DDI_SUCCESS); 1741 } 1742 1743 static int 1744 yge_resume(yge_dev_t *dev) 1745 { 1746 uint8_t pm_cap; 1747 1748 DEV_LOCK(dev); 1749 1750 /* ensure the pmcsr status is D0 state */ 1751 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1752 1753 if ((pm_cap = yge_find_capability(dev, PCI_CAP_ID_PM)) != 0) { 1754 uint16_t pmcsr; 1755 pmcsr = pci_config_get16(dev->d_pcih, pm_cap + PCI_PMCSR); 1756 pmcsr &= ~PCI_PMCSR_STATE_MASK; 1757 pci_config_put16(dev->d_pcih, pm_cap + PCI_PMCSR, 1758 pmcsr | PCI_PMCSR_D0); 1759 } 1760 1761 /* Enable PCI access and bus master. */ 1762 pci_config_put16(dev->d_pcih, PCI_CONF_COMM, 1763 pci_config_get16(dev->d_pcih, PCI_CONF_COMM) | 1764 PCI_COMM_IO | PCI_COMM_MAE | PCI_COMM_ME); 1765 1766 /* Enable all clocks. */ 1767 switch (dev->d_hw_id) { 1768 case CHIP_ID_YUKON_EX: 1769 case CHIP_ID_YUKON_EC_U: 1770 case CHIP_ID_YUKON_FE_P: 1771 pci_config_put32(dev->d_pcih, PCI_OUR_REG_3, 0); 1772 break; 1773 } 1774 1775 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1776 1777 yge_reset(dev); 1778 1779 /* Make sure interrupts are reenabled */ 1780 CSR_WRITE_4(dev, B0_IMSK, 0); 1781 CSR_WRITE_4(dev, B0_IMSK, Y2_IS_HW_ERR | Y2_IS_STAT_BMU); 1782 CSR_WRITE_4(dev, B0_HWE_IMSK, 1783 Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1784 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP); 1785 1786 for (int i = 0; i < dev->d_num_port; i++) { 1787 yge_port_t *port = dev->d_port[i]; 1788 1789 if (port != NULL && port->p_running) { 1790 yge_start_port(port); 1791 } 1792 } 1793 dev->d_suspended = B_FALSE; 1794 1795 DEV_UNLOCK(dev); 1796 1797 /* Reset MII layer */ 1798 for (int i = 0; i < dev->d_num_port; i++) { 1799 yge_port_t *port = dev->d_port[i]; 1800 1801 if (port->p_running) { 1802 mii_resume(port->p_mii); 1803 mac_tx_update(port->p_mh); 1804 } 1805 } 1806 1807 return (DDI_SUCCESS); 1808 } 1809 1810 static mblk_t * 1811 yge_rxeof(yge_port_t *port, uint32_t status, int len) 1812 { 1813 yge_dev_t *dev = port->p_dev; 1814 mblk_t *mp; 1815 int cons, rxlen; 1816 yge_buf_t *rxb; 1817 yge_ring_t *ring; 1818 1819 ASSERT(mutex_owned(&dev->d_rxlock)); 1820 1821 if (!port->p_running) 1822 return (NULL); 1823 1824 ring = &port->p_rx_ring; 1825 cons = port->p_rx_cons; 1826 rxlen = status >> 16; 1827 rxb = &port->p_rx_buf[cons]; 1828 mp = NULL; 1829 1830 1831 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) && 1832 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) { 1833 /* 1834 * Apparently the status for this chip is not reliable. 1835 * Only perform minimal consistency checking; the MAC 1836 * and upper protocols will have to filter any garbage. 1837 */ 1838 if ((len > port->p_framesize) || (rxlen != len)) { 1839 goto bad; 1840 } 1841 } else { 1842 if ((len > port->p_framesize) || (rxlen != len) || 1843 ((status & GMR_FS_ANY_ERR) != 0) || 1844 ((status & GMR_FS_RX_OK) == 0)) { 1845 goto bad; 1846 } 1847 } 1848 1849 if ((mp = allocb(len + YGE_HEADROOM, BPRI_HI)) != NULL) { 1850 1851 /* good packet - yay */ 1852 mp->b_rptr += YGE_HEADROOM; 1853 SYNCBUF(rxb, DDI_DMA_SYNC_FORKERNEL); 1854 bcopy(rxb->b_buf, mp->b_rptr, len); 1855 mp->b_wptr = mp->b_rptr + len; 1856 } else { 1857 port->p_stats.rx_nobuf++; 1858 } 1859 1860 bad: 1861 1862 PUTCTRL(ring, cons, port->p_framesize | OP_PACKET | HW_OWNER); 1863 SYNCENTRY(ring, cons, DDI_DMA_SYNC_FORDEV); 1864 1865 CSR_WRITE_2(dev, 1866 Y2_PREF_Q_ADDR(port->p_rxq, PREF_UNIT_PUT_IDX_REG), 1867 cons); 1868 1869 YGE_INC(port->p_rx_cons, YGE_RX_RING_CNT); 1870 1871 return (mp); 1872 } 1873 1874 static boolean_t 1875 yge_txeof_locked(yge_port_t *port, int idx) 1876 { 1877 int prog; 1878 int16_t cons; 1879 boolean_t resched; 1880 1881 if (!port->p_running) { 1882 return (B_FALSE); 1883 } 1884 1885 cons = port->p_tx_cons; 1886 prog = 0; 1887 for (; cons != idx; YGE_INC(cons, YGE_TX_RING_CNT)) { 1888 if (port->p_tx_cnt <= 0) 1889 break; 1890 prog++; 1891 port->p_tx_cnt--; 1892 /* No need to sync LEs as we didn't update LEs. */ 1893 } 1894 1895 port->p_tx_cons = cons; 1896 1897 if (prog > 0) { 1898 resched = port->p_wantw; 1899 port->p_tx_wdog = 0; 1900 port->p_wantw = B_FALSE; 1901 return (resched); 1902 } else { 1903 return (B_FALSE); 1904 } 1905 } 1906 1907 static void 1908 yge_txeof(yge_port_t *port, int idx) 1909 { 1910 boolean_t resched; 1911 1912 TX_LOCK(port->p_dev); 1913 1914 resched = yge_txeof_locked(port, idx); 1915 1916 TX_UNLOCK(port->p_dev); 1917 1918 if (resched && port->p_running) { 1919 mac_tx_update(port->p_mh); 1920 } 1921 } 1922 1923 static void 1924 yge_restart_task(yge_dev_t *dev) 1925 { 1926 yge_port_t *port; 1927 1928 DEV_LOCK(dev); 1929 1930 /* Cancel pending I/O and free all Rx/Tx buffers. */ 1931 for (int i = 0; i < dev->d_num_port; i++) { 1932 port = dev->d_port[i]; 1933 if (port->p_running) 1934 yge_stop_port(dev->d_port[i]); 1935 } 1936 yge_reset(dev); 1937 for (int i = 0; i < dev->d_num_port; i++) { 1938 port = dev->d_port[i]; 1939 1940 if (port->p_running) 1941 yge_start_port(port); 1942 } 1943 1944 DEV_UNLOCK(dev); 1945 1946 for (int i = 0; i < dev->d_num_port; i++) { 1947 port = dev->d_port[i]; 1948 1949 mii_reset(port->p_mii); 1950 if (port->p_running) 1951 mac_tx_update(port->p_mh); 1952 } 1953 } 1954 1955 static void 1956 yge_tick(void *arg) 1957 { 1958 yge_dev_t *dev = arg; 1959 yge_port_t *port; 1960 boolean_t restart = B_FALSE; 1961 boolean_t resched = B_FALSE; 1962 int idx; 1963 1964 DEV_LOCK(dev); 1965 1966 if (dev->d_suspended) { 1967 DEV_UNLOCK(dev); 1968 return; 1969 } 1970 1971 for (int i = 0; i < dev->d_num_port; i++) { 1972 port = dev->d_port[i]; 1973 1974 if (!port->p_running) 1975 continue; 1976 1977 if (port->p_tx_cnt) { 1978 uint32_t ridx; 1979 1980 /* 1981 * Reclaim first as there is a possibility of losing 1982 * Tx completion interrupts. 1983 */ 1984 ridx = port->p_port == YGE_PORT_A ? 1985 STAT_TXA1_RIDX : STAT_TXA2_RIDX; 1986 idx = CSR_READ_2(dev, ridx); 1987 if (port->p_tx_cons != idx) { 1988 resched = yge_txeof_locked(port, idx); 1989 1990 } else { 1991 1992 /* detect TX hang */ 1993 port->p_tx_wdog++; 1994 if (port->p_tx_wdog > YGE_TX_TIMEOUT) { 1995 port->p_tx_wdog = 0; 1996 yge_error(NULL, port, 1997 "TX hang detected!"); 1998 restart = B_TRUE; 1999 } 2000 } 2001 } 2002 } 2003 2004 DEV_UNLOCK(dev); 2005 if (restart) { 2006 yge_dispatch(dev, YGE_TASK_RESTART); 2007 } else { 2008 if (resched) { 2009 for (int i = 0; i < dev->d_num_port; i++) { 2010 port = dev->d_port[i]; 2011 2012 if (port->p_running) 2013 mac_tx_update(port->p_mh); 2014 } 2015 } 2016 } 2017 } 2018 2019 static int 2020 yge_intr_gmac(yge_port_t *port) 2021 { 2022 yge_dev_t *dev = port->p_dev; 2023 int pnum = port->p_port; 2024 uint8_t status; 2025 int dispatch_wrk = 0; 2026 2027 status = CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC)); 2028 2029 /* GMAC Rx FIFO overrun. */ 2030 if ((status & GM_IS_RX_FF_OR) != 0) { 2031 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_CLI_RX_FO); 2032 yge_error(NULL, port, "Rx FIFO overrun!"); 2033 dispatch_wrk |= YGE_TASK_RESTART; 2034 } 2035 /* GMAC Tx FIFO underrun. */ 2036 if ((status & GM_IS_TX_FF_UR) != 0) { 2037 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_CLI_TX_FU); 2038 yge_error(NULL, port, "Tx FIFO underrun!"); 2039 /* 2040 * In case of Tx underrun, we may need to flush/reset 2041 * Tx MAC but that would also require 2042 * resynchronization with status LEs. Reinitializing 2043 * status LEs would affect the other port in dual MAC 2044 * configuration so it should be avoided if we can. 2045 * Due to lack of documentation it's all vague guess 2046 * but it needs more investigation. 2047 */ 2048 } 2049 return (dispatch_wrk); 2050 } 2051 2052 static void 2053 yge_handle_hwerr(yge_port_t *port, uint32_t status) 2054 { 2055 yge_dev_t *dev = port->p_dev; 2056 2057 if ((status & Y2_IS_PAR_RD1) != 0) { 2058 yge_error(NULL, port, "RAM buffer read parity error"); 2059 /* Clear IRQ. */ 2060 CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL), 2061 RI_CLR_RD_PERR); 2062 } 2063 if ((status & Y2_IS_PAR_WR1) != 0) { 2064 yge_error(NULL, port, "RAM buffer write parity error"); 2065 /* Clear IRQ. */ 2066 CSR_WRITE_2(dev, SELECT_RAM_BUFFER(port->p_port, B3_RI_CTRL), 2067 RI_CLR_WR_PERR); 2068 } 2069 if ((status & Y2_IS_PAR_MAC1) != 0) { 2070 yge_error(NULL, port, "Tx MAC parity error"); 2071 /* Clear IRQ. */ 2072 CSR_WRITE_4(dev, MR_ADDR(port->p_port, TX_GMF_CTRL_T), 2073 GMF_CLI_TX_PE); 2074 } 2075 if ((status & Y2_IS_PAR_RX1) != 0) { 2076 yge_error(NULL, port, "Rx parity error"); 2077 /* Clear IRQ. */ 2078 CSR_WRITE_4(dev, Q_ADDR(port->p_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 2079 } 2080 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 2081 yge_error(NULL, port, "TCP segmentation error"); 2082 /* Clear IRQ. */ 2083 CSR_WRITE_4(dev, Q_ADDR(port->p_txq, Q_CSR), BMU_CLR_IRQ_TCP); 2084 } 2085 } 2086 2087 static void 2088 yge_intr_hwerr(yge_dev_t *dev) 2089 { 2090 uint32_t status; 2091 uint32_t tlphead[4]; 2092 2093 status = CSR_READ_4(dev, B0_HWE_ISRC); 2094 /* Time Stamp timer overflow. */ 2095 if ((status & Y2_IS_TIST_OV) != 0) 2096 CSR_WRITE_1(dev, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 2097 if ((status & Y2_IS_PCI_NEXP) != 0) { 2098 /* 2099 * PCI Express Error occurred which is not described in PEX 2100 * spec. 2101 * This error is also mapped either to Master Abort( 2102 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 2103 * can only be cleared there. 2104 */ 2105 yge_error(dev, NULL, "PCI Express protocol violation error"); 2106 } 2107 2108 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 2109 uint16_t v16; 2110 2111 if ((status & Y2_IS_IRQ_STAT) != 0) 2112 yge_error(dev, NULL, "Unexpected IRQ Status error"); 2113 if ((status & Y2_IS_MST_ERR) != 0) 2114 yge_error(dev, NULL, "Unexpected IRQ Master error"); 2115 /* Reset all bits in the PCI status register. */ 2116 v16 = pci_config_get16(dev->d_pcih, PCI_CONF_STAT); 2117 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2118 pci_config_put16(dev->d_pcih, PCI_CONF_STAT, v16 | 2119 PCI_STAT_S_PERROR | PCI_STAT_S_SYSERR | PCI_STAT_R_MAST_AB | 2120 PCI_STAT_R_TARG_AB | PCI_STAT_PERROR); 2121 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2122 } 2123 2124 /* Check for PCI Express Uncorrectable Error. */ 2125 if ((status & Y2_IS_PCI_EXP) != 0) { 2126 uint32_t v32; 2127 2128 /* 2129 * On PCI Express bus bridges are called root complexes (RC). 2130 * PCI Express errors are recognized by the root complex too, 2131 * which requests the system to handle the problem. After 2132 * error occurrence it may be that no access to the adapter 2133 * may be performed any longer. 2134 */ 2135 2136 v32 = CSR_PCI_READ_4(dev, PEX_UNC_ERR_STAT); 2137 if ((v32 & PEX_UNSUP_REQ) != 0) { 2138 /* Ignore unsupported request error. */ 2139 yge_error(dev, NULL, 2140 "Uncorrectable PCI Express error"); 2141 } 2142 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 2143 int i; 2144 2145 /* Get TLP header form Log Registers. */ 2146 for (i = 0; i < 4; i++) 2147 tlphead[i] = CSR_PCI_READ_4(dev, 2148 PEX_HEADER_LOG + i * 4); 2149 /* Check for vendor defined broadcast message. */ 2150 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 2151 dev->d_intrhwemask &= ~Y2_IS_PCI_EXP; 2152 CSR_WRITE_4(dev, B0_HWE_IMSK, 2153 dev->d_intrhwemask); 2154 (void) CSR_READ_4(dev, B0_HWE_IMSK); 2155 } 2156 } 2157 /* Clear the interrupt. */ 2158 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_ON); 2159 CSR_PCI_WRITE_4(dev, PEX_UNC_ERR_STAT, 0xffffffff); 2160 CSR_WRITE_1(dev, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 2161 } 2162 2163 if ((status & Y2_HWE_L1_MASK) != 0 && dev->d_port[YGE_PORT_A] != NULL) 2164 yge_handle_hwerr(dev->d_port[YGE_PORT_A], status); 2165 if ((status & Y2_HWE_L2_MASK) != 0 && dev->d_port[YGE_PORT_B] != NULL) 2166 yge_handle_hwerr(dev->d_port[YGE_PORT_B], status >> 8); 2167 } 2168 2169 /* 2170 * Returns B_TRUE if there is potentially more work to do. 2171 */ 2172 static boolean_t 2173 yge_handle_events(yge_dev_t *dev, mblk_t **heads, mblk_t **tails, int *txindex) 2174 { 2175 yge_port_t *port; 2176 yge_ring_t *ring; 2177 uint32_t control, status; 2178 int cons, idx, len, pnum; 2179 mblk_t *mp; 2180 uint32_t rxprogs[2]; 2181 2182 rxprogs[0] = rxprogs[1] = 0; 2183 2184 idx = CSR_READ_2(dev, STAT_PUT_IDX); 2185 if (idx == dev->d_stat_cons) { 2186 return (B_FALSE); 2187 } 2188 2189 ring = &dev->d_status_ring; 2190 2191 for (cons = dev->d_stat_cons; cons != idx; ) { 2192 /* Sync status LE. */ 2193 SYNCENTRY(ring, cons, DDI_DMA_SYNC_FORKERNEL); 2194 control = GETCTRL(ring, cons); 2195 if ((control & HW_OWNER) == 0) { 2196 yge_error(dev, NULL, "Status descriptor error: " 2197 "index %d, control %x", cons, control); 2198 break; 2199 } 2200 2201 status = GETSTAT(ring, cons); 2202 2203 control &= ~HW_OWNER; 2204 len = control & STLE_LEN_MASK; 2205 pnum = ((control >> 16) & 0x01); 2206 port = dev->d_port[pnum]; 2207 if (port == NULL) { 2208 yge_error(dev, NULL, "Invalid port opcode: 0x%08x", 2209 control & STLE_OP_MASK); 2210 goto finish; 2211 } 2212 2213 switch (control & STLE_OP_MASK) { 2214 case OP_RXSTAT: 2215 mp = yge_rxeof(port, status, len); 2216 if (mp != NULL) { 2217 if (heads[pnum] == NULL) 2218 heads[pnum] = mp; 2219 else 2220 tails[pnum]->b_next = mp; 2221 tails[pnum] = mp; 2222 } 2223 2224 rxprogs[pnum]++; 2225 break; 2226 2227 case OP_TXINDEXLE: 2228 txindex[0] = status & STLE_TXA1_MSKL; 2229 txindex[1] = 2230 ((status & STLE_TXA2_MSKL) >> STLE_TXA2_SHIFTL) | 2231 ((len & STLE_TXA2_MSKH) << STLE_TXA2_SHIFTH); 2232 break; 2233 default: 2234 yge_error(dev, NULL, "Unhandled opcode: 0x%08x", 2235 control & STLE_OP_MASK); 2236 break; 2237 } 2238 finish: 2239 2240 /* Give it back to HW. */ 2241 PUTCTRL(ring, cons, control); 2242 SYNCENTRY(ring, cons, DDI_DMA_SYNC_FORDEV); 2243 2244 YGE_INC(cons, YGE_STAT_RING_CNT); 2245 if (rxprogs[pnum] > dev->d_process_limit) { 2246 break; 2247 } 2248 } 2249 2250 dev->d_stat_cons = cons; 2251 if (dev->d_stat_cons != CSR_READ_2(dev, STAT_PUT_IDX)) 2252 return (B_TRUE); 2253 else 2254 return (B_FALSE); 2255 } 2256 2257 /*ARGSUSED1*/ 2258 static uint_t 2259 yge_intr(caddr_t arg1, caddr_t arg2) 2260 { 2261 yge_dev_t *dev; 2262 yge_port_t *port1; 2263 yge_port_t *port2; 2264 uint32_t status; 2265 mblk_t *heads[2], *tails[2]; 2266 int txindex[2]; 2267 int dispatch_wrk; 2268 2269 dev = (void *)arg1; 2270 2271 heads[0] = heads[1] = NULL; 2272 tails[0] = tails[1] = NULL; 2273 txindex[0] = txindex[1] = -1; 2274 dispatch_wrk = 0; 2275 2276 port1 = dev->d_port[YGE_PORT_A]; 2277 port2 = dev->d_port[YGE_PORT_B]; 2278 2279 RX_LOCK(dev); 2280 2281 if (dev->d_suspended) { 2282 RX_UNLOCK(dev); 2283 return (DDI_INTR_UNCLAIMED); 2284 } 2285 2286 /* Get interrupt source. */ 2287 status = CSR_READ_4(dev, B0_Y2_SP_ISRC2); 2288 if (status == 0 || status == 0xffffffff || 2289 (status & dev->d_intrmask) == 0) { /* Stray interrupt ? */ 2290 /* Reenable interrupts. */ 2291 CSR_WRITE_4(dev, B0_Y2_SP_ICR, 2); 2292 RX_UNLOCK(dev); 2293 return (DDI_INTR_UNCLAIMED); 2294 } 2295 2296 if ((status & Y2_IS_HW_ERR) != 0) { 2297 yge_intr_hwerr(dev); 2298 } 2299 2300 if (status & Y2_IS_IRQ_MAC1) { 2301 dispatch_wrk |= yge_intr_gmac(port1); 2302 } 2303 if (status & Y2_IS_IRQ_MAC2) { 2304 dispatch_wrk |= yge_intr_gmac(port2); 2305 } 2306 2307 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 2308 yge_error(NULL, status & Y2_IS_CHK_RX1 ? port1 : port2, 2309 "Rx descriptor error"); 2310 dev->d_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 2311 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); 2312 (void) CSR_READ_4(dev, B0_IMSK); 2313 } 2314 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 2315 yge_error(NULL, status & Y2_IS_CHK_TXA1 ? port1 : port2, 2316 "Tx descriptor error"); 2317 dev->d_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 2318 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); 2319 (void) CSR_READ_4(dev, B0_IMSK); 2320 } 2321 2322 /* handle events until it returns false */ 2323 while (yge_handle_events(dev, heads, tails, txindex)) 2324 /* NOP */; 2325 2326 /* Do receive/transmit events */ 2327 if ((status & Y2_IS_STAT_BMU)) { 2328 CSR_WRITE_4(dev, STAT_CTRL, SC_STAT_CLR_IRQ); 2329 } 2330 2331 /* Reenable interrupts. */ 2332 CSR_WRITE_4(dev, B0_Y2_SP_ICR, 2); 2333 2334 RX_UNLOCK(dev); 2335 2336 if (dispatch_wrk) { 2337 yge_dispatch(dev, dispatch_wrk); 2338 } 2339 2340 if (port1->p_running) { 2341 if (txindex[0] >= 0) { 2342 yge_txeof(port1, txindex[0]); 2343 } 2344 if (heads[0]) 2345 mac_rx(port1->p_mh, NULL, heads[0]); 2346 } else { 2347 if (heads[0]) { 2348 mblk_t *mp; 2349 while ((mp = heads[0]) != NULL) { 2350 heads[0] = mp->b_next; 2351 freemsg(mp); 2352 } 2353 } 2354 } 2355 2356 if (port2->p_running) { 2357 if (txindex[1] >= 0) { 2358 yge_txeof(port2, txindex[1]); 2359 } 2360 if (heads[1]) 2361 mac_rx(port2->p_mh, NULL, heads[1]); 2362 } else { 2363 if (heads[1]) { 2364 mblk_t *mp; 2365 while ((mp = heads[1]) != NULL) { 2366 heads[1] = mp->b_next; 2367 freemsg(mp); 2368 } 2369 } 2370 } 2371 2372 return (DDI_INTR_CLAIMED); 2373 } 2374 2375 static void 2376 yge_set_tx_stfwd(yge_port_t *port) 2377 { 2378 yge_dev_t *dev = port->p_dev; 2379 int pnum = port->p_port; 2380 2381 switch (dev->d_hw_id) { 2382 case CHIP_ID_YUKON_EX: 2383 if (dev->d_hw_rev == CHIP_REV_YU_EX_A0) 2384 goto yukon_ex_workaround; 2385 2386 if (port->p_mtu > ETHERMTU) 2387 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), 2388 TX_JUMBO_ENA | TX_STFW_ENA); 2389 else 2390 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), 2391 TX_JUMBO_DIS | TX_STFW_ENA); 2392 break; 2393 default: 2394 yukon_ex_workaround: 2395 if (port->p_mtu > ETHERMTU) { 2396 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 2397 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_AE_THR), 2398 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 2399 /* Disable Store & Forward mode for Tx. */ 2400 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), 2401 TX_JUMBO_ENA | TX_STFW_DIS); 2402 } else { 2403 /* Enable Store & Forward mode for Tx. */ 2404 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), 2405 TX_JUMBO_DIS | TX_STFW_ENA); 2406 } 2407 break; 2408 } 2409 } 2410 2411 static void 2412 yge_start_port(yge_port_t *port) 2413 { 2414 yge_dev_t *dev = port->p_dev; 2415 uint16_t gmac; 2416 int32_t pnum; 2417 int32_t rxq; 2418 int32_t txq; 2419 uint32_t reg; 2420 2421 pnum = port->p_port; 2422 txq = port->p_txq; 2423 rxq = port->p_rxq; 2424 2425 if (port->p_mtu < ETHERMTU) 2426 port->p_framesize = ETHERMTU; 2427 else 2428 port->p_framesize = port->p_mtu; 2429 port->p_framesize += sizeof (struct ether_vlan_header); 2430 2431 /* 2432 * Note for the future, if we enable offloads: 2433 * In Yukon EC Ultra, TSO & checksum offload is not 2434 * supported for jumbo frame. 2435 */ 2436 2437 /* GMAC Control reset */ 2438 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_SET); 2439 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_RST_CLR); 2440 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_F_LOOPB_OFF); 2441 if (dev->d_hw_id == CHIP_ID_YUKON_EX) 2442 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), 2443 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 2444 GMC_BYP_RETR_ON); 2445 /* 2446 * Initialize GMAC first such that speed/duplex/flow-control 2447 * parameters are renegotiated with the interface is brought up. 2448 */ 2449 GMAC_WRITE_2(dev, pnum, GM_GP_CTRL, 0); 2450 2451 /* Dummy read the Interrupt Source Register. */ 2452 (void) CSR_READ_1(dev, MR_ADDR(pnum, GMAC_IRQ_SRC)); 2453 2454 /* Clear MIB stats. */ 2455 yge_stats_clear(port); 2456 2457 /* Disable FCS. */ 2458 GMAC_WRITE_2(dev, pnum, GM_RX_CTRL, GM_RXCR_CRC_DIS); 2459 2460 /* Setup Transmit Control Register. */ 2461 GMAC_WRITE_2(dev, pnum, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 2462 2463 /* Setup Transmit Flow Control Register. */ 2464 GMAC_WRITE_2(dev, pnum, GM_TX_FLOW_CTRL, 0xffff); 2465 2466 /* Setup Transmit Parameter Register. */ 2467 GMAC_WRITE_2(dev, pnum, GM_TX_PARAM, 2468 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 2469 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 2470 2471 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 2472 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 2473 2474 if (port->p_mtu > ETHERMTU) 2475 gmac |= GM_SMOD_JUMBO_ENA; 2476 GMAC_WRITE_2(dev, pnum, GM_SERIAL_MODE, gmac); 2477 2478 /* Disable interrupts for counter overflows. */ 2479 GMAC_WRITE_2(dev, pnum, GM_TX_IRQ_MSK, 0); 2480 GMAC_WRITE_2(dev, pnum, GM_RX_IRQ_MSK, 0); 2481 GMAC_WRITE_2(dev, pnum, GM_TR_IRQ_MSK, 0); 2482 2483 /* Configure Rx MAC FIFO. */ 2484 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET); 2485 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_CLR); 2486 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 2487 if (dev->d_hw_id == CHIP_ID_YUKON_FE_P || 2488 dev->d_hw_id == CHIP_ID_YUKON_EX) 2489 reg |= GMF_RX_OVER_ON; 2490 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), reg); 2491 2492 /* Set receive filter. */ 2493 yge_setrxfilt(port); 2494 2495 /* Flush Rx MAC FIFO on any flow control or error. */ 2496 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); 2497 2498 /* 2499 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 2500 * due to hardware hang on receipt of pause frames. 2501 */ 2502 reg = RX_GMF_FL_THR_DEF + 1; 2503 /* FE+ magic */ 2504 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) && 2505 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) 2506 reg = 0x178; 2507 2508 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_FL_THR), reg); 2509 2510 /* Configure Tx MAC FIFO. */ 2511 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET); 2512 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_CLR); 2513 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_OPER_ON); 2514 2515 /* Disable hardware VLAN tag insertion/stripping. */ 2516 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); 2517 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); 2518 2519 if ((port->p_flags & PORT_FLAG_RAMBUF) == 0) { 2520 /* Set Rx Pause threshold. */ 2521 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) && 2522 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) { 2523 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR), 2524 MSK_ECU_LLPP); 2525 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR), 2526 MSK_FEP_ULPP); 2527 } else { 2528 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_LP_THR), 2529 MSK_ECU_LLPP); 2530 CSR_WRITE_1(dev, MR_ADDR(pnum, RX_GMF_UP_THR), 2531 MSK_ECU_ULPP); 2532 } 2533 /* Configure store-and-forward for TX */ 2534 yge_set_tx_stfwd(port); 2535 } 2536 2537 if ((dev->d_hw_id == CHIP_ID_YUKON_FE_P) && 2538 (dev->d_hw_rev == CHIP_REV_YU_FE2_A0)) { 2539 /* Disable dynamic watermark */ 2540 reg = CSR_READ_4(dev, MR_ADDR(pnum, TX_GMF_EA)); 2541 reg &= ~TX_DYN_WM_ENA; 2542 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_EA), reg); 2543 } 2544 2545 /* 2546 * Disable Force Sync bit and Alloc bit in Tx RAM interface 2547 * arbiter as we don't use Sync Tx queue. 2548 */ 2549 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), 2550 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 2551 /* Enable the RAM Interface Arbiter. */ 2552 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_ENA_ARB); 2553 2554 /* Setup RAM buffer. */ 2555 yge_set_rambuffer(port); 2556 2557 /* Disable Tx sync Queue. */ 2558 CSR_WRITE_1(dev, RB_ADDR(port->p_txsq, RB_CTRL), RB_RST_SET); 2559 2560 /* Setup Tx Queue Bus Memory Interface. */ 2561 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_CLR_RESET); 2562 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_OPER_INIT); 2563 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_FIFO_OP_ON); 2564 CSR_WRITE_2(dev, Q_ADDR(txq, Q_WM), MSK_BMU_TX_WM); 2565 2566 switch (dev->d_hw_id) { 2567 case CHIP_ID_YUKON_EC_U: 2568 if (dev->d_hw_rev == CHIP_REV_YU_EC_U_A0) { 2569 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 2570 CSR_WRITE_2(dev, Q_ADDR(txq, Q_AL), MSK_ECU_TXFF_LEV); 2571 } 2572 break; 2573 case CHIP_ID_YUKON_EX: 2574 /* 2575 * Yukon Extreme seems to have silicon bug for 2576 * automatic Tx checksum calculation capability. 2577 */ 2578 if (dev->d_hw_rev == CHIP_REV_YU_EX_B0) 2579 CSR_WRITE_4(dev, Q_ADDR(txq, Q_F), F_TX_CHK_AUTO_OFF); 2580 break; 2581 } 2582 2583 /* Setup Rx Queue Bus Memory Interface. */ 2584 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_CLR_RESET); 2585 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_OPER_INIT); 2586 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_FIFO_OP_ON); 2587 if (dev->d_bustype == PEX_BUS) { 2588 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), 0x80); 2589 } else { 2590 CSR_WRITE_2(dev, Q_ADDR(rxq, Q_WM), MSK_BMU_RX_WM); 2591 } 2592 if (dev->d_hw_id == CHIP_ID_YUKON_EC_U && 2593 dev->d_hw_rev >= CHIP_REV_YU_EC_U_A1) { 2594 /* MAC Rx RAM Read is controlled by hardware. */ 2595 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); 2596 } 2597 2598 yge_init_tx_ring(port); 2599 2600 /* Disable Rx checksum offload and RSS hash. */ 2601 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), 2602 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 2603 2604 yge_init_rx_ring(port); 2605 2606 /* Configure interrupt handling. */ 2607 if (port == dev->d_port[YGE_PORT_A]) { 2608 dev->d_intrmask |= Y2_IS_PORT_A; 2609 dev->d_intrhwemask |= Y2_HWE_L1_MASK; 2610 } else if (port == dev->d_port[YGE_PORT_B]) { 2611 dev->d_intrmask |= Y2_IS_PORT_B; 2612 dev->d_intrhwemask |= Y2_HWE_L2_MASK; 2613 } 2614 CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask); 2615 (void) CSR_READ_4(dev, B0_HWE_IMSK); 2616 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); 2617 (void) CSR_READ_4(dev, B0_IMSK); 2618 2619 /* Enable RX/TX GMAC */ 2620 gmac = GMAC_READ_2(dev, pnum, GM_GP_CTRL); 2621 gmac |= (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2622 GMAC_WRITE_2(port->p_dev, port->p_port, GM_GP_CTRL, gmac); 2623 /* Read again to ensure writing. */ 2624 (void) GMAC_READ_2(dev, pnum, GM_GP_CTRL); 2625 2626 /* Reset TX timer */ 2627 port->p_tx_wdog = 0; 2628 } 2629 2630 static void 2631 yge_set_rambuffer(yge_port_t *port) 2632 { 2633 yge_dev_t *dev; 2634 int ltpp, utpp; 2635 int pnum; 2636 uint32_t rxq; 2637 uint32_t txq; 2638 2639 dev = port->p_dev; 2640 pnum = port->p_port; 2641 rxq = port->p_rxq; 2642 txq = port->p_txq; 2643 2644 if ((port->p_flags & PORT_FLAG_RAMBUF) == 0) 2645 return; 2646 2647 /* Setup Rx Queue. */ 2648 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_CLR); 2649 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_START), dev->d_rxqstart[pnum] / 8); 2650 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_END), dev->d_rxqend[pnum] / 8); 2651 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_WP), dev->d_rxqstart[pnum] / 8); 2652 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RP), dev->d_rxqstart[pnum] / 8); 2653 2654 utpp = 2655 (dev->d_rxqend[pnum] + 1 - dev->d_rxqstart[pnum] - RB_ULPP) / 8; 2656 ltpp = 2657 (dev->d_rxqend[pnum] + 1 - dev->d_rxqstart[pnum] - RB_LLPP_B) / 8; 2658 2659 if (dev->d_rxqsize < MSK_MIN_RXQ_SIZE) 2660 ltpp += (RB_LLPP_B - RB_LLPP_S) / 8; 2661 2662 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_UTPP), utpp); 2663 CSR_WRITE_4(dev, RB_ADDR(rxq, RB_RX_LTPP), ltpp); 2664 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 2665 2666 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_ENA_OP_MD); 2667 (void) CSR_READ_1(dev, RB_ADDR(rxq, RB_CTRL)); 2668 2669 /* Setup Tx Queue. */ 2670 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_CLR); 2671 CSR_WRITE_4(dev, RB_ADDR(txq, RB_START), dev->d_txqstart[pnum] / 8); 2672 CSR_WRITE_4(dev, RB_ADDR(txq, RB_END), dev->d_txqend[pnum] / 8); 2673 CSR_WRITE_4(dev, RB_ADDR(txq, RB_WP), dev->d_txqstart[pnum] / 8); 2674 CSR_WRITE_4(dev, RB_ADDR(txq, RB_RP), dev->d_txqstart[pnum] / 8); 2675 /* Enable Store & Forward for Tx side. */ 2676 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_STFWD); 2677 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_ENA_OP_MD); 2678 (void) CSR_READ_1(dev, RB_ADDR(txq, RB_CTRL)); 2679 } 2680 2681 static void 2682 yge_set_prefetch(yge_dev_t *dev, int qaddr, yge_ring_t *ring) 2683 { 2684 /* Reset the prefetch unit. */ 2685 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 2686 PREF_UNIT_RST_SET); 2687 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 2688 PREF_UNIT_RST_CLR); 2689 /* Set LE base address. */ 2690 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 2691 YGE_ADDR_LO(ring->r_paddr)); 2692 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 2693 YGE_ADDR_HI(ring->r_paddr)); 2694 /* Set the list last index. */ 2695 CSR_WRITE_2(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 2696 ring->r_num - 1); 2697 /* Turn on prefetch unit. */ 2698 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 2699 PREF_UNIT_OP_ON); 2700 /* Dummy read to ensure write. */ 2701 (void) CSR_READ_4(dev, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 2702 } 2703 2704 static void 2705 yge_stop_port(yge_port_t *port) 2706 { 2707 yge_dev_t *dev = port->p_dev; 2708 int pnum = port->p_port; 2709 uint32_t txq = port->p_txq; 2710 uint32_t rxq = port->p_rxq; 2711 uint32_t val; 2712 int i; 2713 2714 dev = port->p_dev; 2715 2716 /* 2717 * shutdown timeout 2718 */ 2719 port->p_tx_wdog = 0; 2720 2721 /* Disable interrupts. */ 2722 if (pnum == YGE_PORT_A) { 2723 dev->d_intrmask &= ~Y2_IS_PORT_A; 2724 dev->d_intrhwemask &= ~Y2_HWE_L1_MASK; 2725 } else { 2726 dev->d_intrmask &= ~Y2_IS_PORT_B; 2727 dev->d_intrhwemask &= ~Y2_HWE_L2_MASK; 2728 } 2729 CSR_WRITE_4(dev, B0_HWE_IMSK, dev->d_intrhwemask); 2730 (void) CSR_READ_4(dev, B0_HWE_IMSK); 2731 CSR_WRITE_4(dev, B0_IMSK, dev->d_intrmask); 2732 (void) CSR_READ_4(dev, B0_IMSK); 2733 2734 /* Disable Tx/Rx MAC. */ 2735 val = GMAC_READ_2(dev, pnum, GM_GP_CTRL); 2736 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 2737 GMAC_WRITE_2(dev, pnum, GM_GP_CTRL, val); 2738 /* Read again to ensure writing. */ 2739 (void) GMAC_READ_2(dev, pnum, GM_GP_CTRL); 2740 2741 /* Update stats and clear counters. */ 2742 yge_stats_update(port); 2743 2744 /* Stop Tx BMU. */ 2745 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP); 2746 val = CSR_READ_4(dev, Q_ADDR(txq, Q_CSR)); 2747 for (i = 0; i < YGE_TIMEOUT; i += 10) { 2748 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 2749 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_STOP); 2750 val = CSR_READ_4(dev, Q_ADDR(txq, Q_CSR)); 2751 } else 2752 break; 2753 drv_usecwait(10); 2754 } 2755 /* This is probably fairly catastrophic. */ 2756 if ((val & (BMU_STOP | BMU_IDLE)) == 0) 2757 yge_error(NULL, port, "Tx BMU stop failed"); 2758 2759 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET | RB_DIS_OP_MD); 2760 2761 /* Disable all GMAC interrupt. */ 2762 CSR_WRITE_1(dev, MR_ADDR(pnum, GMAC_IRQ_MSK), 0); 2763 2764 /* Disable the RAM Interface Arbiter. */ 2765 CSR_WRITE_1(dev, MR_ADDR(pnum, TXA_CTRL), TXA_DIS_ARB); 2766 2767 /* Reset the PCI FIFO of the async Tx queue */ 2768 CSR_WRITE_4(dev, Q_ADDR(txq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 2769 2770 /* Reset the Tx prefetch units. */ 2771 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(txq, PREF_UNIT_CTRL_REG), 2772 PREF_UNIT_RST_SET); 2773 2774 /* Reset the RAM Buffer async Tx queue. */ 2775 CSR_WRITE_1(dev, RB_ADDR(txq, RB_CTRL), RB_RST_SET); 2776 2777 /* Reset Tx MAC FIFO. */ 2778 CSR_WRITE_4(dev, MR_ADDR(pnum, TX_GMF_CTRL_T), GMF_RST_SET); 2779 /* Set Pause Off. */ 2780 CSR_WRITE_4(dev, MR_ADDR(pnum, GMAC_CTRL), GMC_PAUSE_OFF); 2781 2782 /* 2783 * The Rx Stop command will not work for Yukon-2 if the BMU does not 2784 * reach the end of packet and since we can't make sure that we have 2785 * incoming data, we must reset the BMU while it is not during a DMA 2786 * transfer. Since it is possible that the Rx path is still active, 2787 * the Rx RAM buffer will be stopped first, so any possible incoming 2788 * data will not trigger a DMA. After the RAM buffer is stopped, the 2789 * BMU is polled until any DMA in progress is ended and only then it 2790 * will be reset. 2791 */ 2792 2793 /* Disable the RAM Buffer receive queue. */ 2794 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); 2795 for (i = 0; i < YGE_TIMEOUT; i += 10) { 2796 if (CSR_READ_1(dev, RB_ADDR(rxq, Q_RSL)) == 2797 CSR_READ_1(dev, RB_ADDR(rxq, Q_RL))) 2798 break; 2799 drv_usecwait(10); 2800 } 2801 /* This is probably nearly a fatal error. */ 2802 if (i == YGE_TIMEOUT) 2803 yge_error(NULL, port, "Rx BMU stop failed"); 2804 2805 CSR_WRITE_4(dev, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); 2806 /* Reset the Rx prefetch unit. */ 2807 CSR_WRITE_4(dev, Y2_PREF_Q_ADDR(rxq, PREF_UNIT_CTRL_REG), 2808 PREF_UNIT_RST_SET); 2809 /* Reset the RAM Buffer receive queue. */ 2810 CSR_WRITE_1(dev, RB_ADDR(rxq, RB_CTRL), RB_RST_SET); 2811 /* Reset Rx MAC FIFO. */ 2812 CSR_WRITE_4(dev, MR_ADDR(pnum, RX_GMF_CTRL_T), GMF_RST_SET); 2813 } 2814 2815 /* 2816 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 2817 * counter clears high 16 bits of the counter such that accessing 2818 * lower 16 bits should be the last operation. 2819 */ 2820 #define YGE_READ_MIB32(x, y) \ 2821 GMAC_READ_4(dev, x, y) 2822 2823 #define YGE_READ_MIB64(x, y) \ 2824 ((((uint64_t)YGE_READ_MIB32(x, (y) + 8)) << 32) + \ 2825 (uint64_t)YGE_READ_MIB32(x, y)) 2826 2827 static void 2828 yge_stats_clear(yge_port_t *port) 2829 { 2830 yge_dev_t *dev; 2831 uint16_t gmac; 2832 int32_t pnum; 2833 2834 pnum = port->p_port; 2835 dev = port->p_dev; 2836 2837 /* Set MIB Clear Counter Mode. */ 2838 gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR); 2839 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 2840 /* Read all MIB Counters with Clear Mode set. */ 2841 for (int i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += 4) 2842 (void) YGE_READ_MIB32(pnum, i); 2843 /* Clear MIB Clear Counter Mode. */ 2844 gmac &= ~GM_PAR_MIB_CLR; 2845 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac); 2846 } 2847 2848 static void 2849 yge_stats_update(yge_port_t *port) 2850 { 2851 yge_dev_t *dev; 2852 struct yge_hw_stats *stats; 2853 uint16_t gmac; 2854 int32_t pnum; 2855 2856 dev = port->p_dev; 2857 pnum = port->p_port; 2858 2859 if (dev->d_suspended || !port->p_running) { 2860 return; 2861 } 2862 stats = &port->p_stats; 2863 /* Set MIB Clear Counter Mode. */ 2864 gmac = GMAC_READ_2(dev, pnum, GM_PHY_ADDR); 2865 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 2866 2867 /* Rx stats. */ 2868 stats->rx_ucast_frames += YGE_READ_MIB32(pnum, GM_RXF_UC_OK); 2869 stats->rx_bcast_frames += YGE_READ_MIB32(pnum, GM_RXF_BC_OK); 2870 stats->rx_pause_frames += YGE_READ_MIB32(pnum, GM_RXF_MPAUSE); 2871 stats->rx_mcast_frames += YGE_READ_MIB32(pnum, GM_RXF_MC_OK); 2872 stats->rx_crc_errs += YGE_READ_MIB32(pnum, GM_RXF_FCS_ERR); 2873 (void) YGE_READ_MIB32(pnum, GM_RXF_SPARE1); 2874 stats->rx_good_octets += YGE_READ_MIB64(pnum, GM_RXO_OK_LO); 2875 stats->rx_bad_octets += YGE_READ_MIB64(pnum, GM_RXO_ERR_LO); 2876 stats->rx_runts += YGE_READ_MIB32(pnum, GM_RXF_SHT); 2877 stats->rx_runt_errs += YGE_READ_MIB32(pnum, GM_RXE_FRAG); 2878 stats->rx_pkts_64 += YGE_READ_MIB32(pnum, GM_RXF_64B); 2879 stats->rx_pkts_65_127 += YGE_READ_MIB32(pnum, GM_RXF_127B); 2880 stats->rx_pkts_128_255 += YGE_READ_MIB32(pnum, GM_RXF_255B); 2881 stats->rx_pkts_256_511 += YGE_READ_MIB32(pnum, GM_RXF_511B); 2882 stats->rx_pkts_512_1023 += YGE_READ_MIB32(pnum, GM_RXF_1023B); 2883 stats->rx_pkts_1024_1518 += YGE_READ_MIB32(pnum, GM_RXF_1518B); 2884 stats->rx_pkts_1519_max += YGE_READ_MIB32(pnum, GM_RXF_MAX_SZ); 2885 stats->rx_pkts_too_long += YGE_READ_MIB32(pnum, GM_RXF_LNG_ERR); 2886 stats->rx_pkts_jabbers += YGE_READ_MIB32(pnum, GM_RXF_JAB_PKT); 2887 (void) YGE_READ_MIB32(pnum, GM_RXF_SPARE2); 2888 stats->rx_fifo_oflows += YGE_READ_MIB32(pnum, GM_RXE_FIFO_OV); 2889 (void) YGE_READ_MIB32(pnum, GM_RXF_SPARE3); 2890 2891 /* Tx stats. */ 2892 stats->tx_ucast_frames += YGE_READ_MIB32(pnum, GM_TXF_UC_OK); 2893 stats->tx_bcast_frames += YGE_READ_MIB32(pnum, GM_TXF_BC_OK); 2894 stats->tx_pause_frames += YGE_READ_MIB32(pnum, GM_TXF_MPAUSE); 2895 stats->tx_mcast_frames += YGE_READ_MIB32(pnum, GM_TXF_MC_OK); 2896 stats->tx_octets += YGE_READ_MIB64(pnum, GM_TXO_OK_LO); 2897 stats->tx_pkts_64 += YGE_READ_MIB32(pnum, GM_TXF_64B); 2898 stats->tx_pkts_65_127 += YGE_READ_MIB32(pnum, GM_TXF_127B); 2899 stats->tx_pkts_128_255 += YGE_READ_MIB32(pnum, GM_TXF_255B); 2900 stats->tx_pkts_256_511 += YGE_READ_MIB32(pnum, GM_TXF_511B); 2901 stats->tx_pkts_512_1023 += YGE_READ_MIB32(pnum, GM_TXF_1023B); 2902 stats->tx_pkts_1024_1518 += YGE_READ_MIB32(pnum, GM_TXF_1518B); 2903 stats->tx_pkts_1519_max += YGE_READ_MIB32(pnum, GM_TXF_MAX_SZ); 2904 (void) YGE_READ_MIB32(pnum, GM_TXF_SPARE1); 2905 stats->tx_colls += YGE_READ_MIB32(pnum, GM_TXF_COL); 2906 stats->tx_late_colls += YGE_READ_MIB32(pnum, GM_TXF_LAT_COL); 2907 stats->tx_excess_colls += YGE_READ_MIB32(pnum, GM_TXF_ABO_COL); 2908 stats->tx_multi_colls += YGE_READ_MIB32(pnum, GM_TXF_MUL_COL); 2909 stats->tx_single_colls += YGE_READ_MIB32(pnum, GM_TXF_SNG_COL); 2910 stats->tx_underflows += YGE_READ_MIB32(pnum, GM_TXE_FIFO_UR); 2911 /* Clear MIB Clear Counter Mode. */ 2912 gmac &= ~GM_PAR_MIB_CLR; 2913 GMAC_WRITE_2(dev, pnum, GM_PHY_ADDR, gmac); 2914 } 2915 2916 #undef YGE_READ_MIB32 2917 #undef YGE_READ_MIB64 2918 2919 uint32_t 2920 yge_hashbit(const uint8_t *addr) 2921 { 2922 int idx; 2923 int bit; 2924 uint_t data; 2925 uint32_t crc; 2926 #define POLY_BE 0x04c11db7 2927 2928 crc = 0xffffffff; 2929 for (idx = 0; idx < 6; idx++) { 2930 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 2931 crc = (crc << 1) 2932 ^ ((((crc >> 31) ^ data) & 1) ? POLY_BE : 0); 2933 } 2934 } 2935 #undef POLY_BE 2936 2937 return (crc % 64); 2938 } 2939 2940 int 2941 yge_m_stat(void *arg, uint_t stat, uint64_t *val) 2942 { 2943 yge_port_t *port = arg; 2944 struct yge_hw_stats *stats = &port->p_stats; 2945 2946 if (stat == MAC_STAT_IFSPEED) { 2947 /* 2948 * This is the first stat we are asked about. We update only 2949 * for this stat, to avoid paying the hefty cost of the update 2950 * once for each stat. 2951 */ 2952 DEV_LOCK(port->p_dev); 2953 yge_stats_update(port); 2954 DEV_UNLOCK(port->p_dev); 2955 } 2956 2957 if (mii_m_getstat(port->p_mii, stat, val) == 0) { 2958 return (0); 2959 } 2960 2961 switch (stat) { 2962 case MAC_STAT_MULTIRCV: 2963 *val = stats->rx_mcast_frames; 2964 break; 2965 2966 case MAC_STAT_BRDCSTRCV: 2967 *val = stats->rx_bcast_frames; 2968 break; 2969 2970 case MAC_STAT_MULTIXMT: 2971 *val = stats->tx_mcast_frames; 2972 break; 2973 2974 case MAC_STAT_BRDCSTXMT: 2975 *val = stats->tx_bcast_frames; 2976 break; 2977 2978 case MAC_STAT_IPACKETS: 2979 *val = stats->rx_ucast_frames; 2980 break; 2981 2982 case MAC_STAT_RBYTES: 2983 *val = stats->rx_good_octets; 2984 break; 2985 2986 case MAC_STAT_OPACKETS: 2987 *val = stats->tx_ucast_frames; 2988 break; 2989 2990 case MAC_STAT_OBYTES: 2991 *val = stats->tx_octets; 2992 break; 2993 2994 case MAC_STAT_NORCVBUF: 2995 *val = stats->rx_nobuf; 2996 break; 2997 2998 case MAC_STAT_COLLISIONS: 2999 *val = stats->tx_colls; 3000 break; 3001 3002 case ETHER_STAT_ALIGN_ERRORS: 3003 *val = stats->rx_runt_errs; 3004 break; 3005 3006 case ETHER_STAT_FCS_ERRORS: 3007 *val = stats->rx_crc_errs; 3008 break; 3009 3010 case ETHER_STAT_FIRST_COLLISIONS: 3011 *val = stats->tx_single_colls; 3012 break; 3013 3014 case ETHER_STAT_MULTI_COLLISIONS: 3015 *val = stats->tx_multi_colls; 3016 break; 3017 3018 case ETHER_STAT_TX_LATE_COLLISIONS: 3019 *val = stats->tx_late_colls; 3020 break; 3021 3022 case ETHER_STAT_EX_COLLISIONS: 3023 *val = stats->tx_excess_colls; 3024 break; 3025 3026 case ETHER_STAT_TOOLONG_ERRORS: 3027 *val = stats->rx_pkts_too_long; 3028 break; 3029 3030 case MAC_STAT_OVERFLOWS: 3031 *val = stats->rx_fifo_oflows; 3032 break; 3033 3034 case MAC_STAT_UNDERFLOWS: 3035 *val = stats->tx_underflows; 3036 break; 3037 3038 case ETHER_STAT_TOOSHORT_ERRORS: 3039 *val = stats->rx_runts; 3040 break; 3041 3042 case ETHER_STAT_JABBER_ERRORS: 3043 *val = stats->rx_pkts_jabbers; 3044 break; 3045 3046 default: 3047 return (ENOTSUP); 3048 } 3049 return (0); 3050 } 3051 3052 int 3053 yge_m_start(void *arg) 3054 { 3055 yge_port_t *port = arg; 3056 3057 DEV_LOCK(port->p_dev); 3058 3059 /* 3060 * We defer resource allocation to this point, because we 3061 * don't want to waste DMA resources that might better be used 3062 * elsewhere, if the port is not actually being used. 3063 * 3064 * Furthermore, this gives us a more graceful handling of dynamic 3065 * MTU modification. 3066 */ 3067 if (yge_txrx_dma_alloc(port) != DDI_SUCCESS) { 3068 /* Make sure we free up partially allocated resources. */ 3069 yge_txrx_dma_free(port); 3070 DEV_UNLOCK(port->p_dev); 3071 return (ENOMEM); 3072 } 3073 3074 if (!port->p_dev->d_suspended) 3075 yge_start_port(port); 3076 port->p_running = B_TRUE; 3077 DEV_UNLOCK(port->p_dev); 3078 3079 mii_start(port->p_mii); 3080 3081 return (0); 3082 } 3083 3084 void 3085 yge_m_stop(void *arg) 3086 { 3087 yge_port_t *port = arg; 3088 yge_dev_t *dev = port->p_dev; 3089 3090 DEV_LOCK(dev); 3091 if (!dev->d_suspended) 3092 yge_stop_port(port); 3093 3094 port->p_running = B_FALSE; 3095 3096 /* Release resources we don't need */ 3097 yge_txrx_dma_free(port); 3098 DEV_UNLOCK(dev); 3099 } 3100 3101 int 3102 yge_m_promisc(void *arg, boolean_t on) 3103 { 3104 yge_port_t *port = arg; 3105 3106 DEV_LOCK(port->p_dev); 3107 3108 /* Save current promiscuous mode. */ 3109 port->p_promisc = on; 3110 yge_setrxfilt(port); 3111 3112 DEV_UNLOCK(port->p_dev); 3113 3114 return (0); 3115 } 3116 3117 int 3118 yge_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 3119 { 3120 yge_port_t *port = arg; 3121 int bit; 3122 boolean_t update; 3123 3124 bit = yge_hashbit(addr); 3125 ASSERT(bit < 64); 3126 3127 DEV_LOCK(port->p_dev); 3128 if (add) { 3129 if (port->p_mccount[bit] == 0) { 3130 /* Set the corresponding bit in the hash table. */ 3131 port->p_mchash[bit / 32] |= (1 << (bit % 32)); 3132 update = B_TRUE; 3133 } 3134 port->p_mccount[bit]++; 3135 } else { 3136 ASSERT(port->p_mccount[bit] > 0); 3137 port->p_mccount[bit]--; 3138 if (port->p_mccount[bit] == 0) { 3139 port->p_mchash[bit / 32] &= ~(1 << (bit % 32)); 3140 update = B_TRUE; 3141 } 3142 } 3143 3144 if (update) { 3145 yge_setrxfilt(port); 3146 } 3147 DEV_UNLOCK(port->p_dev); 3148 return (0); 3149 } 3150 3151 int 3152 yge_m_unicst(void *arg, const uint8_t *macaddr) 3153 { 3154 yge_port_t *port = arg; 3155 3156 DEV_LOCK(port->p_dev); 3157 3158 bcopy(macaddr, port->p_curraddr, ETHERADDRL); 3159 yge_setrxfilt(port); 3160 3161 DEV_UNLOCK(port->p_dev); 3162 3163 return (0); 3164 } 3165 3166 mblk_t * 3167 yge_m_tx(void *arg, mblk_t *mp) 3168 { 3169 yge_port_t *port = arg; 3170 mblk_t *nmp; 3171 int enq = 0; 3172 uint32_t ridx; 3173 int idx; 3174 boolean_t resched = B_FALSE; 3175 3176 TX_LOCK(port->p_dev); 3177 3178 if (port->p_dev->d_suspended) { 3179 3180 TX_UNLOCK(port->p_dev); 3181 3182 while ((nmp = mp) != NULL) { 3183 /* carrier_errors++; */ 3184 mp = mp->b_next; 3185 freemsg(nmp); 3186 } 3187 return (NULL); 3188 } 3189 3190 /* attempt a reclaim */ 3191 ridx = port->p_port == YGE_PORT_A ? 3192 STAT_TXA1_RIDX : STAT_TXA2_RIDX; 3193 idx = CSR_READ_2(port->p_dev, ridx); 3194 if (port->p_tx_cons != idx) 3195 resched = yge_txeof_locked(port, idx); 3196 3197 while (mp != NULL) { 3198 nmp = mp->b_next; 3199 mp->b_next = NULL; 3200 3201 if (!yge_send(port, mp)) { 3202 mp->b_next = nmp; 3203 break; 3204 } 3205 enq++; 3206 mp = nmp; 3207 3208 } 3209 if (enq > 0) { 3210 /* Transmit */ 3211 CSR_WRITE_2(port->p_dev, 3212 Y2_PREF_Q_ADDR(port->p_txq, PREF_UNIT_PUT_IDX_REG), 3213 port->p_tx_prod); 3214 } 3215 3216 TX_UNLOCK(port->p_dev); 3217 3218 if (resched) 3219 mac_tx_update(port->p_mh); 3220 3221 return (mp); 3222 } 3223 3224 void 3225 yge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 3226 { 3227 #ifdef YGE_MII_LOOPBACK 3228 /* LINTED E_FUNC_SET_NOT_USED */ 3229 yge_port_t *port = arg; 3230 3231 /* 3232 * Right now, the MII common layer does not properly handle 3233 * loopback on these PHYs. Fixing this should be done at some 3234 * point in the future. 3235 */ 3236 if (mii_m_loop_ioctl(port->p_mii, wq, mp)) 3237 return; 3238 #else 3239 _NOTE(ARGUNUSED(arg)); 3240 #endif 3241 3242 miocnak(wq, mp, 0, EINVAL); 3243 } 3244 3245 int 3246 yge_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3247 uint_t pr_valsize, const void *pr_val) 3248 { 3249 yge_port_t *port = arg; 3250 uint32_t new_mtu; 3251 int err = 0; 3252 3253 err = mii_m_setprop(port->p_mii, pr_name, pr_num, pr_valsize, pr_val); 3254 if (err != ENOTSUP) { 3255 return (err); 3256 } 3257 3258 DEV_LOCK(port->p_dev); 3259 3260 switch (pr_num) { 3261 case MAC_PROP_MTU: 3262 if (pr_valsize < sizeof (new_mtu)) { 3263 err = EINVAL; 3264 break; 3265 } 3266 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3267 if (new_mtu == port->p_mtu) { 3268 /* no change */ 3269 err = 0; 3270 break; 3271 } 3272 if (new_mtu < ETHERMTU) { 3273 yge_error(NULL, port, 3274 "Maximum MTU size too small: %d", new_mtu); 3275 err = EINVAL; 3276 break; 3277 } 3278 if (new_mtu > (port->p_flags & PORT_FLAG_NOJUMBO ? 3279 ETHERMTU : YGE_JUMBO_MTU)) { 3280 yge_error(NULL, port, 3281 "Maximum MTU size too big: %d", new_mtu); 3282 err = EINVAL; 3283 break; 3284 } 3285 if (port->p_running) { 3286 yge_error(NULL, port, 3287 "Unable to change maximum MTU while running"); 3288 err = EBUSY; 3289 break; 3290 } 3291 3292 3293 /* 3294 * NB: It would probably be better not to hold the 3295 * DEVLOCK, but releasing it creates a potential race 3296 * if m_start is called concurrently. 3297 * 3298 * It turns out that the MAC layer guarantees safety 3299 * for us here by using a cut out for this kind of 3300 * notification call back anyway. 3301 * 3302 * See R8. and R14. in mac.c locking comments, which read 3303 * as follows: 3304 * 3305 * R8. Since it is not guaranteed (see R14) that 3306 * drivers won't hold locks across mac driver 3307 * interfaces, the MAC layer must provide a cut out 3308 * for control interfaces like upcall notifications 3309 * and start them in a separate thread. 3310 * 3311 * R14. It would be preferable if MAC drivers don't 3312 * hold any locks across any mac call. However at a 3313 * minimum they must not hold any locks across data 3314 * upcalls. They must also make sure that all 3315 * references to mac data structures are cleaned up 3316 * and that it is single threaded at mac_unregister 3317 * time. 3318 */ 3319 err = mac_maxsdu_update(port->p_mh, new_mtu); 3320 if (err != 0) { 3321 /* This should never occur! */ 3322 yge_error(NULL, port, 3323 "Failed notifying GLDv3 of new maximum MTU"); 3324 } else { 3325 port->p_mtu = new_mtu; 3326 } 3327 break; 3328 3329 default: 3330 err = ENOTSUP; 3331 break; 3332 } 3333 3334 err: 3335 DEV_UNLOCK(port->p_dev); 3336 3337 return (err); 3338 } 3339 3340 int 3341 yge_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3342 uint_t pr_valsize, void *pr_val) 3343 { 3344 yge_port_t *port = arg; 3345 3346 return (mii_m_getprop(port->p_mii, pr_name, pr_num, pr_valsize, 3347 pr_val)); 3348 } 3349 3350 static void 3351 yge_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3352 mac_prop_info_handle_t prh) 3353 { 3354 yge_port_t *port = arg; 3355 3356 switch (pr_num) { 3357 case MAC_PROP_MTU: 3358 mac_prop_info_set_range_uint32(prh, ETHERMTU, 3359 port->p_flags & PORT_FLAG_NOJUMBO ? 3360 ETHERMTU : YGE_JUMBO_MTU); 3361 break; 3362 default: 3363 mii_m_propinfo(port->p_mii, pr_name, pr_num, prh); 3364 break; 3365 } 3366 } 3367 3368 void 3369 yge_dispatch(yge_dev_t *dev, int flag) 3370 { 3371 TASK_LOCK(dev); 3372 dev->d_task_flags |= flag; 3373 TASK_SIGNAL(dev); 3374 TASK_UNLOCK(dev); 3375 } 3376 3377 void 3378 yge_task(void *arg) 3379 { 3380 yge_dev_t *dev = arg; 3381 int flags; 3382 3383 for (;;) { 3384 3385 TASK_LOCK(dev); 3386 while ((flags = dev->d_task_flags) == 0) 3387 TASK_WAIT(dev); 3388 3389 dev->d_task_flags = 0; 3390 TASK_UNLOCK(dev); 3391 3392 /* 3393 * This should be the first thing after the sleep so if we are 3394 * requested to exit we do that and not waste time doing work 3395 * we will then abandone. 3396 */ 3397 if (flags & YGE_TASK_EXIT) 3398 break; 3399 3400 /* all processing done without holding locks */ 3401 if (flags & YGE_TASK_RESTART) 3402 yge_restart_task(dev); 3403 } 3404 } 3405 3406 void 3407 yge_error(yge_dev_t *dev, yge_port_t *port, char *fmt, ...) 3408 { 3409 va_list ap; 3410 char buf[256]; 3411 int ppa; 3412 3413 va_start(ap, fmt); 3414 (void) vsnprintf(buf, sizeof (buf), fmt, ap); 3415 va_end(ap); 3416 3417 if (dev == NULL && port == NULL) { 3418 cmn_err(CE_WARN, "yge: %s", buf); 3419 } else { 3420 if (port != NULL) 3421 ppa = port->p_ppa; 3422 else 3423 ppa = ddi_get_instance(dev->d_dip); 3424 cmn_err(CE_WARN, "yge%d: %s", ppa, buf); 3425 } 3426 } 3427 3428 static int 3429 yge_ddi_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 3430 { 3431 yge_dev_t *dev; 3432 int rv; 3433 3434 switch (cmd) { 3435 case DDI_ATTACH: 3436 dev = kmem_zalloc(sizeof (*dev), KM_SLEEP); 3437 dev->d_port[0] = kmem_zalloc(sizeof (yge_port_t), KM_SLEEP); 3438 dev->d_port[1] = kmem_zalloc(sizeof (yge_port_t), KM_SLEEP); 3439 dev->d_dip = dip; 3440 ddi_set_driver_private(dip, dev); 3441 3442 dev->d_port[0]->p_port = 0; 3443 dev->d_port[0]->p_dev = dev; 3444 dev->d_port[1]->p_port = 0; 3445 dev->d_port[1]->p_dev = dev; 3446 3447 rv = yge_attach(dev); 3448 if (rv != DDI_SUCCESS) { 3449 ddi_set_driver_private(dip, 0); 3450 kmem_free(dev->d_port[1], sizeof (yge_port_t)); 3451 kmem_free(dev->d_port[0], sizeof (yge_port_t)); 3452 kmem_free(dev, sizeof (*dev)); 3453 } 3454 return (rv); 3455 3456 case DDI_RESUME: 3457 dev = ddi_get_driver_private(dip); 3458 ASSERT(dev != NULL); 3459 return (yge_resume(dev)); 3460 3461 default: 3462 return (DDI_FAILURE); 3463 } 3464 } 3465 3466 static int 3467 yge_ddi_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 3468 { 3469 yge_dev_t *dev; 3470 mac_handle_t mh; 3471 3472 switch (cmd) { 3473 case DDI_DETACH: 3474 3475 dev = ddi_get_driver_private(dip); 3476 3477 /* attempt to unregister MACs from Nemo */ 3478 for (int i = 0; i < dev->d_num_port; i++) { 3479 3480 if (((mh = dev->d_port[i]->p_mh) != NULL) && 3481 (mac_disable(mh) != 0)) { 3482 /* 3483 * We'd really like a mac_enable to reenable 3484 * any MACs that we previously disabled. Too 3485 * bad GLDv3 doesn't have one. 3486 */ 3487 return (DDI_FAILURE); 3488 } 3489 } 3490 3491 ASSERT(dip == dev->d_dip); 3492 yge_detach(dev); 3493 ddi_set_driver_private(dip, 0); 3494 for (int i = 0; i < dev->d_num_port; i++) { 3495 if ((mh = dev->d_port[i]->p_mh) != NULL) { 3496 /* This can't fail after mac_disable above. */ 3497 (void) mac_unregister(mh); 3498 } 3499 } 3500 kmem_free(dev->d_port[1], sizeof (yge_port_t)); 3501 kmem_free(dev->d_port[0], sizeof (yge_port_t)); 3502 kmem_free(dev, sizeof (*dev)); 3503 return (DDI_SUCCESS); 3504 3505 case DDI_SUSPEND: 3506 dev = ddi_get_driver_private(dip); 3507 ASSERT(dev != NULL); 3508 return (yge_suspend(dev)); 3509 3510 default: 3511 return (DDI_FAILURE); 3512 } 3513 } 3514 3515 static int 3516 yge_quiesce(dev_info_t *dip) 3517 { 3518 yge_dev_t *dev; 3519 3520 dev = ddi_get_driver_private(dip); 3521 ASSERT(dev != NULL); 3522 3523 /* NB: No locking! We are called in single threaded context */ 3524 for (int i = 0; i < dev->d_num_port; i++) { 3525 yge_port_t *port = dev->d_port[i]; 3526 if (port->p_running) 3527 yge_stop_port(port); 3528 } 3529 3530 /* Disable all interrupts. */ 3531 CSR_WRITE_4(dev, B0_IMSK, 0); 3532 (void) CSR_READ_4(dev, B0_IMSK); 3533 CSR_WRITE_4(dev, B0_HWE_IMSK, 0); 3534 (void) CSR_READ_4(dev, B0_HWE_IMSK); 3535 3536 /* Put hardware into reset. */ 3537 CSR_WRITE_2(dev, B0_CTST, CS_RST_SET); 3538 3539 return (DDI_SUCCESS); 3540 } 3541 3542 /* 3543 * Stream information 3544 */ 3545 DDI_DEFINE_STREAM_OPS(yge_devops, nulldev, nulldev, yge_ddi_attach, 3546 yge_ddi_detach, nodev, NULL, D_MP, NULL, yge_quiesce); 3547 3548 /* 3549 * Module linkage information. 3550 */ 3551 3552 static struct modldrv yge_modldrv = { 3553 &mod_driverops, /* drv_modops */ 3554 "Yukon 2 Ethernet", /* drv_linkinfo */ 3555 &yge_devops /* drv_dev_ops */ 3556 }; 3557 3558 static struct modlinkage yge_modlinkage = { 3559 MODREV_1, /* ml_rev */ 3560 &yge_modldrv, /* ml_linkage */ 3561 NULL 3562 }; 3563 3564 /* 3565 * DDI entry points. 3566 */ 3567 int 3568 _init(void) 3569 { 3570 int rv; 3571 mac_init_ops(&yge_devops, "yge"); 3572 if ((rv = mod_install(&yge_modlinkage)) != DDI_SUCCESS) { 3573 mac_fini_ops(&yge_devops); 3574 } 3575 return (rv); 3576 } 3577 3578 int 3579 _fini(void) 3580 { 3581 int rv; 3582 if ((rv = mod_remove(&yge_modlinkage)) == DDI_SUCCESS) { 3583 mac_fini_ops(&yge_devops); 3584 } 3585 return (rv); 3586 } 3587 3588 int 3589 _info(struct modinfo *modinfop) 3590 { 3591 return (mod_info(&yge_modlinkage, modinfop)); 3592 } 3593