1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2006 8 * Damien Bergamini <damien.bergamini@free.fr> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 #ifndef _WPIREG_H_ 24 #define _WPIREG_H_ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 #define WPI_TX_RING_COUNT 256 33 #define WPI_SVC_RING_COUNT 256 34 #define WPI_CMD_RING_COUNT 256 35 #define WPI_RX_RING_COUNT 64 36 37 /* 38 * Rings must be aligned on a four 4K-pages boundary. 39 * I had a hard time figuring this out. 40 */ 41 #define WPI_RING_DMA_ALIGN 0x4000 42 43 /* 44 * maximum scatter/gather 45 */ 46 #define WPI_MAX_SCATTER 4 47 48 /* 49 * Control and status registers. 50 */ 51 #define WPI_HWCONFIG 0x000 52 #define WPI_INTR 0x008 53 #define WPI_MASK 0x00c 54 #define WPI_INTR_STATUS 0x010 55 #define WPI_GPIO_STATUS 0x018 56 #define WPI_RESET 0x020 57 #define WPI_GPIO_CTL 0x024 58 #define WPI_EEPROM_CTL 0x02c 59 #define WPI_EEPROM_STATUS 0x030 60 #define WPI_UCODE_CLR 0x05c 61 #define WPI_TEMPERATURE 0x060 62 #define WPI_CHICKEN 0x100 63 #define WPI_PLL_CTL 0x20c 64 #define WPI_FW_TARGET 0x410 65 #define WPI_WRITE_MEM_ADDR 0x444 66 #define WPI_READ_MEM_ADDR 0x448 67 #define WPI_WRITE_MEM_DATA 0x44c 68 #define WPI_READ_MEM_DATA 0x450 69 #define WPI_TX_WIDX 0x460 70 #define WPI_TX_CTL(qid) (0x940 + (qid) * 8) 71 #define WPI_TX_BASE(qid) (0x944 + (qid) * 8) 72 #define WPI_TX_DESC(qid) (0x980 + (qid) * 80) 73 #define WPI_RX_CONFIG 0xc00 74 #define WPI_RX_BASE 0xc04 75 #define WPI_RX_WIDX 0xc20 76 #define WPI_RX_RIDX_PTR 0xc24 77 #define WPI_RX_CTL 0xcc0 78 #define WPI_RX_STATUS 0xcc4 79 #define WPI_TX_CONFIG(qid) (0xd00 + (qid) * 32) 80 #define WPI_TX_CREDIT(qid) (0xd04 + (qid) * 32) 81 #define WPI_TX_STATE(qid) (0xd08 + (qid) * 32) 82 #define WPI_TX_BASE_PTR 0xe80 83 #define WPI_MSG_CONFIG 0xe88 84 #define WPI_TX_STATUS 0xe90 85 86 87 /* 88 * NIC internal memory offsets. 89 */ 90 #define WPI_MEM_MODE 0x2e00 91 #define WPI_MEM_RA 0x2e04 92 #define WPI_MEM_TXCFG 0x2e10 93 #define WPI_MEM_MAGIC4 0x2e14 94 #define WPI_MEM_MAGIC5 0x2e20 95 #define WPI_MEM_BYPASS1 0x2e2c 96 #define WPI_MEM_BYPASS2 0x2e30 97 #define WPI_MEM_CLOCK1 0x3004 98 #define WPI_MEM_CLOCK2 0x3008 99 #define WPI_MEM_POWER 0x300c 100 #define WPI_MEM_PCIDEV 0x3010 101 #define WPI_MEM_UCODE_CTL 0x3400 102 #define WPI_MEM_UCODE_SRC 0x3404 103 #define WPI_MEM_UCODE_DST 0x3408 104 #define WPI_MEM_UCODE_SIZE 0x340c 105 #define WPI_MEM_UCODE_BASE 0x3800 106 107 108 /* 109 * possible flags for register WPI_HWCONFIG 110 */ 111 #define WPI_HW_ALM_MB (1 << 8) 112 #define WPI_HW_ALM_MM (1 << 9) 113 #define WPI_HW_SKU_MRC (1 << 10) 114 #define WPI_HW_REV_D (1 << 11) 115 #define WPI_HW_TYPE_B (1 << 12) 116 117 /* 118 * possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR 119 */ 120 #define WPI_MEM_4 ((sizeof (uint32_t) - 1) << 24) 121 122 /* 123 * possible values for WPI_FW_TARGET 124 */ 125 #define WPI_FW_TEXT 0x00000000 126 #define WPI_FW_DATA 0x00800000 127 128 /* 129 * possible flags for WPI_GPIO_STATUS 130 */ 131 #define WPI_POWERED (1 << 9) 132 133 /* 134 * possible flags for register WPI_RESET 135 */ 136 #define WPI_NEVO_RESET (1 << 0) 137 #define WPI_SW_RESET (1 << 7) 138 #define WPI_MASTER_DISABLED (1 << 8) 139 #define WPI_STOP_MASTER (1 << 9) 140 141 /* 142 * possible flags for register WPI_GPIO_CTL 143 */ 144 #define WPI_GPIO_CLOCK (1 << 0) 145 #define WPI_GPIO_INIT (1 << 2) 146 #define WPI_GPIO_MAC (1 << 3) 147 #define WPI_GPIO_SLEEP (1 << 4) 148 #define WPI_GPIO_PWR_STATUS 0x07000000 149 #define WPI_GPIO_PWR_SLEEP (4 << 24) 150 151 /* 152 * possible flags for register WPI_CHICKEN 153 */ 154 #define WPI_CHICKEN_RXNOLOS (1 << 23) 155 156 /* 157 * possible flags for register WPI_PLL_CTL 158 */ 159 #define WPI_PLL_INIT (1 << 24) 160 161 /* 162 * possible flags for register WPI_UCODE_CLR 163 */ 164 #define WPI_RADIO_OFF (1 << 1) 165 #define WPI_DISABLE_CMD (1 << 2) 166 167 /* 168 * possible flags for WPI_RX_STATUS 169 */ 170 #define WPI_RX_IDLE (1 << 24) 171 172 /* 173 * possible flags for register WPI_UC_CTL 174 */ 175 #define WPI_UC_RUN (1 << 30) 176 177 /* 178 * possible flags for register WPI_INTR_CSR 179 */ 180 #define WPI_ALIVE_INTR (1 << 0) 181 #define WPI_WAKEUP_INTR (1 << 1) 182 #define WPI_SW_ERROR (1 << 25) 183 #define WPI_TX_INTR (1 << 27) 184 #define WPI_HW_ERROR (1 << 29) 185 #define WPI_RX_INTR (((uint32_t)1) << 31) 186 187 #define WPI_INTR_MASK \ 188 (WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR | \ 189 WPI_ALIVE_INTR | WPI_WAKEUP_INTR) 190 191 /* 192 * possible flags for register WPI_TX_STATUS 193 */ 194 #define WPI_TX_IDLE(qid) (1 << ((qid) + 24) | 1 << ((qid) + 16)) 195 196 /* 197 * possible flags for register WPI_EEPROM_CTL 198 */ 199 #define WPI_EEPROM_READY (1 << 0) 200 201 /* 202 * possible flags for register WPI_EEPROM_STATUS 203 */ 204 #define WPI_EEPROM_VERSION 0x00000007 205 #define WPI_EEPROM_LOCKED 0x00000180 206 207 208 typedef struct wpi_shared { 209 uint32_t txbase[8]; 210 uint32_t next; 211 uint32_t reserved[2]; 212 } wpi_shared_t; 213 214 #define WPI_MAX_SEG_LEN 65520 215 typedef struct wpi_tx_desc { 216 uint32_t flags; 217 #define WPI_PAD32(x) (roundup(x, 4) - (x)) 218 219 struct { 220 uint32_t addr; 221 uint32_t len; 222 } segs[WPI_MAX_SCATTER]; 223 uint8_t reserved[28]; 224 } wpi_tx_desc_t; 225 226 typedef struct wpi_tx_stat { 227 uint8_t nrts; 228 uint8_t ntries; 229 uint8_t nkill; 230 uint8_t rate; 231 uint32_t duration; 232 uint32_t status; 233 } wpi_tx_stat_t; 234 235 typedef struct wpi_rx_desc { 236 uint32_t len; 237 uint8_t type; 238 #define WPI_UC_READY 1 239 #define WPI_RX_DONE 27 240 #define WPI_TX_DONE 28 241 #define WPI_START_SCAN 130 242 #define WPI_START_RESULT 131 243 #define WPI_STOP_SCAN 132 244 #define WPI_STATE_CHANGED 161 245 246 uint8_t flags; 247 uint8_t idx; 248 uint8_t qid; 249 } wpi_rx_desc_t; 250 251 typedef struct wpi_rx_stat { 252 uint8_t len; 253 #define WPI_STAT_MAXLEN 20 254 255 uint8_t id; 256 uint8_t rssi; /* received signal strength */ 257 #define WPI_RSSI_OFFSET 95 258 259 uint8_t agc; /* access gain control */ 260 uint16_t signal; 261 uint16_t noise; 262 } wpi_rx_stat_t; 263 264 typedef struct wpi_rx_head { 265 uint16_t chan; 266 uint16_t flags; 267 uint8_t reserved; 268 uint8_t rate; 269 uint16_t len; 270 } wpi_rx_head_t; 271 272 typedef struct wpi_rx_tail { 273 uint32_t flags; 274 #define WPI_RX_NO_CRC_ERR (1 << 0) 275 #define WPI_RX_NO_OVFL_ERR (1 << 1) 276 #define WPI_RX_NOERROR (WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR) 277 278 uint64_t tstamp; 279 uint32_t tbeacon; 280 } wpi_rx_tail_t; 281 282 typedef struct wpi_tx_cmd { 283 uint8_t code; 284 #define WPI_CMD_CONFIGURE 16 285 #define WPI_CMD_ASSOCIATE 17 286 #define WPI_CMD_SET_WME 19 287 #define WPI_CMD_TSF 20 288 #define WPI_CMD_ADD_NODE 24 289 #define WPI_CMD_TX_DATA 28 290 #define WPI_CMD_MRR_SETUP 71 291 #define WPI_CMD_SET_LED 72 292 #define WPI_CMD_SET_POWER_MODE 119 293 #define WPI_CMD_SCAN 128 294 #define WPI_CMD_SET_BEACON 145 295 #define WPI_CMD_BLUETOOTH 155 296 #define WPI_CMD_TXPOWER 176 297 298 uint8_t flags; 299 uint8_t idx; 300 uint8_t qid; 301 uint8_t data[124]; 302 } wpi_tx_cmd_t; 303 304 /* 305 * structure for WPI_CMD_CONFIGURE 306 */ 307 typedef struct wpi_config { 308 uint8_t myaddr[IEEE80211_ADDR_LEN]; 309 uint16_t reserved1; 310 uint8_t bssid[IEEE80211_ADDR_LEN]; 311 uint16_t reserved2; 312 uint32_t reserved3[2]; 313 uint8_t mode; 314 #define WPI_MODE_HOSTAP 1 315 #define WPI_MODE_STA 3 316 #define WPI_MODE_IBSS 4 317 #define WPI_MODE_MONITOR 6 318 319 uint8_t reserved4[3]; 320 uint8_t ofdm_mask; 321 uint8_t cck_mask; 322 uint16_t state; 323 #define WPI_CONFIG_ASSOCIATED 4 324 325 uint32_t flags; 326 #define WPI_CONFIG_24GHZ (1 << 0) 327 #define WPI_CONFIG_CCK (1 << 1) 328 #define WPI_CONFIG_AUTO (1 << 2) 329 #define WPI_CONFIG_SHSLOT (1 << 4) 330 #define WPI_CONFIG_SHPREAMBLE (1 << 5) 331 #define WPI_CONFIG_NODIVERSITY (1 << 7) 332 #define WPI_CONFIG_ANTENNA_A (1 << 8) 333 #define WPI_CONFIG_ANTENNA_B (1 << 9) 334 #define WPI_CONFIG_TSF (1 << 15) 335 336 uint32_t filter; 337 #define WPI_FILTER_PROMISC (1 << 0) 338 #define WPI_FILTER_CTL (1 << 1) 339 #define WPI_FILTER_MULTICAST (1 << 2) 340 #define WPI_FILTER_NODECRYPTUNI (1 << 3) 341 #define WPI_FILTER_NODECRYPTMUL (1 << 4) 342 #define WPI_FILTER_BSS (1 << 5) 343 #define WPI_FILTER_BEACON (1 << 6) 344 345 uint8_t chan; 346 uint8_t reserved6[3]; 347 } wpi_config_t; 348 349 /* 350 * structure for command WPI_CMD_ASSOCIATE 351 */ 352 typedef struct wpi_assoc { 353 uint32_t flags; 354 uint32_t filter; 355 uint8_t ofdm_mask; 356 uint8_t cck_mask; 357 uint16_t reserved; 358 } wpi_assoc_t; 359 360 /* 361 * structure for command WPI_CMD_SET_WME 362 */ 363 typedef struct wpi_wme_setup { 364 uint32_t flags; 365 struct { 366 uint16_t cwmin; 367 uint16_t cwmax; 368 uint8_t aifsn; 369 uint8_t reserved; 370 uint16_t txop; 371 } ac[WME_NUM_AC]; 372 } wpi_wme_setup_t; 373 374 /* 375 * structure for command WPI_CMD_TSF 376 */ 377 typedef struct wpi_cmd_tsf { 378 uint64_t tstamp; 379 uint16_t bintval; 380 uint16_t atim; 381 uint32_t binitval; 382 uint16_t lintval; 383 uint16_t reserved; 384 } wpi_cmd_tsf_t; 385 386 /* 387 * structure for WPI_CMD_ADD_NODE 388 */ 389 typedef struct wpi_node { 390 uint8_t control; 391 #define WPI_NODE_UPDATE (1 << 0) 392 393 uint8_t reserved1[3]; 394 uint8_t bssid[IEEE80211_ADDR_LEN]; 395 uint16_t reserved2; 396 uint8_t id; 397 #define WPI_ID_BSS 0 398 #define WPI_ID_BROADCAST 24 399 400 uint8_t sta_mask; 401 uint16_t reserved3; 402 uint16_t key_flags; 403 uint8_t tkip; 404 uint8_t reserved4; 405 uint16_t ttak[5]; 406 uint8_t keyp; 407 uint8_t reserved5; 408 uint8_t key[16]; 409 uint32_t flags; 410 uint32_t mask; 411 uint16_t tid; 412 uint8_t rate; 413 uint8_t reserved6; 414 uint8_t add_imm; 415 uint8_t del_imm; 416 uint16_t add_imm_start; 417 } wpi_node_t; 418 419 /* 420 * structure for command WPI_CMD_TX_DATA 421 */ 422 typedef struct wpi_cmd_data { 423 uint16_t len; 424 uint16_t lnext; 425 uint32_t flags; 426 #define WPI_TX_NEED_RTS (1 << 1) 427 #define WPI_TX_NEED_ACK (1 << 3) 428 #define WPI_TX_FULL_TXOP (1 << 7) 429 #define WPI_TX_BT_DISABLE (1 << 12) 430 #define WPI_TX_AUTO_SEQ (1 << 13) 431 #define WPI_TX_INSERT_TSTAMP (1 << 16) 432 #define WPI_TX_CALIBRATION (1 << 17) 433 434 uint8_t rate; 435 uint8_t id; 436 uint8_t tid; 437 uint8_t security; 438 uint8_t key[16]; 439 uint8_t tkip[8]; 440 uint32_t fnext; 441 uint32_t lifetime; 442 uint8_t ofdm_mask; 443 uint8_t cck_mask; 444 uint8_t rts_ntries; 445 uint8_t data_ntries; 446 uint16_t timeout; 447 uint16_t txop; 448 } wpi_cmd_data_t; 449 450 /* 451 * structure for command WPI_CMD_SET_BEACON 452 */ 453 typedef struct wpi_cmd_beacon { 454 uint16_t len; 455 uint16_t reserved1; 456 uint32_t flags; /* same as wpi_cmd_data */ 457 uint8_t rate; 458 uint8_t id; 459 uint8_t reserved2[30]; 460 uint32_t lifetime; 461 uint8_t ofdm_mask; 462 uint8_t cck_mask; 463 uint16_t reserved3[3]; 464 uint16_t tim; 465 uint8_t timsz; 466 uint8_t reserved4; 467 struct ieee80211_frame wh; 468 } wpi_cmd_beacon_t; 469 470 /* 471 * structure for WPI_CMD_MRR_SETUP 472 */ 473 typedef struct wpi_mrr_setup { 474 uint32_t which; 475 #define WPI_MRR_CTL 0 476 #define WPI_MRR_DATA 1 477 478 struct { 479 uint8_t signal; 480 uint8_t flags; 481 uint8_t ntries; 482 uint8_t next; 483 #define WPI_OFDM6 0 484 #define WPI_OFDM54 7 485 #define WPI_CCK1 8 486 #define WPI_CCK11 11 487 488 } rates[WPI_CCK11 + 1]; 489 } wpi_mrr_setup_t; 490 491 /* 492 * structure for WPI_CMD_SET_LED 493 */ 494 typedef struct wpi_cmd_led { 495 uint32_t unit; /* multiplier (in usecs) */ 496 uint8_t which; 497 #define WPI_LED_ACTIVITY 1 498 #define WPI_LED_LINK 2 499 500 uint8_t off; 501 uint8_t on; 502 uint8_t reserved; 503 } wpi_cmd_led_t; 504 505 /* 506 * structure for WPI_CMD_SET_POWER_MODE 507 */ 508 typedef struct wpi_power { 509 uint32_t flags; 510 uint32_t rx_timeout; 511 uint32_t tx_timeout; 512 uint32_t sleep[5]; 513 } wpi_power_t; 514 515 /* 516 * structure for command WPI_CMD_SCAN 517 */ 518 typedef struct wpi_scan_hdr { 519 uint8_t len; 520 uint8_t first; 521 uint8_t reserved1; 522 uint8_t nchan; 523 uint16_t quiet; 524 uint16_t threshold; 525 uint32_t reserved2[3]; 526 uint32_t filter; 527 uint32_t reserved3; 528 uint16_t pbrlen; 529 uint16_t reserved4; 530 uint32_t magic1; 531 uint8_t rate; 532 uint8_t id; 533 uint16_t reserved5; 534 uint32_t reserved6[7]; 535 uint32_t mask; 536 uint32_t reserved7[2]; 537 uint8_t reserved8; 538 uint8_t esslen; 539 uint8_t essid[134]; 540 541 /* followed by probe request body */ 542 /* followed by nchan x wpi_scan_chan */ 543 } wpi_scan_hdr_t; 544 545 typedef struct wpi_scan_chan { 546 uint8_t flags; 547 uint8_t chan; 548 uint16_t magic; /* XXX */ 549 uint16_t active; /* dwell time */ 550 uint16_t passive; /* dwell time */ 551 } wpi_scan_chan_t; 552 553 /* 554 * structure for WPI_CMD_BLUETOOTH 555 */ 556 typedef struct wpi_bluetooth { 557 uint8_t flags; 558 uint8_t lead; 559 uint8_t kill; 560 uint8_t reserved; 561 uint32_t ack; 562 uint32_t cts; 563 } wpi_bluetooth_t; 564 565 /* 566 * structure for command WPI_CMD_TXPOWER 567 */ 568 typedef struct wpi_txpower { 569 uint32_t reserved1; 570 uint16_t pwr1[14]; 571 uint32_t reserved2[2]; 572 uint16_t pwr2[14]; 573 uint32_t reserved3[2]; 574 } wpi_txpower_t; 575 576 577 /* 578 * firmware image header 579 */ 580 typedef struct wpi_firmware_hdr { 581 uint32_t version; 582 uint32_t textsz; 583 uint32_t datasz; 584 uint32_t bootsz; 585 } wpi_firmware_hdr_t; 586 587 /* 588 * structure for WPI_UC_READY notification 589 */ 590 typedef struct wpi_ucode_info { 591 uint32_t version; 592 uint8_t revision[8]; 593 uint8_t type; 594 uint8_t subtype; 595 uint16_t reserved; 596 uint32_t logptr; 597 uint32_t errorptr; 598 uint32_t timestamp; 599 uint32_t valid; 600 } wpi_ucode_info_t; 601 602 /* 603 * structure for WPI_START_SCAN notification 604 */ 605 typedef struct wpi_start_scan { 606 uint64_t tstamp; 607 uint32_t tbeacon; 608 uint8_t chan; 609 uint8_t band; 610 uint16_t reserved; 611 uint32_t status; 612 } wpi_start_scan_t; 613 614 615 #define WPI_EEPROM_MAC 0x015 616 #define WPI_EEPROM_REVISION 0x035 617 #define WPI_EEPROM_CAPABILITIES 0x045 618 #define WPI_EEPROM_TYPE 0x04a 619 #define WPI_EEPROM_PWR1 0x1ae 620 #define WPI_EEPROM_PWR2 0x1bc 621 622 #define WPI_READ(sc, reg) \ 623 ddi_get32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg))) 624 625 #define WPI_WRITE(sc, reg, val) \ 626 ddi_put32((sc)->sc_handle, (uint32_t *)((sc)->sc_base + (reg)), (val)) 627 628 #define WPI_WRITE_REGION_4(sc, offset, datap, count) { \ 629 uint32_t *p = (datap); \ 630 uint32_t s = (offset); \ 631 uint32_t c = (count); \ 632 while (--c > 0) { \ 633 ddi_put32((sc)->sc_handle, \ 634 (uint32_t *)((sc)->sc_base + s), *p); \ 635 p++; \ 636 s += 4; \ 637 } \ 638 } 639 640 #ifdef __cplusplus 641 } 642 #endif 643 644 #endif /* _WPIREG_H_ */ 645