1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 /* 27 * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver, Depends on the 28 * Generic LAN Driver utility functions in /kernel/misc/mac 29 * 30 * This product is covered by one or more of the following patents: 31 * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and 32 * US6,327,625. 33 * 34 * Currently supports: 35 * RTL8139 36 */ 37 38 #include <sys/types.h> 39 #include <sys/debug.h> 40 #include <sys/errno.h> 41 42 #include <sys/stropts.h> 43 #include <sys/stream.h> 44 #include <sys/kmem.h> 45 #include <sys/conf.h> 46 #include <sys/ddi.h> 47 #include <sys/devops.h> 48 #include <sys/ksynch.h> 49 #include <sys/stat.h> 50 #include <sys/conf.h> 51 #include <sys/modctl.h> 52 #include <sys/dlpi.h> 53 #include <sys/ethernet.h> 54 #include <sys/vlan.h> 55 #include <sys/strsun.h> 56 #include <sys/pci.h> 57 #include <sys/sunddi.h> 58 #include <sys/mii.h> 59 #include <sys/miiregs.h> 60 #include <sys/mac_provider.h> 61 #include <sys/mac_ether.h> 62 63 #include "rtls.h" 64 65 /* 66 * Declarations and Module Linkage 67 */ 68 69 /* 70 * This is the string displayed by modinfo, etc. 71 */ 72 static char rtls_ident[] = "RealTek 8139 Ethernet driver"; 73 74 #ifdef RTLS_DEBUG 75 int rtls_debug = 0; 76 #endif 77 78 /* 79 * Required system entry points 80 */ 81 static int rtls_attach(dev_info_t *, ddi_attach_cmd_t); 82 static int rtls_detach(dev_info_t *, ddi_detach_cmd_t); 83 static int rtls_quiesce(dev_info_t *); 84 85 /* 86 * Required driver entry points for MAC 87 */ 88 static int rtls_m_start(void *); 89 static void rtls_m_stop(void *); 90 static int rtls_m_unicst(void *, const uint8_t *); 91 static int rtls_m_multicst(void *, boolean_t, const uint8_t *); 92 static int rtls_m_promisc(void *, boolean_t); 93 static mblk_t *rtls_m_tx(void *, mblk_t *); 94 static int rtls_m_getprop(void *, const char *, mac_prop_id_t, uint_t, 95 void *); 96 static int rtls_m_setprop(void *, const char *, mac_prop_id_t, uint_t, 97 const void *); 98 static void rtls_m_propinfo(void *, const char *, mac_prop_id_t, 99 mac_prop_info_handle_t); 100 static int rtls_m_stat(void *, uint_t, uint64_t *); 101 102 static uint_t rtls_intr(caddr_t); 103 104 /* 105 * MII entry points 106 */ 107 static uint16_t rtls_mii_read(void *, uint8_t, uint8_t); 108 static void rtls_mii_write(void *, uint8_t, uint8_t, uint16_t); 109 static void rtls_mii_notify(void *, link_state_t); 110 111 /* 112 * Internal functions used by the above entry points 113 */ 114 static int rtls_chip_reset(rtls_t *, boolean_t); 115 static void rtls_chip_init(rtls_t *); 116 static void rtls_chip_stop(rtls_t *rtlsp); 117 static void rtls_chip_start(rtls_t *rtlsp); 118 static void rtls_chip_restart(rtls_t *rtlsp); 119 static void rtls_get_mac_addr(rtls_t *, uint8_t *); 120 static void rtls_set_mac_addr(rtls_t *, const uint8_t *); 121 static uint_t rtls_hash_index(const uint8_t *); 122 static boolean_t rtls_send(rtls_t *, mblk_t *); 123 static void rtls_receive(rtls_t *); 124 125 /* 126 * Buffer Management Routines 127 */ 128 static int rtls_alloc_bufs(rtls_t *); 129 static void rtls_free_bufs(rtls_t *); 130 static int rtls_alloc_dma_mem(rtls_t *, size_t, ddi_device_acc_attr_t *, 131 uint_t, dma_area_t *); 132 static void rtls_free_dma_mem(dma_area_t *); 133 134 #ifdef RTLS_DEBUG 135 static void rtls_reg_print(rtls_t *); /* debug routine */ 136 #endif 137 138 #define RTLS_DRIVER_NAME "rtls" 139 140 /* 141 * Used for buffers allocated by ddi_dma_mem_alloc() 142 */ 143 static ddi_dma_attr_t dma_attr = { 144 DMA_ATTR_V0, /* dma_attr version */ 145 0, /* dma_attr_addr_lo */ 146 (uint_t)0xFFFFFFFF, /* dma_attr_addr_hi */ 147 0x7FFFFFFF, /* dma_attr_count_max */ 148 4, /* dma_attr_align */ 149 0x3F, /* dma_attr_burstsizes */ 150 1, /* dma_attr_minxfer */ 151 (uint_t)0xFFFFFFFF, /* dma_attr_maxxfer */ 152 (uint_t)0xFFFFFFFF, /* dma_attr_seg */ 153 1, /* dma_attr_sgllen */ 154 1, /* dma_attr_granular */ 155 0, /* dma_attr_flags */ 156 }; 157 158 /* 159 * PIO access attributes for registers 160 */ 161 static ddi_device_acc_attr_t rtls_reg_accattr = { 162 DDI_DEVICE_ATTR_V0, 163 DDI_STRUCTURE_LE_ACC, 164 DDI_STRICTORDER_ACC 165 }; 166 167 /* 168 * DMA access attributes for data 169 */ 170 static ddi_device_acc_attr_t rtls_buf_accattr = { 171 DDI_DEVICE_ATTR_V0, 172 DDI_NEVERSWAP_ACC, 173 DDI_STRICTORDER_ACC 174 }; 175 176 uchar_t rtls_broadcastaddr[] = { 177 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 178 }; 179 180 static mac_callbacks_t rtls_m_callbacks = { 181 MC_PROPERTIES, 182 rtls_m_stat, 183 rtls_m_start, 184 rtls_m_stop, 185 rtls_m_promisc, 186 rtls_m_multicst, 187 rtls_m_unicst, 188 rtls_m_tx, 189 NULL, 190 NULL, /* mc_ioctl */ 191 NULL, /* mc_getcapab */ 192 NULL, /* mc_open */ 193 NULL, /* mc_close */ 194 rtls_m_setprop, 195 rtls_m_getprop, 196 rtls_m_propinfo 197 }; 198 199 static mii_ops_t rtls_mii_ops = { 200 MII_OPS_VERSION, 201 rtls_mii_read, 202 rtls_mii_write, 203 rtls_mii_notify, /* notify */ 204 NULL, /* reset */ 205 }; 206 207 DDI_DEFINE_STREAM_OPS(rtls_dev_ops, nulldev, nulldev, rtls_attach, rtls_detach, 208 nodev, NULL, D_MP, NULL, rtls_quiesce); 209 210 /* 211 * Standard module linkage initialization for a MAC driver 212 */ 213 static struct modldrv rtls_modldrv = { 214 &mod_driverops, /* type of module. This one is a driver */ 215 rtls_ident, /* short description */ 216 &rtls_dev_ops /* driver specific ops */ 217 }; 218 219 static struct modlinkage modlinkage = { 220 MODREV_1, { (void *)&rtls_modldrv, NULL } 221 }; 222 223 /* 224 * ========== RealTek chip register access Routines ========== 225 */ 226 static uint8_t rtls_reg_get8(rtls_t *rtlsp, uint32_t reg); 227 #pragma inline(rtls_reg_get8) 228 static uint8_t 229 rtls_reg_get8(rtls_t *rtlsp, uint32_t reg) 230 { 231 uint8_t *addr; 232 233 addr = REG8(rtlsp->io_reg, reg); 234 return (ddi_get8(rtlsp->io_handle, addr)); 235 } 236 237 static uint16_t rtls_reg_get16(rtls_t *rtlsp, uint32_t reg); 238 #pragma inline(rtls_reg_get16) 239 static uint16_t 240 rtls_reg_get16(rtls_t *rtlsp, uint32_t reg) 241 { 242 uint16_t *addr; 243 244 addr = REG16(rtlsp->io_reg, reg); 245 return (ddi_get16(rtlsp->io_handle, addr)); 246 } 247 248 static uint32_t rtls_reg_get32(rtls_t *rtlsp, uint32_t reg); 249 #pragma inline(rtls_reg_get32) 250 static uint32_t 251 rtls_reg_get32(rtls_t *rtlsp, uint32_t reg) 252 { 253 uint32_t *addr; 254 255 addr = REG32(rtlsp->io_reg, reg); 256 return (ddi_get32(rtlsp->io_handle, addr)); 257 } 258 259 static void rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value); 260 #pragma inline(rtls_reg_set8) 261 static void 262 rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value) 263 { 264 uint8_t *addr; 265 266 addr = REG8(rtlsp->io_reg, reg); 267 ddi_put8(rtlsp->io_handle, addr, value); 268 } 269 270 static void rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value); 271 #pragma inline(rtls_reg_set16) 272 static void 273 rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value) 274 { 275 uint16_t *addr; 276 277 addr = REG16(rtlsp->io_reg, reg); 278 ddi_put16(rtlsp->io_handle, addr, value); 279 } 280 281 static void rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value); 282 #pragma inline(rtls_reg_set32) 283 static void 284 rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value) 285 { 286 uint32_t *addr; 287 288 addr = REG32(rtlsp->io_reg, reg); 289 ddi_put32(rtlsp->io_handle, addr, value); 290 } 291 292 /* 293 * ========== Module Loading Entry Points ========== 294 */ 295 int 296 _init(void) 297 { 298 int rv; 299 300 mac_init_ops(&rtls_dev_ops, RTLS_DRIVER_NAME); 301 if ((rv = mod_install(&modlinkage)) != DDI_SUCCESS) { 302 mac_fini_ops(&rtls_dev_ops); 303 } 304 return (rv); 305 } 306 307 int 308 _fini(void) 309 { 310 int rv; 311 312 if ((rv = mod_remove(&modlinkage)) == DDI_SUCCESS) { 313 mac_fini_ops(&rtls_dev_ops); 314 } 315 return (rv); 316 } 317 318 int 319 _info(struct modinfo *modinfop) 320 { 321 return (mod_info(&modlinkage, modinfop)); 322 } 323 324 325 /* 326 * ========== DDI Entry Points ========== 327 */ 328 329 /* 330 * attach(9E) -- Attach a device to the system 331 * 332 * Called once for each board successfully probed. 333 */ 334 static int 335 rtls_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 336 { 337 rtls_t *rtlsp; /* Our private device info */ 338 ddi_acc_handle_t pci_handle; 339 uint16_t pci_commond; 340 uint16_t vendorid; 341 uint16_t deviceid; 342 uint32_t device; 343 mac_register_t *macp; 344 int err; 345 346 switch (cmd) { 347 case DDI_ATTACH: 348 break; 349 case DDI_RESUME: 350 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 351 return (DDI_FAILURE); 352 } 353 mutex_enter(&rtlsp->rtls_io_lock); 354 mutex_enter(&rtlsp->rtls_rx_lock); 355 mutex_enter(&rtlsp->rtls_tx_lock); 356 /* 357 * Turn on Master Enable (DMA) and IO Enable bits. 358 * Enable PCI Memory Space accesses 359 * Disable Memory Write/Invalidate 360 */ 361 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 362 mutex_exit(&rtlsp->rtls_tx_lock); 363 mutex_exit(&rtlsp->rtls_rx_lock); 364 mutex_exit(&rtlsp->rtls_io_lock); 365 return (DDI_FAILURE); 366 } 367 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 368 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 369 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 370 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 371 pci_config_teardown(&pci_handle); 372 373 rtls_chip_restart(rtlsp); 374 rtlsp->chip_error = B_FALSE; 375 rtlsp->tx_retry = 0; 376 rtlsp->rtls_suspended = B_FALSE; 377 mutex_exit(&rtlsp->rtls_tx_lock); 378 mutex_exit(&rtlsp->rtls_rx_lock); 379 mutex_exit(&rtlsp->rtls_io_lock); 380 381 mii_resume(rtlsp->mii); 382 383 mac_tx_update(rtlsp->mh); 384 return (DDI_SUCCESS); 385 default: 386 return (DDI_FAILURE); 387 } 388 389 /* 390 * we don't support high level interrupts in the driver 391 */ 392 if (ddi_intr_hilevel(devinfo, 0) != 0) { 393 cmn_err(CE_WARN, "unsupported high level interrupt"); 394 return (DDI_FAILURE); 395 } 396 397 /* 398 * Get handle to access pci configuration space 399 */ 400 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 401 cmn_err(CE_WARN, "pci_config_setup fail."); 402 return (DDI_FAILURE); 403 } 404 405 /* 406 * Make sure we support this particular vendor/device 407 */ 408 vendorid = pci_config_get16(pci_handle, PCI_CONF_VENID); 409 deviceid = pci_config_get16(pci_handle, PCI_CONF_DEVID); 410 device = vendorid; 411 device = (device << 16) | deviceid; /* combine two id together */ 412 413 /* 414 * See if we support this device 415 * We do not return for wrong device id. It's user risk. 416 */ 417 switch (device) { 418 default: 419 cmn_err(CE_WARN, 420 "RTLS doesn't support this device: " 421 "vendorID = 0x%x, deviceID = 0x%x", 422 vendorid, deviceid); 423 break; 424 case RTLS_SUPPORT_DEVICE_1: 425 case RTLS_SUPPORT_DEVICE_2: 426 case RTLS_SUPPORT_DEVICE_3: 427 case RTLS_SUPPORT_DEVICE_4: 428 break; 429 } 430 431 /* 432 * Turn on Master Enable (DMA) and IO Enable bits. 433 * Enable PCI Memory Space accesses 434 * Disable Memory Write/Invalidate 435 */ 436 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 437 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 438 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 439 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 440 441 /* 442 * Free handle to access pci configuration space 443 */ 444 pci_config_teardown(&pci_handle); 445 446 rtlsp = kmem_zalloc(sizeof (rtls_t), KM_SLEEP); 447 448 ddi_set_driver_private(devinfo, rtlsp); 449 rtlsp->devinfo = devinfo; 450 rtlsp->instance = ddi_get_instance(devinfo); 451 452 /* 453 * Map operating register 454 */ 455 err = ddi_regs_map_setup(devinfo, 1, &rtlsp->io_reg, 456 (offset_t)0, 0, &rtls_reg_accattr, &rtlsp->io_handle); 457 if (err != DDI_SUCCESS) { 458 kmem_free((caddr_t)rtlsp, sizeof (rtls_t)); 459 cmn_err(CE_WARN, "ddi_regs_map_setup fail."); 460 return (DDI_FAILURE); 461 } 462 463 /* 464 * Allocate the TX and RX descriptors/buffers 465 */ 466 if (rtls_alloc_bufs(rtlsp) == DDI_FAILURE) { 467 cmn_err(CE_WARN, "DMA buffer allocation fail."); 468 goto fail; 469 } 470 471 /* 472 * Reset the chip 473 */ 474 err = rtls_chip_reset(rtlsp, B_FALSE); 475 if (err != DDI_SUCCESS) 476 goto fail; 477 478 /* 479 * Init rtls_t structure 480 */ 481 rtls_get_mac_addr(rtlsp, rtlsp->netaddr); 482 483 /* 484 * Add the interrupt handler 485 * 486 * This will prevent receiving interrupts before device is ready, as 487 * we are initializing device after setting the interrupts. So we 488 * will not get our interrupt handler invoked by OS while our device 489 * is still coming up or timer routines will not start till we are 490 * all set to process... 491 */ 492 493 if (ddi_add_intr(devinfo, 0, &rtlsp->iblk, NULL, rtls_intr, 494 (caddr_t)rtlsp) != DDI_SUCCESS) { 495 cmn_err(CE_WARN, "ddi_add_intr fail."); 496 goto late_fail; 497 } 498 499 if ((rtlsp->mii = mii_alloc(rtlsp, devinfo, &rtls_mii_ops)) == NULL) { 500 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 501 goto late_fail; 502 } 503 /* 504 * Note: Some models of 8139 can support pause, but we have 505 * not implemented support for it at this time. This might be 506 * an interesting feature to add later. 507 */ 508 mii_set_pauseable(rtlsp->mii, B_FALSE, B_FALSE); 509 510 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 511 cmn_err(CE_WARN, "mac_alloc fail."); 512 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 513 goto late_fail; 514 } 515 516 /* 517 * Init mutex 518 */ 519 mutex_init(&rtlsp->rtls_io_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 520 mutex_init(&rtlsp->rtls_tx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 521 mutex_init(&rtlsp->rtls_rx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 522 523 /* 524 * Initialize pointers to device specific functions which will be 525 * used by the generic layer. 526 */ 527 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 528 macp->m_driver = rtlsp; 529 macp->m_dip = devinfo; 530 macp->m_src_addr = rtlsp->netaddr; 531 macp->m_callbacks = &rtls_m_callbacks; 532 macp->m_min_sdu = 0; 533 macp->m_max_sdu = ETHERMTU; 534 macp->m_margin = VLAN_TAGSZ; 535 536 if (mac_register(macp, &rtlsp->mh) != 0) { 537 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 538 mutex_destroy(&rtlsp->rtls_io_lock); 539 mutex_destroy(&rtlsp->rtls_tx_lock); 540 mutex_destroy(&rtlsp->rtls_rx_lock); 541 goto late_fail; 542 } 543 544 mac_free(macp); 545 546 return (DDI_SUCCESS); 547 548 late_fail: 549 if (macp) 550 mac_free(macp); 551 if (rtlsp->mii) 552 mii_free(rtlsp->mii); 553 554 fail: 555 ddi_regs_map_free(&rtlsp->io_handle); 556 rtls_free_bufs(rtlsp); 557 kmem_free(rtlsp, sizeof (rtls_t)); 558 559 return (DDI_FAILURE); 560 } 561 562 /* 563 * detach(9E) -- Detach a device from the system 564 */ 565 static int 566 rtls_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 567 { 568 rtls_t *rtlsp; /* our private device info */ 569 570 /* 571 * Get the driver private structure 572 */ 573 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 574 return (DDI_FAILURE); 575 } 576 577 switch (cmd) { 578 case DDI_DETACH: 579 break; 580 581 case DDI_SUSPEND: 582 mii_suspend(rtlsp->mii); 583 584 mutex_enter(&rtlsp->rtls_io_lock); 585 mutex_enter(&rtlsp->rtls_rx_lock); 586 mutex_enter(&rtlsp->rtls_tx_lock); 587 588 rtlsp->rtls_suspended = B_TRUE; 589 rtls_chip_stop(rtlsp); 590 591 mutex_exit(&rtlsp->rtls_tx_lock); 592 mutex_exit(&rtlsp->rtls_rx_lock); 593 mutex_exit(&rtlsp->rtls_io_lock); 594 return (DDI_SUCCESS); 595 596 default: 597 return (DDI_FAILURE); 598 } 599 600 if (mac_unregister(rtlsp->mh) != 0) { 601 /* device busy */ 602 return (DDI_FAILURE); 603 } 604 605 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 606 607 mii_free(rtlsp->mii); 608 609 mutex_destroy(&rtlsp->rtls_io_lock); 610 mutex_destroy(&rtlsp->rtls_tx_lock); 611 mutex_destroy(&rtlsp->rtls_rx_lock); 612 613 ddi_regs_map_free(&rtlsp->io_handle); 614 rtls_free_bufs(rtlsp); 615 kmem_free(rtlsp, sizeof (rtls_t)); 616 617 return (DDI_SUCCESS); 618 } 619 620 /* 621 * quiesce(9E) entry point. 622 * 623 * This function is called when the system is single-threaded at high 624 * PIL with preemption disabled. Therefore, this function must not be 625 * blocked. 626 * 627 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 628 * DDI_FAILURE indicates an error condition and should almost never happen. 629 */ 630 static int 631 rtls_quiesce(dev_info_t *devinfo) 632 { 633 rtls_t *rtlsp; /* our private device info */ 634 635 /* 636 * Get the driver private structure 637 */ 638 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 639 return (DDI_FAILURE); 640 } 641 return (rtls_chip_reset(rtlsp, B_TRUE)); 642 } 643 644 /* 645 * ========== MAC Entry Points ========== 646 */ 647 648 /* 649 * rtls_m_start() -- start the board receiving and allow transmits 650 */ 651 static int 652 rtls_m_start(void *arg) 653 { 654 rtls_t *rtlsp = (rtls_t *)arg; 655 656 mutex_enter(&rtlsp->rtls_io_lock); 657 mutex_enter(&rtlsp->rtls_rx_lock); 658 mutex_enter(&rtlsp->rtls_tx_lock); 659 660 if (!rtlsp->rtls_suspended) 661 rtls_chip_restart(rtlsp); 662 663 rtlsp->rtls_running = B_TRUE; 664 665 mutex_exit(&rtlsp->rtls_tx_lock); 666 mutex_exit(&rtlsp->rtls_rx_lock); 667 mutex_exit(&rtlsp->rtls_io_lock); 668 669 drv_usecwait(100); 670 671 mii_start(rtlsp->mii); 672 673 return (0); 674 } 675 676 /* 677 * rtls_m_stop() -- stop board receiving and transmits 678 */ 679 static void 680 rtls_m_stop(void *arg) 681 { 682 rtls_t *rtlsp = (rtls_t *)arg; 683 684 mii_stop(rtlsp->mii); 685 686 mutex_enter(&rtlsp->rtls_io_lock); 687 688 if (!rtlsp->rtls_suspended) 689 rtls_chip_stop(rtlsp); 690 rtlsp->rtls_running = B_FALSE; 691 692 mutex_exit(&rtlsp->rtls_io_lock); 693 } 694 695 /* 696 * rtls_m_unicst() -- set the physical network address 697 * on the board 698 */ 699 static int 700 rtls_m_unicst(void *arg, const uint8_t *macaddr) 701 { 702 rtls_t *rtlsp = arg; 703 704 mutex_enter(&rtlsp->rtls_io_lock); 705 bcopy(macaddr, rtlsp->netaddr, ETHERADDRL); 706 if (!rtlsp->rtls_suspended) 707 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 708 mutex_exit(&rtlsp->rtls_io_lock); 709 return (0); 710 } 711 712 /* 713 * rtls_m_multicst() -- set(enable) or disable a multicast address 714 * 715 * Program the hardware to enable/disable the multicast address in "mcast". 716 */ 717 static int 718 rtls_m_multicst(void *arg, boolean_t enable, const uint8_t *mcast) 719 { 720 rtls_t *rtlsp = (rtls_t *)arg; 721 uint_t index; 722 uint32_t *hashp; 723 724 mutex_enter(&rtlsp->rtls_io_lock); 725 hashp = rtlsp->multi_hash; 726 index = rtls_hash_index(mcast); 727 /* index value is between 0 and 63 */ 728 729 if (enable) { 730 if (rtlsp->multicast_cnt[index]++) { 731 mutex_exit(&rtlsp->rtls_io_lock); 732 return (0); 733 } 734 hashp[index/32] |= 1<< (index % 32); 735 } else { 736 if (--rtlsp->multicast_cnt[index]) { 737 mutex_exit(&rtlsp->rtls_io_lock); 738 return (0); 739 } 740 hashp[index/32] &= ~(1<< (index % 32)); 741 } 742 743 /* 744 * Set multicast register 745 */ 746 if (!rtlsp->rtls_suspended) { 747 rtls_reg_set32(rtlsp, MULTICAST_0_REG, hashp[0]); 748 rtls_reg_set32(rtlsp, MULTICAST_4_REG, hashp[1]); 749 } 750 751 mutex_exit(&rtlsp->rtls_io_lock); 752 753 return (0); 754 } 755 756 /* 757 * rtls_hash_index() -- a hashing function used for setting the 758 * node address or a multicast address 759 */ 760 static uint_t 761 rtls_hash_index(const uint8_t *address) 762 { 763 uint32_t crc = (ulong_t)RTLS_HASH_CRC; 764 uint32_t const POLY = RTLS_HASH_POLY; 765 uint32_t msb; 766 int bytes; 767 uchar_t currentbyte; 768 uint_t index; 769 int bit; 770 771 for (bytes = 0; bytes < ETHERADDRL; bytes++) { 772 currentbyte = address[bytes]; 773 for (bit = 0; bit < 8; bit++) { 774 msb = crc >> 31; 775 crc <<= 1; 776 if (msb ^ (currentbyte & 1)) { 777 crc ^= POLY; 778 crc |= 0x00000001; 779 } 780 currentbyte >>= 1; 781 } 782 } 783 784 index = crc >> 26; 785 786 return (index); 787 } 788 789 /* 790 * rtls_m_promisc() -- set or reset promiscuous mode on the board 791 */ 792 static int 793 rtls_m_promisc(void *arg, boolean_t on) 794 { 795 rtls_t *rtlsp = arg; 796 797 mutex_enter(&rtlsp->rtls_io_lock); 798 799 rtlsp->promisc = on; 800 if (!rtlsp->rtls_suspended) { 801 uint32_t val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 802 if (on) { 803 val32 |= RX_ACCEPT_ALL_PACKET; 804 } else { 805 val32 &= ~RX_ACCEPT_ALL_PACKET; 806 } 807 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32); 808 } 809 mutex_exit(&rtlsp->rtls_io_lock); 810 811 return (0); 812 } 813 814 /* 815 * rtls_m_stat() -- retrieve statistic 816 * 817 * MAC calls this routine just before it reads the driver's statistics 818 * structure. If your board maintains statistics, this is the time to 819 * read them in and update the values in the structure. If the driver 820 * maintains statistics continuously, this routine need do nothing. 821 */ 822 static int 823 rtls_m_stat(void *arg, uint_t stat, uint64_t *val) 824 { 825 rtls_t *rtlsp = arg; 826 827 if (mii_m_getstat(rtlsp->mii, stat, val) == 0) { 828 return (0); 829 } 830 831 switch (stat) { 832 case MAC_STAT_IPACKETS: 833 *val = rtlsp->stats.ipackets; 834 break; 835 case MAC_STAT_RBYTES: 836 *val = rtlsp->stats.rbytes; 837 break; 838 case MAC_STAT_OPACKETS: 839 *val = rtlsp->stats.opackets; 840 break; 841 case MAC_STAT_OBYTES: 842 *val = rtlsp->stats.obytes; 843 break; 844 case MAC_STAT_IERRORS: 845 *val = rtlsp->stats.rcv_err; 846 break; 847 case MAC_STAT_OERRORS: 848 *val = rtlsp->stats.xmt_err; 849 break; 850 case MAC_STAT_MULTIRCV: 851 *val = rtlsp->stats.multi_rcv; 852 break; 853 case MAC_STAT_BRDCSTRCV: 854 *val = rtlsp->stats.brdcst_rcv; 855 break; 856 case MAC_STAT_MULTIXMT: 857 *val = rtlsp->stats.multi_xmt; 858 break; 859 case MAC_STAT_BRDCSTXMT: 860 *val = rtlsp->stats.brdcst_xmt; 861 break; 862 case MAC_STAT_UNDERFLOWS: 863 *val = rtlsp->stats.underflow; 864 break; 865 case MAC_STAT_OVERFLOWS: 866 *val = rtlsp->stats.overflow; 867 break; 868 case MAC_STAT_NORCVBUF: 869 *val = rtlsp->stats.no_rcvbuf; 870 break; 871 case MAC_STAT_COLLISIONS: 872 *val = rtlsp->stats.collisions; 873 break; 874 case ETHER_STAT_FCS_ERRORS: 875 *val = rtlsp->stats.crc_err; 876 break; 877 case ETHER_STAT_ALIGN_ERRORS: 878 *val = rtlsp->stats.frame_err; 879 break; 880 case ETHER_STAT_DEFER_XMTS: 881 *val = rtlsp->stats.defer; 882 break; 883 case ETHER_STAT_TX_LATE_COLLISIONS: 884 *val = rtlsp->stats.xmt_latecoll; 885 break; 886 case ETHER_STAT_TOOLONG_ERRORS: 887 *val = rtlsp->stats.too_long; 888 break; 889 case ETHER_STAT_TOOSHORT_ERRORS: 890 *val = rtlsp->stats.in_short; 891 break; 892 case ETHER_STAT_CARRIER_ERRORS: 893 *val = rtlsp->stats.no_carrier; 894 break; 895 case ETHER_STAT_FIRST_COLLISIONS: 896 *val = rtlsp->stats.firstcol; 897 break; 898 case ETHER_STAT_MULTI_COLLISIONS: 899 *val = rtlsp->stats.multicol; 900 break; 901 default: 902 return (ENOTSUP); 903 } 904 905 /* 906 * RTL8139 don't support MII statistics, 907 * these values are maintained by the driver software. 908 */ 909 910 #ifdef RTLS_DEBUG 911 if (rtls_debug & RTLS_TRACE) 912 rtls_reg_print(rtlsp); 913 #endif 914 915 return (0); 916 } 917 918 int 919 rtls_m_getprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz, 920 void *val) 921 { 922 rtls_t *rtlsp = arg; 923 924 return (mii_m_getprop(rtlsp->mii, name, num, sz, val)); 925 } 926 927 int 928 rtls_m_setprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz, 929 const void *val) 930 { 931 rtls_t *rtlsp = arg; 932 933 return (mii_m_setprop(rtlsp->mii, name, num, sz, val)); 934 } 935 936 static void 937 rtls_m_propinfo(void *arg, const char *name, mac_prop_id_t num, 938 mac_prop_info_handle_t prh) 939 { 940 rtls_t *rtlsp = arg; 941 942 mii_m_propinfo(rtlsp->mii, name, num, prh); 943 } 944 945 /* 946 * rtls_send() -- send a packet 947 * 948 * Called when a packet is ready to be transmitted. A pointer to an 949 * M_DATA message that contains the packet is passed to this routine. 950 * The complete LLC header is contained in the message's first message 951 * block, and the remainder of the packet is contained within 952 * additional M_DATA message blocks linked to the first message block. 953 * 954 * Returns B_TRUE if the packet was properly disposed of, or B_FALSE if 955 * if the packet is being deferred and should be tried again later. 956 */ 957 958 static boolean_t 959 rtls_send(rtls_t *rtlsp, mblk_t *mp) 960 { 961 int totlen; 962 int ncc; 963 uint16_t cur_desc; 964 uint32_t tx_status; 965 966 ASSERT(mp != NULL); 967 ASSERT(rtlsp->rtls_running); 968 969 mutex_enter(&rtlsp->rtls_tx_lock); 970 971 if (rtlsp->rtls_suspended) { 972 mutex_exit(&rtlsp->rtls_tx_lock); 973 return (B_FALSE); 974 } 975 976 /* 977 * If chip error ... 978 */ 979 if (rtlsp->chip_error) { 980 #ifdef RTLS_DEBUG 981 cmn_err(CE_WARN, 982 "%s: send fail--CHIP ERROR!", 983 rtlsp->ifname); 984 #endif 985 mutex_exit(&rtlsp->rtls_tx_lock); 986 freemsg(mp); 987 return (B_TRUE); 988 } 989 990 /* 991 * If chip link down ... Note that experimentation shows that 992 * the device seems not to care about whether or not we have 993 * this check, but if we don't add the check here, it might 994 * not be properly reported as a carrier error. 995 */ 996 if (rtls_reg_get8(rtlsp, MEDIA_STATUS_REG) & MEDIA_STATUS_LINK) { 997 #ifdef RTLS_DEBUG 998 cmn_err(CE_WARN, 999 "%s: send fail--LINK DOWN!", 1000 rtlsp->ifname); 1001 #endif 1002 rtlsp->stats.no_carrier++; 1003 mutex_exit(&rtlsp->rtls_tx_lock); 1004 freemsg(mp); 1005 return (B_TRUE); 1006 } 1007 1008 /* 1009 * Current transmit descriptor 1010 */ 1011 cur_desc = rtlsp->tx_current_desc; 1012 ASSERT(cur_desc < RTLS_MAX_TX_DESC); 1013 1014 /* 1015 * RealTek 8139 has 4 tx descriptor for transmit. In the first tx loop 1016 * of transmit,we needn't judge transmit status. 1017 */ 1018 if (rtlsp->tx_first_loop < RTLS_MAX_TX_DESC) { 1019 rtlsp->tx_first_loop++; 1020 goto tx_ready; 1021 } 1022 1023 /* 1024 * If it's not the first tx loop, we need judge whether the chip is 1025 * busy or not. Otherwise, we have to reschedule send and wait... 1026 */ 1027 tx_status = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc); 1028 1029 /* 1030 * H/W doesn't complete packet transmit 1031 */ 1032 if (!(tx_status & TX_COMPLETE_FLAG)) { 1033 #ifdef RTLS_DEBUG 1034 if (rtls_debug & RTLS_SEND) { 1035 cmn_err(CE_NOTE, 1036 "%s: rtls_send: need_sched", rtlsp->ifname); 1037 } 1038 #endif 1039 /* 1040 * Through test, we find RTL8139 tx status might be 1041 * not-completing all along. We have to reset chip 1042 * to make RTL8139 tansmit re-work. 1043 */ 1044 if (rtlsp->tx_retry++ > RTLS_TX_RETRY_NUM) { 1045 1046 /* 1047 * Wait transmit h/w more time... 1048 */ 1049 RTLS_TX_WAIT_TIMEOUT; /* 100 ms */ 1050 1051 /* 1052 * Judge tx status again, if it remains not-completing, 1053 * we can confirm RTL8139 is in chip error state 1054 * and must reset it. 1055 */ 1056 tx_status = rtls_reg_get32(rtlsp, 1057 TX_STATUS_DESC0_REG + 4 * cur_desc); 1058 if (!(tx_status & TX_COMPLETE_FLAG)) { 1059 #ifdef RTLS_DEBUG 1060 cmn_err(CE_NOTE, "%s: tx chip_error = 0x%x", 1061 rtlsp->ifname, tx_status); 1062 #endif 1063 rtlsp->tx_retry = 0; 1064 rtlsp->chip_error = B_TRUE; 1065 rtlsp->stats.xmt_err++; 1066 rtlsp->stats.mac_xmt_err++; 1067 mutex_exit(&rtlsp->rtls_tx_lock); 1068 freemsg(mp); 1069 return (B_TRUE); 1070 } 1071 } else { 1072 rtlsp->stats.defer++; 1073 rtlsp->need_sched = B_TRUE; 1074 mutex_exit(&rtlsp->rtls_tx_lock); 1075 return (B_FALSE); 1076 } 1077 } 1078 1079 /* 1080 * Transmit error? 1081 */ 1082 if (tx_status & TX_ERR_FLAG) { 1083 #ifdef RTLS_DEBUG 1084 if (rtls_debug & RTLS_SEND) { 1085 cmn_err(CE_NOTE, "%s: transmit error, status = 0x%x", 1086 rtlsp->ifname, tx_status); 1087 } 1088 #endif 1089 rtlsp->stats.xmt_err++; 1090 if (tx_status & TX_STATUS_TX_UNDERRUN) 1091 rtlsp->stats.underflow++; 1092 if (tx_status & TX_STATUS_CS_LOST) 1093 rtlsp->stats.no_carrier++; 1094 if (tx_status & TX_STATUS_OWC) 1095 rtlsp->stats.xmt_latecoll++; 1096 } 1097 ncc = ((tx_status & TX_STATUS_NCC) >> TX_STATUS_NCC_SHIFT); 1098 if (ncc != 0) { 1099 rtlsp->stats.collisions += ncc; 1100 rtlsp->stats.firstcol++; 1101 rtlsp->stats.multicol += ncc - 1; 1102 } 1103 1104 tx_ready: 1105 /* 1106 * Initialize variable 1107 */ 1108 rtlsp->tx_retry = 0; 1109 totlen = 0; 1110 1111 /* 1112 * Copy packet to tx descriptor buffer 1113 */ 1114 totlen = msgsize(mp); 1115 if (totlen > (ETHERMAX + 4)) { /* 4 bytes for VLAN header */ 1116 cmn_err(CE_NOTE, 1117 "%s: rtls_send: try to send large %d packet", 1118 rtlsp->ifname, totlen); 1119 rtlsp->stats.mac_xmt_err++; 1120 rtlsp->stats.xmt_err++; 1121 freemsg(mp); 1122 mutex_exit(&rtlsp->rtls_tx_lock); 1123 return (B_TRUE); 1124 } 1125 1126 /* this will free the mblk */ 1127 mcopymsg(mp, rtlsp->tx_buf[cur_desc]); 1128 1129 /* update stats */ 1130 if (*rtlsp->tx_buf[cur_desc] & 0x1) { 1131 uint16_t *ptr = (void *)rtlsp->tx_buf[cur_desc]; 1132 if ((ptr[0] == 0xffff) && 1133 (ptr[1] == 0xffff) && 1134 (ptr[2] == 0xffff)) { 1135 rtlsp->stats.brdcst_xmt++; 1136 } else { 1137 rtlsp->stats.multi_xmt++; 1138 } 1139 } 1140 rtlsp->stats.opackets++; 1141 rtlsp->stats.obytes += totlen; 1142 1143 if (totlen < ETHERMIN) { 1144 bzero(rtlsp->tx_buf[cur_desc] + totlen, ETHERMIN - totlen); 1145 totlen = ETHERMIN; 1146 } 1147 1148 /* make sure caches are flushed */ 1149 (void) ddi_dma_sync(rtlsp->dma_area_tx[cur_desc].dma_hdl, 0, totlen, 1150 DDI_DMA_SYNC_FORDEV); 1151 1152 /* 1153 * Start transmit 1154 * set transmit FIFO threshhold to 0x30*32 = 1536 bytes 1155 * to avoid tx underrun. 1156 */ 1157 rtls_reg_set32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc, 1158 totlen | (0x30 << TX_STATUS_TX_THRESHOLD_SHIFT)); 1159 1160 /* 1161 * Update the value of current tx descriptor 1162 */ 1163 cur_desc++; 1164 cur_desc %= RTLS_MAX_TX_DESC; 1165 rtlsp->tx_current_desc = cur_desc; 1166 1167 mutex_exit(&rtlsp->rtls_tx_lock); 1168 1169 return (B_TRUE); 1170 } 1171 1172 /* 1173 * rtls_m_tx() -- send a chain of packets, linked by mp->b_next. 1174 */ 1175 static mblk_t * 1176 rtls_m_tx(void *arg, mblk_t *mp) 1177 { 1178 rtls_t *rtlsp = arg; 1179 mblk_t *next; 1180 1181 while (mp != NULL) { 1182 next = mp->b_next; 1183 mp->b_next = NULL; 1184 if (!rtls_send(rtlsp, mp)) { 1185 mp->b_next = next; 1186 break; 1187 } 1188 mp = next; 1189 } 1190 return (mp); 1191 } 1192 1193 /* 1194 * rtls_receive() -- receive packets 1195 * 1196 * Called when receive interrupts detected 1197 */ 1198 static void 1199 rtls_receive(rtls_t *rtlsp) 1200 { 1201 mblk_t *head = NULL; 1202 mblk_t **mpp; 1203 mblk_t *mp; 1204 uint16_t rx_status; 1205 uint16_t packet_len; 1206 int wrap_size; 1207 uint32_t cur_rx; 1208 uint8_t *rx_ptr; 1209 1210 mpp = &head; 1211 1212 mutex_enter(&rtlsp->rtls_rx_lock); 1213 1214 if (rtlsp->rtls_suspended) { 1215 mutex_exit(&rtlsp->rtls_rx_lock); 1216 return; 1217 } 1218 1219 while ((rtls_reg_get8(rtlsp, RT_COMMAND_REG) 1220 & RT_COMMAND_BUFF_EMPTY) == 0) { 1221 1222 /* 1223 * Chip error state 1224 */ 1225 if (rtlsp->chip_error) { 1226 #ifdef RTLS_DEBUG 1227 cmn_err(CE_WARN, 1228 "%s: receive fail--CHIP ERROR!", 1229 rtlsp->ifname); 1230 #endif 1231 break; 1232 } 1233 1234 cur_rx = rtlsp->cur_rx; 1235 rx_ptr = rtlsp->rx_ring + cur_rx; 1236 packet_len = (rx_ptr[3] << 8) | (rx_ptr[2]); 1237 rx_status = rx_ptr[0]; 1238 1239 /* 1240 * DMA still in progress 1241 */ 1242 if (packet_len == RX_STATUS_DMA_BUSY) { 1243 cmn_err(CE_NOTE, "%s: Rx DMA still in progress", 1244 rtlsp->ifname); 1245 break; 1246 } 1247 1248 /* 1249 * Check receive status 1250 */ 1251 if ((rx_status & RX_ERR_FLAGS) || 1252 (!(rx_status & RX_HEADER_STATUS_ROK)) || 1253 (packet_len < (ETHERMIN + ETHERFCSL)) || 1254 (packet_len > (ETHERMAX + ETHERFCSL + 4))) { 1255 #ifdef RTLS_DEBUG 1256 cmn_err(CE_NOTE, 1257 "%s: receive error, status = 0x%x, length = %d", 1258 rtlsp->ifname, rx_status, packet_len); 1259 #endif 1260 /* 1261 * Rx error statistics 1262 */ 1263 if ((rx_status & RX_HEADER_STATUS_RUNT) || 1264 (packet_len < (ETHERMIN + ETHERFCSL))) 1265 rtlsp->stats.in_short++; 1266 else if (packet_len > (ETHERMAX + ETHERFCSL + 4)) 1267 rtlsp->stats.too_long++; 1268 else if (rx_status & RX_HEADER_STATUS_CRC) 1269 rtlsp->stats.crc_err++; 1270 else if (rx_status & RX_HEADER_STATUS_FAE) 1271 rtlsp->stats.frame_err++; 1272 1273 /* 1274 * Set chip_error flag to reset chip: 1275 * (suggested in RealTek programming guide.) 1276 */ 1277 rtlsp->chip_error = B_TRUE; 1278 mutex_exit(&rtlsp->rtls_rx_lock); 1279 return; 1280 } 1281 1282 /* 1283 * We need not up-send ETHERFCSL bytes of receive packet 1284 */ 1285 packet_len -= ETHERFCSL; 1286 1287 /* 1288 * Allocate buffer to receive this good packet 1289 */ 1290 mp = allocb(packet_len, 0); 1291 1292 /* 1293 * Copy the data found into the new cluster, we have (+4) 1294 * to get us past the packet head data that the rtl chip 1295 * places at the start of the message 1296 */ 1297 if ((cur_rx + packet_len + RX_HEADER_SIZE) 1298 > RTLS_RX_BUF_RING) { 1299 wrap_size = cur_rx + packet_len + RX_HEADER_SIZE 1300 - RTLS_RX_BUF_RING; 1301 #ifdef RTLS_DEBUG 1302 if (rtls_debug & RTLS_RECV) { 1303 cmn_err(CE_NOTE, 1304 "%s: Rx: packet_len = %d, wrap_size = %d", 1305 rtlsp->ifname, packet_len, wrap_size); 1306 } 1307 #endif 1308 1309 if (mp != NULL) { 1310 /* Flush caches */ 1311 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1312 cur_rx + RX_HEADER_SIZE, 1313 packet_len - wrap_size, 1314 DDI_DMA_SYNC_FORKERNEL); 1315 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1316 0, wrap_size, 1317 DDI_DMA_SYNC_FORKERNEL); 1318 1319 /* 1320 * Copy in first section of message as stored 1321 * at the end of the ring buffer 1322 */ 1323 bcopy(rx_ptr + RX_HEADER_SIZE, 1324 mp->b_wptr, packet_len - wrap_size); 1325 mp->b_wptr += packet_len - wrap_size; 1326 bcopy(rtlsp->rx_ring, mp->b_wptr, wrap_size); 1327 mp->b_wptr += wrap_size; 1328 *mpp = mp; 1329 mpp = &mp->b_next; 1330 1331 rtlsp->stats.ipackets++; 1332 if (rx_status & RX_HEADER_STATUS_BCAST) 1333 rtlsp->stats.brdcst_rcv++; 1334 if (rx_status & RX_HEADER_STATUS_MULTI) 1335 rtlsp->stats.multi_rcv++; 1336 rtlsp->stats.rbytes += packet_len; 1337 } else { 1338 rtlsp->stats.no_rcvbuf++; 1339 } 1340 1341 cur_rx = RTLS_RX_ADDR_ALIGNED(wrap_size + ETHERFCSL); 1342 /* 4-byte aligned */ 1343 } else { 1344 1345 if (mp != NULL) { 1346 /* Flush caches */ 1347 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1348 cur_rx + RX_HEADER_SIZE, packet_len, 1349 DDI_DMA_SYNC_FORKERNEL); 1350 bcopy(rx_ptr + RX_HEADER_SIZE, mp->b_wptr, 1351 packet_len); 1352 mp->b_wptr += packet_len; 1353 *mpp = mp; 1354 mpp = &mp->b_next; 1355 1356 rtlsp->stats.ipackets++; 1357 if (rx_status & RX_HEADER_STATUS_BCAST) 1358 rtlsp->stats.brdcst_rcv++; 1359 if (rx_status & RX_HEADER_STATUS_MULTI) 1360 rtlsp->stats.multi_rcv++; 1361 rtlsp->stats.rbytes += packet_len; 1362 } else { 1363 rtlsp->stats.no_rcvbuf++; 1364 } 1365 cur_rx += packet_len + RX_HEADER_SIZE + ETHERFCSL; 1366 1367 cur_rx = RTLS_RX_ADDR_ALIGNED(cur_rx); 1368 /* 4-byte aligned */ 1369 } 1370 1371 /* 1372 * Update rx buffer ring read pointer: 1373 * give us a little leeway to ensure no overflow 1374 */ 1375 rtlsp->cur_rx = cur_rx; 1376 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, 1377 cur_rx - READ_ADDR_GAP); 1378 } 1379 mutex_exit(&rtlsp->rtls_rx_lock); 1380 1381 /* 1382 * Upsend packet 1383 */ 1384 if (head) { 1385 mac_rx(rtlsp->mh, NULL, head); 1386 } 1387 } 1388 1389 /* 1390 * rtls_intr() -- interrupt from board to inform us that a receive or 1391 * link change. 1392 */ 1393 static uint_t 1394 rtls_intr(caddr_t arg) 1395 { 1396 rtls_t *rtlsp = (void *)arg; 1397 uint32_t int_status; 1398 uint32_t val32; 1399 boolean_t resched = B_FALSE; 1400 1401 mutex_enter(&rtlsp->rtls_io_lock); 1402 if (rtlsp->rtls_suspended) { 1403 mutex_exit(&rtlsp->rtls_io_lock); 1404 return (DDI_INTR_UNCLAIMED); 1405 } 1406 1407 /* 1408 * Was this interrupt caused by our device... 1409 */ 1410 int_status = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1411 if (!(int_status & rtlsp->int_mask)) { 1412 mutex_exit(&rtlsp->rtls_io_lock); 1413 return (DDI_INTR_UNCLAIMED); 1414 /* indicate it wasn't our interrupt */ 1415 } 1416 1417 /* 1418 * Clear interrupt 1419 */ 1420 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, int_status); 1421 1422 /* 1423 * If chip error, restart chip... 1424 */ 1425 if (rtlsp->chip_error) { 1426 mutex_enter(&rtlsp->rtls_rx_lock); 1427 mutex_enter(&rtlsp->rtls_tx_lock); 1428 rtls_chip_restart(rtlsp); 1429 rtlsp->chip_error = B_FALSE; 1430 rtlsp->tx_retry = 0; 1431 mutex_exit(&rtlsp->rtls_tx_lock); 1432 mutex_exit(&rtlsp->rtls_rx_lock); 1433 mutex_exit(&rtlsp->rtls_io_lock); 1434 return (DDI_INTR_CLAIMED); 1435 /* no need to hand other interrupts */ 1436 } 1437 1438 /* 1439 * Transmit error interrupt 1440 */ 1441 if (int_status & TX_ERR_INT) { 1442 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1443 val32 |= TX_CLEAR_ABORT; 1444 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32); 1445 cmn_err(CE_WARN, "%s: transmit abort!!!", rtlsp->ifname); 1446 } 1447 1448 /* 1449 * Trigger mac_tx_update 1450 */ 1451 if (rtlsp->need_sched) { 1452 rtlsp->need_sched = B_FALSE; 1453 resched = B_TRUE; 1454 } 1455 1456 mutex_exit(&rtlsp->rtls_io_lock); 1457 1458 /* 1459 * Receive interrupt 1460 */ 1461 if (int_status & RTLS_RX_INT) { 1462 if (int_status & RX_OVERFLOW_INT) { 1463 rtlsp->stats.overflow++; 1464 rtlsp->stats.rcv_err++; 1465 } 1466 rtls_receive(rtlsp); 1467 } 1468 1469 /* 1470 * Link change interrupt. 1471 */ 1472 if (int_status & LINK_CHANGE_INT) { 1473 mii_check(rtlsp->mii); 1474 } 1475 1476 if (resched) { 1477 mac_tx_update(rtlsp->mh); 1478 } 1479 1480 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1481 } 1482 1483 /* 1484 * ========== Buffer Management Routines ========== 1485 */ 1486 1487 /* 1488 * rtls_alloc_dma_mem() -- allocate an area of memory and a DMA handle 1489 * for accessing it 1490 */ 1491 static int 1492 rtls_alloc_dma_mem(rtls_t *rtlsp, size_t memsize, 1493 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p) 1494 { 1495 caddr_t vaddr; 1496 int err; 1497 1498 /* 1499 * Allocate handle 1500 */ 1501 err = ddi_dma_alloc_handle(rtlsp->devinfo, &dma_attr, 1502 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 1503 if (err != DDI_SUCCESS) { 1504 cmn_err(CE_WARN, 1505 "%s: rtls_alloc_dma_mem: ddi_dma_alloc_handle failed: %d", 1506 rtlsp->ifname, err); 1507 dma_p->dma_hdl = NULL; 1508 return (DDI_FAILURE); 1509 } 1510 1511 /* 1512 * Allocate memory 1513 */ 1514 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 1515 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 1516 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl); 1517 if (err != DDI_SUCCESS) { 1518 cmn_err(CE_WARN, 1519 "%s: rtls_alloc_dma_mem: ddi_dma_mem_alloc failed: %d", 1520 rtlsp->ifname, err); 1521 ddi_dma_free_handle(&dma_p->dma_hdl); 1522 dma_p->dma_hdl = NULL; 1523 dma_p->acc_hdl = NULL; 1524 return (DDI_FAILURE); 1525 } 1526 1527 /* 1528 * Bind the two together 1529 */ 1530 dma_p->mem_va = vaddr; 1531 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 1532 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL, 1533 &dma_p->cookie, &dma_p->ncookies); 1534 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) { 1535 cmn_err(CE_WARN, 1536 "%s: rtls_alloc_dma_mem: " 1537 "ddi_dma_addr_bind_handle failed: %d", 1538 rtlsp->ifname, err); 1539 ddi_dma_mem_free(&dma_p->acc_hdl); 1540 ddi_dma_free_handle(&dma_p->dma_hdl); 1541 dma_p->acc_hdl = NULL; 1542 dma_p->dma_hdl = NULL; 1543 return (DDI_FAILURE); 1544 } 1545 1546 return (DDI_SUCCESS); 1547 } 1548 1549 /* 1550 * rtls_free_dma_mem() -- free one allocated area of DMAable memory 1551 */ 1552 static void 1553 rtls_free_dma_mem(dma_area_t *dma_p) 1554 { 1555 if (dma_p->dma_hdl != NULL) { 1556 if (dma_p->ncookies) { 1557 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 1558 dma_p->ncookies = 0; 1559 } 1560 ddi_dma_free_handle(&dma_p->dma_hdl); 1561 dma_p->dma_hdl = NULL; 1562 } 1563 1564 if (dma_p->acc_hdl != NULL) { 1565 ddi_dma_mem_free(&dma_p->acc_hdl); 1566 dma_p->acc_hdl = NULL; 1567 } 1568 } 1569 1570 /* 1571 * rtls_alloc_bufs() -- allocate descriptors/buffers for this device instance 1572 */ 1573 static int 1574 rtls_alloc_bufs(rtls_t *rtlsp) 1575 { 1576 int i; 1577 int err; 1578 1579 /* 1580 * Allocate memory & handle for Tx buffers 1581 */ 1582 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1583 err = rtls_alloc_dma_mem(rtlsp, 1584 RTLS_TX_BUF_SIZE, 1585 &rtls_buf_accattr, 1586 DDI_DMA_WRITE | DDI_DMA_STREAMING, 1587 &rtlsp->dma_area_tx[i]); 1588 1589 if (err != DDI_SUCCESS) 1590 return (DDI_FAILURE); 1591 1592 rtlsp->tx_buf[i] = (uint8_t *)rtlsp->dma_area_tx[i].mem_va; 1593 } 1594 1595 /* 1596 * Allocate memory & handle for Rx buffers 1597 */ 1598 err = rtls_alloc_dma_mem(rtlsp, 1599 RTLS_RX_BUF_SIZE, 1600 &rtls_buf_accattr, 1601 DDI_DMA_READ | DDI_DMA_STREAMING, 1602 &rtlsp->dma_area_rx); 1603 1604 if (err != DDI_SUCCESS) 1605 return (DDI_FAILURE); 1606 1607 rtlsp->rx_ring = (uint8_t *)rtlsp->dma_area_rx.mem_va; 1608 1609 return (DDI_SUCCESS); 1610 } 1611 1612 /* 1613 * rtls_free_bufs() -- free descriptors/buffers allocated for this 1614 * device instance. 1615 */ 1616 static void 1617 rtls_free_bufs(rtls_t *rtlsp) 1618 { 1619 int i; 1620 1621 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1622 rtls_free_dma_mem(&rtlsp->dma_area_tx[i]); 1623 rtlsp->tx_buf[i] = NULL; 1624 } 1625 1626 rtls_free_dma_mem(&rtlsp->dma_area_rx); 1627 rtlsp->rx_ring = NULL; 1628 } 1629 1630 /* 1631 * ========== Chip H/W Operation Routines ========== 1632 */ 1633 1634 /* 1635 * rtls_chip_reset() -- reset chip 1636 */ 1637 static int 1638 rtls_chip_reset(rtls_t *rtlsp, boolean_t quiesce) 1639 { 1640 int i; 1641 uint16_t val16; 1642 uint8_t val8; 1643 1644 /* 1645 * Chip should be in STOP state 1646 */ 1647 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1648 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1649 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1650 1651 /* 1652 * Disable interrupt 1653 */ 1654 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1655 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1656 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1657 1658 /* 1659 * Clear pended interrupt 1660 */ 1661 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1662 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1663 1664 /* 1665 * Reset chip 1666 */ 1667 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1668 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8 | RT_COMMAND_RESET); 1669 1670 /* 1671 * Wait for reset success 1672 */ 1673 i = 0; 1674 while (rtls_reg_get8(rtlsp, RT_COMMAND_REG) & RT_COMMAND_RESET) { 1675 if (++i > RTLS_RESET_WAIT_NUM) { 1676 /* 1677 * At quiesce path we can't call cmn_err(), as 1678 * it might block 1679 */ 1680 if (!quiesce) 1681 cmn_err(CE_WARN, 1682 "%s: chip reset fail.", rtlsp->ifname); 1683 return (DDI_FAILURE); 1684 } 1685 RTLS_RESET_WAIT_INTERVAL; 1686 } 1687 1688 return (DDI_SUCCESS); 1689 } 1690 1691 /* 1692 * rtls_chip_init() -- initialize the specified network board short of 1693 * actually starting the board. Call after rtls_chip_reset(). 1694 */ 1695 static void 1696 rtls_chip_init(rtls_t *rtlsp) 1697 { 1698 uint32_t val32; 1699 uint16_t val16; 1700 uint8_t val8; 1701 1702 /* 1703 * Initialize internal data structures 1704 */ 1705 rtlsp->cur_rx = 0; 1706 rtlsp->tx_current_desc = 0; 1707 rtlsp->tx_first_loop = 0; 1708 1709 /* 1710 * Set DMA physical rx/tx buffer address to register 1711 */ 1712 rtls_reg_set32(rtlsp, RX_BUFF_ADDR_REG, 1713 (ulong_t)rtlsp->dma_area_rx.cookie.dmac_address); 1714 rtls_reg_set32(rtlsp, TX_ADDR_DESC0_REG, 1715 (ulong_t)rtlsp->dma_area_tx[0].cookie.dmac_address); 1716 rtls_reg_set32(rtlsp, TX_ADDR_DESC1_REG, 1717 (ulong_t)rtlsp->dma_area_tx[1].cookie.dmac_address); 1718 rtls_reg_set32(rtlsp, TX_ADDR_DESC2_REG, 1719 (ulong_t)rtlsp->dma_area_tx[2].cookie.dmac_address); 1720 rtls_reg_set32(rtlsp, TX_ADDR_DESC3_REG, 1721 (ulong_t)rtlsp->dma_area_tx[3].cookie.dmac_address); 1722 1723 /* 1724 * Start transmit/receive before set tx/rx configuration register 1725 */ 1726 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1727 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1728 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1729 1730 /* 1731 * Set transmit configuration register 1732 */ 1733 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1734 val32 &= TX_CONSIG_REG_RESERVE; 1735 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32 | TX_CONFIG_DEFAULT); 1736 1737 /* 1738 * Set receive configuration register 1739 */ 1740 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 1741 val32 &= RX_CONSIG_REG_RESERVE; 1742 if (rtlsp->promisc) 1743 val32 |= RX_ACCEPT_ALL_PACKET; 1744 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32 | RX_CONFIG_DEFAULT); 1745 1746 /* 1747 * Set multicast register 1748 */ 1749 rtls_reg_set32(rtlsp, MULTICAST_0_REG, rtlsp->multi_hash[0]); 1750 rtls_reg_set32(rtlsp, MULTICAST_4_REG, rtlsp->multi_hash[1]); 1751 1752 /* 1753 * Set unicast address 1754 */ 1755 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 1756 1757 /* 1758 * Set current address of packet read 1759 */ 1760 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, RX_READ_RESET_VAL); 1761 1762 /* 1763 * No early-rx interrupts 1764 */ 1765 val16 = rtls_reg_get16(rtlsp, RT_MUL_INTSEL_REG); 1766 val16 &= ~RT_MUL_INTSEL_BITS; 1767 rtls_reg_set16(rtlsp, RT_MUL_INTSEL_REG, val16); 1768 } 1769 1770 /* 1771 * rtls_chip_start() -- start chip 1772 */ 1773 static void 1774 rtls_chip_start(rtls_t *rtlsp) 1775 { 1776 uint16_t val16; 1777 uint8_t val8; 1778 1779 /* 1780 * Start transmit/receive 1781 */ 1782 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1783 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1784 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1785 1786 /* 1787 * Enable interrupt 1788 */ 1789 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1790 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 | RTLS_INT_MASK); 1791 rtlsp->int_mask = RTLS_INT_MASK; 1792 } 1793 1794 /* 1795 * rtls_chip_restart() -- restart chip 1796 */ 1797 static void 1798 rtls_chip_restart(rtls_t *rtlsp) 1799 { 1800 (void) rtls_chip_reset(rtlsp, B_FALSE); 1801 rtls_chip_init(rtlsp); 1802 rtls_chip_start(rtlsp); 1803 } 1804 1805 /* 1806 * rtls_chip_stop() -- stop board receiving 1807 */ 1808 static void 1809 rtls_chip_stop(rtls_t *rtlsp) 1810 { 1811 uint16_t val16; 1812 uint8_t val8; 1813 1814 /* 1815 * Disable interrupt 1816 */ 1817 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1818 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1819 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1820 1821 /* 1822 * Clear pended interrupt 1823 */ 1824 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1825 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1826 1827 /* 1828 * Stop the board and disable transmit/receive 1829 */ 1830 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1831 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1832 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1833 } 1834 1835 /* 1836 * rtls_get_mac_addr() -- get the physical network address on the board 1837 */ 1838 static void 1839 rtls_get_mac_addr(rtls_t *rtlsp, uint8_t *macaddr) 1840 { 1841 uint32_t val32; 1842 1843 /* 1844 * Read first 4-byte of mac address 1845 */ 1846 val32 = rtls_reg_get32(rtlsp, ID_0_REG); 1847 macaddr[0] = val32 & 0xff; 1848 val32 = val32 >> 8; 1849 macaddr[1] = val32 & 0xff; 1850 val32 = val32 >> 8; 1851 macaddr[2] = val32 & 0xff; 1852 val32 = val32 >> 8; 1853 macaddr[3] = val32 & 0xff; 1854 1855 /* 1856 * Read last 2-byte of mac address 1857 */ 1858 val32 = rtls_reg_get32(rtlsp, ID_4_REG); 1859 macaddr[4] = val32 & 0xff; 1860 val32 = val32 >> 8; 1861 macaddr[5] = val32 & 0xff; 1862 } 1863 1864 static void 1865 rtls_set_mac_addr(rtls_t *rtlsp, const uint8_t *macaddr) 1866 { 1867 uint32_t val32; 1868 uint8_t val8; 1869 1870 /* 1871 * Change to config register write enable mode 1872 */ 1873 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG); 1874 val8 |= RT_93c46_MODE_CONFIG; 1875 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1876 1877 /* 1878 * Get first 4 bytes of mac address 1879 */ 1880 val32 = macaddr[3]; 1881 val32 = val32 << 8; 1882 val32 |= macaddr[2]; 1883 val32 = val32 << 8; 1884 val32 |= macaddr[1]; 1885 val32 = val32 << 8; 1886 val32 |= macaddr[0]; 1887 1888 /* 1889 * Set first 4 bytes of mac address 1890 */ 1891 rtls_reg_set32(rtlsp, ID_0_REG, val32); 1892 1893 /* 1894 * Get last 2 bytes of mac address 1895 */ 1896 val32 = macaddr[5]; 1897 val32 = val32 << 8; 1898 val32 |= macaddr[4]; 1899 1900 /* 1901 * Set last 2 bytes of mac address 1902 */ 1903 val32 |= rtls_reg_get32(rtlsp, ID_4_REG) & ~0xffff; 1904 rtls_reg_set32(rtlsp, ID_4_REG, val32); 1905 1906 /* 1907 * Return to normal network/host communication mode 1908 */ 1909 val8 &= ~RT_93c46_MODE_CONFIG; 1910 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1911 } 1912 1913 static uint16_t 1914 rtls_mii_read(void *arg, uint8_t phy, uint8_t reg) 1915 { 1916 rtls_t *rtlsp = arg; 1917 uint16_t val; 1918 1919 if (phy != 1) { 1920 return (0xffff); 1921 } 1922 switch (reg) { 1923 case MII_CONTROL: 1924 val = rtls_reg_get16(rtlsp, BASIC_MODE_CONTROL_REG); 1925 break; 1926 case MII_STATUS: 1927 val = rtls_reg_get16(rtlsp, BASIC_MODE_STATUS_REG); 1928 break; 1929 case MII_AN_ADVERT: 1930 val = rtls_reg_get16(rtlsp, AUTO_NEGO_AD_REG); 1931 break; 1932 case MII_AN_LPABLE: 1933 val = rtls_reg_get16(rtlsp, AUTO_NEGO_LP_REG); 1934 break; 1935 case MII_AN_EXPANSION: 1936 val = rtls_reg_get16(rtlsp, AUTO_NEGO_EXP_REG); 1937 break; 1938 case MII_VENDOR(0): 1939 /* 1940 * We "simulate" a vendor private register so that the 1941 * PHY layer can access it to determine detected link 1942 * speed/duplex. 1943 */ 1944 val = rtls_reg_get8(rtlsp, MEDIA_STATUS_REG); 1945 break; 1946 case MII_PHYIDH: 1947 case MII_PHYIDL: 1948 default: 1949 val = 0; 1950 break; 1951 } 1952 return (val); 1953 } 1954 1955 void 1956 rtls_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) 1957 { 1958 rtls_t *rtlsp = arg; 1959 uint8_t val8; 1960 1961 if (phy != 1) { 1962 return; 1963 } 1964 switch (reg) { 1965 case MII_CONTROL: 1966 /* Enable writes to all bits of BMCR */ 1967 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG); 1968 val8 |= RT_93c46_MODE_CONFIG; 1969 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1970 /* write out the value */ 1971 rtls_reg_set16(rtlsp, BASIC_MODE_CONTROL_REG, val); 1972 1973 /* Return to normal network/host communication mode */ 1974 val8 &= ~RT_93c46_MODE_CONFIG; 1975 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1976 return; 1977 1978 case MII_STATUS: 1979 rtls_reg_set16(rtlsp, BASIC_MODE_STATUS_REG, val); 1980 break; 1981 case MII_AN_ADVERT: 1982 rtls_reg_set16(rtlsp, AUTO_NEGO_AD_REG, val); 1983 break; 1984 case MII_AN_LPABLE: 1985 rtls_reg_set16(rtlsp, AUTO_NEGO_LP_REG, val); 1986 break; 1987 case MII_AN_EXPANSION: 1988 rtls_reg_set16(rtlsp, AUTO_NEGO_EXP_REG, val); 1989 break; 1990 case MII_PHYIDH: 1991 case MII_PHYIDL: 1992 default: 1993 /* these are not writable */ 1994 break; 1995 } 1996 } 1997 1998 void 1999 rtls_mii_notify(void *arg, link_state_t link) 2000 { 2001 rtls_t *rtlsp = arg; 2002 2003 mac_link_update(rtlsp->mh, link); 2004 } 2005 2006 #ifdef RTLS_DEBUG 2007 /* 2008 * rtls_reg_print() -- print out reg value(for debug use only) 2009 */ 2010 static void 2011 rtls_reg_print(rtls_t *rtlsp) 2012 { 2013 uint8_t val8; 2014 uint16_t val16; 2015 uint32_t val32; 2016 2017 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 2018 cmn_err(CE_NOTE, "%s: RT_COMMAND_REG = 0x%x", 2019 rtlsp->ifname, val8); 2020 delay(drv_usectohz(1000)); 2021 2022 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 2023 cmn_err(CE_NOTE, "%s: RT_INT_STATUS_REG = 0x%x", 2024 rtlsp->ifname, val16); 2025 delay(drv_usectohz(1000)); 2026 2027 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 2028 cmn_err(CE_NOTE, "%s: RT_INT_MASK_REG = 0x%x", 2029 rtlsp->ifname, val16); 2030 delay(drv_usectohz(1000)); 2031 2032 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 2033 cmn_err(CE_NOTE, "%s: RX_CONFIG_REG = 0x%x", 2034 rtlsp->ifname, val32); 2035 delay(drv_usectohz(1000)); 2036 2037 val16 = rtls_reg_get16(rtlsp, TX_DESC_STAUS_REG); 2038 cmn_err(CE_NOTE, "%s: TX_DESC_STAUS_REG = 0x%x, cur_desc = %d", 2039 rtlsp->ifname, val16, rtlsp->tx_current_desc); 2040 delay(drv_usectohz(1000)); 2041 2042 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG); 2043 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC0_REG = 0x%x", 2044 rtlsp->ifname, val32); 2045 delay(drv_usectohz(1000)); 2046 2047 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC1_REG); 2048 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC1_REG = 0x%x", 2049 rtlsp->ifname, val32); 2050 delay(drv_usectohz(1000)); 2051 2052 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC2_REG); 2053 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC2_REG = 0x%x", 2054 rtlsp->ifname, val32); 2055 delay(drv_usectohz(1000)); 2056 2057 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC3_REG); 2058 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC3_REG = 0x%x", 2059 rtlsp->ifname, val32); 2060 delay(drv_usectohz(1000)); 2061 2062 cmn_err(CE_NOTE, "%s: in = %llu, multicast = %llu, broadcast = %llu", 2063 rtlsp->ifname, 2064 (unsigned long long)rtlsp->stats.ipackets, 2065 (unsigned long long)rtlsp->stats.multi_rcv, 2066 (unsigned long long)rtlsp->stats.brdcst_rcv); 2067 delay(drv_usectohz(1000)); 2068 } 2069 #endif 2070