1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include "rge.h" 27 28 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 29 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 30 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 31 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 32 33 /* 34 * Patchable globals: 35 * 36 * rge_autorecover 37 * Enables/disables automatic recovery after fault detection 38 */ 39 static uint32_t rge_autorecover = 1; 40 41 /* 42 * globals: 43 */ 44 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 45 static uint32_t rge_watchdog_count = 1 << 16; 46 47 /* 48 * Operating register get/set access routines 49 */ 50 51 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 52 #pragma inline(rge_reg_get32) 53 54 static uint32_t 55 rge_reg_get32(rge_t *rgep, uintptr_t regno) 56 { 57 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 58 (void *)rgep, regno)); 59 60 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 61 } 62 63 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 64 #pragma inline(rge_reg_put32) 65 66 static void 67 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 68 { 69 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 70 (void *)rgep, regno, data)); 71 72 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 73 } 74 75 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 76 #pragma inline(rge_reg_set32) 77 78 static void 79 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 80 { 81 uint32_t regval; 82 83 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 84 (void *)rgep, regno, bits)); 85 86 regval = rge_reg_get32(rgep, regno); 87 regval |= bits; 88 rge_reg_put32(rgep, regno, regval); 89 } 90 91 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 92 #pragma inline(rge_reg_clr32) 93 94 static void 95 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 96 { 97 uint32_t regval; 98 99 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 100 (void *)rgep, regno, bits)); 101 102 regval = rge_reg_get32(rgep, regno); 103 regval &= ~bits; 104 rge_reg_put32(rgep, regno, regval); 105 } 106 107 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 108 #pragma inline(rge_reg_get16) 109 110 static uint16_t 111 rge_reg_get16(rge_t *rgep, uintptr_t regno) 112 { 113 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 114 (void *)rgep, regno)); 115 116 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 117 } 118 119 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 120 #pragma inline(rge_reg_put16) 121 122 static void 123 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 124 { 125 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 126 (void *)rgep, regno, data)); 127 128 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 129 } 130 131 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 132 #pragma inline(rge_reg_get8) 133 134 static uint8_t 135 rge_reg_get8(rge_t *rgep, uintptr_t regno) 136 { 137 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 138 (void *)rgep, regno)); 139 140 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 141 } 142 143 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 144 #pragma inline(rge_reg_put8) 145 146 static void 147 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 148 { 149 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 150 (void *)rgep, regno, data)); 151 152 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 153 } 154 155 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 156 #pragma inline(rge_reg_set8) 157 158 static void 159 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 160 { 161 uint8_t regval; 162 163 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 164 (void *)rgep, regno, bits)); 165 166 regval = rge_reg_get8(rgep, regno); 167 regval |= bits; 168 rge_reg_put8(rgep, regno, regval); 169 } 170 171 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 172 #pragma inline(rge_reg_clr8) 173 174 static void 175 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 176 { 177 uint8_t regval; 178 179 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 180 (void *)rgep, regno, bits)); 181 182 regval = rge_reg_get8(rgep, regno); 183 regval &= ~bits; 184 rge_reg_put8(rgep, regno, regval); 185 } 186 187 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 188 #pragma no_inline(rge_mii_get16) 189 190 uint16_t 191 rge_mii_get16(rge_t *rgep, uintptr_t mii) 192 { 193 uint32_t regval; 194 uint32_t val32; 195 uint32_t i; 196 197 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 198 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 199 200 /* 201 * Waiting for PHY reading OK 202 */ 203 for (i = 0; i < PHY_RESET_LOOP; i++) { 204 drv_usecwait(1000); 205 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 206 if (val32 & PHY_ACCESS_WR_FLAG) 207 return ((uint16_t)(val32 & 0xffff)); 208 } 209 210 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 211 return ((uint16_t)~0u); 212 } 213 214 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 215 #pragma no_inline(rge_mii_put16) 216 217 void 218 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 219 { 220 uint32_t regval; 221 uint32_t val32; 222 uint32_t i; 223 224 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 225 regval |= data & PHY_DATA_MASK; 226 regval |= PHY_ACCESS_WR_FLAG; 227 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 228 229 /* 230 * Waiting for PHY writing OK 231 */ 232 for (i = 0; i < PHY_RESET_LOOP; i++) { 233 drv_usecwait(1000); 234 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 235 if (!(val32 & PHY_ACCESS_WR_FLAG)) 236 return; 237 } 238 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 239 mii, data)); 240 } 241 242 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 243 #pragma no_inline(rge_ephy_put16) 244 245 void 246 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 247 { 248 uint32_t regval; 249 uint32_t val32; 250 uint32_t i; 251 252 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 253 regval |= data & EPHY_DATA_MASK; 254 regval |= EPHY_ACCESS_WR_FLAG; 255 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 256 257 /* 258 * Waiting for PHY writing OK 259 */ 260 for (i = 0; i < PHY_RESET_LOOP; i++) { 261 drv_usecwait(1000); 262 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 263 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 264 return; 265 } 266 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 267 emii, data)); 268 } 269 270 /* 271 * Atomically shift a 32-bit word left, returning 272 * the value it had *before* the shift was applied 273 */ 274 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 275 #pragma inline(rge_mii_put16) 276 277 static uint32_t 278 rge_atomic_shl32(uint32_t *sp, uint_t count) 279 { 280 uint32_t oldval; 281 uint32_t newval; 282 283 /* ATOMICALLY */ 284 do { 285 oldval = *sp; 286 newval = oldval << count; 287 } while (cas32(sp, oldval, newval) != oldval); 288 289 return (oldval); 290 } 291 292 /* 293 * PHY operation routines 294 */ 295 #if RGE_DEBUGGING 296 297 void 298 rge_phydump(rge_t *rgep) 299 { 300 uint16_t regs[32]; 301 int i; 302 303 ASSERT(mutex_owned(rgep->genlock)); 304 305 for (i = 0; i < 32; ++i) { 306 regs[i] = rge_mii_get16(rgep, i); 307 } 308 309 for (i = 0; i < 32; i += 8) 310 RGE_DEBUG(("rge_phydump: " 311 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 312 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 313 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 314 } 315 316 #endif /* RGE_DEBUGGING */ 317 318 static void 319 rge_phy_check(rge_t *rgep) 320 { 321 uint16_t gig_ctl; 322 323 if (rgep->param_link_up == LINK_STATE_DOWN) { 324 /* 325 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 326 * every 15 seconds whin link down & advertise is 1000. 327 */ 328 if (rgep->chipid.phy_ver == PHY_VER_S) { 329 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 330 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 331 rgep->link_down_count++; 332 if (rgep->link_down_count > 15) { 333 (void) rge_phy_reset(rgep); 334 rgep->stats.phy_reset++; 335 rgep->link_down_count = 0; 336 } 337 } 338 } 339 } else { 340 rgep->link_down_count = 0; 341 } 342 } 343 344 /* 345 * Basic low-level function to reset the PHY. 346 * Doesn't incorporate any special-case workarounds. 347 * 348 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 349 */ 350 boolean_t 351 rge_phy_reset(rge_t *rgep) 352 { 353 uint16_t control; 354 uint_t count; 355 356 /* 357 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 358 */ 359 control = rge_mii_get16(rgep, MII_CONTROL); 360 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 361 for (count = 0; count < 5; count++) { 362 drv_usecwait(100); 363 control = rge_mii_get16(rgep, MII_CONTROL); 364 if (BIC(control, MII_CONTROL_RESET)) 365 return (B_TRUE); 366 } 367 368 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 369 return (B_FALSE); 370 } 371 372 /* 373 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 374 * and advertisements with the required settings as specified by the various 375 * param_* variables that can be poked via the NDD interface. 376 * 377 * We always reset the PHY and reprogram *all* the relevant registers, 378 * not just those changed. This should cause the link to go down, and then 379 * back up again once the link is stable and autonegotiation (if enabled) 380 * is complete. We should get a link state change interrupt somewhere along 381 * the way ... 382 * 383 * NOTE: <genlock> must already be held by the caller 384 */ 385 void 386 rge_phy_update(rge_t *rgep) 387 { 388 boolean_t adv_autoneg; 389 boolean_t adv_pause; 390 boolean_t adv_asym_pause; 391 boolean_t adv_1000fdx; 392 boolean_t adv_1000hdx; 393 boolean_t adv_100fdx; 394 boolean_t adv_100hdx; 395 boolean_t adv_10fdx; 396 boolean_t adv_10hdx; 397 398 uint16_t control; 399 uint16_t gigctrl; 400 uint16_t anar; 401 402 ASSERT(mutex_owned(rgep->genlock)); 403 404 RGE_DEBUG(("rge_phy_update: autoneg %d " 405 "pause %d asym_pause %d " 406 "1000fdx %d 1000hdx %d " 407 "100fdx %d 100hdx %d " 408 "10fdx %d 10hdx %d ", 409 rgep->param_adv_autoneg, 410 rgep->param_adv_pause, rgep->param_adv_asym_pause, 411 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 412 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 413 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 414 415 control = gigctrl = anar = 0; 416 417 /* 418 * PHY settings are normally based on the param_* variables, 419 * but if any loopback mode is in effect, that takes precedence. 420 * 421 * RGE supports MAC-internal loopback, PHY-internal loopback, 422 * and External loopback at a variety of speeds (with a special 423 * cable). In all cases, autoneg is turned OFF, full-duplex 424 * is turned ON, and the speed/mastership is forced. 425 */ 426 switch (rgep->param_loop_mode) { 427 case RGE_LOOP_NONE: 428 default: 429 adv_autoneg = rgep->param_adv_autoneg; 430 adv_pause = rgep->param_adv_pause; 431 adv_asym_pause = rgep->param_adv_asym_pause; 432 adv_1000fdx = rgep->param_adv_1000fdx; 433 adv_1000hdx = rgep->param_adv_1000hdx; 434 adv_100fdx = rgep->param_adv_100fdx; 435 adv_100hdx = rgep->param_adv_100hdx; 436 adv_10fdx = rgep->param_adv_10fdx; 437 adv_10hdx = rgep->param_adv_10hdx; 438 break; 439 440 case RGE_LOOP_INTERNAL_PHY: 441 case RGE_LOOP_INTERNAL_MAC: 442 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 443 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 444 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 445 rgep->param_link_duplex = LINK_DUPLEX_FULL; 446 447 switch (rgep->param_loop_mode) { 448 case RGE_LOOP_INTERNAL_PHY: 449 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 450 rgep->param_link_speed = 1000; 451 adv_1000fdx = B_TRUE; 452 } else { 453 rgep->param_link_speed = 100; 454 adv_100fdx = B_TRUE; 455 } 456 control = MII_CONTROL_LOOPBACK; 457 break; 458 459 case RGE_LOOP_INTERNAL_MAC: 460 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 461 rgep->param_link_speed = 1000; 462 adv_1000fdx = B_TRUE; 463 } else { 464 rgep->param_link_speed = 100; 465 adv_100fdx = B_TRUE; 466 break; 467 } 468 } 469 470 RGE_DEBUG(("rge_phy_update: autoneg %d " 471 "pause %d asym_pause %d " 472 "1000fdx %d 1000hdx %d " 473 "100fdx %d 100hdx %d " 474 "10fdx %d 10hdx %d ", 475 adv_autoneg, 476 adv_pause, adv_asym_pause, 477 adv_1000fdx, adv_1000hdx, 478 adv_100fdx, adv_100hdx, 479 adv_10fdx, adv_10hdx)); 480 481 /* 482 * We should have at least one technology capability set; 483 * if not, we select a default of 1000Mb/s full-duplex 484 */ 485 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 486 !adv_1000hdx && !adv_100hdx && !adv_10hdx) { 487 if (rgep->chipid.mac_ver != MAC_VER_8101E) 488 adv_1000fdx = B_TRUE; 489 } else { 490 adv_1000fdx = B_FALSE; 491 adv_100fdx = B_TRUE; 492 } 493 } 494 495 /* 496 * Now transform the adv_* variables into the proper settings 497 * of the PHY registers ... 498 * 499 * If autonegotiation is (now) enabled, we want to trigger 500 * a new autonegotiation cycle once the PHY has been 501 * programmed with the capabilities to be advertised. 502 * 503 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 504 */ 505 if (adv_autoneg) 506 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 507 508 if (adv_1000fdx) 509 control |= MII_CONTROL_1GB|MII_CONTROL_FDUPLEX; 510 else if (adv_1000hdx) 511 control |= MII_CONTROL_1GB; 512 else if (adv_100fdx) 513 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 514 else if (adv_100hdx) 515 control |= MII_CONTROL_100MB; 516 else if (adv_10fdx) 517 control |= MII_CONTROL_FDUPLEX; 518 else if (adv_10hdx) 519 control |= 0; 520 else 521 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 522 523 if (adv_1000fdx) { 524 gigctrl |= MII_1000BT_CTL_ADV_FDX; 525 /* 526 * Chipset limitation: need set other capabilities to true 527 */ 528 if (rgep->chipid.is_pcie) 529 adv_1000hdx = B_TRUE; 530 adv_100fdx = B_TRUE; 531 adv_100hdx = B_TRUE; 532 adv_10fdx = B_TRUE; 533 adv_10hdx = B_TRUE; 534 } 535 536 if (adv_1000hdx) 537 gigctrl |= MII_1000BT_CTL_ADV_HDX; 538 539 if (adv_100fdx) 540 anar |= MII_ABILITY_100BASE_TX_FD; 541 if (adv_100hdx) 542 anar |= MII_ABILITY_100BASE_TX; 543 if (adv_10fdx) 544 anar |= MII_ABILITY_10BASE_T_FD; 545 if (adv_10hdx) 546 anar |= MII_ABILITY_10BASE_T; 547 548 if (adv_pause) 549 anar |= MII_ABILITY_PAUSE; 550 if (adv_asym_pause) 551 anar |= MII_ABILITY_ASMPAUSE; 552 553 /* 554 * Munge in any other fixed bits we require ... 555 */ 556 anar |= MII_AN_SELECTOR_8023; 557 558 /* 559 * Restart the PHY and write the new values. Note the 560 * time, so that we can say whether subsequent link state 561 * changes can be attributed to our reprogramming the PHY 562 */ 563 rge_phy_init(rgep); 564 if (rgep->chipid.mac_ver == MAC_VER_8168B_B || 565 rgep->chipid.mac_ver == MAC_VER_8168B_C) { 566 /* power up PHY for RTL8168B chipset */ 567 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 568 rge_mii_put16(rgep, PHY_0E_REG, 0x0000); 569 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 570 } 571 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 572 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 573 rge_mii_put16(rgep, MII_CONTROL, control); 574 575 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 576 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 577 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 578 } 579 580 void rge_phy_init(rge_t *rgep); 581 #pragma no_inline(rge_phy_init) 582 583 void 584 rge_phy_init(rge_t *rgep) 585 { 586 rgep->phy_mii_addr = 1; 587 588 /* 589 * Below phy config steps are copied from the Programming Guide 590 * (there's no detail comments for these steps.) 591 */ 592 switch (rgep->chipid.mac_ver) { 593 case MAC_VER_8169S_D: 594 case MAC_VER_8169S_E : 595 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 596 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 597 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 598 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 599 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 600 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 601 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 602 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 603 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 604 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 605 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 606 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 607 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 608 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 609 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 610 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 611 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 612 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 613 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 614 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 615 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 616 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 617 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 618 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 619 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 620 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 621 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 622 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 623 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 624 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 625 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 626 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 627 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 628 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 629 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 630 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 631 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 632 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 633 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 634 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 635 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 636 break; 637 638 case MAC_VER_8169SB: 639 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 640 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 641 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 642 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 643 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 644 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 645 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 646 break; 647 648 case MAC_VER_8169SC: 649 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 650 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 651 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 652 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 653 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 654 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 655 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 656 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 657 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 658 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 659 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 660 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 661 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 662 break; 663 664 case MAC_VER_8168: 665 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 666 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 667 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 668 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 669 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 670 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 671 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 672 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 673 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 674 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 675 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 676 break; 677 678 case MAC_VER_8168B_B: 679 case MAC_VER_8168B_C: 680 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 681 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 682 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 683 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 684 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 685 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 686 break; 687 } 688 } 689 690 void rge_chip_ident(rge_t *rgep); 691 #pragma no_inline(rge_chip_ident) 692 693 void 694 rge_chip_ident(rge_t *rgep) 695 { 696 chip_id_t *chip = &rgep->chipid; 697 uint32_t val32; 698 uint16_t val16; 699 700 /* 701 * Read and record MAC version 702 */ 703 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 704 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 705 chip->mac_ver = val32; 706 switch (chip->mac_ver) { 707 case MAC_VER_8168: 708 case MAC_VER_8168B_B: 709 case MAC_VER_8168B_C: 710 case MAC_VER_8168C: 711 case MAC_VER_8101E: 712 case MAC_VER_8101E_B: 713 chip->is_pcie = B_TRUE; 714 break; 715 716 default: 717 chip->is_pcie = B_FALSE; 718 break; 719 } 720 721 /* 722 * Read and record PHY version 723 */ 724 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 725 val16 &= PHY_VER_MASK; 726 chip->phy_ver = val16; 727 728 /* set pci latency timer */ 729 if (chip->mac_ver == MAC_VER_8169 || 730 chip->mac_ver == MAC_VER_8169S_D || 731 chip->mac_ver == MAC_VER_8169SC) 732 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 733 734 if (chip->mac_ver == MAC_VER_8169SC) { 735 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 736 val16 &= 0x0300; 737 if (val16 == 0x1) /* 66Mhz PCI */ 738 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff); 739 else if (val16 == 0x0) /* 33Mhz PCI */ 740 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00); 741 } 742 743 /* 744 * PCIE chipset require the Rx buffer start address must be 745 * 8-byte alignment and the Rx buffer size must be multiple of 8. 746 * We'll just use bcopy in receive procedure for the PCIE chipset. 747 */ 748 if (chip->is_pcie) { 749 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 750 if (rgep->default_mtu > ETHERMTU) { 751 rge_notice(rgep, "Jumbo packets not supported " 752 "for this PCIE chipset"); 753 rgep->default_mtu = ETHERMTU; 754 } 755 } 756 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 757 rgep->head_room = 0; 758 else 759 rgep->head_room = RGE_HEADROOM; 760 761 /* 762 * Initialize other variables. 763 */ 764 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 765 rgep->default_mtu = ETHERMTU; 766 if (rgep->default_mtu > ETHERMTU) { 767 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 768 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 769 rgep->ethmax_size = RGE_JUMBO_SIZE; 770 } else { 771 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 772 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 773 rgep->ethmax_size = ETHERMAX; 774 } 775 chip->rxconfig = RX_CONFIG_DEFAULT; 776 chip->txconfig = TX_CONFIG_DEFAULT; 777 778 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 779 rgep->ifname, chip->mac_ver, chip->phy_ver)); 780 } 781 782 /* 783 * Perform first-stage chip (re-)initialisation, using only config-space 784 * accesses: 785 * 786 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 787 * returning the data in the structure pointed to by <idp>. 788 * + Enable Memory Space accesses. 789 * + Enable Bus Mastering according. 790 */ 791 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 792 #pragma no_inline(rge_chip_cfg_init) 793 794 void 795 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 796 { 797 ddi_acc_handle_t handle; 798 uint16_t commd; 799 800 handle = rgep->cfg_handle; 801 802 /* 803 * Save PCI cache line size and subsystem vendor ID 804 */ 805 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 806 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 807 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 808 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 809 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 810 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 811 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 812 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 813 814 /* 815 * Turn on Master Enable (DMA) and IO Enable bits. 816 * Enable PCI Memory Space accesses 817 */ 818 commd = cidp->command; 819 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 820 pci_config_put16(handle, PCI_CONF_COMM, commd); 821 822 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 823 cidp->vendor, cidp->device, cidp->revision)); 824 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 825 cidp->subven, cidp->subdev)); 826 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 827 cidp->clsize, cidp->latency, cidp->command)); 828 } 829 830 int rge_chip_reset(rge_t *rgep); 831 #pragma no_inline(rge_chip_reset) 832 833 int 834 rge_chip_reset(rge_t *rgep) 835 { 836 int i; 837 uint8_t val8; 838 839 /* 840 * Chip should be in STOP state 841 */ 842 rge_reg_clr8(rgep, RT_COMMAND_REG, 843 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 844 845 /* 846 * Disable interrupt 847 */ 848 rgep->int_mask = INT_MASK_NONE; 849 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 850 851 /* 852 * Clear pended interrupt 853 */ 854 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 855 856 /* 857 * Reset chip 858 */ 859 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 860 861 /* 862 * Wait for reset success 863 */ 864 for (i = 0; i < CHIP_RESET_LOOP; i++) { 865 drv_usecwait(10); 866 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 867 if (!(val8 & RT_COMMAND_RESET)) { 868 rgep->rge_chip_state = RGE_CHIP_RESET; 869 return (0); 870 } 871 } 872 RGE_REPORT((rgep, "rge_chip_reset fail.")); 873 return (-1); 874 } 875 876 void rge_chip_init(rge_t *rgep); 877 #pragma no_inline(rge_chip_init) 878 879 void 880 rge_chip_init(rge_t *rgep) 881 { 882 uint32_t val32; 883 uint32_t val16; 884 uint32_t *hashp; 885 chip_id_t *chip = &rgep->chipid; 886 887 if (chip->is_pcie) { 888 /* 889 * Increase the threshold voltage of RX sensitivity 890 */ 891 if (chip->mac_ver != MAC_VER_8168 && 892 chip->mac_ver != MAC_VER_8168C && 893 chip->mac_ver != MAC_VER_8101E_B) 894 rge_ephy_put16(rgep, 0x01, 0x1bd3); 895 896 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 897 val16 = 0x12<<8 | val16; 898 if (rgep->chipid.mac_ver != MAC_VER_8101E && 899 rgep->chipid.mac_ver != MAC_VER_8101E_B && 900 rgep->chipid.mac_ver != MAC_VER_8101E_C && 901 rgep->chipid.mac_ver != MAC_VER_8168B_C && 902 rgep->chipid.mac_ver != MAC_VER_8168C) { 903 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 904 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 905 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 906 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 907 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 908 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 909 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 910 val32 |= 0x7000; 911 val32 &= 0xffff5fff; 912 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 913 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 914 } 915 } 916 917 /* 918 * Config MII register 919 */ 920 rgep->param_link_up = LINK_STATE_DOWN; 921 rge_phy_update(rgep); 922 923 /* 924 * Enable Rx checksum offload. 925 * Then for vlan support, we must enable receive vlan de-tagging. 926 * Otherwise, there'll be checksum error. 927 */ 928 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 929 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 930 if (chip->mac_ver == MAC_VER_8169S_D) { 931 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 932 rge_reg_put8(rgep, RESV_82_REG, 0x01); 933 } 934 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 935 936 /* 937 * Start transmit/receive before set tx/rx configuration register 938 */ 939 if (!chip->is_pcie) 940 rge_reg_set8(rgep, RT_COMMAND_REG, 941 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 942 943 /* 944 * Set dump tally counter register 945 */ 946 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 947 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 948 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 949 val32 &= DUMP_COUNTER_REG_RESV; 950 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 951 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 952 953 /* 954 * Change to config register write enable mode 955 */ 956 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 957 958 /* 959 * Set Tx/Rx maximum packet size 960 */ 961 if (rgep->default_mtu > ETHERMTU) { 962 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 963 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 964 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { 965 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 966 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 967 } else { 968 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); 969 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); 970 } 971 972 /* 973 * Set receive configuration register 974 */ 975 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 976 val32 &= RX_CONFIG_REG_RESV; 977 if (rgep->promisc) 978 val32 |= RX_ACCEPT_ALL_PKT; 979 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 980 981 /* 982 * Set transmit configuration register 983 */ 984 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 985 val32 &= TX_CONFIG_REG_RESV; 986 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 987 988 /* 989 * Set Tx/Rx descriptor register 990 */ 991 val32 = rgep->tx_desc.cookie.dmac_laddress; 992 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 993 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 994 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 995 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 996 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 997 val32 = rgep->rx_desc.cookie.dmac_laddress; 998 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 999 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 1000 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 1001 1002 /* 1003 * Suggested setting from Realtek 1004 */ 1005 if (rgep->chipid.mac_ver != MAC_VER_8101E) 1006 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1007 else 1008 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); 1009 1010 /* 1011 * Set multicast register 1012 */ 1013 hashp = (uint32_t *)rgep->mcast_hash; 1014 if (rgep->promisc) { 1015 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U); 1016 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U); 1017 } else { 1018 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1019 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1020 } 1021 1022 /* 1023 * Msic register setting: 1024 * -- Missed packet counter: clear it 1025 * -- TimerInt Register 1026 * -- Timer count register 1027 */ 1028 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1029 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1030 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1031 1032 /* 1033 * disable the Unicast Wakeup Frame capability 1034 */ 1035 rge_reg_clr8(rgep, RT_CONFIG_5_REG, RT_UNI_WAKE_FRAME); 1036 1037 /* 1038 * Return to normal network/host communication mode 1039 */ 1040 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1041 drv_usecwait(20); 1042 } 1043 1044 /* 1045 * rge_chip_start() -- start the chip transmitting and/or receiving, 1046 * including enabling interrupts 1047 */ 1048 void rge_chip_start(rge_t *rgep); 1049 #pragma no_inline(rge_chip_start) 1050 1051 void 1052 rge_chip_start(rge_t *rgep) 1053 { 1054 /* 1055 * Clear statistics 1056 */ 1057 bzero(&rgep->stats, sizeof (rge_stats_t)); 1058 DMA_ZERO(rgep->dma_area_stats); 1059 1060 /* 1061 * Start transmit/receive 1062 */ 1063 rge_reg_set8(rgep, RT_COMMAND_REG, 1064 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1065 1066 /* 1067 * Enable interrupt 1068 */ 1069 rgep->int_mask = RGE_INT_MASK; 1070 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1071 1072 /* 1073 * All done! 1074 */ 1075 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1076 } 1077 1078 /* 1079 * rge_chip_stop() -- stop board receiving 1080 * 1081 * Since this function is also invoked by rge_quiesce(), it 1082 * must not block; also, no tracing or logging takes place 1083 * when invoked by rge_quiesce(). 1084 */ 1085 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1086 #pragma no_inline(rge_chip_stop) 1087 1088 void 1089 rge_chip_stop(rge_t *rgep, boolean_t fault) 1090 { 1091 /* 1092 * Disable interrupt 1093 */ 1094 rgep->int_mask = INT_MASK_NONE; 1095 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1096 1097 /* 1098 * Clear pended interrupt 1099 */ 1100 if (!rgep->suspended) { 1101 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1102 } 1103 1104 /* 1105 * Stop the board and disable transmit/receive 1106 */ 1107 rge_reg_clr8(rgep, RT_COMMAND_REG, 1108 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1109 1110 if (fault) 1111 rgep->rge_chip_state = RGE_CHIP_FAULT; 1112 else 1113 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1114 } 1115 1116 /* 1117 * rge_get_mac_addr() -- get the MAC address on NIC 1118 */ 1119 static void rge_get_mac_addr(rge_t *rgep); 1120 #pragma inline(rge_get_mac_addr) 1121 1122 static void 1123 rge_get_mac_addr(rge_t *rgep) 1124 { 1125 uint8_t *macaddr = rgep->netaddr; 1126 uint32_t val32; 1127 1128 /* 1129 * Read first 4-byte of mac address 1130 */ 1131 val32 = rge_reg_get32(rgep, ID_0_REG); 1132 macaddr[0] = val32 & 0xff; 1133 val32 = val32 >> 8; 1134 macaddr[1] = val32 & 0xff; 1135 val32 = val32 >> 8; 1136 macaddr[2] = val32 & 0xff; 1137 val32 = val32 >> 8; 1138 macaddr[3] = val32 & 0xff; 1139 1140 /* 1141 * Read last 2-byte of mac address 1142 */ 1143 val32 = rge_reg_get32(rgep, ID_4_REG); 1144 macaddr[4] = val32 & 0xff; 1145 val32 = val32 >> 8; 1146 macaddr[5] = val32 & 0xff; 1147 } 1148 1149 static void rge_set_mac_addr(rge_t *rgep); 1150 #pragma inline(rge_set_mac_addr) 1151 1152 static void 1153 rge_set_mac_addr(rge_t *rgep) 1154 { 1155 uint8_t *p = rgep->netaddr; 1156 uint32_t val32; 1157 1158 /* 1159 * Change to config register write enable mode 1160 */ 1161 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1162 1163 /* 1164 * Get first 4 bytes of mac address 1165 */ 1166 val32 = p[3]; 1167 val32 = val32 << 8; 1168 val32 |= p[2]; 1169 val32 = val32 << 8; 1170 val32 |= p[1]; 1171 val32 = val32 << 8; 1172 val32 |= p[0]; 1173 1174 /* 1175 * Set first 4 bytes of mac address 1176 */ 1177 rge_reg_put32(rgep, ID_0_REG, val32); 1178 1179 /* 1180 * Get last 2 bytes of mac address 1181 */ 1182 val32 = p[5]; 1183 val32 = val32 << 8; 1184 val32 |= p[4]; 1185 1186 /* 1187 * Set last 2 bytes of mac address 1188 */ 1189 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1190 rge_reg_put32(rgep, ID_4_REG, val32); 1191 1192 /* 1193 * Return to normal network/host communication mode 1194 */ 1195 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1196 } 1197 1198 static void rge_set_multi_addr(rge_t *rgep); 1199 #pragma inline(rge_set_multi_addr) 1200 1201 static void 1202 rge_set_multi_addr(rge_t *rgep) 1203 { 1204 uint32_t *hashp; 1205 1206 hashp = (uint32_t *)rgep->mcast_hash; 1207 1208 /* 1209 * Change to config register write enable mode 1210 */ 1211 if (rgep->chipid.mac_ver == MAC_VER_8169SC) { 1212 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1213 } 1214 if (rgep->promisc) { 1215 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U); 1216 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U); 1217 } else { 1218 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1219 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1220 } 1221 1222 /* 1223 * Return to normal network/host communication mode 1224 */ 1225 if (rgep->chipid.mac_ver == MAC_VER_8169SC) { 1226 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1227 } 1228 } 1229 1230 static void rge_set_promisc(rge_t *rgep); 1231 #pragma inline(rge_set_promisc) 1232 1233 static void 1234 rge_set_promisc(rge_t *rgep) 1235 { 1236 if (rgep->promisc) 1237 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1238 else 1239 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1240 } 1241 1242 /* 1243 * rge_chip_sync() -- program the chip with the unicast MAC address, 1244 * the multicast hash table, the required level of promiscuity, and 1245 * the current loopback mode ... 1246 */ 1247 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1248 #pragma no_inline(rge_chip_sync) 1249 1250 void 1251 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1252 { 1253 switch (todo) { 1254 case RGE_GET_MAC: 1255 rge_get_mac_addr(rgep); 1256 break; 1257 case RGE_SET_MAC: 1258 /* Reprogram the unicast MAC address(es) ... */ 1259 rge_set_mac_addr(rgep); 1260 break; 1261 case RGE_SET_MUL: 1262 /* Reprogram the hashed multicast address table ... */ 1263 rge_set_multi_addr(rgep); 1264 break; 1265 case RGE_SET_PROMISC: 1266 /* Set or clear the PROMISCUOUS mode bit */ 1267 rge_set_multi_addr(rgep); 1268 rge_set_promisc(rgep); 1269 break; 1270 default: 1271 break; 1272 } 1273 } 1274 1275 void rge_chip_blank(void *arg, time_t ticks, uint_t count, int flag); 1276 #pragma no_inline(rge_chip_blank) 1277 1278 /* ARGSUSED */ 1279 void 1280 rge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 1281 { 1282 _NOTE(ARGUNUSED(arg, ticks, count)); 1283 } 1284 1285 void rge_tx_trigger(rge_t *rgep); 1286 #pragma no_inline(rge_tx_trigger) 1287 1288 void 1289 rge_tx_trigger(rge_t *rgep) 1290 { 1291 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1292 } 1293 1294 void rge_hw_stats_dump(rge_t *rgep); 1295 #pragma no_inline(rge_tx_trigger) 1296 1297 void 1298 rge_hw_stats_dump(rge_t *rgep) 1299 { 1300 int i = 0; 1301 1302 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1303 drv_usecwait(100); 1304 if (++i > STATS_DUMP_LOOP) { 1305 RGE_DEBUG(("rge h/w statistics dump fail!")); 1306 rgep->rge_chip_state = RGE_CHIP_ERROR; 1307 return; 1308 } 1309 } 1310 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1311 1312 /* 1313 * Start H/W statistics dump for RTL8169 chip 1314 */ 1315 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1316 } 1317 1318 /* 1319 * ========== Hardware interrupt handler ========== 1320 */ 1321 1322 #undef RGE_DBG 1323 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1324 1325 static void rge_wake_factotum(rge_t *rgep); 1326 #pragma inline(rge_wake_factotum) 1327 1328 static void 1329 rge_wake_factotum(rge_t *rgep) 1330 { 1331 if (rgep->factotum_flag == 0) { 1332 rgep->factotum_flag = 1; 1333 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1334 } 1335 } 1336 1337 /* 1338 * rge_intr() -- handle chip interrupts 1339 */ 1340 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1341 #pragma no_inline(rge_intr) 1342 1343 uint_t 1344 rge_intr(caddr_t arg1, caddr_t arg2) 1345 { 1346 rge_t *rgep = (rge_t *)arg1; 1347 uint16_t int_status; 1348 1349 _NOTE(ARGUNUSED(arg2)) 1350 1351 mutex_enter(rgep->genlock); 1352 1353 if (rgep->suspended) { 1354 mutex_exit(rgep->genlock); 1355 return (DDI_INTR_UNCLAIMED); 1356 } 1357 1358 /* 1359 * Was this interrupt caused by our device... 1360 */ 1361 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1362 if (!(int_status & rgep->int_mask)) { 1363 mutex_exit(rgep->genlock); 1364 return (DDI_INTR_UNCLAIMED); 1365 /* indicate it wasn't our interrupt */ 1366 } 1367 rgep->stats.intr++; 1368 1369 /* 1370 * Clear interrupt 1371 * For PCIE chipset, we need disable interrupt first. 1372 */ 1373 if (rgep->chipid.is_pcie) 1374 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1375 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1376 1377 /* 1378 * Cable link change interrupt 1379 */ 1380 if (int_status & LINK_CHANGE_INT) { 1381 rge_chip_cyclic(rgep); 1382 } 1383 1384 mutex_exit(rgep->genlock); 1385 1386 /* 1387 * Receive interrupt 1388 */ 1389 if (int_status & RGE_RX_INT) 1390 rge_receive(rgep); 1391 1392 /* 1393 * Re-enable interrupt for PCIE chipset 1394 */ 1395 if (rgep->chipid.is_pcie) 1396 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1397 1398 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1399 } 1400 1401 /* 1402 * ========== Factotum, implemented as a softint handler ========== 1403 */ 1404 1405 #undef RGE_DBG 1406 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1407 1408 static boolean_t rge_factotum_link_check(rge_t *rgep); 1409 #pragma no_inline(rge_factotum_link_check) 1410 1411 static boolean_t 1412 rge_factotum_link_check(rge_t *rgep) 1413 { 1414 uint8_t media_status; 1415 int32_t link; 1416 1417 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1418 link = (media_status & PHY_STATUS_LINK_UP) ? 1419 LINK_STATE_UP : LINK_STATE_DOWN; 1420 if (rgep->param_link_up != link) { 1421 /* 1422 * Link change. 1423 */ 1424 rgep->param_link_up = link; 1425 1426 if (link == LINK_STATE_UP) { 1427 if (media_status & PHY_STATUS_1000MF) { 1428 rgep->param_link_speed = RGE_SPEED_1000M; 1429 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1430 } else { 1431 rgep->param_link_speed = 1432 (media_status & PHY_STATUS_100M) ? 1433 RGE_SPEED_100M : RGE_SPEED_10M; 1434 rgep->param_link_duplex = 1435 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1436 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1437 } 1438 } 1439 return (B_TRUE); 1440 } 1441 return (B_FALSE); 1442 } 1443 1444 /* 1445 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1446 */ 1447 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1448 #pragma no_inline(rge_factotum_stall_check) 1449 1450 static boolean_t 1451 rge_factotum_stall_check(rge_t *rgep) 1452 { 1453 uint32_t dogval; 1454 1455 ASSERT(mutex_owned(rgep->genlock)); 1456 1457 /* 1458 * Specific check for Tx stall ... 1459 * 1460 * The 'watchdog' counter is incremented whenever a packet 1461 * is queued, reset to 1 when some (but not all) buffers 1462 * are reclaimed, reset to 0 (disabled) when all buffers 1463 * are reclaimed, and shifted left here. If it exceeds the 1464 * threshold value, the chip is assumed to have stalled and 1465 * is put into the ERROR state. The factotum will then reset 1466 * it on the next pass. 1467 * 1468 * All of which should ensure that we don't get into a state 1469 * where packets are left pending indefinitely! 1470 */ 1471 if (rgep->resched_needed) 1472 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1473 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1474 if (dogval < rge_watchdog_count) 1475 return (B_FALSE); 1476 1477 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1478 return (B_TRUE); 1479 1480 } 1481 1482 /* 1483 * The factotum is woken up when there's something to do that we'd rather 1484 * not do from inside a hardware interrupt handler or high-level cyclic. 1485 * Its two main tasks are: 1486 * reset & restart the chip after an error 1487 * check the link status whenever necessary 1488 */ 1489 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1490 #pragma no_inline(rge_chip_factotum) 1491 1492 uint_t 1493 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1494 { 1495 rge_t *rgep; 1496 uint_t result; 1497 boolean_t error; 1498 boolean_t linkchg; 1499 1500 rgep = (rge_t *)arg1; 1501 _NOTE(ARGUNUSED(arg2)) 1502 1503 if (rgep->factotum_flag == 0) 1504 return (DDI_INTR_UNCLAIMED); 1505 1506 rgep->factotum_flag = 0; 1507 result = DDI_INTR_CLAIMED; 1508 error = B_FALSE; 1509 linkchg = B_FALSE; 1510 1511 mutex_enter(rgep->genlock); 1512 switch (rgep->rge_chip_state) { 1513 default: 1514 break; 1515 1516 case RGE_CHIP_RUNNING: 1517 linkchg = rge_factotum_link_check(rgep); 1518 error = rge_factotum_stall_check(rgep); 1519 break; 1520 1521 case RGE_CHIP_ERROR: 1522 error = B_TRUE; 1523 break; 1524 1525 case RGE_CHIP_FAULT: 1526 /* 1527 * Fault detected, time to reset ... 1528 */ 1529 if (rge_autorecover) { 1530 RGE_REPORT((rgep, "automatic recovery activated")); 1531 rge_restart(rgep); 1532 } 1533 break; 1534 } 1535 1536 /* 1537 * If an error is detected, stop the chip now, marking it as 1538 * faulty, so that it will be reset next time through ... 1539 */ 1540 if (error) 1541 rge_chip_stop(rgep, B_TRUE); 1542 mutex_exit(rgep->genlock); 1543 1544 /* 1545 * If the link state changed, tell the world about it. 1546 * Note: can't do this while still holding the mutex. 1547 */ 1548 if (linkchg) 1549 mac_link_update(rgep->mh, rgep->param_link_up); 1550 1551 return (result); 1552 } 1553 1554 /* 1555 * High-level cyclic handler 1556 * 1557 * This routine schedules a (low-level) softint callback to the 1558 * factotum, and prods the chip to update the status block (which 1559 * will cause a hardware interrupt when complete). 1560 */ 1561 void rge_chip_cyclic(void *arg); 1562 #pragma no_inline(rge_chip_cyclic) 1563 1564 void 1565 rge_chip_cyclic(void *arg) 1566 { 1567 rge_t *rgep; 1568 1569 rgep = arg; 1570 1571 switch (rgep->rge_chip_state) { 1572 default: 1573 return; 1574 1575 case RGE_CHIP_RUNNING: 1576 rge_phy_check(rgep); 1577 break; 1578 1579 case RGE_CHIP_FAULT: 1580 case RGE_CHIP_ERROR: 1581 break; 1582 } 1583 1584 rge_wake_factotum(rgep); 1585 } 1586 1587 1588 /* 1589 * ========== Ioctl subfunctions ========== 1590 */ 1591 1592 #undef RGE_DBG 1593 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1594 1595 #if RGE_DEBUGGING || RGE_DO_PPIO 1596 1597 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1598 #pragma no_inline(rge_chip_peek_cfg) 1599 1600 static void 1601 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1602 { 1603 uint64_t regval; 1604 uint64_t regno; 1605 1606 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1607 (void *)rgep, (void *)ppd)); 1608 1609 regno = ppd->pp_acc_offset; 1610 1611 switch (ppd->pp_acc_size) { 1612 case 1: 1613 regval = pci_config_get8(rgep->cfg_handle, regno); 1614 break; 1615 1616 case 2: 1617 regval = pci_config_get16(rgep->cfg_handle, regno); 1618 break; 1619 1620 case 4: 1621 regval = pci_config_get32(rgep->cfg_handle, regno); 1622 break; 1623 1624 case 8: 1625 regval = pci_config_get64(rgep->cfg_handle, regno); 1626 break; 1627 } 1628 1629 ppd->pp_acc_data = regval; 1630 } 1631 1632 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1633 #pragma no_inline(rge_chip_poke_cfg) 1634 1635 static void 1636 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1637 { 1638 uint64_t regval; 1639 uint64_t regno; 1640 1641 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1642 (void *)rgep, (void *)ppd)); 1643 1644 regno = ppd->pp_acc_offset; 1645 regval = ppd->pp_acc_data; 1646 1647 switch (ppd->pp_acc_size) { 1648 case 1: 1649 pci_config_put8(rgep->cfg_handle, regno, regval); 1650 break; 1651 1652 case 2: 1653 pci_config_put16(rgep->cfg_handle, regno, regval); 1654 break; 1655 1656 case 4: 1657 pci_config_put32(rgep->cfg_handle, regno, regval); 1658 break; 1659 1660 case 8: 1661 pci_config_put64(rgep->cfg_handle, regno, regval); 1662 break; 1663 } 1664 } 1665 1666 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1667 #pragma no_inline(rge_chip_peek_reg) 1668 1669 static void 1670 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1671 { 1672 uint64_t regval; 1673 void *regaddr; 1674 1675 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1676 (void *)rgep, (void *)ppd)); 1677 1678 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1679 1680 switch (ppd->pp_acc_size) { 1681 case 1: 1682 regval = ddi_get8(rgep->io_handle, regaddr); 1683 break; 1684 1685 case 2: 1686 regval = ddi_get16(rgep->io_handle, regaddr); 1687 break; 1688 1689 case 4: 1690 regval = ddi_get32(rgep->io_handle, regaddr); 1691 break; 1692 1693 case 8: 1694 regval = ddi_get64(rgep->io_handle, regaddr); 1695 break; 1696 } 1697 1698 ppd->pp_acc_data = regval; 1699 } 1700 1701 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1702 #pragma no_inline(rge_chip_peek_reg) 1703 1704 static void 1705 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1706 { 1707 uint64_t regval; 1708 void *regaddr; 1709 1710 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1711 (void *)rgep, (void *)ppd)); 1712 1713 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1714 regval = ppd->pp_acc_data; 1715 1716 switch (ppd->pp_acc_size) { 1717 case 1: 1718 ddi_put8(rgep->io_handle, regaddr, regval); 1719 break; 1720 1721 case 2: 1722 ddi_put16(rgep->io_handle, regaddr, regval); 1723 break; 1724 1725 case 4: 1726 ddi_put32(rgep->io_handle, regaddr, regval); 1727 break; 1728 1729 case 8: 1730 ddi_put64(rgep->io_handle, regaddr, regval); 1731 break; 1732 } 1733 } 1734 1735 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1736 #pragma no_inline(rge_chip_peek_mii) 1737 1738 static void 1739 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1740 { 1741 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1742 (void *)rgep, (void *)ppd)); 1743 1744 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1745 } 1746 1747 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1748 #pragma no_inline(rge_chip_poke_mii) 1749 1750 static void 1751 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1752 { 1753 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1754 (void *)rgep, (void *)ppd)); 1755 1756 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1757 } 1758 1759 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1760 #pragma no_inline(rge_chip_peek_mem) 1761 1762 static void 1763 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1764 { 1765 uint64_t regval; 1766 void *vaddr; 1767 1768 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1769 (void *)rgep, (void *)ppd)); 1770 1771 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1772 1773 switch (ppd->pp_acc_size) { 1774 case 1: 1775 regval = *(uint8_t *)vaddr; 1776 break; 1777 1778 case 2: 1779 regval = *(uint16_t *)vaddr; 1780 break; 1781 1782 case 4: 1783 regval = *(uint32_t *)vaddr; 1784 break; 1785 1786 case 8: 1787 regval = *(uint64_t *)vaddr; 1788 break; 1789 } 1790 1791 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1792 (void *)rgep, (void *)ppd, regval, vaddr)); 1793 1794 ppd->pp_acc_data = regval; 1795 } 1796 1797 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1798 #pragma no_inline(rge_chip_poke_mem) 1799 1800 static void 1801 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1802 { 1803 uint64_t regval; 1804 void *vaddr; 1805 1806 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1807 (void *)rgep, (void *)ppd)); 1808 1809 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1810 regval = ppd->pp_acc_data; 1811 1812 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1813 (void *)rgep, (void *)ppd, regval, vaddr)); 1814 1815 switch (ppd->pp_acc_size) { 1816 case 1: 1817 *(uint8_t *)vaddr = (uint8_t)regval; 1818 break; 1819 1820 case 2: 1821 *(uint16_t *)vaddr = (uint16_t)regval; 1822 break; 1823 1824 case 4: 1825 *(uint32_t *)vaddr = (uint32_t)regval; 1826 break; 1827 1828 case 8: 1829 *(uint64_t *)vaddr = (uint64_t)regval; 1830 break; 1831 } 1832 } 1833 1834 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1835 struct iocblk *iocp); 1836 #pragma no_inline(rge_pp_ioctl) 1837 1838 static enum ioc_reply 1839 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1840 { 1841 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1842 rge_peekpoke_t *ppd; 1843 dma_area_t *areap; 1844 uint64_t sizemask; 1845 uint64_t mem_va; 1846 uint64_t maxoff; 1847 boolean_t peek; 1848 1849 switch (cmd) { 1850 default: 1851 /* NOTREACHED */ 1852 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1853 return (IOC_INVAL); 1854 1855 case RGE_PEEK: 1856 peek = B_TRUE; 1857 break; 1858 1859 case RGE_POKE: 1860 peek = B_FALSE; 1861 break; 1862 } 1863 1864 /* 1865 * Validate format of ioctl 1866 */ 1867 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1868 return (IOC_INVAL); 1869 if (mp->b_cont == NULL) 1870 return (IOC_INVAL); 1871 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1872 1873 /* 1874 * Validate request parameters 1875 */ 1876 switch (ppd->pp_acc_space) { 1877 default: 1878 return (IOC_INVAL); 1879 1880 case RGE_PP_SPACE_CFG: 1881 /* 1882 * Config space 1883 */ 1884 sizemask = 8|4|2|1; 1885 mem_va = 0; 1886 maxoff = PCI_CONF_HDR_SIZE; 1887 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1888 break; 1889 1890 case RGE_PP_SPACE_REG: 1891 /* 1892 * Memory-mapped I/O space 1893 */ 1894 sizemask = 8|4|2|1; 1895 mem_va = 0; 1896 maxoff = RGE_REGISTER_MAX; 1897 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1898 break; 1899 1900 case RGE_PP_SPACE_MII: 1901 /* 1902 * PHY's MII registers 1903 * NB: all PHY registers are two bytes, but the 1904 * addresses increment in ones (word addressing). 1905 * So we scale the address here, then undo the 1906 * transformation inside the peek/poke functions. 1907 */ 1908 ppd->pp_acc_offset *= 2; 1909 sizemask = 2; 1910 mem_va = 0; 1911 maxoff = (MII_MAXREG+1)*2; 1912 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1913 break; 1914 1915 case RGE_PP_SPACE_RGE: 1916 /* 1917 * RGE data structure! 1918 */ 1919 sizemask = 8|4|2|1; 1920 mem_va = (uintptr_t)rgep; 1921 maxoff = sizeof (*rgep); 1922 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1923 break; 1924 1925 case RGE_PP_SPACE_STATISTICS: 1926 case RGE_PP_SPACE_TXDESC: 1927 case RGE_PP_SPACE_TXBUFF: 1928 case RGE_PP_SPACE_RXDESC: 1929 case RGE_PP_SPACE_RXBUFF: 1930 /* 1931 * Various DMA_AREAs 1932 */ 1933 switch (ppd->pp_acc_space) { 1934 case RGE_PP_SPACE_TXDESC: 1935 areap = &rgep->dma_area_txdesc; 1936 break; 1937 case RGE_PP_SPACE_RXDESC: 1938 areap = &rgep->dma_area_rxdesc; 1939 break; 1940 case RGE_PP_SPACE_STATISTICS: 1941 areap = &rgep->dma_area_stats; 1942 break; 1943 } 1944 1945 sizemask = 8|4|2|1; 1946 mem_va = (uintptr_t)areap->mem_va; 1947 maxoff = areap->alength; 1948 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1949 break; 1950 } 1951 1952 switch (ppd->pp_acc_size) { 1953 default: 1954 return (IOC_INVAL); 1955 1956 case 8: 1957 case 4: 1958 case 2: 1959 case 1: 1960 if ((ppd->pp_acc_size & sizemask) == 0) 1961 return (IOC_INVAL); 1962 break; 1963 } 1964 1965 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1966 return (IOC_INVAL); 1967 1968 if (ppd->pp_acc_offset >= maxoff) 1969 return (IOC_INVAL); 1970 1971 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1972 return (IOC_INVAL); 1973 1974 /* 1975 * All OK - go do it! 1976 */ 1977 ppd->pp_acc_offset += mem_va; 1978 (*ppfn)(rgep, ppd); 1979 return (peek ? IOC_REPLY : IOC_ACK); 1980 } 1981 1982 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1983 struct iocblk *iocp); 1984 #pragma no_inline(rge_diag_ioctl) 1985 1986 static enum ioc_reply 1987 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1988 { 1989 ASSERT(mutex_owned(rgep->genlock)); 1990 1991 switch (cmd) { 1992 default: 1993 /* NOTREACHED */ 1994 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 1995 return (IOC_INVAL); 1996 1997 case RGE_DIAG: 1998 /* 1999 * Currently a no-op 2000 */ 2001 return (IOC_ACK); 2002 2003 case RGE_PEEK: 2004 case RGE_POKE: 2005 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 2006 2007 case RGE_PHY_RESET: 2008 return (IOC_RESTART_ACK); 2009 2010 case RGE_SOFT_RESET: 2011 case RGE_HARD_RESET: 2012 /* 2013 * Reset and reinitialise the 570x hardware 2014 */ 2015 rge_restart(rgep); 2016 return (IOC_ACK); 2017 } 2018 2019 /* NOTREACHED */ 2020 } 2021 2022 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2023 2024 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2025 struct iocblk *iocp); 2026 #pragma no_inline(rge_mii_ioctl) 2027 2028 static enum ioc_reply 2029 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2030 { 2031 struct rge_mii_rw *miirwp; 2032 2033 /* 2034 * Validate format of ioctl 2035 */ 2036 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2037 return (IOC_INVAL); 2038 if (mp->b_cont == NULL) 2039 return (IOC_INVAL); 2040 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2041 2042 /* 2043 * Validate request parameters ... 2044 */ 2045 if (miirwp->mii_reg > MII_MAXREG) 2046 return (IOC_INVAL); 2047 2048 switch (cmd) { 2049 default: 2050 /* NOTREACHED */ 2051 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2052 return (IOC_INVAL); 2053 2054 case RGE_MII_READ: 2055 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2056 return (IOC_REPLY); 2057 2058 case RGE_MII_WRITE: 2059 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2060 return (IOC_ACK); 2061 } 2062 2063 /* NOTREACHED */ 2064 } 2065 2066 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2067 struct iocblk *iocp); 2068 #pragma no_inline(rge_chip_ioctl) 2069 2070 enum ioc_reply 2071 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2072 { 2073 int cmd; 2074 2075 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2076 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2077 2078 ASSERT(mutex_owned(rgep->genlock)); 2079 2080 cmd = iocp->ioc_cmd; 2081 switch (cmd) { 2082 default: 2083 /* NOTREACHED */ 2084 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2085 return (IOC_INVAL); 2086 2087 case RGE_DIAG: 2088 case RGE_PEEK: 2089 case RGE_POKE: 2090 case RGE_PHY_RESET: 2091 case RGE_SOFT_RESET: 2092 case RGE_HARD_RESET: 2093 #if RGE_DEBUGGING || RGE_DO_PPIO 2094 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2095 #else 2096 return (IOC_INVAL); 2097 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2098 2099 case RGE_MII_READ: 2100 case RGE_MII_WRITE: 2101 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2102 2103 } 2104 2105 /* NOTREACHED */ 2106 } 2107