1 /* 2 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2005, 2006 8 * Damien Bergamini <damien.bergamini@free.fr> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 /* 24 * Ralink Technology RT2560 chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #pragma ident "%Z%%M% %I% %E% SMI" 29 30 #include <sys/types.h> 31 #include <sys/byteorder.h> 32 #include <sys/conf.h> 33 #include <sys/cmn_err.h> 34 #include <sys/stat.h> 35 #include <sys/ddi.h> 36 #include <sys/sunddi.h> 37 #include <sys/strsubr.h> 38 #include <sys/ethernet.h> 39 #include <inet/common.h> 40 #include <inet/nd.h> 41 #include <inet/mi.h> 42 #include <sys/note.h> 43 #include <sys/stream.h> 44 #include <sys/strsun.h> 45 #include <sys/modctl.h> 46 #include <sys/devops.h> 47 #include <sys/dlpi.h> 48 #include <sys/mac.h> 49 #include <sys/mac_wifi.h> 50 #include <sys/net80211.h> 51 #include <sys/net80211_proto.h> 52 #include <sys/varargs.h> 53 #include <sys/policy.h> 54 #include <sys/pci.h> 55 #include <sys/crypto/common.h> 56 #include <sys/crypto/api.h> 57 #include <inet/wifi_ioctl.h> 58 59 #include "ral_rate.h" 60 #include "rt2560_reg.h" 61 #include "rt2560_var.h" 62 63 64 static void *ral_soft_state_p = NULL; 65 66 #define RAL_TXBUF_SIZE (IEEE80211_MAX_LEN) 67 #define RAL_RXBUF_SIZE (IEEE80211_MAX_LEN) 68 69 /* quickly determine if a given rate is CCK or OFDM */ 70 #define RAL_RATE_IS_OFDM(rate) ((rate) >= 12 && (rate) != 22) 71 #define RAL_ACK_SIZE 14 /* 10 + 4(FCS) */ 72 #define RAL_CTS_SIZE 14 /* 10 + 4(FCS) */ 73 #define RAL_SIFS 10 /* us */ 74 #define RT2560_TXRX_TURNAROUND 10 /* us */ 75 76 /* 77 * Supported rates for 802.11a/b/g modes (in 500Kbps unit). 78 */ 79 static const struct ieee80211_rateset rt2560_rateset_11a = 80 { 8, { 12, 18, 24, 36, 48, 72, 96, 108 } }; 81 82 static const struct ieee80211_rateset rt2560_rateset_11b = 83 { 4, { 2, 4, 11, 22 } }; 84 85 static const struct ieee80211_rateset rt2560_rateset_11g = 86 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } }; 87 88 static const struct { 89 uint32_t reg; 90 uint32_t val; 91 } rt2560_def_mac[] = { 92 RT2560_DEF_MAC 93 }; 94 95 static const struct { 96 uint8_t reg; 97 uint8_t val; 98 } rt2560_def_bbp[] = { 99 RT2560_DEF_BBP 100 }; 101 102 static const uint32_t rt2560_rf2522_r2[] = RT2560_RF2522_R2; 103 static const uint32_t rt2560_rf2523_r2[] = RT2560_RF2523_R2; 104 static const uint32_t rt2560_rf2524_r2[] = RT2560_RF2524_R2; 105 static const uint32_t rt2560_rf2525_r2[] = RT2560_RF2525_R2; 106 static const uint32_t rt2560_rf2525_hi_r2[] = RT2560_RF2525_HI_R2; 107 static const uint32_t rt2560_rf2525e_r2[] = RT2560_RF2525E_R2; 108 static const uint32_t rt2560_rf2526_r2[] = RT2560_RF2526_R2; 109 static const uint32_t rt2560_rf2526_hi_r2[] = RT2560_RF2526_HI_R2; 110 111 static const struct { 112 uint8_t chan; 113 uint32_t r1, r2, r4; 114 } rt2560_rf5222[] = { 115 RT2560_RF5222 116 }; 117 118 /* 119 * PIO access attributes for registers 120 */ 121 static ddi_device_acc_attr_t ral_csr_accattr = { 122 DDI_DEVICE_ATTR_V0, 123 DDI_STRUCTURE_LE_ACC, 124 DDI_STRICTORDER_ACC 125 }; 126 127 /* 128 * DMA access attributes for descriptors: NOT to be byte swapped. 129 */ 130 static ddi_device_acc_attr_t ral_desc_accattr = { 131 DDI_DEVICE_ATTR_V0, 132 DDI_STRUCTURE_LE_ACC, 133 DDI_STRICTORDER_ACC 134 }; 135 136 /* 137 * Describes the chip's DMA engine 138 */ 139 static ddi_dma_attr_t ral_dma_attr = { 140 DMA_ATTR_V0, /* dma_attr version */ 141 0x0000000000000000ull, /* dma_attr_addr_lo */ 142 0xFFFFFFFF, /* dma_attr_addr_hi */ 143 0x00000000FFFFFFFFull, /* dma_attr_count_max */ 144 0x0000000000000001ull, /* dma_attr_align */ 145 0x00000FFF, /* dma_attr_burstsizes */ 146 0x00000001, /* dma_attr_minxfer */ 147 0x000000000000FFFFull, /* dma_attr_maxxfer */ 148 0xFFFFFFFFFFFFFFFFull, /* dma_attr_seg */ 149 1, /* dma_attr_sgllen */ 150 0x00000001, /* dma_attr_granular */ 151 0 /* dma_attr_flags */ 152 }; 153 154 /* 155 * device operations 156 */ 157 static int rt2560_attach(dev_info_t *, ddi_attach_cmd_t); 158 static int rt2560_detach(dev_info_t *, ddi_detach_cmd_t); 159 static int rt2560_reset(dev_info_t *, ddi_reset_cmd_t); 160 161 /* 162 * Module Loading Data & Entry Points 163 */ 164 DDI_DEFINE_STREAM_OPS(ral_dev_ops, nulldev, nulldev, rt2560_attach, 165 rt2560_detach, rt2560_reset, NULL, D_MP, NULL); 166 167 static struct modldrv ral_modldrv = { 168 &mod_driverops, /* Type of module. This one is a driver */ 169 "Ralink RT2500 driver v%I%", /* short description */ 170 &ral_dev_ops /* driver specific ops */ 171 }; 172 173 static struct modlinkage modlinkage = { 174 MODREV_1, 175 (void *)&ral_modldrv, 176 NULL 177 }; 178 179 static int rt2560_m_stat(void *, uint_t, uint64_t *); 180 static int rt2560_m_start(void *); 181 static void rt2560_m_stop(void *); 182 static int rt2560_m_promisc(void *, boolean_t); 183 static int rt2560_m_multicst(void *, boolean_t, const uint8_t *); 184 static int rt2560_m_unicst(void *, const uint8_t *); 185 static mblk_t *rt2560_m_tx(void *, mblk_t *); 186 static void rt2560_m_ioctl(void *, queue_t *, mblk_t *); 187 188 static mac_callbacks_t rt2560_m_callbacks = { 189 MC_IOCTL, 190 rt2560_m_stat, 191 rt2560_m_start, 192 rt2560_m_stop, 193 rt2560_m_promisc, 194 rt2560_m_multicst, 195 rt2560_m_unicst, 196 rt2560_m_tx, 197 NULL, /* mc_resources; */ 198 rt2560_m_ioctl, 199 NULL /* mc_getcapab */ 200 }; 201 202 uint32_t ral_dbg_flags = 0; 203 204 void 205 ral_debug(uint32_t dbg_flags, const int8_t *fmt, ...) 206 { 207 va_list args; 208 209 if (dbg_flags & ral_dbg_flags) { 210 va_start(args, fmt); 211 vcmn_err(CE_CONT, fmt, args); 212 va_end(args); 213 } 214 } 215 216 static void 217 rt2560_set_basicrates(struct rt2560_softc *sc) 218 { 219 struct ieee80211com *ic = &sc->sc_ic; 220 221 /* update basic rate set */ 222 if (ic->ic_curmode == IEEE80211_MODE_11B) { 223 /* 11b basic rates: 1, 2Mbps */ 224 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x3); 225 } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) { 226 /* 11a basic rates: 6, 12, 24Mbps */ 227 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x150); 228 } else { 229 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 230 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x15f); 231 } 232 } 233 234 static void 235 rt2560_update_led(struct rt2560_softc *sc, int led1, int led2) 236 { 237 uint32_t tmp; 238 239 /* set ON period to 70ms and OFF period to 30ms */ 240 tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30; 241 RAL_WRITE(sc, RT2560_LEDCSR, tmp); 242 } 243 244 static void 245 rt2560_set_bssid(struct rt2560_softc *sc, uint8_t *bssid) 246 { 247 uint32_t tmp; 248 249 tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; 250 RAL_WRITE(sc, RT2560_CSR5, tmp); 251 252 tmp = bssid[4] | bssid[5] << 8; 253 RAL_WRITE(sc, RT2560_CSR6, tmp); 254 255 RAL_DEBUG(RAL_DBG_HW, "setting BSSID to " MACSTR "\n", MAC2STR(bssid)); 256 } 257 258 259 static void 260 rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val) 261 { 262 uint32_t tmp; 263 int ntries; 264 265 for (ntries = 0; ntries < 100; ntries++) { 266 if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY)) 267 break; 268 drv_usecwait(1); 269 } 270 if (ntries == 100) { 271 RAL_DEBUG(RAL_DBG_HW, "could not write to BBP\n"); 272 return; 273 } 274 275 tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val; 276 RAL_WRITE(sc, RT2560_BBPCSR, tmp); 277 278 RAL_DEBUG(RAL_DBG_HW, "BBP R%u <- 0x%02x\n", reg, val); 279 } 280 281 static uint8_t 282 rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg) 283 { 284 uint32_t val; 285 int ntries; 286 287 val = RT2560_BBP_BUSY | reg << 8; 288 RAL_WRITE(sc, RT2560_BBPCSR, val); 289 290 for (ntries = 0; ntries < 100; ntries++) { 291 val = RAL_READ(sc, RT2560_BBPCSR); 292 if (!(val & RT2560_BBP_BUSY)) 293 return (val & 0xff); 294 drv_usecwait(1); 295 } 296 297 RAL_DEBUG(RAL_DBG_HW, "could not read from BBP\n"); 298 return (0); 299 } 300 301 static void 302 rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val) 303 { 304 uint32_t tmp; 305 int ntries; 306 307 for (ntries = 0; ntries < 100; ntries++) { 308 if (!(RAL_READ(sc, RT2560_RFCSR) & RT2560_RF_BUSY)) 309 break; 310 drv_usecwait(1); 311 } 312 if (ntries == 100) { 313 RAL_DEBUG(RAL_DBG_HW, "could not write to RF\n"); 314 return; 315 } 316 317 tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 | 318 (reg & 0x3); 319 RAL_WRITE(sc, RT2560_RFCSR, tmp); 320 321 /* remember last written value in sc */ 322 sc->rf_regs[reg] = val; 323 324 RAL_DEBUG(RAL_DBG_HW, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 325 } 326 327 static void 328 rt2560_set_chan(struct rt2560_softc *sc, struct ieee80211_channel *c) 329 { 330 struct ieee80211com *ic = &sc->sc_ic; 331 uint8_t power, tmp; 332 uint_t i, chan; 333 334 chan = ieee80211_chan2ieee(ic, c); 335 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 336 return; 337 338 if (IEEE80211_IS_CHAN_2GHZ(c)) 339 power = min(sc->txpow[chan - 1], 31); 340 else 341 power = 31; 342 343 /* adjust txpower using ifconfig settings */ 344 power -= (100 - ic->ic_txpowlimit) / 8; 345 346 RAL_DEBUG(RAL_DBG_CHAN, "setting channel to %u, txpower to %u\n", 347 chan, power); 348 349 switch (sc->rf_rev) { 350 case RT2560_RF_2522: 351 rt2560_rf_write(sc, RAL_RF1, 0x00814); 352 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2522_r2[chan - 1]); 353 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 354 break; 355 356 case RT2560_RF_2523: 357 rt2560_rf_write(sc, RAL_RF1, 0x08804); 358 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2523_r2[chan - 1]); 359 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 360 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 361 break; 362 363 case RT2560_RF_2524: 364 rt2560_rf_write(sc, RAL_RF1, 0x0c808); 365 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2524_r2[chan - 1]); 366 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 367 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 368 break; 369 370 case RT2560_RF_2525: 371 rt2560_rf_write(sc, RAL_RF1, 0x08808); 372 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_hi_r2[chan - 1]); 373 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 374 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 375 376 rt2560_rf_write(sc, RAL_RF1, 0x08808); 377 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_r2[chan - 1]); 378 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 379 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 380 break; 381 382 case RT2560_RF_2525E: 383 rt2560_rf_write(sc, RAL_RF1, 0x08808); 384 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525e_r2[chan - 1]); 385 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 386 rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 387 break; 388 389 case RT2560_RF_2526: 390 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_hi_r2[chan - 1]); 391 rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 392 rt2560_rf_write(sc, RAL_RF1, 0x08804); 393 394 rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_r2[chan - 1]); 395 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 396 rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 397 break; 398 399 /* dual-band RF */ 400 case RT2560_RF_5222: 401 for (i = 0; rt2560_rf5222[i].chan != chan; i++) { 402 } 403 404 rt2560_rf_write(sc, RAL_RF1, rt2560_rf5222[i].r1); 405 rt2560_rf_write(sc, RAL_RF2, rt2560_rf5222[i].r2); 406 rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 407 rt2560_rf_write(sc, RAL_RF4, rt2560_rf5222[i].r4); 408 break; 409 } 410 411 if (ic->ic_state != IEEE80211_S_SCAN) { 412 /* set Japan filter bit for channel 14 */ 413 tmp = rt2560_bbp_read(sc, 70); 414 415 tmp &= ~RT2560_JAPAN_FILTER; 416 if (chan == 14) 417 tmp |= RT2560_JAPAN_FILTER; 418 419 rt2560_bbp_write(sc, 70, tmp); 420 421 /* clear CRC errors */ 422 (void) RAL_READ(sc, RT2560_CNT0); 423 } 424 } 425 426 /* 427 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 428 * synchronization. 429 */ 430 static void 431 rt2560_enable_tsf_sync(struct rt2560_softc *sc) 432 { 433 struct ieee80211com *ic = &sc->sc_ic; 434 uint16_t logcwmin, preload; 435 uint32_t tmp; 436 437 /* first, disable TSF synchronization */ 438 RAL_WRITE(sc, RT2560_CSR14, 0); 439 440 tmp = 16 * ic->ic_bss->in_intval; 441 RAL_WRITE(sc, RT2560_CSR12, tmp); 442 443 RAL_WRITE(sc, RT2560_CSR13, 0); 444 445 logcwmin = 5; 446 preload = (ic->ic_opmode == IEEE80211_M_STA) ? 384 : 1024; 447 tmp = logcwmin << 16 | preload; 448 RAL_WRITE(sc, RT2560_BCNOCSR, tmp); 449 450 /* finally, enable TSF synchronization */ 451 tmp = RT2560_ENABLE_TSF | RT2560_ENABLE_TBCN; 452 if (ic->ic_opmode == IEEE80211_M_STA) 453 tmp |= RT2560_ENABLE_TSF_SYNC(1); 454 else 455 tmp |= RT2560_ENABLE_TSF_SYNC(2) | 456 RT2560_ENABLE_BEACON_GENERATOR; 457 RAL_WRITE(sc, RT2560_CSR14, tmp); 458 459 RAL_DEBUG(RAL_DBG_HW, "enabling TSF synchronization\n"); 460 } 461 462 static void 463 rt2560_update_plcp(struct rt2560_softc *sc) 464 { 465 struct ieee80211com *ic = &sc->sc_ic; 466 467 /* no short preamble for 1Mbps */ 468 RAL_WRITE(sc, RT2560_PLCP1MCSR, 0x00700400); 469 470 if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) { 471 /* values taken from the reference driver */ 472 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380401); 473 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x00150402); 474 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b8403); 475 } else { 476 /* same values as above or'ed 0x8 */ 477 RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380409); 478 RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x0015040a); 479 RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b840b); 480 } 481 482 RAL_DEBUG(RAL_DBG_HW, "updating PLCP for %s preamble\n", 483 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "short" : "long"); 484 } 485 486 /* 487 * This function can be called by ieee80211_set_shortslottime(). Refer to 488 * IEEE Std 802.11-1999 pp. 85 to know how these values are computed. 489 */ 490 void 491 rt2560_update_slot(struct ieee80211com *ic, int onoff) 492 { 493 struct rt2560_softc *sc = (struct rt2560_softc *)ic; 494 uint8_t slottime; 495 uint16_t tx_sifs, tx_pifs, tx_difs, eifs; 496 uint32_t tmp; 497 498 /* slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; */ 499 slottime = (onoff ? 9 : 20); 500 501 /* update the MAC slot boundaries */ 502 tx_sifs = RAL_SIFS - RT2560_TXRX_TURNAROUND; 503 tx_pifs = tx_sifs + slottime; 504 tx_difs = tx_sifs + 2 * slottime; 505 eifs = (ic->ic_curmode == IEEE80211_MODE_11B) ? 364 : 60; 506 507 tmp = RAL_READ(sc, RT2560_CSR11); 508 tmp = (tmp & ~0x1f00) | slottime << 8; 509 RAL_WRITE(sc, RT2560_CSR11, tmp); 510 511 tmp = tx_pifs << 16 | tx_sifs; 512 RAL_WRITE(sc, RT2560_CSR18, tmp); 513 514 tmp = eifs << 16 | tx_difs; 515 RAL_WRITE(sc, RT2560_CSR19, tmp); 516 517 RAL_DEBUG(RAL_DBG_HW, "setting slottime to %uus\n", slottime); 518 } 519 520 int 521 ral_dma_region_alloc(struct rt2560_softc *sc, struct dma_region *dr, 522 size_t size, uint_t alloc_flags, uint_t bind_flags) 523 { 524 dev_info_t *dip = sc->sc_dev; 525 int err; 526 527 RAL_DEBUG(RAL_DBG_DMA, "ral_dma_region_alloc() size=%u\n", size); 528 529 err = ddi_dma_alloc_handle(dip, &ral_dma_attr, DDI_DMA_SLEEP, NULL, 530 &dr->dr_hnd); 531 if (err != DDI_SUCCESS) 532 goto fail1; 533 534 err = ddi_dma_mem_alloc(dr->dr_hnd, size, &ral_desc_accattr, 535 alloc_flags, DDI_DMA_SLEEP, NULL, 536 &dr->dr_base, &dr->dr_size, &dr->dr_acc); 537 if (err != DDI_SUCCESS) 538 goto fail2; 539 540 err = ddi_dma_addr_bind_handle(dr->dr_hnd, NULL, 541 dr->dr_base, dr->dr_size, 542 bind_flags, DDI_DMA_SLEEP, NULL, &dr->dr_cookie, &dr->dr_ccnt); 543 if (err != DDI_SUCCESS) 544 goto fail3; 545 546 if (dr->dr_ccnt != 1) { 547 err = DDI_FAILURE; 548 goto fail4; 549 } 550 551 dr->dr_pbase = dr->dr_cookie.dmac_address; 552 RAL_DEBUG(RAL_DBG_DMA, "get physical-base=0x%08x\n", dr->dr_pbase); 553 554 return (DDI_SUCCESS); 555 556 fail4: 557 (void) ddi_dma_unbind_handle(dr->dr_hnd); 558 fail3: 559 ddi_dma_mem_free(&dr->dr_acc); 560 fail2: 561 ddi_dma_free_handle(&dr->dr_hnd); 562 fail1: 563 return (err); 564 } 565 566 /* ARGSUSED */ 567 void 568 ral_dma_region_free(struct rt2560_softc *sc, struct dma_region *dr) 569 { 570 (void) ddi_dma_unbind_handle(dr->dr_hnd); 571 ddi_dma_mem_free(&dr->dr_acc); 572 ddi_dma_free_handle(&dr->dr_hnd); 573 } 574 575 int 576 rt2560_alloc_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring, 577 int count) 578 { 579 int i, err; 580 int size; 581 582 ring->count = count; 583 ring->queued = 0; 584 ring->cur = ring->next = 0; 585 ring->cur_encrypt = ring->next_encrypt = 0; 586 587 ring->data = kmem_zalloc(count * (sizeof (struct rt2560_tx_data)), 588 KM_SLEEP); 589 ring->dr_txbuf = kmem_zalloc(count * (sizeof (struct dma_region)), 590 KM_SLEEP); 591 592 err = ral_dma_region_alloc(sc, &ring->dr_desc, 593 count * (sizeof (struct rt2560_tx_desc)), 594 DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT); 595 596 if (err != DDI_SUCCESS) 597 goto fail1; 598 599 size = roundup(RAL_TXBUF_SIZE, sc->sc_cachelsz); 600 for (i = 0; i < count; i++) { 601 err = ral_dma_region_alloc(sc, &ring->dr_txbuf[i], size, 602 DDI_DMA_STREAMING, DDI_DMA_WRITE | DDI_DMA_STREAMING); 603 if (err != DDI_SUCCESS) { 604 while (i >= 0) { 605 ral_dma_region_free(sc, &ring->dr_txbuf[i]); 606 i--; 607 } 608 goto fail2; 609 } 610 } 611 612 ring->physaddr = LE_32(ring->dr_desc.dr_pbase); 613 ring->desc = (struct rt2560_tx_desc *)ring->dr_desc.dr_base; 614 615 for (i = 0; i < count; i++) { 616 ring->desc[i].physaddr = LE_32(ring->dr_txbuf[i].dr_pbase); 617 ring->data[i].buf = ring->dr_txbuf[i].dr_base; 618 } 619 620 return (DDI_SUCCESS); 621 fail2: 622 ral_dma_region_free(sc, &ring->dr_desc); 623 fail1: 624 return (err); 625 } 626 627 /* ARGSUSED */ 628 void 629 rt2560_reset_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring) 630 { 631 struct rt2560_tx_desc *desc; 632 struct rt2560_tx_data *data; 633 int i; 634 635 for (i = 0; i < ring->count; i++) { 636 desc = &ring->desc[i]; 637 data = &ring->data[i]; 638 639 if (data->ni != NULL) { 640 ieee80211_free_node(data->ni); 641 data->ni = NULL; 642 } 643 644 desc->flags = 0; 645 } 646 647 (void) ddi_dma_sync(ring->dr_desc.dr_hnd, 0, 648 ring->count * sizeof (struct rt2560_tx_desc), DDI_DMA_SYNC_FORDEV); 649 650 ring->queued = 0; 651 ring->cur = ring->next = 0; 652 ring->cur_encrypt = ring->next_encrypt = 0; 653 } 654 655 void 656 rt2560_free_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring) 657 { 658 struct rt2560_tx_data *data; 659 int i; 660 661 ral_dma_region_free(sc, &ring->dr_desc); 662 /* tx buf */ 663 for (i = 0; i < ring->count; i++) { 664 data = &ring->data[i]; 665 if (data->ni != NULL) { 666 ieee80211_free_node(data->ni); 667 data->ni = NULL; 668 } 669 670 ral_dma_region_free(sc, &ring->dr_txbuf[i]); 671 } 672 673 kmem_free(ring->data, ring->count * (sizeof (struct rt2560_tx_data))); 674 kmem_free(ring->dr_txbuf, ring->count * (sizeof (struct dma_region))); 675 } 676 677 void 678 rt2560_ring_hwsetup(struct rt2560_softc *sc) 679 { 680 uint32_t tmp; 681 682 /* setup tx rings */ 683 tmp = ((uint32_t)RT2560_PRIO_RING_COUNT << 24) | 684 RT2560_ATIM_RING_COUNT << 16 | 685 RT2560_TX_RING_COUNT << 8 | 686 RT2560_TX_DESC_SIZE; 687 688 /* rings must be initialized in this exact order */ 689 RAL_WRITE(sc, RT2560_TXCSR2, tmp); 690 RAL_WRITE(sc, RT2560_TXCSR3, sc->txq.physaddr); 691 RAL_WRITE(sc, RT2560_TXCSR5, sc->prioq.physaddr); 692 693 /* setup rx ring */ 694 tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE; 695 696 RAL_WRITE(sc, RT2560_RXCSR1, tmp); 697 RAL_WRITE(sc, RT2560_RXCSR2, sc->rxq.physaddr); 698 } 699 700 int 701 rt2560_alloc_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring, 702 int count) 703 { 704 struct rt2560_rx_desc *desc; 705 struct rt2560_rx_data *data; 706 int i, err; 707 int size; 708 709 ring->count = count; 710 ring->cur = ring->next = 0; 711 ring->cur_decrypt = 0; 712 713 ring->data = kmem_zalloc(count * (sizeof (struct rt2560_rx_data)), 714 KM_SLEEP); 715 ring->dr_rxbuf = kmem_zalloc(count * (sizeof (struct dma_region)), 716 KM_SLEEP); 717 718 err = ral_dma_region_alloc(sc, &ring->dr_desc, 719 count * (sizeof (struct rt2560_rx_desc)), 720 DDI_DMA_CONSISTENT, DDI_DMA_RDWR | DDI_DMA_CONSISTENT); 721 722 if (err != DDI_SUCCESS) 723 goto fail1; 724 725 size = roundup(RAL_RXBUF_SIZE, sc->sc_cachelsz); 726 for (i = 0; i < count; i++) { 727 err = ral_dma_region_alloc(sc, &ring->dr_rxbuf[i], size, 728 DDI_DMA_STREAMING, DDI_DMA_READ | DDI_DMA_STREAMING); 729 if (err != DDI_SUCCESS) { 730 while (i >= 0) { 731 ral_dma_region_free(sc, &ring->dr_rxbuf[i]); 732 i--; 733 } 734 goto fail2; 735 } 736 } 737 738 ring->physaddr = ring->dr_desc.dr_pbase; 739 ring->desc = (struct rt2560_rx_desc *)ring->dr_desc.dr_base; 740 741 for (i = 0; i < count; i++) { 742 desc = &ring->desc[i]; 743 data = &ring->data[i]; 744 745 desc->physaddr = LE_32(ring->dr_rxbuf[i].dr_pbase); 746 desc->flags = LE_32(RT2560_RX_BUSY); 747 748 data->buf = ring->dr_rxbuf[i].dr_base; 749 } 750 751 return (DDI_SUCCESS); 752 fail2: 753 ral_dma_region_free(sc, &ring->dr_desc); 754 fail1: 755 return (err); 756 } 757 758 /* ARGSUSED */ 759 static void 760 rt2560_reset_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring) 761 { 762 int i; 763 764 for (i = 0; i < ring->count; i++) { 765 ring->desc[i].flags = LE_32(RT2560_RX_BUSY); 766 ring->data[i].drop = 0; 767 } 768 769 (void) ddi_dma_sync(ring->dr_desc.dr_hnd, 0, 770 ring->count * sizeof (struct rt2560_rx_desc), 771 DDI_DMA_SYNC_FORKERNEL); 772 773 ring->cur = ring->next = 0; 774 ring->cur_decrypt = 0; 775 } 776 777 static void 778 rt2560_free_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring) 779 { 780 int i; 781 782 ral_dma_region_free(sc, &ring->dr_desc); 783 /* rx buf */ 784 for (i = 0; i < ring->count; i++) 785 ral_dma_region_free(sc, &ring->dr_rxbuf[i]); 786 787 kmem_free(ring->data, ring->count * (sizeof (struct rt2560_rx_data))); 788 kmem_free(ring->dr_rxbuf, ring->count * (sizeof (struct dma_region))); 789 } 790 791 /* ARGSUSED */ 792 static struct ieee80211_node * 793 rt2560_node_alloc(ieee80211com_t *ic) 794 { 795 struct rt2560_node *rn; 796 797 rn = kmem_zalloc(sizeof (struct rt2560_node), KM_SLEEP); 798 return ((rn != NULL) ? &rn->ni : NULL); 799 } 800 801 static void 802 rt2560_node_free(struct ieee80211_node *in) 803 { 804 ieee80211com_t *ic = in->in_ic; 805 806 ic->ic_node_cleanup(in); 807 if (in->in_wpa_ie != NULL) 808 ieee80211_free(in->in_wpa_ie); 809 kmem_free(in, sizeof (struct rt2560_node)); 810 } 811 812 /* 813 * This function is called periodically (every 200ms) during scanning to 814 * switch from one channel to another. 815 */ 816 static void 817 rt2560_next_scan(void *arg) 818 { 819 struct rt2560_softc *sc = arg; 820 struct ieee80211com *ic = &sc->sc_ic; 821 822 if (ic->ic_state == IEEE80211_S_SCAN) 823 (void) ieee80211_next_scan(ic); 824 } 825 826 /* 827 * This function is called for each node present in the node station table. 828 */ 829 /* ARGSUSED */ 830 static void 831 rt2560_iter_func(void *arg, struct ieee80211_node *ni) 832 { 833 struct rt2560_node *rn = (struct rt2560_node *)ni; 834 835 ral_rssadapt_updatestats(&rn->rssadapt); 836 } 837 838 /* 839 * This function is called periodically (every 100ms) in RUN state to update 840 * the rate adaptation statistics. 841 */ 842 static void 843 rt2560_update_rssadapt(void *arg) 844 { 845 struct rt2560_softc *sc = arg; 846 struct ieee80211com *ic = &sc->sc_ic; 847 848 ieee80211_iterate_nodes(&ic->ic_sta, rt2560_iter_func, arg); 849 sc->sc_rssadapt_id = timeout(rt2560_update_rssadapt, (void *)sc, 850 drv_usectohz(100 * 1000)); 851 } 852 853 static void 854 rt2560_statedog(void *arg) 855 { 856 struct rt2560_softc *sc = arg; 857 struct ieee80211com *ic = &sc->sc_ic; 858 enum ieee80211_state state; 859 860 RAL_LOCK(sc); 861 862 RAL_DEBUG(RAL_DBG_MSG, "rt2560_statedog(...)\n"); 863 864 sc->sc_state_id = 0; 865 state = ic->ic_state; 866 ic->ic_state = sc->sc_ostate; 867 868 RAL_UNLOCK(sc); 869 870 ieee80211_new_state(ic, state, -1); 871 872 } 873 874 static int 875 rt2560_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 876 { 877 struct rt2560_softc *sc = (struct rt2560_softc *)ic; 878 enum ieee80211_state ostate; 879 struct ieee80211_node *ni; 880 int err; 881 882 RAL_LOCK(sc); 883 884 ostate = ic->ic_state; 885 sc->sc_ostate = ostate; 886 887 if (sc->sc_scan_id != 0) { 888 (void) untimeout(sc->sc_scan_id); 889 sc->sc_scan_id = 0; 890 } 891 892 if (sc->sc_rssadapt_id != 0) { 893 (void) untimeout(sc->sc_rssadapt_id); 894 sc->sc_rssadapt_id = 0; 895 } 896 897 if (sc->sc_state_id != 0) { 898 (void) untimeout(sc->sc_state_id); 899 sc->sc_state_id = 0; 900 } 901 902 switch (nstate) { 903 case IEEE80211_S_INIT: 904 if (ostate == IEEE80211_S_RUN) { 905 /* abort TSF synchronization */ 906 RAL_WRITE(sc, RT2560_CSR14, 0); 907 /* turn association led off */ 908 rt2560_update_led(sc, 0, 0); 909 } 910 break; 911 912 case IEEE80211_S_SCAN: 913 rt2560_set_chan(sc, ic->ic_curchan); 914 sc->sc_scan_id = timeout(rt2560_next_scan, (void *)sc, 915 drv_usectohz(sc->dwelltime * 1000)); 916 break; 917 918 case IEEE80211_S_AUTH: 919 RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_AUTH ...\n"); 920 rt2560_set_chan(sc, ic->ic_curchan); 921 break; 922 923 case IEEE80211_S_ASSOC: 924 RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_ASSOC ...\n"); 925 rt2560_set_chan(sc, ic->ic_curchan); 926 927 drv_usecwait(10 * 1000); /* dlink */ 928 sc->sc_state_id = timeout(rt2560_statedog, (void *)sc, 929 drv_usectohz(300 * 1000)); /* ap7-3 */ 930 break; 931 932 case IEEE80211_S_RUN: 933 RAL_DEBUG(RAL_DBG_STATE, "-> IEEE80211_S_RUN ...\n"); 934 rt2560_set_chan(sc, ic->ic_curchan); 935 936 ni = ic->ic_bss; 937 938 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 939 rt2560_update_plcp(sc); 940 rt2560_set_basicrates(sc); 941 rt2560_set_bssid(sc, ni->in_bssid); 942 } 943 944 /* turn assocation led on */ 945 rt2560_update_led(sc, 1, 0); 946 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 947 sc->sc_rssadapt_id = timeout(rt2560_update_rssadapt, 948 (void *)sc, drv_usectohz(100 * 1000)); 949 rt2560_enable_tsf_sync(sc); 950 } 951 break; 952 } 953 954 RAL_UNLOCK(sc); 955 956 err = sc->sc_newstate(ic, nstate, arg); 957 /* 958 * Finally, start any timers. 959 */ 960 if (nstate == IEEE80211_S_RUN) 961 ieee80211_start_watchdog(ic, 1); 962 963 return (err); 964 } 965 966 /* 967 * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or 968 * 93C66). 969 */ 970 static uint16_t 971 rt2560_eeprom_read(struct rt2560_softc *sc, uint8_t addr) 972 { 973 uint32_t tmp; 974 uint16_t val; 975 int n; 976 977 /* clock C once before the first command */ 978 RT2560_EEPROM_CTL(sc, 0); 979 980 RT2560_EEPROM_CTL(sc, RT2560_S); 981 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 982 RT2560_EEPROM_CTL(sc, RT2560_S); 983 984 /* write start bit (1) */ 985 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D); 986 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C); 987 988 /* write READ opcode (10) */ 989 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D); 990 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C); 991 RT2560_EEPROM_CTL(sc, RT2560_S); 992 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 993 994 /* write address (A5-A0 or A7-A0) */ 995 n = (RAL_READ(sc, RT2560_CSR21) & RT2560_93C46) ? 5 : 7; 996 for (; n >= 0; n--) { 997 RT2560_EEPROM_CTL(sc, RT2560_S | 998 (((addr >> n) & 1) << RT2560_SHIFT_D)); 999 RT2560_EEPROM_CTL(sc, RT2560_S | 1000 (((addr >> n) & 1) << RT2560_SHIFT_D) | RT2560_C); 1001 } 1002 1003 RT2560_EEPROM_CTL(sc, RT2560_S); 1004 1005 /* read data Q15-Q0 */ 1006 val = 0; 1007 for (n = 15; n >= 0; n--) { 1008 RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); 1009 tmp = RAL_READ(sc, RT2560_CSR21); 1010 val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n; 1011 RT2560_EEPROM_CTL(sc, RT2560_S); 1012 } 1013 1014 RT2560_EEPROM_CTL(sc, 0); 1015 1016 /* clear Chip Select and clock C */ 1017 RT2560_EEPROM_CTL(sc, RT2560_S); 1018 RT2560_EEPROM_CTL(sc, 0); 1019 RT2560_EEPROM_CTL(sc, RT2560_C); 1020 1021 return (val); 1022 } 1023 1024 static void 1025 rt2560_tx_intr(struct rt2560_softc *sc) 1026 { 1027 struct ieee80211com *ic = &sc->sc_ic; 1028 struct rt2560_tx_desc *desc; 1029 struct rt2560_tx_data *data; 1030 struct rt2560_node *rn; 1031 1032 struct dma_region *dr; 1033 int count; 1034 1035 dr = &sc->txq.dr_desc; 1036 count = sc->txq.count; 1037 1038 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1039 DDI_DMA_SYNC_FORKERNEL); 1040 1041 mutex_enter(&sc->txq.tx_lock); 1042 1043 for (;;) { 1044 desc = &sc->txq.desc[sc->txq.next]; 1045 data = &sc->txq.data[sc->txq.next]; 1046 1047 if ((LE_32(desc->flags) & RT2560_TX_BUSY) || 1048 (LE_32(desc->flags) & RT2560_TX_CIPHER_BUSY) || 1049 !(LE_32(desc->flags) & RT2560_TX_VALID)) 1050 break; 1051 1052 rn = (struct rt2560_node *)data->ni; 1053 1054 switch (LE_32(desc->flags) & RT2560_TX_RESULT_MASK) { 1055 case RT2560_TX_SUCCESS: 1056 RAL_DEBUG(RAL_DBG_INTR, "data frame sent success\n"); 1057 if (data->id.id_node != NULL) { 1058 ral_rssadapt_raise_rate(ic, &rn->rssadapt, 1059 &data->id); 1060 } 1061 break; 1062 1063 case RT2560_TX_SUCCESS_RETRY: 1064 RAL_DEBUG(RAL_DBG_INTR, 1065 "data frame sent after %u retries\n", 1066 (LE_32(desc->flags) >> 5) & 0x7); 1067 sc->sc_tx_retries++; 1068 break; 1069 1070 case RT2560_TX_FAIL_RETRY: 1071 RAL_DEBUG(RAL_DBG_INTR, 1072 "sending data frame failed (too much retries)\n"); 1073 if (data->id.id_node != NULL) { 1074 ral_rssadapt_lower_rate(ic, data->ni, 1075 &rn->rssadapt, &data->id); 1076 } 1077 break; 1078 1079 case RT2560_TX_FAIL_INVALID: 1080 case RT2560_TX_FAIL_OTHER: 1081 default: 1082 RAL_DEBUG(RAL_DBG_INTR, "sending data frame failed " 1083 "0x%08x\n", LE_32(desc->flags)); 1084 break; 1085 } 1086 1087 ieee80211_free_node(data->ni); 1088 data->ni = NULL; 1089 1090 /* descriptor is no longer valid */ 1091 desc->flags &= ~LE_32(RT2560_TX_VALID); 1092 1093 RAL_DEBUG(RAL_DBG_INTR, "tx done idx=%u\n", sc->txq.next); 1094 1095 sc->txq.queued--; 1096 sc->txq.next = (sc->txq.next + 1) % RT2560_TX_RING_COUNT; 1097 1098 if (sc->sc_need_sched && 1099 sc->txq.queued < (RT2560_TX_RING_COUNT - 32)) { 1100 sc->sc_need_sched = 0; 1101 mac_tx_update(ic->ic_mach); 1102 } 1103 } 1104 1105 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1106 DDI_DMA_SYNC_FORDEV); 1107 1108 sc->sc_tx_timer = 0; 1109 mutex_exit(&sc->txq.tx_lock); 1110 } 1111 1112 static void 1113 rt2560_prio_intr(struct rt2560_softc *sc) 1114 { 1115 struct rt2560_tx_desc *desc; 1116 struct rt2560_tx_data *data; 1117 1118 struct dma_region *dr; 1119 int count; 1120 1121 dr = &sc->prioq.dr_desc; 1122 count = sc->prioq.count; 1123 1124 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1125 DDI_DMA_SYNC_FORKERNEL); 1126 1127 mutex_enter(&sc->prioq.tx_lock); 1128 1129 for (;;) { 1130 desc = &sc->prioq.desc[sc->prioq.next]; 1131 data = &sc->prioq.data[sc->prioq.next]; 1132 1133 if ((LE_32(desc->flags) & RT2560_TX_BUSY) || 1134 !(LE_32(desc->flags) & RT2560_TX_VALID)) 1135 break; 1136 1137 switch (LE_32(desc->flags) & RT2560_TX_RESULT_MASK) { 1138 case RT2560_TX_SUCCESS: 1139 RAL_DEBUG(RAL_DBG_INTR, "mgt frame sent success\n"); 1140 break; 1141 1142 case RT2560_TX_SUCCESS_RETRY: 1143 RAL_DEBUG(RAL_DBG_INTR, 1144 "mgt frame sent after %u retries\n", 1145 (LE_32(desc->flags) >> 5) & 0x7); 1146 break; 1147 1148 case RT2560_TX_FAIL_RETRY: 1149 RAL_DEBUG(RAL_DBG_INTR, 1150 "sending mgt frame failed (too much " "retries)\n"); 1151 break; 1152 1153 case RT2560_TX_FAIL_INVALID: 1154 case RT2560_TX_FAIL_OTHER: 1155 default: 1156 RAL_DEBUG(RAL_DBG_INTR, "sending mgt frame failed " 1157 "0x%08x\n", LE_32(desc->flags)); 1158 } 1159 1160 ieee80211_free_node(data->ni); 1161 data->ni = NULL; 1162 1163 /* descriptor is no longer valid */ 1164 desc->flags &= ~LE_32(RT2560_TX_VALID); 1165 1166 RAL_DEBUG(RAL_DBG_INTR, "prio done idx=%u\n", sc->prioq.next); 1167 1168 sc->prioq.queued--; 1169 sc->prioq.next = (sc->prioq.next + 1) % RT2560_PRIO_RING_COUNT; 1170 } 1171 1172 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1173 DDI_DMA_SYNC_FORDEV); 1174 1175 sc->sc_tx_timer = 0; 1176 mutex_exit(&sc->prioq.tx_lock); 1177 } 1178 1179 /* 1180 * Some frames were received. Pass them to the hardware cipher engine before 1181 * sending them to the 802.11 layer. 1182 */ 1183 void 1184 rt2560_rx_intr(struct rt2560_softc *sc) 1185 { 1186 struct ieee80211com *ic = &sc->sc_ic; 1187 struct rt2560_rx_desc *desc; 1188 struct rt2560_rx_data *data; 1189 struct ieee80211_frame *wh; 1190 struct ieee80211_node *ni; 1191 struct rt2560_node *rn; 1192 1193 mblk_t *m; 1194 uint32_t len; 1195 char *rxbuf; 1196 1197 struct dma_region *dr, *dr_bf; 1198 int count; 1199 1200 dr = &sc->rxq.dr_desc; 1201 count = sc->rxq.count; 1202 1203 mutex_enter(&sc->rxq.rx_lock); 1204 1205 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_RX_DESC_SIZE, 1206 DDI_DMA_SYNC_FORKERNEL); 1207 1208 for (;;) { 1209 desc = &sc->rxq.desc[sc->rxq.cur]; 1210 data = &sc->rxq.data[sc->rxq.cur]; 1211 1212 if ((LE_32(desc->flags) & RT2560_RX_BUSY) || 1213 (LE_32(desc->flags) & RT2560_RX_CIPHER_BUSY)) 1214 break; 1215 1216 data->drop = 0; 1217 1218 if ((LE_32(desc->flags) & RT2560_RX_PHY_ERROR) || 1219 (LE_32(desc->flags) & RT2560_RX_CRC_ERROR)) { 1220 /* 1221 * This should not happen since we did not request 1222 * to receive those frames when we filled RXCSR0. 1223 */ 1224 RAL_DEBUG(RAL_DBG_RX, "PHY or CRC error flags 0x%08x\n", 1225 LE_32(desc->flags)); 1226 data->drop = 1; 1227 } 1228 1229 if (((LE_32(desc->flags) >> 16) & 0xfff) > RAL_RXBUF_SIZE) { 1230 RAL_DEBUG(RAL_DBG_RX, "bad length\n"); 1231 data->drop = 1; 1232 } 1233 1234 if (data->drop) { 1235 sc->sc_rx_err++; 1236 goto skip; 1237 } 1238 1239 rxbuf = data->buf; 1240 len = (LE_32(desc->flags) >> 16) & 0xfff; 1241 1242 if ((len < sizeof (struct ieee80211_frame_min)) || 1243 (len > RAL_RXBUF_SIZE)) { 1244 RAL_DEBUG(RAL_DBG_RX, "bad frame length=%u\n", len); 1245 sc->sc_rx_err++; 1246 goto skip; 1247 } 1248 1249 if ((m = allocb(len, BPRI_MED)) == NULL) { 1250 RAL_DEBUG(RAL_DBG_RX, "rt2560_rx_intr():" 1251 " allocate mblk failed.\n"); 1252 sc->sc_rx_nobuf++; 1253 goto skip; 1254 } 1255 1256 dr_bf = &sc->rxq.dr_rxbuf[sc->rxq.cur]; 1257 (void) ddi_dma_sync(dr_bf->dr_hnd, 0, dr_bf->dr_size, 1258 DDI_DMA_SYNC_FORCPU); 1259 1260 bcopy(rxbuf, m->b_rptr, len); 1261 m->b_wptr += len; 1262 1263 wh = (struct ieee80211_frame *)m->b_rptr; 1264 ni = ieee80211_find_rxnode(ic, wh); 1265 1266 /* give rssi to the rate adatation algorithm */ 1267 rn = (struct rt2560_node *)ni; 1268 ral_rssadapt_input(ic, ni, &rn->rssadapt, desc->rssi); 1269 1270 /* send the frame to the 802.11 layer */ 1271 (void) ieee80211_input(ic, m, ni, desc->rssi, 0); 1272 1273 /* node is no longer needed */ 1274 ieee80211_free_node(ni); 1275 1276 skip: desc->flags = LE_32(RT2560_RX_BUSY); 1277 RAL_DEBUG(RAL_DBG_RX, "rx done idx=%u\n", sc->rxq.cur); 1278 1279 sc->rxq.cur = (sc->rxq.cur + 1) % RT2560_RX_RING_COUNT; 1280 } 1281 mutex_exit(&sc->rxq.rx_lock); 1282 1283 (void) ddi_dma_sync(dr->dr_hnd, 0, count * RT2560_TX_DESC_SIZE, 1284 DDI_DMA_SYNC_FORDEV); 1285 } 1286 1287 uint_t 1288 ral_softint_handler(caddr_t data) 1289 { 1290 struct rt2560_softc *sc = (struct rt2560_softc *)data; 1291 1292 /* 1293 * Check if the soft interrupt is triggered by another 1294 * driver at the same level. 1295 */ 1296 RAL_LOCK(sc); 1297 if (sc->sc_rx_pend) { 1298 sc->sc_rx_pend = 0; 1299 RAL_UNLOCK(sc); 1300 rt2560_rx_intr((struct rt2560_softc *)data); 1301 return (DDI_INTR_CLAIMED); 1302 } 1303 RAL_UNLOCK(sc); 1304 return (DDI_INTR_UNCLAIMED); 1305 } 1306 1307 /* 1308 * Return the expected ack rate for a frame transmitted at rate `rate'. 1309 * XXX: this should depend on the destination node basic rate set. 1310 */ 1311 static int 1312 rt2560_ack_rate(struct ieee80211com *ic, int rate) 1313 { 1314 switch (rate) { 1315 /* CCK rates */ 1316 case 2: 1317 return (2); 1318 case 4: 1319 case 11: 1320 case 22: 1321 return ((ic->ic_curmode == IEEE80211_MODE_11B) ? 4 : rate); 1322 1323 /* OFDM rates */ 1324 case 12: 1325 case 18: 1326 return (12); 1327 case 24: 1328 case 36: 1329 return (24); 1330 case 48: 1331 case 72: 1332 case 96: 1333 case 108: 1334 return (48); 1335 } 1336 1337 /* default to 1Mbps */ 1338 return (2); 1339 } 1340 1341 /* 1342 * Compute the duration (in us) needed to transmit `len' bytes at rate `rate'. 1343 * The function automatically determines the operating mode depending on the 1344 * given rate. `flags' indicates whether short preamble is in use or not. 1345 */ 1346 static uint16_t 1347 rt2560_txtime(int len, int rate, uint32_t flags) 1348 { 1349 uint16_t txtime; 1350 1351 if (RAL_RATE_IS_OFDM(rate)) { 1352 /* IEEE Std 802.11a-1999, pp. 37 */ 1353 txtime = (8 + 4 * len + 3 + rate - 1) / rate; 1354 txtime = 16 + 4 + 4 * txtime + 6; 1355 } else { 1356 /* IEEE Std 802.11b-1999, pp. 28 */ 1357 txtime = (16 * len + rate - 1) / rate; 1358 if (rate != 2 && (flags & IEEE80211_F_SHPREAMBLE)) 1359 txtime += 72 + 24; 1360 else 1361 txtime += 144 + 48; 1362 } 1363 1364 return (txtime); 1365 } 1366 1367 static uint8_t 1368 rt2560_plcp_signal(int rate) 1369 { 1370 switch (rate) { 1371 /* CCK rates (returned values are device-dependent) */ 1372 case 2: return (0x0); 1373 case 4: return (0x1); 1374 case 11: return (0x2); 1375 case 22: return (0x3); 1376 1377 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 1378 case 12: return (0xb); 1379 case 18: return (0xf); 1380 case 24: return (0xa); 1381 case 36: return (0xe); 1382 case 48: return (0x9); 1383 case 72: return (0xd); 1384 case 96: return (0x8); 1385 case 108: return (0xc); 1386 1387 /* unsupported rates (should not get there) */ 1388 default: return (0xff); 1389 } 1390 } 1391 1392 void 1393 rt2560_setup_tx_desc(struct rt2560_softc *sc, struct rt2560_tx_desc *desc, 1394 uint32_t flags, int len, int rate, int encrypt) 1395 { 1396 struct ieee80211com *ic = &sc->sc_ic; 1397 uint16_t plcp_length; 1398 int remainder; 1399 1400 desc->flags = LE_32(flags); 1401 desc->flags |= LE_32(len << 16); 1402 desc->flags |= encrypt ? LE_32(RT2560_TX_CIPHER_BUSY) : 1403 LE_32(RT2560_TX_BUSY | RT2560_TX_VALID); 1404 1405 desc->wme = LE_16( 1406 RT2560_AIFSN(2) | 1407 RT2560_LOGCWMIN(3) | 1408 RT2560_LOGCWMAX(8)); 1409 1410 /* setup PLCP fields */ 1411 desc->plcp_signal = rt2560_plcp_signal(rate); 1412 desc->plcp_service = 4; 1413 1414 len += IEEE80211_CRC_LEN; 1415 if (RAL_RATE_IS_OFDM(rate)) { 1416 desc->flags |= LE_32(RT2560_TX_OFDM); 1417 1418 plcp_length = len & 0xfff; 1419 desc->plcp_length_hi = plcp_length >> 6; 1420 desc->plcp_length_lo = plcp_length & 0x3f; 1421 } else { 1422 plcp_length = (16 * len + rate - 1) / rate; 1423 if (rate == 22) { 1424 remainder = (16 * len) % 22; 1425 if (remainder != 0 && remainder < 7) 1426 desc->plcp_service |= RT2560_PLCP_LENGEXT; 1427 } 1428 desc->plcp_length_hi = plcp_length >> 8; 1429 desc->plcp_length_lo = plcp_length & 0xff; 1430 1431 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1432 desc->plcp_signal |= 0x08; 1433 } 1434 } 1435 1436 /* ARGSUSED */ 1437 int 1438 rt2560_mgmt_send(ieee80211com_t *ic, mblk_t *mp, uint8_t type) 1439 { 1440 struct rt2560_softc *sc = (struct rt2560_softc *)ic; 1441 struct rt2560_tx_desc *desc; 1442 struct rt2560_tx_data *data; 1443 struct ieee80211_frame *wh; 1444 uint16_t dur; 1445 uint32_t flags = 0; 1446 int rate, err = DDI_SUCCESS; 1447 1448 int off, pktlen, mblen; 1449 caddr_t dest; 1450 mblk_t *m, *m0; 1451 1452 struct dma_region *dr; 1453 uint32_t idx; 1454 struct ieee80211_node *ni; 1455 struct ieee80211_key *k; 1456 1457 mutex_enter(&sc->prioq.tx_lock); 1458 1459 if (sc->prioq.queued >= RT2560_PRIO_RING_COUNT) { 1460 err = ENOMEM; 1461 sc->sc_tx_nobuf++; 1462 goto fail1; 1463 } 1464 1465 m = allocb(msgdsize(mp) + 32, BPRI_MED); 1466 if (m == NULL) { 1467 RAL_DEBUG(RAL_DBG_TX, "rt2560_mgmt_send: can't alloc mblk.\n"); 1468 err = DDI_FAILURE; 1469 goto fail1; 1470 } 1471 1472 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) { 1473 mblen = MBLKL(m0); 1474 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen); 1475 off += mblen; 1476 } 1477 m->b_wptr += off; 1478 1479 wh = (struct ieee80211_frame *)m->b_rptr; 1480 ni = ieee80211_find_txnode(ic, wh->i_addr1); 1481 1482 if (ni == NULL) { 1483 err = DDI_FAILURE; 1484 sc->sc_tx_err++; 1485 goto fail2; 1486 } 1487 1488 /* to support shared_key auth mode */ 1489 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1490 k = ieee80211_crypto_encap(ic, m); 1491 if (k == NULL) { 1492 err = DDI_FAILURE; 1493 sc->sc_tx_err++; 1494 goto fail3; 1495 } 1496 /* packet header may have moved, reset our local pointer */ 1497 wh = (struct ieee80211_frame *)m->b_rptr; 1498 } 1499 1500 desc = &sc->prioq.desc[sc->prioq.cur]; 1501 data = &sc->prioq.data[sc->prioq.cur]; 1502 1503 rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) ? 12 : 2; 1504 data->ni = ieee80211_ref_node(ni); 1505 1506 pktlen = msgdsize(m); 1507 dest = data->buf; 1508 bcopy(m->b_rptr, dest, pktlen); 1509 1510 wh = (struct ieee80211_frame *)m->b_rptr; 1511 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1512 flags |= RT2560_TX_ACK; 1513 1514 dur = rt2560_txtime(RAL_ACK_SIZE, rate, ic->ic_flags) + 1515 RAL_SIFS; 1516 *(uint16_t *)wh->i_dur = LE_16(dur); 1517 1518 /* tell hardware to add timestamp for probe responses */ 1519 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1520 IEEE80211_FC0_TYPE_MGT && 1521 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1522 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1523 flags |= RT2560_TX_TIMESTAMP; 1524 } 1525 1526 rt2560_setup_tx_desc(sc, desc, flags, pktlen, rate, 0); 1527 1528 idx = sc->prioq.cur; 1529 1530 dr = &sc->prioq.dr_txbuf[idx]; 1531 (void) ddi_dma_sync(dr->dr_hnd, 0, RAL_TXBUF_SIZE, DDI_DMA_SYNC_FORDEV); 1532 1533 dr = &sc->prioq.dr_desc; 1534 (void) ddi_dma_sync(dr->dr_hnd, idx * RT2560_TX_DESC_SIZE, 1535 RT2560_TX_DESC_SIZE, DDI_DMA_SYNC_FORDEV); 1536 1537 RAL_DEBUG(RAL_DBG_MGMT, "sending mgt frame len=%u idx=%u rate=%u\n", 1538 pktlen, sc->prioq.cur, rate); 1539 1540 /* kick prio */ 1541 sc->prioq.queued++; /* IF > RT2560_PRIO_RING_COUNT? FULL */ 1542 sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT; 1543 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO); 1544 1545 sc->sc_tx_timer = 5; 1546 1547 ic->ic_stats.is_tx_frags++; 1548 ic->ic_stats.is_tx_bytes += pktlen; 1549 1550 fail3: 1551 ieee80211_free_node(ni); 1552 fail2: 1553 freemsg(m); 1554 fail1: 1555 freemsg(mp); 1556 mutex_exit(&sc->prioq.tx_lock); 1557 1558 return (err); 1559 } 1560 1561 static int 1562 rt2560_send(ieee80211com_t *ic, mblk_t *mp) 1563 { 1564 struct rt2560_softc *sc = (struct rt2560_softc *)ic; 1565 struct rt2560_tx_desc *desc; 1566 struct rt2560_tx_data *data; 1567 struct rt2560_node *rn; 1568 struct ieee80211_rateset *rs; 1569 struct ieee80211_frame *wh; 1570 struct ieee80211_key *k; 1571 uint16_t dur; 1572 uint32_t flags = 0; 1573 int rate, err = DDI_SUCCESS; 1574 1575 struct ieee80211_node *ni; 1576 mblk_t *m, *m0; 1577 int off, mblen, pktlen; 1578 caddr_t dest; 1579 1580 struct dma_region *dr; 1581 uint32_t idx; 1582 1583 mutex_enter(&sc->txq.tx_lock); 1584 1585 if (sc->txq.queued >= RT2560_TX_RING_COUNT - 1) { 1586 RAL_DEBUG(RAL_DBG_TX, "ral: rt2560_tx_data(): " 1587 "no TX DMA buffer available!\n"); 1588 sc->sc_need_sched = 1; 1589 sc->sc_tx_nobuf++; 1590 err = ENOMEM; 1591 goto fail1; 1592 } 1593 1594 m = allocb(msgdsize(mp) + 32, BPRI_MED); 1595 if (m == NULL) { 1596 RAL_DEBUG(RAL_DBG_TX, "rt2560_xmit(): can't alloc mblk.\n"); 1597 err = DDI_FAILURE; 1598 goto fail1; 1599 } 1600 1601 for (off = 0, m0 = mp; m0 != NULL; m0 = m0->b_cont) { 1602 mblen = MBLKL(m0); 1603 (void) memcpy(m->b_rptr + off, m0->b_rptr, mblen); 1604 off += mblen; 1605 } 1606 m->b_wptr += off; 1607 1608 wh = (struct ieee80211_frame *)m->b_rptr; 1609 ni = ieee80211_find_txnode(ic, wh->i_addr1); 1610 1611 if (ni == NULL) { 1612 err = DDI_FAILURE; 1613 sc->sc_tx_err++; 1614 goto fail2; 1615 } 1616 1617 (void) ieee80211_encap(ic, m, ni); 1618 1619 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1620 k = ieee80211_crypto_encap(ic, m); 1621 if (k == NULL) { 1622 sc->sc_tx_err++; 1623 err = DDI_FAILURE; 1624 goto fail3; 1625 } 1626 /* packet header may have moved, reset our local pointer */ 1627 wh = (struct ieee80211_frame *)m->b_rptr; 1628 } 1629 1630 /* 1631 * RTS/CTS exchange ignore, since the max packet will less than 1632 * the rtsthreshold (2346) 1633 * Unnecessary codes deleted. 1634 */ 1635 1636 data = &sc->txq.data[sc->txq.cur]; 1637 desc = &sc->txq.desc[sc->txq.cur]; 1638 1639 data->ni = ieee80211_ref_node(ni); 1640 1641 pktlen = msgdsize(m); 1642 dest = data->buf; 1643 bcopy(m->b_rptr, dest, pktlen); 1644 1645 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) { 1646 rs = &ic->ic_sup_rates[ic->ic_curmode]; 1647 rate = rs->ir_rates[ic->ic_fixed_rate]; 1648 } else { 1649 rs = &ni->in_rates; 1650 rn = (struct rt2560_node *)ni; 1651 ni->in_txrate = ral_rssadapt_choose(&rn->rssadapt, rs, wh, 1652 pktlen, NULL, 0); 1653 rate = rs->ir_rates[ni->in_txrate]; 1654 } 1655 1656 rate &= IEEE80211_RATE_VAL; 1657 if (rate <= 0) { 1658 rate = 2; /* basic rate */ 1659 } 1660 1661 /* remember link conditions for rate adaptation algorithm */ 1662 if (ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) { 1663 data->id.id_len = pktlen; 1664 data->id.id_rateidx = ni->in_txrate; 1665 data->id.id_node = ni; 1666 data->id.id_rssi = ni->in_rssi; 1667 } else 1668 data->id.id_node = NULL; 1669 1670 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1671 flags |= RT2560_TX_ACK; 1672 1673 dur = rt2560_txtime(RAL_ACK_SIZE, rt2560_ack_rate(ic, rate), 1674 ic->ic_flags) + RAL_SIFS; 1675 *(uint16_t *)wh->i_dur = LE_16(dur); 1676 } 1677 1678 /* flags |= RT2560_TX_CIPHER_NONE; */ 1679 rt2560_setup_tx_desc(sc, desc, flags, pktlen, rate, 0); 1680 1681 idx = sc->txq.cur; 1682 1683 dr = &sc->txq.dr_txbuf[idx]; 1684 (void) ddi_dma_sync(dr->dr_hnd, 0, RAL_TXBUF_SIZE, DDI_DMA_SYNC_FORDEV); 1685 1686 dr = &sc->txq.dr_desc; 1687 (void) ddi_dma_sync(dr->dr_hnd, idx * RT2560_TX_DESC_SIZE, 1688 RT2560_TX_DESC_SIZE, DDI_DMA_SYNC_FORDEV); 1689 1690 RAL_DEBUG(RAL_DBG_TX, "sending data frame len=%u idx=%u rate=%u\n", 1691 pktlen, sc->txq.cur, rate); 1692 1693 /* kick tx */ 1694 sc->txq.queued++; 1695 sc->txq.cur = (sc->txq.cur + 1) % RT2560_TX_RING_COUNT; 1696 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_TX); 1697 1698 sc->sc_tx_timer = 5; 1699 1700 ic->ic_stats.is_tx_frags++; 1701 ic->ic_stats.is_tx_bytes += pktlen; 1702 1703 freemsg(mp); 1704 fail3: 1705 ieee80211_free_node(ni); 1706 fail2: 1707 freemsg(m); 1708 fail1: 1709 mutex_exit(&sc->txq.tx_lock); 1710 return (err); 1711 } 1712 1713 static mblk_t * 1714 rt2560_m_tx(void *arg, mblk_t *mp) 1715 { 1716 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 1717 struct ieee80211com *ic = &sc->sc_ic; 1718 mblk_t *next; 1719 1720 /* 1721 * No data frames go out unless we're associated; this 1722 * should not happen as the 802.11 layer does not enable 1723 * the xmit queue until we enter the RUN state. 1724 */ 1725 if (ic->ic_state != IEEE80211_S_RUN) { 1726 RAL_DEBUG(RAL_DBG_TX, "ral: rt2560_tx_data(): " 1727 "discard, state %u\n", ic->ic_state); 1728 freemsgchain(mp); 1729 return (NULL); 1730 } 1731 1732 while (mp != NULL) { 1733 next = mp->b_next; 1734 mp->b_next = NULL; 1735 if (rt2560_send(ic, mp) != DDI_SUCCESS) { 1736 mp->b_next = next; 1737 freemsgchain(mp); 1738 return (NULL); 1739 } 1740 mp = next; 1741 } 1742 return (mp); 1743 } 1744 1745 static void 1746 rt2560_set_macaddr(struct rt2560_softc *sc, uint8_t *addr) 1747 { 1748 uint32_t tmp; 1749 1750 tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; 1751 RAL_WRITE(sc, RT2560_CSR3, tmp); 1752 1753 tmp = addr[4] | addr[5] << 8; 1754 RAL_WRITE(sc, RT2560_CSR4, tmp); 1755 1756 RAL_DEBUG(RAL_DBG_HW, 1757 "setting MAC address to " MACSTR "\n", MAC2STR(addr)); 1758 } 1759 1760 static void 1761 rt2560_get_macaddr(struct rt2560_softc *sc, uint8_t *addr) 1762 { 1763 uint32_t tmp; 1764 1765 tmp = RAL_READ(sc, RT2560_CSR3); 1766 addr[0] = tmp & 0xff; 1767 addr[1] = (tmp >> 8) & 0xff; 1768 addr[2] = (tmp >> 16) & 0xff; 1769 addr[3] = (tmp >> 24); 1770 1771 tmp = RAL_READ(sc, RT2560_CSR4); 1772 addr[4] = tmp & 0xff; 1773 addr[5] = (tmp >> 8) & 0xff; 1774 } 1775 1776 static void 1777 rt2560_update_promisc(struct rt2560_softc *sc) 1778 { 1779 uint32_t tmp; 1780 1781 tmp = RAL_READ(sc, RT2560_RXCSR0); 1782 tmp &= ~RT2560_DROP_NOT_TO_ME; 1783 if (!(sc->sc_rcr & RAL_RCR_PROMISC)) 1784 tmp |= RT2560_DROP_NOT_TO_ME; 1785 1786 RAL_WRITE(sc, RT2560_RXCSR0, tmp); 1787 RAL_DEBUG(RAL_DBG_HW, "%s promiscuous mode\n", 1788 (sc->sc_rcr & RAL_RCR_PROMISC) ? "entering" : "leaving"); 1789 } 1790 1791 static const char * 1792 rt2560_get_rf(int rev) 1793 { 1794 switch (rev) { 1795 case RT2560_RF_2522: return ("RT2522"); 1796 case RT2560_RF_2523: return ("RT2523"); 1797 case RT2560_RF_2524: return ("RT2524"); 1798 case RT2560_RF_2525: return ("RT2525"); 1799 case RT2560_RF_2525E: return ("RT2525e"); 1800 case RT2560_RF_2526: return ("RT2526"); 1801 case RT2560_RF_5222: return ("RT5222"); 1802 default: return ("unknown"); 1803 } 1804 } 1805 1806 static void 1807 rt2560_read_eeprom(struct rt2560_softc *sc) 1808 { 1809 uint16_t val; 1810 int i; 1811 1812 val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0); 1813 sc->rf_rev = (val >> 11) & 0x7; 1814 sc->hw_radio = (val >> 10) & 0x1; 1815 sc->led_mode = (val >> 6) & 0x7; 1816 sc->rx_ant = (val >> 4) & 0x3; 1817 sc->tx_ant = (val >> 2) & 0x3; 1818 sc->nb_ant = val & 0x3; 1819 1820 /* read default values for BBP registers */ 1821 for (i = 0; i < 16; i++) { 1822 val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i); 1823 sc->bbp_prom[i].reg = val >> 8; 1824 sc->bbp_prom[i].val = val & 0xff; 1825 } 1826 1827 /* read Tx power for all b/g channels */ 1828 for (i = 0; i < 14 / 2; i++) { 1829 val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i); 1830 sc->txpow[i * 2] = val >> 8; 1831 sc->txpow[i * 2 + 1] = val & 0xff; 1832 } 1833 } 1834 1835 static int 1836 rt2560_bbp_init(struct rt2560_softc *sc) 1837 { 1838 #define N(a) (sizeof (a) / sizeof ((a)[0])) 1839 int i, ntries; 1840 1841 /* wait for BBP to be ready */ 1842 for (ntries = 0; ntries < 100; ntries++) { 1843 if (rt2560_bbp_read(sc, RT2560_BBP_VERSION) != 0) 1844 break; 1845 drv_usecwait(1); 1846 } 1847 if (ntries == 100) { 1848 RAL_DEBUG(RAL_DBG_HW, "timeout waiting for BBP\n"); 1849 return (EIO); 1850 } 1851 /* initialize BBP registers to default values */ 1852 for (i = 0; i < N(rt2560_def_bbp); i++) { 1853 rt2560_bbp_write(sc, rt2560_def_bbp[i].reg, 1854 rt2560_def_bbp[i].val); 1855 } 1856 1857 return (0); 1858 #undef N 1859 } 1860 1861 static void 1862 rt2560_set_txantenna(struct rt2560_softc *sc, int antenna) 1863 { 1864 uint32_t tmp; 1865 uint8_t tx; 1866 1867 tx = rt2560_bbp_read(sc, RT2560_BBP_TX) & ~RT2560_BBP_ANTMASK; 1868 if (antenna == 1) 1869 tx |= RT2560_BBP_ANTA; 1870 else if (antenna == 2) 1871 tx |= RT2560_BBP_ANTB; 1872 else 1873 tx |= RT2560_BBP_DIVERSITY; 1874 1875 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1876 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526 || 1877 sc->rf_rev == RT2560_RF_5222) 1878 tx |= RT2560_BBP_FLIPIQ; 1879 1880 rt2560_bbp_write(sc, RT2560_BBP_TX, tx); 1881 1882 /* update values for CCK and OFDM in BBPCSR1 */ 1883 tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007; 1884 tmp |= (tx & 0x7) << 16 | (tx & 0x7); 1885 RAL_WRITE(sc, RT2560_BBPCSR1, tmp); 1886 } 1887 1888 static void 1889 rt2560_set_rxantenna(struct rt2560_softc *sc, int antenna) 1890 { 1891 uint8_t rx; 1892 1893 rx = rt2560_bbp_read(sc, RT2560_BBP_RX) & ~RT2560_BBP_ANTMASK; 1894 if (antenna == 1) 1895 rx |= RT2560_BBP_ANTA; 1896 else if (antenna == 2) 1897 rx |= RT2560_BBP_ANTB; 1898 else 1899 rx |= RT2560_BBP_DIVERSITY; 1900 1901 /* need to force no I/Q flip for RF 2525e and 2526 */ 1902 if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526) 1903 rx &= ~RT2560_BBP_FLIPIQ; 1904 1905 rt2560_bbp_write(sc, RT2560_BBP_RX, rx); 1906 } 1907 1908 static void 1909 rt2560_stop(struct rt2560_softc *sc) 1910 { 1911 struct ieee80211com *ic = &sc->sc_ic; 1912 1913 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 1914 ieee80211_stop_watchdog(ic); /* stop the watchdog */ 1915 1916 RAL_LOCK(sc); 1917 sc->sc_tx_timer = 0; 1918 1919 /* abort Tx */ 1920 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX); 1921 1922 /* disable Rx */ 1923 RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX); 1924 1925 /* reset ASIC (imply reset BBP) */ 1926 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); 1927 RAL_WRITE(sc, RT2560_CSR1, 0); 1928 1929 /* disable interrupts */ 1930 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 1931 1932 /* reset Tx and Rx rings */ 1933 rt2560_reset_tx_ring(sc, &sc->txq); 1934 rt2560_reset_tx_ring(sc, &sc->prioq); 1935 rt2560_reset_rx_ring(sc, &sc->rxq); 1936 RAL_UNLOCK(sc); 1937 } 1938 1939 static int 1940 rt2560_init(struct rt2560_softc *sc) 1941 { 1942 #define N(a) (sizeof (a) / sizeof ((a)[0])) 1943 /* struct rt2560_softc *sc = priv; */ 1944 struct ieee80211com *ic = &sc->sc_ic; 1945 uint32_t tmp; 1946 int i; 1947 1948 rt2560_stop(sc); 1949 1950 RAL_LOCK(sc); 1951 /* setup tx/rx ring */ 1952 rt2560_ring_hwsetup(sc); 1953 1954 /* initialize MAC registers to default values */ 1955 for (i = 0; i < N(rt2560_def_mac); i++) 1956 RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val); 1957 1958 rt2560_set_macaddr(sc, ic->ic_macaddr); 1959 1960 /* set basic rate set (will be updated later) */ 1961 RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x153); 1962 1963 rt2560_set_txantenna(sc, sc->tx_ant); 1964 rt2560_set_rxantenna(sc, sc->rx_ant); 1965 rt2560_update_slot(ic, 1); 1966 rt2560_update_plcp(sc); 1967 rt2560_update_led(sc, 0, 0); 1968 1969 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); 1970 RAL_WRITE(sc, RT2560_CSR1, RT2560_HOST_READY); 1971 1972 if (rt2560_bbp_init(sc) != 0) { 1973 RAL_UNLOCK(sc); 1974 rt2560_stop(sc); 1975 return (DDI_FAILURE); 1976 } 1977 1978 /* set default BSS channel */ 1979 rt2560_set_chan(sc, ic->ic_curchan); 1980 1981 /* kick Rx */ 1982 tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR; 1983 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 1984 tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR; 1985 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 1986 tmp |= RT2560_DROP_TODS; 1987 if (!(sc->sc_rcr & RAL_RCR_PROMISC)) 1988 tmp |= RT2560_DROP_NOT_TO_ME; 1989 1990 } 1991 RAL_WRITE(sc, RT2560_RXCSR0, tmp); 1992 1993 /* clear old FCS and Rx FIFO errors */ 1994 (void) RAL_READ(sc, RT2560_CNT0); 1995 (void) RAL_READ(sc, RT2560_CNT4); 1996 1997 /* clear any pending interrupts */ 1998 RAL_WRITE(sc, RT2560_CSR7, 0xffffffff); 1999 /* enable interrupts */ 2000 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK); 2001 2002 RAL_UNLOCK(sc); 2003 #undef N 2004 return (DDI_SUCCESS); 2005 } 2006 2007 void 2008 rt2560_watchdog(void *arg) 2009 { 2010 struct rt2560_softc *sc = arg; 2011 struct ieee80211com *ic = &sc->sc_ic; 2012 int ntimer = 0; 2013 2014 RAL_LOCK(sc); 2015 ic->ic_watchdog_timer = 0; 2016 2017 if (!RAL_IS_RUNNING(sc)) { 2018 RAL_UNLOCK(sc); 2019 return; 2020 } 2021 2022 if (sc->sc_tx_timer > 0) { 2023 if (--sc->sc_tx_timer == 0) { 2024 RAL_DEBUG(RAL_DBG_MSG, "tx timer timeout\n"); 2025 RAL_UNLOCK(sc); 2026 (void) rt2560_init(sc); 2027 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2028 return; 2029 } 2030 } 2031 2032 if (ic->ic_state == IEEE80211_S_RUN) 2033 ntimer = 1; 2034 2035 RAL_UNLOCK(sc); 2036 2037 ieee80211_watchdog(ic); 2038 2039 if (ntimer) 2040 ieee80211_start_watchdog(ic, ntimer); 2041 } 2042 2043 static int 2044 rt2560_m_start(void *arg) 2045 { 2046 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2047 crypto_mech_type_t type; 2048 int err; 2049 2050 2051 type = crypto_mech2id(SUN_CKM_RC4); /* load rc4 module into kernel */ 2052 RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_m_start(%d)\n", type); 2053 2054 /* 2055 * initialize rt2560 hardware 2056 */ 2057 err = rt2560_init(sc); 2058 if (err != DDI_SUCCESS) { 2059 RAL_DEBUG(RAL_DBG_GLD, "device configuration failed\n"); 2060 goto fail; 2061 } 2062 sc->sc_flags |= RAL_FLAG_RUNNING; /* RUNNING */ 2063 return (err); 2064 2065 fail: 2066 rt2560_stop(sc); 2067 return (err); 2068 } 2069 2070 static void 2071 rt2560_m_stop(void *arg) 2072 { 2073 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2074 2075 RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_m_stop()\n"); 2076 2077 (void) rt2560_stop(sc); 2078 sc->sc_flags &= ~RAL_FLAG_RUNNING; /* STOP */ 2079 } 2080 2081 static int 2082 rt2560_m_unicst(void *arg, const uint8_t *macaddr) 2083 { 2084 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2085 struct ieee80211com *ic = &sc->sc_ic; 2086 2087 RAL_DEBUG(RAL_DBG_GLD, "rt2560_m_unicst(): " MACSTR "\n", 2088 MAC2STR(macaddr)); 2089 2090 IEEE80211_ADDR_COPY(ic->ic_macaddr, macaddr); 2091 (void) rt2560_set_macaddr(sc, (uint8_t *)macaddr); 2092 (void) rt2560_init(sc); 2093 2094 return (0); 2095 } 2096 2097 /*ARGSUSED*/ 2098 static int 2099 rt2560_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 2100 { 2101 return (0); 2102 } 2103 2104 static int 2105 rt2560_m_promisc(void *arg, boolean_t on) 2106 { 2107 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2108 2109 RAL_DEBUG(RAL_DBG_GLD, "rt2560_m_promisc()\n"); 2110 2111 if (on) { 2112 sc->sc_rcr |= RAL_RCR_PROMISC; 2113 sc->sc_rcr |= RAL_RCR_MULTI; 2114 } else { 2115 sc->sc_rcr &= ~RAL_RCR_PROMISC; 2116 sc->sc_rcr &= ~RAL_RCR_PROMISC; 2117 } 2118 2119 rt2560_update_promisc(sc); 2120 return (0); 2121 } 2122 2123 static void 2124 rt2560_m_ioctl(void* arg, queue_t *wq, mblk_t *mp) 2125 { 2126 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2127 struct ieee80211com *ic = &sc->sc_ic; 2128 int err; 2129 2130 err = ieee80211_ioctl(ic, wq, mp); 2131 RAL_LOCK(sc); 2132 if (err == ENETRESET) { 2133 if (RAL_IS_RUNNING(sc)) { 2134 RAL_UNLOCK(sc); 2135 (void) rt2560_init(sc); 2136 (void) ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 2137 RAL_LOCK(sc); 2138 } 2139 } 2140 RAL_UNLOCK(sc); 2141 } 2142 2143 static int 2144 rt2560_m_stat(void *arg, uint_t stat, uint64_t *val) 2145 { 2146 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2147 ieee80211com_t *ic = &sc->sc_ic; 2148 ieee80211_node_t *ni = ic->ic_bss; 2149 struct ieee80211_rateset *rs = &ni->in_rates; 2150 2151 RAL_LOCK(sc); 2152 switch (stat) { 2153 case MAC_STAT_IFSPEED: 2154 *val = ((ic->ic_fixed_rate == IEEE80211_FIXED_RATE_NONE) ? 2155 (rs->ir_rates[ni->in_txrate] & IEEE80211_RATE_VAL) 2156 : ic->ic_fixed_rate) / 2 * 1000000; 2157 break; 2158 case MAC_STAT_NOXMTBUF: 2159 *val = sc->sc_tx_nobuf; 2160 break; 2161 case MAC_STAT_NORCVBUF: 2162 *val = sc->sc_rx_nobuf; 2163 break; 2164 case MAC_STAT_IERRORS: 2165 *val = sc->sc_rx_err; 2166 break; 2167 case MAC_STAT_RBYTES: 2168 *val = ic->ic_stats.is_rx_bytes; 2169 break; 2170 case MAC_STAT_IPACKETS: 2171 *val = ic->ic_stats.is_rx_frags; 2172 break; 2173 case MAC_STAT_OBYTES: 2174 *val = ic->ic_stats.is_tx_bytes; 2175 break; 2176 case MAC_STAT_OPACKETS: 2177 *val = ic->ic_stats.is_tx_frags; 2178 break; 2179 case MAC_STAT_OERRORS: 2180 case WIFI_STAT_TX_FAILED: 2181 *val = sc->sc_tx_err; 2182 break; 2183 case WIFI_STAT_TX_RETRANS: 2184 *val = sc->sc_tx_retries; 2185 break; 2186 case WIFI_STAT_FCS_ERRORS: 2187 case WIFI_STAT_WEP_ERRORS: 2188 case WIFI_STAT_TX_FRAGS: 2189 case WIFI_STAT_MCAST_TX: 2190 case WIFI_STAT_RTS_SUCCESS: 2191 case WIFI_STAT_RTS_FAILURE: 2192 case WIFI_STAT_ACK_FAILURE: 2193 case WIFI_STAT_RX_FRAGS: 2194 case WIFI_STAT_MCAST_RX: 2195 case WIFI_STAT_RX_DUPS: 2196 RAL_UNLOCK(sc); 2197 return (ieee80211_stat(ic, stat, val)); 2198 default: 2199 RAL_UNLOCK(sc); 2200 return (ENOTSUP); 2201 } 2202 RAL_UNLOCK(sc); 2203 2204 return (0); 2205 } 2206 2207 static uint_t 2208 rt2560_intr(caddr_t arg) 2209 { 2210 struct rt2560_softc *sc = (struct rt2560_softc *)arg; 2211 uint32_t r; 2212 2213 RAL_LOCK(sc); 2214 2215 r = RAL_READ(sc, RT2560_CSR7); 2216 RAL_WRITE(sc, RT2560_CSR7, r); 2217 2218 if (r == 0xffffffff) { 2219 RAL_UNLOCK(sc); 2220 return (DDI_INTR_UNCLAIMED); 2221 } 2222 2223 if (!(r & RT2560_INTR_ALL)) { 2224 RAL_UNLOCK(sc); 2225 return (DDI_INTR_UNCLAIMED); 2226 } 2227 2228 /* disable interrupts */ 2229 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 2230 2231 if (r & RT2560_TX_DONE) { 2232 RAL_UNLOCK(sc); 2233 rt2560_tx_intr(sc); 2234 RAL_LOCK(sc); 2235 } 2236 2237 if (r & RT2560_PRIO_DONE) { 2238 RAL_UNLOCK(sc); 2239 rt2560_prio_intr(sc); 2240 RAL_LOCK(sc); 2241 } 2242 2243 if (r & RT2560_RX_DONE) { 2244 sc->sc_rx_pend = 1; 2245 ddi_trigger_softintr(sc->sc_softint_id); 2246 } 2247 2248 /* re-enable interrupts */ 2249 RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK); 2250 RAL_UNLOCK(sc); 2251 2252 return (DDI_INTR_CLAIMED); 2253 } 2254 2255 static int 2256 rt2560_reset(dev_info_t *devinfo, ddi_reset_cmd_t cmd) 2257 { 2258 struct rt2560_softc *sc; 2259 2260 RAL_DEBUG(RAL_DBG_GLD, "rt2560_reset(0x%p)\n", (void *)devinfo); 2261 2262 if (cmd != DDI_RESET_FORCE) 2263 return (DDI_FAILURE); 2264 2265 sc = ddi_get_soft_state(ral_soft_state_p, ddi_get_instance(devinfo)); 2266 2267 /* abort Tx */ 2268 RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX); 2269 2270 /* disable Rx */ 2271 RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX); 2272 2273 /* reset ASIC (imply reset BBP) */ 2274 RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); 2275 RAL_WRITE(sc, RT2560_CSR1, 0); 2276 2277 /* disable interrupts */ 2278 RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); 2279 2280 return (DDI_SUCCESS); 2281 } 2282 2283 static int 2284 rt2560_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 2285 { 2286 struct rt2560_softc *sc; 2287 struct ieee80211com *ic; 2288 int err, i; 2289 int instance; 2290 2291 ddi_acc_handle_t ioh; 2292 caddr_t regs; 2293 uint16_t vendor_id, device_id, command; 2294 uint8_t cachelsz; 2295 char strbuf[32]; 2296 2297 wifi_data_t wd = { 0 }; 2298 mac_register_t *macp; 2299 2300 RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_attach()\n"); 2301 2302 if (cmd != DDI_ATTACH) 2303 return (DDI_FAILURE); 2304 2305 instance = ddi_get_instance(devinfo); 2306 2307 if (ddi_soft_state_zalloc(ral_soft_state_p, instance) != DDI_SUCCESS) { 2308 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2309 "unable to alloc soft_state_p\n"); 2310 return (DDI_FAILURE); 2311 } 2312 2313 sc = ddi_get_soft_state(ral_soft_state_p, instance); 2314 ic = (ieee80211com_t *)&sc->sc_ic; 2315 sc->sc_dev = devinfo; 2316 2317 /* pci configuration */ 2318 err = ddi_regs_map_setup(devinfo, 0, ®s, 0, 0, &ral_csr_accattr, 2319 &ioh); 2320 if (err != DDI_SUCCESS) { 2321 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2322 "ddi_regs_map_setup() failed"); 2323 goto fail1; 2324 } 2325 2326 cachelsz = ddi_get8(ioh, (uint8_t *)(regs + PCI_CONF_CACHE_LINESZ)); 2327 if (cachelsz == 0) 2328 cachelsz = 0x10; 2329 sc->sc_cachelsz = cachelsz << 2; 2330 2331 vendor_id = ddi_get16(ioh, (uint16_t *)(regs + PCI_CONF_VENID)); 2332 device_id = ddi_get16(ioh, (uint16_t *)(regs + PCI_CONF_DEVID)); 2333 2334 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): vendor 0x%x, " 2335 "device id 0x%x, cache size %d\n", vendor_id, device_id, cachelsz); 2336 2337 /* 2338 * Enable response to memory space accesses, 2339 * and enabe bus master. 2340 */ 2341 command = PCI_COMM_MAE | PCI_COMM_ME; 2342 ddi_put16(ioh, (uint16_t *)(regs + PCI_CONF_COMM), command); 2343 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2344 "set command reg to 0x%x \n", command); 2345 2346 ddi_put8(ioh, (uint8_t *)(regs + PCI_CONF_LATENCY_TIMER), 0xa8); 2347 ddi_put8(ioh, (uint8_t *)(regs + PCI_CONF_ILINE), 0x10); 2348 ddi_regs_map_free(&ioh); 2349 2350 /* pci i/o space */ 2351 err = ddi_regs_map_setup(devinfo, 1, 2352 &sc->sc_rbase, 0, 0, &ral_csr_accattr, &sc->sc_ioh); 2353 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2354 "regs map1 = %x err=%d\n", regs, err); 2355 if (err != DDI_SUCCESS) { 2356 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2357 "ddi_regs_map_setup() failed"); 2358 goto fail1; 2359 } 2360 2361 /* initialize the ral rate */ 2362 ral_rate_init(); 2363 2364 /* retrieve RT2560 rev. no */ 2365 sc->asic_rev = RAL_READ(sc, RT2560_CSR0); 2366 2367 /* retrieve MAC address */ 2368 rt2560_get_macaddr(sc, ic->ic_macaddr); 2369 2370 /* retrieve RF rev. no and various other things from EEPROM */ 2371 rt2560_read_eeprom(sc); 2372 2373 RAL_DEBUG(RAL_DBG_GLD, "MAC/BBP RT2560 (rev 0x%02x), RF %s\n", 2374 sc->asic_rev, rt2560_get_rf(sc->rf_rev)); 2375 2376 /* 2377 * Allocate Tx and Rx rings. 2378 */ 2379 err = rt2560_alloc_tx_ring(sc, &sc->txq, RT2560_TX_RING_COUNT); 2380 if (err != DDI_SUCCESS) { 2381 RAL_DEBUG(RAL_DBG_GLD, "could not allocate Tx ring\n"); 2382 goto fail2; 2383 } 2384 err = rt2560_alloc_tx_ring(sc, &sc->prioq, RT2560_PRIO_RING_COUNT); 2385 if (err != DDI_SUCCESS) { 2386 RAL_DEBUG(RAL_DBG_GLD, "could not allocate Prio ring\n"); 2387 goto fail3; 2388 } 2389 err = rt2560_alloc_rx_ring(sc, &sc->rxq, RT2560_RX_RING_COUNT); 2390 if (err != DDI_SUCCESS) { 2391 RAL_DEBUG(RAL_DBG_GLD, "could not allocate Rx ring\n"); 2392 goto fail4; 2393 } 2394 2395 mutex_init(&sc->sc_genlock, NULL, MUTEX_DRIVER, NULL); 2396 mutex_init(&sc->txq.tx_lock, NULL, MUTEX_DRIVER, NULL); 2397 mutex_init(&sc->prioq.tx_lock, NULL, MUTEX_DRIVER, NULL); 2398 mutex_init(&sc->rxq.rx_lock, NULL, MUTEX_DRIVER, NULL); 2399 2400 2401 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 2402 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 2403 ic->ic_state = IEEE80211_S_INIT; 2404 2405 ic->ic_maxrssi = 63; 2406 ic->ic_set_shortslot = rt2560_update_slot; 2407 ic->ic_xmit = rt2560_mgmt_send; 2408 2409 /* set device capabilities */ 2410 ic->ic_caps = 2411 IEEE80211_C_TXPMGT | /* tx power management */ 2412 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 2413 IEEE80211_C_SHSLOT; /* short slot time supported */ 2414 2415 ic->ic_caps |= IEEE80211_C_WPA; /* Support WPA/WPA2 */ 2416 2417 #define IEEE80211_CHAN_A \ 2418 (IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM) 2419 2420 if (sc->rf_rev == RT2560_RF_5222) { 2421 /* set supported .11a rates */ 2422 ic->ic_sup_rates[IEEE80211_MODE_11A] = rt2560_rateset_11a; 2423 2424 /* set supported .11a channels */ 2425 for (i = 36; i <= 64; i += 4) { 2426 ic->ic_sup_channels[i].ich_freq = 2427 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2428 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2429 } 2430 for (i = 100; i <= 140; i += 4) { 2431 ic->ic_sup_channels[i].ich_freq = 2432 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2433 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2434 } 2435 for (i = 149; i <= 161; i += 4) { 2436 ic->ic_sup_channels[i].ich_freq = 2437 ieee80211_ieee2mhz(i, IEEE80211_CHAN_5GHZ); 2438 ic->ic_sup_channels[i].ich_flags = IEEE80211_CHAN_A; 2439 } 2440 } 2441 2442 /* set supported .11b and .11g rates */ 2443 ic->ic_sup_rates[IEEE80211_MODE_11B] = rt2560_rateset_11b; 2444 ic->ic_sup_rates[IEEE80211_MODE_11G] = rt2560_rateset_11g; 2445 2446 /* set supported .11b and .11g channels (1 through 14) */ 2447 for (i = 1; i <= 14; i++) { 2448 ic->ic_sup_channels[i].ich_freq = 2449 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ); 2450 ic->ic_sup_channels[i].ich_flags = 2451 IEEE80211_CHAN_CCK | IEEE80211_CHAN_OFDM | 2452 IEEE80211_CHAN_DYN | IEEE80211_CHAN_2GHZ; 2453 } 2454 2455 ieee80211_attach(ic); 2456 2457 /* register WPA door */ 2458 ieee80211_register_door(ic, ddi_driver_name(devinfo), 2459 ddi_get_instance(devinfo)); 2460 2461 ic->ic_node_alloc = rt2560_node_alloc; 2462 ic->ic_node_free = rt2560_node_free; 2463 2464 /* override state transition machine */ 2465 sc->sc_newstate = ic->ic_newstate; 2466 ic->ic_newstate = rt2560_newstate; 2467 ic->ic_watchdog = rt2560_watchdog; 2468 ieee80211_media_init(ic); 2469 ic->ic_def_txkey = 0; 2470 2471 sc->sc_rcr = 0; 2472 sc->sc_rx_pend = 0; 2473 sc->dwelltime = 300; 2474 sc->sc_flags &= ~RAL_FLAG_RUNNING; 2475 2476 err = ddi_add_softintr(devinfo, DDI_SOFTINT_LOW, 2477 &sc->sc_softint_id, NULL, 0, ral_softint_handler, (caddr_t)sc); 2478 if (err != DDI_SUCCESS) { 2479 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2480 "ddi_add_softintr() failed"); 2481 goto fail5; 2482 } 2483 2484 err = ddi_get_iblock_cookie(devinfo, 0, &sc->sc_iblock); 2485 if (err != DDI_SUCCESS) { 2486 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2487 "Can not get iblock cookie for INT\n"); 2488 goto fail6; 2489 } 2490 2491 err = ddi_add_intr(devinfo, 0, NULL, NULL, rt2560_intr, (caddr_t)sc); 2492 if (err != DDI_SUCCESS) { 2493 RAL_DEBUG(RAL_DBG_GLD, 2494 "unable to add device interrupt handler\n"); 2495 goto fail6; 2496 } 2497 2498 /* 2499 * Provide initial settings for the WiFi plugin; whenever this 2500 * information changes, we need to call mac_plugindata_update() 2501 */ 2502 wd.wd_opmode = ic->ic_opmode; 2503 wd.wd_secalloc = WIFI_SEC_NONE; 2504 IEEE80211_ADDR_COPY(wd.wd_bssid, ic->ic_bss->in_bssid); 2505 2506 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 2507 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2508 "MAC version mismatch\n"); 2509 goto fail7; 2510 } 2511 2512 macp->m_type_ident = MAC_PLUGIN_IDENT_WIFI; 2513 macp->m_driver = sc; 2514 macp->m_dip = devinfo; 2515 macp->m_src_addr = ic->ic_macaddr; 2516 macp->m_callbacks = &rt2560_m_callbacks; 2517 macp->m_min_sdu = 0; 2518 macp->m_max_sdu = IEEE80211_MTU; 2519 macp->m_pdata = &wd; 2520 macp->m_pdata_size = sizeof (wd); 2521 2522 err = mac_register(macp, &ic->ic_mach); 2523 mac_free(macp); 2524 if (err != 0) { 2525 RAL_DEBUG(RAL_DBG_GLD, "ral: rt2560_attach(): " 2526 "mac_register err %x\n", err); 2527 goto fail7; 2528 } 2529 2530 /* 2531 * Create minor node of type DDI_NT_NET_WIFI 2532 */ 2533 (void) snprintf(strbuf, sizeof (strbuf), "%s%d", 2534 "ral", instance); 2535 err = ddi_create_minor_node(devinfo, strbuf, S_IFCHR, 2536 instance + 1, DDI_NT_NET_WIFI, 0); 2537 2538 if (err != DDI_SUCCESS) 2539 RAL_DEBUG(RAL_DBG_GLD, "ddi_create_minor_node() failed\n"); 2540 2541 /* 2542 * Notify link is down now 2543 */ 2544 mac_link_update(ic->ic_mach, LINK_STATE_DOWN); 2545 2546 RAL_DEBUG(RAL_DBG_GLD, "rt2560_attach() exit successfully.\n"); 2547 return (DDI_SUCCESS); 2548 fail7: 2549 ddi_remove_intr(devinfo, 0, sc->sc_iblock); 2550 fail6: 2551 ddi_remove_softintr(sc->sc_softint_id); 2552 fail5: 2553 mutex_destroy(&sc->sc_genlock); 2554 mutex_destroy(&sc->txq.tx_lock); 2555 mutex_destroy(&sc->prioq.tx_lock); 2556 mutex_destroy(&sc->rxq.rx_lock); 2557 2558 rt2560_free_rx_ring(sc, &sc->rxq); 2559 fail4: 2560 rt2560_free_tx_ring(sc, &sc->prioq); 2561 fail3: 2562 rt2560_free_tx_ring(sc, &sc->txq); 2563 fail2: 2564 ddi_regs_map_free(&sc->sc_ioh); 2565 fail1: 2566 ddi_soft_state_free(ral_soft_state_p, ddi_get_instance(devinfo)); 2567 2568 return (DDI_FAILURE); 2569 } 2570 2571 static int 2572 rt2560_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 2573 { 2574 struct rt2560_softc *sc; 2575 2576 RAL_DEBUG(RAL_DBG_GLD, "enter rt2560_detach()\n"); 2577 sc = ddi_get_soft_state(ral_soft_state_p, ddi_get_instance(devinfo)); 2578 2579 if (cmd != DDI_DETACH) 2580 return (DDI_FAILURE); 2581 2582 rt2560_stop(sc); 2583 2584 /* 2585 * Unregister from the MAC layer subsystem 2586 */ 2587 if (mac_unregister(sc->sc_ic.ic_mach) != 0) 2588 return (DDI_FAILURE); 2589 2590 ddi_remove_intr(devinfo, 0, sc->sc_iblock); 2591 ddi_remove_softintr(sc->sc_softint_id); 2592 2593 /* 2594 * detach ieee80211 layer 2595 */ 2596 ieee80211_detach(&sc->sc_ic); 2597 2598 rt2560_free_tx_ring(sc, &sc->txq); 2599 rt2560_free_tx_ring(sc, &sc->prioq); 2600 rt2560_free_rx_ring(sc, &sc->rxq); 2601 2602 ddi_regs_map_free(&sc->sc_ioh); 2603 2604 mutex_destroy(&sc->sc_genlock); 2605 mutex_destroy(&sc->txq.tx_lock); 2606 mutex_destroy(&sc->prioq.tx_lock); 2607 mutex_destroy(&sc->rxq.rx_lock); 2608 2609 ddi_remove_minor_node(devinfo, NULL); 2610 ddi_soft_state_free(ral_soft_state_p, ddi_get_instance(devinfo)); 2611 2612 return (DDI_SUCCESS); 2613 } 2614 2615 int 2616 _info(struct modinfo *modinfop) 2617 { 2618 return (mod_info(&modlinkage, modinfop)); 2619 } 2620 2621 int 2622 _init(void) 2623 { 2624 int status; 2625 2626 status = ddi_soft_state_init(&ral_soft_state_p, 2627 sizeof (struct rt2560_softc), 1); 2628 if (status != 0) 2629 return (status); 2630 2631 mac_init_ops(&ral_dev_ops, "ral"); 2632 status = mod_install(&modlinkage); 2633 if (status != 0) { 2634 mac_fini_ops(&ral_dev_ops); 2635 ddi_soft_state_fini(&ral_soft_state_p); 2636 } 2637 return (status); 2638 } 2639 2640 int 2641 _fini(void) 2642 { 2643 int status; 2644 2645 status = mod_remove(&modlinkage); 2646 if (status == 0) { 2647 mac_fini_ops(&ral_dev_ops); 2648 ddi_soft_state_fini(&ral_soft_state_p); 2649 } 2650 return (status); 2651 } 2652