1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCIC device/interrupt handler 31 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 32 * and Toshiba (and possibly other clones) PCMCIA adapter chip 33 * sets. It implements a subset of Socket Services as defined 34 * in the Solaris PCMCIA design documents 35 */ 36 37 /* 38 * currently defined "properties" 39 * 40 * clock-frequency bus clock frequency 41 * smi system management interrupt override 42 * need-mult-irq need status IRQ for each pair of sockets 43 * disable-audio don't route audio signal to speaker 44 */ 45 46 47 #include <sys/types.h> 48 #include <sys/inttypes.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/user.h> 52 #include <sys/buf.h> 53 #include <sys/file.h> 54 #include <sys/uio.h> 55 #include <sys/conf.h> 56 #include <sys/stat.h> 57 #include <sys/autoconf.h> 58 #include <sys/vtoc.h> 59 #include <sys/dkio.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/sunndi.h> 63 #include <sys/var.h> 64 #include <sys/callb.h> 65 #include <sys/open.h> 66 #include <sys/ddidmareq.h> 67 #include <sys/dma_engine.h> 68 #include <sys/kstat.h> 69 #include <sys/kmem.h> 70 #include <sys/modctl.h> 71 #include <sys/pci.h> 72 #include <sys/pci_impl.h> 73 74 #include <sys/pctypes.h> 75 #include <sys/pcmcia.h> 76 #include <sys/sservice.h> 77 78 #include <sys/note.h> 79 80 #include <sys/pcic_reg.h> 81 #include <sys/pcic_var.h> 82 83 #if defined(__sparc) 84 #include <sys/pci/pci_nexus.h> 85 #endif 86 87 #include <sys/hotplug/hpcsvc.h> 88 #include <sys/syshw.h> 89 #include "cardbus/cardbus.h" 90 91 #define SOFTC_SIZE (sizeof (anp_t)) 92 93 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 94 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 95 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 96 static uint_t pcic_intr(caddr_t, caddr_t); 97 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 98 static int pcic_probe(dev_info_t *); 99 100 static int pcic_open(dev_t *, int, int, cred_t *); 101 static int pcic_close(dev_t, int, int, cred_t *); 102 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 103 104 typedef struct pcm_regs pcm_regs_t; 105 106 static void pcic_init_assigned(dev_info_t *); 107 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 108 pci_regspec_t *, int); 109 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 110 111 /* 112 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 113 * are xlated into DMA ctlops. To make this nexus work on x86, we 114 * need to have the default ddi_dma_mctl ctlops in the bus_ops 115 * structure, just to pass the request to the parent. The correct 116 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 117 */ 118 static 119 struct bus_ops pcmciabus_ops = { 120 BUSO_REV, 121 pcmcia_bus_map, 122 NULL, 123 NULL, 124 NULL, 125 i_ddi_map_fault, 126 ddi_no_dma_map, 127 ddi_no_dma_allochdl, 128 ddi_no_dma_freehdl, 129 ddi_no_dma_bindhdl, 130 ddi_no_dma_unbindhdl, 131 ddi_no_dma_flush, 132 ddi_no_dma_win, 133 ddi_dma_mctl, 134 pcmcia_ctlops, 135 pcmcia_prop_op, 136 NULL, /* (*bus_get_eventcookie)(); */ 137 NULL, /* (*bus_add_eventcall)(); */ 138 NULL, /* (*bus_remove_eventcall)(); */ 139 NULL, /* (*bus_post_event)(); */ 140 NULL, /* (*bus_intr_ctl)(); */ 141 NULL, /* (*bus_config)(); */ 142 NULL, /* (*bus_unconfig)(); */ 143 NULL, /* (*bus_fm_init)(); */ 144 NULL, /* (*bus_fm_fini)(); */ 145 NULL, /* (*bus_enter)() */ 146 NULL, /* (*bus_exit)() */ 147 NULL, /* (*bus_power)() */ 148 pcmcia_intr_ops /* (*bus_intr_op)(); */ 149 }; 150 151 static struct cb_ops pcic_cbops = { 152 pcic_open, 153 pcic_close, 154 nodev, 155 nodev, 156 nodev, 157 nodev, 158 nodev, 159 pcic_ioctl, 160 nodev, 161 nodev, 162 nodev, 163 nochpoll, 164 ddi_prop_op, 165 NULL, 166 #ifdef CARDBUS 167 D_NEW | D_MP | D_HOTPLUG 168 #else 169 D_NEW | D_MP 170 #endif 171 }; 172 173 static struct dev_ops pcic_devops = { 174 DEVO_REV, 175 0, 176 pcic_getinfo, 177 nulldev, 178 pcic_probe, 179 pcic_attach, 180 pcic_detach, 181 nulldev, 182 &pcic_cbops, 183 &pcmciabus_ops, 184 NULL 185 }; 186 187 void *pcic_soft_state_p = NULL; 188 static int pcic_maxinst = -1; 189 static timeout_id_t pcic_delayed_resume_toid; 190 191 int pcic_do_insertion = 1; 192 int pcic_do_removal = 1; 193 194 struct irqmap { 195 int irq; 196 int count; 197 } pcic_irq_map[16]; 198 199 200 int pcic_debug = 0x0; 201 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 202 extern void cardbus_dump_pci_config(dev_info_t *dip); 203 extern void cardbus_dump_socket(dev_info_t *dip); 204 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 205 static void pcic_dump_debqueue(char *msg); 206 207 #if defined(PCIC_DEBUG) 208 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 209 210 #define pcic_mutex_enter(a) \ 211 { \ 212 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 213 mutex_enter(a); \ 214 }; 215 216 #define pcic_mutex_exit(a) \ 217 { \ 218 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 219 mutex_exit(a); \ 220 }; 221 222 #else 223 #define pcic_mutex_enter(a) mutex_enter(a) 224 #define pcic_mutex_exit(a) mutex_exit(a) 225 #endif 226 227 #define PCIC_VCC_3VLEVEL 1 228 #define PCIC_VCC_5VLEVEL 2 229 #define PCIC_VCC_12LEVEL 3 230 231 /* bit patterns to select voltage levels */ 232 int pcic_vpp_levels[13] = { 233 0, 0, 0, 234 1, /* 3.3V */ 235 0, 236 1, /* 5V */ 237 0, 0, 0, 0, 0, 0, 238 2 /* 12V */ 239 }; 240 241 uint8_t pcic_cbv_levels[13] = { 242 0, 0, 0, 243 3, /* 3.3V */ 244 0, 245 2, /* 5V */ 246 0, 0, 0, 0, 0, 0, 247 1 /* 12V */ 248 }; 249 250 struct power_entry pcic_power[4] = { 251 { 252 0, VCC|VPP1|VPP2 253 }, 254 { 255 33, /* 3.3Volt */ 256 VCC|VPP1|VPP2 257 }, 258 { 259 5*10, /* 5Volt */ 260 VCC|VPP1|VPP2 /* currently only know about this */ 261 }, 262 { 263 12*10, /* 12Volt */ 264 VPP1|VPP2 265 } 266 }; 267 268 /* 269 * Base used to allocate ranges of PCI memory on x86 systems 270 * Each instance gets a chunk above the base that is used to map 271 * in the memory and I/O windows for that device. 272 * Pages below the base are also allocated for the EXCA registers, 273 * one per instance. 274 */ 275 #define PCIC_PCI_MEMCHUNK 0x1000000 276 277 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 278 static int pcic_debounce_time = 200000; /* In micro-seconds */ 279 280 struct debounce { 281 pcic_socket_t *pcs; 282 clock_t expire; 283 struct debounce *next; 284 }; 285 286 static syshw_t pcic_syshw = { 287 0, "PC Card Socket 0", SH_CONNECTION, 288 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID|SYSHW_VAL0_VALID, 289 B_FALSE, {2, 0, 0, 0} 290 }; 291 292 static struct debounce *pcic_deb_queue = NULL; 293 static kmutex_t pcic_deb_mtx; 294 static kcondvar_t pcic_deb_cv; 295 static kthread_t *pcic_deb_threadid; 296 297 static inthandler_t *pcic_handlers; 298 299 static void pcic_setup_adapter(pcicdev_t *); 300 static int pcic_change(pcicdev_t *, int); 301 static int pcic_ll_reset(pcicdev_t *, int); 302 static void pcic_mswait(pcicdev_t *, int, int); 303 static boolean_t pcic_check_ready(pcicdev_t *, int); 304 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 305 static void pcic_ready_wait(pcicdev_t *, int); 306 extern int pcmcia_get_intr(dev_info_t *, int); 307 extern int pcmcia_return_intr(dev_info_t *, int); 308 309 static int pcic_callback(dev_info_t *, int (*)(), int); 310 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 311 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 312 static int pcic_get_page(dev_info_t *, get_page_t *); 313 static int pcic_get_socket(dev_info_t *, get_socket_t *); 314 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 315 static int pcic_get_window(dev_info_t *, get_window_t *); 316 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 317 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 318 static int pcic_reset_socket(dev_info_t *, int, int); 319 static int pcic_set_page(dev_info_t *, set_page_t *); 320 static int pcic_set_window(dev_info_t *, set_window_t *); 321 static int pcic_set_socket(dev_info_t *, set_socket_t *); 322 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 323 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 324 static void pcic_pm_detection(void *); 325 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 326 static int clext_reg_read(pcicdev_t *, int, uchar_t); 327 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 328 static int pcic_calc_speed(pcicdev_t *, uint32_t); 329 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 330 static int pcic_find_pci_type(pcicdev_t *); 331 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 332 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 333 static uint_t pcic_cd_softint(caddr_t, caddr_t); 334 static uint8_t pcic_getb(pcicdev_t *, int, int); 335 static void pcic_putb(pcicdev_t *, int, int, int8_t); 336 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 337 static uint_t pcic_softintr(caddr_t, caddr_t); 338 339 static void pcic_debounce(pcic_socket_t *); 340 static void pcic_delayed_resume(void *); 341 static void *pcic_add_debqueue(pcic_socket_t *, int); 342 static void pcic_rm_debqueue(void *); 343 static void pcic_deb_thread(); 344 345 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 346 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 347 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 348 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 349 static void pcic_cb_enable_intr(dev_info_t *); 350 static void pcic_cb_disable_intr(dev_info_t *); 351 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 352 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 353 354 static cb_nexus_cb_t pcic_cbnexus_ops = { 355 pcic_cb_enable_intr, 356 pcic_cb_disable_intr 357 }; 358 359 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 360 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 361 362 static void pcic_syshw_cardstate(syshw_t *, void *); 363 364 #if defined(__sparc) 365 static int pcic_fault(enum pci_fault_ops op, void *arg); 366 #endif 367 368 /* 369 * Default to support for Voyager IIi if sparc is defined. 370 * Appart from the PCI base addresses this only effect the TI1250. 371 */ 372 #if defined(sparc) 373 #define VOYAGER 374 #endif 375 376 377 /* 378 * pcmcia_attach() uses 0 and 128 upwards for the initpcmcia and devctl 379 * interfaces so we use 254. 380 */ 381 #define SYSHW_MINOR 254 382 383 /* 384 * Forward declarations for syshw interface (See end of file). 385 */ 386 static void syshw_attach(pcicdev_t *); 387 static void syshw_detach(pcicdev_t *); 388 static void syshw_resume(pcicdev_t *); 389 390 #ifdef VOYAGER 391 static uint_t syshw_intr(caddr_t); 392 static uint_t syshw_intr_hi(pcicdev_t *); 393 #endif 394 395 static int syshw_open(dev_t *, int, int, cred_t *); 396 static int syshw_close(dev_t, int, int, cred_t *); 397 static int syshw_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 398 static uint32_t syshw_add2map(syshw_t *, void (*)(syshw_t *, void *), void *); 399 static void syshw_send_signal(int); 400 401 /* 402 * pcmcia interface operations structure 403 * this is the private interface that is exported to the nexus 404 */ 405 pcmcia_if_t pcic_if_ops = { 406 PCIF_MAGIC, 407 PCIF_VERSION, 408 pcic_callback, 409 pcic_get_adapter, 410 pcic_get_page, 411 pcic_get_socket, 412 pcic_get_status, 413 pcic_get_window, 414 pcic_inquire_adapter, 415 pcic_inquire_socket, 416 pcic_inquire_window, 417 pcic_reset_socket, 418 pcic_set_page, 419 pcic_set_window, 420 pcic_set_socket, 421 pcic_set_interrupt, 422 pcic_clear_interrupt, 423 NULL, 424 }; 425 426 /* 427 * chip type identification routines 428 * this list of functions is searched until one of them succeeds 429 * or all fail. i82365SL is assumed if failed. 430 */ 431 static int pcic_ci_cirrus(pcicdev_t *); 432 static int pcic_ci_vadem(pcicdev_t *); 433 static int pcic_ci_ricoh(pcicdev_t *); 434 435 int (*pcic_ci_funcs[])(pcicdev_t *) = { 436 pcic_ci_cirrus, 437 pcic_ci_vadem, 438 pcic_ci_ricoh, 439 NULL 440 }; 441 442 static struct modldrv modldrv = { 443 &mod_driverops, /* Type of module. This one is a driver */ 444 "PCIC PCMCIA adapter driver %I%", /* Name of the module. */ 445 &pcic_devops, /* driver ops */ 446 }; 447 448 static struct modlinkage modlinkage = { 449 MODREV_1, (void *)&modldrv, NULL 450 }; 451 452 int 453 _init() 454 { 455 int stat; 456 457 /* Allocate soft state */ 458 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 459 SOFTC_SIZE, 2)) != DDI_SUCCESS) 460 return (stat); 461 462 if ((stat = mod_install(&modlinkage)) != 0) 463 ddi_soft_state_fini(&pcic_soft_state_p); 464 465 return (stat); 466 } 467 468 int 469 _fini() 470 { 471 int stat = 0; 472 473 if ((stat = mod_remove(&modlinkage)) != 0) 474 return (stat); 475 476 if (pcic_deb_threadid) { 477 mutex_enter(&pcic_deb_mtx); 478 pcic_deb_threadid = 0; 479 while (!pcic_deb_threadid) 480 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 481 pcic_deb_threadid = 0; 482 mutex_exit(&pcic_deb_mtx); 483 484 mutex_destroy(&pcic_deb_mtx); 485 cv_destroy(&pcic_deb_cv); 486 } 487 488 ddi_soft_state_fini(&pcic_soft_state_p); 489 490 return (stat); 491 } 492 493 int 494 _info(struct modinfo *modinfop) 495 { 496 return (mod_info(&modlinkage, modinfop)); 497 } 498 499 /* 500 * pcic_getinfo() 501 * provide instance/device information about driver 502 */ 503 /*ARGSUSED*/ 504 static int 505 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 506 { 507 anp_t *anp; 508 int error = DDI_SUCCESS; 509 minor_t minor; 510 511 switch (cmd) { 512 case DDI_INFO_DEVT2DEVINFO: 513 minor = getminor((dev_t)arg); 514 if (minor == SYSHW_MINOR) 515 minor = 0; 516 else 517 minor &= 0x7f; 518 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 519 *result = NULL; 520 else 521 *result = anp->an_dip; 522 break; 523 case DDI_INFO_DEVT2INSTANCE: 524 minor = getminor((dev_t)arg); 525 if (minor == SYSHW_MINOR) 526 minor = 0; 527 else 528 minor &= 0x7f; 529 *result = (void *)((long)minor); 530 break; 531 default: 532 error = DDI_FAILURE; 533 break; 534 } 535 return (error); 536 } 537 538 static int 539 pcic_probe(dev_info_t *dip) 540 { 541 int value; 542 ddi_device_acc_attr_t attr; 543 ddi_acc_handle_t handle; 544 uchar_t *index, *data; 545 546 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 547 return (DDI_PROBE_DONTCARE); 548 549 /* 550 * find a PCIC device (any vendor) 551 * while there can be up to 4 such devices in 552 * a system, we currently only look for 1 553 * per probe. There will be up to 2 chips per 554 * instance since they share I/O space 555 */ 556 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 557 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 558 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 559 560 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 561 (caddr_t *)&index, 562 PCIC_ISA_CONTROL_REG_OFFSET, 563 PCIC_ISA_CONTROL_REG_LENGTH, 564 &attr, &handle) != DDI_SUCCESS) 565 return (DDI_PROBE_FAILURE); 566 567 data = index + 1; 568 569 #if defined(PCIC_DEBUG) 570 if (pcic_debug) 571 cmn_err(CE_CONT, "pcic_probe: entered\n"); 572 if (pcic_debug) 573 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 574 #endif 575 ddi_put8(handle, index, PCIC_CHIP_REVISION); 576 ddi_put8(handle, data, 0); 577 value = ddi_get8(handle, data); 578 #if defined(PCIC_DEBUG) 579 if (pcic_debug) 580 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 581 #endif 582 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 583 (value & 0x30) == 0) { 584 /* 585 * we probably have a PCIC chip in the system 586 * do a little more checking. If we find one, 587 * reset everything in case of softboot 588 */ 589 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 590 ddi_put8(handle, data, 0); 591 value = ddi_get8(handle, data); 592 #if defined(PCIC_DEBUG) 593 if (pcic_debug) 594 cmn_err(CE_CONT, "\tzero test = %x\n", value); 595 #endif 596 /* should read back as zero */ 597 if (value == 0) { 598 /* 599 * we do have one and it is off the bus 600 */ 601 #if defined(PCIC_DEBUG) 602 if (pcic_debug) 603 cmn_err(CE_CONT, "pcic_probe: success\n"); 604 #endif 605 ddi_regs_map_free(&handle); 606 return (DDI_PROBE_SUCCESS); 607 } 608 } 609 #if defined(PCIC_DEBUG) 610 if (pcic_debug) 611 cmn_err(CE_CONT, "pcic_probe: failed\n"); 612 #endif 613 ddi_regs_map_free(&handle); 614 return (DDI_PROBE_FAILURE); 615 } 616 617 /* 618 * These are just defaults they can also be changed via a property in the 619 * conf file. 620 */ 621 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 622 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 623 static int pcic_do_pcmcia_sr = 0; 624 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 625 626 /* 627 * enable insertion/removal interrupt for 32bit cards 628 */ 629 static int 630 cardbus_enable_cd_intr(dev_info_t *dip) 631 { 632 ddi_acc_handle_t iohandle; 633 caddr_t ioaddr; 634 ddi_device_acc_attr_t attr; 635 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 636 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 637 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 638 (void) ddi_regs_map_setup(dip, 1, 639 (caddr_t *)&ioaddr, 640 0, 641 4096, 642 &attr, &iohandle); 643 644 /* CSC Interrupt: Card detect interrupt on */ 645 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 646 ddi_get32(iohandle, 647 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 648 649 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 650 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 651 652 ddi_regs_map_free(&iohandle); 653 return (1); 654 } 655 656 /* 657 * pcic_attach() 658 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 659 * to the system. This is a child of "sysbus" since that is where 660 * the hardware lives, but it provides services to the "pcmcia" 661 * nexus driver. It gives a pointer back via its private data 662 * structure which contains both the dip and socket services entry 663 * points 664 */ 665 static int 666 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 667 { 668 anp_t *pcic_nexus; 669 pcicdev_t *pcic; 670 int irqlevel, value; 671 int pci_cfrn, pci_ctrn; 672 int i, j, smi, actual; 673 char *typename; 674 char bus_type[16] = "(unknown)"; 675 int len = sizeof (bus_type); 676 ddi_device_acc_attr_t attr; 677 anp_t *anp = ddi_get_driver_private(dip); 678 uint_t pri; 679 syshw_t *shwp; 680 681 #if defined(PCIC_DEBUG) 682 if (pcic_debug) { 683 cmn_err(CE_CONT, "pcic_attach: entered\n"); 684 } 685 #endif 686 switch (cmd) { 687 case DDI_ATTACH: 688 break; 689 case DDI_RESUME: 690 pcic = anp->an_private; 691 /* 692 * for now, this is a simulated resume. 693 * a real one may need different things. 694 */ 695 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 696 mutex_enter(&pcic->pc_lock); 697 /* should probe for new sockets showing up */ 698 pcic_setup_adapter(pcic); 699 syshw_resume(pcic); 700 pcic->pc_flags &= ~PCF_SUSPENDED; 701 mutex_exit(&pcic->pc_lock); 702 (void) pcmcia_begin_resume(dip); 703 /* 704 * this will do the CARD_INSERTION 705 * due to needing time for threads to 706 * run, it must be delayed for a short amount 707 * of time. pcmcia_wait_insert checks for all 708 * children to be removed and then triggers insert. 709 */ 710 /* 711 * The reason for having a single timeout here 712 * rather than seperate timeout()s for each instance 713 * is due to the limited number (2) of callout threads 714 * available in Solaris 2.6. A single 1250A ends up 715 * as two instances of the interface with one slot each. 716 * The pcic_delayed_resume() function ends by calling 717 * pcmcia_wait_insert() which at one point does a 718 * delay(). delay() is implemented with a timeout() 719 * call so you end up with both the callout() 720 * threads waiting to be woken up by another callout(). 721 * This situation locks up the machine hence the 722 * convolution here to only use one timeout. 723 */ 724 if (!pcic_delayed_resume_toid) 725 pcic_delayed_resume_toid = 726 timeout(pcic_delayed_resume, (caddr_t)0, 727 drv_usectohz(pcic_wait_insert_time)); 728 729 /* 730 * for complete implementation need END_RESUME (later) 731 */ 732 return (DDI_SUCCESS); 733 734 } 735 return (DDI_SUCCESS); 736 default: 737 return (DDI_FAILURE); 738 } 739 740 /* 741 * Allocate soft state associated with this instance. 742 */ 743 if (ddi_soft_state_zalloc(pcic_soft_state_p, 744 ddi_get_instance(dip)) != DDI_SUCCESS) { 745 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 746 ddi_get_instance(dip)); 747 return (DDI_FAILURE); 748 } 749 750 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 751 ddi_get_instance(dip)); 752 753 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 754 755 pcic->dip = dip; 756 pcic_nexus->an_dip = dip; 757 pcic_nexus->an_if = &pcic_if_ops; 758 pcic_nexus->an_private = pcic; 759 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 760 pcic->pc_power = pcic_power; 761 762 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 763 "pci-control-reg-number", pci_control_reg_num); 764 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 765 "pci-config-reg-number", pci_config_reg_num); 766 767 ddi_set_driver_private(dip, pcic_nexus); 768 769 /* 770 * pcic->pc_irq is really the IPL level we want to run at 771 * set the default values here and override from intr spec 772 */ 773 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 774 "interrupt-priorities", -1); 775 776 if (pcic->pc_irq == -1) { 777 int actual; 778 uint_t pri; 779 ddi_intr_handle_t hdl; 780 781 /* see if intrspec tells us different */ 782 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 783 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 784 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 785 pcic->pc_irq = pri; 786 else 787 pcic->pc_irq = LOCK_LEVEL + 1; 788 (void) ddi_intr_free(hdl); 789 } 790 } 791 pcic_nexus->an_ipl = pcic->pc_irq; 792 793 /* 794 * Check our parent bus type. We do different things based on which 795 * bus we're on. 796 */ 797 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 798 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 799 "device_type", (caddr_t)&bus_type[0], &len) != 800 DDI_PROP_SUCCESS) { 801 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 802 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 803 "bus-type", (caddr_t)&bus_type[0], &len) != 804 DDI_PROP_SUCCESS) { 805 806 cmn_err(CE_CONT, 807 "pcic%d: can't find parent bus type\n", 808 ddi_get_instance(dip)); 809 810 kmem_free(pcic, sizeof (pcicdev_t)); 811 return (DDI_FAILURE); 812 } 813 } /* ddi_prop_op("device_type") */ 814 815 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 816 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) { 817 pcic->pc_flags = PCF_PCIBUS; 818 } else { 819 #if defined(__sparc) 820 cmn_err(CE_CONT, "pcic%d: unsupported parent bus type: [%s]\n", 821 ddi_get_instance(dip), bus_type); 822 823 kmem_free(pcic, sizeof (pcicdev_t)); 824 return (DDI_FAILURE); 825 #else 826 pcic->pc_flags = 0; 827 #endif 828 } 829 830 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 831 DDI_PROP_CANSLEEP, 832 "clock-frequency", 0)) == 0) { 833 if (pcic->pc_flags & PCF_PCIBUS) 834 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 835 else 836 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 837 } else { 838 /* 839 * OBP can declare the speed in Hz... 840 */ 841 if (pcic->bus_speed > 1000000) 842 pcic->bus_speed /= 1000000; 843 } /* ddi_prop_op("clock-frequency") */ 844 845 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 846 847 #ifdef PCIC_DEBUG 848 if (pcic_debug) { 849 cmn_err(CE_CONT, 850 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 851 ddi_get_instance(dip), 852 bus_type, pcic->bus_speed); 853 } 854 #endif 855 856 /* 857 * The reg properties on a PCI node are different than those 858 * on a non-PCI node. Handle that difference here. 859 * If it turns out to be a CardBus chip, we have even more 860 * differences. 861 */ 862 if (pcic->pc_flags & PCF_PCIBUS) { 863 int class_code; 864 #if defined(__i386) || defined(__amd64) 865 pcic->pc_base = 0x1000000; 866 pcic->pc_bound = (uint32_t)~0; 867 pcic->pc_iobase = 0x1000; 868 pcic->pc_iobound = 0xefff; 869 #elif defined(__sparc) 870 pcic->pc_base = 0x0; 871 pcic->pc_bound = (uint32_t)~0; 872 pcic->pc_iobase = 0x00000; 873 pcic->pc_iobound = 0xffff; 874 #endif 875 876 /* usually need to get at config space so map first */ 877 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 878 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 879 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 880 881 if (ddi_regs_map_setup(dip, pci_cfrn, 882 (caddr_t *)&pcic->cfgaddr, 883 PCIC_PCI_CONFIG_REG_OFFSET, 884 PCIC_PCI_CONFIG_REG_LENGTH, 885 &attr, 886 &pcic->cfg_handle) != 887 DDI_SUCCESS) { 888 cmn_err(CE_CONT, 889 "pcic%d: unable to map config space" 890 "regs\n", 891 ddi_get_instance(dip)); 892 893 kmem_free(pcic, sizeof (pcicdev_t)); 894 return (DDI_FAILURE); 895 } /* ddi_regs_map_setup */ 896 897 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 898 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 899 "class-code", -1); 900 #ifdef PCIC_DEBUG 901 if (pcic_debug) { 902 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 903 class_code); 904 } 905 #endif 906 907 switch (class_code) { 908 case PCIC_PCI_CARDBUS: 909 pcic->pc_flags |= PCF_CARDBUS; 910 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 911 /* 912 * Get access to the adapter registers on the 913 * PCI bus. A 4K memory page 914 */ 915 #if defined(PCIC_DEBUG) 916 pcic_err(dip, 8, "Is Cardbus device\n"); 917 if (pcic_debug) { 918 int nr; 919 long rs; 920 (void) ddi_dev_nregs(dip, &nr); 921 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 922 "cfghndl 0x%p nregs %d", 923 (void *)pcic->cfgaddr, 924 (void *)pcic->cfg_handle, nr); 925 926 (void) ddi_dev_regsize(dip, 927 PCIC_PCI_CONTROL_REG_NUM, &rs); 928 929 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 930 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 931 } 932 #endif 933 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 934 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 935 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 936 937 if (ddi_regs_map_setup(dip, pci_ctrn, 938 (caddr_t *)&pcic->ioaddr, 939 PCIC_PCI_CONTROL_REG_OFFSET, 940 PCIC_CB_CONTROL_REG_LENGTH, 941 &attr, &pcic->handle) != 942 DDI_SUCCESS) { 943 cmn_err(CE_CONT, 944 "pcic%d: unable to map PCI regs\n", 945 ddi_get_instance(dip)); 946 ddi_regs_map_free(&pcic->cfg_handle); 947 kmem_free(pcic, sizeof (pcicdev_t)); 948 return (DDI_FAILURE); 949 } /* ddi_regs_map_setup */ 950 951 /* 952 * Find out the chip type - If we're on a PCI bus, 953 * the adapter has that information in the PCI 954 * config space. 955 * Note that we call pcic_find_pci_type here since 956 * it needs a valid mapped pcic->handle to 957 * access some of the adapter registers in 958 * some cases. 959 */ 960 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 961 ddi_regs_map_free(&pcic->handle); 962 ddi_regs_map_free(&pcic->cfg_handle); 963 kmem_free(pcic, sizeof (pcicdev_t)); 964 cmn_err(CE_WARN, "pcic: %s: unsupported " 965 "bridge\n", 966 ddi_get_name_addr(dip)); 967 return (DDI_FAILURE); 968 } 969 break; 970 971 default: 972 case PCIC_PCI_PCMCIA: 973 /* 974 * Get access to the adapter IO registers on the 975 * PCI bus config space. 976 */ 977 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 978 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 979 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 980 981 /* 982 * We need a default mapping to the adapter's IO 983 * control register space. For most adapters 984 * that are of class PCIC_PCI_PCMCIA (or of 985 * a default class) the control registers 986 * will be using the 82365-type control/data 987 * format. 988 */ 989 if (ddi_regs_map_setup(dip, pci_ctrn, 990 (caddr_t *)&pcic->ioaddr, 991 PCIC_PCI_CONTROL_REG_OFFSET, 992 PCIC_PCI_CONTROL_REG_LENGTH, 993 &attr, 994 &pcic->handle) != DDI_SUCCESS) { 995 cmn_err(CE_CONT, 996 "pcic%d: unable to map PCI regs\n", 997 ddi_get_instance(dip)); 998 ddi_regs_map_free(&pcic->cfg_handle); 999 kmem_free(pcic, sizeof (pcicdev_t)); 1000 return (DDI_FAILURE); 1001 } /* ddi_regs_map_setup */ 1002 1003 /* 1004 * Find out the chip type - If we're on a PCI bus, 1005 * the adapter has that information in the PCI 1006 * config space. 1007 * Note that we call pcic_find_pci_type here since 1008 * it needs a valid mapped pcic->handle to 1009 * access some of the adapter registers in 1010 * some cases. 1011 */ 1012 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 1013 ddi_regs_map_free(&pcic->handle); 1014 ddi_regs_map_free(&pcic->cfg_handle); 1015 kmem_free(pcic, sizeof (pcicdev_t)); 1016 cmn_err(CE_WARN, "pcic: %s: unsupported " 1017 "bridge\n", 1018 ddi_get_name_addr(dip)); 1019 return (DDI_FAILURE); 1020 } 1021 1022 /* 1023 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 1024 * for extended registers even though they are 1025 * not CardBus adapters. For those adapters, 1026 * re-map pcic->handle to be large enough to 1027 * encompass the Yenta registers. 1028 */ 1029 switch (pcic->pc_type) { 1030 case PCIC_TI_PCI1031: 1031 ddi_regs_map_free(&pcic->handle); 1032 1033 if (ddi_regs_map_setup(dip, 1034 PCIC_PCI_CONTROL_REG_NUM, 1035 (caddr_t *)&pcic->ioaddr, 1036 PCIC_PCI_CONTROL_REG_OFFSET, 1037 PCIC_CB_CONTROL_REG_LENGTH, 1038 &attr, 1039 &pcic->handle) != DDI_SUCCESS) { 1040 cmn_err(CE_CONT, 1041 "pcic%d: unable to map " 1042 "PCI regs\n", 1043 ddi_get_instance(dip)); 1044 ddi_regs_map_free(&pcic->cfg_handle); 1045 kmem_free(pcic, sizeof (pcicdev_t)); 1046 return (DDI_FAILURE); 1047 } /* ddi_regs_map_setup */ 1048 break; 1049 default: 1050 break; 1051 } /* switch (pcic->pc_type) */ 1052 break; 1053 } /* switch (class_code) */ 1054 } else { 1055 /* 1056 * We're not on a PCI bus, so assume an ISA bus type 1057 * register property. Get access to the adapter IO 1058 * registers on a non-PCI bus. 1059 */ 1060 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1061 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 1062 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1063 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 1064 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 1065 1066 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1067 (caddr_t *)&pcic->ioaddr, 1068 PCIC_ISA_CONTROL_REG_OFFSET, 1069 PCIC_ISA_CONTROL_REG_LENGTH, 1070 &attr, 1071 &pcic->handle) != DDI_SUCCESS) { 1072 cmn_err(CE_CONT, 1073 "pcic%d: unable to map ISA registers\n", 1074 ddi_get_instance(dip)); 1075 1076 kmem_free(pcic, sizeof (pcicdev_t)); 1077 return (DDI_FAILURE); 1078 } /* ddi_regs_map_setup */ 1079 1080 /* ISA bus is limited to 24-bits, but not first 640K */ 1081 pcic->pc_base = 0xd0000; 1082 pcic->pc_bound = (uint32_t)~0; 1083 pcic->pc_iobase = 0x1000; 1084 pcic->pc_iobound = 0xefff; 1085 } /* !PCF_PCIBUS */ 1086 1087 #ifdef PCIC_DEBUG 1088 if (pcic_debug) { 1089 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1090 pcic->pc_flags, pcic->pc_type); 1091 } 1092 #endif 1093 1094 /* 1095 * Setup various adapter registers for the PCI case. For the 1096 * non-PCI case, find out the chip type. 1097 */ 1098 if (pcic->pc_flags & PCF_PCIBUS) { 1099 int iline; 1100 #if defined(__sparc) 1101 iline = 0; 1102 #else 1103 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1104 #endif 1105 1106 /* set flags and socket counts based on chip type */ 1107 switch (pcic->pc_type) { 1108 uint32_t cfg; 1109 case PCIC_INTEL_i82092: 1110 cfg = ddi_get8(pcic->cfg_handle, 1111 pcic->cfgaddr + PCIC_82092_PCICON); 1112 /* we can only support 4 Socket version */ 1113 if (cfg & PCIC_82092_4_SOCKETS) { 1114 pcic->pc_numsockets = 4; 1115 pcic->pc_type = PCIC_INTEL_i82092; 1116 if (iline != 0xFF) 1117 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1118 else 1119 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1120 } else { 1121 cmn_err(CE_CONT, 1122 "pcic%d: Intel 82092 adapter " 1123 "in unsupported configuration: 0x%x", 1124 ddi_get_instance(pcic->dip), cfg); 1125 pcic->pc_numsockets = 0; 1126 } /* PCIC_82092_4_SOCKETS */ 1127 break; 1128 case PCIC_CL_PD6730: 1129 case PCIC_CL_PD6729: 1130 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1131 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1132 DDI_PROP_CANSLEEP, 1133 "interrupts", 0); 1134 /* if not interrupt pin then must use ISA style IRQs */ 1135 if (cfg == 0 || iline == 0xFF) 1136 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1137 else { 1138 /* 1139 * we have the option to use PCI interrupts. 1140 * this might not be optimal but in some cases 1141 * is the only thing possible (sparc case). 1142 * we now deterine what is possible. 1143 */ 1144 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1145 } 1146 pcic->pc_numsockets = 2; 1147 pcic->pc_flags |= PCF_IO_REMAP; 1148 break; 1149 case PCIC_TI_PCI1031: 1150 /* this chip doesn't do CardBus but looks like one */ 1151 pcic->pc_flags &= ~PCF_CARDBUS; 1152 /* FALLTHROUGH */ 1153 default: 1154 pcic->pc_flags |= PCF_IO_REMAP; 1155 /* FALLTHROUGH */ 1156 /* indicate feature even if not supported */ 1157 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1158 /* Not sure if these apply to all these chips */ 1159 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1160 pcic->pc_flags |= pcic_use_cbpwrctl; 1161 1162 pcic->pc_numsockets = 1; /* one per function */ 1163 if (iline != 0xFF) { 1164 uint8_t cfg; 1165 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1166 1167 cfg = ddi_get8(pcic->cfg_handle, 1168 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1169 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1170 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1171 PCIC_BRIDGE_CTL_REG), cfg); 1172 } 1173 else 1174 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1175 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1176 break; 1177 } 1178 } else { 1179 /* 1180 * We're not on a PCI bus so do some more 1181 * checking for adapter type here. 1182 * For the non-PCI bus case: 1183 * It could be any one of a number of different chips 1184 * If we can't determine anything else, it is assumed 1185 * to be an Intel 82365SL. The Cirrus Logic PD6710 1186 * has an extension register that provides unique 1187 * identification. Toshiba chip isn't detailed as yet. 1188 */ 1189 1190 /* Init the CL id mode */ 1191 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1192 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1193 1194 /* default to Intel i82365SL and then refine */ 1195 pcic->pc_type = PCIC_I82365SL; 1196 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1197 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1198 /* go until one succeeds or none left */ 1199 if (pcic_ci_funcs[value](pcic)) 1200 break; 1201 } 1202 1203 /* any chip specific flags get set here */ 1204 switch (pcic->pc_type) { 1205 case PCIC_CL_PD6722: 1206 pcic->pc_flags |= PCF_DMA; 1207 } 1208 1209 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1210 /* 1211 * look for total number of sockets. 1212 * basically check each possible socket for 1213 * presence like in probe 1214 */ 1215 1216 /* turn all windows off */ 1217 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1218 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1219 1220 /* 1221 * if a zero is read back, then this socket 1222 * might be present. It would be except for 1223 * some systems that map the secondary PCIC 1224 * chip space back to the first. 1225 */ 1226 if (value != 0) { 1227 /* definitely not so skip */ 1228 /* note: this is for Compaq support */ 1229 continue; 1230 } 1231 1232 /* further tests */ 1233 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1234 PCIC_REV_MASK; 1235 if (!(value >= PCIC_REV_LEVEL_LOW && 1236 value <= PCIC_REV_LEVEL_HI)) 1237 break; 1238 1239 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1240 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1241 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1242 1243 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1244 if (value != 0xaa || j != 0x55) 1245 break; 1246 1247 /* 1248 * at this point we know if we have hardware 1249 * of some type and not just the bus holding 1250 * a pattern for us. We still have to determine 1251 * the case where more than 2 sockets are 1252 * really the same due to peculiar mappings of 1253 * hardware. 1254 */ 1255 j = pcic->pc_numsockets++; 1256 pcic->pc_sockets[j].pcs_flags = 0; 1257 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1258 pcic->pc_sockets[j].pcs_socket = i; 1259 1260 /* put PC Card into RESET, just in case */ 1261 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1262 pcic_putb(pcic, i, PCIC_INTERRUPT, 1263 value & ~PCIC_RESET); 1264 } 1265 1266 #if defined(PCIC_DEBUG) 1267 if (pcic_debug) 1268 cmn_err(CE_CONT, "num sockets = %d\n", 1269 pcic->pc_numsockets); 1270 #endif 1271 if (pcic->pc_numsockets == 0) { 1272 ddi_regs_map_free(&pcic->handle); 1273 kmem_free(pcic, sizeof (pcicdev_t)); 1274 return (DDI_FAILURE); 1275 } 1276 1277 /* 1278 * need to think this through again in light of 1279 * Compaq not following the model that all the 1280 * chip vendors recommend. IBM 755 seems to be 1281 * afflicted as well. Basically, if the vendor 1282 * wired things wrong, socket 0 responds for socket 2 1283 * accesses, etc. 1284 */ 1285 if (pcic->pc_numsockets > 2) { 1286 int count = pcic->pc_numsockets / 4; 1287 for (i = 0; i < count; i++) { 1288 /* put pattern into socket 0 */ 1289 pcic_putb(pcic, i, 1290 PCIC_SYSMEM_0_STARTLOW, 0x11); 1291 1292 /* put pattern into socket 2 */ 1293 pcic_putb(pcic, i + 2, 1294 PCIC_SYSMEM_0_STARTLOW, 0x33); 1295 1296 /* read back socket 0 */ 1297 value = pcic_getb(pcic, i, 1298 PCIC_SYSMEM_0_STARTLOW); 1299 1300 /* read back chip 1 socket 0 */ 1301 j = pcic_getb(pcic, i + 2, 1302 PCIC_SYSMEM_0_STARTLOW); 1303 if (j == value) { 1304 pcic->pc_numsockets -= 2; 1305 } 1306 } 1307 } 1308 1309 smi = 0xff; /* no more override */ 1310 1311 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1312 DDI_PROP_DONTPASS, "need-mult-irq", 1313 0xffff) != 0xffff) 1314 pcic->pc_flags |= PCF_MULT_IRQ; 1315 1316 } /* !PCF_PCIBUS */ 1317 1318 /* 1319 * some platforms/busses need to have resources setup 1320 * this is temporary until a real resource allocator is 1321 * implemented. 1322 */ 1323 1324 pcic_init_assigned(dip); 1325 1326 typename = pcic->pc_chipname; 1327 1328 #ifdef PCIC_DEBUG 1329 if (pcic_debug) { 1330 int nregs, nintrs; 1331 1332 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1333 nregs = 0; 1334 1335 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1336 nintrs = 0; 1337 1338 cmn_err(CE_CONT, 1339 "pcic%d: %d register sets, %d interrupts\n", 1340 ddi_get_instance(dip), nregs, nintrs); 1341 1342 nintrs = 0; 1343 while (nregs--) { 1344 off_t size; 1345 1346 if (ddi_dev_regsize(dip, nintrs, &size) == 1347 DDI_SUCCESS) { 1348 cmn_err(CE_CONT, 1349 "\tregnum %d size %ld (0x%lx)" 1350 "bytes", 1351 nintrs, size, size); 1352 if (nintrs == 1353 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1354 PCIC_ISA_CONTROL_REG_NUM : 1355 PCIC_PCI_CONTROL_REG_NUM)) 1356 cmn_err(CE_CONT, 1357 " mapped at: 0x%p\n", 1358 (void *)pcic->ioaddr); 1359 else 1360 cmn_err(CE_CONT, "\n"); 1361 } else { 1362 cmn_err(CE_CONT, 1363 "\tddi_dev_regsize(rnumber" 1364 "= %d) returns DDI_FAILURE\n", 1365 nintrs); 1366 } 1367 nintrs++; 1368 } /* while */ 1369 } /* if (pcic_debug) */ 1370 #endif 1371 1372 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1373 1374 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1375 "disable-audio", 0)) 1376 pcic->pc_flags |= PCF_AUDIO; 1377 1378 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1379 "disable-cardbus", 0)) 1380 pcic->pc_flags &= ~PCF_CARDBUS; 1381 1382 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1383 typename); 1384 1385 /* 1386 * Init all socket SMI levels to 0 (no SMI) 1387 */ 1388 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1389 pcic->pc_sockets[i].pcs_smi = 0; 1390 pcic->pc_sockets[i].pcs_debounce_id = 0; 1391 pcic->pc_sockets[i].pcs_pcic = pcic; 1392 } 1393 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1394 1395 /* 1396 * Setup the IRQ handler(s) 1397 */ 1398 switch (pcic->pc_intr_mode) { 1399 int xx; 1400 case PCIC_INTR_MODE_ISA: 1401 /* 1402 * On a non-PCI bus, we just use whatever SMI IRQ level was 1403 * specified above, and the IO IRQ levels are allocated 1404 * dynamically. 1405 */ 1406 for (xx = 15, smi = 0; xx >= 0; xx--) { 1407 if (PCIC_IRQ(xx) & 1408 PCIC_AVAIL_IRQS) { 1409 smi = pcmcia_get_intr(dip, xx); 1410 if (smi >= 0) 1411 break; 1412 } 1413 } 1414 #if defined(PCIC_DEBUG) 1415 if (pcic_debug) 1416 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1417 #endif 1418 /* init to same so share is easy */ 1419 for (i = 0; i < pcic->pc_numsockets; i++) 1420 pcic->pc_sockets[i].pcs_smi = smi; 1421 /* any special handling of IRQ levels */ 1422 if (pcic->pc_flags & PCF_MULT_IRQ) { 1423 for (i = 2; i < pcic->pc_numsockets; i++) { 1424 if ((i & 1) == 0) { 1425 int xx; 1426 for (xx = 15, smi = 0; xx >= 0; xx--) { 1427 if (PCIC_IRQ(xx) & 1428 PCIC_AVAIL_IRQS) { 1429 smi = 1430 pcmcia_get_intr(dip, 1431 xx); 1432 if (smi >= 0) 1433 break; 1434 } 1435 } 1436 } 1437 if (smi >= 0) 1438 pcic->pc_sockets[i].pcs_smi = smi; 1439 } 1440 } 1441 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1442 sizeof (ddi_intr_handle_t), KM_SLEEP); 1443 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1444 struct intrspec *ispecp; 1445 struct ddi_parent_private_data *pdp; 1446 1447 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1448 continue; 1449 else { 1450 irqlevel = pcic->pc_sockets[i].pcs_smi; 1451 } 1452 /* 1453 * now convert the allocated IRQ into an intrspec 1454 * and ask our parent to add it. Don't use 1455 * the ddi_add_intr since we don't have a 1456 * default intrspec in all cases. 1457 * 1458 * note: this sort of violates DDI but we don't 1459 * get hardware intrspecs for many of the devices. 1460 * at the same time, we know how to allocate them 1461 * so we do the right thing. 1462 */ 1463 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1464 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1465 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1466 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1467 ddi_get_name(dip)); 1468 goto isa_exit1; 1469 } 1470 1471 /* 1472 * See earlier note: 1473 * Since some devices don't have 'intrspec' 1474 * we make one up in rootnex. 1475 * 1476 * However, it is not properly initialized as 1477 * the data it needs is present in this driver 1478 * and there is no interface to pass that up. 1479 * Specially 'irqlevel' is very important and 1480 * it is part of pcic struct. 1481 * 1482 * Set 'intrspec' up here; otherwise adding the 1483 * interrupt will fail. 1484 */ 1485 pdp = ddi_get_parent_data(dip); 1486 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1487 ispecp->intrspec_vec = irqlevel; 1488 ispecp->intrspec_pri = pcic->pc_irq; 1489 1490 /* Stay compatible w/ PCMCIA */ 1491 pcic->pc_pri = (ddi_iblock_cookie_t) 1492 (uintptr_t)pcic->pc_irq; 1493 pcic->pc_dcookie.idev_priority = 1494 (uintptr_t)pcic->pc_pri; 1495 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1496 1497 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1498 pcic->pc_irq); 1499 1500 if (i == 0) { 1501 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1502 DDI_INTR_PRI(pcic->pc_irq)); 1503 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1504 NULL); 1505 } 1506 1507 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1508 pcic_intr, (caddr_t)pcic, NULL)) { 1509 cmn_err(CE_WARN, 1510 "%s: ddi_intr_add_handler failed", 1511 ddi_get_name(dip)); 1512 goto isa_exit2; 1513 } 1514 1515 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1516 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1517 ddi_get_name(dip)); 1518 for (j = i; j < 0; j--) 1519 (void) ddi_intr_remove_handler( 1520 pcic->pc_intr_htblp[j]); 1521 goto isa_exit2; 1522 } 1523 } 1524 break; 1525 case PCIC_INTR_MODE_PCI_1: 1526 case PCIC_INTR_MODE_PCI: 1527 /* 1528 * If we're on a PCI bus, we route all interrupts, both SMI 1529 * and IO interrupts, through a single interrupt line. 1530 * Assign the SMI IRQ level to the IO IRQ level here. 1531 */ 1532 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1533 KM_SLEEP); 1534 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1535 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1536 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1537 goto pci_exit1; 1538 1539 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1540 &pri) != DDI_SUCCESS) { 1541 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1542 goto pci_exit1; 1543 } 1544 1545 pcic->pc_pri = (void *)(uintptr_t)pri; 1546 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1547 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1548 1549 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1550 pcic_intr, (caddr_t)pcic, NULL)) 1551 goto pci_exit2; 1552 1553 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1554 (void) ddi_intr_remove_handler( 1555 pcic->pc_pci_intr_hdlp[0]); 1556 goto pci_exit2; 1557 } 1558 1559 /* Stay compatible w/ PCMCIA */ 1560 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1561 1562 /* init to same (PCI) so share is easy */ 1563 for (i = 0; i < pcic->pc_numsockets; i++) 1564 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1565 break; 1566 } 1567 1568 /* 1569 * Setup the adapter hardware to some reasonable defaults. 1570 */ 1571 mutex_enter(&pcic->pc_lock); 1572 /* mark the driver state as attached */ 1573 pcic->pc_flags |= PCF_ATTACHED; 1574 pcic_setup_adapter(pcic); 1575 1576 for (j = 0; j < pcic->pc_numsockets; j++) 1577 if (ddi_intr_add_softint(dip, 1578 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1579 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1580 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1581 goto pci_exit2; 1582 1583 #if defined(PCIC_DEBUG) 1584 if (pcic_debug) 1585 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1586 pcic->pc_numsockets); 1587 #endif 1588 1589 pcic_nexus->an_iblock = &pcic->pc_pri; 1590 pcic_nexus->an_idev = &pcic->pc_dcookie; 1591 1592 mutex_exit(&pcic->pc_lock); 1593 1594 #ifdef CARDBUS 1595 (void) cardbus_enable_cd_intr(dip); 1596 if (pcic_debug) { 1597 1598 cardbus_dump_pci_config(dip); 1599 cardbus_dump_socket(dip); 1600 } 1601 1602 /* 1603 * Give the Cardbus misc module a chance to do it's per-adapter 1604 * instance setup. Note that there is no corresponding detach() 1605 * call. 1606 */ 1607 if (pcic->pc_flags & PCF_CARDBUS) 1608 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1609 cmn_err(CE_CONT, 1610 "pcic_attach: cardbus_attach failed\n"); 1611 goto pci_exit2; 1612 } 1613 #endif 1614 1615 /* 1616 * Give the PCMCIA misc module a chance to do it's per-adapter 1617 * instance setup. 1618 */ 1619 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1620 goto pci_exit2; 1621 1622 syshw_attach(pcic); 1623 if (pcic_maxinst == -1) { 1624 /* This assumes that all instances run at the same IPL. */ 1625 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1626 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1627 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1628 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1629 v.v_maxsyspri - 2); 1630 } 1631 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1632 /* 1633 * Setup a debounce timeout to do an initial card detect 1634 * and enable interrupts. 1635 */ 1636 for (j = 0; j < pcic->pc_numsockets; j++) { 1637 shwp = kmem_alloc(sizeof (syshw_t), KM_SLEEP); 1638 if (shwp) { 1639 bcopy(&pcic_syshw, shwp, sizeof (pcic_syshw)); 1640 pcic_syshw.id_string[15]++; 1641 pcic->pc_sockets[j].pcs_syshwsig = 1642 syshw_add2map(shwp, pcic_syshw_cardstate, 1643 &pcic->pc_sockets[j]); 1644 } 1645 pcic->pc_sockets[j].pcs_debounce_id = 1646 pcic_add_debqueue(&pcic->pc_sockets[j], 1647 drv_usectohz(pcic_debounce_time)); 1648 } 1649 1650 return (i); 1651 1652 isa_exit2: 1653 mutex_destroy(&pcic->intr_lock); 1654 mutex_destroy(&pcic->pc_lock); 1655 for (j = i; j < 0; j--) 1656 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1657 isa_exit1: 1658 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1659 ddi_regs_map_free(&pcic->handle); 1660 if (pcic->pc_flags & PCF_PCIBUS) 1661 ddi_regs_map_free(&pcic->cfg_handle); 1662 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1663 sizeof (ddi_intr_handle_t)); 1664 kmem_free(pcic, sizeof (pcicdev_t)); 1665 return (DDI_FAILURE); 1666 1667 pci_exit2: 1668 mutex_destroy(&pcic->intr_lock); 1669 mutex_destroy(&pcic->pc_lock); 1670 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1671 pci_exit1: 1672 ddi_regs_map_free(&pcic->handle); 1673 if (pcic->pc_flags & PCF_PCIBUS) 1674 ddi_regs_map_free(&pcic->cfg_handle); 1675 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1676 kmem_free(pcic, sizeof (pcicdev_t)); 1677 return (DDI_FAILURE); 1678 } 1679 1680 /* 1681 * pcic_detach() 1682 * request to detach from the system 1683 */ 1684 static int 1685 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1686 { 1687 anp_t *anp = ddi_get_driver_private(dip); 1688 pcicdev_t *pcic = anp->an_private; 1689 int i; 1690 1691 switch (cmd) { 1692 case DDI_DETACH: 1693 /* don't detach if the nexus still talks to us */ 1694 if (pcic->pc_callback != NULL) 1695 return (DDI_FAILURE); 1696 syshw_detach(pcic); 1697 1698 /* kill off the pm simulation */ 1699 if (pcic->pc_pmtimer) 1700 (void) untimeout(pcic->pc_pmtimer); 1701 1702 /* turn everything off for all sockets and chips */ 1703 for (i = 0; i < pcic->pc_numsockets; i++) { 1704 if (pcic->pc_sockets[i].pcs_debounce_id) 1705 pcic_rm_debqueue( 1706 pcic->pc_sockets[i].pcs_debounce_id); 1707 pcic->pc_sockets[i].pcs_debounce_id = 0; 1708 1709 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1710 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1711 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1712 /* disable interrupts and put card into RESET */ 1713 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1714 } 1715 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1716 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1717 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1718 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1719 pcic->pc_flags = 0; 1720 mutex_destroy(&pcic->pc_lock); 1721 mutex_destroy(&pcic->intr_lock); 1722 cv_destroy(&pcic->pm_cv); 1723 if (pcic->pc_flags & PCF_PCIBUS) 1724 ddi_regs_map_free(&pcic->cfg_handle); 1725 if (pcic->handle) 1726 ddi_regs_map_free(&pcic->handle); 1727 kmem_free(pcic, sizeof (pcicdev_t)); 1728 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1729 return (DDI_SUCCESS); 1730 1731 case DDI_SUSPEND: 1732 case DDI_PM_SUSPEND: 1733 /* 1734 * we got a suspend event (either real or imagined) 1735 * so notify the nexus proper that all existing cards 1736 * should go away. 1737 */ 1738 mutex_enter(&pcic->pc_lock); 1739 #ifdef CARDBUS 1740 if (pcic->pc_flags & PCF_CARDBUS) 1741 for (i = 0; i < pcic->pc_numsockets; i++) 1742 if ((pcic->pc_sockets[i].pcs_flags & 1743 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1744 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) 1745 if (!cardbus_can_suspend(dip)) { 1746 mutex_exit(&pcic->pc_lock); 1747 cmn_err(CE_WARN, 1748 "Please unconfigure all " 1749 "CardBus devices before " 1750 "attempting to suspend\n"); 1751 return (DDI_FAILURE); 1752 } 1753 #endif 1754 /* turn everything off for all sockets and chips */ 1755 for (i = 0; i < pcic->pc_numsockets; i++) { 1756 if (pcic->pc_sockets[i].pcs_debounce_id) 1757 pcic_rm_debqueue( 1758 pcic->pc_sockets[i].pcs_debounce_id); 1759 pcic->pc_sockets[i].pcs_debounce_id = 0; 1760 1761 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1762 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1763 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1764 /* disable interrupts and put card into RESET */ 1765 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1766 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1767 if (pcic->pc_flags & PCF_CBPWRCTL) 1768 pcic_putcb(pcic, CB_CONTROL, 0); 1769 1770 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1771 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1772 /* 1773 * Because we are half way through a save 1774 * all this does is schedule a removal event 1775 * to cs for when the system comes back. 1776 * This doesn't actually matter. 1777 */ 1778 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1779 pcic->pc_callback) { 1780 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1781 PCE_CARD_REMOVAL, 1782 pcic->pc_sockets[i].pcs_socket); 1783 } 1784 } 1785 } 1786 1787 pcic->pc_flags |= PCF_SUSPENDED; 1788 mutex_exit(&pcic->pc_lock); 1789 pcic_delayed_resume_toid = 0; 1790 1791 /* 1792 * when true power management exists, save the adapter 1793 * state here to enable a recovery. For the emulation 1794 * condition, the state is gone 1795 */ 1796 return (DDI_SUCCESS); 1797 1798 default: 1799 return (EINVAL); 1800 } 1801 } 1802 1803 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1804 static uint32_t pcic_tisysctl_offbits = 0; 1805 static uint32_t pcic_default_latency = 0x40; 1806 1807 static void 1808 pcic_setup_adapter(pcicdev_t *pcic) 1809 { 1810 int i; 1811 int value, flags; 1812 1813 if (pcic->pc_flags & PCF_PCIBUS) { 1814 /* 1815 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1816 */ 1817 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1818 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1819 } 1820 /* enable each socket */ 1821 for (i = 0; i < pcic->pc_numsockets; i++) { 1822 pcic->pc_sockets[i].pcs_flags = 0; 1823 /* find out the socket capabilities (I/O vs memory) */ 1824 value = pcic_getb(pcic, i, 1825 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1826 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1827 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1828 1829 /* disable all windows just in case */ 1830 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1831 1832 switch (pcic->pc_type) { 1833 uint32_t cfg32; 1834 uint16_t cfg16; 1835 uint8_t cfg; 1836 1837 /* enable extended registers for Vadem */ 1838 case PCIC_VADEM_VG469: 1839 case PCIC_VADEM: 1840 1841 /* enable card status change interrupt for socket */ 1842 break; 1843 1844 case PCIC_I82365SL: 1845 break; 1846 1847 case PCIC_CL_PD6710: 1848 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1849 break; 1850 1851 /* 1852 * On the CL_6730, we need to set up the interrupt 1853 * signalling mode (PCI mode) and set the SMI and 1854 * IRQ interrupt lines to PCI/level-mode. 1855 */ 1856 case PCIC_CL_PD6730: 1857 switch (pcic->pc_intr_mode) { 1858 case PCIC_INTR_MODE_PCI_1: 1859 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1860 ((clext_reg_read(pcic, i, 1861 PCIC_CLEXT_MISC_CTL_3) & 1862 ~PCIC_CLEXT_INT_PCI) | 1863 PCIC_CLEXT_INT_PCI)); 1864 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1865 (PCIC_CLEXT_IRQ_LVL_MODE | 1866 PCIC_CLEXT_SMI_LVL_MODE)); 1867 cfg = PCIC_CL_LP_DYN_MODE; 1868 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1869 break; 1870 case PCIC_INTR_MODE_ISA: 1871 break; 1872 } 1873 break; 1874 /* 1875 * On the CL_6729, we set the SMI and IRQ interrupt 1876 * lines to PCI/level-mode. as well as program the 1877 * correct clock speed divider bit. 1878 */ 1879 case PCIC_CL_PD6729: 1880 switch (pcic->pc_intr_mode) { 1881 case PCIC_INTR_MODE_PCI_1: 1882 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1883 (PCIC_CLEXT_IRQ_LVL_MODE | 1884 PCIC_CLEXT_SMI_LVL_MODE)); 1885 1886 break; 1887 case PCIC_INTR_MODE_ISA: 1888 break; 1889 } 1890 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1891 cfg = 0; 1892 cfg |= PCIC_CL_TIMER_CLK_DIV; 1893 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1894 } 1895 break; 1896 case PCIC_INTEL_i82092: 1897 cfg = PCIC_82092_EN_TIMING; 1898 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1899 cfg |= PCIC_82092_PCICLK_25MHZ; 1900 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1901 PCIC_82092_PCICON, cfg); 1902 break; 1903 case PCIC_TI_PCI1130: 1904 case PCIC_TI_PCI1131: 1905 case PCIC_TI_PCI1250: 1906 case PCIC_TI_PCI1031: 1907 cfg = ddi_get8(pcic->cfg_handle, 1908 pcic->cfgaddr + PCIC_DEVCTL_REG); 1909 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1910 switch (pcic->pc_intr_mode) { 1911 case PCIC_INTR_MODE_ISA: 1912 cfg |= PCIC_DEVCTL_INTR_ISA; 1913 break; 1914 } 1915 #ifdef PCIC_DEBUG 1916 if (pcic_debug) { 1917 cmn_err(CE_CONT, "pcic_setup_adapter: " 1918 "write reg 0x%x=%x \n", 1919 PCIC_DEVCTL_REG, cfg); 1920 } 1921 #endif 1922 ddi_put8(pcic->cfg_handle, 1923 pcic->cfgaddr + PCIC_DEVCTL_REG, 1924 cfg); 1925 1926 cfg = ddi_get8(pcic->cfg_handle, 1927 pcic->cfgaddr + PCIC_CRDCTL_REG); 1928 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1929 PCIC_CRDCTL_PCIFUNC); 1930 switch (pcic->pc_intr_mode) { 1931 case PCIC_INTR_MODE_PCI_1: 1932 cfg |= PCIC_CRDCTL_PCIINTR | 1933 PCIC_CRDCTL_PCICSC | 1934 PCIC_CRDCTL_PCIFUNC; 1935 pcic->pc_flags |= PCF_USE_SMI; 1936 break; 1937 } 1938 #ifdef PCIC_DEBUG 1939 if (pcic_debug) { 1940 cmn_err(CE_CONT, "pcic_setup_adapter: " 1941 " write reg 0x%x=%x \n", 1942 PCIC_CRDCTL_REG, cfg); 1943 } 1944 #endif 1945 ddi_put8(pcic->cfg_handle, 1946 pcic->cfgaddr + PCIC_CRDCTL_REG, 1947 cfg); 1948 break; 1949 case PCIC_TI_PCI1221: 1950 case PCIC_TI_PCI1225: 1951 cfg = ddi_get8(pcic->cfg_handle, 1952 pcic->cfgaddr + PCIC_DEVCTL_REG); 1953 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1954 #ifdef PCIC_DEBUG 1955 if (pcic_debug) { 1956 cmn_err(CE_CONT, "pcic_setup_adapter: " 1957 " write reg 0x%x=%x \n", 1958 PCIC_DEVCTL_REG, cfg); 1959 } 1960 #endif 1961 ddi_put8(pcic->cfg_handle, 1962 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1963 1964 cfg = ddi_get8(pcic->cfg_handle, 1965 pcic->cfgaddr + PCIC_DIAG_REG); 1966 if (pcic->pc_type == PCIC_TI_PCI1225) { 1967 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1968 } else { 1969 cfg |= PCIC_DIAG_ASYNC; 1970 } 1971 pcic->pc_flags |= PCF_USE_SMI; 1972 #ifdef PCIC_DEBUG 1973 if (pcic_debug) { 1974 cmn_err(CE_CONT, "pcic_setup_adapter: " 1975 " write reg 0x%x=%x \n", 1976 PCIC_DIAG_REG, cfg); 1977 } 1978 #endif 1979 ddi_put8(pcic->cfg_handle, 1980 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1981 break; 1982 case PCIC_TI_PCI1520: 1983 case PCIC_TI_PCI1510: 1984 case PCIC_TI_VENDOR: 1985 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1986 cfg = ddi_get8(pcic->cfg_handle, 1987 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1988 cfg |= PCIC_FUN_INT_MOD_ISA; 1989 ddi_put8(pcic->cfg_handle, 1990 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1991 cfg); 1992 } 1993 cfg = ddi_get8(pcic->cfg_handle, 1994 pcic->cfgaddr + PCIC_DEVCTL_REG); 1995 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1996 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) 1997 cfg |= PCIC_DEVCTL_INTR_ISA; 1998 ddi_put8(pcic->cfg_handle, 1999 pcic->cfgaddr + PCIC_DEVCTL_REG, 2000 cfg); 2001 2002 /* tie INTA and INTB together */ 2003 cfg = ddi_get8(pcic->cfg_handle, 2004 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 2005 cfg |= PCIC_SYSCTL_INTRTIE; 2006 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 2007 PCIC_SYSCTL_REG + 3), cfg); 2008 cfg = ddi_get8(pcic->cfg_handle, 2009 pcic->cfgaddr + PCIC_DIAG_REG); 2010 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2011 ddi_put8(pcic->cfg_handle, 2012 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2013 break; 2014 case PCIC_TI_PCI1410: 2015 cfg = ddi_get8(pcic->cfg_handle, 2016 pcic->cfgaddr + PCIC_DIAG_REG); 2017 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2018 ddi_put8(pcic->cfg_handle, 2019 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2020 break; 2021 case PCIC_TOSHIBA_TOPIC100: 2022 case PCIC_TOSHIBA_TOPIC95: 2023 case PCIC_TOSHIBA_VENDOR: 2024 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2025 PCIC_TOSHIBA_SLOT_CTL_REG); 2026 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 2027 PCIC_TOSHIBA_SCR_SLOTEN); 2028 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 2029 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 2030 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 2031 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 2032 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2033 PCIC_TOSHIBA_INTR_CTL_REG); 2034 switch (pcic->pc_intr_mode) { 2035 case PCIC_INTR_MODE_ISA: 2036 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 2037 ddi_put8(pcic->cfg_handle, 2038 pcic->cfgaddr + 2039 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2040 2041 cfg = ddi_get8(pcic->cfg_handle, 2042 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2043 cfg |= PCIC_FUN_INT_MOD_ISA; 2044 ddi_put8(pcic->cfg_handle, 2045 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2046 cfg); 2047 break; 2048 case PCIC_INTR_MODE_PCI_1: 2049 cfg |= PCIC_TOSHIBA_ICR_SRC; 2050 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 2051 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 2052 ddi_put8(pcic->cfg_handle, 2053 pcic->cfgaddr + 2054 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2055 break; 2056 } 2057 break; 2058 case PCIC_O2MICRO_VENDOR: 2059 cfg32 = ddi_get32(pcic->cfg_handle, 2060 (uint32_t *)(pcic->cfgaddr + 2061 PCIC_O2MICRO_MISC_CTL)); 2062 switch (pcic->pc_intr_mode) { 2063 case PCIC_INTR_MODE_ISA: 2064 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2065 PCIC_O2MICRO_INT_MOD_PCI); 2066 ddi_put32(pcic->cfg_handle, 2067 (uint32_t *)(pcic->cfgaddr + 2068 PCIC_O2MICRO_MISC_CTL), 2069 cfg32); 2070 cfg = ddi_get8(pcic->cfg_handle, 2071 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2072 cfg |= PCIC_FUN_INT_MOD_ISA; 2073 ddi_put8(pcic->cfg_handle, 2074 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2075 cfg); 2076 break; 2077 case PCIC_INTR_MODE_PCI_1: 2078 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2079 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2080 ddi_put32(pcic->cfg_handle, 2081 (uint32_t *)(pcic->cfgaddr + 2082 PCIC_O2MICRO_MISC_CTL), 2083 cfg32); 2084 break; 2085 } 2086 break; 2087 case PCIC_RICOH_VENDOR: 2088 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2089 cfg16 = ddi_get16(pcic->cfg_handle, 2090 (uint16_t *)(pcic->cfgaddr + 2091 PCIC_RICOH_MISC_CTL_2)); 2092 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2093 PCIC_RICOH_FUN_INT_MOD); 2094 ddi_put16(pcic->cfg_handle, 2095 (uint16_t *)(pcic->cfgaddr + 2096 PCIC_RICOH_MISC_CTL_2), 2097 cfg16); 2098 2099 cfg16 = ddi_get16(pcic->cfg_handle, 2100 (uint16_t *)(pcic->cfgaddr + 2101 PCIC_RICOH_MISC_CTL)); 2102 cfg16 |= PCIC_RICOH_SIRQ_EN; 2103 ddi_put16(pcic->cfg_handle, 2104 (uint16_t *)(pcic->cfgaddr + 2105 PCIC_RICOH_MISC_CTL), 2106 cfg16); 2107 2108 cfg = ddi_get8(pcic->cfg_handle, 2109 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2110 cfg |= PCIC_FUN_INT_MOD_ISA; 2111 ddi_put8(pcic->cfg_handle, 2112 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2113 cfg); 2114 } 2115 break; 2116 default: 2117 break; 2118 } /* switch */ 2119 2120 /* 2121 * The default value in the EEPROM (loaded on reset) for 2122 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that 2123 * MFUNC0 is connected to INTA, and MFUNC1 is connected to 2124 * INTB. This applies to all TI CardBus controllers. 2125 */ 2126 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID && 2127 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) { 2128 value = ddi_get32(pcic->cfg_handle, 2129 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG)); 2130 value &= ~0xff; 2131 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr + 2132 PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL); 2133 } 2134 2135 /* setup general card status change interrupt */ 2136 switch (pcic->pc_type) { 2137 case PCIC_TI_PCI1225: 2138 case PCIC_TI_PCI1221: 2139 case PCIC_TI_PCI1031: 2140 case PCIC_TI_PCI1520: 2141 case PCIC_TI_PCI1410: 2142 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2143 PCIC_CHANGE_DEFAULT); 2144 break; 2145 default: 2146 if (pcic->pc_intr_mode == 2147 PCIC_INTR_MODE_PCI_1) { 2148 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2149 PCIC_CHANGE_DEFAULT); 2150 break; 2151 } else { 2152 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2153 PCIC_CHANGE_DEFAULT | 2154 (pcic->pc_sockets[i].pcs_smi << 4)); 2155 break; 2156 } 2157 } 2158 2159 pcic->pc_flags |= PCF_INTRENAB; 2160 2161 /* take card out of RESET */ 2162 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2163 /* turn power off and let CS do this */ 2164 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2165 2166 /* final chip specific initialization */ 2167 switch (pcic->pc_type) { 2168 case PCIC_VADEM: 2169 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2170 PCIC_VC_DELAYENABLE); 2171 pcic->pc_flags |= PCF_DEBOUNCE; 2172 /* FALLTHROUGH */ 2173 case PCIC_I82365SL: 2174 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2175 PCIC_GC_CSC_WRITE); 2176 /* clear any pending interrupts */ 2177 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2178 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2179 break; 2180 /* The 82092 uses PCI config space to enable interrupts */ 2181 case PCIC_INTEL_i82092: 2182 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2183 PCIC_82092_INT_ENABLE); 2184 break; 2185 case PCIC_CL_PD6729: 2186 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2187 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2188 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2189 value | PCIC_CL_TIMER_CLK_DIV); 2190 } 2191 break; 2192 } /* switch */ 2193 2194 #if defined(PCIC_DEBUG) 2195 if (pcic_debug) 2196 cmn_err(CE_CONT, 2197 "socket %d value=%x, flags = %x (%s)\n", 2198 i, value, pcic->pc_sockets[i].pcs_flags, 2199 (pcic->pc_sockets[i].pcs_flags & 2200 PCS_CARD_PRESENT) ? 2201 "card present" : "no card"); 2202 #endif 2203 } 2204 } 2205 2206 /* 2207 * pcic_intr(caddr_t, caddr_t) 2208 * interrupt handler for the PCIC style adapter 2209 * handles all basic interrupts and also checks 2210 * for status changes and notifies the nexus if 2211 * necessary 2212 * 2213 * On PCI bus adapters, also handles all card 2214 * IO interrupts. 2215 */ 2216 /*ARGSUSED*/ 2217 uint32_t 2218 pcic_intr(caddr_t arg1, caddr_t arg2) 2219 { 2220 pcicdev_t *pcic = (pcicdev_t *)arg1; 2221 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2222 uint8_t status; 2223 uint_t io_ints; 2224 2225 #if defined(PCIC_DEBUG) 2226 pcic_err(pcic->dip, 0xf, 2227 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2228 " pc_numsockets=%d \n", 2229 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2230 #endif 2231 2232 if (!(pcic->pc_flags & PCF_ATTACHED)) 2233 return (DDI_INTR_UNCLAIMED); 2234 2235 mutex_enter(&pcic->intr_lock); 2236 2237 if (pcic->pc_flags & PCF_SUSPENDED) { 2238 mutex_exit(&pcic->intr_lock); 2239 return (ret); 2240 } 2241 2242 /* 2243 * need to change to only ACK and touch the slot that 2244 * actually caused the interrupt. Currently everything 2245 * is acked 2246 * 2247 * we need to look at all known sockets to determine 2248 * what might have happened, so step through the list 2249 * of them 2250 */ 2251 #ifdef VOYAGER 2252 ret = syshw_intr_hi(pcic); 2253 #endif 2254 2255 /* 2256 * Set the bitmask for IO interrupts to initially include all sockets 2257 */ 2258 io_ints = (1 << pcic->pc_numsockets) - 1; 2259 2260 for (i = 0; i < pcic->pc_numsockets; i++) { 2261 int card_type; 2262 pcic_socket_t *sockp; 2263 int value_cb = 0; 2264 2265 sockp = &pcic->pc_sockets[i]; 2266 /* get the socket's I/O addresses */ 2267 2268 if (sockp->pcs_flags & PCS_WAITING) { 2269 io_ints &= ~(1 << i); 2270 continue; 2271 } 2272 2273 if (sockp->pcs_flags & PCS_CARD_IO) 2274 card_type = IF_IO; 2275 else 2276 card_type = IF_MEMORY; 2277 2278 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2279 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2280 2281 value = pcic_change(pcic, i); 2282 2283 if ((value != 0) || (value_cb != 0)) { 2284 int x = pcic->pc_cb_arg; 2285 2286 ret = DDI_INTR_CLAIMED; 2287 2288 #if defined(PCIC_DEBUG) 2289 pcic_err(pcic->dip, 0x9, 2290 "card_type = %d, value_cb = 0x%x\n", 2291 card_type, 2292 value_cb ? value_cb : 2293 pcic_getcb(pcic, CB_STATUS_EVENT)); 2294 if (pcic_debug) 2295 cmn_err(CE_CONT, 2296 "\tchange on socket %d (%x)\n", i, 2297 value); 2298 #endif 2299 /* find out what happened */ 2300 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2301 2302 /* acknowledge the interrupt */ 2303 if (value_cb) 2304 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2305 2306 if (value) 2307 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2308 value); 2309 2310 if (pcic->pc_callback == NULL) { 2311 /* if not callback handler, nothing to do */ 2312 continue; 2313 } 2314 2315 /* Card Detect */ 2316 if (value & PCIC_CD_DETECT || 2317 value_cb & CB_PS_CCDMASK) { 2318 uint8_t irq; 2319 #if defined(PCIC_DEBUG) 2320 if (pcic_debug) 2321 cmn_err(CE_CONT, 2322 "\tcd_detect: status=%x," 2323 " flags=%x\n", 2324 status, sockp->pcs_flags); 2325 #else 2326 #ifdef lint 2327 if (status == 0) 2328 status++; 2329 #endif 2330 #endif 2331 /* 2332 * Turn off all interrupts for this socket here. 2333 */ 2334 irq = pcic_getb(pcic, sockp->pcs_socket, 2335 PCIC_MANAGEMENT_INT); 2336 irq &= ~PCIC_CHANGE_MASK; 2337 pcic_putb(pcic, sockp->pcs_socket, 2338 PCIC_MANAGEMENT_INT, irq); 2339 2340 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2341 2342 /* 2343 * Put the socket in debouncing state so that 2344 * the leaf driver won't receive interrupts. 2345 * Crucial for handling surprise-removal. 2346 */ 2347 sockp->pcs_flags |= PCS_DEBOUNCING; 2348 2349 if (!sockp->pcs_cd_softint_flg) { 2350 sockp->pcs_cd_softint_flg = 1; 2351 (void) ddi_intr_trigger_softint( 2352 sockp->pcs_cd_softint_hdl, NULL); 2353 } 2354 2355 io_ints &= ~(1 << i); 2356 } /* PCIC_CD_DETECT */ 2357 2358 /* Ready/Change Detect */ 2359 sockp->pcs_state ^= SBM_RDYBSY; 2360 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2361 sockp->pcs_flags |= PCS_READY; 2362 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2363 } 2364 2365 /* Battery Warn Detect */ 2366 if (card_type == IF_MEMORY && 2367 value & PCIC_BW_DETECT && 2368 !(sockp->pcs_state & SBM_BVD2)) { 2369 sockp->pcs_state |= SBM_BVD2; 2370 PC_CALLBACK(pcic->dip, x, 2371 PCE_CARD_BATTERY_WARN, i); 2372 } 2373 2374 /* Battery Dead Detect */ 2375 if (value & PCIC_BD_DETECT) { 2376 /* 2377 * need to work out event if RI not enabled 2378 * and card_type == IF_IO 2379 */ 2380 if (card_type == IF_MEMORY && 2381 !(sockp->pcs_state & SBM_BVD1)) { 2382 sockp->pcs_state |= SBM_BVD1; 2383 PC_CALLBACK(pcic->dip, x, 2384 PCE_CARD_BATTERY_DEAD, 2385 i); 2386 } else { 2387 /* 2388 * information in pin replacement 2389 * register if one is available 2390 */ 2391 PC_CALLBACK(pcic->dip, x, 2392 PCE_CARD_STATUS_CHANGE, 2393 i); 2394 } /* IF_MEMORY */ 2395 } /* PCIC_BD_DETECT */ 2396 } /* if pcic_change */ 2397 /* 2398 * for any controllers that we can detect whether a socket 2399 * had an interrupt for the PC Card, we should sort that out 2400 * here. 2401 */ 2402 } /* for pc_numsockets */ 2403 2404 /* 2405 * If we're on a PCI bus, we may need to cycle through each IO 2406 * interrupt handler that is registered since they all 2407 * share the same interrupt line. 2408 */ 2409 2410 2411 #if defined(PCIC_DEBUG) 2412 pcic_err(pcic->dip, 0xf, 2413 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2414 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2415 #endif 2416 2417 if (io_ints) { 2418 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED) 2419 ret = DDI_INTR_CLAIMED; 2420 } 2421 2422 mutex_exit(&pcic->intr_lock); 2423 2424 #if defined(PCIC_DEBUG) 2425 pcic_err(pcic->dip, 0xf, 2426 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2427 ret, value, DDI_INTR_CLAIMED); 2428 #endif 2429 2430 return (ret); 2431 } 2432 2433 /* 2434 * pcic_change() 2435 * check to see if this socket had a change in state 2436 * by checking the status change register 2437 */ 2438 static int 2439 pcic_change(pcicdev_t *pcic, int socket) 2440 { 2441 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2442 } 2443 2444 /* 2445 * pcic_do_io_intr - calls client interrupt handlers 2446 */ 2447 static int 2448 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2449 { 2450 inthandler_t *tmp; 2451 int ret = DDI_INTR_UNCLAIMED; 2452 2453 #if defined(PCIC_DEBUG) 2454 pcic_err(pcic->dip, 0xf, 2455 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2456 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2457 #endif 2458 2459 if (pcic->irq_top != NULL) { 2460 tmp = pcic->irq_current; 2461 2462 do { 2463 int cur = pcic->irq_current->socket; 2464 pcic_socket_t *sockp = 2465 &pcic->pc_sockets[cur]; 2466 2467 #if defined(PCIC_DEBUG) 2468 pcic_err(pcic->dip, 0xf, 2469 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2470 sockp->pcs_flags, PCS_CARD_PRESENT); 2471 pcic_err(pcic->dip, 0xf, 2472 "\t sockets=%d cur=%d intr=%p arg1=%p " 2473 "arg2=%p\n", 2474 sockets, cur, (void *)pcic->irq_current->intr, 2475 pcic->irq_current->arg1, 2476 pcic->irq_current->arg2); 2477 #endif 2478 if ((sockp->pcs_flags & PCS_CARD_PRESENT) && 2479 !(sockp->pcs_flags & PCS_DEBOUNCING) && 2480 (sockets & (1 << cur))) { 2481 2482 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2483 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2484 ret = DDI_INTR_CLAIMED; 2485 2486 #if defined(PCIC_DEBUG) 2487 pcic_err(pcic->dip, 0xf, 2488 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2489 ret, DDI_INTR_CLAIMED); 2490 #endif 2491 } 2492 2493 2494 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2495 pcic->irq_current = pcic->irq_top; 2496 2497 } while (pcic->irq_current != tmp); 2498 2499 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2500 pcic->irq_current = pcic->irq_top; 2501 2502 } else { 2503 ret = DDI_INTR_UNCLAIMED; 2504 } 2505 2506 #if defined(PCIC_DEBUG) 2507 pcic_err(pcic->dip, 0xf, 2508 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2509 ret, DDI_INTR_CLAIMED); 2510 #endif 2511 2512 return (ret); 2513 2514 } 2515 2516 /* 2517 * pcic_inquire_adapter() 2518 * SocketServices InquireAdapter function 2519 * get characteristics of the physical adapter 2520 */ 2521 /*ARGSUSED*/ 2522 static int 2523 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2524 { 2525 anp_t *anp = ddi_get_driver_private(dip); 2526 pcicdev_t *pcic = anp->an_private; 2527 2528 config->NumSockets = pcic->pc_numsockets; 2529 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2530 config->NumEDCs = 0; 2531 config->AdpCaps = 0; 2532 config->ActiveHigh = 0; 2533 config->ActiveLow = PCIC_AVAIL_IRQS; 2534 config->NumPower = pcic->pc_numpower; 2535 config->power_entry = pcic->pc_power; /* until we resolve this */ 2536 #if defined(PCIC_DEBUG) 2537 if (pcic_debug) { 2538 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2539 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2540 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2541 } 2542 #endif 2543 config->ResourceFlags = 0; 2544 switch (pcic->pc_intr_mode) { 2545 case PCIC_INTR_MODE_PCI_1: 2546 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2547 RES_IRQ_SHAREABLE; 2548 break; 2549 } 2550 return (SUCCESS); 2551 } 2552 2553 /* 2554 * pcic_callback() 2555 * The PCMCIA nexus calls us via this function 2556 * in order to set the callback function we are 2557 * to call the nexus with 2558 */ 2559 /*ARGSUSED*/ 2560 static int 2561 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2562 { 2563 anp_t *anp = ddi_get_driver_private(dip); 2564 pcicdev_t *pcic = anp->an_private; 2565 2566 if (handler != NULL) { 2567 pcic->pc_callback = handler; 2568 pcic->pc_cb_arg = arg; 2569 pcic->pc_flags |= PCF_CALLBACK; 2570 } else { 2571 pcic->pc_callback = NULL; 2572 pcic->pc_cb_arg = 0; 2573 pcic->pc_flags &= ~PCF_CALLBACK; 2574 } 2575 /* 2576 * we're now registered with the nexus 2577 * it is acceptable to do callbacks at this point. 2578 * don't call back from here though since it could block 2579 */ 2580 return (PC_SUCCESS); 2581 } 2582 2583 /* 2584 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2585 * calculate the speed bits from the specified memory speed 2586 * there may be more to do here 2587 */ 2588 2589 static int 2590 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2591 { 2592 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2593 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2594 2595 switch (pcic->pc_type) { 2596 case PCIC_I82365SL: 2597 case PCIC_VADEM: 2598 case PCIC_VADEM_VG469: 2599 default: 2600 /* Intel chip wants it in waitstates */ 2601 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2602 if (speed <= wspeed) 2603 wspeed = 0; 2604 else if (speed <= (wspeed += mhztons(bspeed))) 2605 wspeed = 1; 2606 else if (speed <= (wspeed += mhztons(bspeed))) 2607 wspeed = 2; 2608 else 2609 wspeed = 3; 2610 wspeed <<= 6; /* put in right bit positions */ 2611 break; 2612 2613 case PCIC_INTEL_i82092: 2614 wspeed = SYSMEM_82092_80NS; 2615 if (speed > 80) 2616 wspeed = SYSMEM_82092_100NS; 2617 if (speed > 100) 2618 wspeed = SYSMEM_82092_150NS; 2619 if (speed > 150) 2620 wspeed = SYSMEM_82092_200NS; 2621 if (speed > 200) 2622 wspeed = SYSMEM_82092_250NS; 2623 if (speed > 250) 2624 wspeed = SYSMEM_82092_600NS; 2625 wspeed <<= 5; /* put in right bit positions */ 2626 break; 2627 2628 } /* switch */ 2629 2630 return (wspeed); 2631 } 2632 2633 /* 2634 * These values are taken from the PC Card Standard Electrical Specification. 2635 * Generally the larger value is taken if 2 are possible. 2636 */ 2637 static struct pcic_card_times { 2638 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2639 uint16_t setup; /* Corresponding address setup time. */ 2640 uint16_t width; /* Corresponding width, OE or WE. */ 2641 uint16_t hold; /* Corresponding data or address hold time. */ 2642 } pcic_card_times[] = { 2643 2644 /* 2645 * Note: The rounded up times for 250, 200 & 150 have been increased 2646 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2647 * See BugID 00663. 2648 */ 2649 2650 /* 2651 * Rounded up times Original times from 2652 * that add up to the the PCMCIA Spec. 2653 * cycle time. 2654 */ 2655 {600, 180, 370, 140}, /* 100, 300, 70 */ 2656 {400, 120, 300, 90}, /* Made this one up */ 2657 {250, 100, 190, 70}, /* 30, 150, 30 */ 2658 {200, 80, 170, 70}, /* 20, 120, 30 */ 2659 {150, 50, 110, 40}, /* 20, 80, 20 */ 2660 {100, 40, 80, 40}, /* 10, 60, 15 */ 2661 {0, 10, 60, 15} /* 10, 60, 15 */ 2662 }; 2663 2664 /* 2665 * pcic_set_cdtimers 2666 * This is specific to several Cirrus Logic chips 2667 */ 2668 static void 2669 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2670 { 2671 int cmd, set, rec, offset, clk_pulse; 2672 struct pcic_card_times *ctp; 2673 2674 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2675 offset = 3; 2676 else 2677 offset = 0; 2678 2679 clk_pulse = mhztons(pcic->bus_speed); 2680 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++); 2681 2682 /* 2683 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2684 */ 2685 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2686 if (set < 0) 2687 set = 0; 2688 2689 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2690 if (cmd < 0) 2691 cmd = 0; 2692 2693 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2694 if (rec < 0) 2695 rec = 0; 2696 2697 #if defined(PCIC_DEBUG) 2698 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2699 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2700 (unsigned)speed, offset == 3 ? 1 : 0, 2701 ctp->cycle, clk_pulse, cmd, set, rec); 2702 #endif 2703 2704 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2705 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2706 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2707 } 2708 2709 /* 2710 * pcic_set_window 2711 * essentially the same as the Socket Services specification 2712 * We use socket and not adapter since they are identifiable 2713 * but the rest is the same 2714 * 2715 * dip pcic driver's device information 2716 * window parameters for the request 2717 */ 2718 static int 2719 pcic_set_window(dev_info_t *dip, set_window_t *window) 2720 { 2721 anp_t *anp = ddi_get_driver_private(dip); 2722 pcicdev_t *pcic = anp->an_private; 2723 int select; 2724 int socket, pages, which, ret; 2725 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2726 ra_return_t res; 2727 ndi_ra_request_t req; 2728 uint32_t base = window->base; 2729 2730 #if defined(PCIC_DEBUG) 2731 if (pcic_debug) { 2732 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2733 cmn_err(CE_CONT, 2734 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2735 window->window, window->socket, window->WindowSize, 2736 window->speed); 2737 cmn_err(CE_CONT, 2738 "\tbase=%x, state=%x\n", (unsigned)window->base, 2739 (unsigned)window->state); 2740 } 2741 #endif 2742 2743 /* 2744 * do some basic sanity checking on what we support 2745 * we don't do paged mode 2746 */ 2747 if (window->state & WS_PAGED) { 2748 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2749 return (BAD_ATTRIBUTE); 2750 } 2751 2752 /* 2753 * we don't care about previous mappings. 2754 * Card Services will deal with that so don't 2755 * even check 2756 */ 2757 2758 socket = window->socket; 2759 2760 if (!(window->state & WS_IO)) { 2761 int win, tmp; 2762 pcs_memwin_t *memp; 2763 #if defined(PCIC_DEBUG) 2764 if (pcic_debug) 2765 cmn_err(CE_CONT, "\twindow type is memory\n"); 2766 #endif 2767 /* this is memory window mapping */ 2768 win = window->window % PCIC_NUMWINSOCK; 2769 tmp = window->window / PCIC_NUMWINSOCK; 2770 2771 /* only windows 2-6 can do memory mapping */ 2772 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2773 cmn_err(CE_CONT, 2774 "\tattempt to map to non-mem window\n"); 2775 return (BAD_WINDOW); 2776 } 2777 2778 if (window->WindowSize == 0) 2779 window->WindowSize = MEM_MIN; 2780 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2781 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2782 return (BAD_SIZE); 2783 } 2784 2785 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2786 2787 memp = &sockp->pcs_windows[win].mem; 2788 memp->pcw_speed = window->speed; 2789 2790 win -= PCIC_IOWINDOWS; /* put in right range */ 2791 2792 if (window->WindowSize != memp->pcw_len) 2793 which = memp->pcw_len; 2794 else 2795 which = 0; 2796 2797 if (window->state & WS_ENABLED) { 2798 uint32_t wspeed; 2799 #if defined(PCIC_DEBUG) 2800 if (pcic_debug) { 2801 cmn_err(CE_CONT, 2802 "\tbase=%x, win=%d\n", (unsigned)base, 2803 win); 2804 if (which) 2805 cmn_err(CE_CONT, 2806 "\tneed to remap window\n"); 2807 } 2808 #endif 2809 2810 if (which && (memp->pcw_status & PCW_MAPPED)) { 2811 ddi_regs_map_free(&memp->pcw_handle); 2812 res.ra_addr_lo = memp->pcw_base; 2813 res.ra_len = memp->pcw_len; 2814 (void) pcmcia_free_mem(memp->res_dip, &res); 2815 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2816 memp->pcw_hostmem = NULL; 2817 memp->pcw_base = NULL; 2818 memp->pcw_len = 0; 2819 } 2820 2821 which = window->WindowSize >> PAGE_SHIFT; 2822 2823 if (!(memp->pcw_status & PCW_MAPPED)) { 2824 ret = 0; 2825 2826 memp->pcw_base = base; 2827 bzero(&req, sizeof (req)); 2828 req.ra_len = which << PAGE_SHIFT; 2829 req.ra_addr = (uint64_t)memp->pcw_base; 2830 req.ra_boundbase = pcic->pc_base; 2831 req.ra_boundlen = pcic->pc_bound; 2832 req.ra_flags = (memp->pcw_base ? 2833 NDI_RA_ALLOC_SPECIFIED : 0) | 2834 NDI_RA_ALLOC_BOUNDED; 2835 req.ra_align_mask = 2836 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2837 #if defined(PCIC_DEBUG) 2838 pcic_err(dip, 8, 2839 "\tlen 0x%"PRIx64 2840 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2841 " blen 0x%"PRIx64" flags 0x%x" 2842 " algn 0x%"PRIx64"\n", 2843 req.ra_len, req.ra_addr, 2844 req.ra_boundbase, 2845 req.ra_boundlen, req.ra_flags, 2846 req.ra_align_mask); 2847 #endif 2848 2849 ret = pcmcia_alloc_mem(dip, &req, &res, 2850 &memp->res_dip); 2851 if (ret == DDI_FAILURE) { 2852 mutex_exit(&pcic->pc_lock); 2853 cmn_err(CE_WARN, 2854 "\tpcmcia_alloc_mem() failed\n"); 2855 return (BAD_SIZE); 2856 } 2857 memp->pcw_base = res.ra_addr_lo; 2858 base = memp->pcw_base; 2859 2860 #if defined(PCIC_DEBUG) 2861 if (pcic_debug) 2862 cmn_err(CE_CONT, 2863 "\tsetwindow: new base=%x\n", 2864 (unsigned)memp->pcw_base); 2865 #endif 2866 memp->pcw_len = window->WindowSize; 2867 2868 which = pcmcia_map_reg(pcic->dip, 2869 window->child, 2870 &res, 2871 (uint32_t)(window->state & 2872 0xffff) | 2873 (window->socket << 16), 2874 (caddr_t *)&memp->pcw_hostmem, 2875 &memp->pcw_handle, 2876 &window->attr, NULL); 2877 2878 if (which != DDI_SUCCESS) { 2879 2880 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2881 "failed\n"); 2882 2883 res.ra_addr_lo = memp->pcw_base; 2884 res.ra_len = memp->pcw_len; 2885 (void) pcmcia_free_mem(memp->res_dip, &res); 2886 2887 mutex_exit(&pcic->pc_lock); 2888 2889 return (BAD_WINDOW); 2890 } 2891 memp->pcw_status |= PCW_MAPPED; 2892 #if defined(PCIC_DEBUG) 2893 if (pcic_debug) 2894 cmn_err(CE_CONT, 2895 "\tmap=%x, hostmem=%p\n", 2896 which, 2897 (void *)memp->pcw_hostmem); 2898 #endif 2899 } else { 2900 base = memp->pcw_base; 2901 } 2902 2903 /* report the handle back to caller */ 2904 window->handle = memp->pcw_handle; 2905 2906 #if defined(PCIC_DEBUG) 2907 if (pcic_debug) { 2908 cmn_err(CE_CONT, 2909 "\twindow mapped to %x@%x len=%d\n", 2910 (unsigned)window->base, 2911 (unsigned)memp->pcw_base, 2912 memp->pcw_len); 2913 } 2914 #endif 2915 2916 /* find the register set offset */ 2917 select = win * PCIC_MEM_1_OFFSET; 2918 #if defined(PCIC_DEBUG) 2919 if (pcic_debug) 2920 cmn_err(CE_CONT, "\tselect=%x\n", select); 2921 #endif 2922 2923 /* 2924 * at this point, the register window indicator has 2925 * been converted to be an offset from the first 2926 * set of registers that are used for programming 2927 * the window mapping and the offset used to select 2928 * the correct set of registers to access the 2929 * specified socket. This allows basing everything 2930 * off the _0 window 2931 */ 2932 2933 /* map the physical page base address */ 2934 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2935 which |= (window->speed <= MEM_SPEED_MIN) ? 2936 SYSMEM_ZERO_WAIT : 0; 2937 2938 /* need to select register set */ 2939 select = PCIC_MEM_1_OFFSET * win; 2940 2941 pcic_putb(pcic, socket, 2942 PCIC_SYSMEM_0_STARTLOW + select, 2943 SYSMEM_LOW(base)); 2944 pcic_putb(pcic, socket, 2945 PCIC_SYSMEM_0_STARTHI + select, 2946 SYSMEM_HIGH(base) | which); 2947 2948 /* 2949 * Some adapters can decode window addresses greater 2950 * than 16-bits worth, so handle them here. 2951 */ 2952 switch (pcic->pc_type) { 2953 case PCIC_INTEL_i82092: 2954 pcic_putb(pcic, socket, 2955 PCIC_82092_CPAGE, 2956 SYSMEM_EXT(base)); 2957 break; 2958 case PCIC_CL_PD6729: 2959 case PCIC_CL_PD6730: 2960 clext_reg_write(pcic, socket, 2961 PCIC_CLEXT_MMAP0_UA + win, 2962 SYSMEM_EXT(base)); 2963 break; 2964 case PCIC_TI_PCI1130: 2965 /* 2966 * Note that the TI chip has one upper byte 2967 * per socket so all windows get bound to a 2968 * 16MB segment. This must be detected and 2969 * handled appropriately. We can detect that 2970 * it is done by seeing if the pc_base has 2971 * changed and changing when the register 2972 * is first set. This will force the bounds 2973 * to be correct. 2974 */ 2975 if (pcic->pc_bound == 0xffffffff) { 2976 pcic_putb(pcic, socket, 2977 PCIC_TI_WINDOW_PAGE_PCI, 2978 SYSMEM_EXT(base)); 2979 pcic->pc_base = SYSMEM_EXT(base) << 24; 2980 pcic->pc_bound = 0x1000000; 2981 } 2982 break; 2983 case PCIC_TI_PCI1031: 2984 case PCIC_TI_PCI1131: 2985 case PCIC_TI_PCI1250: 2986 case PCIC_TI_PCI1225: 2987 case PCIC_TI_PCI1221: 2988 case PCIC_SMC_34C90: 2989 case PCIC_CL_PD6832: 2990 case PCIC_RICOH_RL5C466: 2991 case PCIC_TI_PCI1410: 2992 case PCIC_ENE_1410: 2993 case PCIC_TI_PCI1510: 2994 case PCIC_TI_PCI1520: 2995 case PCIC_O2_OZ6912: 2996 case PCIC_TI_PCI1420: 2997 case PCIC_ENE_1420: 2998 case PCIC_TI_VENDOR: 2999 case PCIC_TOSHIBA_TOPIC100: 3000 case PCIC_TOSHIBA_TOPIC95: 3001 case PCIC_TOSHIBA_VENDOR: 3002 case PCIC_RICOH_VENDOR: 3003 case PCIC_O2MICRO_VENDOR: 3004 pcic_putb(pcic, socket, 3005 PCIC_YENTA_MEM_PAGE + win, 3006 SYSMEM_EXT(base)); 3007 break; 3008 default: 3009 cmn_err(CE_NOTE, "pcic_set_window: unknown " 3010 "cardbus vendor:0x%X\n", 3011 pcic->pc_type); 3012 pcic_putb(pcic, socket, 3013 PCIC_YENTA_MEM_PAGE + win, 3014 SYSMEM_EXT(base)); 3015 3016 break; 3017 } /* switch */ 3018 3019 /* 3020 * specify the length of the mapped range 3021 * we convert to pages (rounding up) so that 3022 * the hardware gets the right thing 3023 */ 3024 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 3025 3026 /* 3027 * Setup this window's timing. 3028 */ 3029 switch (pcic->pc_type) { 3030 case PCIC_CL_PD6729: 3031 case PCIC_CL_PD6730: 3032 case PCIC_CL_PD6710: 3033 case PCIC_CL_PD6722: 3034 wspeed = SYSMEM_CLTIMER_SET_0; 3035 pcic_set_cdtimers(pcic, socket, 3036 window->speed, 3037 wspeed); 3038 break; 3039 3040 case PCIC_INTEL_i82092: 3041 default: 3042 wspeed = pcic_calc_speed(pcic, window->speed); 3043 break; 3044 } /* switch */ 3045 3046 #if defined(PCIC_DEBUG) 3047 if (pcic_debug) 3048 cmn_err(CE_CONT, 3049 "\twindow %d speed bits = %x for " 3050 "%dns\n", 3051 win, (unsigned)wspeed, window->speed); 3052 #endif 3053 3054 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 3055 SYSMEM_LOW(base + 3056 (pages * PCIC_PAGE)-1)); 3057 3058 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 3059 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 3060 wspeed); 3061 3062 /* 3063 * now map the card's memory pages - we start with page 3064 * 0 3065 * we also default to AM -- set page might change it 3066 */ 3067 base = memp->pcw_base; 3068 pcic_putb(pcic, socket, 3069 PCIC_CARDMEM_0_LOW + select, 3070 CARDMEM_LOW(0 - (uint32_t)base)); 3071 3072 pcic_putb(pcic, socket, 3073 PCIC_CARDMEM_0_HI + select, 3074 CARDMEM_HIGH(0 - (uint32_t)base) | 3075 CARDMEM_REG_ACTIVE); 3076 3077 /* 3078 * enable the window even though redundant 3079 * and SetPage may do it again. 3080 */ 3081 select = pcic_getb(pcic, socket, 3082 PCIC_MAPPING_ENABLE); 3083 select |= SYSMEM_WINDOW(win); 3084 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3085 memp->pcw_offset = 0; 3086 memp->pcw_status |= PCW_ENABLED; 3087 } else { 3088 /* 3089 * not only do we unmap the memory, the 3090 * window has been turned off. 3091 */ 3092 if (which && memp->pcw_status & PCW_MAPPED) { 3093 ddi_regs_map_free(&memp->pcw_handle); 3094 res.ra_addr_lo = memp->pcw_base; 3095 res.ra_len = memp->pcw_len; 3096 (void) pcmcia_free_mem(memp->res_dip, &res); 3097 memp->pcw_hostmem = NULL; 3098 memp->pcw_status &= ~PCW_MAPPED; 3099 } 3100 3101 /* disable current mapping */ 3102 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3103 select &= ~SYSMEM_WINDOW(win); 3104 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3105 memp->pcw_status &= ~PCW_ENABLED; 3106 } 3107 memp->pcw_len = window->WindowSize; 3108 window->handle = memp->pcw_handle; 3109 #if defined(PCIC_DEBUG) 3110 if (pcic_debug) 3111 xxdmp_all_regs(pcic, window->socket, -1); 3112 #endif 3113 } else { 3114 /* 3115 * This is a request for an IO window 3116 */ 3117 int win, tmp; 3118 pcs_iowin_t *winp; 3119 /* I/O windows */ 3120 #if defined(PCIC_DEBUG) 3121 if (pcic_debug) 3122 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3123 #endif 3124 3125 /* only windows 0 and 1 can do I/O */ 3126 win = window->window % PCIC_NUMWINSOCK; 3127 tmp = window->window / PCIC_NUMWINSOCK; 3128 3129 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3130 cmn_err(CE_WARN, 3131 "\twindow is out of range (%d)\n", 3132 window->window); 3133 return (BAD_WINDOW); 3134 } 3135 3136 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3137 3138 winp = &sockp->pcs_windows[win].io; 3139 winp->pcw_speed = window->speed; 3140 if (window->WindowSize != 1 && window->WindowSize & 1) { 3141 /* we don't want an odd-size window */ 3142 window->WindowSize++; 3143 } 3144 winp->pcw_len = window->WindowSize; 3145 3146 if (window->state & WS_ENABLED) { 3147 if (winp->pcw_status & PCW_MAPPED) { 3148 ddi_regs_map_free(&winp->pcw_handle); 3149 res.ra_addr_lo = winp->pcw_base; 3150 res.ra_len = winp->pcw_len; 3151 (void) pcmcia_free_io(winp->res_dip, &res); 3152 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3153 } 3154 3155 /* 3156 * if the I/O address wasn't allocated, allocate 3157 * it now. If it was allocated, it better 3158 * be free to use. 3159 * The winp->pcw_offset value is set and used 3160 * later on if the particular adapter 3161 * that we're running on has the ability 3162 * to translate IO accesses to the card 3163 * (such as some adapters in the Cirrus 3164 * Logic family). 3165 */ 3166 winp->pcw_offset = 0; 3167 3168 /* 3169 * Setup the request parameters for the 3170 * requested base and length. If 3171 * we're on an adapter that has 3172 * IO window offset registers, then 3173 * we don't need a specific base 3174 * address, just a length, and then 3175 * we'll cause the correct IO address 3176 * to be generated on the socket by 3177 * setting up the IO window offset 3178 * registers. 3179 * For adapters that support this capability, we 3180 * always use the IO window offset registers, 3181 * even if the passed base/length would be in 3182 * range. 3183 */ 3184 base = window->base; 3185 bzero(&req, sizeof (req)); 3186 req.ra_len = window->WindowSize; 3187 3188 req.ra_addr = (uint64_t) 3189 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3190 req.ra_flags = (req.ra_addr) ? 3191 NDI_RA_ALLOC_SPECIFIED : 0; 3192 3193 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3194 /* need to rethink this */ 3195 req.ra_boundbase = pcic->pc_iobase; 3196 req.ra_boundlen = pcic->pc_iobound; 3197 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3198 3199 #if defined(PCIC_DEBUG) 3200 pcic_err(dip, 8, 3201 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3202 "bbase 0x%"PRIx64 3203 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3204 PRIx64"\n", 3205 req.ra_len, (uint64_t)req.ra_addr, 3206 req.ra_boundbase, 3207 req.ra_boundlen, req.ra_flags, 3208 req.ra_align_mask); 3209 #endif 3210 3211 /* 3212 * Try to allocate the space. If we fail this, 3213 * return the appropriate error depending 3214 * on whether the caller specified a 3215 * specific base address or not. 3216 */ 3217 if (pcmcia_alloc_io(dip, &req, &res, 3218 &winp->res_dip) == DDI_FAILURE) { 3219 winp->pcw_status &= ~PCW_ENABLED; 3220 mutex_exit(&pcic->pc_lock); 3221 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3222 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3223 "bbase 0x%" PRIx64 3224 "blen 0x%" PRIx64 "flags 0x%x" 3225 "algn 0x%" PRIx64 "\n", 3226 req.ra_len, req.ra_addr, 3227 req.ra_boundbase, 3228 req.ra_boundlen, req.ra_flags, 3229 req.ra_align_mask); 3230 3231 return (base?BAD_BASE:BAD_SIZE); 3232 } /* pcmcia_alloc_io */ 3233 3234 /* 3235 * Don't change the original base. Either we use 3236 * the offset registers below (PCF_IO_REMAP is set) 3237 * or it was allocated correctly anyway. 3238 */ 3239 winp->pcw_base = res.ra_addr_lo; 3240 3241 #if defined(PCIC_DEBUG) 3242 pcic_err(dip, 8, 3243 "\tsetwindow: new base=%x orig base 0x%x\n", 3244 (unsigned)winp->pcw_base, base); 3245 #endif 3246 3247 if ((which = pcmcia_map_reg(pcic->dip, 3248 window->child, 3249 &res, 3250 (uint32_t)(window->state & 3251 0xffff) | 3252 (window->socket << 16), 3253 (caddr_t *)&winp->pcw_hostmem, 3254 &winp->pcw_handle, 3255 &window->attr, 3256 base)) != DDI_SUCCESS) { 3257 3258 cmn_err(CE_WARN, "pcmcia_map_reg()" 3259 "failed\n"); 3260 3261 res.ra_addr_lo = winp->pcw_base; 3262 res.ra_len = winp->pcw_len; 3263 (void) pcmcia_free_io(winp->res_dip, &res); 3264 3265 mutex_exit(&pcic->pc_lock); 3266 return (BAD_WINDOW); 3267 } 3268 3269 window->handle = winp->pcw_handle; 3270 winp->pcw_status |= PCW_MAPPED; 3271 3272 /* find the register set offset */ 3273 select = win * PCIC_IO_OFFSET; 3274 3275 #if defined(PCIC_DEBUG) 3276 if (pcic_debug) { 3277 cmn_err(CE_CONT, 3278 "\tenable: window=%d, select=%x, " 3279 "base=%x, handle=%p\n", 3280 win, select, 3281 (unsigned)window->base, 3282 (void *)window->handle); 3283 } 3284 #endif 3285 /* 3286 * at this point, the register window indicator has 3287 * been converted to be an offset from the first 3288 * set of registers that are used for programming 3289 * the window mapping and the offset used to select 3290 * the correct set of registers to access the 3291 * specified socket. This allows basing everything 3292 * off the _0 window 3293 */ 3294 3295 /* map the I/O base in */ 3296 pcic_putb(pcic, socket, 3297 PCIC_IO_ADDR_0_STARTLOW + select, 3298 LOW_BYTE((uint32_t)winp->pcw_base)); 3299 pcic_putb(pcic, socket, 3300 PCIC_IO_ADDR_0_STARTHI + select, 3301 HIGH_BYTE((uint32_t)winp->pcw_base)); 3302 3303 pcic_putb(pcic, socket, 3304 PCIC_IO_ADDR_0_STOPLOW + select, 3305 LOW_BYTE((uint32_t)winp->pcw_base + 3306 window->WindowSize - 1)); 3307 pcic_putb(pcic, socket, 3308 PCIC_IO_ADDR_0_STOPHI + select, 3309 HIGH_BYTE((uint32_t)winp->pcw_base + 3310 window->WindowSize - 1)); 3311 3312 /* 3313 * We've got the requested IO space, now see if we 3314 * need to adjust the IO window offset registers 3315 * so that the correct IO address is generated 3316 * at the socket. If this window doesn't have 3317 * this capability, then we're all done setting 3318 * up the IO resources. 3319 */ 3320 if (pcic->pc_flags & PCF_IO_REMAP) { 3321 3322 3323 /* 3324 * Note that only 16 bits are used to program 3325 * the registers but leave 32 bits on pcw_offset 3326 * so that we can generate the original base 3327 * in get_window() 3328 */ 3329 winp->pcw_offset = (base - winp->pcw_base); 3330 3331 pcic_putb(pcic, socket, 3332 PCIC_IO_OFFSET_LOW + 3333 (win * PCIC_IO_OFFSET_OFFSET), 3334 winp->pcw_offset & 0x0ff); 3335 pcic_putb(pcic, socket, 3336 PCIC_IO_OFFSET_HI + 3337 (win * PCIC_IO_OFFSET_OFFSET), 3338 (winp->pcw_offset >> 8) & 0x0ff); 3339 3340 } /* PCF_IO_REMAP */ 3341 3342 /* now get the other details (size, etc) right */ 3343 3344 /* 3345 * Set the data size control bits here. Most of the 3346 * adapters will ignore IOMEM_16BIT when 3347 * IOMEM_IOCS16 is set, except for the Intel 3348 * 82092, which only pays attention to the 3349 * IOMEM_16BIT bit. Sigh... Intel can't even 3350 * make a proper clone of their own chip. 3351 * The 82092 also apparently can't set the timing 3352 * of I/O windows. 3353 */ 3354 which = (window->state & WS_16BIT) ? 3355 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3356 3357 switch (pcic->pc_type) { 3358 case PCIC_CL_PD6729: 3359 case PCIC_CL_PD6730: 3360 case PCIC_CL_PD6710: 3361 case PCIC_CL_PD6722: 3362 case PCIC_CL_PD6832: 3363 /* 3364 * Select Timer Set 1 - this will take 3365 * effect when the PCIC_IO_CONTROL 3366 * register is written to later on; 3367 * the call to pcic_set_cdtimers 3368 * just sets up the timer itself. 3369 */ 3370 which |= IOMEM_CLTIMER_SET_1; 3371 pcic_set_cdtimers(pcic, socket, 3372 window->speed, 3373 IOMEM_CLTIMER_SET_1); 3374 which |= IOMEM_IOCS16; 3375 break; 3376 case PCIC_TI_PCI1031: 3377 3378 if (window->state & WS_16BIT) 3379 which |= IOMEM_WAIT16; 3380 3381 break; 3382 case PCIC_TI_PCI1130: 3383 3384 if (window->state & WS_16BIT) 3385 which |= IOMEM_WAIT16; 3386 3387 break; 3388 case PCIC_INTEL_i82092: 3389 break; 3390 default: 3391 if (window->speed > 3392 mhztons(pcic->bus_speed) * 3) 3393 which |= IOMEM_WAIT16; 3394 #ifdef notdef 3395 if (window->speed < 3396 mhztons(pcic->bus_speed) * 6) 3397 which |= IOMEM_ZERO_WAIT; 3398 #endif 3399 break; 3400 } /* switch (pc_type) */ 3401 3402 /* 3403 * Setup the data width and timing 3404 */ 3405 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3406 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3407 select |= IOMEM_SETWIN(win, which); 3408 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3409 3410 /* 3411 * Enable the IO window 3412 */ 3413 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3414 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3415 select | IOMEM_WINDOW(win)); 3416 3417 winp->pcw_status |= PCW_ENABLED; 3418 3419 #if defined(PCIC_DEBUG) 3420 if (pcic_debug) { 3421 cmn_err(CE_CONT, 3422 "\twhich = %x, select = %x (%x)\n", 3423 which, select, 3424 IOMEM_SETWIN(win, which)); 3425 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3426 } 3427 #endif 3428 } else { 3429 /* 3430 * not only do we unmap the IO space, the 3431 * window has been turned off. 3432 */ 3433 if (winp->pcw_status & PCW_MAPPED) { 3434 ddi_regs_map_free(&winp->pcw_handle); 3435 res.ra_addr_lo = winp->pcw_base; 3436 res.ra_len = winp->pcw_len; 3437 (void) pcmcia_free_io(winp->res_dip, &res); 3438 winp->pcw_status &= ~PCW_MAPPED; 3439 } 3440 3441 /* disable current mapping */ 3442 select = pcic_getb(pcic, socket, 3443 PCIC_MAPPING_ENABLE); 3444 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3445 select &= ~IOMEM_WINDOW(win)); 3446 winp->pcw_status &= ~PCW_ENABLED; 3447 3448 winp->pcw_base = 0; 3449 winp->pcw_len = 0; 3450 winp->pcw_offset = 0; 3451 window->base = 0; 3452 /* now make sure we don't accidentally re-enable */ 3453 /* find the register set offset */ 3454 select = win * PCIC_IO_OFFSET; 3455 pcic_putb(pcic, socket, 3456 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3457 pcic_putb(pcic, socket, 3458 PCIC_IO_ADDR_0_STARTHI + select, 0); 3459 pcic_putb(pcic, socket, 3460 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3461 pcic_putb(pcic, socket, 3462 PCIC_IO_ADDR_0_STOPHI + select, 0); 3463 } 3464 } 3465 mutex_exit(&pcic->pc_lock); 3466 3467 return (SUCCESS); 3468 } 3469 3470 /* 3471 * pcic_card_state() 3472 * compute the instantaneous Card State information 3473 */ 3474 static int 3475 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3476 { 3477 int value, result; 3478 #if defined(PCIC_DEBUG) 3479 int orig_value; 3480 #endif 3481 3482 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3483 3484 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3485 3486 #if defined(PCIC_DEBUG) 3487 orig_value = value; 3488 if (pcic_debug >= 8) 3489 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3490 (void *)sockp, 3491 value, 3492 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3493 sockp->pcs_socket); 3494 #endif 3495 /* 3496 * Lie to socket services if we are not ready. 3497 * This is when we are starting up or during debounce timeouts 3498 * or if the card is a cardbus card. 3499 */ 3500 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3501 !sockp->pcs_debounce_id && 3502 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3503 result = SBM_CD; 3504 3505 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3506 result |= SBM_WP; 3507 if (value & PCIC_POWER_ON) { 3508 if (value & PCIC_READY) 3509 result |= SBM_RDYBSY; 3510 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3511 if (value & PCIC_BVD1) 3512 result |= SBM_BVD1; 3513 if (value & PCIC_BVD2) 3514 result |= SBM_BVD2; 3515 } 3516 } else 3517 result = 0; 3518 3519 mutex_exit(&pcic->pc_lock); 3520 3521 #if defined(PCIC_DEBUG) 3522 pcic_err(pcic->dip, 8, 3523 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3524 (void *) sockp, orig_value, 3525 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3526 sockp->pcs_socket, result); 3527 #endif 3528 3529 return (result); 3530 } 3531 3532 /* 3533 * pcic_set_page() 3534 * SocketServices SetPage function 3535 * set the page of PC Card memory that should be in the mapped 3536 * window 3537 */ 3538 /*ARGSUSED*/ 3539 static int 3540 pcic_set_page(dev_info_t *dip, set_page_t *page) 3541 { 3542 anp_t *anp = ddi_get_driver_private(dip); 3543 pcicdev_t *pcic = anp->an_private; 3544 int select; 3545 int which, socket, window; 3546 uint32_t base; 3547 pcs_memwin_t *memp; 3548 3549 /* get real socket/window numbers */ 3550 window = page->window % PCIC_NUMWINSOCK; 3551 socket = page->window / PCIC_NUMWINSOCK; 3552 3553 #if defined(PCIC_DEBUG) 3554 if (pcic_debug) { 3555 cmn_err(CE_CONT, 3556 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3557 window, socket, page->page); 3558 } 3559 #endif 3560 /* only windows 2-6 work on memory */ 3561 if (window < PCIC_IOWINDOWS) 3562 return (BAD_WINDOW); 3563 3564 /* only one page supported (but any size) */ 3565 if (page->page != 0) 3566 return (BAD_PAGE); 3567 3568 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3569 3570 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3571 window -= PCIC_IOWINDOWS; 3572 3573 #if defined(PCIC_DEBUG) 3574 if (pcic_debug) 3575 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3576 (uint32_t)memp->pcw_base, 3577 (void *)memp->pcw_hostmem, memp->pcw_len); 3578 #endif 3579 3580 /* window must be enabled */ 3581 if (!(memp->pcw_status & PCW_ENABLED)) 3582 return (BAD_ATTRIBUTE); 3583 3584 /* find the register set offset */ 3585 select = window * PCIC_MEM_1_OFFSET; 3586 #if defined(PCIC_DEBUG) 3587 if (pcic_debug) 3588 cmn_err(CE_CONT, "\tselect=%x\n", select); 3589 #endif 3590 3591 /* 3592 * now map the card's memory pages - we start with page 0 3593 */ 3594 3595 which = 0; /* assume simple case */ 3596 if (page->state & PS_ATTRIBUTE) { 3597 which |= CARDMEM_REG_ACTIVE; 3598 memp->pcw_status |= PCW_ATTRIBUTE; 3599 } else { 3600 memp->pcw_status &= ~PCW_ATTRIBUTE; 3601 } 3602 3603 /* 3604 * if caller says Write Protect, enforce it. 3605 */ 3606 if (page->state & PS_WP) { 3607 which |= CARDMEM_WRITE_PROTECT; 3608 memp->pcw_status |= PCW_WP; 3609 } else { 3610 memp->pcw_status &= ~PCW_WP; 3611 } 3612 #if defined(PCIC_DEBUG) 3613 if (pcic_debug) { 3614 cmn_err(CE_CONT, "\tmemory type = %s\n", 3615 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3616 if (which & CARDMEM_WRITE_PROTECT) 3617 cmn_err(CE_CONT, "\twrite protect\n"); 3618 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3619 (unsigned)page->offset, 3620 (unsigned)memp->pcw_base, 3621 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3622 } 3623 #endif 3624 /* address computation based on 64MB range and not larger */ 3625 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3626 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3627 CARDMEM_LOW((int)page->offset - (int)base)); 3628 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3629 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3630 CARDMEM_HIGH((int)page->offset - base) | which); 3631 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3632 3633 /* 3634 * while not really necessary, this just makes sure 3635 * nothing turned the window off behind our backs 3636 */ 3637 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3638 which |= SYSMEM_WINDOW(window); 3639 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3640 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3641 3642 memp->pcw_offset = (off_t)page->offset; 3643 3644 #if defined(PCIC_DEBUG) 3645 if (pcic_debug) { 3646 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3647 (void *)memp->pcw_hostmem, 3648 (uint32_t)*memp->pcw_hostmem); 3649 3650 xxdmp_all_regs(pcic, socket, -1); 3651 3652 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3653 (void *)memp->pcw_hostmem, 3654 (uint32_t)*memp->pcw_hostmem); 3655 } 3656 #endif 3657 3658 if (which & PCW_ATTRIBUTE) 3659 pcic_mswait(pcic, socket, 2); 3660 3661 mutex_exit(&pcic->pc_lock); 3662 3663 return (SUCCESS); 3664 } 3665 3666 /* 3667 * pcic_set_vcc_level() 3668 * 3669 * set voltage based on adapter information 3670 * 3671 * this routine implements a limited solution for support of 3.3v cards. 3672 * the general solution, which would fully support the pcmcia spec 3673 * as far as allowing client drivers to request which voltage levels 3674 * to be set, requires more framework support and driver changes - ess 3675 */ 3676 static int 3677 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3678 { 3679 uint32_t socket_present_state; 3680 3681 #if defined(PCIC_DEBUG) 3682 if (pcic_debug) { 3683 cmn_err(CE_CONT, 3684 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3685 (void *)pcic, socket->VccLevel); 3686 } 3687 #endif 3688 3689 /* 3690 * check VccLevel 3691 * if this is zero, power is being turned off 3692 * if it is non-zero, power is being turned on. 3693 */ 3694 if (socket->VccLevel == 0) { 3695 return (0); 3696 } 3697 3698 /* 3699 * range checking for sanity's sake 3700 */ 3701 if (socket->VccLevel >= pcic->pc_numpower) { 3702 return (BAD_VCC); 3703 } 3704 3705 switch (pcic->pc_io_type) { 3706 /* 3707 * Yenta-compliant adapters have vcc info in the extended registers 3708 * Other adapters can be added as needed, but the 'default' case 3709 * has been left as it was previously so as not to break existing 3710 * adapters. 3711 */ 3712 case PCIC_IO_TYPE_YENTA: 3713 /* 3714 * Here we ignore the VccLevel passed in and read the 3715 * card type from the adapter socket present state register 3716 */ 3717 socket_present_state = 3718 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3719 PCIC_PRESENT_STATE_REG)); 3720 #if defined(PCIC_DEBUG) 3721 if (pcic_debug) { 3722 cmn_err(CE_CONT, 3723 "socket present state = 0x%x\n", 3724 socket_present_state); 3725 } 3726 #endif 3727 switch (socket_present_state & PCIC_VCC_MASK) { 3728 case PCIC_VCC_3VCARD: 3729 /* fall through */ 3730 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3731 socket->VccLevel = PCIC_VCC_3VLEVEL; 3732 return 3733 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3734 case PCIC_VCC_5VCARD: 3735 socket->VccLevel = PCIC_VCC_5VLEVEL; 3736 return 3737 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3738 default: 3739 /* 3740 * if no card is present, this can be the 3741 * case of a client making a SetSocket call 3742 * after card removal. In this case we return 3743 * the current power level 3744 */ 3745 return ((unsigned)ddi_get8(pcic->handle, 3746 pcic->ioaddr + CB_R2_OFFSET + 3747 PCIC_POWER_CONTROL)); 3748 } 3749 3750 default: 3751 3752 switch (socket->VccLevel) { 3753 case PCIC_VCC_3VLEVEL: 3754 return (BAD_VCC); 3755 case PCIC_VCC_5VLEVEL: 3756 /* enable Vcc */ 3757 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3758 default: 3759 return (BAD_VCC); 3760 } 3761 } 3762 } 3763 3764 3765 /* 3766 * pcic_set_socket() 3767 * Socket Services SetSocket call 3768 * sets basic socket configuration 3769 */ 3770 static int 3771 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3772 { 3773 anp_t *anp = ddi_get_driver_private(dip); 3774 pcicdev_t *pcic = anp->an_private; 3775 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3776 int irq, interrupt, mirq; 3777 int powerlevel = 0; 3778 int ind, value, orig_pwrctl; 3779 3780 #if defined(PCIC_DEBUG) 3781 if (pcic_debug) { 3782 cmn_err(CE_CONT, 3783 "pcic_set_socket(dip=%p, socket=%d)" 3784 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3785 socket->socket, socket->VccLevel, socket->Vpp1Level, 3786 socket->Vpp2Level); 3787 } 3788 #endif 3789 /* 3790 * check VccLevel, etc. before setting mutex 3791 * if this is zero, power is being turned off 3792 * if it is non-zero, power is being turned on. 3793 * the default case is to assume Vcc only. 3794 */ 3795 3796 /* this appears to be very implementation specific */ 3797 3798 if (socket->Vpp1Level != socket->Vpp2Level) 3799 return (BAD_VPP); 3800 3801 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3802 powerlevel = 0; 3803 sockp->pcs_vcc = 0; 3804 sockp->pcs_vpp1 = 0; 3805 sockp->pcs_vpp2 = 0; 3806 } else { 3807 #if defined(PCIC_DEBUG) 3808 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3809 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3810 #endif 3811 /* valid Vcc power level? */ 3812 if (socket->VccLevel >= pcic->pc_numpower) 3813 return (BAD_VCC); 3814 3815 switch (pcic_power[socket->VccLevel].PowerLevel) { 3816 case 33: /* 3.3V */ 3817 case 60: /* for bad CIS in Option GPRS card */ 3818 if (!(pcic->pc_flags & PCF_33VCAP)) { 3819 cmn_err(CE_WARN, 3820 "%s%d: Bad Request for 3.3V " 3821 "(Controller incapable)\n", 3822 ddi_get_name(pcic->dip), 3823 ddi_get_instance(pcic->dip)); 3824 return (BAD_VCC); 3825 } 3826 /* FALLTHROUGH */ 3827 case 50: /* 5V */ 3828 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3829 pcic_getcb(pcic, CB_PRESENT_STATE) & 3830 CB_PS_33VCARD) { 3831 /* 3832 * This is actually a 3.3V card. 3833 * Solaris Card Services 3834 * doesn't understand 3.3V 3835 * so we cheat and change 3836 * the setting to the one appropriate to 3.3V. 3837 * Note that this is the entry number 3838 * in the pcic_power[] array. 3839 */ 3840 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3841 } else 3842 sockp->pcs_vcc = socket->VccLevel; 3843 break; 3844 default: 3845 return (BAD_VCC); 3846 } 3847 3848 /* enable Vcc */ 3849 powerlevel = POWER_CARD_ENABLE; 3850 3851 #if defined(PCIC_DEBUG) 3852 if (pcic_debug) { 3853 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3854 socket->VccLevel, powerlevel); 3855 } 3856 #endif 3857 ind = 0; /* default index to 0 power */ 3858 if ((int)socket->Vpp1Level >= 0 && 3859 socket->Vpp1Level < pcic->pc_numpower) { 3860 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3861 & VPP1)) { 3862 return (BAD_VPP); 3863 } 3864 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3865 powerlevel |= pcic_vpp_levels[ind]; 3866 sockp->pcs_vpp1 = socket->Vpp1Level; 3867 } 3868 if ((int)socket->Vpp2Level >= 0 && 3869 socket->Vpp2Level < pcic->pc_numpower) { 3870 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3871 & VPP2)) { 3872 return (BAD_VPP); 3873 } 3874 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3875 powerlevel |= (pcic_vpp_levels[ind] << 2); 3876 sockp->pcs_vpp2 = socket->Vpp2Level; 3877 } 3878 3879 if (pcic->pc_flags & PCF_VPPX) { 3880 /* 3881 * this adapter doesn't allow separate Vpp1/Vpp2 3882 * if one is turned on, both are turned on and only 3883 * the Vpp1 bits should be set 3884 */ 3885 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3886 /* must be the same if one not zero */ 3887 if (sockp->pcs_vpp1 != 0 && 3888 sockp->pcs_vpp2 != 0) { 3889 cmn_err(CE_WARN, 3890 "%s%d: Bad Power Request " 3891 "(Vpp1/2 not the same)\n", 3892 ddi_get_name(pcic->dip), 3893 ddi_get_instance(pcic->dip)); 3894 return (BAD_VPP); 3895 } 3896 } 3897 powerlevel &= ~(3<<2); 3898 } 3899 3900 #if defined(PCIC_DEBUG) 3901 if (pcic_debug) { 3902 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3903 powerlevel, ind); 3904 } 3905 #endif 3906 } 3907 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3908 3909 /* turn socket->IREQRouting off while programming */ 3910 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3911 interrupt &= ~PCIC_INTR_MASK; 3912 if (pcic->pc_flags & PCF_USE_SMI) 3913 interrupt |= PCIC_INTR_ENABLE; 3914 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3915 3916 switch (pcic->pc_type) { 3917 case PCIC_INTEL_i82092: 3918 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3919 PCIC_82092_INT_DISABLE); 3920 break; 3921 default: 3922 break; 3923 } /* switch */ 3924 3925 /* the SCIntMask specifies events to detect */ 3926 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3927 3928 #if defined(PCIC_DEBUG) 3929 if (pcic_debug) 3930 cmn_err(CE_CONT, 3931 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3932 socket->SCIntMask, interrupt, mirq); 3933 #endif 3934 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3935 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3936 mirq & ~PCIC_CHANGE_MASK); 3937 3938 /* save the mask we want to use */ 3939 sockp->pcs_intmask = socket->SCIntMask; 3940 3941 /* 3942 * Until there is a card present it's not worth enabling 3943 * any interrupts except "Card detect". This is done 3944 * elsewhere in the driver so don't change things if 3945 * there is no card! 3946 */ 3947 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3948 3949 /* now update the hardware to reflect events desired */ 3950 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3951 mirq |= PCIC_BD_DETECT; 3952 3953 if (sockp->pcs_intmask & SBM_BVD2) 3954 mirq |= PCIC_BW_DETECT; 3955 3956 if (sockp->pcs_intmask & SBM_RDYBSY) 3957 mirq |= PCIC_RD_DETECT; 3958 3959 if (sockp->pcs_intmask & SBM_CD) 3960 mirq |= PCIC_CD_DETECT; 3961 } 3962 3963 if (sockp->pcs_flags & PCS_READY) { 3964 /* 3965 * card just came ready. 3966 * make sure enough time elapses 3967 * before touching it. 3968 */ 3969 sockp->pcs_flags &= ~PCS_READY; 3970 pcic_mswait(pcic, socket->socket, 10); 3971 } 3972 3973 #if defined(PCIC_DEBUG) 3974 if (pcic_debug) { 3975 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3976 } 3977 #endif 3978 3979 switch (pcic->pc_type) { 3980 case PCIC_I82365SL: 3981 case PCIC_VADEM: 3982 case PCIC_VADEM_VG469: 3983 /* 3984 * The Intel version has different options. This is a 3985 * special case of GPI which might be used for eject 3986 */ 3987 3988 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 3989 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 3990 pcic->pc_flags & PCF_GPI_EJECT) { 3991 irq |= PCIC_GPI_ENABLE; 3992 } else { 3993 irq &= ~PCIC_GPI_ENABLE; 3994 } 3995 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 3996 break; 3997 case PCIC_CL_PD6710: 3998 case PCIC_CL_PD6722: 3999 if (socket->IFType == IF_IO) { 4000 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 4001 value = pcic_getb(pcic, socket->socket, 4002 PCIC_MISC_CTL_1); 4003 if (pcic->pc_flags & PCF_AUDIO) 4004 value |= PCIC_MC_SPEAKER_ENB; 4005 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4006 value); 4007 } else { 4008 value = pcic_getb(pcic, socket->socket, 4009 PCIC_MISC_CTL_1); 4010 value &= ~PCIC_MC_SPEAKER_ENB; 4011 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4012 value); 4013 } 4014 break; 4015 case PCIC_CL_PD6729: 4016 case PCIC_CL_PD6730: 4017 case PCIC_CL_PD6832: 4018 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 4019 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4020 value |= PCIC_MC_SPEAKER_ENB; 4021 } else { 4022 value &= ~PCIC_MC_SPEAKER_ENB; 4023 } 4024 4025 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4026 value |= PCIC_MC_3VCC; 4027 else 4028 value &= ~PCIC_MC_3VCC; 4029 4030 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 4031 break; 4032 4033 case PCIC_O2_OZ6912: 4034 value = pcic_getcb(pcic, CB_MISCCTRL); 4035 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 4036 value |= (1<<25); 4037 else 4038 value &= ~(1<<25); 4039 pcic_putcb(pcic, CB_MISCCTRL, value); 4040 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4041 powerlevel |= 0x08; 4042 break; 4043 4044 case PCIC_TI_PCI1250: 4045 case PCIC_TI_PCI1221: 4046 case PCIC_TI_PCI1225: 4047 case PCIC_TI_PCI1410: 4048 case PCIC_ENE_1410: 4049 case PCIC_TI_PCI1510: 4050 case PCIC_TI_PCI1520: 4051 case PCIC_TI_PCI1420: 4052 case PCIC_ENE_1420: 4053 value = ddi_get8(pcic->cfg_handle, 4054 pcic->cfgaddr + PCIC_CRDCTL_REG); 4055 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4056 value |= PCIC_CRDCTL_SPKR_ENBL; 4057 } else { 4058 value &= ~PCIC_CRDCTL_SPKR_ENBL; 4059 } 4060 ddi_put8(pcic->cfg_handle, 4061 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4062 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4063 powerlevel |= 0x08; 4064 break; 4065 } 4066 4067 /* 4068 * ctlind processing -- we can ignore this 4069 * there aren't any outputs on the chip for this and 4070 * the GUI will display what it thinks is correct 4071 */ 4072 4073 /* 4074 * If outputs are enabled and the power is going off 4075 * turn off outputs first. 4076 */ 4077 4078 /* power setup -- if necessary */ 4079 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4080 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4081 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4082 pcic_putb(pcic, socket->socket, 4083 PCIC_POWER_CONTROL, orig_pwrctl); 4084 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4085 } 4086 4087 if (pcic->pc_flags & PCF_CBPWRCTL) { 4088 value = pcic_cbus_powerctl(pcic, socket->socket); 4089 powerlevel = 0; 4090 } else 4091 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4092 4093 if (value != SUCCESS) { 4094 mutex_exit(&pcic->pc_lock); 4095 return (value); 4096 } 4097 4098 /* 4099 * If outputs were disabled and the power is going on 4100 * turn on outputs afterwards. 4101 */ 4102 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4103 orig_pwrctl = pcic_getb(pcic, socket->socket, 4104 PCIC_POWER_CONTROL); 4105 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4106 pcic_putb(pcic, socket->socket, 4107 PCIC_POWER_CONTROL, orig_pwrctl); 4108 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4109 } 4110 4111 /* 4112 * Once we have done the power stuff can re-enable management 4113 * interrupts. 4114 */ 4115 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4116 4117 #if defined(PCIC_DEBUG) 4118 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4119 "cbctl 0x%x\n", 4120 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4121 pcic_getcb(pcic, CB_CONTROL)); 4122 #endif 4123 4124 /* irq processing */ 4125 if (socket->IFType == IF_IO) { 4126 /* IRQ only for I/O */ 4127 irq = socket->IREQRouting & PCIC_INTR_MASK; 4128 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4129 value &= ~PCIC_INTR_MASK; 4130 4131 /* to enable I/O operation */ 4132 value |= PCIC_IO_CARD | PCIC_RESET; 4133 sockp->pcs_flags |= PCS_CARD_IO; 4134 if (irq != sockp->pcs_irq) { 4135 if (sockp->pcs_irq != 0) 4136 cmn_err(CE_CONT, 4137 "SetSocket: IRQ mismatch %x != %x!\n", 4138 irq, sockp->pcs_irq); 4139 else 4140 sockp->pcs_irq = irq; 4141 } 4142 irq = sockp->pcs_irq; 4143 4144 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4145 if (socket->IREQRouting & IRQ_ENABLE) { 4146 pcic_enable_io_intr(pcic, socket->socket, irq); 4147 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4148 } else { 4149 pcic_disable_io_intr(pcic, socket->socket); 4150 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4151 } 4152 #if defined(PCIC_DEBUG) 4153 if (pcic_debug) { 4154 cmn_err(CE_CONT, 4155 "\tsocket type is I/O and irq %x is %s\n", irq, 4156 (socket->IREQRouting & IRQ_ENABLE) ? 4157 "enabled" : "not enabled"); 4158 xxdmp_all_regs(pcic, socket->socket, 20); 4159 } 4160 #endif 4161 } else { 4162 /* make sure I/O mode is off */ 4163 4164 sockp->pcs_irq = 0; 4165 4166 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4167 value &= ~PCIC_IO_CARD; 4168 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4169 pcic_disable_io_intr(pcic, socket->socket); 4170 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4171 } 4172 4173 sockp->pcs_state &= ~socket->State; 4174 4175 mutex_exit(&pcic->pc_lock); 4176 return (SUCCESS); 4177 } 4178 4179 /* 4180 * pcic_inquire_socket() 4181 * SocketServices InquireSocket function 4182 * returns basic characteristics of the socket 4183 */ 4184 /*ARGSUSED*/ 4185 static int 4186 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4187 { 4188 anp_t *anp = ddi_get_driver_private(dip); 4189 pcicdev_t *pcic = anp->an_private; 4190 int value; 4191 4192 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4193 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4194 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4195 value = pcic->pc_sockets[socket->socket].pcs_flags; 4196 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4197 socket->ActiveHigh = 0; 4198 /* these are the usable IRQs */ 4199 socket->ActiveLow = 0xfff0; 4200 return (SUCCESS); 4201 } 4202 4203 /* 4204 * pcic_inquire_window() 4205 * SocketServices InquireWindow function 4206 * returns detailed characteristics of the window 4207 * this is where windows get tied to sockets 4208 */ 4209 /*ARGSUSED*/ 4210 static int 4211 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4212 { 4213 int type, socket; 4214 4215 type = window->window % PCIC_NUMWINSOCK; 4216 socket = window->window / PCIC_NUMWINSOCK; 4217 4218 #if defined(PCIC_DEBUG) 4219 if (pcic_debug >= 8) 4220 cmn_err(CE_CONT, 4221 "pcic_inquire_window: window = %d/%d socket=%d\n", 4222 window->window, type, socket); 4223 #endif 4224 if (type < PCIC_IOWINDOWS) { 4225 window->WndCaps = WC_IO|WC_WAIT; 4226 type = IF_IO; 4227 } else { 4228 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4229 type = IF_MEMORY; 4230 } 4231 4232 /* initialize the socket map - one socket per window */ 4233 PR_ZERO(window->Sockets); 4234 PR_SET(window->Sockets, socket); 4235 4236 if (type == IF_IO) { 4237 iowin_char_t *io; 4238 io = &window->iowin_char; 4239 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4240 WC_16BIT; 4241 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4242 io->LastByte = (baseaddr_t)IOMEM_LAST; 4243 io->MinSize = IOMEM_MIN; 4244 io->MaxSize = IOMEM_MAX; 4245 io->ReqGran = IOMEM_GRAN; 4246 io->AddrLines = IOMEM_DECODE; 4247 io->EISASlot = 0; 4248 } else { 4249 mem_win_char_t *mem; 4250 mem = &window->mem_win_char; 4251 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4252 WC_16BIT|WC_WP; 4253 4254 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4255 mem->LastByte = (baseaddr_t)MEM_LAST; 4256 4257 mem->MinSize = MEM_MIN; 4258 mem->MaxSize = MEM_MAX; 4259 mem->ReqGran = PCIC_PAGE; 4260 mem->ReqBase = 0; 4261 mem->ReqOffset = PCIC_PAGE; 4262 mem->Slowest = MEM_SPEED_MAX; 4263 mem->Fastest = MEM_SPEED_MIN; 4264 } 4265 return (SUCCESS); 4266 } 4267 4268 /* 4269 * pcic_get_adapter() 4270 * SocketServices GetAdapter function 4271 * this is nearly a no-op. 4272 */ 4273 /*ARGSUSED*/ 4274 static int 4275 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4276 { 4277 anp_t *anp = ddi_get_driver_private(dip); 4278 pcicdev_t *pcic = anp->an_private; 4279 4280 if (pcic->pc_flags & PCF_INTRENAB) 4281 adapt->SCRouting = IRQ_ENABLE; 4282 adapt->state = 0; 4283 return (SUCCESS); 4284 } 4285 4286 /* 4287 * pcic_get_page() 4288 * SocketServices GetPage function 4289 * returns info about the window 4290 */ 4291 /*ARGSUSED*/ 4292 static int 4293 pcic_get_page(dev_info_t *dip, get_page_t *page) 4294 { 4295 anp_t *anp = ddi_get_driver_private(dip); 4296 pcicdev_t *pcic = anp->an_private; 4297 int socket, window; 4298 pcs_memwin_t *winp; 4299 4300 socket = page->window / PCIC_NUMWINSOCK; 4301 window = page->window % PCIC_NUMWINSOCK; 4302 4303 /* I/O windows are the first two */ 4304 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4305 return (BAD_WINDOW); 4306 } 4307 4308 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4309 4310 if (page->page != 0) 4311 return (BAD_PAGE); 4312 4313 page->state = 0; 4314 if (winp->pcw_status & PCW_ENABLED) 4315 page->state |= PS_ENABLED; 4316 if (winp->pcw_status & PCW_ATTRIBUTE) 4317 page->state |= PS_ATTRIBUTE; 4318 if (winp->pcw_status & PCW_WP) 4319 page->state |= PS_WP; 4320 4321 page->offset = (off_t)winp->pcw_offset; 4322 4323 return (SUCCESS); 4324 } 4325 4326 /* 4327 * pcic_get_socket() 4328 * SocketServices GetSocket 4329 * returns information about the current socket setting 4330 */ 4331 /*ARGSUSED*/ 4332 static int 4333 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4334 { 4335 anp_t *anp = ddi_get_driver_private(dip); 4336 pcicdev_t *pcic = anp->an_private; 4337 int socknum, irq_enabled; 4338 pcic_socket_t *sockp; 4339 4340 socknum = socket->socket; 4341 sockp = &pcic->pc_sockets[socknum]; 4342 4343 socket->SCIntMask = sockp->pcs_intmask; 4344 sockp->pcs_state = pcic_card_state(pcic, sockp); 4345 4346 socket->state = sockp->pcs_state; 4347 if (socket->state & SBM_CD) { 4348 socket->VccLevel = sockp->pcs_vcc; 4349 socket->Vpp1Level = sockp->pcs_vpp1; 4350 socket->Vpp2Level = sockp->pcs_vpp2; 4351 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4352 IRQ_ENABLE : 0; 4353 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4354 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4355 IF_IO : IF_MEMORY; 4356 } else { 4357 socket->VccLevel = 0; 4358 socket->Vpp1Level = 0; 4359 socket->Vpp2Level = 0; 4360 socket->IRQRouting = 0; 4361 socket->IFType = IF_MEMORY; 4362 } 4363 socket->CtlInd = 0; /* no indicators */ 4364 4365 return (SUCCESS); 4366 } 4367 4368 /* 4369 * pcic_get_status() 4370 * SocketServices GetStatus 4371 * returns status information about the PC Card in 4372 * the selected socket 4373 */ 4374 /*ARGSUSED*/ 4375 static int 4376 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4377 { 4378 anp_t *anp = ddi_get_driver_private(dip); 4379 pcicdev_t *pcic = anp->an_private; 4380 int socknum, irq_enabled; 4381 pcic_socket_t *sockp; 4382 4383 socknum = status->socket; 4384 sockp = &pcic->pc_sockets[socknum]; 4385 4386 status->CardState = pcic_card_state(pcic, sockp); 4387 status->SocketState = sockp->pcs_state; 4388 status->CtlInd = 0; /* no indicators */ 4389 4390 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4391 status->SocketState |= SBM_CD; 4392 if (status->CardState & SBM_CD) { 4393 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4394 IRQ_ENABLE : 0; 4395 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4396 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4397 IF_IO : IF_MEMORY; 4398 } else { 4399 status->IRQRouting = 0; 4400 status->IFType = IF_MEMORY; 4401 } 4402 4403 #if defined(PCIC_DEBUG) 4404 if (pcic_debug >= 8) 4405 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4406 "SocketState=%x\n", 4407 socknum, status->CardState, status->SocketState); 4408 #endif 4409 switch (pcic->pc_type) { 4410 uint32_t present_state; 4411 case PCIC_TI_PCI1410: 4412 case PCIC_TI_PCI1520: 4413 case PCIC_TI_PCI1420: 4414 case PCIC_ENE_1420: 4415 case PCIC_TOSHIBA_TOPIC100: 4416 case PCIC_TOSHIBA_TOPIC95: 4417 case PCIC_TOSHIBA_VENDOR: 4418 case PCIC_O2MICRO_VENDOR: 4419 case PCIC_TI_VENDOR: 4420 case PCIC_RICOH_VENDOR: 4421 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4422 if (present_state & PCIC_CB_CARD) 4423 status->IFType = IF_CARDBUS; 4424 #if defined(PCIC_DEBUG) 4425 if (pcic_debug >= 8) 4426 cmn_err(CE_CONT, "pcic_get_status: present_state=0x%x\n", 4427 present_state); 4428 #endif 4429 break; 4430 default: 4431 break; 4432 } 4433 4434 return (SUCCESS); 4435 } 4436 4437 /* 4438 * pcic_get_window() 4439 * SocketServices GetWindow function 4440 * returns state information about the specified window 4441 */ 4442 /*ARGSUSED*/ 4443 static int 4444 pcic_get_window(dev_info_t *dip, get_window_t *window) 4445 { 4446 anp_t *anp = ddi_get_driver_private(dip); 4447 pcicdev_t *pcic = anp->an_private; 4448 int socket, win; 4449 pcic_socket_t *sockp; 4450 pcs_memwin_t *winp; 4451 4452 socket = window->window / PCIC_NUMWINSOCK; 4453 win = window->window % PCIC_NUMWINSOCK; 4454 #if defined(PCIC_DEBUG) 4455 if (pcic_debug) { 4456 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4457 socket, win); 4458 } 4459 #endif 4460 4461 if (socket > pcic->pc_numsockets) 4462 return (BAD_WINDOW); 4463 4464 sockp = &pcic->pc_sockets[socket]; 4465 winp = &sockp->pcs_windows[win].mem; 4466 4467 window->socket = socket; 4468 window->size = winp->pcw_len; 4469 window->speed = winp->pcw_speed; 4470 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4471 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4472 4473 if (win >= PCIC_IOWINDOWS) { 4474 window->state = 0; 4475 } else { 4476 window->state = WS_IO; 4477 } 4478 if (winp->pcw_status & PCW_ENABLED) 4479 window->state |= WS_ENABLED; 4480 4481 if (winp->pcw_status & PCS_CARD_16BIT) 4482 window->state |= WS_16BIT; 4483 #if defined(PCIC_DEBUG) 4484 if (pcic_debug) 4485 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4486 window->size, (unsigned)window->speed, 4487 (void *)window->handle, window->state); 4488 #endif 4489 4490 return (SUCCESS); 4491 } 4492 4493 /* 4494 * pcic_ll_reset 4495 * low level reset 4496 * separated out so it can be called when already locked 4497 * 4498 * There are two variables that control the RESET timing: 4499 * pcic_prereset_time - time in mS before asserting RESET 4500 * pcic_reset_time - time in mS to assert RESET 4501 * 4502 */ 4503 int pcic_prereset_time = 1; 4504 int pcic_reset_time = 10; 4505 int pcic_postreset_time = 20; 4506 int pcic_vpp_is_vcc_during_reset = 0; 4507 4508 static int 4509 pcic_ll_reset(pcicdev_t *pcic, int socket) 4510 { 4511 int windowbits, iobits; 4512 uint32_t pwr; 4513 4514 /* save windows that were on */ 4515 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4516 if (pcic_reset_time == 0) 4517 return (windowbits); 4518 /* turn all windows off */ 4519 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4520 4521 #if defined(PCIC_DEBUG) 4522 pcic_err(pcic->dip, 6, 4523 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4524 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4525 pcic_getcb(pcic, CB_CONTROL), 4526 pcic_getcb(pcic, CB_PRESENT_STATE)); 4527 #endif 4528 4529 if (pcic_vpp_is_vcc_during_reset) { 4530 4531 /* 4532 * Set VPP to VCC for the duration of the reset - for aironet 4533 * card. 4534 */ 4535 if (pcic->pc_flags & PCF_CBPWRCTL) { 4536 pwr = pcic_getcb(pcic, CB_CONTROL); 4537 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4538 (void) pcic_getcb(pcic, CB_CONTROL); 4539 } else { 4540 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4541 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4542 pwr | 1); 4543 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4544 } 4545 } 4546 4547 if (pcic_prereset_time > 0) { 4548 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4549 pcic_prereset_time); 4550 pcic_mswait(pcic, socket, pcic_prereset_time); 4551 } 4552 4553 /* turn interrupts off and start a reset */ 4554 pcic_err(pcic->dip, 8, 4555 "pcic_ll_reset turn interrupts off and start a reset\n"); 4556 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4557 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4558 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4559 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4560 4561 switch (pcic->pc_type) { 4562 case PCIC_INTEL_i82092: 4563 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4564 PCIC_82092_INT_DISABLE); 4565 break; 4566 default: 4567 break; 4568 } /* switch */ 4569 4570 pcic->pc_sockets[socket].pcs_state = 0; 4571 4572 if (pcic_reset_time > 0) { 4573 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4574 pcic_reset_time); 4575 pcic_mswait(pcic, socket, pcic_reset_time); 4576 } 4577 4578 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4579 4580 /* take it out of RESET now */ 4581 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4582 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4583 4584 /* 4585 * can't access the card for 20ms, but we really don't 4586 * want to sit around that long. The pcic is still usable. 4587 * memory accesses must wait for RDY to come up. 4588 */ 4589 if (pcic_postreset_time > 0) { 4590 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4591 pcic_postreset_time); 4592 pcic_mswait(pcic, socket, pcic_postreset_time); 4593 } 4594 4595 if (pcic_vpp_is_vcc_during_reset > 1) { 4596 4597 /* 4598 * Return VPP power to whatever it was before. 4599 */ 4600 if (pcic->pc_flags & PCF_CBPWRCTL) { 4601 pcic_putcb(pcic, CB_CONTROL, pwr); 4602 (void) pcic_getcb(pcic, CB_CONTROL); 4603 } else { 4604 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4605 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4606 } 4607 } 4608 4609 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4610 4611 return (windowbits); 4612 } 4613 4614 /* 4615 * pcic_reset_socket() 4616 * SocketServices ResetSocket function 4617 * puts the PC Card in the socket into the RESET state 4618 * and then takes it out after the the cycle time 4619 * The socket is back to initial state when done 4620 */ 4621 static int 4622 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4623 { 4624 anp_t *anp = ddi_get_driver_private(dip); 4625 pcicdev_t *pcic = anp->an_private; 4626 int value; 4627 int i, mint; 4628 pcic_socket_t *sockp; 4629 4630 #if defined(PCIC_DEBUG) 4631 if (pcic_debug >= 8) 4632 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4633 (void *)dip, socket, mode, 4634 mode == RESET_MODE_FULL ? "full" : "partial"); 4635 #endif 4636 4637 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4638 4639 /* Turn off management interupts. */ 4640 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4641 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4642 4643 sockp = &pcic->pc_sockets[socket]; 4644 4645 value = pcic_ll_reset(pcic, socket); 4646 if (mode == RESET_MODE_FULL) { 4647 /* disable and unmap all mapped windows */ 4648 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4649 if (i < PCIC_IOWINDOWS) { 4650 if (sockp->pcs_windows[i].io.pcw_status & 4651 PCW_MAPPED) { 4652 pcs_iowin_t *io; 4653 io = &sockp->pcs_windows[i].io; 4654 io->pcw_status &= ~PCW_ENABLED; 4655 } 4656 } else { 4657 if (sockp->pcs_windows[i].mem.pcw_status & 4658 PCW_MAPPED) { 4659 pcs_memwin_t *mem; 4660 mem = &sockp->pcs_windows[i].mem; 4661 mem->pcw_status &= ~PCW_ENABLED; 4662 } 4663 } 4664 } 4665 } else { 4666 /* turn windows back on */ 4667 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4668 /* wait the rest of the time here */ 4669 pcic_mswait(pcic, socket, 10); 4670 } 4671 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4672 mutex_exit(&pcic->pc_lock); 4673 return (SUCCESS); 4674 } 4675 4676 /* 4677 * pcic_set_interrupt() 4678 * SocketServices SetInterrupt function 4679 */ 4680 static int 4681 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4682 { 4683 anp_t *anp = ddi_get_driver_private(dip); 4684 pcicdev_t *pcic = anp->an_private; 4685 int value = DDI_SUCCESS; 4686 inthandler_t *intr; 4687 4688 #if defined(PCIC_DEBUG) 4689 if (pcic_debug) { 4690 cmn_err(CE_CONT, 4691 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4692 pcic->pc_intr_mode); 4693 cmn_err(CE_CONT, 4694 "\t irq_top=%p handler=%p handler_id=%x\n", 4695 (void *)pcic->irq_top, (void *)handler->handler, 4696 handler->handler_id); 4697 } 4698 #endif 4699 4700 /* 4701 * If we're on a PCI bus, we route all IO IRQs through a single 4702 * PCI interrupt (typically INT A#) so we don't have to do 4703 * much other than add the caller to general interrupt handler 4704 * and set some state. 4705 */ 4706 4707 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4708 if (intr == NULL) 4709 return (NO_RESOURCE); 4710 4711 switch (pcic->pc_intr_mode) { 4712 case PCIC_INTR_MODE_PCI_1: 4713 /* 4714 * We only allow above-lock-level IO IRQ handlers 4715 * in the PCI bus case. 4716 */ 4717 4718 mutex_enter(&pcic->intr_lock); 4719 4720 if (pcic->irq_top == NULL) { 4721 pcic->irq_top = intr; 4722 pcic->irq_current = pcic->irq_top; 4723 } else { 4724 while (pcic->irq_current->next != NULL) 4725 pcic->irq_current = pcic->irq_current->next; 4726 pcic->irq_current->next = intr; 4727 pcic->irq_current = pcic->irq_current->next; 4728 } 4729 4730 pcic->irq_current->intr = 4731 (ddi_intr_handler_t *)handler->handler; 4732 pcic->irq_current->handler_id = handler->handler_id; 4733 pcic->irq_current->arg1 = handler->arg1; 4734 pcic->irq_current->arg2 = handler->arg2; 4735 pcic->irq_current->socket = handler->socket; 4736 4737 mutex_exit(&pcic->intr_lock); 4738 4739 handler->iblk_cookie = &pcic->pc_pri; 4740 handler->idev_cookie = &pcic->pc_dcookie; 4741 break; 4742 4743 default: 4744 intr->intr = (ddi_intr_handler_t *)handler->handler; 4745 intr->handler_id = handler->handler_id; 4746 intr->arg1 = handler->arg1; 4747 intr->arg2 = handler->arg2; 4748 intr->socket = handler->socket; 4749 intr->irq = handler->irq; 4750 4751 /* 4752 * need to revisit this to see if interrupts can be 4753 * shared someday. Note that IRQ is set in the common 4754 * code. 4755 */ 4756 mutex_enter(&pcic->pc_lock); 4757 if (pcic->pc_handlers == NULL) { 4758 pcic->pc_handlers = intr; 4759 intr->next = intr->prev = intr; 4760 } else { 4761 insque(intr, pcic->pc_handlers); 4762 } 4763 mutex_exit(&pcic->pc_lock); 4764 4765 break; 4766 } 4767 4768 /* 4769 * need to fill in cookies in event of multiple high priority 4770 * interrupt handlers on same IRQ 4771 */ 4772 4773 #if defined(PCIC_DEBUG) 4774 if (pcic_debug) { 4775 cmn_err(CE_CONT, 4776 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4777 (void *)pcic->irq_top, value); 4778 } 4779 #endif 4780 4781 if (value == DDI_SUCCESS) { 4782 return (SUCCESS); 4783 } else { 4784 return (BAD_IRQ); 4785 } 4786 } 4787 4788 /* 4789 * pcic_clear_interrupt() 4790 * SocketServices ClearInterrupt function 4791 * 4792 * Interrupts for PCIC are complicated by the fact that we must 4793 * follow several different models for interrupts. 4794 * ISA: there is an interrupt per adapter and per socket and 4795 * they can't be shared. 4796 * PCI: some adapters have one PCI interrupt available while others 4797 * have up to 4. Solaris may or may not allow us to use more 4798 * than 1 so we essentially share them all at this point. 4799 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4800 * This is like ISA but we have to fudge and create an intrspec 4801 * that PCI's parent understands and bypass the PCI nexus. 4802 * multifunction: this requires sharing the interrupts on a per-socket 4803 * basis. 4804 */ 4805 static int 4806 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4807 { 4808 anp_t *anp = ddi_get_driver_private(dip); 4809 pcicdev_t *pcic = anp->an_private; 4810 inthandler_t *intr, *prev, *current; 4811 int i; 4812 4813 /* 4814 * If we're on a PCI bus, we route all IO IRQs through a single 4815 * PCI interrupt (typically INT A#) so we don't have to do 4816 * much other than remove the caller from the general 4817 * interrupt handler callout list. 4818 */ 4819 4820 #if defined(PCIC_DEBUG) 4821 if (pcic_debug) { 4822 cmn_err(CE_CONT, 4823 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4824 pcic->pc_intr_mode); 4825 cmn_err(CE_CONT, 4826 "\t irq_top=%p handler=%p handler_id=%x\n", 4827 (void *)pcic->irq_top, (void *)handler->handler, 4828 handler->handler_id); 4829 } 4830 #endif 4831 4832 switch (pcic->pc_intr_mode) { 4833 case PCIC_INTR_MODE_PCI_1: 4834 4835 mutex_enter(&pcic->intr_lock); 4836 if (pcic->irq_top == NULL) { 4837 mutex_exit(&pcic->intr_lock); 4838 return (BAD_IRQ); 4839 } 4840 4841 intr = NULL; 4842 pcic->irq_current = pcic->irq_top; 4843 4844 while ((pcic->irq_current != NULL) && 4845 (pcic->irq_current->handler_id != 4846 handler->handler_id)) { 4847 intr = pcic->irq_current; 4848 pcic->irq_current = pcic->irq_current->next; 4849 } 4850 4851 if (pcic->irq_current == NULL) { 4852 mutex_exit(&pcic->intr_lock); 4853 return (BAD_IRQ); 4854 } 4855 4856 if (intr != NULL) { 4857 intr->next = pcic->irq_current->next; 4858 } else { 4859 pcic->irq_top = pcic->irq_current->next; 4860 } 4861 4862 current = pcic->irq_current; 4863 pcic->irq_current = pcic->irq_top; 4864 mutex_exit(&pcic->intr_lock); 4865 kmem_free(current, sizeof (inthandler_t)); 4866 4867 break; 4868 4869 default: 4870 4871 mutex_enter(&pcic->pc_lock); 4872 intr = pcic_handlers; 4873 prev = (inthandler_t *)&pcic_handlers; 4874 4875 while (intr != NULL) { 4876 if (intr->handler_id == handler->handler_id) { 4877 i = intr->irq & PCIC_INTR_MASK; 4878 if (--pcic_irq_map[i].count == 0) { 4879 /* multi-handler form */ 4880 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4881 (void) ddi_intr_remove_handler( 4882 pcic->pc_intr_htblp[i]); 4883 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4884 (void) pcmcia_return_intr(pcic->dip, i); 4885 #if defined(PCIC_DEBUG) 4886 if (pcic_debug) { 4887 cmn_err(CE_CONT, 4888 "removing interrupt %d at %s " 4889 "priority\n", i, "high"); 4890 cmn_err(CE_CONT, 4891 "ddi_remove_intr(%p, %x, %p)\n", 4892 (void *)dip, 4893 0, 4894 (void *)intr->iblk_cookie); 4895 } 4896 #endif 4897 } 4898 prev->next = intr->next; 4899 kmem_free(intr, sizeof (inthandler_t)); 4900 intr = prev->next; 4901 } else { 4902 prev = intr; 4903 intr = intr->next; 4904 } /* if (handler_id) */ 4905 } /* while */ 4906 4907 mutex_exit(&pcic->pc_lock); 4908 } 4909 4910 #if defined(PCIC_DEBUG) 4911 if (pcic_debug) { 4912 cmn_err(CE_CONT, 4913 "pcic_clear_interrupt: exit irq_top=%p\n", 4914 (void *)pcic->irq_top); 4915 } 4916 #endif 4917 4918 4919 return (SUCCESS); 4920 } 4921 4922 struct intel_regs { 4923 char *name; 4924 int off; 4925 char *fmt; 4926 } iregs[] = { 4927 {"ident ", 0}, 4928 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4929 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4930 "\7DRD\10OE"}, 4931 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4932 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4933 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4934 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4935 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4936 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4937 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4938 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4939 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4940 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4941 {"io0-slow ", 8}, 4942 {"io0-shi ", 9}, 4943 {"io0-elow ", 0xa}, 4944 {"io0-ehi ", 0xb}, 4945 {"io1-slow ", 0xc}, 4946 {"io1-shi ", 0xd}, 4947 {"io1-elow ", 0xe}, 4948 {"io1-ehi ", 0xf}, 4949 {"mem0-slow ", 0x10}, 4950 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4951 {"mem0-elow ", 0x12}, 4952 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4953 {"card0-low ", 0x14}, 4954 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4955 {"mem1-slow ", 0x18}, 4956 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4957 {"mem1-elow ", 0x1a}, 4958 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4959 {"card1-low ", 0x1c}, 4960 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4961 {"mem2-slow ", 0x20}, 4962 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4963 {"mem2-elow ", 0x22}, 4964 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4965 {"card2-low ", 0x24}, 4966 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4967 {"mem3-slow ", 0x28}, 4968 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4969 {"mem3-elow ", 0x2a}, 4970 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4971 {"card3-low ", 0x2c}, 4972 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4973 4974 {"mem4-slow ", 0x30}, 4975 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4976 {"mem4-elow ", 0x32}, 4977 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4978 {"card4-low ", 0x34}, 4979 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4980 {"mpage0 ", 0x40}, 4981 {"mpage1 ", 0x41}, 4982 {"mpage2 ", 0x42}, 4983 {"mpage3 ", 0x43}, 4984 {"mpage4 ", 0x44}, 4985 {NULL}, 4986 }; 4987 4988 static struct intel_regs cregs[] = { 4989 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 4990 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 4991 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 4992 {"chip-info ", 0x1f, "\20\6DUAL"}, 4993 {"IO-offlow0", 0x36}, 4994 {"IO-offhi0 ", 0x37}, 4995 {"IO-offlow1", 0x38}, 4996 {"IO-offhi1 ", 0x39}, 4997 NULL, 4998 }; 4999 5000 static struct intel_regs cxregs[] = { 5001 {"ext-ctl-1 ", 0x03, 5002 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 5003 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 5004 {"mem0-up ", 0x05}, 5005 {"mem1-up ", 0x06}, 5006 {"mem2-up ", 0x07}, 5007 {"mem3-up ", 0x08}, 5008 {"mem4-up ", 0x09}, 5009 {NULL} 5010 }; 5011 5012 void 5013 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 5014 { 5015 int i, value, j; 5016 char buff[256]; 5017 char *fmt; 5018 5019 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 5020 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 5021 int sval; 5022 if (cregs[i].off == PCIC_MISC_CTL_2) 5023 sval = 0; 5024 else 5025 sval = socket; 5026 value = pcic_getb(pcic, sval, cregs[i].off); 5027 if (i & 1) { 5028 if (cregs[i].fmt) 5029 fmt = "%s\t%s\t%b\n"; 5030 else 5031 fmt = "%s\t%s\t%x\n"; 5032 cmn_err(CE_CONT, fmt, buff, 5033 cregs[i].name, value, cregs[i].fmt); 5034 buff[0] = '\0'; 5035 } else { 5036 if (cregs[i].fmt) 5037 fmt = "\t%s\t%b"; 5038 else 5039 fmt = "\t%s\t%x"; 5040 (void) sprintf(buff, fmt, 5041 cregs[i].name, value, cregs[i].fmt); 5042 for (j = strlen(buff); j < 40; j++) 5043 buff[j] = ' '; 5044 buff[40] = '\0'; 5045 } 5046 } 5047 cmn_err(CE_CONT, "%s\n", buff); 5048 5049 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 5050 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 5051 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 5052 5053 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 5054 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 5055 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 5056 5057 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 5058 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 5059 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 5060 5061 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5062 5063 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5064 value = clext_reg_read(pcic, socket, cxregs[i].off); 5065 if (i & 1) { 5066 if (cxregs[i].fmt) 5067 fmt = "%s\t%s\t%b\n"; 5068 else 5069 fmt = "%s\t%s\t%x\n"; 5070 cmn_err(CE_CONT, fmt, buff, 5071 cxregs[i].name, value, cxregs[i].fmt); 5072 buff[0] = '\0'; 5073 } else { 5074 if (cxregs[i].fmt) 5075 fmt = "\t%s\t%b"; 5076 else 5077 fmt = "\t%s\t%x"; 5078 (void) sprintf(buff, fmt, 5079 cxregs[i].name, value, cxregs[i].fmt); 5080 for (j = strlen(buff); j < 40; j++) 5081 buff[j] = ' '; 5082 buff[40] = '\0'; 5083 } 5084 } 5085 } 5086 5087 #if defined(PCIC_DEBUG) 5088 static void 5089 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5090 { 5091 int i, value, j; 5092 char buff[256]; 5093 char *fmt; 5094 5095 #if defined(PCIC_DEBUG) 5096 if (pcic_debug < 2) 5097 return; 5098 #endif 5099 cmn_err(CE_CONT, 5100 "----------- PCIC Registers for socket %d---------\n", 5101 socket); 5102 cmn_err(CE_CONT, 5103 "\tname value name value\n"); 5104 5105 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5106 value = pcic_getb(pcic, socket, iregs[i].off); 5107 if (i & 1) { 5108 if (iregs[i].fmt) 5109 fmt = "%s\t%s\t%b\n"; 5110 else 5111 fmt = "%s\t%s\t%x\n"; 5112 cmn_err(CE_CONT, fmt, buff, 5113 iregs[i].name, value, iregs[i].fmt); 5114 buff[0] = '\0'; 5115 } else { 5116 if (iregs[i].fmt) 5117 fmt = "\t%s\t%b"; 5118 else 5119 fmt = "\t%s\t%x"; 5120 (void) sprintf(buff, fmt, 5121 iregs[i].name, value, iregs[i].fmt); 5122 for (j = strlen(buff); j < 40; j++) 5123 buff[j] = ' '; 5124 buff[40] = '\0'; 5125 } 5126 } 5127 switch (pcic->pc_type) { 5128 case PCIC_CL_PD6710: 5129 case PCIC_CL_PD6722: 5130 case PCIC_CL_PD6729: 5131 case PCIC_CL_PD6832: 5132 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5133 break; 5134 } 5135 cmn_err(CE_CONT, "%s\n", buff); 5136 } 5137 #endif 5138 5139 /* 5140 * pcic_mswait(ms) 5141 * sleep ms milliseconds 5142 * call drv_usecwait once for each ms 5143 */ 5144 static void 5145 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5146 { 5147 if (ms) { 5148 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5149 pcic_mutex_exit(&pcic->pc_lock); 5150 delay(drv_usectohz(ms*1000)); 5151 pcic_mutex_enter(&pcic->pc_lock); 5152 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5153 } 5154 } 5155 5156 /* 5157 * pcic_check_ready(pcic, index, off) 5158 * Wait for card to come ready 5159 * We only wait if the card is NOT in RESET 5160 * and power is on. 5161 */ 5162 static boolean_t 5163 pcic_check_ready(pcicdev_t *pcic, int socket) 5164 { 5165 int ifstate, intstate; 5166 5167 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5168 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5169 5170 if ((intstate & PCIC_RESET) && 5171 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5172 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5173 return (B_TRUE); 5174 5175 #ifdef PCIC_DEBUG 5176 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5177 "ifstate = 0x%x\n", intstate, ifstate); 5178 if (pcic_debug) { 5179 pcic_debug += 4; 5180 xxdmp_all_regs(pcic, socket, -1); 5181 pcic_debug -= 4; 5182 } 5183 #endif 5184 return (B_FALSE); 5185 } 5186 5187 /* 5188 * Cirrus Logic extended register read/write routines 5189 */ 5190 static int 5191 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5192 { 5193 int val; 5194 5195 switch (pcic->pc_io_type) { 5196 case PCIC_IO_TYPE_YENTA: 5197 val = ddi_get8(pcic->handle, 5198 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5199 break; 5200 default: 5201 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5202 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5203 break; 5204 } 5205 5206 return (val); 5207 } 5208 5209 static void 5210 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5211 { 5212 switch (pcic->pc_io_type) { 5213 case PCIC_IO_TYPE_YENTA: 5214 ddi_put8(pcic->handle, 5215 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5216 break; 5217 default: 5218 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5219 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5220 break; 5221 } 5222 } 5223 5224 /* 5225 * Misc PCI functions 5226 */ 5227 static void 5228 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5229 { 5230 unsigned cmd; 5231 5232 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5233 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5234 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5235 (PCI_COMM_IO|PCI_COMM_MAE)) 5236 return; 5237 5238 if (flags & PCIC_ENABLE_IO) 5239 cmd |= PCI_COMM_IO; 5240 5241 if (flags & PCIC_ENABLE_MEM) 5242 cmd |= PCI_COMM_MAE; 5243 5244 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5245 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5246 } 5247 5248 /* 5249 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5250 */ 5251 static int 5252 pcic_find_pci_type(pcicdev_t *pcic) 5253 { 5254 uint32_t vend, device; 5255 5256 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5257 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5258 "vendor-id", -1); 5259 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5260 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5261 "device-id", -1); 5262 5263 device = PCI_ID(vend, device); 5264 pcic->pc_type = device; 5265 pcic->pc_chipname = "PCI:unknown"; 5266 5267 switch (device) { 5268 case PCIC_INTEL_i82092: 5269 pcic->pc_chipname = PCIC_TYPE_i82092; 5270 break; 5271 case PCIC_CL_PD6729: 5272 pcic->pc_chipname = PCIC_TYPE_PD6729; 5273 /* 5274 * Some 6730's incorrectly identify themselves 5275 * as a 6729, so we need to do some more tests 5276 * here to see if the device that's claiming 5277 * to be a 6729 is really a 6730. 5278 */ 5279 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5280 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5281 0) { 5282 pcic->pc_chipname = PCIC_TYPE_PD6730; 5283 pcic->pc_type = PCIC_CL_PD6730; 5284 } 5285 break; 5286 case PCIC_CL_PD6730: 5287 pcic->pc_chipname = PCIC_TYPE_PD6730; 5288 break; 5289 case PCIC_CL_PD6832: 5290 pcic->pc_chipname = PCIC_TYPE_PD6832; 5291 break; 5292 case PCIC_SMC_34C90: 5293 pcic->pc_chipname = PCIC_TYPE_34C90; 5294 break; 5295 case PCIC_TOSHIBA_TOPIC95: 5296 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5297 break; 5298 case PCIC_TOSHIBA_TOPIC100: 5299 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5300 break; 5301 case PCIC_TI_PCI1031: 5302 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5303 break; 5304 case PCIC_TI_PCI1130: 5305 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5306 break; 5307 case PCIC_TI_PCI1131: 5308 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5309 break; 5310 case PCIC_TI_PCI1250: 5311 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5312 break; 5313 case PCIC_TI_PCI1225: 5314 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5315 break; 5316 case PCIC_TI_PCI1410: 5317 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5318 break; 5319 case PCIC_TI_PCI1510: 5320 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5321 break; 5322 case PCIC_TI_PCI1520: 5323 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5324 break; 5325 case PCIC_TI_PCI1221: 5326 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5327 break; 5328 case PCIC_TI_PCI1050: 5329 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5330 break; 5331 case PCIC_ENE_1410: 5332 pcic->pc_chipname = PCIC_TYPE_1410; 5333 break; 5334 case PCIC_O2_OZ6912: 5335 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5336 break; 5337 case PCIC_RICOH_RL5C466: 5338 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5339 break; 5340 case PCIC_TI_PCI1420: 5341 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5342 break; 5343 case PCIC_ENE_1420: 5344 pcic->pc_chipname = PCIC_TYPE_1420; 5345 break; 5346 default: 5347 switch (PCI_ID(vend, (uint32_t)0)) { 5348 case PCIC_TOSHIBA_VENDOR: 5349 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5350 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5351 break; 5352 case PCIC_TI_VENDOR: 5353 pcic->pc_chipname = PCIC_TYPE_TI; 5354 pcic->pc_type = PCIC_TI_VENDOR; 5355 break; 5356 case PCIC_O2MICRO_VENDOR: 5357 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5358 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5359 break; 5360 case PCIC_RICOH_VENDOR: 5361 pcic->pc_chipname = PCIC_TYPE_RICOH; 5362 pcic->pc_type = PCIC_RICOH_VENDOR; 5363 break; 5364 default: 5365 if (!(pcic->pc_flags & PCF_CARDBUS)) 5366 return (DDI_FAILURE); 5367 pcic->pc_chipname = PCIC_TYPE_YENTA; 5368 break; 5369 } 5370 } 5371 return (DDI_SUCCESS); 5372 } 5373 5374 static void 5375 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5376 { 5377 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5378 pcic->cfgaddr + PCIC_82092_PPIRR); 5379 uchar_t val; 5380 5381 if (intr == PCIC_82092_CTL_SMI) { 5382 val = PCIC_82092_SMI_CTL(socket, 5383 PCIC_82092_INT_DISABLE); 5384 ppirr &= ~val; 5385 val = PCIC_82092_SMI_CTL(socket, state); 5386 ppirr |= val; 5387 } else { 5388 val = PCIC_82092_IRQ_CTL(socket, 5389 PCIC_82092_INT_DISABLE); 5390 ppirr &= ~val; 5391 val = PCIC_82092_IRQ_CTL(socket, state); 5392 ppirr |= val; 5393 } 5394 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5395 ppirr); 5396 } 5397 5398 static uint_t 5399 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5400 { 5401 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5402 uint_t rc = DDI_INTR_UNCLAIMED; 5403 5404 _NOTE(ARGUNUSED(arg2)) 5405 5406 mutex_enter(&sockp->pcs_pcic->pc_lock); 5407 if (sockp->pcs_cd_softint_flg) { 5408 uint8_t status; 5409 sockp->pcs_cd_softint_flg = 0; 5410 rc = DDI_INTR_CLAIMED; 5411 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5412 PCIC_INTERFACE_STATUS); 5413 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5414 } 5415 mutex_exit(&sockp->pcs_pcic->pc_lock); 5416 return (rc); 5417 } 5418 5419 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5420 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5421 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5422 5423 #ifdef CARDBUS 5424 static uint32_t pcic_cbps_on = 0; 5425 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5426 CB_PS_XVCARD | CB_PS_YVCARD; 5427 #else 5428 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5429 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5430 CB_PS_CBCARD | 5431 CB_PS_XVCARD | CB_PS_YVCARD; 5432 #endif 5433 static void 5434 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5435 { 5436 boolean_t do_debounce = B_FALSE; 5437 int debounce_time = drv_usectohz(pcic_debounce_time); 5438 uint8_t irq; 5439 timeout_id_t debounce; 5440 5441 /* 5442 * Always reset debounce but may need to check original state later. 5443 */ 5444 debounce = sockp->pcs_debounce_id; 5445 sockp->pcs_debounce_id = 0; 5446 5447 /* 5448 * Check to see whether a card is present or not. There are 5449 * only two states that we are concerned with - the state 5450 * where both CD pins are asserted, which means that the 5451 * card is fully seated, and the state where neither CD 5452 * pin is asserted, which means that the card is not 5453 * present. 5454 * The CD signals are generally very noisy and cause a lot of 5455 * contact bounce as the card is being inserted and 5456 * removed, so we need to do some software debouncing. 5457 */ 5458 5459 #ifdef PCIC_DEBUG 5460 pcic_err(pcic->dip, 6, 5461 "pcic%d handle_cd_change: socket %d card status 0x%x" 5462 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5463 sockp->pcs_socket, status, debounce); 5464 #endif 5465 switch (status & PCIC_ISTAT_CD_MASK) { 5466 case PCIC_CD_PRESENT_OK: 5467 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5468 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5469 uint32_t cbps; 5470 #ifdef PCIC_DEBUG 5471 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5472 #endif 5473 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5474 #ifdef PCIC_DEBUG 5475 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5476 #endif 5477 /* 5478 * Check the CB bits are sane. 5479 */ 5480 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5481 cbps & pcic_cbps_off) { 5482 cmn_err(CE_WARN, 5483 "%s%d: Odd Cardbus Present State 0x%x\n", 5484 ddi_get_name(pcic->dip), 5485 ddi_get_instance(pcic->dip), 5486 cbps); 5487 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5488 debounce = 0; 5489 debounce_time = drv_usectohz(1000000); 5490 } 5491 if (debounce) { 5492 sockp->pcs_flags |= PCS_CARD_PRESENT; 5493 if (pcic_do_insertion) { 5494 5495 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5496 5497 if (cbps & CB_PS_16BITCARD) { 5498 pcic_err(pcic->dip, 8, "16 bit card inserted\n"); 5499 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5500 /* calls pcm_adapter_callback() */ 5501 if (pcic->pc_callback) { 5502 5503 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 5504 pcic->dip, PCM_DEVICETYPE, 5505 "pccard"); 5506 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5507 PCE_CARD_INSERT, 5508 sockp->pcs_socket); 5509 } 5510 } else if (cbps & CB_PS_CBCARD) { 5511 pcic_err(pcic->dip, 8, "32 bit card inserted\n"); 5512 5513 if (pcic->pc_flags & PCF_CARDBUS) { 5514 sockp->pcs_flags |= PCS_CARD_ISCARDBUS; 5515 #ifdef CARDBUS 5516 if (!pcic_load_cardbus(pcic, sockp)) { 5517 pcic_unload_cardbus(pcic, sockp); 5518 } 5519 5520 #else 5521 cmn_err(CE_NOTE, 5522 "32 bit Cardbus not supported in" 5523 " this device driver\n"); 5524 #endif 5525 } else { 5526 /* 5527 * Ignore the card 5528 */ 5529 cmn_err(CE_NOTE, 5530 "32 bit Cardbus not supported on this" 5531 " device\n"); 5532 } 5533 } else { 5534 cmn_err(CE_NOTE, 5535 "Unsupported PCMCIA card inserted\n"); 5536 } 5537 } 5538 syshw_send_signal(sockp->pcs_syshwsig); 5539 } else { 5540 do_debounce = B_TRUE; 5541 } 5542 } else { 5543 /* 5544 * It is possible to come through here if the system 5545 * starts up with cards already inserted. Do nothing 5546 * and don't worry about it. 5547 */ 5548 #ifdef PCIC_DEBUG 5549 pcic_err(pcic->dip, 5, 5550 "pcic%d: Odd card insertion indication on socket %d\n", 5551 ddi_get_instance(pcic->dip), 5552 sockp->pcs_socket); 5553 #endif 5554 } 5555 break; 5556 5557 default: 5558 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5559 /* 5560 * Someone has started to insert a card so delay a while. 5561 */ 5562 do_debounce = B_TRUE; 5563 break; 5564 } 5565 /* 5566 * Otherwise this is basically the same as not present 5567 * so fall through. 5568 */ 5569 5570 /* FALLTHRU */ 5571 case 0: 5572 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5573 if (pcic->pc_flags & PCF_CBPWRCTL) { 5574 pcic_putcb(pcic, CB_CONTROL, 0); 5575 } else { 5576 pcic_putb(pcic, sockp->pcs_socket, PCIC_POWER_CONTROL, 0); 5577 (void) pcic_getb(pcic, sockp->pcs_socket, 5578 PCIC_POWER_CONTROL); 5579 } 5580 #ifdef PCIC_DEBUG 5581 pcic_err(pcic->dip, 8, "Card removed\n"); 5582 #endif 5583 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5584 5585 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5586 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5587 if (pcic_do_removal && pcic->pc_callback) { 5588 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5589 PCE_CARD_REMOVAL, sockp->pcs_socket); 5590 } 5591 } 5592 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5593 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5594 sockp->pcs_flags |= PCS_CARD_CBREM; 5595 } 5596 sockp->pcs_flags |= PCS_CARD_REMOVED; 5597 5598 do_debounce = B_TRUE; 5599 } 5600 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5601 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5602 /* 5603 * Ensure that we do the unloading in the 5604 * debounce handler, that way we're not doing 5605 * nasty things in an interrupt handler. e.g. 5606 * a USB device will wait for data which will 5607 * obviously never come because we've 5608 * unplugged the device, but the wait will 5609 * wait forever because no interrupts can 5610 * come in... 5611 */ 5612 #ifdef CARDBUS 5613 pcic_unload_cardbus(pcic, sockp); 5614 /* pcic_dump_all(pcic); */ 5615 #endif 5616 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5617 } 5618 syshw_send_signal(sockp->pcs_syshwsig); 5619 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5620 } 5621 break; 5622 } /* switch */ 5623 5624 if (do_debounce) { 5625 /* 5626 * Delay doing 5627 * anything for a while so that things can settle 5628 * down a little. Interrupts are already disabled. 5629 * Reset the state and we'll reevaluate the 5630 * whole kit 'n kaboodle when the timeout fires 5631 */ 5632 #ifdef PCIC_DEBUG 5633 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5634 "socket %d.%d\n", 5635 ddi_get_instance(pcic->dip), 5636 sockp->pcs_socket); 5637 #endif 5638 sockp->pcs_debounce_id = pcic_add_debqueue(sockp, debounce_time); 5639 5640 /* 5641 * We bug out here without re-enabling interrupts. They will 5642 * be re-enabled when the debounce timeout swings through 5643 * here. 5644 */ 5645 return; 5646 } 5647 5648 /* 5649 * Turn on Card detect interrupts. Other interrupts will be 5650 * enabled during set_socket calls. 5651 * 5652 * Note that set_socket only changes interrupt settings when there 5653 * is a card present. 5654 */ 5655 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5656 irq |= PCIC_CD_DETECT; 5657 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5658 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5659 5660 /* Out from debouncing state */ 5661 sockp->pcs_flags &= ~PCS_DEBOUNCING; 5662 5663 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5664 } 5665 5666 /* 5667 * pcic_getb() 5668 * get an I/O byte based on the yardware decode method 5669 */ 5670 static uint8_t 5671 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5672 { 5673 int work; 5674 5675 #if defined(PCIC_DEBUG) 5676 if (pcic_debug == 0x7fff) { 5677 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5678 (void *)pcic, socket, reg); 5679 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5680 pcic->pc_io_type, (void *)pcic->handle, 5681 (void *)pcic->ioaddr); 5682 } 5683 #endif 5684 5685 switch (pcic->pc_io_type) { 5686 case PCIC_IO_TYPE_YENTA: 5687 return (ddi_get8(pcic->handle, 5688 pcic->ioaddr + CB_R2_OFFSET + reg)); 5689 default: 5690 work = (socket * PCIC_SOCKET_1) | reg; 5691 ddi_put8(pcic->handle, pcic->ioaddr, work); 5692 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5693 } 5694 } 5695 5696 static void 5697 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5698 { 5699 int work; 5700 5701 #if defined(PCIC_DEBUG) 5702 if (pcic_debug == 0x7fff) { 5703 cmn_err(CE_CONT, 5704 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5705 (void *)pcic, socket, reg, value); 5706 cmn_err(CE_CONT, 5707 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5708 pcic->pc_io_type, (void *)pcic->handle, 5709 (void *)pcic->ioaddr); 5710 } 5711 #endif 5712 5713 5714 switch (pcic->pc_io_type) { 5715 case PCIC_IO_TYPE_YENTA: 5716 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5717 value); 5718 break; 5719 default: 5720 work = (socket * PCIC_SOCKET_1) | reg; 5721 ddi_put8(pcic->handle, pcic->ioaddr, work); 5722 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5723 break; 5724 } 5725 } 5726 5727 /* 5728 * chip identification functions 5729 */ 5730 5731 /* 5732 * chip identification: Cirrus Logic PD6710/6720/6722 5733 */ 5734 static int 5735 pcic_ci_cirrus(pcicdev_t *pcic) 5736 { 5737 int value1, value2; 5738 5739 /* Init the CL id mode */ 5740 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5741 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5742 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5743 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5744 5745 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5746 (value2 & PCIC_CI_ID) == 0) { 5747 /* chip is a Cirrus Logic and not Intel */ 5748 pcic->pc_type = PCIC_CL_PD6710; 5749 if (value1 & PCIC_CI_SLOTS) 5750 pcic->pc_chipname = PCIC_TYPE_PD6720; 5751 else 5752 pcic->pc_chipname = PCIC_TYPE_PD6710; 5753 /* now fine tune things just in case a 6722 */ 5754 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5755 if (value1 == 0) { 5756 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5757 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5758 if (value1 == 0x55) { 5759 pcic->pc_chipname = PCIC_TYPE_PD6722; 5760 pcic->pc_type = PCIC_CL_PD6722; 5761 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5762 } 5763 } 5764 return (1); 5765 } 5766 return (0); 5767 } 5768 5769 /* 5770 * chip identification: Vadem (VG365/465/468/469) 5771 */ 5772 5773 static void 5774 pcic_vadem_enable(pcicdev_t *pcic) 5775 { 5776 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5777 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5778 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5779 } 5780 5781 static int 5782 pcic_ci_vadem(pcicdev_t *pcic) 5783 { 5784 int value; 5785 5786 pcic_vadem_enable(pcic); 5787 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5788 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5789 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5790 (value | PCIC_VADEM_D3) || 5791 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5792 PCIC_VADEM_469) { 5793 int vadem, new; 5794 pcic_vadem_enable(pcic); 5795 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5796 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5797 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5798 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5799 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5800 5801 /* want to lock but leave mouse or other on */ 5802 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5803 switch (value & PCIC_REV_MASK) { 5804 case PCIC_VADEM_365: 5805 pcic->pc_chipname = PCIC_VG_365; 5806 pcic->pc_type = PCIC_VADEM; 5807 break; 5808 case PCIC_VADEM_465: 5809 pcic->pc_chipname = PCIC_VG_465; 5810 pcic->pc_type = PCIC_VADEM; 5811 pcic->pc_flags |= PCF_1SOCKET; 5812 break; 5813 case PCIC_VADEM_468: 5814 pcic->pc_chipname = PCIC_VG_468; 5815 pcic->pc_type = PCIC_VADEM; 5816 break; 5817 case PCIC_VADEM_469: 5818 pcic->pc_chipname = PCIC_VG_469; 5819 pcic->pc_type = PCIC_VADEM_VG469; 5820 break; 5821 } 5822 return (1); 5823 } 5824 return (0); 5825 } 5826 5827 /* 5828 * chip identification: Ricoh 5829 */ 5830 static int 5831 pcic_ci_ricoh(pcicdev_t *pcic) 5832 { 5833 int value; 5834 5835 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5836 switch (value) { 5837 case PCIC_RF_296: 5838 pcic->pc_type = PCIC_RICOH; 5839 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5840 return (1); 5841 case PCIC_RF_396: 5842 pcic->pc_type = PCIC_RICOH; 5843 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5844 return (1); 5845 } 5846 return (0); 5847 } 5848 5849 5850 /* 5851 * set up available address spaces in busra 5852 */ 5853 static void 5854 pcic_init_assigned(dev_info_t *dip) 5855 { 5856 pcm_regs_t *pcic_avail_p; 5857 pci_regspec_t *pci_avail_p, *regs; 5858 int len, entries, rlen; 5859 dev_info_t *pdip; 5860 5861 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5862 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5863 /* 5864 * found "available" property at the cardbus/pcmcia node 5865 * need to translate address space entries from pcmcia 5866 * format to pci format 5867 */ 5868 entries = len / sizeof (pcm_regs_t); 5869 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5870 KM_SLEEP); 5871 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5872 entries) == DDI_SUCCESS) 5873 (void) pci_resource_setup_avail(dip, pci_avail_p, 5874 entries); 5875 kmem_free(pcic_avail_p, len); 5876 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5877 return; 5878 } 5879 5880 /* 5881 * "legacy" platforms will have "available" property in pci node 5882 */ 5883 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5884 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5885 "available", (caddr_t)&pci_avail_p, &len) == 5886 DDI_PROP_SUCCESS) { 5887 /* (void) pci_resource_setup(pdip); */ 5888 kmem_free(pci_avail_p, len); 5889 break; 5890 } 5891 } 5892 5893 if (pdip == NULL) { 5894 int len; 5895 char bus_type[16] = "(unknown)"; 5896 dev_info_t *par; 5897 5898 cmn_err(CE_CONT, 5899 "?pcic_init_assigned: no available property for pcmcia\n"); 5900 5901 /* 5902 * This code is taken from pci_resource_setup() but does 5903 * not attempt to use the "available" property to populate 5904 * the ndi maps that are created. 5905 * The fact that we will actually 5906 * free some resource below (that was allocated by OBP) 5907 * should be enough to be going on with. 5908 */ 5909 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5910 len = sizeof (bus_type); 5911 5912 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5913 PROP_LEN_AND_VAL_BUF, 5914 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5915 "device_type", 5916 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5917 (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 5918 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0)) 5919 break; 5920 } 5921 if (par != NULL && 5922 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5923 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5924 par = NULL; 5925 } else { 5926 #ifdef CARDBUS 5927 cardbus_bus_range_t *bus_range; 5928 int k; 5929 5930 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5931 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5932 if (bus_range->lo != bus_range->hi) 5933 pcic_err(pdip, 9, "allowable bus range is " 5934 "%u->%u\n", bus_range->lo, bus_range->hi); 5935 else { 5936 pcic_err(pdip, 0, 5937 "!No spare PCI bus numbers, range is " 5938 "%u->%u, cardbus isn't usable\n", 5939 bus_range->lo, bus_range->hi); 5940 } 5941 kmem_free(bus_range, k); 5942 } else 5943 pcic_err(pdip, 0, "!No bus-range property seems to " 5944 "have been set up\n"); 5945 #endif 5946 /* 5947 * Have a valid parent with the "available" property 5948 */ 5949 (void) pci_resource_setup(pdip); 5950 } 5951 5952 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5953 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5954 "assigned-addresses", 5955 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5956 ra_return_t ra; 5957 5958 /* 5959 * On the UltraBook IIi the ranges are assigned under 5960 * openboot. If we don't free them here the first I/O 5961 * space that can be used is up above 0x10000 which 5962 * doesn't work for this driver due to restrictions 5963 * on the PCI I/O addresses the controllers can cope with. 5964 * They are never going to be used by anything else 5965 * so free them up to the general pool. AG. 5966 */ 5967 pcic_err(dip, 1, "Free assigned addresses\n"); 5968 5969 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5970 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5971 regs[0].pci_size_low == 0x1000000) { 5972 ra.ra_addr_lo = regs[0].pci_phys_low; 5973 ra.ra_len = regs[0].pci_size_low; 5974 (void) pcmcia_free_mem(dip, &ra); 5975 } 5976 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5977 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5978 (regs[1].pci_size_low == 0x8000 || 5979 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5980 { 5981 ra.ra_addr_lo = regs[1].pci_phys_low; 5982 ra.ra_len = regs[1].pci_size_low; 5983 (void) pcmcia_free_io(dip, &ra); 5984 } 5985 kmem_free((caddr_t)regs, rlen); 5986 } 5987 } 5988 5989 /* 5990 * translate "available" from pcmcia format to pci format 5991 */ 5992 static int 5993 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 5994 pci_regspec_t *pci_p, int entries) 5995 { 5996 int i, range_len, range_entries; 5997 pcic_ranges_t *pcic_range_p; 5998 5999 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 6000 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 6001 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 6002 "no ranges property for pcmcia\n"); 6003 return (DDI_FAILURE); 6004 } 6005 6006 range_entries = range_len / sizeof (pcic_ranges_t); 6007 6008 /* for each "available" entry to be translated */ 6009 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 6010 int j; 6011 pcic_ranges_t *range_p = pcic_range_p; 6012 pci_p->pci_phys_hi = -1u; /* default invalid value */ 6013 6014 /* for each "ranges" entry to be searched */ 6015 for (j = 0; j < range_entries; j++, range_p++) { 6016 uint64_t range_end = range_p->pcic_range_caddrlo + 6017 range_p->pcic_range_size; 6018 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 6019 6020 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 6021 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 6022 (range_end < avail_end)) 6023 continue; 6024 6025 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 6026 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 6027 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 6028 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 6029 pci_p->pci_size_hi = 0; 6030 pci_p->pci_size_low = pcic_p->phys_len; 6031 } 6032 } 6033 kmem_free(pcic_range_p, range_len); 6034 return (DDI_SUCCESS); 6035 } 6036 6037 static int 6038 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 6039 { 6040 if (getminor(*dev) == SYSHW_MINOR) 6041 return (syshw_open(dev, flag, otyp, cred)); 6042 #ifdef CARDBUS 6043 if (cardbus_is_cb_minor(*dev)) 6044 return (cardbus_open(dev, flag, otyp, cred)); 6045 #endif 6046 return (EINVAL); 6047 } 6048 6049 static int 6050 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 6051 { 6052 if (getminor(dev) == SYSHW_MINOR) 6053 return (syshw_close(dev, flag, otyp, cred)); 6054 #ifdef CARDBUS 6055 if (cardbus_is_cb_minor(dev)) 6056 return (cardbus_close(dev, flag, otyp, cred)); 6057 #endif 6058 return (EINVAL); 6059 } 6060 6061 static int 6062 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 6063 int *rval) 6064 { 6065 if (getminor(dev) == SYSHW_MINOR) 6066 return (syshw_ioctl(dev, cmd, arg, mode, cred, rval)); 6067 #ifdef CARDBUS 6068 if (cardbus_is_cb_minor(dev)) 6069 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6070 #endif 6071 return (EINVAL); 6072 } 6073 6074 6075 static boolean_t 6076 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6077 { 6078 uint32_t present_state; 6079 dev_info_t *dip = pcic->dip; 6080 set_socket_t s; 6081 get_socket_t g; 6082 boolean_t retval; 6083 unsigned vccLevel; 6084 6085 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6086 6087 pcic_mutex_exit(&pcic->pc_lock); 6088 6089 bzero(&s, sizeof (set_socket_t)); 6090 s.socket = sockp->pcs_socket; 6091 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6092 s.IFType = IF_CARDBUS; 6093 s.State = (unsigned)~0; 6094 6095 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6096 if (present_state & PCIC_VCC_3VCARD) 6097 s.VccLevel = PCIC_VCC_3VLEVEL; 6098 else if (present_state & PCIC_VCC_5VCARD) 6099 s.VccLevel = PCIC_VCC_5VLEVEL; 6100 else { 6101 cmn_err(CE_CONT, 6102 "pcic_load_cardbus: unsupported card voltage\n"); 6103 goto failure; 6104 } 6105 vccLevel = s.VccLevel; 6106 s.Vpp1Level = s.Vpp2Level = 0; 6107 6108 if (pcic_set_socket(dip, &s) != SUCCESS) 6109 goto failure; 6110 6111 if (pcic_reset_socket(dip, sockp->pcs_socket, 6112 RESET_MODE_CARD_ONLY) != SUCCESS) 6113 goto failure; 6114 6115 bzero(&g, sizeof (get_socket_t)); 6116 g.socket = sockp->pcs_socket; 6117 if (pcic_get_socket(dip, &g) != SUCCESS) 6118 goto failure; 6119 6120 bzero(&s, sizeof (set_socket_t)); 6121 s.socket = sockp->pcs_socket; 6122 s.SCIntMask = SBM_CD; 6123 s.IREQRouting = g.IRQRouting; 6124 s.IFType = g.IFType; 6125 s.CtlInd = g.CtlInd; 6126 s.State = (unsigned)~0; 6127 s.VccLevel = vccLevel; 6128 s.Vpp1Level = s.Vpp2Level = 0; 6129 6130 if (pcic_set_socket(dip, &s) != SUCCESS) 6131 goto failure; 6132 6133 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6134 goto exit; 6135 6136 failure: 6137 retval = B_FALSE; 6138 6139 exit: 6140 pcic_mutex_enter(&pcic->pc_lock); 6141 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6142 retval ? "success" : "failure"); 6143 return (retval); 6144 } 6145 6146 static void 6147 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6148 { 6149 dev_info_t *dip = pcic->dip; 6150 set_socket_t s; 6151 6152 pcic_mutex_exit(&pcic->pc_lock); 6153 6154 cardbus_unload_cardbus(dip); 6155 6156 bzero(&s, sizeof (set_socket_t)); 6157 s.socket = sockp->pcs_socket; 6158 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6159 s.IREQRouting = 0; 6160 s.IFType = IF_MEMORY; 6161 s.CtlInd = 0; 6162 s.State = 0; 6163 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6164 6165 (void) pcic_set_socket(dip, &s); 6166 6167 pcic_mutex_enter(&pcic->pc_lock); 6168 } 6169 6170 static uint32_t 6171 pcic_getcb(pcicdev_t *pcic, int reg) 6172 { 6173 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6174 6175 return (ddi_get32(pcic->handle, 6176 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6177 } 6178 6179 static void 6180 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6181 { 6182 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6183 6184 ddi_put32(pcic->handle, 6185 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6186 } 6187 6188 static void 6189 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6190 { 6191 uint8_t value; 6192 uint16_t brdgctl; 6193 6194 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6195 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6196 6197 switch (pcic->pc_type) { 6198 case PCIC_INTEL_i82092: 6199 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6200 PCIC_82092_INT_ENABLE); 6201 break; 6202 case PCIC_O2_OZ6912: 6203 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6204 value |= 0x8; 6205 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6206 break; 6207 case PCIC_CL_PD6832: 6208 case PCIC_TI_PCI1250: 6209 case PCIC_TI_PCI1221: 6210 case PCIC_TI_PCI1225: 6211 case PCIC_TI_PCI1410: 6212 case PCIC_ENE_1410: 6213 case PCIC_TI_PCI1510: 6214 case PCIC_TI_PCI1520: 6215 case PCIC_TI_PCI1420: 6216 case PCIC_ENE_1420: 6217 /* route card functional interrupts to PCI interrupts */ 6218 brdgctl = ddi_get16(pcic->cfg_handle, 6219 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6220 pcic_err(NULL, 1, 6221 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6222 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6223 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6224 ddi_put16(pcic->cfg_handle, 6225 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6226 brdgctl); 6227 /* Flush the write */ 6228 (void) ddi_get16(pcic->cfg_handle, 6229 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6230 break; 6231 default: 6232 break; 6233 } 6234 } 6235 6236 static void 6237 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6238 { 6239 uint8_t value; 6240 uint16_t brdgctl; 6241 6242 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6243 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6244 6245 switch (pcic->pc_type) { 6246 case PCIC_INTEL_i82092: 6247 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6248 PCIC_82092_INT_DISABLE); 6249 break; 6250 case PCIC_O2_OZ6912: 6251 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6252 value &= ~0x8; 6253 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6254 /* Flush the write */ 6255 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6256 break; 6257 case PCIC_CL_PD6832: 6258 case PCIC_TI_PCI1250: 6259 case PCIC_TI_PCI1221: 6260 case PCIC_TI_PCI1225: 6261 case PCIC_TI_PCI1410: 6262 case PCIC_ENE_1410: 6263 case PCIC_TI_PCI1510: 6264 case PCIC_TI_PCI1520: 6265 case PCIC_TI_PCI1420: 6266 case PCIC_ENE_1420: 6267 /* 6268 * This maps I/O interrupts to ExCA which 6269 * have been turned off by the write to 6270 * PCIC_INTERRUPT above. It would appear to 6271 * be the only way to actually turn I/O Ints off 6272 * while retaining CS Ints. 6273 */ 6274 brdgctl = ddi_get16(pcic->cfg_handle, 6275 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6276 pcic_err(NULL, 1, 6277 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6278 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6279 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6280 ddi_put16(pcic->cfg_handle, 6281 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6282 brdgctl); 6283 /* Flush the write */ 6284 (void) ddi_get16(pcic->cfg_handle, 6285 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6286 break; 6287 default: 6288 break; 6289 } 6290 } 6291 6292 static void 6293 pcic_cb_enable_intr(dev_info_t *dip) 6294 { 6295 anp_t *anp = ddi_get_driver_private(dip); 6296 pcicdev_t *pcic = anp->an_private; 6297 6298 mutex_enter(&pcic->pc_lock); 6299 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6300 mutex_exit(&pcic->pc_lock); 6301 } 6302 6303 static void 6304 pcic_cb_disable_intr(dev_info_t *dip) 6305 { 6306 anp_t *anp = ddi_get_driver_private(dip); 6307 pcicdev_t *pcic = anp->an_private; 6308 6309 mutex_enter(&pcic->pc_lock); 6310 pcic_disable_io_intr(pcic, 0); 6311 mutex_exit(&pcic->pc_lock); 6312 } 6313 6314 static int 6315 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6316 { 6317 int nerr = 0; 6318 if (e & PCI_STAT_PERROR) { 6319 nerr++; 6320 cmn_err(CE_CONT, "detected parity error.\n"); 6321 } 6322 if (e & PCI_STAT_S_SYSERR) { 6323 nerr++; 6324 if (bridge_secondary) 6325 cmn_err(CE_CONT, "received system error.\n"); 6326 else 6327 cmn_err(CE_CONT, "signalled system error.\n"); 6328 } 6329 if (e & PCI_STAT_R_MAST_AB) { 6330 nerr++; 6331 cmn_err(CE_CONT, "received master abort.\n"); 6332 } 6333 if (e & PCI_STAT_R_TARG_AB) 6334 cmn_err(CE_CONT, "received target abort.\n"); 6335 if (e & PCI_STAT_S_TARG_AB) 6336 cmn_err(CE_CONT, "signalled target abort\n"); 6337 if (e & PCI_STAT_S_PERROR) { 6338 nerr++; 6339 cmn_err(CE_CONT, "signalled parity error\n"); 6340 } 6341 return (nerr); 6342 } 6343 6344 #if defined(__sparc) 6345 static int 6346 pcic_fault(enum pci_fault_ops op, void *arg) 6347 { 6348 pcicdev_t *pcic = (pcicdev_t *)arg; 6349 ushort_t pci_cfg_stat = 6350 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6351 ushort_t pci_cfg_sec_stat = 6352 pci_config_get16(pcic->cfg_handle, 0x16); 6353 char nm[24]; 6354 int nerr = 0; 6355 6356 cardbus_dump_pci_config(pcic->dip); 6357 6358 switch (op) { 6359 case FAULT_LOG: 6360 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6361 ddi_get_instance(pcic->dip)); 6362 6363 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6364 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6365 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6366 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6367 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6368 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6369 return (nerr); 6370 case FAULT_POKEFINI: 6371 case FAULT_RESET: 6372 pci_config_put16(pcic->cfg_handle, 6373 PCI_CONF_STAT, pci_cfg_stat); 6374 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6375 break; 6376 case FAULT_POKEFLT: 6377 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6378 return (1); 6379 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6380 return (1); 6381 break; 6382 default: 6383 break; 6384 } 6385 return (DDI_SUCCESS); 6386 } 6387 #endif 6388 6389 static void 6390 pcic_delayed_resume(void *arg) 6391 { 6392 int i, j, interrupt; 6393 anp_t *pcic_nexus; 6394 pcicdev_t *pcic; 6395 6396 _NOTE(ARGUNUSED(arg)) 6397 6398 #if defined(PCIC_DEBUG) 6399 pcic_err(NULL, 6, "pcic_delayed_resume(): entered\n"); 6400 #endif 6401 for (j = 0; j <= pcic_maxinst; j++) { 6402 6403 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, j); 6404 if (!pcic_nexus) 6405 continue; 6406 pcic = (pcicdev_t *)pcic_nexus->an_private; 6407 if (!pcic) 6408 continue; 6409 6410 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6411 for (i = 0; i < pcic->pc_numsockets; i++) { 6412 /* Enable interrupts on PCI if needs be */ 6413 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6414 if (pcic->pc_flags & PCF_USE_SMI) 6415 interrupt |= PCIC_INTR_ENABLE; 6416 pcic_putb(pcic, i, PCIC_INTERRUPT, 6417 PCIC_RESET | interrupt); 6418 pcic->pc_sockets[i].pcs_debounce_id = 6419 pcic_add_debqueue(&pcic->pc_sockets[i], 6420 drv_usectohz(pcic_debounce_time)); 6421 } 6422 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6423 if (pcic_do_pcmcia_sr) 6424 (void) pcmcia_wait_insert(pcic->dip); 6425 } 6426 } 6427 6428 static void 6429 pcic_debounce(pcic_socket_t *pcs) 6430 { 6431 uint8_t status, stschng; 6432 6433 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6434 pcs->pcs_flags &= ~PCS_STARTING; 6435 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6436 PCIC_CARD_STATUS_CHANGE); 6437 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6438 PCIC_INTERFACE_STATUS); 6439 #ifdef PCIC_DEBUG 6440 pcic_err(pcs->pcs_pcic->dip, 8, 6441 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6442 "chg 0x%x flg 0x%x\n", 6443 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6444 status, stschng, pcs->pcs_flags); 6445 #endif 6446 6447 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6448 PCIC_CD_DETECT); 6449 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6450 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6451 } 6452 6453 static void 6454 pcic_deb_thread() 6455 { 6456 callb_cpr_t cprinfo; 6457 struct debounce *debp; 6458 clock_t lastt; 6459 6460 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6461 callb_generic_cpr, "pcic debounce thread"); 6462 mutex_enter(&pcic_deb_mtx); 6463 while (pcic_deb_threadid) { 6464 while (pcic_deb_queue) { 6465 #ifdef PCIC_DEBUG 6466 pcic_dump_debqueue("Thread"); 6467 #endif 6468 debp = pcic_deb_queue; 6469 (void) drv_getparm(LBOLT, &lastt); 6470 if (lastt >= debp->expire) { 6471 pcic_deb_queue = debp->next; 6472 mutex_exit(&pcic_deb_mtx); 6473 pcic_debounce(debp->pcs); 6474 mutex_enter(&pcic_deb_mtx); 6475 kmem_free(debp, sizeof (*debp)); 6476 } else { 6477 (void) cv_timedwait(&pcic_deb_cv, 6478 &pcic_deb_mtx, debp->expire); 6479 } 6480 } 6481 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6482 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6483 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6484 } 6485 pcic_deb_threadid = (kthread_t *)1; 6486 cv_signal(&pcic_deb_cv); 6487 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6488 thread_exit(); 6489 } 6490 6491 static void * 6492 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6493 { 6494 clock_t lbolt; 6495 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6496 6497 (void) drv_getparm(LBOLT, &lbolt); 6498 dbp = kmem_alloc(sizeof (struct debounce), KM_SLEEP); 6499 6500 dbp->expire = lbolt + clocks; 6501 dbp->pcs = pcs; 6502 mutex_enter(&pcic_deb_mtx); 6503 while (*dbpp) { 6504 if (dbp->expire > (*dbpp)->expire) 6505 dbpp = &((*dbpp)->next); 6506 else 6507 break; 6508 } 6509 dbp->next = *dbpp; 6510 *dbpp = dbp; 6511 #ifdef PCIC_DEBUG 6512 pcic_dump_debqueue("Add"); 6513 #endif 6514 cv_signal(&pcic_deb_cv); 6515 mutex_exit(&pcic_deb_mtx); 6516 return (dbp); 6517 } 6518 6519 static void 6520 pcic_rm_debqueue(void *id) 6521 { 6522 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6523 6524 dbp = (struct debounce *)id; 6525 mutex_enter(&pcic_deb_mtx); 6526 while (*dbpp) { 6527 if (*dbpp == dbp) { 6528 *dbpp = dbp->next; 6529 kmem_free(dbp, sizeof (*dbp)); 6530 #ifdef PCIC_DEBUG 6531 pcic_dump_debqueue("Remove"); 6532 #endif 6533 cv_signal(&pcic_deb_cv); 6534 mutex_exit(&pcic_deb_mtx); 6535 return; 6536 } 6537 dbpp = &((*dbpp)->next); 6538 } 6539 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6540 mutex_exit(&pcic_deb_mtx); 6541 } 6542 6543 6544 static int pcic_powerdelay = 0; 6545 6546 static int 6547 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6548 { 6549 int ind, value, orig_pwrctl; 6550 6551 /* power setup -- if necessary */ 6552 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6553 6554 #if defined(PCIC_DEBUG) 6555 pcic_err(pcic->dip, 6, 6556 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6557 socket, powerlevel, orig_pwrctl); 6558 #endif 6559 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6560 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6561 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6562 if (powerlevel != orig_pwrctl) { 6563 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6564 int ifs; 6565 /* 6566 * set power to socket 6567 * note that the powerlevel was calculated earlier 6568 */ 6569 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6570 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6571 6572 /* 6573 * this second write to the power control register 6574 * is needed to resolve a problem on 6575 * the IBM ThinkPad 750 6576 * where the first write doesn't latch. 6577 * The second write appears to always work and 6578 * doesn't hurt the operation of other chips 6579 * so we can just use it -- this is good since we can't 6580 * determine what chip the 750 actually uses 6581 * (I suspect an early Ricoh). 6582 */ 6583 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6584 6585 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6586 pcic_mswait(pcic, socket, pcic_powerdelay); 6587 #if defined(PCIC_DEBUG) 6588 pcic_err(pcic->dip, 8, 6589 "\tpowerlevel reg = %x (ifs %x)\n", 6590 value, pcic_getb(pcic, socket, 6591 PCIC_INTERFACE_STATUS)); 6592 pcic_err(pcic->dip, 8, 6593 "CBus regs: PS 0x%x, Control 0x%x\n", 6594 pcic_getcb(pcic, CB_PRESENT_STATE), 6595 pcic_getcb(pcic, CB_CONTROL)); 6596 #endif 6597 /* 6598 * since power was touched, make sure it says it 6599 * is on. This lets it become stable. 6600 */ 6601 for (ind = 0; ind < 20; ind++) { 6602 ifs = pcic_getb(pcic, socket, 6603 PCIC_INTERFACE_STATUS); 6604 if (ifs & PCIC_POWER_ON) 6605 break; 6606 else { 6607 pcic_putb(pcic, socket, 6608 PCIC_POWER_CONTROL, 0); 6609 (void) pcic_getb(pcic, socket, 6610 PCIC_POWER_CONTROL); 6611 pcic_mswait(pcic, socket, 40); 6612 if (ind == 10) { 6613 pcic_putcb(pcic, CB_EVENT_FORCE, 6614 CB_EF_CVTEST); 6615 pcic_mswait(pcic, socket, 100); 6616 } 6617 pcic_putb(pcic, socket, 6618 PCIC_POWER_CONTROL, 6619 powerlevel & ~POWER_OUTPUT_ENABLE); 6620 (void) pcic_getb(pcic, socket, 6621 PCIC_POWER_CONTROL); 6622 pcic_mswait(pcic, socket, 6623 pcic_powerdelay); 6624 pcic_putb(pcic, socket, 6625 PCIC_POWER_CONTROL, powerlevel); 6626 (void) pcic_getb(pcic, socket, 6627 PCIC_POWER_CONTROL); 6628 pcic_mswait(pcic, socket, 6629 pcic_powerdelay); 6630 } 6631 } 6632 6633 if (!(ifs & PCIC_POWER_ON)) { 6634 cmn_err(CE_WARN, 6635 "pcic socket %d: Power didn't get turned" 6636 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6637 "misc1 0x%x igc 0x%x ind %d\n", 6638 socket, ifs, 6639 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6640 orig_pwrctl, 6641 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6642 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6643 ind); 6644 return (BAD_VCC); 6645 } 6646 #if defined(PCIC_DEBUG) 6647 pcic_err(pcic->dip, 8, 6648 "\tind = %d, if status %x pwrc 0x%x " 6649 "misc1 0x%x igc 0x%x\n", 6650 ind, ifs, 6651 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6652 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6653 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6654 #endif 6655 } else { 6656 /* explicitly turned off the power */ 6657 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6658 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6659 } 6660 } 6661 return (SUCCESS); 6662 } 6663 6664 static int pcic_cbdoreset_during_poweron = 1; 6665 static int 6666 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6667 { 6668 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6669 int ind, iobits; 6670 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6671 6672 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6673 6674 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6675 cbctl |= pcic_cbv_levels[ind]; 6676 6677 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6678 cbctl |= (pcic_cbv_levels[ind]<<4); 6679 6680 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6681 6682 #if defined(PCIC_DEBUG) 6683 pcic_err(pcic->dip, 6, 6684 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6685 "cbctl 0x%x->0x%x\n", 6686 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6687 #endif 6688 if (cbctl != orig_cbctl) { 6689 if (pcic_cbdoreset_during_poweron && 6690 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6691 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6692 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits & ~PCIC_RESET); 6693 } 6694 pcic_putcb(pcic, CB_CONTROL, cbctl); 6695 6696 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6697 pcic_mswait(pcic, socket, pcic_powerdelay); 6698 return (SUCCESS); 6699 } 6700 for (ind = 0; ind < 20; ind++) { 6701 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6702 6703 if (cbstev & CB_SE_POWER_CYCLE) { 6704 6705 /* 6706 * delay 400 ms: though the standard defines that the Vcc 6707 * set-up time is 20 ms, some PC-Card bridge requires longer 6708 * duration. 6709 * Note: We should check the status AFTER the delay to give time 6710 * for things to stabilize. 6711 */ 6712 pcic_mswait(pcic, socket, 400); 6713 6714 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6715 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6716 /* break; */ 6717 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6718 } 6719 if (cbctl & CB_PS_BADVCC) { 6720 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6721 break; 6722 } 6723 6724 #if defined(PCIC_DEBUG) 6725 pcic_err(pcic->dip, 8, 6726 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6727 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6728 cbctl, orig_cbctl); 6729 #endif 6730 if (pcic_cbdoreset_during_poweron && 6731 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6732 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6733 } 6734 return (SUCCESS); 6735 } 6736 pcic_mswait(pcic, socket, 40); 6737 } 6738 if (pcic_cbdoreset_during_poweron && 6739 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6740 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6741 } 6742 cmn_err(CE_WARN, 6743 "pcic socket %d: Power didn't get turned on/off!\n" 6744 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6745 "vcc %d vpp1 %d", socket, cbstev, 6746 pcic_getcb(pcic, CB_PRESENT_STATE), 6747 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6748 return (BAD_VCC); 6749 } 6750 return (SUCCESS); 6751 } 6752 6753 static int pcic_do_pprintf = 0; 6754 6755 static void 6756 pcic_dump_debqueue(char *msg) 6757 { 6758 struct debounce *debp = pcic_deb_queue; 6759 clock_t lbolt; 6760 6761 (void) drv_getparm(LBOLT, &lbolt); 6762 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6763 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6764 while (debp) { 6765 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6766 (void *) debp, (int)debp->expire, (void *) debp->next, 6767 debp->pcs->pcs_debounce_id); 6768 debp = debp->next; 6769 } 6770 } 6771 6772 6773 /* PRINTFLIKE3 */ 6774 static void 6775 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6776 { 6777 if (pcic_debug && (level <= pcic_debug)) { 6778 va_list adx; 6779 int instance; 6780 char buf[256]; 6781 const char *name; 6782 #if !defined(PCIC_DEBUG) 6783 int ce; 6784 char qmark = 0; 6785 6786 if (level <= 3) 6787 ce = CE_WARN; 6788 else 6789 ce = CE_CONT; 6790 if (level == 4) 6791 qmark = 1; 6792 #endif 6793 6794 if (dip) { 6795 instance = ddi_get_instance(dip); 6796 /* name = ddi_binding_name(dip); */ 6797 name = ddi_driver_name(dip); 6798 } else { 6799 instance = 0; 6800 name = ""; 6801 } 6802 6803 va_start(adx, fmt); 6804 (void) vsprintf(buf, fmt, adx); 6805 va_end(adx); 6806 6807 #if defined(PCIC_DEBUG) 6808 if (pcic_do_pprintf) { 6809 if (dip) { 6810 if (instance >= 0) 6811 prom_printf("%s(%d),0x%p: %s", name, 6812 instance, dip, buf); 6813 else 6814 prom_printf("%s,0x%p: %s", 6815 name, dip, buf); 6816 } else 6817 prom_printf(buf); 6818 } else { 6819 if (dip) { 6820 if (instance >= 0) 6821 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6822 name, instance, (void *) dip, buf); 6823 else 6824 cmn_err(CE_CONT, "%s,0x%p: %s", 6825 name, (void *) dip, buf); 6826 } else 6827 cmn_err(CE_CONT, buf); 6828 } 6829 #else 6830 if (dip) 6831 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6832 instance, buf); 6833 else 6834 cmn_err(ce, qmark ? "?%s" : buf, buf); 6835 #endif 6836 } 6837 } 6838 6839 6840 static void 6841 pcic_syshw_cardstate(syshw_t *item, void *arg) 6842 { 6843 pcic_socket_t *pcs = (pcic_socket_t *)arg; 6844 6845 if (pcs->pcs_flags & PCS_CARD_PRESENT) { 6846 item->state = B_TRUE; 6847 if (pcs->pcs_flags & PCS_CARD_IS16BIT) 6848 item->values[0] = 1; 6849 else if (pcs->pcs_flags & PCS_CARD_ISCARDBUS) 6850 item->values[0] = 2; 6851 else 6852 item->values[0] = 0; 6853 } else { 6854 item->state = B_FALSE; 6855 item->values[0] = 0; 6856 } 6857 } 6858 6859 /* 6860 * Tadpole additional for the syshw interface used to control the 6861 * start/stop switch which is physically linked to the GPIO1 pin 6862 * on the 1250a. 6863 */ 6864 6865 #define CLIENT_CALLED 0x8000000 6866 #define NCE_EVENT_MASK 0xffff 6867 6868 typedef struct _client { 6869 pid_t pid; /* set by kernel */ 6870 int flags; /* NCE_REGISTER... */ 6871 int priority; /* >100 unless root */ 6872 int events; /* pending event flags */ 6873 int event_sig; /* SIG... etc */ 6874 struct _client *next; /* set by kernel */ 6875 struct _client *prev; /* set by kernel */ 6876 } client_data; 6877 6878 static client_data *cl_data; 6879 static int n_clients; 6880 static kmutex_t client_mtx, intr_mtx; 6881 6882 static void delete_client(int); 6883 6884 #ifdef VOYAGER 6885 static uint32_t runstop_sig; 6886 static ddi_softintr_t softint_id; 6887 static uchar_t softint_flag; 6888 static int switch_debounce_time = 100; /* in milliseconds */ 6889 static timeout_id_t switch_to_id; 6890 6891 static syshw_t syshw_run_stop = { 6892 0, "Run/Stop", SH_SWITCH, 6893 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID, 6894 B_FALSE, { 0 } }; 6895 6896 static void 6897 syshw_get_run_stop(syshw_t *item, void *arg) 6898 { 6899 pcicdev_t *pcic = (pcicdev_t *)arg; 6900 6901 if (ddi_get8(pcic->cfg_handle, 6902 pcic->cfgaddr + PCIC_GPIO1_REG) & PCIC_GPIO_DIN) 6903 item->state = B_TRUE; 6904 else 6905 item->state = B_FALSE; 6906 } 6907 6908 6909 #endif 6910 6911 static void 6912 syshw_attach(pcicdev_t *pcic) 6913 { 6914 if (ddi_get_instance(pcic->dip) != 0) 6915 return; 6916 6917 #ifdef VOYAGER 6918 if (pcic->pc_type == PCIC_TI_PCI1250) { 6919 6920 /* 6921 * Only setup run/stop on a Voyager. 6922 * This is currently defined as 6923 * a TI1250 on a SPARC architecture. May have to make this a 6924 * property definition in the future. 6925 */ 6926 if (ddi_add_softintr(pcic->dip, 6927 DDI_SOFTINT_LOW, &softint_id, 6928 NULL, NULL, syshw_intr, 6929 (caddr_t)pcic) == DDI_SUCCESS) { 6930 runstop_sig = syshw_add2map(&syshw_run_stop, 6931 syshw_get_run_stop, pcic); 6932 mutex_init(&intr_mtx, NULL, MUTEX_DRIVER, 6933 pcic->pc_pri); 6934 ddi_put8(pcic->cfg_handle, 6935 pcic->cfgaddr + PCIC_GPIO1_REG, 6936 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | 6937 PCIC_GPIO_DELTA); 6938 } 6939 } 6940 #endif 6941 mutex_init(&client_mtx, "syshw client", MUTEX_DRIVER, NULL); 6942 (void) ddi_create_minor_node(pcic->dip, "syshw", S_IFCHR, 6943 SYSHW_MINOR, NULL, NULL); 6944 } 6945 6946 static void 6947 syshw_detach(pcicdev_t *pcic) 6948 { 6949 #ifdef VOYAGER 6950 if (pcic->pc_type == PCIC_TI_PCI1250) { 6951 pcic_mutex_enter(&intr_mtx); 6952 6953 /* 6954 * Turn off this interrupt. 6955 */ 6956 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6957 PCIC_GPIO_FINPUT); 6958 6959 if (switch_to_id) 6960 (void) untimeout(switch_to_id); 6961 switch_to_id = 0; 6962 softint_flag = 0; 6963 6964 pcic_mutex_exit(&intr_mtx); 6965 ddi_remove_softintr(softint_id); 6966 mutex_destroy(&intr_mtx); 6967 } 6968 #endif 6969 6970 ddi_remove_minor_node(pcic->dip, NULL); 6971 mutex_destroy(&client_mtx); 6972 } 6973 6974 static void 6975 syshw_resume(pcicdev_t *pcic) 6976 { 6977 #ifdef VOYAGER 6978 if (pcic->pc_type == PCIC_TI_PCI1250) { 6979 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6980 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | PCIC_GPIO_DELTA); 6981 } 6982 #else 6983 _NOTE(ARGUNUSED(pcic)) 6984 #endif 6985 } 6986 6987 #ifdef VOYAGER 6988 static uint_t 6989 syshw_intr_hi(pcicdev_t *pcic) 6990 { 6991 uchar_t regval; 6992 6993 if (pcic->pc_type != PCIC_TI_PCI1250) 6994 return (DDI_INTR_UNCLAIMED); 6995 6996 regval = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG); 6997 if (regval & PCIC_GPIO_DELTA) { 6998 pcic_mutex_enter(&intr_mtx); 6999 if (softint_flag == 0 && switch_to_id == 0) { 7000 softint_flag = 1; 7001 ddi_trigger_softintr(softint_id); 7002 } 7003 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 7004 regval); 7005 pcic_mutex_exit(&intr_mtx); 7006 return (DDI_INTR_CLAIMED); 7007 } 7008 7009 return (DDI_INTR_UNCLAIMED); 7010 } 7011 7012 /* 7013 * Don't deliver the signal until the debounce period has expired. 7014 * Unfortuately this means it end up as a three tier interrupt just 7015 * to indicate a bit change. 7016 */ 7017 static void 7018 syshw_debounce_to(void *arg) 7019 { 7020 _NOTE(ARGUNUSED(arg)) 7021 7022 if (switch_to_id) { 7023 pcic_mutex_enter(&intr_mtx); 7024 switch_to_id = 0; 7025 pcic_mutex_exit(&intr_mtx); 7026 syshw_send_signal(runstop_sig); 7027 return; 7028 } 7029 } 7030 7031 static uint_t 7032 syshw_intr(caddr_t arg) 7033 { 7034 _NOTE(ARGUNUSED(arg)) 7035 7036 if (softint_flag) { 7037 pcic_mutex_enter(&intr_mtx); 7038 softint_flag = 0; 7039 if (!switch_to_id) 7040 switch_to_id = timeout(syshw_debounce_to, arg, 7041 drv_usectohz(switch_debounce_time * 1000)); 7042 pcic_mutex_exit(&intr_mtx); 7043 return (DDI_INTR_CLAIMED); 7044 } 7045 return (DDI_INTR_UNCLAIMED); 7046 } 7047 #endif 7048 7049 /* 7050 * Send signals to the registered clients 7051 */ 7052 static void 7053 syshw_send_signal(int events) 7054 { 7055 client_data *ptr; 7056 proc_t *pr; 7057 int done_flag; 7058 7059 ptr = cl_data; 7060 while (ptr != NULL) { 7061 done_flag = CLIENT_CALLED; 7062 7063 if ((ptr->flags & events) && 7064 (ptr->event_sig != 0) && 7065 ((ptr->flags & done_flag) == 0)) { 7066 7067 /* 7068 * only call the process if: 7069 * it has not already received the nce signal 7070 * its signal was not zero (just in case) 7071 * and it is registered to receive this signal 7072 */ 7073 pcic_mutex_enter(&pidlock); 7074 pr = prfind(ptr->pid); 7075 pcic_mutex_exit(&pidlock); 7076 if (pr == NULL) { 7077 /* 7078 * This process has died, 7079 * so we free its memory and move on 7080 * start at the begining again: 7081 * a waste of cycles but it makes things easy.. 7082 */ 7083 delete_client(ptr->pid); 7084 ptr = cl_data; 7085 } else { 7086 ptr->events |= (events & ptr->flags & 7087 NCE_EVENT_MASK); 7088 psignal(pr, ptr->event_sig); 7089 ptr->flags |= done_flag; 7090 ptr = ptr->next; 7091 } 7092 } else { 7093 ptr = ptr->next; 7094 } 7095 } 7096 7097 ptr = cl_data; 7098 while (ptr != NULL) { 7099 ptr->flags &= ~done_flag; 7100 ptr = ptr->next; 7101 } 7102 } 7103 7104 static int 7105 syshw_open(dev_t *dev, int flag, int otyp, cred_t *cred) 7106 { 7107 _NOTE(ARGUNUSED(dev, flag, cred)) 7108 7109 if (otyp != OTYP_CHR) 7110 return (EINVAL); 7111 7112 return (0); 7113 } 7114 7115 static int 7116 syshw_close(dev_t dev, int flag, int otyp, cred_t *cred) 7117 { 7118 _NOTE(ARGUNUSED(dev, flag, otyp, cred)) 7119 7120 return (0); 7121 } 7122 7123 /* 7124 * Add a client to the list of interested processes 7125 */ 7126 static void 7127 add_client(client_data *new) 7128 { 7129 client_data * ptr; 7130 7131 n_clients++; 7132 if (cl_data == NULL) { 7133 cl_data = new; 7134 return; 7135 } 7136 7137 ptr = cl_data; 7138 while ((ptr->next != NULL) && (ptr->priority <= new->priority)) 7139 ptr = ptr->next; 7140 7141 if (ptr == cl_data) { 7142 /* at head of the list */ 7143 cl_data = new; 7144 new->next = ptr; 7145 new->prev = NULL; 7146 if (ptr != NULL) 7147 ptr->prev = new; 7148 } else { 7149 /* somewhere else in the list - insert after */ 7150 new->next = ptr->next; 7151 ptr->next = new; 7152 new->prev = ptr; 7153 if (new->next != NULL) 7154 (new->next)->prev = new; 7155 } 7156 } 7157 7158 /* 7159 * Locate a client data structure in the client list by looking for a PID match. 7160 */ 7161 static client_data * 7162 locate_client(pid_t pid) 7163 { 7164 client_data * ptr = cl_data; 7165 7166 while ((ptr != NULL) && (ptr->pid != pid)) 7167 ptr = ptr->next; 7168 7169 return (ptr); 7170 } 7171 7172 /* 7173 * Remove a client record from the client list 7174 */ 7175 static void 7176 delete_client(pid_t pid) 7177 { 7178 client_data * ptr; 7179 7180 ptr = locate_client(pid); 7181 if (ptr == NULL) 7182 return; /* hmmm!! */ 7183 7184 n_clients--; 7185 7186 if (ptr == cl_data) { 7187 /* remove the head of the list */ 7188 cl_data = ptr->next; 7189 } 7190 if (ptr->prev != NULL) 7191 (ptr->prev)->next = ptr->next; 7192 if (ptr->next != NULL) 7193 (ptr->next)->prev = ptr->prev; 7194 7195 kmem_free(ptr, sizeof (client_data)); 7196 } 7197 7198 static void 7199 unregister_event_client() 7200 { 7201 pcic_mutex_enter(&client_mtx); 7202 delete_client(ddi_get_pid()); 7203 pcic_mutex_exit(&client_mtx); 7204 } 7205 7206 static int 7207 register_event_client(client_data *u_client) 7208 { 7209 int error; 7210 client_data * client; 7211 7212 pcic_mutex_enter(&client_mtx); 7213 client = locate_client(ddi_get_pid()); 7214 if (client) { 7215 /* 7216 * we are re-registering ourself 7217 * so we delete the previous entry 7218 */ 7219 delete_client(ddi_get_pid()); 7220 } 7221 7222 client = (client_data *)kmem_alloc(sizeof (client_data), KM_SLEEP); 7223 7224 if (client) { 7225 client->pid = ddi_get_pid(); 7226 client->priority = u_client->priority; 7227 client->flags = u_client->flags & NCE_EVENT_MASK; 7228 client->events = 0; 7229 client->event_sig = u_client->event_sig; 7230 client->next = NULL; 7231 client->prev = NULL; 7232 add_client(client); 7233 error = 0; 7234 } else 7235 error = EIO; 7236 7237 pcic_mutex_exit(&client_mtx); 7238 return (error); 7239 } 7240 7241 /* 7242 * Read the currently pending event flags for the process in question 7243 */ 7244 static int 7245 check_events_pending(caddr_t data) 7246 { 7247 client_data * client; 7248 int error = 0; 7249 7250 pcic_mutex_enter(&client_mtx); 7251 client = locate_client(ddi_get_pid()); 7252 if (client) { 7253 if (copyout((caddr_t)&client->events, data, sizeof (int))) 7254 error = EFAULT; 7255 else 7256 client->events = 0; 7257 } else 7258 error = EINVAL; 7259 7260 pcic_mutex_exit(&client_mtx); 7261 return (error); 7262 } 7263 7264 7265 #define MAXITEMS 8 7266 static syshw_t *syshw_map[MAXITEMS]; 7267 static void (*syshw_getfuncs[MAXITEMS])(syshw_t *, void *); 7268 static void *syshw_getfunc_args[MAXITEMS]; 7269 static int nsyshw_items = 0; 7270 #define NSYSHW_ITEMS nsyshw_items 7271 7272 static uint32_t 7273 syshw_add2map(syshw_t *item, void (*getfunc)(syshw_t *, void *), void *getarg) 7274 { 7275 uint32_t rval = (1 << nsyshw_items); 7276 if (nsyshw_items == MAXITEMS) 7277 return (0); 7278 item->hw_id = nsyshw_items; 7279 syshw_map[nsyshw_items] = item; 7280 syshw_getfuncs[nsyshw_items] = getfunc; 7281 syshw_getfunc_args[nsyshw_items] = getarg; 7282 nsyshw_items++; 7283 return (rval); 7284 } 7285 7286 static int 7287 syshw_ioctl(dev_t dev, int cmd, intptr_t ioctldata, int mode, 7288 cred_t *cred, int *rval) 7289 { 7290 caddr_t data = (caddr_t)ioctldata; 7291 syshw_t sh; 7292 hwev_t hwev; 7293 client_data dummy_client; 7294 int rc = 0, i; 7295 7296 _NOTE(ARGUNUSED(dev, mode, cred, rval)) 7297 7298 switch (cmd) { 7299 default: 7300 rc = EINVAL; 7301 break; 7302 7303 case SYSHW_GET_ITEM: 7304 case SYSHW_GET_ITEM_MAXVALUES: 7305 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7306 rc = EFAULT; 7307 break; 7308 } 7309 7310 if (sh.hw_id >= NSYSHW_ITEMS) { 7311 rc = EINVAL; 7312 break; 7313 } 7314 7315 sh = *syshw_map[sh.hw_id]; 7316 if (!sh.id_string[0]) { 7317 rc = ENOTTY; 7318 break; 7319 } 7320 if (cmd == SYSHW_GET_ITEM) { 7321 if (syshw_getfuncs[sh.hw_id]) 7322 syshw_getfuncs[sh.hw_id](&sh, 7323 syshw_getfunc_args[sh.hw_id]); 7324 else 7325 rc = ENOTTY; 7326 } 7327 7328 if (copyout((caddr_t)&sh, data, sizeof (sh))) { 7329 rc = EFAULT; 7330 break; 7331 } 7332 break; 7333 7334 case SYSHW_SET_ITEM: 7335 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7336 rc = EFAULT; 7337 break; 7338 } 7339 7340 if (sh.hw_id >= NSYSHW_ITEMS || 7341 !syshw_map[sh.hw_id]->id_string[0] || 7342 !(syshw_map[sh.hw_id]->capabilities & 7343 (SYSHW_STATE_MODIFY | SYSHW_VAL0_MODIFY | 7344 SYSHW_VAL1_MODIFY | SYSHW_VAL2_MODIFY | 7345 SYSHW_VAL3_MODIFY))) { 7346 rc = EINVAL; 7347 break; 7348 } 7349 7350 switch (sh.hw_id) { 7351 default: 7352 rc = EINVAL; 7353 break; 7354 } 7355 break; 7356 7357 case SYSHW_EVREG: 7358 if (copyin(data, (caddr_t)&hwev, sizeof (hwev))) { 7359 rc = EFAULT; 7360 break; 7361 } 7362 7363 for (i = 0; i < NSYSHW_ITEMS; i++) { 7364 if (hwev.events & (1 << i) && 7365 !(syshw_map[i]->capabilities & 7366 SYSHW_CAN_SIGNAL_CHANGE)) { 7367 rc = EINVAL; 7368 break; 7369 } 7370 } 7371 if (hwev.event_sig != SIGUSR1 && hwev.event_sig != SIGUSR2) 7372 rc = EINVAL; 7373 7374 if (!rc) { 7375 dummy_client.priority = 100; 7376 dummy_client.flags = hwev.events; 7377 dummy_client.event_sig = hwev.event_sig; 7378 rc = register_event_client(&dummy_client); 7379 } 7380 break; 7381 7382 case SYSHW_EVUNREG: 7383 unregister_event_client(); 7384 break; 7385 7386 case SYSHW_CHKEV: 7387 rc = check_events_pending(data); 7388 break; 7389 } 7390 return (rc); 7391 } 7392