1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCIC device/interrupt handler 31 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 32 * and Toshiba (and possibly other clones) PCMCIA adapter chip 33 * sets. It implements a subset of Socket Services as defined 34 * in the Solaris PCMCIA design documents 35 */ 36 37 /* 38 * currently defined "properties" 39 * 40 * clock-frequency bus clock frequency 41 * smi system management interrupt override 42 * need-mult-irq need status IRQ for each pair of sockets 43 * disable-audio don't route audio signal to speaker 44 */ 45 46 47 #include <sys/types.h> 48 #include <sys/inttypes.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/user.h> 52 #include <sys/buf.h> 53 #include <sys/file.h> 54 #include <sys/uio.h> 55 #include <sys/conf.h> 56 #include <sys/stat.h> 57 #include <sys/autoconf.h> 58 #include <sys/vtoc.h> 59 #include <sys/dkio.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/sunndi.h> 63 #include <sys/var.h> 64 #include <sys/callb.h> 65 #include <sys/open.h> 66 #include <sys/ddidmareq.h> 67 #include <sys/dma_engine.h> 68 #include <sys/kstat.h> 69 #include <sys/kmem.h> 70 #include <sys/modctl.h> 71 #include <sys/pci.h> 72 #include <sys/pci_impl.h> 73 74 #include <sys/pctypes.h> 75 #include <sys/pcmcia.h> 76 #include <sys/sservice.h> 77 78 #include <sys/note.h> 79 80 #include <sys/pcic_reg.h> 81 #include <sys/pcic_var.h> 82 83 #if defined(__sparc) 84 #include <sys/pci/pci_nexus.h> 85 #endif 86 87 #include <sys/hotplug/hpcsvc.h> 88 #include <sys/syshw.h> 89 #include "cardbus/cardbus.h" 90 91 #define SOFTC_SIZE (sizeof (anp_t)) 92 93 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 94 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 95 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 96 static uint_t pcic_intr(caddr_t, caddr_t); 97 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 98 static int pcic_probe(dev_info_t *); 99 100 static int pcic_open(dev_t *, int, int, cred_t *); 101 static int pcic_close(dev_t, int, int, cred_t *); 102 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 103 104 typedef struct pcm_regs pcm_regs_t; 105 106 static void pcic_init_assigned(dev_info_t *); 107 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 108 pci_regspec_t *, int); 109 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 110 111 /* 112 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 113 * are xlated into DMA ctlops. To make this nexus work on x86, we 114 * need to have the default ddi_dma_mctl ctlops in the bus_ops 115 * structure, just to pass the request to the parent. The correct 116 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 117 */ 118 static 119 struct bus_ops pcmciabus_ops = { 120 BUSO_REV, 121 pcmcia_bus_map, 122 NULL, 123 NULL, 124 NULL, 125 i_ddi_map_fault, 126 ddi_no_dma_map, 127 ddi_no_dma_allochdl, 128 ddi_no_dma_freehdl, 129 ddi_no_dma_bindhdl, 130 ddi_no_dma_unbindhdl, 131 ddi_no_dma_flush, 132 ddi_no_dma_win, 133 ddi_dma_mctl, 134 pcmcia_ctlops, 135 pcmcia_prop_op, 136 NULL, /* (*bus_get_eventcookie)(); */ 137 NULL, /* (*bus_add_eventcall)(); */ 138 NULL, /* (*bus_remove_eventcall)(); */ 139 NULL, /* (*bus_post_event)(); */ 140 NULL, /* (*bus_intr_ctl)(); */ 141 NULL, /* (*bus_config)(); */ 142 NULL, /* (*bus_unconfig)(); */ 143 NULL, /* (*bus_fm_init)(); */ 144 NULL, /* (*bus_fm_fini)(); */ 145 NULL, /* (*bus_enter)() */ 146 NULL, /* (*bus_exit)() */ 147 NULL, /* (*bus_power)() */ 148 pcmcia_intr_ops /* (*bus_intr_op)(); */ 149 }; 150 151 static struct cb_ops pcic_cbops = { 152 pcic_open, 153 pcic_close, 154 nodev, 155 nodev, 156 nodev, 157 nodev, 158 nodev, 159 pcic_ioctl, 160 nodev, 161 nodev, 162 nodev, 163 nochpoll, 164 ddi_prop_op, 165 NULL, 166 #ifdef CARDBUS 167 D_NEW | D_MP | D_HOTPLUG 168 #else 169 D_NEW | D_MP 170 #endif 171 }; 172 173 static struct dev_ops pcic_devops = { 174 DEVO_REV, 175 0, 176 pcic_getinfo, 177 nulldev, 178 pcic_probe, 179 pcic_attach, 180 pcic_detach, 181 nulldev, 182 &pcic_cbops, 183 &pcmciabus_ops, 184 NULL 185 }; 186 187 void *pcic_soft_state_p = NULL; 188 static int pcic_maxinst = -1; 189 static timeout_id_t pcic_delayed_resume_toid; 190 191 int pcic_do_insertion = 1; 192 int pcic_do_removal = 1; 193 194 struct irqmap { 195 int irq; 196 int count; 197 } pcic_irq_map[16]; 198 199 200 int pcic_debug = 0x0; 201 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 202 extern void cardbus_dump_pci_config(dev_info_t *dip); 203 extern void cardbus_dump_socket(dev_info_t *dip); 204 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 205 static void pcic_dump_debqueue(char *msg); 206 207 #if defined(PCIC_DEBUG) 208 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 209 210 #define pcic_mutex_enter(a) \ 211 { \ 212 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 213 mutex_enter(a); \ 214 }; 215 216 #define pcic_mutex_exit(a) \ 217 { \ 218 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 219 mutex_exit(a); \ 220 }; 221 222 #else 223 #define pcic_mutex_enter(a) mutex_enter(a) 224 #define pcic_mutex_exit(a) mutex_exit(a) 225 #endif 226 227 #define PCIC_VCC_3VLEVEL 1 228 #define PCIC_VCC_5VLEVEL 2 229 #define PCIC_VCC_12LEVEL 3 230 231 /* bit patterns to select voltage levels */ 232 int pcic_vpp_levels[13] = { 233 0, 0, 0, 234 1, /* 3.3V */ 235 0, 236 1, /* 5V */ 237 0, 0, 0, 0, 0, 0, 238 2 /* 12V */ 239 }; 240 241 uint8_t pcic_cbv_levels[13] = { 242 0, 0, 0, 243 3, /* 3.3V */ 244 0, 245 2, /* 5V */ 246 0, 0, 0, 0, 0, 0, 247 1 /* 12V */ 248 }; 249 250 struct power_entry pcic_power[4] = { 251 { 252 0, VCC|VPP1|VPP2 253 }, 254 { 255 33, /* 3.3Volt */ 256 VCC|VPP1|VPP2 257 }, 258 { 259 5*10, /* 5Volt */ 260 VCC|VPP1|VPP2 /* currently only know about this */ 261 }, 262 { 263 12*10, /* 12Volt */ 264 VPP1|VPP2 265 } 266 }; 267 268 /* 269 * Base used to allocate ranges of PCI memory on x86 systems 270 * Each instance gets a chunk above the base that is used to map 271 * in the memory and I/O windows for that device. 272 * Pages below the base are also allocated for the EXCA registers, 273 * one per instance. 274 */ 275 #define PCIC_PCI_MEMCHUNK 0x1000000 276 277 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 278 static int pcic_debounce_time = 200000; /* In micro-seconds */ 279 280 struct debounce { 281 pcic_socket_t *pcs; 282 clock_t expire; 283 struct debounce *next; 284 }; 285 286 static syshw_t pcic_syshw = { 287 0, "PC Card Socket 0", SH_CONNECTION, 288 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID|SYSHW_VAL0_VALID, 289 B_FALSE, {2, 0, 0, 0} 290 }; 291 292 static struct debounce *pcic_deb_queue = NULL; 293 static kmutex_t pcic_deb_mtx; 294 static kcondvar_t pcic_deb_cv; 295 static kthread_t *pcic_deb_threadid; 296 297 static inthandler_t *pcic_handlers; 298 299 static void pcic_setup_adapter(pcicdev_t *); 300 static int pcic_change(pcicdev_t *, int); 301 static int pcic_ll_reset(pcicdev_t *, int); 302 static void pcic_mswait(pcicdev_t *, int, int); 303 static boolean_t pcic_check_ready(pcicdev_t *, int); 304 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 305 static void pcic_ready_wait(pcicdev_t *, int); 306 extern int pcmcia_get_intr(dev_info_t *, int); 307 extern int pcmcia_return_intr(dev_info_t *, int); 308 309 static int pcic_callback(dev_info_t *, int (*)(), int); 310 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 311 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 312 static int pcic_get_page(dev_info_t *, get_page_t *); 313 static int pcic_get_socket(dev_info_t *, get_socket_t *); 314 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 315 static int pcic_get_window(dev_info_t *, get_window_t *); 316 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 317 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 318 static int pcic_reset_socket(dev_info_t *, int, int); 319 static int pcic_set_page(dev_info_t *, set_page_t *); 320 static int pcic_set_window(dev_info_t *, set_window_t *); 321 static int pcic_set_socket(dev_info_t *, set_socket_t *); 322 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 323 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 324 static void pcic_pm_detection(void *); 325 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 326 static int clext_reg_read(pcicdev_t *, int, uchar_t); 327 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 328 static int pcic_calc_speed(pcicdev_t *, uint32_t); 329 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 330 static int pcic_find_pci_type(pcicdev_t *); 331 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 332 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 333 static uint_t pcic_cd_softint(caddr_t, caddr_t); 334 static uint8_t pcic_getb(pcicdev_t *, int, int); 335 static void pcic_putb(pcicdev_t *, int, int, int8_t); 336 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 337 static uint_t pcic_softintr(caddr_t, caddr_t); 338 339 static void pcic_debounce(pcic_socket_t *); 340 static void pcic_delayed_resume(void *); 341 static void *pcic_add_debqueue(pcic_socket_t *, int); 342 static void pcic_rm_debqueue(void *); 343 static void pcic_deb_thread(); 344 345 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 346 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 347 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 348 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 349 static void pcic_cb_enable_intr(dev_info_t *); 350 static void pcic_cb_disable_intr(dev_info_t *); 351 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 352 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 353 354 static cb_nexus_cb_t pcic_cbnexus_ops = { 355 pcic_cb_enable_intr, 356 pcic_cb_disable_intr 357 }; 358 359 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 360 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 361 362 static void pcic_syshw_cardstate(syshw_t *, void *); 363 364 #if defined(__sparc) 365 static int pcic_fault(enum pci_fault_ops op, void *arg); 366 #endif 367 368 /* 369 * Default to support for Voyager IIi if sparc is defined. 370 * Appart from the PCI base addresses this only effect the TI1250. 371 */ 372 #if defined(sparc) 373 #define VOYAGER 374 #endif 375 376 377 /* 378 * pcmcia_attach() uses 0 and 128 upwards for the initpcmcia and devctl 379 * interfaces so we use 254. 380 */ 381 #define SYSHW_MINOR 254 382 383 /* 384 * Forward declarations for syshw interface (See end of file). 385 */ 386 static void syshw_attach(pcicdev_t *); 387 static void syshw_detach(pcicdev_t *); 388 static void syshw_resume(pcicdev_t *); 389 390 #ifdef VOYAGER 391 static uint_t syshw_intr(caddr_t); 392 static uint_t syshw_intr_hi(pcicdev_t *); 393 #endif 394 395 static int syshw_open(dev_t *, int, int, cred_t *); 396 static int syshw_close(dev_t, int, int, cred_t *); 397 static int syshw_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 398 static uint32_t syshw_add2map(syshw_t *, void (*)(syshw_t *, void *), void *); 399 static void syshw_send_signal(int); 400 401 /* 402 * pcmcia interface operations structure 403 * this is the private interface that is exported to the nexus 404 */ 405 pcmcia_if_t pcic_if_ops = { 406 PCIF_MAGIC, 407 PCIF_VERSION, 408 pcic_callback, 409 pcic_get_adapter, 410 pcic_get_page, 411 pcic_get_socket, 412 pcic_get_status, 413 pcic_get_window, 414 pcic_inquire_adapter, 415 pcic_inquire_socket, 416 pcic_inquire_window, 417 pcic_reset_socket, 418 pcic_set_page, 419 pcic_set_window, 420 pcic_set_socket, 421 pcic_set_interrupt, 422 pcic_clear_interrupt, 423 NULL, 424 }; 425 426 /* 427 * chip type identification routines 428 * this list of functions is searched until one of them succeeds 429 * or all fail. i82365SL is assumed if failed. 430 */ 431 static int pcic_ci_cirrus(pcicdev_t *); 432 static int pcic_ci_vadem(pcicdev_t *); 433 static int pcic_ci_ricoh(pcicdev_t *); 434 435 int (*pcic_ci_funcs[])(pcicdev_t *) = { 436 pcic_ci_cirrus, 437 pcic_ci_vadem, 438 pcic_ci_ricoh, 439 NULL 440 }; 441 442 static struct modldrv modldrv = { 443 &mod_driverops, /* Type of module. This one is a driver */ 444 "PCIC PCMCIA adapter driver %I%", /* Name of the module. */ 445 &pcic_devops, /* driver ops */ 446 }; 447 448 static struct modlinkage modlinkage = { 449 MODREV_1, (void *)&modldrv, NULL 450 }; 451 452 int 453 _init() 454 { 455 int stat; 456 457 /* Allocate soft state */ 458 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 459 SOFTC_SIZE, 2)) != DDI_SUCCESS) 460 return (stat); 461 462 if ((stat = mod_install(&modlinkage)) != 0) 463 ddi_soft_state_fini(&pcic_soft_state_p); 464 465 return (stat); 466 } 467 468 int 469 _fini() 470 { 471 int stat = 0; 472 473 if ((stat = mod_remove(&modlinkage)) != 0) 474 return (stat); 475 476 if (pcic_deb_threadid) { 477 mutex_enter(&pcic_deb_mtx); 478 pcic_deb_threadid = 0; 479 while (!pcic_deb_threadid) 480 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 481 pcic_deb_threadid = 0; 482 mutex_exit(&pcic_deb_mtx); 483 484 mutex_destroy(&pcic_deb_mtx); 485 cv_destroy(&pcic_deb_cv); 486 } 487 488 ddi_soft_state_fini(&pcic_soft_state_p); 489 490 return (stat); 491 } 492 493 int 494 _info(struct modinfo *modinfop) 495 { 496 return (mod_info(&modlinkage, modinfop)); 497 } 498 499 /* 500 * pcic_getinfo() 501 * provide instance/device information about driver 502 */ 503 /*ARGSUSED*/ 504 static int 505 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 506 { 507 anp_t *anp; 508 int error = DDI_SUCCESS; 509 minor_t minor; 510 511 switch (cmd) { 512 case DDI_INFO_DEVT2DEVINFO: 513 minor = getminor((dev_t)arg); 514 if (minor == SYSHW_MINOR) 515 minor = 0; 516 else 517 minor &= 0x7f; 518 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 519 *result = NULL; 520 else 521 *result = anp->an_dip; 522 break; 523 case DDI_INFO_DEVT2INSTANCE: 524 minor = getminor((dev_t)arg); 525 if (minor == SYSHW_MINOR) 526 minor = 0; 527 else 528 minor &= 0x7f; 529 *result = (void *)((long)minor); 530 break; 531 default: 532 error = DDI_FAILURE; 533 break; 534 } 535 return (error); 536 } 537 538 static int 539 pcic_probe(dev_info_t *dip) 540 { 541 int value; 542 ddi_device_acc_attr_t attr; 543 ddi_acc_handle_t handle; 544 uchar_t *index, *data; 545 546 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 547 return (DDI_PROBE_DONTCARE); 548 549 /* 550 * find a PCIC device (any vendor) 551 * while there can be up to 4 such devices in 552 * a system, we currently only look for 1 553 * per probe. There will be up to 2 chips per 554 * instance since they share I/O space 555 */ 556 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 557 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 558 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 559 560 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 561 (caddr_t *)&index, 562 PCIC_ISA_CONTROL_REG_OFFSET, 563 PCIC_ISA_CONTROL_REG_LENGTH, 564 &attr, &handle) != DDI_SUCCESS) 565 return (DDI_PROBE_FAILURE); 566 567 data = index + 1; 568 569 #if defined(PCIC_DEBUG) 570 if (pcic_debug) 571 cmn_err(CE_CONT, "pcic_probe: entered\n"); 572 if (pcic_debug) 573 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 574 #endif 575 ddi_put8(handle, index, PCIC_CHIP_REVISION); 576 ddi_put8(handle, data, 0); 577 value = ddi_get8(handle, data); 578 #if defined(PCIC_DEBUG) 579 if (pcic_debug) 580 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 581 #endif 582 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 583 (value & 0x30) == 0) { 584 /* 585 * we probably have a PCIC chip in the system 586 * do a little more checking. If we find one, 587 * reset everything in case of softboot 588 */ 589 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 590 ddi_put8(handle, data, 0); 591 value = ddi_get8(handle, data); 592 #if defined(PCIC_DEBUG) 593 if (pcic_debug) 594 cmn_err(CE_CONT, "\tzero test = %x\n", value); 595 #endif 596 /* should read back as zero */ 597 if (value == 0) { 598 /* 599 * we do have one and it is off the bus 600 */ 601 #if defined(PCIC_DEBUG) 602 if (pcic_debug) 603 cmn_err(CE_CONT, "pcic_probe: success\n"); 604 #endif 605 ddi_regs_map_free(&handle); 606 return (DDI_PROBE_SUCCESS); 607 } 608 } 609 #if defined(PCIC_DEBUG) 610 if (pcic_debug) 611 cmn_err(CE_CONT, "pcic_probe: failed\n"); 612 #endif 613 ddi_regs_map_free(&handle); 614 return (DDI_PROBE_FAILURE); 615 } 616 617 /* 618 * These are just defaults they can also be changed via a property in the 619 * conf file. 620 */ 621 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 622 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 623 static int pcic_do_pcmcia_sr = 0; 624 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 625 626 /* 627 * enable insertion/removal interrupt for 32bit cards 628 */ 629 static int 630 cardbus_enable_cd_intr(dev_info_t *dip) 631 { 632 ddi_acc_handle_t iohandle; 633 caddr_t ioaddr; 634 ddi_device_acc_attr_t attr; 635 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 636 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 637 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 638 (void) ddi_regs_map_setup(dip, 1, 639 (caddr_t *)&ioaddr, 640 0, 641 4096, 642 &attr, &iohandle); 643 644 /* CSC Interrupt: Card detect interrupt on */ 645 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 646 ddi_get32(iohandle, 647 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 648 649 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 650 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 651 652 ddi_regs_map_free(&iohandle); 653 return (1); 654 } 655 656 /* 657 * pcic_attach() 658 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 659 * to the system. This is a child of "sysbus" since that is where 660 * the hardware lives, but it provides services to the "pcmcia" 661 * nexus driver. It gives a pointer back via its private data 662 * structure which contains both the dip and socket services entry 663 * points 664 */ 665 static int 666 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 667 { 668 anp_t *pcic_nexus; 669 pcicdev_t *pcic; 670 int irqlevel, value; 671 int pci_cfrn, pci_ctrn; 672 int i, j, smi, actual; 673 char *typename; 674 char bus_type[16] = "(unknown)"; 675 int len = sizeof (bus_type); 676 ddi_device_acc_attr_t attr; 677 anp_t *anp = ddi_get_driver_private(dip); 678 uint_t pri; 679 syshw_t *shwp; 680 681 #if defined(PCIC_DEBUG) 682 if (pcic_debug) { 683 cmn_err(CE_CONT, "pcic_attach: entered\n"); 684 } 685 #endif 686 switch (cmd) { 687 case DDI_ATTACH: 688 break; 689 case DDI_RESUME: 690 pcic = anp->an_private; 691 /* 692 * for now, this is a simulated resume. 693 * a real one may need different things. 694 */ 695 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 696 mutex_enter(&pcic->pc_lock); 697 /* should probe for new sockets showing up */ 698 pcic_setup_adapter(pcic); 699 syshw_resume(pcic); 700 pcic->pc_flags &= ~PCF_SUSPENDED; 701 mutex_exit(&pcic->pc_lock); 702 (void) pcmcia_begin_resume(dip); 703 /* 704 * this will do the CARD_INSERTION 705 * due to needing time for threads to 706 * run, it must be delayed for a short amount 707 * of time. pcmcia_wait_insert checks for all 708 * children to be removed and then triggers insert. 709 */ 710 /* 711 * The reason for having a single timeout here 712 * rather than seperate timeout()s for each instance 713 * is due to the limited number (2) of callout threads 714 * available in Solaris 2.6. A single 1250A ends up 715 * as two instances of the interface with one slot each. 716 * The pcic_delayed_resume() function ends by calling 717 * pcmcia_wait_insert() which at one point does a 718 * delay(). delay() is implemented with a timeout() 719 * call so you end up with both the callout() 720 * threads waiting to be woken up by another callout(). 721 * This situation locks up the machine hence the 722 * convolution here to only use one timeout. 723 */ 724 if (!pcic_delayed_resume_toid) 725 pcic_delayed_resume_toid = 726 timeout(pcic_delayed_resume, (caddr_t)0, 727 drv_usectohz(pcic_wait_insert_time)); 728 729 /* 730 * for complete implementation need END_RESUME (later) 731 */ 732 return (DDI_SUCCESS); 733 734 } 735 return (DDI_SUCCESS); 736 default: 737 return (DDI_FAILURE); 738 } 739 740 /* 741 * Allocate soft state associated with this instance. 742 */ 743 if (ddi_soft_state_zalloc(pcic_soft_state_p, 744 ddi_get_instance(dip)) != DDI_SUCCESS) { 745 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 746 ddi_get_instance(dip)); 747 return (DDI_FAILURE); 748 } 749 750 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 751 ddi_get_instance(dip)); 752 753 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 754 755 pcic->dip = dip; 756 pcic_nexus->an_dip = dip; 757 pcic_nexus->an_if = &pcic_if_ops; 758 pcic_nexus->an_private = pcic; 759 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 760 pcic->pc_power = pcic_power; 761 762 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 763 "pci-control-reg-number", pci_control_reg_num); 764 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 765 "pci-config-reg-number", pci_config_reg_num); 766 767 ddi_set_driver_private(dip, pcic_nexus); 768 769 /* 770 * pcic->pc_irq is really the IPL level we want to run at 771 * set the default values here and override from intr spec 772 */ 773 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 774 "interrupt-priorities", -1); 775 776 if (pcic->pc_irq == -1) { 777 int actual; 778 uint_t pri; 779 ddi_intr_handle_t hdl; 780 781 /* see if intrspec tells us different */ 782 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 783 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 784 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 785 pcic->pc_irq = pri; 786 else 787 pcic->pc_irq = LOCK_LEVEL + 1; 788 (void) ddi_intr_free(hdl); 789 } 790 } 791 pcic_nexus->an_ipl = pcic->pc_irq; 792 793 /* 794 * Check our parent bus type. We do different things based on which 795 * bus we're on. 796 */ 797 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 798 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 799 "device_type", (caddr_t)&bus_type[0], &len) != 800 DDI_PROP_SUCCESS) { 801 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 802 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 803 "bus-type", (caddr_t)&bus_type[0], &len) != 804 DDI_PROP_SUCCESS) { 805 806 cmn_err(CE_CONT, 807 "pcic%d: can't find parent bus type\n", 808 ddi_get_instance(dip)); 809 810 kmem_free(pcic, sizeof (pcicdev_t)); 811 return (DDI_FAILURE); 812 } 813 } /* ddi_prop_op("device_type") */ 814 815 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0) { 816 pcic->pc_flags = PCF_PCIBUS; 817 } else { 818 #if defined(__sparc) 819 cmn_err(CE_CONT, "pcic%d: unsupported parent bus type: [%s]\n", 820 ddi_get_instance(dip), bus_type); 821 822 kmem_free(pcic, sizeof (pcicdev_t)); 823 return (DDI_FAILURE); 824 #else 825 pcic->pc_flags = 0; 826 #endif 827 } 828 829 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 830 DDI_PROP_CANSLEEP, 831 "clock-frequency", 0)) == 0) { 832 if (pcic->pc_flags & PCF_PCIBUS) 833 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 834 else 835 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 836 } else { 837 /* 838 * OBP can declare the speed in Hz... 839 */ 840 if (pcic->bus_speed > 1000000) 841 pcic->bus_speed /= 1000000; 842 } /* ddi_prop_op("clock-frequency") */ 843 844 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 845 846 #ifdef PCIC_DEBUG 847 if (pcic_debug) { 848 cmn_err(CE_CONT, 849 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 850 ddi_get_instance(dip), 851 bus_type, pcic->bus_speed); 852 } 853 #endif 854 855 /* 856 * The reg properties on a PCI node are different than those 857 * on a non-PCI node. Handle that difference here. 858 * If it turns out to be a CardBus chip, we have even more 859 * differences. 860 */ 861 if (pcic->pc_flags & PCF_PCIBUS) { 862 int class_code; 863 #if defined(__i386) || defined(__amd64) 864 pcic->pc_base = 0x1000000; 865 pcic->pc_bound = (uint32_t)~0; 866 pcic->pc_iobase = 0x1000; 867 pcic->pc_iobound = 0xefff; 868 #elif defined(__sparc) 869 pcic->pc_base = 0x0; 870 pcic->pc_bound = (uint32_t)~0; 871 pcic->pc_iobase = 0x00000; 872 pcic->pc_iobound = 0xffff; 873 #endif 874 875 /* usually need to get at config space so map first */ 876 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 877 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 878 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 879 880 if (ddi_regs_map_setup(dip, pci_cfrn, 881 (caddr_t *)&pcic->cfgaddr, 882 PCIC_PCI_CONFIG_REG_OFFSET, 883 PCIC_PCI_CONFIG_REG_LENGTH, 884 &attr, 885 &pcic->cfg_handle) != 886 DDI_SUCCESS) { 887 cmn_err(CE_CONT, 888 "pcic%d: unable to map config space" 889 "regs\n", 890 ddi_get_instance(dip)); 891 892 kmem_free(pcic, sizeof (pcicdev_t)); 893 return (DDI_FAILURE); 894 } /* ddi_regs_map_setup */ 895 896 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 897 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 898 "class-code", -1); 899 #ifdef PCIC_DEBUG 900 if (pcic_debug) { 901 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 902 class_code); 903 } 904 #endif 905 906 switch (class_code) { 907 case PCIC_PCI_CARDBUS: 908 pcic->pc_flags |= PCF_CARDBUS; 909 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 910 /* 911 * Get access to the adapter registers on the 912 * PCI bus. A 4K memory page 913 */ 914 #if defined(PCIC_DEBUG) 915 pcic_err(dip, 8, "Is Cardbus device\n"); 916 if (pcic_debug) { 917 int nr; 918 long rs; 919 (void) ddi_dev_nregs(dip, &nr); 920 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 921 "cfghndl 0x%p nregs %d", 922 (void *)pcic->cfgaddr, 923 (void *)pcic->cfg_handle, nr); 924 925 (void) ddi_dev_regsize(dip, 926 PCIC_PCI_CONTROL_REG_NUM, &rs); 927 928 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 929 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 930 } 931 #endif 932 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 933 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 934 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 935 936 if (ddi_regs_map_setup(dip, pci_ctrn, 937 (caddr_t *)&pcic->ioaddr, 938 PCIC_PCI_CONTROL_REG_OFFSET, 939 PCIC_CB_CONTROL_REG_LENGTH, 940 &attr, &pcic->handle) != 941 DDI_SUCCESS) { 942 cmn_err(CE_CONT, 943 "pcic%d: unable to map PCI regs\n", 944 ddi_get_instance(dip)); 945 ddi_regs_map_free(&pcic->cfg_handle); 946 kmem_free(pcic, sizeof (pcicdev_t)); 947 return (DDI_FAILURE); 948 } /* ddi_regs_map_setup */ 949 950 /* 951 * Find out the chip type - If we're on a PCI bus, 952 * the adapter has that information in the PCI 953 * config space. 954 * Note that we call pcic_find_pci_type here since 955 * it needs a valid mapped pcic->handle to 956 * access some of the adapter registers in 957 * some cases. 958 */ 959 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 960 ddi_regs_map_free(&pcic->handle); 961 ddi_regs_map_free(&pcic->cfg_handle); 962 kmem_free(pcic, sizeof (pcicdev_t)); 963 cmn_err(CE_WARN, "pcic: %s: unsupported " 964 "bridge\n", 965 ddi_get_name_addr(dip)); 966 return (DDI_FAILURE); 967 } 968 break; 969 970 default: 971 case PCIC_PCI_PCMCIA: 972 /* 973 * Get access to the adapter IO registers on the 974 * PCI bus config space. 975 */ 976 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 977 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 978 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 979 980 /* 981 * We need a default mapping to the adapter's IO 982 * control register space. For most adapters 983 * that are of class PCIC_PCI_PCMCIA (or of 984 * a default class) the control registers 985 * will be using the 82365-type control/data 986 * format. 987 */ 988 if (ddi_regs_map_setup(dip, pci_ctrn, 989 (caddr_t *)&pcic->ioaddr, 990 PCIC_PCI_CONTROL_REG_OFFSET, 991 PCIC_PCI_CONTROL_REG_LENGTH, 992 &attr, 993 &pcic->handle) != DDI_SUCCESS) { 994 cmn_err(CE_CONT, 995 "pcic%d: unable to map PCI regs\n", 996 ddi_get_instance(dip)); 997 ddi_regs_map_free(&pcic->cfg_handle); 998 kmem_free(pcic, sizeof (pcicdev_t)); 999 return (DDI_FAILURE); 1000 } /* ddi_regs_map_setup */ 1001 1002 /* 1003 * Find out the chip type - If we're on a PCI bus, 1004 * the adapter has that information in the PCI 1005 * config space. 1006 * Note that we call pcic_find_pci_type here since 1007 * it needs a valid mapped pcic->handle to 1008 * access some of the adapter registers in 1009 * some cases. 1010 */ 1011 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 1012 ddi_regs_map_free(&pcic->handle); 1013 ddi_regs_map_free(&pcic->cfg_handle); 1014 kmem_free(pcic, sizeof (pcicdev_t)); 1015 cmn_err(CE_WARN, "pcic: %s: unsupported " 1016 "bridge\n", 1017 ddi_get_name_addr(dip)); 1018 return (DDI_FAILURE); 1019 } 1020 1021 /* 1022 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 1023 * for extended registers even though they are 1024 * not CardBus adapters. For those adapters, 1025 * re-map pcic->handle to be large enough to 1026 * encompass the Yenta registers. 1027 */ 1028 switch (pcic->pc_type) { 1029 case PCIC_TI_PCI1031: 1030 ddi_regs_map_free(&pcic->handle); 1031 1032 if (ddi_regs_map_setup(dip, 1033 PCIC_PCI_CONTROL_REG_NUM, 1034 (caddr_t *)&pcic->ioaddr, 1035 PCIC_PCI_CONTROL_REG_OFFSET, 1036 PCIC_CB_CONTROL_REG_LENGTH, 1037 &attr, 1038 &pcic->handle) != DDI_SUCCESS) { 1039 cmn_err(CE_CONT, 1040 "pcic%d: unable to map " 1041 "PCI regs\n", 1042 ddi_get_instance(dip)); 1043 ddi_regs_map_free(&pcic->cfg_handle); 1044 kmem_free(pcic, sizeof (pcicdev_t)); 1045 return (DDI_FAILURE); 1046 } /* ddi_regs_map_setup */ 1047 break; 1048 default: 1049 break; 1050 } /* switch (pcic->pc_type) */ 1051 break; 1052 } /* switch (class_code) */ 1053 } else { 1054 /* 1055 * We're not on a PCI bus, so assume an ISA bus type 1056 * register property. Get access to the adapter IO 1057 * registers on a non-PCI bus. 1058 */ 1059 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1060 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 1061 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1062 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 1063 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 1064 1065 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1066 (caddr_t *)&pcic->ioaddr, 1067 PCIC_ISA_CONTROL_REG_OFFSET, 1068 PCIC_ISA_CONTROL_REG_LENGTH, 1069 &attr, 1070 &pcic->handle) != DDI_SUCCESS) { 1071 cmn_err(CE_CONT, 1072 "pcic%d: unable to map ISA registers\n", 1073 ddi_get_instance(dip)); 1074 1075 kmem_free(pcic, sizeof (pcicdev_t)); 1076 return (DDI_FAILURE); 1077 } /* ddi_regs_map_setup */ 1078 1079 /* ISA bus is limited to 24-bits, but not first 640K */ 1080 pcic->pc_base = 0xd0000; 1081 pcic->pc_bound = (uint32_t)~0; 1082 pcic->pc_iobase = 0x1000; 1083 pcic->pc_iobound = 0xefff; 1084 } /* !PCF_PCIBUS */ 1085 1086 #ifdef PCIC_DEBUG 1087 if (pcic_debug) { 1088 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1089 pcic->pc_flags, pcic->pc_type); 1090 } 1091 #endif 1092 1093 /* 1094 * Setup various adapter registers for the PCI case. For the 1095 * non-PCI case, find out the chip type. 1096 */ 1097 if (pcic->pc_flags & PCF_PCIBUS) { 1098 int iline; 1099 #if defined(__sparc) 1100 iline = 0; 1101 #else 1102 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1103 #endif 1104 1105 /* set flags and socket counts based on chip type */ 1106 switch (pcic->pc_type) { 1107 uint32_t cfg; 1108 case PCIC_INTEL_i82092: 1109 cfg = ddi_get8(pcic->cfg_handle, 1110 pcic->cfgaddr + PCIC_82092_PCICON); 1111 /* we can only support 4 Socket version */ 1112 if (cfg & PCIC_82092_4_SOCKETS) { 1113 pcic->pc_numsockets = 4; 1114 pcic->pc_type = PCIC_INTEL_i82092; 1115 if (iline != 0xFF) 1116 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1117 else 1118 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1119 } else { 1120 cmn_err(CE_CONT, 1121 "pcic%d: Intel 82092 adapter " 1122 "in unsupported configuration: 0x%x", 1123 ddi_get_instance(pcic->dip), cfg); 1124 pcic->pc_numsockets = 0; 1125 } /* PCIC_82092_4_SOCKETS */ 1126 break; 1127 case PCIC_CL_PD6730: 1128 case PCIC_CL_PD6729: 1129 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1130 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1131 DDI_PROP_CANSLEEP, 1132 "interrupts", 0); 1133 /* if not interrupt pin then must use ISA style IRQs */ 1134 if (cfg == 0 || iline == 0xFF) 1135 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1136 else { 1137 /* 1138 * we have the option to use PCI interrupts. 1139 * this might not be optimal but in some cases 1140 * is the only thing possible (sparc case). 1141 * we now deterine what is possible. 1142 */ 1143 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1144 } 1145 pcic->pc_numsockets = 2; 1146 pcic->pc_flags |= PCF_IO_REMAP; 1147 break; 1148 case PCIC_TI_PCI1031: 1149 /* this chip doesn't do CardBus but looks like one */ 1150 pcic->pc_flags &= ~PCF_CARDBUS; 1151 /* FALLTHROUGH */ 1152 default: 1153 pcic->pc_flags |= PCF_IO_REMAP; 1154 /* FALLTHROUGH */ 1155 /* indicate feature even if not supported */ 1156 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1157 /* Not sure if these apply to all these chips */ 1158 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1159 pcic->pc_flags |= pcic_use_cbpwrctl; 1160 1161 pcic->pc_numsockets = 1; /* one per function */ 1162 if (iline != 0xFF) { 1163 uint8_t cfg; 1164 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1165 1166 cfg = ddi_get8(pcic->cfg_handle, 1167 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1168 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1169 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1170 PCIC_BRIDGE_CTL_REG), cfg); 1171 } 1172 else 1173 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1174 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1175 break; 1176 } 1177 } else { 1178 /* 1179 * We're not on a PCI bus so do some more 1180 * checking for adapter type here. 1181 * For the non-PCI bus case: 1182 * It could be any one of a number of different chips 1183 * If we can't determine anything else, it is assumed 1184 * to be an Intel 82365SL. The Cirrus Logic PD6710 1185 * has an extension register that provides unique 1186 * identification. Toshiba chip isn't detailed as yet. 1187 */ 1188 1189 /* Init the CL id mode */ 1190 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1191 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1192 1193 /* default to Intel i82365SL and then refine */ 1194 pcic->pc_type = PCIC_I82365SL; 1195 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1196 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1197 /* go until one succeeds or none left */ 1198 if (pcic_ci_funcs[value](pcic)) 1199 break; 1200 } 1201 1202 /* any chip specific flags get set here */ 1203 switch (pcic->pc_type) { 1204 case PCIC_CL_PD6722: 1205 pcic->pc_flags |= PCF_DMA; 1206 } 1207 1208 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1209 /* 1210 * look for total number of sockets. 1211 * basically check each possible socket for 1212 * presence like in probe 1213 */ 1214 1215 /* turn all windows off */ 1216 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1217 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1218 1219 /* 1220 * if a zero is read back, then this socket 1221 * might be present. It would be except for 1222 * some systems that map the secondary PCIC 1223 * chip space back to the first. 1224 */ 1225 if (value != 0) { 1226 /* definitely not so skip */ 1227 /* note: this is for Compaq support */ 1228 continue; 1229 } 1230 1231 /* further tests */ 1232 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1233 PCIC_REV_MASK; 1234 if (!(value >= PCIC_REV_LEVEL_LOW && 1235 value <= PCIC_REV_LEVEL_HI)) 1236 break; 1237 1238 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1239 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1240 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1241 1242 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1243 if (value != 0xaa || j != 0x55) 1244 break; 1245 1246 /* 1247 * at this point we know if we have hardware 1248 * of some type and not just the bus holding 1249 * a pattern for us. We still have to determine 1250 * the case where more than 2 sockets are 1251 * really the same due to peculiar mappings of 1252 * hardware. 1253 */ 1254 j = pcic->pc_numsockets++; 1255 pcic->pc_sockets[j].pcs_flags = 0; 1256 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1257 pcic->pc_sockets[j].pcs_socket = i; 1258 1259 /* put PC Card into RESET, just in case */ 1260 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1261 pcic_putb(pcic, i, PCIC_INTERRUPT, 1262 value & ~PCIC_RESET); 1263 } 1264 1265 #if defined(PCIC_DEBUG) 1266 if (pcic_debug) 1267 cmn_err(CE_CONT, "num sockets = %d\n", 1268 pcic->pc_numsockets); 1269 #endif 1270 if (pcic->pc_numsockets == 0) { 1271 ddi_regs_map_free(&pcic->handle); 1272 kmem_free(pcic, sizeof (pcicdev_t)); 1273 return (DDI_FAILURE); 1274 } 1275 1276 /* 1277 * need to think this through again in light of 1278 * Compaq not following the model that all the 1279 * chip vendors recommend. IBM 755 seems to be 1280 * afflicted as well. Basically, if the vendor 1281 * wired things wrong, socket 0 responds for socket 2 1282 * accesses, etc. 1283 */ 1284 if (pcic->pc_numsockets > 2) { 1285 int count = pcic->pc_numsockets / 4; 1286 for (i = 0; i < count; i++) { 1287 /* put pattern into socket 0 */ 1288 pcic_putb(pcic, i, 1289 PCIC_SYSMEM_0_STARTLOW, 0x11); 1290 1291 /* put pattern into socket 2 */ 1292 pcic_putb(pcic, i + 2, 1293 PCIC_SYSMEM_0_STARTLOW, 0x33); 1294 1295 /* read back socket 0 */ 1296 value = pcic_getb(pcic, i, 1297 PCIC_SYSMEM_0_STARTLOW); 1298 1299 /* read back chip 1 socket 0 */ 1300 j = pcic_getb(pcic, i + 2, 1301 PCIC_SYSMEM_0_STARTLOW); 1302 if (j == value) { 1303 pcic->pc_numsockets -= 2; 1304 } 1305 } 1306 } 1307 1308 smi = 0xff; /* no more override */ 1309 1310 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1311 DDI_PROP_DONTPASS, "need-mult-irq", 1312 0xffff) != 0xffff) 1313 pcic->pc_flags |= PCF_MULT_IRQ; 1314 1315 } /* !PCF_PCIBUS */ 1316 1317 /* 1318 * some platforms/busses need to have resources setup 1319 * this is temporary until a real resource allocator is 1320 * implemented. 1321 */ 1322 1323 pcic_init_assigned(dip); 1324 1325 typename = pcic->pc_chipname; 1326 1327 #ifdef PCIC_DEBUG 1328 if (pcic_debug) { 1329 int nregs, nintrs; 1330 1331 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1332 nregs = 0; 1333 1334 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1335 nintrs = 0; 1336 1337 cmn_err(CE_CONT, 1338 "pcic%d: %d register sets, %d interrupts\n", 1339 ddi_get_instance(dip), nregs, nintrs); 1340 1341 nintrs = 0; 1342 while (nregs--) { 1343 off_t size; 1344 1345 if (ddi_dev_regsize(dip, nintrs, &size) == 1346 DDI_SUCCESS) { 1347 cmn_err(CE_CONT, 1348 "\tregnum %d size %ld (0x%lx)" 1349 "bytes", 1350 nintrs, size, size); 1351 if (nintrs == 1352 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1353 PCIC_ISA_CONTROL_REG_NUM : 1354 PCIC_PCI_CONTROL_REG_NUM)) 1355 cmn_err(CE_CONT, 1356 " mapped at: 0x%p\n", 1357 (void *)pcic->ioaddr); 1358 else 1359 cmn_err(CE_CONT, "\n"); 1360 } else { 1361 cmn_err(CE_CONT, 1362 "\tddi_dev_regsize(rnumber" 1363 "= %d) returns DDI_FAILURE\n", 1364 nintrs); 1365 } 1366 nintrs++; 1367 } /* while */ 1368 } /* if (pcic_debug) */ 1369 #endif 1370 1371 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1372 1373 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1374 "disable-audio", 0)) 1375 pcic->pc_flags |= PCF_AUDIO; 1376 1377 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1378 "disable-cardbus", 0)) 1379 pcic->pc_flags &= ~PCF_CARDBUS; 1380 1381 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1382 typename); 1383 1384 /* 1385 * Init all socket SMI levels to 0 (no SMI) 1386 */ 1387 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1388 pcic->pc_sockets[i].pcs_smi = 0; 1389 pcic->pc_sockets[i].pcs_debounce_id = 0; 1390 pcic->pc_sockets[i].pcs_pcic = pcic; 1391 } 1392 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1393 1394 /* 1395 * Setup the IRQ handler(s) 1396 */ 1397 switch (pcic->pc_intr_mode) { 1398 int xx; 1399 case PCIC_INTR_MODE_ISA: 1400 /* 1401 * On a non-PCI bus, we just use whatever SMI IRQ level was 1402 * specified above, and the IO IRQ levels are allocated 1403 * dynamically. 1404 */ 1405 for (xx = 15, smi = 0; xx >= 0; xx--) { 1406 if (PCIC_IRQ(xx) & 1407 PCIC_AVAIL_IRQS) { 1408 smi = pcmcia_get_intr(dip, xx); 1409 if (smi >= 0) 1410 break; 1411 } 1412 } 1413 #if defined(PCIC_DEBUG) 1414 if (pcic_debug) 1415 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1416 #endif 1417 /* init to same so share is easy */ 1418 for (i = 0; i < pcic->pc_numsockets; i++) 1419 pcic->pc_sockets[i].pcs_smi = smi; 1420 /* any special handling of IRQ levels */ 1421 if (pcic->pc_flags & PCF_MULT_IRQ) { 1422 for (i = 2; i < pcic->pc_numsockets; i++) { 1423 if ((i & 1) == 0) { 1424 int xx; 1425 for (xx = 15, smi = 0; xx >= 0; xx--) { 1426 if (PCIC_IRQ(xx) & 1427 PCIC_AVAIL_IRQS) { 1428 smi = 1429 pcmcia_get_intr(dip, 1430 xx); 1431 if (smi >= 0) 1432 break; 1433 } 1434 } 1435 } 1436 if (smi >= 0) 1437 pcic->pc_sockets[i].pcs_smi = smi; 1438 } 1439 } 1440 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1441 sizeof (ddi_intr_handle_t), KM_SLEEP); 1442 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1443 struct intrspec *ispecp; 1444 struct ddi_parent_private_data *pdp; 1445 1446 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1447 continue; 1448 else { 1449 irqlevel = pcic->pc_sockets[i].pcs_smi; 1450 } 1451 /* 1452 * now convert the allocated IRQ into an intrspec 1453 * and ask our parent to add it. Don't use 1454 * the ddi_add_intr since we don't have a 1455 * default intrspec in all cases. 1456 * 1457 * note: this sort of violates DDI but we don't 1458 * get hardware intrspecs for many of the devices. 1459 * at the same time, we know how to allocate them 1460 * so we do the right thing. 1461 */ 1462 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1463 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1464 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1465 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1466 ddi_get_name(dip)); 1467 goto isa_exit1; 1468 } 1469 1470 /* 1471 * See earlier note: 1472 * Since some devices don't have 'intrspec' 1473 * we make one up in rootnex. 1474 * 1475 * However, it is not properly initialized as 1476 * the data it needs is present in this driver 1477 * and there is no interface to pass that up. 1478 * Specially 'irqlevel' is very important and 1479 * it is part of pcic struct. 1480 * 1481 * Set 'intrspec' up here; otherwise adding the 1482 * interrupt will fail. 1483 */ 1484 pdp = ddi_get_parent_data(dip); 1485 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1486 ispecp->intrspec_vec = irqlevel; 1487 ispecp->intrspec_pri = pcic->pc_irq; 1488 1489 /* Stay compatible w/ PCMCIA */ 1490 pcic->pc_pri = (ddi_iblock_cookie_t) 1491 (uintptr_t)pcic->pc_irq; 1492 pcic->pc_dcookie.idev_priority = 1493 (uintptr_t)pcic->pc_pri; 1494 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1495 1496 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1497 pcic->pc_irq); 1498 1499 if (i == 0) { 1500 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1501 DDI_INTR_PRI(pcic->pc_irq)); 1502 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1503 NULL); 1504 } 1505 1506 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1507 pcic_intr, (caddr_t)pcic, NULL)) { 1508 cmn_err(CE_WARN, 1509 "%s: ddi_intr_add_handler failed", 1510 ddi_get_name(dip)); 1511 goto isa_exit2; 1512 } 1513 1514 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1515 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1516 ddi_get_name(dip)); 1517 for (j = i; j < 0; j--) 1518 (void) ddi_intr_remove_handler( 1519 pcic->pc_intr_htblp[j]); 1520 goto isa_exit2; 1521 } 1522 } 1523 break; 1524 case PCIC_INTR_MODE_PCI_1: 1525 case PCIC_INTR_MODE_PCI: 1526 /* 1527 * If we're on a PCI bus, we route all interrupts, both SMI 1528 * and IO interrupts, through a single interrupt line. 1529 * Assign the SMI IRQ level to the IO IRQ level here. 1530 */ 1531 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1532 KM_SLEEP); 1533 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1534 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1535 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1536 goto pci_exit1; 1537 1538 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1539 &pri) != DDI_SUCCESS) { 1540 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1541 goto pci_exit1; 1542 } 1543 1544 pcic->pc_pri = (void *)(uintptr_t)pri; 1545 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1546 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1547 1548 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1549 pcic_intr, (caddr_t)pcic, NULL)) 1550 goto pci_exit2; 1551 1552 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1553 (void) ddi_intr_remove_handler( 1554 pcic->pc_pci_intr_hdlp[0]); 1555 goto pci_exit2; 1556 } 1557 1558 /* Stay compatible w/ PCMCIA */ 1559 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1560 1561 /* init to same (PCI) so share is easy */ 1562 for (i = 0; i < pcic->pc_numsockets; i++) 1563 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1564 break; 1565 } 1566 1567 /* 1568 * Setup the adapter hardware to some reasonable defaults. 1569 */ 1570 mutex_enter(&pcic->pc_lock); 1571 /* mark the driver state as attached */ 1572 pcic->pc_flags |= PCF_ATTACHED; 1573 pcic_setup_adapter(pcic); 1574 1575 for (j = 0; j < pcic->pc_numsockets; j++) 1576 if (ddi_intr_add_softint(dip, 1577 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1578 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1579 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1580 goto pci_exit2; 1581 1582 #if defined(PCIC_DEBUG) 1583 if (pcic_debug) 1584 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1585 pcic->pc_numsockets); 1586 #endif 1587 1588 pcic_nexus->an_iblock = &pcic->pc_pri; 1589 pcic_nexus->an_idev = &pcic->pc_dcookie; 1590 1591 mutex_exit(&pcic->pc_lock); 1592 1593 #ifdef CARDBUS 1594 (void) cardbus_enable_cd_intr(dip); 1595 if (pcic_debug) { 1596 1597 cardbus_dump_pci_config(dip); 1598 cardbus_dump_socket(dip); 1599 } 1600 1601 /* 1602 * Give the Cardbus misc module a chance to do it's per-adapter 1603 * instance setup. Note that there is no corresponding detach() 1604 * call. 1605 */ 1606 if (pcic->pc_flags & PCF_CARDBUS) 1607 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1608 cmn_err(CE_CONT, 1609 "pcic_attach: cardbus_attach failed\n"); 1610 goto pci_exit2; 1611 } 1612 #endif 1613 1614 /* 1615 * Give the PCMCIA misc module a chance to do it's per-adapter 1616 * instance setup. 1617 */ 1618 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1619 goto pci_exit2; 1620 1621 syshw_attach(pcic); 1622 if (pcic_maxinst == -1) { 1623 /* This assumes that all instances run at the same IPL. */ 1624 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1625 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1626 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1627 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1628 v.v_maxsyspri - 2); 1629 } 1630 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1631 /* 1632 * Setup a debounce timeout to do an initial card detect 1633 * and enable interrupts. 1634 */ 1635 for (j = 0; j < pcic->pc_numsockets; j++) { 1636 shwp = kmem_alloc(sizeof (syshw_t), KM_SLEEP); 1637 if (shwp) { 1638 bcopy(&pcic_syshw, shwp, sizeof (pcic_syshw)); 1639 pcic_syshw.id_string[15]++; 1640 pcic->pc_sockets[j].pcs_syshwsig = 1641 syshw_add2map(shwp, pcic_syshw_cardstate, 1642 &pcic->pc_sockets[j]); 1643 } 1644 pcic->pc_sockets[j].pcs_debounce_id = 1645 pcic_add_debqueue(&pcic->pc_sockets[j], 1646 drv_usectohz(pcic_debounce_time)); 1647 } 1648 1649 return (i); 1650 1651 isa_exit2: 1652 mutex_destroy(&pcic->intr_lock); 1653 mutex_destroy(&pcic->pc_lock); 1654 for (j = i; j < 0; j--) 1655 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1656 isa_exit1: 1657 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1658 ddi_regs_map_free(&pcic->handle); 1659 if (pcic->pc_flags & PCF_PCIBUS) 1660 ddi_regs_map_free(&pcic->cfg_handle); 1661 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1662 sizeof (ddi_intr_handle_t)); 1663 kmem_free(pcic, sizeof (pcicdev_t)); 1664 return (DDI_FAILURE); 1665 1666 pci_exit2: 1667 mutex_destroy(&pcic->intr_lock); 1668 mutex_destroy(&pcic->pc_lock); 1669 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1670 pci_exit1: 1671 ddi_regs_map_free(&pcic->handle); 1672 if (pcic->pc_flags & PCF_PCIBUS) 1673 ddi_regs_map_free(&pcic->cfg_handle); 1674 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1675 kmem_free(pcic, sizeof (pcicdev_t)); 1676 return (DDI_FAILURE); 1677 } 1678 1679 /* 1680 * pcic_detach() 1681 * request to detach from the system 1682 */ 1683 static int 1684 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1685 { 1686 anp_t *anp = ddi_get_driver_private(dip); 1687 pcicdev_t *pcic = anp->an_private; 1688 int i; 1689 1690 switch (cmd) { 1691 case DDI_DETACH: 1692 /* don't detach if the nexus still talks to us */ 1693 if (pcic->pc_callback != NULL) 1694 return (DDI_FAILURE); 1695 syshw_detach(pcic); 1696 1697 /* kill off the pm simulation */ 1698 if (pcic->pc_pmtimer) 1699 (void) untimeout(pcic->pc_pmtimer); 1700 1701 /* turn everything off for all sockets and chips */ 1702 for (i = 0; i < pcic->pc_numsockets; i++) { 1703 if (pcic->pc_sockets[i].pcs_debounce_id) 1704 pcic_rm_debqueue( 1705 pcic->pc_sockets[i].pcs_debounce_id); 1706 pcic->pc_sockets[i].pcs_debounce_id = 0; 1707 1708 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1709 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1710 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1711 /* disable interrupts and put card into RESET */ 1712 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1713 } 1714 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1715 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1716 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1717 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1718 pcic->pc_flags = 0; 1719 mutex_destroy(&pcic->pc_lock); 1720 mutex_destroy(&pcic->intr_lock); 1721 cv_destroy(&pcic->pm_cv); 1722 if (pcic->pc_flags & PCF_PCIBUS) 1723 ddi_regs_map_free(&pcic->cfg_handle); 1724 if (pcic->handle) 1725 ddi_regs_map_free(&pcic->handle); 1726 kmem_free(pcic, sizeof (pcicdev_t)); 1727 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1728 return (DDI_SUCCESS); 1729 1730 case DDI_SUSPEND: 1731 case DDI_PM_SUSPEND: 1732 /* 1733 * we got a suspend event (either real or imagined) 1734 * so notify the nexus proper that all existing cards 1735 * should go away. 1736 */ 1737 mutex_enter(&pcic->pc_lock); 1738 #ifdef CARDBUS 1739 if (pcic->pc_flags & PCF_CARDBUS) 1740 for (i = 0; i < pcic->pc_numsockets; i++) 1741 if ((pcic->pc_sockets[i].pcs_flags & 1742 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1743 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) 1744 if (!cardbus_can_suspend(dip)) { 1745 mutex_exit(&pcic->pc_lock); 1746 cmn_err(CE_WARN, 1747 "Please unconfigure all " 1748 "CardBus devices before " 1749 "attempting to suspend\n"); 1750 return (DDI_FAILURE); 1751 } 1752 #endif 1753 /* turn everything off for all sockets and chips */ 1754 for (i = 0; i < pcic->pc_numsockets; i++) { 1755 if (pcic->pc_sockets[i].pcs_debounce_id) 1756 pcic_rm_debqueue( 1757 pcic->pc_sockets[i].pcs_debounce_id); 1758 pcic->pc_sockets[i].pcs_debounce_id = 0; 1759 1760 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1761 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1762 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1763 /* disable interrupts and put card into RESET */ 1764 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1765 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1766 if (pcic->pc_flags & PCF_CBPWRCTL) 1767 pcic_putcb(pcic, CB_CONTROL, 0); 1768 1769 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1770 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1771 /* 1772 * Because we are half way through a save 1773 * all this does is schedule a removal event 1774 * to cs for when the system comes back. 1775 * This doesn't actually matter. 1776 */ 1777 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1778 pcic->pc_callback) { 1779 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1780 PCE_CARD_REMOVAL, 1781 pcic->pc_sockets[i].pcs_socket); 1782 } 1783 } 1784 } 1785 1786 pcic->pc_flags |= PCF_SUSPENDED; 1787 mutex_exit(&pcic->pc_lock); 1788 pcic_delayed_resume_toid = 0; 1789 1790 /* 1791 * when true power management exists, save the adapter 1792 * state here to enable a recovery. For the emulation 1793 * condition, the state is gone 1794 */ 1795 return (DDI_SUCCESS); 1796 1797 default: 1798 return (EINVAL); 1799 } 1800 } 1801 1802 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1803 static uint32_t pcic_tisysctl_offbits = 0; 1804 static uint32_t pcic_default_latency = 0x40; 1805 1806 static void 1807 pcic_setup_adapter(pcicdev_t *pcic) 1808 { 1809 int i; 1810 int value, flags; 1811 1812 if (pcic->pc_flags & PCF_PCIBUS) { 1813 /* 1814 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1815 */ 1816 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1817 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1818 } 1819 /* enable each socket */ 1820 for (i = 0; i < pcic->pc_numsockets; i++) { 1821 pcic->pc_sockets[i].pcs_flags = 0; 1822 /* find out the socket capabilities (I/O vs memory) */ 1823 value = pcic_getb(pcic, i, 1824 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1825 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1826 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1827 1828 /* disable all windows just in case */ 1829 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1830 1831 switch (pcic->pc_type) { 1832 uint32_t cfg32; 1833 uint16_t cfg16; 1834 uint8_t cfg; 1835 1836 /* enable extended registers for Vadem */ 1837 case PCIC_VADEM_VG469: 1838 case PCIC_VADEM: 1839 1840 /* enable card status change interrupt for socket */ 1841 break; 1842 1843 case PCIC_I82365SL: 1844 break; 1845 1846 case PCIC_CL_PD6710: 1847 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1848 break; 1849 1850 /* 1851 * On the CL_6730, we need to set up the interrupt 1852 * signalling mode (PCI mode) and set the SMI and 1853 * IRQ interrupt lines to PCI/level-mode. 1854 */ 1855 case PCIC_CL_PD6730: 1856 switch (pcic->pc_intr_mode) { 1857 case PCIC_INTR_MODE_PCI_1: 1858 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1859 ((clext_reg_read(pcic, i, 1860 PCIC_CLEXT_MISC_CTL_3) & 1861 ~PCIC_CLEXT_INT_PCI) | 1862 PCIC_CLEXT_INT_PCI)); 1863 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1864 (PCIC_CLEXT_IRQ_LVL_MODE | 1865 PCIC_CLEXT_SMI_LVL_MODE)); 1866 cfg = PCIC_CL_LP_DYN_MODE; 1867 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1868 break; 1869 case PCIC_INTR_MODE_ISA: 1870 break; 1871 } 1872 break; 1873 /* 1874 * On the CL_6729, we set the SMI and IRQ interrupt 1875 * lines to PCI/level-mode. as well as program the 1876 * correct clock speed divider bit. 1877 */ 1878 case PCIC_CL_PD6729: 1879 switch (pcic->pc_intr_mode) { 1880 case PCIC_INTR_MODE_PCI_1: 1881 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1882 (PCIC_CLEXT_IRQ_LVL_MODE | 1883 PCIC_CLEXT_SMI_LVL_MODE)); 1884 1885 break; 1886 case PCIC_INTR_MODE_ISA: 1887 break; 1888 } 1889 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1890 cfg = 0; 1891 cfg |= PCIC_CL_TIMER_CLK_DIV; 1892 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1893 } 1894 break; 1895 case PCIC_INTEL_i82092: 1896 cfg = PCIC_82092_EN_TIMING; 1897 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1898 cfg |= PCIC_82092_PCICLK_25MHZ; 1899 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1900 PCIC_82092_PCICON, cfg); 1901 break; 1902 case PCIC_TI_PCI1130: 1903 case PCIC_TI_PCI1131: 1904 case PCIC_TI_PCI1250: 1905 case PCIC_TI_PCI1031: 1906 cfg = ddi_get8(pcic->cfg_handle, 1907 pcic->cfgaddr + PCIC_DEVCTL_REG); 1908 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1909 switch (pcic->pc_intr_mode) { 1910 case PCIC_INTR_MODE_ISA: 1911 cfg |= PCIC_DEVCTL_INTR_ISA; 1912 break; 1913 } 1914 #ifdef PCIC_DEBUG 1915 if (pcic_debug) { 1916 cmn_err(CE_CONT, "pcic_setup_adapter: " 1917 "write reg 0x%x=%x \n", 1918 PCIC_DEVCTL_REG, cfg); 1919 } 1920 #endif 1921 ddi_put8(pcic->cfg_handle, 1922 pcic->cfgaddr + PCIC_DEVCTL_REG, 1923 cfg); 1924 1925 cfg = ddi_get8(pcic->cfg_handle, 1926 pcic->cfgaddr + PCIC_CRDCTL_REG); 1927 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1928 PCIC_CRDCTL_PCIFUNC); 1929 switch (pcic->pc_intr_mode) { 1930 case PCIC_INTR_MODE_PCI_1: 1931 cfg |= PCIC_CRDCTL_PCIINTR | 1932 PCIC_CRDCTL_PCICSC | 1933 PCIC_CRDCTL_PCIFUNC; 1934 pcic->pc_flags |= PCF_USE_SMI; 1935 break; 1936 } 1937 #ifdef PCIC_DEBUG 1938 if (pcic_debug) { 1939 cmn_err(CE_CONT, "pcic_setup_adapter: " 1940 " write reg 0x%x=%x \n", 1941 PCIC_CRDCTL_REG, cfg); 1942 } 1943 #endif 1944 ddi_put8(pcic->cfg_handle, 1945 pcic->cfgaddr + PCIC_CRDCTL_REG, 1946 cfg); 1947 break; 1948 case PCIC_TI_PCI1221: 1949 case PCIC_TI_PCI1225: 1950 cfg = ddi_get8(pcic->cfg_handle, 1951 pcic->cfgaddr + PCIC_DEVCTL_REG); 1952 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1953 #ifdef PCIC_DEBUG 1954 if (pcic_debug) { 1955 cmn_err(CE_CONT, "pcic_setup_adapter: " 1956 " write reg 0x%x=%x \n", 1957 PCIC_DEVCTL_REG, cfg); 1958 } 1959 #endif 1960 ddi_put8(pcic->cfg_handle, 1961 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1962 1963 cfg = ddi_get8(pcic->cfg_handle, 1964 pcic->cfgaddr + PCIC_DIAG_REG); 1965 if (pcic->pc_type == PCIC_TI_PCI1225) { 1966 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1967 } else { 1968 cfg |= PCIC_DIAG_ASYNC; 1969 } 1970 pcic->pc_flags |= PCF_USE_SMI; 1971 #ifdef PCIC_DEBUG 1972 if (pcic_debug) { 1973 cmn_err(CE_CONT, "pcic_setup_adapter: " 1974 " write reg 0x%x=%x \n", 1975 PCIC_DIAG_REG, cfg); 1976 } 1977 #endif 1978 ddi_put8(pcic->cfg_handle, 1979 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1980 break; 1981 case PCIC_TI_PCI1520: 1982 case PCIC_TI_PCI1510: 1983 case PCIC_TI_VENDOR: 1984 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1985 cfg = ddi_get8(pcic->cfg_handle, 1986 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1987 cfg |= PCIC_FUN_INT_MOD_ISA; 1988 ddi_put8(pcic->cfg_handle, 1989 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1990 cfg); 1991 } 1992 cfg = ddi_get8(pcic->cfg_handle, 1993 pcic->cfgaddr + PCIC_DEVCTL_REG); 1994 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1995 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) 1996 cfg |= PCIC_DEVCTL_INTR_ISA; 1997 ddi_put8(pcic->cfg_handle, 1998 pcic->cfgaddr + PCIC_DEVCTL_REG, 1999 cfg); 2000 2001 /* tie INTA and INTB together */ 2002 cfg = ddi_get8(pcic->cfg_handle, 2003 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 2004 cfg |= PCIC_SYSCTL_INTRTIE; 2005 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 2006 PCIC_SYSCTL_REG + 3), cfg); 2007 cfg = ddi_get8(pcic->cfg_handle, 2008 pcic->cfgaddr + PCIC_DIAG_REG); 2009 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2010 ddi_put8(pcic->cfg_handle, 2011 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2012 break; 2013 case PCIC_TI_PCI1410: 2014 cfg = ddi_get8(pcic->cfg_handle, 2015 pcic->cfgaddr + PCIC_DIAG_REG); 2016 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2017 ddi_put8(pcic->cfg_handle, 2018 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2019 break; 2020 case PCIC_TOSHIBA_TOPIC100: 2021 case PCIC_TOSHIBA_TOPIC95: 2022 case PCIC_TOSHIBA_VENDOR: 2023 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2024 PCIC_TOSHIBA_SLOT_CTL_REG); 2025 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 2026 PCIC_TOSHIBA_SCR_SLOTEN); 2027 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 2028 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 2029 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 2030 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 2031 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2032 PCIC_TOSHIBA_INTR_CTL_REG); 2033 switch (pcic->pc_intr_mode) { 2034 case PCIC_INTR_MODE_ISA: 2035 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 2036 ddi_put8(pcic->cfg_handle, 2037 pcic->cfgaddr + 2038 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2039 2040 cfg = ddi_get8(pcic->cfg_handle, 2041 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2042 cfg |= PCIC_FUN_INT_MOD_ISA; 2043 ddi_put8(pcic->cfg_handle, 2044 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2045 cfg); 2046 break; 2047 case PCIC_INTR_MODE_PCI_1: 2048 cfg |= PCIC_TOSHIBA_ICR_SRC; 2049 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 2050 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 2051 ddi_put8(pcic->cfg_handle, 2052 pcic->cfgaddr + 2053 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2054 break; 2055 } 2056 break; 2057 case PCIC_O2MICRO_VENDOR: 2058 cfg32 = ddi_get32(pcic->cfg_handle, 2059 (uint32_t *)(pcic->cfgaddr + 2060 PCIC_O2MICRO_MISC_CTL)); 2061 switch (pcic->pc_intr_mode) { 2062 case PCIC_INTR_MODE_ISA: 2063 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2064 PCIC_O2MICRO_INT_MOD_PCI); 2065 ddi_put32(pcic->cfg_handle, 2066 (uint32_t *)(pcic->cfgaddr + 2067 PCIC_O2MICRO_MISC_CTL), 2068 cfg32); 2069 cfg = ddi_get8(pcic->cfg_handle, 2070 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2071 cfg |= PCIC_FUN_INT_MOD_ISA; 2072 ddi_put8(pcic->cfg_handle, 2073 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2074 cfg); 2075 break; 2076 case PCIC_INTR_MODE_PCI_1: 2077 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2078 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2079 ddi_put32(pcic->cfg_handle, 2080 (uint32_t *)(pcic->cfgaddr + 2081 PCIC_O2MICRO_MISC_CTL), 2082 cfg32); 2083 break; 2084 } 2085 break; 2086 case PCIC_RICOH_VENDOR: 2087 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2088 cfg16 = ddi_get16(pcic->cfg_handle, 2089 (uint16_t *)(pcic->cfgaddr + 2090 PCIC_RICOH_MISC_CTL_2)); 2091 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2092 PCIC_RICOH_FUN_INT_MOD); 2093 ddi_put16(pcic->cfg_handle, 2094 (uint16_t *)(pcic->cfgaddr + 2095 PCIC_RICOH_MISC_CTL_2), 2096 cfg16); 2097 2098 cfg16 = ddi_get16(pcic->cfg_handle, 2099 (uint16_t *)(pcic->cfgaddr + 2100 PCIC_RICOH_MISC_CTL)); 2101 cfg16 |= PCIC_RICOH_SIRQ_EN; 2102 ddi_put16(pcic->cfg_handle, 2103 (uint16_t *)(pcic->cfgaddr + 2104 PCIC_RICOH_MISC_CTL), 2105 cfg16); 2106 2107 cfg = ddi_get8(pcic->cfg_handle, 2108 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2109 cfg |= PCIC_FUN_INT_MOD_ISA; 2110 ddi_put8(pcic->cfg_handle, 2111 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2112 cfg); 2113 } 2114 break; 2115 default: 2116 break; 2117 } /* switch */ 2118 2119 /* 2120 * The default value in the EEPROM (loaded on reset) for 2121 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that 2122 * MFUNC0 is connected to INTA, and MFUNC1 is connected to 2123 * INTB. This applies to all TI CardBus controllers. 2124 */ 2125 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID && 2126 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) { 2127 value = ddi_get32(pcic->cfg_handle, 2128 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG)); 2129 value &= ~0xff; 2130 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr + 2131 PCIC_MFROUTE_REG), value|0x22); 2132 } 2133 2134 /* setup general card status change interrupt */ 2135 switch (pcic->pc_type) { 2136 case PCIC_TI_PCI1225: 2137 case PCIC_TI_PCI1221: 2138 case PCIC_TI_PCI1031: 2139 case PCIC_TI_PCI1520: 2140 case PCIC_TI_PCI1410: 2141 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2142 PCIC_CHANGE_DEFAULT); 2143 break; 2144 default: 2145 if (pcic->pc_intr_mode == 2146 PCIC_INTR_MODE_PCI_1) { 2147 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2148 PCIC_CHANGE_DEFAULT); 2149 break; 2150 } else { 2151 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2152 PCIC_CHANGE_DEFAULT | 2153 (pcic->pc_sockets[i].pcs_smi << 4)); 2154 break; 2155 } 2156 } 2157 2158 pcic->pc_flags |= PCF_INTRENAB; 2159 2160 /* take card out of RESET */ 2161 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2162 /* turn power off and let CS do this */ 2163 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2164 2165 /* final chip specific initialization */ 2166 switch (pcic->pc_type) { 2167 case PCIC_VADEM: 2168 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2169 PCIC_VC_DELAYENABLE); 2170 pcic->pc_flags |= PCF_DEBOUNCE; 2171 /* FALLTHROUGH */ 2172 case PCIC_I82365SL: 2173 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2174 PCIC_GC_CSC_WRITE); 2175 /* clear any pending interrupts */ 2176 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2177 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2178 break; 2179 /* The 82092 uses PCI config space to enable interrupts */ 2180 case PCIC_INTEL_i82092: 2181 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2182 PCIC_82092_INT_ENABLE); 2183 break; 2184 case PCIC_CL_PD6729: 2185 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2186 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2187 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2188 value | PCIC_CL_TIMER_CLK_DIV); 2189 } 2190 break; 2191 } /* switch */ 2192 2193 #if defined(PCIC_DEBUG) 2194 if (pcic_debug) 2195 cmn_err(CE_CONT, 2196 "socket %d value=%x, flags = %x (%s)\n", 2197 i, value, pcic->pc_sockets[i].pcs_flags, 2198 (pcic->pc_sockets[i].pcs_flags & 2199 PCS_CARD_PRESENT) ? 2200 "card present" : "no card"); 2201 #endif 2202 } 2203 } 2204 2205 /* 2206 * pcic_intr(caddr_t, caddr_t) 2207 * interrupt handler for the PCIC style adapter 2208 * handles all basic interrupts and also checks 2209 * for status changes and notifies the nexus if 2210 * necessary 2211 * 2212 * On PCI bus adapters, also handles all card 2213 * IO interrupts. 2214 */ 2215 /*ARGSUSED*/ 2216 uint32_t 2217 pcic_intr(caddr_t arg1, caddr_t arg2) 2218 { 2219 pcicdev_t *pcic = (pcicdev_t *)arg1; 2220 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2221 uint8_t status; 2222 uint_t io_ints; 2223 2224 #if defined(PCIC_DEBUG) 2225 pcic_err(pcic->dip, 0xf, 2226 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2227 " pc_numsockets=%d \n", 2228 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2229 #endif 2230 2231 if (!(pcic->pc_flags & PCF_ATTACHED)) 2232 return (DDI_INTR_UNCLAIMED); 2233 2234 mutex_enter(&pcic->intr_lock); 2235 2236 if (pcic->pc_flags & PCF_SUSPENDED) { 2237 mutex_exit(&pcic->intr_lock); 2238 return (ret); 2239 } 2240 2241 /* 2242 * need to change to only ACK and touch the slot that 2243 * actually caused the interrupt. Currently everything 2244 * is acked 2245 * 2246 * we need to look at all known sockets to determine 2247 * what might have happened, so step through the list 2248 * of them 2249 */ 2250 #ifdef VOYAGER 2251 ret = syshw_intr_hi(pcic); 2252 #endif 2253 2254 /* 2255 * Set the bitmask for IO interrupts to initially include all sockets 2256 */ 2257 io_ints = (1 << pcic->pc_numsockets) - 1; 2258 2259 for (i = 0; i < pcic->pc_numsockets; i++) { 2260 int card_type; 2261 pcic_socket_t *sockp; 2262 int value_cb = 0; 2263 2264 sockp = &pcic->pc_sockets[i]; 2265 /* get the socket's I/O addresses */ 2266 2267 if (sockp->pcs_flags & PCS_WAITING) { 2268 io_ints &= ~(1 << i); 2269 continue; 2270 } 2271 2272 if (sockp->pcs_flags & PCS_CARD_IO) 2273 card_type = IF_IO; 2274 else 2275 card_type = IF_MEMORY; 2276 2277 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2278 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2279 2280 value = pcic_change(pcic, i); 2281 2282 if ((value != 0) || (value_cb != 0)) { 2283 int x = pcic->pc_cb_arg; 2284 2285 ret = DDI_INTR_CLAIMED; 2286 2287 #if defined(PCIC_DEBUG) 2288 pcic_err(pcic->dip, 0x9, 2289 "card_type = %d, value_cb = 0x%x\n", 2290 card_type, 2291 value_cb ? value_cb : 2292 pcic_getcb(pcic, CB_STATUS_EVENT)); 2293 if (pcic_debug) 2294 cmn_err(CE_CONT, 2295 "\tchange on socket %d (%x)\n", i, 2296 value); 2297 #endif 2298 /* find out what happened */ 2299 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2300 2301 /* acknowledge the interrupt */ 2302 if (value_cb) 2303 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2304 2305 if (value) 2306 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2307 value); 2308 2309 if (pcic->pc_callback == NULL) { 2310 /* if not callback handler, nothing to do */ 2311 continue; 2312 } 2313 2314 /* Card Detect */ 2315 if (value & PCIC_CD_DETECT || 2316 value_cb & CB_PS_CCDMASK) { 2317 uint8_t irq; 2318 #if defined(PCIC_DEBUG) 2319 if (pcic_debug) 2320 cmn_err(CE_CONT, 2321 "\tcd_detect: status=%x," 2322 " flags=%x\n", 2323 status, sockp->pcs_flags); 2324 #else 2325 #ifdef lint 2326 if (status == 0) 2327 status++; 2328 #endif 2329 #endif 2330 /* 2331 * Turn off all interrupts for this socket here. 2332 */ 2333 irq = pcic_getb(pcic, sockp->pcs_socket, 2334 PCIC_MANAGEMENT_INT); 2335 irq &= ~PCIC_CHANGE_MASK; 2336 pcic_putb(pcic, sockp->pcs_socket, 2337 PCIC_MANAGEMENT_INT, irq); 2338 2339 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2340 2341 /* 2342 * Put the socket in debouncing state so that 2343 * the leaf driver won't receive interrupts. 2344 * Crucial for handling surprise-removal. 2345 */ 2346 sockp->pcs_flags |= PCS_DEBOUNCING; 2347 2348 if (!sockp->pcs_cd_softint_flg) { 2349 sockp->pcs_cd_softint_flg = 1; 2350 (void) ddi_intr_trigger_softint( 2351 sockp->pcs_cd_softint_hdl, NULL); 2352 } 2353 2354 io_ints &= ~(1 << i); 2355 } /* PCIC_CD_DETECT */ 2356 2357 /* Ready/Change Detect */ 2358 sockp->pcs_state ^= SBM_RDYBSY; 2359 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2360 sockp->pcs_flags |= PCS_READY; 2361 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2362 } 2363 2364 /* Battery Warn Detect */ 2365 if (card_type == IF_MEMORY && 2366 value & PCIC_BW_DETECT && 2367 !(sockp->pcs_state & SBM_BVD2)) { 2368 sockp->pcs_state |= SBM_BVD2; 2369 PC_CALLBACK(pcic->dip, x, 2370 PCE_CARD_BATTERY_WARN, i); 2371 } 2372 2373 /* Battery Dead Detect */ 2374 if (value & PCIC_BD_DETECT) { 2375 /* 2376 * need to work out event if RI not enabled 2377 * and card_type == IF_IO 2378 */ 2379 if (card_type == IF_MEMORY && 2380 !(sockp->pcs_state & SBM_BVD1)) { 2381 sockp->pcs_state |= SBM_BVD1; 2382 PC_CALLBACK(pcic->dip, x, 2383 PCE_CARD_BATTERY_DEAD, 2384 i); 2385 } else { 2386 /* 2387 * information in pin replacement 2388 * register if one is available 2389 */ 2390 PC_CALLBACK(pcic->dip, x, 2391 PCE_CARD_STATUS_CHANGE, 2392 i); 2393 } /* IF_MEMORY */ 2394 } /* PCIC_BD_DETECT */ 2395 } /* if pcic_change */ 2396 /* 2397 * for any controllers that we can detect whether a socket 2398 * had an interrupt for the PC Card, we should sort that out 2399 * here. 2400 */ 2401 } /* for pc_numsockets */ 2402 2403 /* 2404 * If we're on a PCI bus, we may need to cycle through each IO 2405 * interrupt handler that is registered since they all 2406 * share the same interrupt line. 2407 */ 2408 2409 2410 #if defined(PCIC_DEBUG) 2411 pcic_err(pcic->dip, 0xf, 2412 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2413 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2414 #endif 2415 2416 if (io_ints) { 2417 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED) 2418 ret = DDI_INTR_CLAIMED; 2419 } 2420 2421 mutex_exit(&pcic->intr_lock); 2422 2423 #if defined(PCIC_DEBUG) 2424 pcic_err(pcic->dip, 0xf, 2425 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2426 ret, value, DDI_INTR_CLAIMED); 2427 #endif 2428 2429 return (ret); 2430 } 2431 2432 /* 2433 * pcic_change() 2434 * check to see if this socket had a change in state 2435 * by checking the status change register 2436 */ 2437 static int 2438 pcic_change(pcicdev_t *pcic, int socket) 2439 { 2440 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2441 } 2442 2443 /* 2444 * pcic_do_io_intr - calls client interrupt handlers 2445 */ 2446 static int 2447 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2448 { 2449 inthandler_t *tmp; 2450 int ret = DDI_INTR_UNCLAIMED; 2451 2452 #if defined(PCIC_DEBUG) 2453 pcic_err(pcic->dip, 0xf, 2454 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2455 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2456 #endif 2457 2458 if (pcic->irq_top != NULL) { 2459 tmp = pcic->irq_current; 2460 2461 do { 2462 int cur = pcic->irq_current->socket; 2463 pcic_socket_t *sockp = 2464 &pcic->pc_sockets[cur]; 2465 2466 #if defined(PCIC_DEBUG) 2467 pcic_err(pcic->dip, 0xf, 2468 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2469 sockp->pcs_flags, PCS_CARD_PRESENT); 2470 pcic_err(pcic->dip, 0xf, 2471 "\t sockets=%d cur=%d intr=%p arg1=%p " 2472 "arg2=%p\n", 2473 sockets, cur, (void *)pcic->irq_current->intr, 2474 pcic->irq_current->arg1, 2475 pcic->irq_current->arg2); 2476 #endif 2477 if ((sockp->pcs_flags & PCS_CARD_PRESENT) && 2478 !(sockp->pcs_flags & PCS_DEBOUNCING) && 2479 (sockets & (1 << cur))) { 2480 2481 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2482 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2483 ret = DDI_INTR_CLAIMED; 2484 2485 #if defined(PCIC_DEBUG) 2486 pcic_err(pcic->dip, 0xf, 2487 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2488 ret, DDI_INTR_CLAIMED); 2489 #endif 2490 } 2491 2492 2493 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2494 pcic->irq_current = pcic->irq_top; 2495 2496 } while (pcic->irq_current != tmp); 2497 2498 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2499 pcic->irq_current = pcic->irq_top; 2500 2501 } else { 2502 ret = DDI_INTR_UNCLAIMED; 2503 } 2504 2505 #if defined(PCIC_DEBUG) 2506 pcic_err(pcic->dip, 0xf, 2507 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2508 ret, DDI_INTR_CLAIMED); 2509 #endif 2510 2511 return (ret); 2512 2513 } 2514 2515 /* 2516 * pcic_inquire_adapter() 2517 * SocketServices InquireAdapter function 2518 * get characteristics of the physical adapter 2519 */ 2520 /*ARGSUSED*/ 2521 static int 2522 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2523 { 2524 anp_t *anp = ddi_get_driver_private(dip); 2525 pcicdev_t *pcic = anp->an_private; 2526 2527 config->NumSockets = pcic->pc_numsockets; 2528 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2529 config->NumEDCs = 0; 2530 config->AdpCaps = 0; 2531 config->ActiveHigh = 0; 2532 config->ActiveLow = PCIC_AVAIL_IRQS; 2533 config->NumPower = pcic->pc_numpower; 2534 config->power_entry = pcic->pc_power; /* until we resolve this */ 2535 #if defined(PCIC_DEBUG) 2536 if (pcic_debug) { 2537 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2538 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2539 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2540 } 2541 #endif 2542 config->ResourceFlags = 0; 2543 switch (pcic->pc_intr_mode) { 2544 case PCIC_INTR_MODE_PCI_1: 2545 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2546 RES_IRQ_SHAREABLE; 2547 break; 2548 } 2549 return (SUCCESS); 2550 } 2551 2552 /* 2553 * pcic_callback() 2554 * The PCMCIA nexus calls us via this function 2555 * in order to set the callback function we are 2556 * to call the nexus with 2557 */ 2558 /*ARGSUSED*/ 2559 static int 2560 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2561 { 2562 anp_t *anp = ddi_get_driver_private(dip); 2563 pcicdev_t *pcic = anp->an_private; 2564 2565 if (handler != NULL) { 2566 pcic->pc_callback = handler; 2567 pcic->pc_cb_arg = arg; 2568 pcic->pc_flags |= PCF_CALLBACK; 2569 } else { 2570 pcic->pc_callback = NULL; 2571 pcic->pc_cb_arg = 0; 2572 pcic->pc_flags &= ~PCF_CALLBACK; 2573 } 2574 /* 2575 * we're now registered with the nexus 2576 * it is acceptable to do callbacks at this point. 2577 * don't call back from here though since it could block 2578 */ 2579 return (PC_SUCCESS); 2580 } 2581 2582 /* 2583 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2584 * calculate the speed bits from the specified memory speed 2585 * there may be more to do here 2586 */ 2587 2588 static int 2589 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2590 { 2591 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2592 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2593 2594 switch (pcic->pc_type) { 2595 case PCIC_I82365SL: 2596 case PCIC_VADEM: 2597 case PCIC_VADEM_VG469: 2598 default: 2599 /* Intel chip wants it in waitstates */ 2600 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2601 if (speed <= wspeed) 2602 wspeed = 0; 2603 else if (speed <= (wspeed += mhztons(bspeed))) 2604 wspeed = 1; 2605 else if (speed <= (wspeed += mhztons(bspeed))) 2606 wspeed = 2; 2607 else 2608 wspeed = 3; 2609 wspeed <<= 6; /* put in right bit positions */ 2610 break; 2611 2612 case PCIC_INTEL_i82092: 2613 wspeed = SYSMEM_82092_80NS; 2614 if (speed > 80) 2615 wspeed = SYSMEM_82092_100NS; 2616 if (speed > 100) 2617 wspeed = SYSMEM_82092_150NS; 2618 if (speed > 150) 2619 wspeed = SYSMEM_82092_200NS; 2620 if (speed > 200) 2621 wspeed = SYSMEM_82092_250NS; 2622 if (speed > 250) 2623 wspeed = SYSMEM_82092_600NS; 2624 wspeed <<= 5; /* put in right bit positions */ 2625 break; 2626 2627 } /* switch */ 2628 2629 return (wspeed); 2630 } 2631 2632 /* 2633 * These values are taken from the PC Card Standard Electrical Specification. 2634 * Generally the larger value is taken if 2 are possible. 2635 */ 2636 static struct pcic_card_times { 2637 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2638 uint16_t setup; /* Corresponding address setup time. */ 2639 uint16_t width; /* Corresponding width, OE or WE. */ 2640 uint16_t hold; /* Corresponding data or address hold time. */ 2641 } pcic_card_times[] = { 2642 2643 /* 2644 * Note: The rounded up times for 250, 200 & 150 have been increased 2645 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2646 * See BugID 00663. 2647 */ 2648 2649 /* 2650 * Rounded up times Original times from 2651 * that add up to the the PCMCIA Spec. 2652 * cycle time. 2653 */ 2654 {600, 180, 370, 140}, /* 100, 300, 70 */ 2655 {400, 120, 300, 90}, /* Made this one up */ 2656 {250, 100, 190, 70}, /* 30, 150, 30 */ 2657 {200, 80, 170, 70}, /* 20, 120, 30 */ 2658 {150, 50, 110, 40}, /* 20, 80, 20 */ 2659 {100, 40, 80, 40}, /* 10, 60, 15 */ 2660 {0, 10, 60, 15} /* 10, 60, 15 */ 2661 }; 2662 2663 /* 2664 * pcic_set_cdtimers 2665 * This is specific to several Cirrus Logic chips 2666 */ 2667 static void 2668 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2669 { 2670 int cmd, set, rec, offset, clk_pulse; 2671 struct pcic_card_times *ctp; 2672 2673 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2674 offset = 3; 2675 else 2676 offset = 0; 2677 2678 clk_pulse = mhztons(pcic->bus_speed); 2679 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++); 2680 2681 /* 2682 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2683 */ 2684 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2685 if (set < 0) 2686 set = 0; 2687 2688 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2689 if (cmd < 0) 2690 cmd = 0; 2691 2692 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2693 if (rec < 0) 2694 rec = 0; 2695 2696 #if defined(PCIC_DEBUG) 2697 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2698 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2699 (unsigned)speed, offset == 3 ? 1 : 0, 2700 ctp->cycle, clk_pulse, cmd, set, rec); 2701 #endif 2702 2703 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2704 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2705 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2706 } 2707 2708 /* 2709 * pcic_set_window 2710 * essentially the same as the Socket Services specification 2711 * We use socket and not adapter since they are identifiable 2712 * but the rest is the same 2713 * 2714 * dip pcic driver's device information 2715 * window parameters for the request 2716 */ 2717 static int 2718 pcic_set_window(dev_info_t *dip, set_window_t *window) 2719 { 2720 anp_t *anp = ddi_get_driver_private(dip); 2721 pcicdev_t *pcic = anp->an_private; 2722 int select; 2723 int socket, pages, which, ret; 2724 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2725 ra_return_t res; 2726 ndi_ra_request_t req; 2727 uint32_t base = window->base; 2728 2729 #if defined(PCIC_DEBUG) 2730 if (pcic_debug) { 2731 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2732 cmn_err(CE_CONT, 2733 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2734 window->window, window->socket, window->WindowSize, 2735 window->speed); 2736 cmn_err(CE_CONT, 2737 "\tbase=%x, state=%x\n", (unsigned)window->base, 2738 (unsigned)window->state); 2739 } 2740 #endif 2741 2742 /* 2743 * do some basic sanity checking on what we support 2744 * we don't do paged mode 2745 */ 2746 if (window->state & WS_PAGED) { 2747 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2748 return (BAD_ATTRIBUTE); 2749 } 2750 2751 /* 2752 * we don't care about previous mappings. 2753 * Card Services will deal with that so don't 2754 * even check 2755 */ 2756 2757 socket = window->socket; 2758 2759 if (!(window->state & WS_IO)) { 2760 int win, tmp; 2761 pcs_memwin_t *memp; 2762 #if defined(PCIC_DEBUG) 2763 if (pcic_debug) 2764 cmn_err(CE_CONT, "\twindow type is memory\n"); 2765 #endif 2766 /* this is memory window mapping */ 2767 win = window->window % PCIC_NUMWINSOCK; 2768 tmp = window->window / PCIC_NUMWINSOCK; 2769 2770 /* only windows 2-6 can do memory mapping */ 2771 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2772 cmn_err(CE_CONT, 2773 "\tattempt to map to non-mem window\n"); 2774 return (BAD_WINDOW); 2775 } 2776 2777 if (window->WindowSize == 0) 2778 window->WindowSize = MEM_MIN; 2779 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2780 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2781 return (BAD_SIZE); 2782 } 2783 2784 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2785 2786 memp = &sockp->pcs_windows[win].mem; 2787 memp->pcw_speed = window->speed; 2788 2789 win -= PCIC_IOWINDOWS; /* put in right range */ 2790 2791 if (window->WindowSize != memp->pcw_len) 2792 which = memp->pcw_len; 2793 else 2794 which = 0; 2795 2796 if (window->state & WS_ENABLED) { 2797 uint32_t wspeed; 2798 #if defined(PCIC_DEBUG) 2799 if (pcic_debug) { 2800 cmn_err(CE_CONT, 2801 "\tbase=%x, win=%d\n", (unsigned)base, 2802 win); 2803 if (which) 2804 cmn_err(CE_CONT, 2805 "\tneed to remap window\n"); 2806 } 2807 #endif 2808 2809 if (which && (memp->pcw_status & PCW_MAPPED)) { 2810 ddi_regs_map_free(&memp->pcw_handle); 2811 res.ra_addr_lo = memp->pcw_base; 2812 res.ra_len = memp->pcw_len; 2813 (void) pcmcia_free_mem(dip, &res); 2814 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2815 memp->pcw_hostmem = NULL; 2816 memp->pcw_base = NULL; 2817 memp->pcw_len = 0; 2818 } 2819 2820 which = window->WindowSize >> PAGE_SHIFT; 2821 2822 if (!(memp->pcw_status & PCW_MAPPED)) { 2823 ret = 0; 2824 2825 memp->pcw_base = base; 2826 bzero(&req, sizeof (req)); 2827 req.ra_len = which << PAGE_SHIFT; 2828 req.ra_addr = (uint64_t)memp->pcw_base; 2829 req.ra_boundbase = pcic->pc_base; 2830 req.ra_boundlen = pcic->pc_bound; 2831 req.ra_flags = (memp->pcw_base ? 2832 NDI_RA_ALLOC_SPECIFIED : 0) | 2833 NDI_RA_ALLOC_BOUNDED; 2834 req.ra_align_mask = 2835 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2836 #if defined(PCIC_DEBUG) 2837 pcic_err(dip, 8, 2838 "\tlen 0x%"PRIx64 2839 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2840 " blen 0x%"PRIx64" flags 0x%x" 2841 " algn 0x%"PRIx64"\n", 2842 req.ra_len, req.ra_addr, 2843 req.ra_boundbase, 2844 req.ra_boundlen, req.ra_flags, 2845 req.ra_align_mask); 2846 #endif 2847 2848 ret = pcmcia_alloc_mem(dip, &req, &res); 2849 if (ret == DDI_FAILURE) { 2850 mutex_exit(&pcic->pc_lock); 2851 cmn_err(CE_WARN, 2852 "\tpcmcia_alloc_mem() failed\n"); 2853 return (BAD_SIZE); 2854 } 2855 memp->pcw_base = res.ra_addr_lo; 2856 base = memp->pcw_base; 2857 2858 #if defined(PCIC_DEBUG) 2859 if (pcic_debug) 2860 cmn_err(CE_CONT, 2861 "\tsetwindow: new base=%x\n", 2862 (unsigned)memp->pcw_base); 2863 #endif 2864 memp->pcw_len = window->WindowSize; 2865 2866 which = pcmcia_map_reg(pcic->dip, 2867 window->child, 2868 &res, 2869 (uint32_t)(window->state & 2870 0xffff) | 2871 (window->socket << 16), 2872 (caddr_t *)&memp->pcw_hostmem, 2873 &memp->pcw_handle, 2874 &window->attr, NULL); 2875 2876 if (which != DDI_SUCCESS) { 2877 2878 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2879 "failed\n"); 2880 2881 res.ra_addr_lo = memp->pcw_base; 2882 res.ra_len = memp->pcw_len; 2883 (void) pcmcia_free_mem(pcic->dip, &res); 2884 2885 mutex_exit(&pcic->pc_lock); 2886 2887 return (BAD_WINDOW); 2888 } 2889 memp->pcw_status |= PCW_MAPPED; 2890 #if defined(PCIC_DEBUG) 2891 if (pcic_debug) 2892 cmn_err(CE_CONT, 2893 "\tmap=%x, hostmem=%p\n", 2894 which, 2895 (void *)memp->pcw_hostmem); 2896 #endif 2897 } else { 2898 base = memp->pcw_base; 2899 } 2900 2901 /* report the handle back to caller */ 2902 window->handle = memp->pcw_handle; 2903 2904 #if defined(PCIC_DEBUG) 2905 if (pcic_debug) { 2906 cmn_err(CE_CONT, 2907 "\twindow mapped to %x@%x len=%d\n", 2908 (unsigned)window->base, 2909 (unsigned)memp->pcw_base, 2910 memp->pcw_len); 2911 } 2912 #endif 2913 2914 /* find the register set offset */ 2915 select = win * PCIC_MEM_1_OFFSET; 2916 #if defined(PCIC_DEBUG) 2917 if (pcic_debug) 2918 cmn_err(CE_CONT, "\tselect=%x\n", select); 2919 #endif 2920 2921 /* 2922 * at this point, the register window indicator has 2923 * been converted to be an offset from the first 2924 * set of registers that are used for programming 2925 * the window mapping and the offset used to select 2926 * the correct set of registers to access the 2927 * specified socket. This allows basing everything 2928 * off the _0 window 2929 */ 2930 2931 /* map the physical page base address */ 2932 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2933 which |= (window->speed <= MEM_SPEED_MIN) ? 2934 SYSMEM_ZERO_WAIT : 0; 2935 2936 /* need to select register set */ 2937 select = PCIC_MEM_1_OFFSET * win; 2938 2939 pcic_putb(pcic, socket, 2940 PCIC_SYSMEM_0_STARTLOW + select, 2941 SYSMEM_LOW(base)); 2942 pcic_putb(pcic, socket, 2943 PCIC_SYSMEM_0_STARTHI + select, 2944 SYSMEM_HIGH(base) | which); 2945 2946 /* 2947 * Some adapters can decode window addresses greater 2948 * than 16-bits worth, so handle them here. 2949 */ 2950 switch (pcic->pc_type) { 2951 case PCIC_INTEL_i82092: 2952 pcic_putb(pcic, socket, 2953 PCIC_82092_CPAGE, 2954 SYSMEM_EXT(base)); 2955 break; 2956 case PCIC_CL_PD6729: 2957 case PCIC_CL_PD6730: 2958 clext_reg_write(pcic, socket, 2959 PCIC_CLEXT_MMAP0_UA + win, 2960 SYSMEM_EXT(base)); 2961 break; 2962 case PCIC_TI_PCI1130: 2963 /* 2964 * Note that the TI chip has one upper byte 2965 * per socket so all windows get bound to a 2966 * 16MB segment. This must be detected and 2967 * handled appropriately. We can detect that 2968 * it is done by seeing if the pc_base has 2969 * changed and changing when the register 2970 * is first set. This will force the bounds 2971 * to be correct. 2972 */ 2973 if (pcic->pc_bound == 0xffffffff) { 2974 pcic_putb(pcic, socket, 2975 PCIC_TI_WINDOW_PAGE_PCI, 2976 SYSMEM_EXT(base)); 2977 pcic->pc_base = SYSMEM_EXT(base) << 24; 2978 pcic->pc_bound = 0x1000000; 2979 } 2980 break; 2981 case PCIC_TI_PCI1031: 2982 case PCIC_TI_PCI1131: 2983 case PCIC_TI_PCI1250: 2984 case PCIC_TI_PCI1225: 2985 case PCIC_TI_PCI1221: 2986 case PCIC_SMC_34C90: 2987 case PCIC_CL_PD6832: 2988 case PCIC_RICOH_RL5C466: 2989 case PCIC_TI_PCI1410: 2990 case PCIC_ENE_1410: 2991 case PCIC_TI_PCI1510: 2992 case PCIC_TI_PCI1520: 2993 case PCIC_O2_OZ6912: 2994 case PCIC_TI_PCI1420: 2995 case PCIC_ENE_1420: 2996 case PCIC_TI_VENDOR: 2997 case PCIC_TOSHIBA_TOPIC100: 2998 case PCIC_TOSHIBA_TOPIC95: 2999 case PCIC_TOSHIBA_VENDOR: 3000 case PCIC_RICOH_VENDOR: 3001 case PCIC_O2MICRO_VENDOR: 3002 pcic_putb(pcic, socket, 3003 PCIC_YENTA_MEM_PAGE + win, 3004 SYSMEM_EXT(base)); 3005 break; 3006 default: 3007 cmn_err(CE_NOTE, "pcic_set_window: unknown " 3008 "cardbus vendor:0x%X\n", 3009 pcic->pc_type); 3010 pcic_putb(pcic, socket, 3011 PCIC_YENTA_MEM_PAGE + win, 3012 SYSMEM_EXT(base)); 3013 3014 break; 3015 } /* switch */ 3016 3017 /* 3018 * specify the length of the mapped range 3019 * we convert to pages (rounding up) so that 3020 * the hardware gets the right thing 3021 */ 3022 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 3023 3024 /* 3025 * Setup this window's timing. 3026 */ 3027 switch (pcic->pc_type) { 3028 case PCIC_CL_PD6729: 3029 case PCIC_CL_PD6730: 3030 case PCIC_CL_PD6710: 3031 case PCIC_CL_PD6722: 3032 wspeed = SYSMEM_CLTIMER_SET_0; 3033 pcic_set_cdtimers(pcic, socket, 3034 window->speed, 3035 wspeed); 3036 break; 3037 3038 case PCIC_INTEL_i82092: 3039 default: 3040 wspeed = pcic_calc_speed(pcic, window->speed); 3041 break; 3042 } /* switch */ 3043 3044 #if defined(PCIC_DEBUG) 3045 if (pcic_debug) 3046 cmn_err(CE_CONT, 3047 "\twindow %d speed bits = %x for " 3048 "%dns\n", 3049 win, (unsigned)wspeed, window->speed); 3050 #endif 3051 3052 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 3053 SYSMEM_LOW(base + 3054 (pages * PCIC_PAGE)-1)); 3055 3056 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 3057 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 3058 wspeed); 3059 3060 /* 3061 * now map the card's memory pages - we start with page 3062 * 0 3063 * we also default to AM -- set page might change it 3064 */ 3065 base = memp->pcw_base; 3066 pcic_putb(pcic, socket, 3067 PCIC_CARDMEM_0_LOW + select, 3068 CARDMEM_LOW(0 - (uint32_t)base)); 3069 3070 pcic_putb(pcic, socket, 3071 PCIC_CARDMEM_0_HI + select, 3072 CARDMEM_HIGH(0 - (uint32_t)base) | 3073 CARDMEM_REG_ACTIVE); 3074 3075 /* 3076 * enable the window even though redundant 3077 * and SetPage may do it again. 3078 */ 3079 select = pcic_getb(pcic, socket, 3080 PCIC_MAPPING_ENABLE); 3081 select |= SYSMEM_WINDOW(win); 3082 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3083 memp->pcw_offset = 0; 3084 memp->pcw_status |= PCW_ENABLED; 3085 } else { 3086 /* 3087 * not only do we unmap the memory, the 3088 * window has been turned off. 3089 */ 3090 if (which && memp->pcw_status & PCW_MAPPED) { 3091 ddi_regs_map_free(&memp->pcw_handle); 3092 res.ra_addr_lo = memp->pcw_base; 3093 res.ra_len = memp->pcw_len; 3094 (void) pcmcia_free_mem(pcic->dip, &res); 3095 memp->pcw_hostmem = NULL; 3096 memp->pcw_status &= ~PCW_MAPPED; 3097 } 3098 3099 /* disable current mapping */ 3100 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3101 select &= ~SYSMEM_WINDOW(win); 3102 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3103 memp->pcw_status &= ~PCW_ENABLED; 3104 } 3105 memp->pcw_len = window->WindowSize; 3106 window->handle = memp->pcw_handle; 3107 #if defined(PCIC_DEBUG) 3108 if (pcic_debug) 3109 xxdmp_all_regs(pcic, window->socket, -1); 3110 #endif 3111 } else { 3112 /* 3113 * This is a request for an IO window 3114 */ 3115 int win, tmp; 3116 pcs_iowin_t *winp; 3117 /* I/O windows */ 3118 #if defined(PCIC_DEBUG) 3119 if (pcic_debug) 3120 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3121 #endif 3122 3123 /* only windows 0 and 1 can do I/O */ 3124 win = window->window % PCIC_NUMWINSOCK; 3125 tmp = window->window / PCIC_NUMWINSOCK; 3126 3127 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3128 cmn_err(CE_WARN, 3129 "\twindow is out of range (%d)\n", 3130 window->window); 3131 return (BAD_WINDOW); 3132 } 3133 3134 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3135 3136 winp = &sockp->pcs_windows[win].io; 3137 winp->pcw_speed = window->speed; 3138 if (window->WindowSize != 1 && window->WindowSize & 1) { 3139 /* we don't want an odd-size window */ 3140 window->WindowSize++; 3141 } 3142 winp->pcw_len = window->WindowSize; 3143 3144 if (window->state & WS_ENABLED) { 3145 if (winp->pcw_status & PCW_MAPPED) { 3146 ddi_regs_map_free(&winp->pcw_handle); 3147 res.ra_addr_lo = winp->pcw_base; 3148 res.ra_len = winp->pcw_len; 3149 (void) pcmcia_free_io(pcic->dip, &res); 3150 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3151 } 3152 3153 /* 3154 * if the I/O address wasn't allocated, allocate 3155 * it now. If it was allocated, it better 3156 * be free to use. 3157 * The winp->pcw_offset value is set and used 3158 * later on if the particular adapter 3159 * that we're running on has the ability 3160 * to translate IO accesses to the card 3161 * (such as some adapters in the Cirrus 3162 * Logic family). 3163 */ 3164 winp->pcw_offset = 0; 3165 3166 /* 3167 * Setup the request parameters for the 3168 * requested base and length. If 3169 * we're on an adapter that has 3170 * IO window offset registers, then 3171 * we don't need a specific base 3172 * address, just a length, and then 3173 * we'll cause the correct IO address 3174 * to be generated on the socket by 3175 * setting up the IO window offset 3176 * registers. 3177 * For adapters that support this capability, we 3178 * always use the IO window offset registers, 3179 * even if the passed base/length would be in 3180 * range. 3181 */ 3182 base = window->base; 3183 bzero(&req, sizeof (req)); 3184 req.ra_len = window->WindowSize; 3185 3186 req.ra_addr = (uint64_t) 3187 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3188 req.ra_flags = (req.ra_addr) ? 3189 NDI_RA_ALLOC_SPECIFIED : 0; 3190 3191 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3192 /* need to rethink this */ 3193 req.ra_boundbase = pcic->pc_iobase; 3194 req.ra_boundlen = pcic->pc_iobound; 3195 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3196 3197 #if defined(PCIC_DEBUG) 3198 pcic_err(dip, 8, 3199 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3200 "bbase 0x%"PRIx64 3201 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3202 PRIx64"\n", 3203 req.ra_len, (uint64_t)req.ra_addr, 3204 req.ra_boundbase, 3205 req.ra_boundlen, req.ra_flags, 3206 req.ra_align_mask); 3207 #endif 3208 3209 /* 3210 * Try to allocate the space. If we fail this, 3211 * return the appropriate error depending 3212 * on whether the caller specified a 3213 * specific base address or not. 3214 */ 3215 if (pcmcia_alloc_io(dip, &req, &res) == DDI_FAILURE) { 3216 winp->pcw_status &= ~PCW_ENABLED; 3217 mutex_exit(&pcic->pc_lock); 3218 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3219 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3220 "bbase 0x%" PRIx64 3221 "blen 0x%" PRIx64 "flags 0x%x" 3222 "algn 0x%" PRIx64 "\n", 3223 req.ra_len, req.ra_addr, 3224 req.ra_boundbase, 3225 req.ra_boundlen, req.ra_flags, 3226 req.ra_align_mask); 3227 3228 return (base?BAD_BASE:BAD_SIZE); 3229 } /* pcmcia_alloc_io */ 3230 3231 /* 3232 * Don't change the original base. Either we use 3233 * the offset registers below (PCF_IO_REMAP is set) 3234 * or it was allocated correctly anyway. 3235 */ 3236 winp->pcw_base = res.ra_addr_lo; 3237 3238 #if defined(PCIC_DEBUG) 3239 pcic_err(dip, 8, 3240 "\tsetwindow: new base=%x orig base 0x%x\n", 3241 (unsigned)winp->pcw_base, base); 3242 #endif 3243 3244 if ((which = pcmcia_map_reg(pcic->dip, 3245 window->child, 3246 &res, 3247 (uint32_t)(window->state & 3248 0xffff) | 3249 (window->socket << 16), 3250 (caddr_t *)&winp->pcw_hostmem, 3251 &winp->pcw_handle, 3252 &window->attr, 3253 base)) != DDI_SUCCESS) { 3254 3255 cmn_err(CE_WARN, "pcmcia_map_reg()" 3256 "failed\n"); 3257 3258 res.ra_addr_lo = winp->pcw_base; 3259 res.ra_len = winp->pcw_len; 3260 (void) pcmcia_free_io(pcic->dip, &res); 3261 3262 mutex_exit(&pcic->pc_lock); 3263 return (BAD_WINDOW); 3264 } 3265 3266 window->handle = winp->pcw_handle; 3267 winp->pcw_status |= PCW_MAPPED; 3268 3269 /* find the register set offset */ 3270 select = win * PCIC_IO_OFFSET; 3271 3272 #if defined(PCIC_DEBUG) 3273 if (pcic_debug) { 3274 cmn_err(CE_CONT, 3275 "\tenable: window=%d, select=%x, " 3276 "base=%x, handle=%p\n", 3277 win, select, 3278 (unsigned)window->base, 3279 (void *)window->handle); 3280 } 3281 #endif 3282 /* 3283 * at this point, the register window indicator has 3284 * been converted to be an offset from the first 3285 * set of registers that are used for programming 3286 * the window mapping and the offset used to select 3287 * the correct set of registers to access the 3288 * specified socket. This allows basing everything 3289 * off the _0 window 3290 */ 3291 3292 /* map the I/O base in */ 3293 pcic_putb(pcic, socket, 3294 PCIC_IO_ADDR_0_STARTLOW + select, 3295 LOW_BYTE((uint32_t)winp->pcw_base)); 3296 pcic_putb(pcic, socket, 3297 PCIC_IO_ADDR_0_STARTHI + select, 3298 HIGH_BYTE((uint32_t)winp->pcw_base)); 3299 3300 pcic_putb(pcic, socket, 3301 PCIC_IO_ADDR_0_STOPLOW + select, 3302 LOW_BYTE((uint32_t)winp->pcw_base + 3303 window->WindowSize - 1)); 3304 pcic_putb(pcic, socket, 3305 PCIC_IO_ADDR_0_STOPHI + select, 3306 HIGH_BYTE((uint32_t)winp->pcw_base + 3307 window->WindowSize - 1)); 3308 3309 /* 3310 * We've got the requested IO space, now see if we 3311 * need to adjust the IO window offset registers 3312 * so that the correct IO address is generated 3313 * at the socket. If this window doesn't have 3314 * this capability, then we're all done setting 3315 * up the IO resources. 3316 */ 3317 if (pcic->pc_flags & PCF_IO_REMAP) { 3318 3319 3320 /* 3321 * Note that only 16 bits are used to program 3322 * the registers but leave 32 bits on pcw_offset 3323 * so that we can generate the original base 3324 * in get_window() 3325 */ 3326 winp->pcw_offset = (base - winp->pcw_base); 3327 3328 pcic_putb(pcic, socket, 3329 PCIC_IO_OFFSET_LOW + 3330 (win * PCIC_IO_OFFSET_OFFSET), 3331 winp->pcw_offset & 0x0ff); 3332 pcic_putb(pcic, socket, 3333 PCIC_IO_OFFSET_HI + 3334 (win * PCIC_IO_OFFSET_OFFSET), 3335 (winp->pcw_offset >> 8) & 0x0ff); 3336 3337 } /* PCF_IO_REMAP */ 3338 3339 /* now get the other details (size, etc) right */ 3340 3341 /* 3342 * Set the data size control bits here. Most of the 3343 * adapters will ignore IOMEM_16BIT when 3344 * IOMEM_IOCS16 is set, except for the Intel 3345 * 82092, which only pays attention to the 3346 * IOMEM_16BIT bit. Sigh... Intel can't even 3347 * make a proper clone of their own chip. 3348 * The 82092 also apparently can't set the timing 3349 * of I/O windows. 3350 */ 3351 which = (window->state & WS_16BIT) ? 3352 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3353 3354 switch (pcic->pc_type) { 3355 case PCIC_CL_PD6729: 3356 case PCIC_CL_PD6730: 3357 case PCIC_CL_PD6710: 3358 case PCIC_CL_PD6722: 3359 case PCIC_CL_PD6832: 3360 /* 3361 * Select Timer Set 1 - this will take 3362 * effect when the PCIC_IO_CONTROL 3363 * register is written to later on; 3364 * the call to pcic_set_cdtimers 3365 * just sets up the timer itself. 3366 */ 3367 which |= IOMEM_CLTIMER_SET_1; 3368 pcic_set_cdtimers(pcic, socket, 3369 window->speed, 3370 IOMEM_CLTIMER_SET_1); 3371 which |= IOMEM_IOCS16; 3372 break; 3373 case PCIC_TI_PCI1031: 3374 3375 if (window->state & WS_16BIT) 3376 which |= IOMEM_WAIT16; 3377 3378 break; 3379 case PCIC_TI_PCI1130: 3380 3381 if (window->state & WS_16BIT) 3382 which |= IOMEM_WAIT16; 3383 3384 break; 3385 case PCIC_INTEL_i82092: 3386 break; 3387 default: 3388 if (window->speed > 3389 mhztons(pcic->bus_speed) * 3) 3390 which |= IOMEM_WAIT16; 3391 #ifdef notdef 3392 if (window->speed < 3393 mhztons(pcic->bus_speed) * 6) 3394 which |= IOMEM_ZERO_WAIT; 3395 #endif 3396 break; 3397 } /* switch (pc_type) */ 3398 3399 /* 3400 * Setup the data width and timing 3401 */ 3402 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3403 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3404 select |= IOMEM_SETWIN(win, which); 3405 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3406 3407 /* 3408 * Enable the IO window 3409 */ 3410 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3411 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3412 select | IOMEM_WINDOW(win)); 3413 3414 winp->pcw_status |= PCW_ENABLED; 3415 3416 #if defined(PCIC_DEBUG) 3417 if (pcic_debug) { 3418 cmn_err(CE_CONT, 3419 "\twhich = %x, select = %x (%x)\n", 3420 which, select, 3421 IOMEM_SETWIN(win, which)); 3422 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3423 } 3424 #endif 3425 } else { 3426 /* 3427 * not only do we unmap the IO space, the 3428 * window has been turned off. 3429 */ 3430 if (winp->pcw_status & PCW_MAPPED) { 3431 ddi_regs_map_free(&winp->pcw_handle); 3432 res.ra_addr_lo = winp->pcw_base; 3433 res.ra_len = winp->pcw_len; 3434 (void) pcmcia_free_io(pcic->dip, &res); 3435 winp->pcw_status &= ~PCW_MAPPED; 3436 } 3437 3438 /* disable current mapping */ 3439 select = pcic_getb(pcic, socket, 3440 PCIC_MAPPING_ENABLE); 3441 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3442 select &= ~IOMEM_WINDOW(win)); 3443 winp->pcw_status &= ~PCW_ENABLED; 3444 3445 winp->pcw_base = 0; 3446 winp->pcw_len = 0; 3447 winp->pcw_offset = 0; 3448 window->base = 0; 3449 /* now make sure we don't accidentally re-enable */ 3450 /* find the register set offset */ 3451 select = win * PCIC_IO_OFFSET; 3452 pcic_putb(pcic, socket, 3453 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3454 pcic_putb(pcic, socket, 3455 PCIC_IO_ADDR_0_STARTHI + select, 0); 3456 pcic_putb(pcic, socket, 3457 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3458 pcic_putb(pcic, socket, 3459 PCIC_IO_ADDR_0_STOPHI + select, 0); 3460 } 3461 } 3462 mutex_exit(&pcic->pc_lock); 3463 3464 return (SUCCESS); 3465 } 3466 3467 /* 3468 * pcic_card_state() 3469 * compute the instantaneous Card State information 3470 */ 3471 static int 3472 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3473 { 3474 int value, result; 3475 #if defined(PCIC_DEBUG) 3476 int orig_value; 3477 #endif 3478 3479 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3480 3481 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3482 3483 #if defined(PCIC_DEBUG) 3484 orig_value = value; 3485 if (pcic_debug >= 8) 3486 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3487 (void *)sockp, 3488 value, 3489 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3490 sockp->pcs_socket); 3491 #endif 3492 /* 3493 * Lie to socket services if we are not ready. 3494 * This is when we are starting up or during debounce timeouts 3495 * or if the card is a cardbus card. 3496 */ 3497 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3498 !sockp->pcs_debounce_id && 3499 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3500 result = SBM_CD; 3501 3502 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3503 result |= SBM_WP; 3504 if (value & PCIC_POWER_ON) { 3505 if (value & PCIC_READY) 3506 result |= SBM_RDYBSY; 3507 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3508 if (value & PCIC_BVD1) 3509 result |= SBM_BVD1; 3510 if (value & PCIC_BVD2) 3511 result |= SBM_BVD2; 3512 } 3513 } else 3514 result = 0; 3515 3516 mutex_exit(&pcic->pc_lock); 3517 3518 #if defined(PCIC_DEBUG) 3519 pcic_err(pcic->dip, 8, 3520 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3521 (void *) sockp, orig_value, 3522 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3523 sockp->pcs_socket, result); 3524 #endif 3525 3526 return (result); 3527 } 3528 3529 /* 3530 * pcic_set_page() 3531 * SocketServices SetPage function 3532 * set the page of PC Card memory that should be in the mapped 3533 * window 3534 */ 3535 /*ARGSUSED*/ 3536 static int 3537 pcic_set_page(dev_info_t *dip, set_page_t *page) 3538 { 3539 anp_t *anp = ddi_get_driver_private(dip); 3540 pcicdev_t *pcic = anp->an_private; 3541 int select; 3542 int which, socket, window; 3543 uint32_t base; 3544 pcs_memwin_t *memp; 3545 3546 /* get real socket/window numbers */ 3547 window = page->window % PCIC_NUMWINSOCK; 3548 socket = page->window / PCIC_NUMWINSOCK; 3549 3550 #if defined(PCIC_DEBUG) 3551 if (pcic_debug) { 3552 cmn_err(CE_CONT, 3553 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3554 window, socket, page->page); 3555 } 3556 #endif 3557 /* only windows 2-6 work on memory */ 3558 if (window < PCIC_IOWINDOWS) 3559 return (BAD_WINDOW); 3560 3561 /* only one page supported (but any size) */ 3562 if (page->page != 0) 3563 return (BAD_PAGE); 3564 3565 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3566 3567 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3568 window -= PCIC_IOWINDOWS; 3569 3570 #if defined(PCIC_DEBUG) 3571 if (pcic_debug) 3572 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3573 (uint32_t)memp->pcw_base, 3574 (void *)memp->pcw_hostmem, memp->pcw_len); 3575 #endif 3576 3577 /* window must be enabled */ 3578 if (!(memp->pcw_status & PCW_ENABLED)) 3579 return (BAD_ATTRIBUTE); 3580 3581 /* find the register set offset */ 3582 select = window * PCIC_MEM_1_OFFSET; 3583 #if defined(PCIC_DEBUG) 3584 if (pcic_debug) 3585 cmn_err(CE_CONT, "\tselect=%x\n", select); 3586 #endif 3587 3588 /* 3589 * now map the card's memory pages - we start with page 0 3590 */ 3591 3592 which = 0; /* assume simple case */ 3593 if (page->state & PS_ATTRIBUTE) { 3594 which |= CARDMEM_REG_ACTIVE; 3595 memp->pcw_status |= PCW_ATTRIBUTE; 3596 } else { 3597 memp->pcw_status &= ~PCW_ATTRIBUTE; 3598 } 3599 3600 /* 3601 * if caller says Write Protect, enforce it. 3602 */ 3603 if (page->state & PS_WP) { 3604 which |= CARDMEM_WRITE_PROTECT; 3605 memp->pcw_status |= PCW_WP; 3606 } else { 3607 memp->pcw_status &= ~PCW_WP; 3608 } 3609 #if defined(PCIC_DEBUG) 3610 if (pcic_debug) { 3611 cmn_err(CE_CONT, "\tmemory type = %s\n", 3612 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3613 if (which & CARDMEM_WRITE_PROTECT) 3614 cmn_err(CE_CONT, "\twrite protect\n"); 3615 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3616 (unsigned)page->offset, 3617 (unsigned)memp->pcw_base, 3618 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3619 } 3620 #endif 3621 /* address computation based on 64MB range and not larger */ 3622 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3623 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3624 CARDMEM_LOW((int)page->offset - (int)base)); 3625 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3626 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3627 CARDMEM_HIGH((int)page->offset - base) | which); 3628 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3629 3630 /* 3631 * while not really necessary, this just makes sure 3632 * nothing turned the window off behind our backs 3633 */ 3634 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3635 which |= SYSMEM_WINDOW(window); 3636 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3637 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3638 3639 memp->pcw_offset = (off_t)page->offset; 3640 3641 #if defined(PCIC_DEBUG) 3642 if (pcic_debug) { 3643 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3644 (void *)memp->pcw_hostmem, 3645 (uint32_t)*memp->pcw_hostmem); 3646 3647 xxdmp_all_regs(pcic, socket, -1); 3648 3649 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3650 (void *)memp->pcw_hostmem, 3651 (uint32_t)*memp->pcw_hostmem); 3652 } 3653 #endif 3654 3655 if (which & PCW_ATTRIBUTE) 3656 pcic_mswait(pcic, socket, 2); 3657 3658 mutex_exit(&pcic->pc_lock); 3659 3660 return (SUCCESS); 3661 } 3662 3663 /* 3664 * pcic_set_vcc_level() 3665 * 3666 * set voltage based on adapter information 3667 * 3668 * this routine implements a limited solution for support of 3.3v cards. 3669 * the general solution, which would fully support the pcmcia spec 3670 * as far as allowing client drivers to request which voltage levels 3671 * to be set, requires more framework support and driver changes - ess 3672 */ 3673 static int 3674 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3675 { 3676 uint32_t socket_present_state; 3677 3678 #if defined(PCIC_DEBUG) 3679 if (pcic_debug) { 3680 cmn_err(CE_CONT, 3681 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3682 (void *)pcic, socket->VccLevel); 3683 } 3684 #endif 3685 3686 /* 3687 * check VccLevel 3688 * if this is zero, power is being turned off 3689 * if it is non-zero, power is being turned on. 3690 */ 3691 if (socket->VccLevel == 0) { 3692 return (0); 3693 } 3694 3695 /* 3696 * range checking for sanity's sake 3697 */ 3698 if (socket->VccLevel >= pcic->pc_numpower) { 3699 return (BAD_VCC); 3700 } 3701 3702 switch (pcic->pc_io_type) { 3703 /* 3704 * Yenta-compliant adapters have vcc info in the extended registers 3705 * Other adapters can be added as needed, but the 'default' case 3706 * has been left as it was previously so as not to break existing 3707 * adapters. 3708 */ 3709 case PCIC_IO_TYPE_YENTA: 3710 /* 3711 * Here we ignore the VccLevel passed in and read the 3712 * card type from the adapter socket present state register 3713 */ 3714 socket_present_state = 3715 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3716 PCIC_PRESENT_STATE_REG)); 3717 #if defined(PCIC_DEBUG) 3718 if (pcic_debug) { 3719 cmn_err(CE_CONT, 3720 "socket present state = 0x%x\n", 3721 socket_present_state); 3722 } 3723 #endif 3724 switch (socket_present_state & PCIC_VCC_MASK) { 3725 case PCIC_VCC_3VCARD: 3726 /* fall through */ 3727 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3728 socket->VccLevel = PCIC_VCC_3VLEVEL; 3729 return 3730 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3731 case PCIC_VCC_5VCARD: 3732 socket->VccLevel = PCIC_VCC_5VLEVEL; 3733 return 3734 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3735 default: 3736 /* 3737 * if no card is present, this can be the 3738 * case of a client making a SetSocket call 3739 * after card removal. In this case we return 3740 * the current power level 3741 */ 3742 return ((unsigned)ddi_get8(pcic->handle, 3743 pcic->ioaddr + CB_R2_OFFSET + 3744 PCIC_POWER_CONTROL)); 3745 } 3746 3747 default: 3748 3749 switch (socket->VccLevel) { 3750 case PCIC_VCC_3VLEVEL: 3751 return (BAD_VCC); 3752 case PCIC_VCC_5VLEVEL: 3753 /* enable Vcc */ 3754 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3755 default: 3756 return (BAD_VCC); 3757 } 3758 } 3759 } 3760 3761 3762 /* 3763 * pcic_set_socket() 3764 * Socket Services SetSocket call 3765 * sets basic socket configuration 3766 */ 3767 static int 3768 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3769 { 3770 anp_t *anp = ddi_get_driver_private(dip); 3771 pcicdev_t *pcic = anp->an_private; 3772 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3773 int irq, interrupt, mirq; 3774 int powerlevel = 0; 3775 int ind, value, orig_pwrctl; 3776 3777 #if defined(PCIC_DEBUG) 3778 if (pcic_debug) { 3779 cmn_err(CE_CONT, 3780 "pcic_set_socket(dip=%p, socket=%d)" 3781 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3782 socket->socket, socket->VccLevel, socket->Vpp1Level, 3783 socket->Vpp2Level); 3784 } 3785 #endif 3786 /* 3787 * check VccLevel, etc. before setting mutex 3788 * if this is zero, power is being turned off 3789 * if it is non-zero, power is being turned on. 3790 * the default case is to assume Vcc only. 3791 */ 3792 3793 /* this appears to be very implementation specific */ 3794 3795 if (socket->Vpp1Level != socket->Vpp2Level) 3796 return (BAD_VPP); 3797 3798 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3799 powerlevel = 0; 3800 sockp->pcs_vcc = 0; 3801 sockp->pcs_vpp1 = 0; 3802 sockp->pcs_vpp2 = 0; 3803 } else { 3804 #if defined(PCIC_DEBUG) 3805 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3806 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3807 #endif 3808 /* valid Vcc power level? */ 3809 if (socket->VccLevel >= pcic->pc_numpower) 3810 return (BAD_VCC); 3811 3812 switch (pcic_power[socket->VccLevel].PowerLevel) { 3813 case 33: /* 3.3V */ 3814 case 60: /* for bad CIS in Option GPRS card */ 3815 if (!(pcic->pc_flags & PCF_33VCAP)) { 3816 cmn_err(CE_WARN, 3817 "%s%d: Bad Request for 3.3V " 3818 "(Controller incapable)\n", 3819 ddi_get_name(pcic->dip), 3820 ddi_get_instance(pcic->dip)); 3821 return (BAD_VCC); 3822 } 3823 /* FALLTHROUGH */ 3824 case 50: /* 5V */ 3825 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3826 pcic_getcb(pcic, CB_PRESENT_STATE) & 3827 CB_PS_33VCARD) { 3828 /* 3829 * This is actually a 3.3V card. 3830 * Solaris Card Services 3831 * doesn't understand 3.3V 3832 * so we cheat and change 3833 * the setting to the one appropriate to 3.3V. 3834 * Note that this is the entry number 3835 * in the pcic_power[] array. 3836 */ 3837 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3838 } else 3839 sockp->pcs_vcc = socket->VccLevel; 3840 break; 3841 default: 3842 return (BAD_VCC); 3843 } 3844 3845 /* enable Vcc */ 3846 powerlevel = POWER_CARD_ENABLE; 3847 3848 #if defined(PCIC_DEBUG) 3849 if (pcic_debug) { 3850 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3851 socket->VccLevel, powerlevel); 3852 } 3853 #endif 3854 ind = 0; /* default index to 0 power */ 3855 if ((int)socket->Vpp1Level >= 0 && 3856 socket->Vpp1Level < pcic->pc_numpower) { 3857 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3858 & VPP1)) { 3859 return (BAD_VPP); 3860 } 3861 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3862 powerlevel |= pcic_vpp_levels[ind]; 3863 sockp->pcs_vpp1 = socket->Vpp1Level; 3864 } 3865 if ((int)socket->Vpp2Level >= 0 && 3866 socket->Vpp2Level < pcic->pc_numpower) { 3867 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3868 & VPP2)) { 3869 return (BAD_VPP); 3870 } 3871 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3872 powerlevel |= (pcic_vpp_levels[ind] << 2); 3873 sockp->pcs_vpp2 = socket->Vpp2Level; 3874 } 3875 3876 if (pcic->pc_flags & PCF_VPPX) { 3877 /* 3878 * this adapter doesn't allow separate Vpp1/Vpp2 3879 * if one is turned on, both are turned on and only 3880 * the Vpp1 bits should be set 3881 */ 3882 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3883 /* must be the same if one not zero */ 3884 if (sockp->pcs_vpp1 != 0 && 3885 sockp->pcs_vpp2 != 0) { 3886 cmn_err(CE_WARN, 3887 "%s%d: Bad Power Request " 3888 "(Vpp1/2 not the same)\n", 3889 ddi_get_name(pcic->dip), 3890 ddi_get_instance(pcic->dip)); 3891 return (BAD_VPP); 3892 } 3893 } 3894 powerlevel &= ~(3<<2); 3895 } 3896 3897 #if defined(PCIC_DEBUG) 3898 if (pcic_debug) { 3899 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3900 powerlevel, ind); 3901 } 3902 #endif 3903 } 3904 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3905 3906 /* turn socket->IREQRouting off while programming */ 3907 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3908 interrupt &= ~PCIC_INTR_MASK; 3909 if (pcic->pc_flags & PCF_USE_SMI) 3910 interrupt |= PCIC_INTR_ENABLE; 3911 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3912 3913 switch (pcic->pc_type) { 3914 case PCIC_INTEL_i82092: 3915 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3916 PCIC_82092_INT_DISABLE); 3917 break; 3918 default: 3919 break; 3920 } /* switch */ 3921 3922 /* the SCIntMask specifies events to detect */ 3923 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3924 3925 #if defined(PCIC_DEBUG) 3926 if (pcic_debug) 3927 cmn_err(CE_CONT, 3928 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3929 socket->SCIntMask, interrupt, mirq); 3930 #endif 3931 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3932 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3933 mirq & ~PCIC_CHANGE_MASK); 3934 3935 /* save the mask we want to use */ 3936 sockp->pcs_intmask = socket->SCIntMask; 3937 3938 /* 3939 * Until there is a card present it's not worth enabling 3940 * any interrupts except "Card detect". This is done 3941 * elsewhere in the driver so don't change things if 3942 * there is no card! 3943 */ 3944 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3945 3946 /* now update the hardware to reflect events desired */ 3947 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3948 mirq |= PCIC_BD_DETECT; 3949 3950 if (sockp->pcs_intmask & SBM_BVD2) 3951 mirq |= PCIC_BW_DETECT; 3952 3953 if (sockp->pcs_intmask & SBM_RDYBSY) 3954 mirq |= PCIC_RD_DETECT; 3955 3956 if (sockp->pcs_intmask & SBM_CD) 3957 mirq |= PCIC_CD_DETECT; 3958 } 3959 3960 if (sockp->pcs_flags & PCS_READY) { 3961 /* 3962 * card just came ready. 3963 * make sure enough time elapses 3964 * before touching it. 3965 */ 3966 sockp->pcs_flags &= ~PCS_READY; 3967 pcic_mswait(pcic, socket->socket, 10); 3968 } 3969 3970 #if defined(PCIC_DEBUG) 3971 if (pcic_debug) { 3972 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3973 } 3974 #endif 3975 3976 switch (pcic->pc_type) { 3977 case PCIC_I82365SL: 3978 case PCIC_VADEM: 3979 case PCIC_VADEM_VG469: 3980 /* 3981 * The Intel version has different options. This is a 3982 * special case of GPI which might be used for eject 3983 */ 3984 3985 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 3986 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 3987 pcic->pc_flags & PCF_GPI_EJECT) { 3988 irq |= PCIC_GPI_ENABLE; 3989 } else { 3990 irq &= ~PCIC_GPI_ENABLE; 3991 } 3992 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 3993 break; 3994 case PCIC_CL_PD6710: 3995 case PCIC_CL_PD6722: 3996 if (socket->IFType == IF_IO) { 3997 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 3998 value = pcic_getb(pcic, socket->socket, 3999 PCIC_MISC_CTL_1); 4000 if (pcic->pc_flags & PCF_AUDIO) 4001 value |= PCIC_MC_SPEAKER_ENB; 4002 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4003 value); 4004 } else { 4005 value = pcic_getb(pcic, socket->socket, 4006 PCIC_MISC_CTL_1); 4007 value &= ~PCIC_MC_SPEAKER_ENB; 4008 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4009 value); 4010 } 4011 break; 4012 case PCIC_CL_PD6729: 4013 case PCIC_CL_PD6730: 4014 case PCIC_CL_PD6832: 4015 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 4016 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4017 value |= PCIC_MC_SPEAKER_ENB; 4018 } else { 4019 value &= ~PCIC_MC_SPEAKER_ENB; 4020 } 4021 4022 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4023 value |= PCIC_MC_3VCC; 4024 else 4025 value &= ~PCIC_MC_3VCC; 4026 4027 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 4028 break; 4029 4030 case PCIC_O2_OZ6912: 4031 value = pcic_getcb(pcic, CB_MISCCTRL); 4032 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 4033 value |= (1<<25); 4034 else 4035 value &= ~(1<<25); 4036 pcic_putcb(pcic, CB_MISCCTRL, value); 4037 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4038 powerlevel |= 0x08; 4039 break; 4040 4041 case PCIC_TI_PCI1250: 4042 case PCIC_TI_PCI1221: 4043 case PCIC_TI_PCI1225: 4044 case PCIC_TI_PCI1410: 4045 case PCIC_ENE_1410: 4046 case PCIC_TI_PCI1510: 4047 case PCIC_TI_PCI1520: 4048 case PCIC_TI_PCI1420: 4049 case PCIC_ENE_1420: 4050 value = ddi_get8(pcic->cfg_handle, 4051 pcic->cfgaddr + PCIC_CRDCTL_REG); 4052 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4053 value |= PCIC_CRDCTL_SPKR_ENBL; 4054 } else { 4055 value &= ~PCIC_CRDCTL_SPKR_ENBL; 4056 } 4057 ddi_put8(pcic->cfg_handle, 4058 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4059 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4060 powerlevel |= 0x08; 4061 break; 4062 } 4063 4064 /* 4065 * ctlind processing -- we can ignore this 4066 * there aren't any outputs on the chip for this and 4067 * the GUI will display what it thinks is correct 4068 */ 4069 4070 /* 4071 * If outputs are enabled and the power is going off 4072 * turn off outputs first. 4073 */ 4074 4075 /* power setup -- if necessary */ 4076 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4077 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4078 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4079 pcic_putb(pcic, socket->socket, 4080 PCIC_POWER_CONTROL, orig_pwrctl); 4081 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4082 } 4083 4084 if (pcic->pc_flags & PCF_CBPWRCTL) { 4085 value = pcic_cbus_powerctl(pcic, socket->socket); 4086 powerlevel = 0; 4087 } else 4088 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4089 4090 if (value != SUCCESS) { 4091 mutex_exit(&pcic->pc_lock); 4092 return (value); 4093 } 4094 4095 /* 4096 * If outputs were disabled and the power is going on 4097 * turn on outputs afterwards. 4098 */ 4099 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4100 orig_pwrctl = pcic_getb(pcic, socket->socket, 4101 PCIC_POWER_CONTROL); 4102 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4103 pcic_putb(pcic, socket->socket, 4104 PCIC_POWER_CONTROL, orig_pwrctl); 4105 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4106 } 4107 4108 /* 4109 * Once we have done the power stuff can re-enable management 4110 * interrupts. 4111 */ 4112 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4113 4114 #if defined(PCIC_DEBUG) 4115 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4116 "cbctl 0x%x\n", 4117 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4118 pcic_getcb(pcic, CB_CONTROL)); 4119 #endif 4120 4121 /* irq processing */ 4122 if (socket->IFType == IF_IO) { 4123 /* IRQ only for I/O */ 4124 irq = socket->IREQRouting & PCIC_INTR_MASK; 4125 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4126 value &= ~PCIC_INTR_MASK; 4127 4128 /* to enable I/O operation */ 4129 value |= PCIC_IO_CARD | PCIC_RESET; 4130 sockp->pcs_flags |= PCS_CARD_IO; 4131 if (irq != sockp->pcs_irq) { 4132 if (sockp->pcs_irq != 0) 4133 cmn_err(CE_CONT, 4134 "SetSocket: IRQ mismatch %x != %x!\n", 4135 irq, sockp->pcs_irq); 4136 else 4137 sockp->pcs_irq = irq; 4138 } 4139 irq = sockp->pcs_irq; 4140 4141 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4142 if (socket->IREQRouting & IRQ_ENABLE) { 4143 pcic_enable_io_intr(pcic, socket->socket, irq); 4144 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4145 } else { 4146 pcic_disable_io_intr(pcic, socket->socket); 4147 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4148 } 4149 #if defined(PCIC_DEBUG) 4150 if (pcic_debug) { 4151 cmn_err(CE_CONT, 4152 "\tsocket type is I/O and irq %x is %s\n", irq, 4153 (socket->IREQRouting & IRQ_ENABLE) ? 4154 "enabled" : "not enabled"); 4155 xxdmp_all_regs(pcic, socket->socket, 20); 4156 } 4157 #endif 4158 } else { 4159 /* make sure I/O mode is off */ 4160 4161 sockp->pcs_irq = 0; 4162 4163 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4164 value &= ~PCIC_IO_CARD; 4165 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4166 pcic_disable_io_intr(pcic, socket->socket); 4167 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4168 } 4169 4170 sockp->pcs_state &= ~socket->State; 4171 4172 mutex_exit(&pcic->pc_lock); 4173 return (SUCCESS); 4174 } 4175 4176 /* 4177 * pcic_inquire_socket() 4178 * SocketServices InquireSocket function 4179 * returns basic characteristics of the socket 4180 */ 4181 /*ARGSUSED*/ 4182 static int 4183 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4184 { 4185 anp_t *anp = ddi_get_driver_private(dip); 4186 pcicdev_t *pcic = anp->an_private; 4187 int value; 4188 4189 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4190 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4191 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4192 value = pcic->pc_sockets[socket->socket].pcs_flags; 4193 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4194 socket->ActiveHigh = 0; 4195 /* these are the usable IRQs */ 4196 socket->ActiveLow = 0xfff0; 4197 return (SUCCESS); 4198 } 4199 4200 /* 4201 * pcic_inquire_window() 4202 * SocketServices InquireWindow function 4203 * returns detailed characteristics of the window 4204 * this is where windows get tied to sockets 4205 */ 4206 /*ARGSUSED*/ 4207 static int 4208 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4209 { 4210 int type, socket; 4211 4212 type = window->window % PCIC_NUMWINSOCK; 4213 socket = window->window / PCIC_NUMWINSOCK; 4214 4215 #if defined(PCIC_DEBUG) 4216 if (pcic_debug >= 8) 4217 cmn_err(CE_CONT, 4218 "pcic_inquire_window: window = %d/%d socket=%d\n", 4219 window->window, type, socket); 4220 #endif 4221 if (type < PCIC_IOWINDOWS) { 4222 window->WndCaps = WC_IO|WC_WAIT; 4223 type = IF_IO; 4224 } else { 4225 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4226 type = IF_MEMORY; 4227 } 4228 4229 /* initialize the socket map - one socket per window */ 4230 PR_ZERO(window->Sockets); 4231 PR_SET(window->Sockets, socket); 4232 4233 if (type == IF_IO) { 4234 iowin_char_t *io; 4235 io = &window->iowin_char; 4236 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4237 WC_16BIT; 4238 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4239 io->LastByte = (baseaddr_t)IOMEM_LAST; 4240 io->MinSize = IOMEM_MIN; 4241 io->MaxSize = IOMEM_MAX; 4242 io->ReqGran = IOMEM_GRAN; 4243 io->AddrLines = IOMEM_DECODE; 4244 io->EISASlot = 0; 4245 } else { 4246 mem_win_char_t *mem; 4247 mem = &window->mem_win_char; 4248 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4249 WC_16BIT|WC_WP; 4250 4251 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4252 mem->LastByte = (baseaddr_t)MEM_LAST; 4253 4254 mem->MinSize = MEM_MIN; 4255 mem->MaxSize = MEM_MAX; 4256 mem->ReqGran = PCIC_PAGE; 4257 mem->ReqBase = 0; 4258 mem->ReqOffset = PCIC_PAGE; 4259 mem->Slowest = MEM_SPEED_MAX; 4260 mem->Fastest = MEM_SPEED_MIN; 4261 } 4262 return (SUCCESS); 4263 } 4264 4265 /* 4266 * pcic_get_adapter() 4267 * SocketServices GetAdapter function 4268 * this is nearly a no-op. 4269 */ 4270 /*ARGSUSED*/ 4271 static int 4272 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4273 { 4274 anp_t *anp = ddi_get_driver_private(dip); 4275 pcicdev_t *pcic = anp->an_private; 4276 4277 if (pcic->pc_flags & PCF_INTRENAB) 4278 adapt->SCRouting = IRQ_ENABLE; 4279 adapt->state = 0; 4280 return (SUCCESS); 4281 } 4282 4283 /* 4284 * pcic_get_page() 4285 * SocketServices GetPage function 4286 * returns info about the window 4287 */ 4288 /*ARGSUSED*/ 4289 static int 4290 pcic_get_page(dev_info_t *dip, get_page_t *page) 4291 { 4292 anp_t *anp = ddi_get_driver_private(dip); 4293 pcicdev_t *pcic = anp->an_private; 4294 int socket, window; 4295 pcs_memwin_t *winp; 4296 4297 socket = page->window / PCIC_NUMWINSOCK; 4298 window = page->window % PCIC_NUMWINSOCK; 4299 4300 /* I/O windows are the first two */ 4301 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4302 return (BAD_WINDOW); 4303 } 4304 4305 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4306 4307 if (page->page != 0) 4308 return (BAD_PAGE); 4309 4310 page->state = 0; 4311 if (winp->pcw_status & PCW_ENABLED) 4312 page->state |= PS_ENABLED; 4313 if (winp->pcw_status & PCW_ATTRIBUTE) 4314 page->state |= PS_ATTRIBUTE; 4315 if (winp->pcw_status & PCW_WP) 4316 page->state |= PS_WP; 4317 4318 page->offset = (off_t)winp->pcw_offset; 4319 4320 return (SUCCESS); 4321 } 4322 4323 /* 4324 * pcic_get_socket() 4325 * SocketServices GetSocket 4326 * returns information about the current socket setting 4327 */ 4328 /*ARGSUSED*/ 4329 static int 4330 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4331 { 4332 anp_t *anp = ddi_get_driver_private(dip); 4333 pcicdev_t *pcic = anp->an_private; 4334 int socknum, irq_enabled; 4335 pcic_socket_t *sockp; 4336 4337 socknum = socket->socket; 4338 sockp = &pcic->pc_sockets[socknum]; 4339 4340 socket->SCIntMask = sockp->pcs_intmask; 4341 sockp->pcs_state = pcic_card_state(pcic, sockp); 4342 4343 socket->state = sockp->pcs_state; 4344 if (socket->state & SBM_CD) { 4345 socket->VccLevel = sockp->pcs_vcc; 4346 socket->Vpp1Level = sockp->pcs_vpp1; 4347 socket->Vpp2Level = sockp->pcs_vpp2; 4348 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4349 IRQ_ENABLE : 0; 4350 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4351 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4352 IF_IO : IF_MEMORY; 4353 } else { 4354 socket->VccLevel = 0; 4355 socket->Vpp1Level = 0; 4356 socket->Vpp2Level = 0; 4357 socket->IRQRouting = 0; 4358 socket->IFType = IF_MEMORY; 4359 } 4360 socket->CtlInd = 0; /* no indicators */ 4361 4362 return (SUCCESS); 4363 } 4364 4365 /* 4366 * pcic_get_status() 4367 * SocketServices GetStatus 4368 * returns status information about the PC Card in 4369 * the selected socket 4370 */ 4371 /*ARGSUSED*/ 4372 static int 4373 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4374 { 4375 anp_t *anp = ddi_get_driver_private(dip); 4376 pcicdev_t *pcic = anp->an_private; 4377 int socknum, irq_enabled; 4378 pcic_socket_t *sockp; 4379 4380 socknum = status->socket; 4381 sockp = &pcic->pc_sockets[socknum]; 4382 4383 status->CardState = pcic_card_state(pcic, sockp); 4384 status->SocketState = sockp->pcs_state; 4385 status->CtlInd = 0; /* no indicators */ 4386 4387 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4388 status->SocketState |= SBM_CD; 4389 if (status->CardState & SBM_CD) { 4390 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4391 IRQ_ENABLE : 0; 4392 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4393 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4394 IF_IO : IF_MEMORY; 4395 } else { 4396 status->IRQRouting = 0; 4397 status->IFType = IF_MEMORY; 4398 } 4399 4400 #if defined(PCIC_DEBUG) 4401 if (pcic_debug >= 8) 4402 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4403 "SocketState=%x\n", 4404 socknum, status->CardState, status->SocketState); 4405 #endif 4406 switch (pcic->pc_type) { 4407 uint32_t present_state; 4408 case PCIC_TI_PCI1410: 4409 case PCIC_TI_PCI1520: 4410 case PCIC_TI_PCI1420: 4411 case PCIC_ENE_1420: 4412 case PCIC_TOSHIBA_TOPIC100: 4413 case PCIC_TOSHIBA_TOPIC95: 4414 case PCIC_TOSHIBA_VENDOR: 4415 case PCIC_O2MICRO_VENDOR: 4416 case PCIC_TI_VENDOR: 4417 case PCIC_RICOH_VENDOR: 4418 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4419 if (present_state & PCIC_CB_CARD) 4420 status->IFType = IF_CARDBUS; 4421 #if defined(PCIC_DEBUG) 4422 if (pcic_debug >= 8) 4423 cmn_err(CE_CONT, "pcic_get_status: present_state=0x%x\n", 4424 present_state); 4425 #endif 4426 break; 4427 default: 4428 break; 4429 } 4430 4431 return (SUCCESS); 4432 } 4433 4434 /* 4435 * pcic_get_window() 4436 * SocketServices GetWindow function 4437 * returns state information about the specified window 4438 */ 4439 /*ARGSUSED*/ 4440 static int 4441 pcic_get_window(dev_info_t *dip, get_window_t *window) 4442 { 4443 anp_t *anp = ddi_get_driver_private(dip); 4444 pcicdev_t *pcic = anp->an_private; 4445 int socket, win; 4446 pcic_socket_t *sockp; 4447 pcs_memwin_t *winp; 4448 4449 socket = window->window / PCIC_NUMWINSOCK; 4450 win = window->window % PCIC_NUMWINSOCK; 4451 #if defined(PCIC_DEBUG) 4452 if (pcic_debug) { 4453 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4454 socket, win); 4455 } 4456 #endif 4457 4458 if (socket > pcic->pc_numsockets) 4459 return (BAD_WINDOW); 4460 4461 sockp = &pcic->pc_sockets[socket]; 4462 winp = &sockp->pcs_windows[win].mem; 4463 4464 window->socket = socket; 4465 window->size = winp->pcw_len; 4466 window->speed = winp->pcw_speed; 4467 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4468 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4469 4470 if (win >= PCIC_IOWINDOWS) { 4471 window->state = 0; 4472 } else { 4473 window->state = WS_IO; 4474 } 4475 if (winp->pcw_status & PCW_ENABLED) 4476 window->state |= WS_ENABLED; 4477 4478 if (winp->pcw_status & PCS_CARD_16BIT) 4479 window->state |= WS_16BIT; 4480 #if defined(PCIC_DEBUG) 4481 if (pcic_debug) 4482 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4483 window->size, (unsigned)window->speed, 4484 (void *)window->handle, window->state); 4485 #endif 4486 4487 return (SUCCESS); 4488 } 4489 4490 /* 4491 * pcic_ll_reset 4492 * low level reset 4493 * separated out so it can be called when already locked 4494 * 4495 * There are two variables that control the RESET timing: 4496 * pcic_prereset_time - time in mS before asserting RESET 4497 * pcic_reset_time - time in mS to assert RESET 4498 * 4499 */ 4500 int pcic_prereset_time = 1; 4501 int pcic_reset_time = 10; 4502 int pcic_postreset_time = 20; 4503 int pcic_vpp_is_vcc_during_reset = 0; 4504 4505 static int 4506 pcic_ll_reset(pcicdev_t *pcic, int socket) 4507 { 4508 int windowbits, iobits; 4509 uint32_t pwr; 4510 4511 /* save windows that were on */ 4512 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4513 if (pcic_reset_time == 0) 4514 return (windowbits); 4515 /* turn all windows off */ 4516 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4517 4518 #if defined(PCIC_DEBUG) 4519 pcic_err(pcic->dip, 6, 4520 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4521 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4522 pcic_getcb(pcic, CB_CONTROL), 4523 pcic_getcb(pcic, CB_PRESENT_STATE)); 4524 #endif 4525 4526 if (pcic_vpp_is_vcc_during_reset) { 4527 4528 /* 4529 * Set VPP to VCC for the duration of the reset - for aironet 4530 * card. 4531 */ 4532 if (pcic->pc_flags & PCF_CBPWRCTL) { 4533 pwr = pcic_getcb(pcic, CB_CONTROL); 4534 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4535 (void) pcic_getcb(pcic, CB_CONTROL); 4536 } else { 4537 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4538 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4539 pwr | 1); 4540 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4541 } 4542 } 4543 4544 if (pcic_prereset_time > 0) { 4545 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4546 pcic_prereset_time); 4547 pcic_mswait(pcic, socket, pcic_prereset_time); 4548 } 4549 4550 /* turn interrupts off and start a reset */ 4551 pcic_err(pcic->dip, 8, 4552 "pcic_ll_reset turn interrupts off and start a reset\n"); 4553 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4554 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4555 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4556 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4557 4558 switch (pcic->pc_type) { 4559 case PCIC_INTEL_i82092: 4560 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4561 PCIC_82092_INT_DISABLE); 4562 break; 4563 default: 4564 break; 4565 } /* switch */ 4566 4567 pcic->pc_sockets[socket].pcs_state = 0; 4568 4569 if (pcic_reset_time > 0) { 4570 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4571 pcic_reset_time); 4572 pcic_mswait(pcic, socket, pcic_reset_time); 4573 } 4574 4575 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4576 4577 /* take it out of RESET now */ 4578 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4579 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4580 4581 /* 4582 * can't access the card for 20ms, but we really don't 4583 * want to sit around that long. The pcic is still usable. 4584 * memory accesses must wait for RDY to come up. 4585 */ 4586 if (pcic_postreset_time > 0) { 4587 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4588 pcic_postreset_time); 4589 pcic_mswait(pcic, socket, pcic_postreset_time); 4590 } 4591 4592 if (pcic_vpp_is_vcc_during_reset > 1) { 4593 4594 /* 4595 * Return VPP power to whatever it was before. 4596 */ 4597 if (pcic->pc_flags & PCF_CBPWRCTL) { 4598 pcic_putcb(pcic, CB_CONTROL, pwr); 4599 (void) pcic_getcb(pcic, CB_CONTROL); 4600 } else { 4601 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4602 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4603 } 4604 } 4605 4606 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4607 4608 return (windowbits); 4609 } 4610 4611 /* 4612 * pcic_reset_socket() 4613 * SocketServices ResetSocket function 4614 * puts the PC Card in the socket into the RESET state 4615 * and then takes it out after the the cycle time 4616 * The socket is back to initial state when done 4617 */ 4618 static int 4619 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4620 { 4621 anp_t *anp = ddi_get_driver_private(dip); 4622 pcicdev_t *pcic = anp->an_private; 4623 int value; 4624 int i, mint; 4625 pcic_socket_t *sockp; 4626 4627 #if defined(PCIC_DEBUG) 4628 if (pcic_debug >= 8) 4629 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4630 (void *)dip, socket, mode, 4631 mode == RESET_MODE_FULL ? "full" : "partial"); 4632 #endif 4633 4634 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4635 4636 /* Turn off management interupts. */ 4637 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4638 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4639 4640 sockp = &pcic->pc_sockets[socket]; 4641 4642 value = pcic_ll_reset(pcic, socket); 4643 if (mode == RESET_MODE_FULL) { 4644 /* disable and unmap all mapped windows */ 4645 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4646 if (i < PCIC_IOWINDOWS) { 4647 if (sockp->pcs_windows[i].io.pcw_status & 4648 PCW_MAPPED) { 4649 pcs_iowin_t *io; 4650 io = &sockp->pcs_windows[i].io; 4651 io->pcw_status &= ~PCW_ENABLED; 4652 } 4653 } else { 4654 if (sockp->pcs_windows[i].mem.pcw_status & 4655 PCW_MAPPED) { 4656 pcs_memwin_t *mem; 4657 mem = &sockp->pcs_windows[i].mem; 4658 mem->pcw_status &= ~PCW_ENABLED; 4659 } 4660 } 4661 } 4662 } else { 4663 /* turn windows back on */ 4664 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4665 /* wait the rest of the time here */ 4666 pcic_mswait(pcic, socket, 10); 4667 } 4668 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4669 mutex_exit(&pcic->pc_lock); 4670 return (SUCCESS); 4671 } 4672 4673 /* 4674 * pcic_set_interrupt() 4675 * SocketServices SetInterrupt function 4676 */ 4677 static int 4678 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4679 { 4680 anp_t *anp = ddi_get_driver_private(dip); 4681 pcicdev_t *pcic = anp->an_private; 4682 int value = DDI_SUCCESS; 4683 inthandler_t *intr; 4684 4685 #if defined(PCIC_DEBUG) 4686 if (pcic_debug) { 4687 cmn_err(CE_CONT, 4688 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4689 pcic->pc_intr_mode); 4690 cmn_err(CE_CONT, 4691 "\t irq_top=%p handler=%p handler_id=%x\n", 4692 (void *)pcic->irq_top, (void *)handler->handler, 4693 handler->handler_id); 4694 } 4695 #endif 4696 4697 /* 4698 * If we're on a PCI bus, we route all IO IRQs through a single 4699 * PCI interrupt (typically INT A#) so we don't have to do 4700 * much other than add the caller to general interrupt handler 4701 * and set some state. 4702 */ 4703 4704 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4705 if (intr == NULL) 4706 return (NO_RESOURCE); 4707 4708 switch (pcic->pc_intr_mode) { 4709 case PCIC_INTR_MODE_PCI_1: 4710 /* 4711 * We only allow above-lock-level IO IRQ handlers 4712 * in the PCI bus case. 4713 */ 4714 4715 mutex_enter(&pcic->intr_lock); 4716 4717 if (pcic->irq_top == NULL) { 4718 pcic->irq_top = intr; 4719 pcic->irq_current = pcic->irq_top; 4720 } else { 4721 while (pcic->irq_current->next != NULL) 4722 pcic->irq_current = pcic->irq_current->next; 4723 pcic->irq_current->next = intr; 4724 pcic->irq_current = pcic->irq_current->next; 4725 } 4726 4727 pcic->irq_current->intr = 4728 (ddi_intr_handler_t *)handler->handler; 4729 pcic->irq_current->handler_id = handler->handler_id; 4730 pcic->irq_current->arg1 = handler->arg1; 4731 pcic->irq_current->arg2 = handler->arg2; 4732 pcic->irq_current->socket = handler->socket; 4733 4734 mutex_exit(&pcic->intr_lock); 4735 4736 handler->iblk_cookie = &pcic->pc_pri; 4737 handler->idev_cookie = &pcic->pc_dcookie; 4738 break; 4739 4740 default: 4741 intr->intr = (ddi_intr_handler_t *)handler->handler; 4742 intr->handler_id = handler->handler_id; 4743 intr->arg1 = handler->arg1; 4744 intr->arg2 = handler->arg2; 4745 intr->socket = handler->socket; 4746 intr->irq = handler->irq; 4747 4748 /* 4749 * need to revisit this to see if interrupts can be 4750 * shared someday. Note that IRQ is set in the common 4751 * code. 4752 */ 4753 mutex_enter(&pcic->pc_lock); 4754 if (pcic->pc_handlers == NULL) { 4755 pcic->pc_handlers = intr; 4756 intr->next = intr->prev = intr; 4757 } else { 4758 insque(intr, pcic->pc_handlers); 4759 } 4760 mutex_exit(&pcic->pc_lock); 4761 4762 break; 4763 } 4764 4765 /* 4766 * need to fill in cookies in event of multiple high priority 4767 * interrupt handlers on same IRQ 4768 */ 4769 4770 #if defined(PCIC_DEBUG) 4771 if (pcic_debug) { 4772 cmn_err(CE_CONT, 4773 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4774 (void *)pcic->irq_top, value); 4775 } 4776 #endif 4777 4778 if (value == DDI_SUCCESS) { 4779 return (SUCCESS); 4780 } else { 4781 return (BAD_IRQ); 4782 } 4783 } 4784 4785 /* 4786 * pcic_clear_interrupt() 4787 * SocketServices ClearInterrupt function 4788 * 4789 * Interrupts for PCIC are complicated by the fact that we must 4790 * follow several different models for interrupts. 4791 * ISA: there is an interrupt per adapter and per socket and 4792 * they can't be shared. 4793 * PCI: some adapters have one PCI interrupt available while others 4794 * have up to 4. Solaris may or may not allow us to use more 4795 * than 1 so we essentially share them all at this point. 4796 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4797 * This is like ISA but we have to fudge and create an intrspec 4798 * that PCI's parent understands and bypass the PCI nexus. 4799 * multifunction: this requires sharing the interrupts on a per-socket 4800 * basis. 4801 */ 4802 static int 4803 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4804 { 4805 anp_t *anp = ddi_get_driver_private(dip); 4806 pcicdev_t *pcic = anp->an_private; 4807 inthandler_t *intr, *prev, *current; 4808 int i; 4809 4810 /* 4811 * If we're on a PCI bus, we route all IO IRQs through a single 4812 * PCI interrupt (typically INT A#) so we don't have to do 4813 * much other than remove the caller from the general 4814 * interrupt handler callout list. 4815 */ 4816 4817 #if defined(PCIC_DEBUG) 4818 if (pcic_debug) { 4819 cmn_err(CE_CONT, 4820 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4821 pcic->pc_intr_mode); 4822 cmn_err(CE_CONT, 4823 "\t irq_top=%p handler=%p handler_id=%x\n", 4824 (void *)pcic->irq_top, (void *)handler->handler, 4825 handler->handler_id); 4826 } 4827 #endif 4828 4829 switch (pcic->pc_intr_mode) { 4830 case PCIC_INTR_MODE_PCI_1: 4831 4832 mutex_enter(&pcic->intr_lock); 4833 if (pcic->irq_top == NULL) { 4834 mutex_exit(&pcic->intr_lock); 4835 return (BAD_IRQ); 4836 } 4837 4838 intr = NULL; 4839 pcic->irq_current = pcic->irq_top; 4840 4841 while ((pcic->irq_current != NULL) && 4842 (pcic->irq_current->handler_id != 4843 handler->handler_id)) { 4844 intr = pcic->irq_current; 4845 pcic->irq_current = pcic->irq_current->next; 4846 } 4847 4848 if (pcic->irq_current == NULL) { 4849 mutex_exit(&pcic->intr_lock); 4850 return (BAD_IRQ); 4851 } 4852 4853 if (intr != NULL) { 4854 intr->next = pcic->irq_current->next; 4855 } else { 4856 pcic->irq_top = pcic->irq_current->next; 4857 } 4858 4859 current = pcic->irq_current; 4860 pcic->irq_current = pcic->irq_top; 4861 mutex_exit(&pcic->intr_lock); 4862 kmem_free(current, sizeof (inthandler_t)); 4863 4864 break; 4865 4866 default: 4867 4868 mutex_enter(&pcic->pc_lock); 4869 intr = pcic_handlers; 4870 prev = (inthandler_t *)&pcic_handlers; 4871 4872 while (intr != NULL) { 4873 if (intr->handler_id == handler->handler_id) { 4874 i = intr->irq & PCIC_INTR_MASK; 4875 if (--pcic_irq_map[i].count == 0) { 4876 /* multi-handler form */ 4877 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4878 (void) ddi_intr_remove_handler( 4879 pcic->pc_intr_htblp[i]); 4880 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4881 (void) pcmcia_return_intr(pcic->dip, i); 4882 #if defined(PCIC_DEBUG) 4883 if (pcic_debug) { 4884 cmn_err(CE_CONT, 4885 "removing interrupt %d at %s " 4886 "priority\n", i, "high"); 4887 cmn_err(CE_CONT, 4888 "ddi_remove_intr(%p, %x, %p)\n", 4889 (void *)dip, 4890 0, 4891 (void *)intr->iblk_cookie); 4892 } 4893 #endif 4894 } 4895 prev->next = intr->next; 4896 kmem_free(intr, sizeof (inthandler_t)); 4897 intr = prev->next; 4898 } else { 4899 prev = intr; 4900 intr = intr->next; 4901 } /* if (handler_id) */ 4902 } /* while */ 4903 4904 mutex_exit(&pcic->pc_lock); 4905 } 4906 4907 #if defined(PCIC_DEBUG) 4908 if (pcic_debug) { 4909 cmn_err(CE_CONT, 4910 "pcic_clear_interrupt: exit irq_top=%p\n", 4911 (void *)pcic->irq_top); 4912 } 4913 #endif 4914 4915 4916 return (SUCCESS); 4917 } 4918 4919 struct intel_regs { 4920 char *name; 4921 int off; 4922 char *fmt; 4923 } iregs[] = { 4924 {"ident ", 0}, 4925 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4926 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4927 "\7DRD\10OE"}, 4928 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4929 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4930 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4931 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4932 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4933 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4934 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4935 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4936 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4937 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4938 {"io0-slow ", 8}, 4939 {"io0-shi ", 9}, 4940 {"io0-elow ", 0xa}, 4941 {"io0-ehi ", 0xb}, 4942 {"io1-slow ", 0xc}, 4943 {"io1-shi ", 0xd}, 4944 {"io1-elow ", 0xe}, 4945 {"io1-ehi ", 0xf}, 4946 {"mem0-slow ", 0x10}, 4947 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4948 {"mem0-elow ", 0x12}, 4949 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4950 {"card0-low ", 0x14}, 4951 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4952 {"mem1-slow ", 0x18}, 4953 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4954 {"mem1-elow ", 0x1a}, 4955 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4956 {"card1-low ", 0x1c}, 4957 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4958 {"mem2-slow ", 0x20}, 4959 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4960 {"mem2-elow ", 0x22}, 4961 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4962 {"card2-low ", 0x24}, 4963 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4964 {"mem3-slow ", 0x28}, 4965 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4966 {"mem3-elow ", 0x2a}, 4967 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4968 {"card3-low ", 0x2c}, 4969 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4970 4971 {"mem4-slow ", 0x30}, 4972 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4973 {"mem4-elow ", 0x32}, 4974 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4975 {"card4-low ", 0x34}, 4976 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4977 {"mpage0 ", 0x40}, 4978 {"mpage1 ", 0x41}, 4979 {"mpage2 ", 0x42}, 4980 {"mpage3 ", 0x43}, 4981 {"mpage4 ", 0x44}, 4982 {NULL}, 4983 }; 4984 4985 static struct intel_regs cregs[] = { 4986 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 4987 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 4988 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 4989 {"chip-info ", 0x1f, "\20\6DUAL"}, 4990 {"IO-offlow0", 0x36}, 4991 {"IO-offhi0 ", 0x37}, 4992 {"IO-offlow1", 0x38}, 4993 {"IO-offhi1 ", 0x39}, 4994 NULL, 4995 }; 4996 4997 static struct intel_regs cxregs[] = { 4998 {"ext-ctl-1 ", 0x03, 4999 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 5000 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 5001 {"mem0-up ", 0x05}, 5002 {"mem1-up ", 0x06}, 5003 {"mem2-up ", 0x07}, 5004 {"mem3-up ", 0x08}, 5005 {"mem4-up ", 0x09}, 5006 {NULL} 5007 }; 5008 5009 void 5010 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 5011 { 5012 int i, value, j; 5013 char buff[256]; 5014 char *fmt; 5015 5016 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 5017 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 5018 int sval; 5019 if (cregs[i].off == PCIC_MISC_CTL_2) 5020 sval = 0; 5021 else 5022 sval = socket; 5023 value = pcic_getb(pcic, sval, cregs[i].off); 5024 if (i & 1) { 5025 if (cregs[i].fmt) 5026 fmt = "%s\t%s\t%b\n"; 5027 else 5028 fmt = "%s\t%s\t%x\n"; 5029 cmn_err(CE_CONT, fmt, buff, 5030 cregs[i].name, value, cregs[i].fmt); 5031 buff[0] = '\0'; 5032 } else { 5033 if (cregs[i].fmt) 5034 fmt = "\t%s\t%b"; 5035 else 5036 fmt = "\t%s\t%x"; 5037 (void) sprintf(buff, fmt, 5038 cregs[i].name, value, cregs[i].fmt); 5039 for (j = strlen(buff); j < 40; j++) 5040 buff[j] = ' '; 5041 buff[40] = '\0'; 5042 } 5043 } 5044 cmn_err(CE_CONT, "%s\n", buff); 5045 5046 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 5047 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 5048 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 5049 5050 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 5051 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 5052 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 5053 5054 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 5055 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 5056 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 5057 5058 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5059 5060 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5061 value = clext_reg_read(pcic, socket, cxregs[i].off); 5062 if (i & 1) { 5063 if (cxregs[i].fmt) 5064 fmt = "%s\t%s\t%b\n"; 5065 else 5066 fmt = "%s\t%s\t%x\n"; 5067 cmn_err(CE_CONT, fmt, buff, 5068 cxregs[i].name, value, cxregs[i].fmt); 5069 buff[0] = '\0'; 5070 } else { 5071 if (cxregs[i].fmt) 5072 fmt = "\t%s\t%b"; 5073 else 5074 fmt = "\t%s\t%x"; 5075 (void) sprintf(buff, fmt, 5076 cxregs[i].name, value, cxregs[i].fmt); 5077 for (j = strlen(buff); j < 40; j++) 5078 buff[j] = ' '; 5079 buff[40] = '\0'; 5080 } 5081 } 5082 } 5083 5084 #if defined(PCIC_DEBUG) 5085 static void 5086 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5087 { 5088 int i, value, j; 5089 char buff[256]; 5090 char *fmt; 5091 5092 #if defined(PCIC_DEBUG) 5093 if (pcic_debug < 2) 5094 return; 5095 #endif 5096 cmn_err(CE_CONT, 5097 "----------- PCIC Registers for socket %d---------\n", 5098 socket); 5099 cmn_err(CE_CONT, 5100 "\tname value name value\n"); 5101 5102 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5103 value = pcic_getb(pcic, socket, iregs[i].off); 5104 if (i & 1) { 5105 if (iregs[i].fmt) 5106 fmt = "%s\t%s\t%b\n"; 5107 else 5108 fmt = "%s\t%s\t%x\n"; 5109 cmn_err(CE_CONT, fmt, buff, 5110 iregs[i].name, value, iregs[i].fmt); 5111 buff[0] = '\0'; 5112 } else { 5113 if (iregs[i].fmt) 5114 fmt = "\t%s\t%b"; 5115 else 5116 fmt = "\t%s\t%x"; 5117 (void) sprintf(buff, fmt, 5118 iregs[i].name, value, iregs[i].fmt); 5119 for (j = strlen(buff); j < 40; j++) 5120 buff[j] = ' '; 5121 buff[40] = '\0'; 5122 } 5123 } 5124 switch (pcic->pc_type) { 5125 case PCIC_CL_PD6710: 5126 case PCIC_CL_PD6722: 5127 case PCIC_CL_PD6729: 5128 case PCIC_CL_PD6832: 5129 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5130 break; 5131 } 5132 cmn_err(CE_CONT, "%s\n", buff); 5133 } 5134 #endif 5135 5136 /* 5137 * pcic_mswait(ms) 5138 * sleep ms milliseconds 5139 * call drv_usecwait once for each ms 5140 */ 5141 static void 5142 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5143 { 5144 if (ms) { 5145 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5146 pcic_mutex_exit(&pcic->pc_lock); 5147 delay(drv_usectohz(ms*1000)); 5148 pcic_mutex_enter(&pcic->pc_lock); 5149 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5150 } 5151 } 5152 5153 /* 5154 * pcic_check_ready(pcic, index, off) 5155 * Wait for card to come ready 5156 * We only wait if the card is NOT in RESET 5157 * and power is on. 5158 */ 5159 static boolean_t 5160 pcic_check_ready(pcicdev_t *pcic, int socket) 5161 { 5162 int ifstate, intstate; 5163 5164 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5165 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5166 5167 if ((intstate & PCIC_RESET) && 5168 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5169 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5170 return (B_TRUE); 5171 5172 #ifdef PCIC_DEBUG 5173 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5174 "ifstate = 0x%x\n", intstate, ifstate); 5175 if (pcic_debug) { 5176 pcic_debug += 4; 5177 xxdmp_all_regs(pcic, socket, -1); 5178 pcic_debug -= 4; 5179 } 5180 #endif 5181 return (B_FALSE); 5182 } 5183 5184 /* 5185 * Cirrus Logic extended register read/write routines 5186 */ 5187 static int 5188 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5189 { 5190 int val; 5191 5192 switch (pcic->pc_io_type) { 5193 case PCIC_IO_TYPE_YENTA: 5194 val = ddi_get8(pcic->handle, 5195 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5196 break; 5197 default: 5198 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5199 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5200 break; 5201 } 5202 5203 return (val); 5204 } 5205 5206 static void 5207 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5208 { 5209 switch (pcic->pc_io_type) { 5210 case PCIC_IO_TYPE_YENTA: 5211 ddi_put8(pcic->handle, 5212 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5213 break; 5214 default: 5215 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5216 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5217 break; 5218 } 5219 } 5220 5221 /* 5222 * Misc PCI functions 5223 */ 5224 static void 5225 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5226 { 5227 unsigned cmd; 5228 5229 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5230 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5231 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5232 (PCI_COMM_IO|PCI_COMM_MAE)) 5233 return; 5234 5235 if (flags & PCIC_ENABLE_IO) 5236 cmd |= PCI_COMM_IO; 5237 5238 if (flags & PCIC_ENABLE_MEM) 5239 cmd |= PCI_COMM_MAE; 5240 5241 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5242 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5243 } 5244 5245 /* 5246 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5247 */ 5248 static int 5249 pcic_find_pci_type(pcicdev_t *pcic) 5250 { 5251 uint32_t vend, device; 5252 5253 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5254 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5255 "vendor-id", -1); 5256 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5257 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5258 "device-id", -1); 5259 5260 device = PCI_ID(vend, device); 5261 pcic->pc_type = device; 5262 pcic->pc_chipname = "PCI:unknown"; 5263 5264 switch (device) { 5265 case PCIC_INTEL_i82092: 5266 pcic->pc_chipname = PCIC_TYPE_i82092; 5267 break; 5268 case PCIC_CL_PD6729: 5269 pcic->pc_chipname = PCIC_TYPE_PD6729; 5270 /* 5271 * Some 6730's incorrectly identify themselves 5272 * as a 6729, so we need to do some more tests 5273 * here to see if the device that's claiming 5274 * to be a 6729 is really a 6730. 5275 */ 5276 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5277 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5278 0) { 5279 pcic->pc_chipname = PCIC_TYPE_PD6730; 5280 pcic->pc_type = PCIC_CL_PD6730; 5281 } 5282 break; 5283 case PCIC_CL_PD6730: 5284 pcic->pc_chipname = PCIC_TYPE_PD6730; 5285 break; 5286 case PCIC_CL_PD6832: 5287 pcic->pc_chipname = PCIC_TYPE_PD6832; 5288 break; 5289 case PCIC_SMC_34C90: 5290 pcic->pc_chipname = PCIC_TYPE_34C90; 5291 break; 5292 case PCIC_TOSHIBA_TOPIC95: 5293 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5294 break; 5295 case PCIC_TOSHIBA_TOPIC100: 5296 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5297 break; 5298 case PCIC_TI_PCI1031: 5299 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5300 break; 5301 case PCIC_TI_PCI1130: 5302 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5303 break; 5304 case PCIC_TI_PCI1131: 5305 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5306 break; 5307 case PCIC_TI_PCI1250: 5308 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5309 break; 5310 case PCIC_TI_PCI1225: 5311 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5312 break; 5313 case PCIC_TI_PCI1410: 5314 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5315 break; 5316 case PCIC_TI_PCI1510: 5317 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5318 break; 5319 case PCIC_TI_PCI1520: 5320 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5321 break; 5322 case PCIC_TI_PCI1221: 5323 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5324 break; 5325 case PCIC_TI_PCI1050: 5326 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5327 break; 5328 case PCIC_ENE_1410: 5329 pcic->pc_chipname = PCIC_TYPE_1410; 5330 break; 5331 case PCIC_O2_OZ6912: 5332 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5333 break; 5334 case PCIC_RICOH_RL5C466: 5335 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5336 break; 5337 case PCIC_TI_PCI1420: 5338 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5339 break; 5340 case PCIC_ENE_1420: 5341 pcic->pc_chipname = PCIC_TYPE_1420; 5342 break; 5343 default: 5344 switch (PCI_ID(vend, (uint32_t)0)) { 5345 case PCIC_TOSHIBA_VENDOR: 5346 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5347 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5348 break; 5349 case PCIC_TI_VENDOR: 5350 pcic->pc_chipname = PCIC_TYPE_TI; 5351 pcic->pc_type = PCIC_TI_VENDOR; 5352 break; 5353 case PCIC_O2MICRO_VENDOR: 5354 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5355 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5356 break; 5357 case PCIC_RICOH_VENDOR: 5358 pcic->pc_chipname = PCIC_TYPE_RICOH; 5359 pcic->pc_type = PCIC_RICOH_VENDOR; 5360 break; 5361 default: 5362 if (!(pcic->pc_flags & PCF_CARDBUS)) 5363 return (DDI_FAILURE); 5364 pcic->pc_chipname = PCIC_TYPE_YENTA; 5365 break; 5366 } 5367 } 5368 return (DDI_SUCCESS); 5369 } 5370 5371 static void 5372 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5373 { 5374 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5375 pcic->cfgaddr + PCIC_82092_PPIRR); 5376 uchar_t val; 5377 5378 if (intr == PCIC_82092_CTL_SMI) { 5379 val = PCIC_82092_SMI_CTL(socket, 5380 PCIC_82092_INT_DISABLE); 5381 ppirr &= ~val; 5382 val = PCIC_82092_SMI_CTL(socket, state); 5383 ppirr |= val; 5384 } else { 5385 val = PCIC_82092_IRQ_CTL(socket, 5386 PCIC_82092_INT_DISABLE); 5387 ppirr &= ~val; 5388 val = PCIC_82092_IRQ_CTL(socket, state); 5389 ppirr |= val; 5390 } 5391 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5392 ppirr); 5393 } 5394 5395 static uint_t 5396 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5397 { 5398 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5399 uint_t rc = DDI_INTR_UNCLAIMED; 5400 5401 _NOTE(ARGUNUSED(arg2)) 5402 5403 mutex_enter(&sockp->pcs_pcic->pc_lock); 5404 if (sockp->pcs_cd_softint_flg) { 5405 uint8_t status; 5406 sockp->pcs_cd_softint_flg = 0; 5407 rc = DDI_INTR_CLAIMED; 5408 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5409 PCIC_INTERFACE_STATUS); 5410 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5411 } 5412 mutex_exit(&sockp->pcs_pcic->pc_lock); 5413 return (rc); 5414 } 5415 5416 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5417 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5418 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5419 5420 #ifdef CARDBUS 5421 static uint32_t pcic_cbps_on = 0; 5422 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5423 CB_PS_XVCARD | CB_PS_YVCARD; 5424 #else 5425 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5426 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5427 CB_PS_CBCARD | 5428 CB_PS_XVCARD | CB_PS_YVCARD; 5429 #endif 5430 static void 5431 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5432 { 5433 boolean_t do_debounce = B_FALSE; 5434 int debounce_time = drv_usectohz(pcic_debounce_time); 5435 uint8_t irq; 5436 timeout_id_t debounce; 5437 5438 /* 5439 * Always reset debounce but may need to check original state later. 5440 */ 5441 debounce = sockp->pcs_debounce_id; 5442 sockp->pcs_debounce_id = 0; 5443 5444 /* 5445 * Check to see whether a card is present or not. There are 5446 * only two states that we are concerned with - the state 5447 * where both CD pins are asserted, which means that the 5448 * card is fully seated, and the state where neither CD 5449 * pin is asserted, which means that the card is not 5450 * present. 5451 * The CD signals are generally very noisy and cause a lot of 5452 * contact bounce as the card is being inserted and 5453 * removed, so we need to do some software debouncing. 5454 */ 5455 5456 #ifdef PCIC_DEBUG 5457 pcic_err(pcic->dip, 6, 5458 "pcic%d handle_cd_change: socket %d card status 0x%x" 5459 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5460 sockp->pcs_socket, status, debounce); 5461 #endif 5462 switch (status & PCIC_ISTAT_CD_MASK) { 5463 case PCIC_CD_PRESENT_OK: 5464 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5465 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5466 uint32_t cbps; 5467 #ifdef PCIC_DEBUG 5468 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5469 #endif 5470 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5471 #ifdef PCIC_DEBUG 5472 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5473 #endif 5474 /* 5475 * Check the CB bits are sane. 5476 */ 5477 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5478 cbps & pcic_cbps_off) { 5479 cmn_err(CE_WARN, 5480 "%s%d: Odd Cardbus Present State 0x%x\n", 5481 ddi_get_name(pcic->dip), 5482 ddi_get_instance(pcic->dip), 5483 cbps); 5484 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5485 debounce = 0; 5486 debounce_time = drv_usectohz(1000000); 5487 } 5488 if (debounce) { 5489 sockp->pcs_flags |= PCS_CARD_PRESENT; 5490 if (pcic_do_insertion) { 5491 5492 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5493 5494 if (cbps & CB_PS_16BITCARD) { 5495 pcic_err(pcic->dip, 8, "16 bit card inserted\n"); 5496 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5497 /* calls pcm_adapter_callback() */ 5498 if (pcic->pc_callback) { 5499 5500 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 5501 pcic->dip, PCM_DEVICETYPE, 5502 "pccard"); 5503 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5504 PCE_CARD_INSERT, 5505 sockp->pcs_socket); 5506 } 5507 } else if (cbps & CB_PS_CBCARD) { 5508 pcic_err(pcic->dip, 8, "32 bit card inserted\n"); 5509 5510 if (pcic->pc_flags & PCF_CARDBUS) { 5511 sockp->pcs_flags |= PCS_CARD_ISCARDBUS; 5512 #ifdef CARDBUS 5513 if (!pcic_load_cardbus(pcic, sockp)) { 5514 pcic_unload_cardbus(pcic, sockp); 5515 } 5516 5517 #else 5518 cmn_err(CE_NOTE, 5519 "32 bit Cardbus not supported in" 5520 " this device driver\n"); 5521 #endif 5522 } else { 5523 /* 5524 * Ignore the card 5525 */ 5526 cmn_err(CE_NOTE, 5527 "32 bit Cardbus not supported on this" 5528 " device\n"); 5529 } 5530 } else { 5531 cmn_err(CE_NOTE, 5532 "Unsupported PCMCIA card inserted\n"); 5533 } 5534 } 5535 syshw_send_signal(sockp->pcs_syshwsig); 5536 } else { 5537 do_debounce = B_TRUE; 5538 } 5539 } else { 5540 /* 5541 * It is possible to come through here if the system 5542 * starts up with cards already inserted. Do nothing 5543 * and don't worry about it. 5544 */ 5545 #ifdef PCIC_DEBUG 5546 pcic_err(pcic->dip, 5, 5547 "pcic%d: Odd card insertion indication on socket %d\n", 5548 ddi_get_instance(pcic->dip), 5549 sockp->pcs_socket); 5550 #endif 5551 } 5552 break; 5553 5554 default: 5555 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5556 /* 5557 * Someone has started to insert a card so delay a while. 5558 */ 5559 do_debounce = B_TRUE; 5560 break; 5561 } 5562 /* 5563 * Otherwise this is basically the same as not present 5564 * so fall through. 5565 */ 5566 5567 /* FALLTHRU */ 5568 case 0: 5569 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5570 if (pcic->pc_flags & PCF_CBPWRCTL) { 5571 pcic_putcb(pcic, CB_CONTROL, 0); 5572 } else { 5573 pcic_putb(pcic, sockp->pcs_socket, PCIC_POWER_CONTROL, 0); 5574 (void) pcic_getb(pcic, sockp->pcs_socket, 5575 PCIC_POWER_CONTROL); 5576 } 5577 #ifdef PCIC_DEBUG 5578 pcic_err(pcic->dip, 8, "Card removed\n"); 5579 #endif 5580 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5581 5582 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5583 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5584 if (pcic_do_removal && pcic->pc_callback) { 5585 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5586 PCE_CARD_REMOVAL, sockp->pcs_socket); 5587 } 5588 } 5589 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5590 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5591 sockp->pcs_flags |= PCS_CARD_CBREM; 5592 } 5593 sockp->pcs_flags |= PCS_CARD_REMOVED; 5594 5595 do_debounce = B_TRUE; 5596 } 5597 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5598 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5599 /* 5600 * Ensure that we do the unloading in the 5601 * debounce handler, that way we're not doing 5602 * nasty things in an interrupt handler. e.g. 5603 * a USB device will wait for data which will 5604 * obviously never come because we've 5605 * unplugged the device, but the wait will 5606 * wait forever because no interrupts can 5607 * come in... 5608 */ 5609 #ifdef CARDBUS 5610 pcic_unload_cardbus(pcic, sockp); 5611 /* pcic_dump_all(pcic); */ 5612 #endif 5613 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5614 } 5615 syshw_send_signal(sockp->pcs_syshwsig); 5616 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5617 } 5618 break; 5619 } /* switch */ 5620 5621 if (do_debounce) { 5622 /* 5623 * Delay doing 5624 * anything for a while so that things can settle 5625 * down a little. Interrupts are already disabled. 5626 * Reset the state and we'll reevaluate the 5627 * whole kit 'n kaboodle when the timeout fires 5628 */ 5629 #ifdef PCIC_DEBUG 5630 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5631 "socket %d.%d\n", 5632 ddi_get_instance(pcic->dip), 5633 sockp->pcs_socket); 5634 #endif 5635 sockp->pcs_debounce_id = pcic_add_debqueue(sockp, debounce_time); 5636 5637 /* 5638 * We bug out here without re-enabling interrupts. They will 5639 * be re-enabled when the debounce timeout swings through 5640 * here. 5641 */ 5642 return; 5643 } 5644 5645 /* 5646 * Turn on Card detect interrupts. Other interrupts will be 5647 * enabled during set_socket calls. 5648 * 5649 * Note that set_socket only changes interrupt settings when there 5650 * is a card present. 5651 */ 5652 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5653 irq |= PCIC_CD_DETECT; 5654 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5655 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5656 5657 /* Out from debouncing state */ 5658 sockp->pcs_flags &= ~PCS_DEBOUNCING; 5659 5660 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5661 } 5662 5663 /* 5664 * pcic_getb() 5665 * get an I/O byte based on the yardware decode method 5666 */ 5667 static uint8_t 5668 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5669 { 5670 int work; 5671 5672 #if defined(PCIC_DEBUG) 5673 if (pcic_debug == 0x7fff) { 5674 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5675 (void *)pcic, socket, reg); 5676 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5677 pcic->pc_io_type, (void *)pcic->handle, 5678 (void *)pcic->ioaddr); 5679 } 5680 #endif 5681 5682 switch (pcic->pc_io_type) { 5683 case PCIC_IO_TYPE_YENTA: 5684 return (ddi_get8(pcic->handle, 5685 pcic->ioaddr + CB_R2_OFFSET + reg)); 5686 default: 5687 work = (socket * PCIC_SOCKET_1) | reg; 5688 ddi_put8(pcic->handle, pcic->ioaddr, work); 5689 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5690 } 5691 } 5692 5693 static void 5694 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5695 { 5696 int work; 5697 5698 #if defined(PCIC_DEBUG) 5699 if (pcic_debug == 0x7fff) { 5700 cmn_err(CE_CONT, 5701 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5702 (void *)pcic, socket, reg, value); 5703 cmn_err(CE_CONT, 5704 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5705 pcic->pc_io_type, (void *)pcic->handle, 5706 (void *)pcic->ioaddr); 5707 } 5708 #endif 5709 5710 5711 switch (pcic->pc_io_type) { 5712 case PCIC_IO_TYPE_YENTA: 5713 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5714 value); 5715 break; 5716 default: 5717 work = (socket * PCIC_SOCKET_1) | reg; 5718 ddi_put8(pcic->handle, pcic->ioaddr, work); 5719 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5720 break; 5721 } 5722 } 5723 5724 /* 5725 * chip identification functions 5726 */ 5727 5728 /* 5729 * chip identification: Cirrus Logic PD6710/6720/6722 5730 */ 5731 static int 5732 pcic_ci_cirrus(pcicdev_t *pcic) 5733 { 5734 int value1, value2; 5735 5736 /* Init the CL id mode */ 5737 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5738 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5739 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5740 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5741 5742 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5743 (value2 & PCIC_CI_ID) == 0) { 5744 /* chip is a Cirrus Logic and not Intel */ 5745 pcic->pc_type = PCIC_CL_PD6710; 5746 if (value1 & PCIC_CI_SLOTS) 5747 pcic->pc_chipname = PCIC_TYPE_PD6720; 5748 else 5749 pcic->pc_chipname = PCIC_TYPE_PD6710; 5750 /* now fine tune things just in case a 6722 */ 5751 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5752 if (value1 == 0) { 5753 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5754 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5755 if (value1 == 0x55) { 5756 pcic->pc_chipname = PCIC_TYPE_PD6722; 5757 pcic->pc_type = PCIC_CL_PD6722; 5758 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5759 } 5760 } 5761 return (1); 5762 } 5763 return (0); 5764 } 5765 5766 /* 5767 * chip identification: Vadem (VG365/465/468/469) 5768 */ 5769 5770 static void 5771 pcic_vadem_enable(pcicdev_t *pcic) 5772 { 5773 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5774 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5775 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5776 } 5777 5778 static int 5779 pcic_ci_vadem(pcicdev_t *pcic) 5780 { 5781 int value; 5782 5783 pcic_vadem_enable(pcic); 5784 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5785 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5786 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5787 (value | PCIC_VADEM_D3) || 5788 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5789 PCIC_VADEM_469) { 5790 int vadem, new; 5791 pcic_vadem_enable(pcic); 5792 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5793 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5794 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5795 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5796 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5797 5798 /* want to lock but leave mouse or other on */ 5799 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5800 switch (value & PCIC_REV_MASK) { 5801 case PCIC_VADEM_365: 5802 pcic->pc_chipname = PCIC_VG_365; 5803 pcic->pc_type = PCIC_VADEM; 5804 break; 5805 case PCIC_VADEM_465: 5806 pcic->pc_chipname = PCIC_VG_465; 5807 pcic->pc_type = PCIC_VADEM; 5808 pcic->pc_flags |= PCF_1SOCKET; 5809 break; 5810 case PCIC_VADEM_468: 5811 pcic->pc_chipname = PCIC_VG_468; 5812 pcic->pc_type = PCIC_VADEM; 5813 break; 5814 case PCIC_VADEM_469: 5815 pcic->pc_chipname = PCIC_VG_469; 5816 pcic->pc_type = PCIC_VADEM_VG469; 5817 break; 5818 } 5819 return (1); 5820 } 5821 return (0); 5822 } 5823 5824 /* 5825 * chip identification: Ricoh 5826 */ 5827 static int 5828 pcic_ci_ricoh(pcicdev_t *pcic) 5829 { 5830 int value; 5831 5832 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5833 switch (value) { 5834 case PCIC_RF_296: 5835 pcic->pc_type = PCIC_RICOH; 5836 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5837 return (1); 5838 case PCIC_RF_396: 5839 pcic->pc_type = PCIC_RICOH; 5840 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5841 return (1); 5842 } 5843 return (0); 5844 } 5845 5846 5847 /* 5848 * set up available address spaces in busra 5849 */ 5850 static void 5851 pcic_init_assigned(dev_info_t *dip) 5852 { 5853 pcm_regs_t *pcic_avail_p; 5854 pci_regspec_t *pci_avail_p, *regs; 5855 int len, entries, rlen; 5856 dev_info_t *pdip; 5857 5858 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5859 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5860 /* 5861 * found "available" property at the cardbus/pcmcia node 5862 * need to translate address space entries from pcmcia 5863 * format to pci format 5864 */ 5865 entries = len / sizeof (pcm_regs_t); 5866 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5867 KM_SLEEP); 5868 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5869 entries) == DDI_SUCCESS) 5870 (void) pci_resource_setup_avail(dip, pci_avail_p, 5871 entries); 5872 kmem_free(pcic_avail_p, len); 5873 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5874 return; 5875 } 5876 5877 /* 5878 * "legacy" platforms will have "available" property in pci node 5879 */ 5880 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5881 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5882 "available", (caddr_t)&pci_avail_p, &len) == 5883 DDI_PROP_SUCCESS) { 5884 /* (void) pci_resource_setup(pdip); */ 5885 kmem_free(pci_avail_p, len); 5886 break; 5887 } 5888 } 5889 5890 if (pdip == NULL) { 5891 int len; 5892 char bus_type[16] = "(unknown)"; 5893 dev_info_t *par; 5894 5895 cmn_err(CE_CONT, 5896 "?pcic_init_assigned: no available property for pcmcia\n"); 5897 5898 /* 5899 * This code is taken from pci_resource_setup() but does 5900 * not attempt to use the "available" property to populate 5901 * the ndi maps that are created. 5902 * The fact that we will actually 5903 * free some resource below (that was allocated by OBP) 5904 * should be enough to be going on with. 5905 */ 5906 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5907 len = sizeof (bus_type); 5908 5909 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5910 PROP_LEN_AND_VAL_BUF, 5911 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5912 "device_type", 5913 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5914 (strcmp(bus_type, "pci") == 0)) 5915 break; 5916 } 5917 if (par != NULL && 5918 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5919 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5920 par = NULL; 5921 } else { 5922 #ifdef CARDBUS 5923 cardbus_bus_range_t *bus_range; 5924 int k; 5925 5926 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5927 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5928 if (bus_range->lo != bus_range->hi) 5929 pcic_err(pdip, 9, "allowable bus range is " 5930 "%u->%u\n", bus_range->lo, bus_range->hi); 5931 else { 5932 pcic_err(pdip, 0, 5933 "!No spare PCI bus numbers, range is " 5934 "%u->%u, cardbus isn't usable\n", 5935 bus_range->lo, bus_range->hi); 5936 } 5937 kmem_free(bus_range, k); 5938 } else 5939 pcic_err(pdip, 0, "!No bus-range property seems to " 5940 "have been set up\n"); 5941 #endif 5942 /* 5943 * Have a valid parent with the "available" property 5944 */ 5945 (void) pci_resource_setup(pdip); 5946 } 5947 5948 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5949 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5950 "assigned-addresses", 5951 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5952 ra_return_t ra; 5953 5954 /* 5955 * On the UltraBook IIi the ranges are assigned under 5956 * openboot. If we don't free them here the first I/O 5957 * space that can be used is up above 0x10000 which 5958 * doesn't work for this driver due to restrictions 5959 * on the PCI I/O addresses the controllers can cope with. 5960 * They are never going to be used by anything else 5961 * so free them up to the general pool. AG. 5962 */ 5963 pcic_err(dip, 1, "Free assigned addresses\n"); 5964 5965 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5966 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5967 regs[0].pci_size_low == 0x1000000) { 5968 ra.ra_addr_lo = regs[0].pci_phys_low; 5969 ra.ra_len = regs[0].pci_size_low; 5970 (void) pcmcia_free_mem(dip, &ra); 5971 } 5972 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5973 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5974 (regs[1].pci_size_low == 0x8000 || 5975 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5976 { 5977 ra.ra_addr_lo = regs[1].pci_phys_low; 5978 ra.ra_len = regs[1].pci_size_low; 5979 (void) pcmcia_free_io(dip, &ra); 5980 } 5981 kmem_free((caddr_t)regs, rlen); 5982 } 5983 } 5984 5985 /* 5986 * translate "available" from pcmcia format to pci format 5987 */ 5988 static int 5989 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 5990 pci_regspec_t *pci_p, int entries) 5991 { 5992 int i, range_len, range_entries; 5993 pcic_ranges_t *pcic_range_p; 5994 5995 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 5996 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 5997 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 5998 "no ranges property for pcmcia\n"); 5999 return (DDI_FAILURE); 6000 } 6001 6002 range_entries = range_len / sizeof (pcic_ranges_t); 6003 6004 /* for each "available" entry to be translated */ 6005 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 6006 int j; 6007 pcic_ranges_t *range_p = pcic_range_p; 6008 pci_p->pci_phys_hi = -1u; /* default invalid value */ 6009 6010 /* for each "ranges" entry to be searched */ 6011 for (j = 0; j < range_entries; j++, range_p++) { 6012 uint64_t range_end = range_p->pcic_range_caddrlo + 6013 range_p->pcic_range_size; 6014 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 6015 6016 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 6017 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 6018 (range_end < avail_end)) 6019 continue; 6020 6021 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 6022 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 6023 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 6024 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 6025 pci_p->pci_size_hi = 0; 6026 pci_p->pci_size_low = pcic_p->phys_len; 6027 } 6028 } 6029 kmem_free(pcic_range_p, range_len); 6030 return (DDI_SUCCESS); 6031 } 6032 6033 static int 6034 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 6035 { 6036 if (getminor(*dev) == SYSHW_MINOR) 6037 return (syshw_open(dev, flag, otyp, cred)); 6038 #ifdef CARDBUS 6039 if (cardbus_is_cb_minor(*dev)) 6040 return (cardbus_open(dev, flag, otyp, cred)); 6041 #endif 6042 return (EINVAL); 6043 } 6044 6045 static int 6046 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 6047 { 6048 if (getminor(dev) == SYSHW_MINOR) 6049 return (syshw_close(dev, flag, otyp, cred)); 6050 #ifdef CARDBUS 6051 if (cardbus_is_cb_minor(dev)) 6052 return (cardbus_close(dev, flag, otyp, cred)); 6053 #endif 6054 return (EINVAL); 6055 } 6056 6057 static int 6058 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 6059 int *rval) 6060 { 6061 if (getminor(dev) == SYSHW_MINOR) 6062 return (syshw_ioctl(dev, cmd, arg, mode, cred, rval)); 6063 #ifdef CARDBUS 6064 if (cardbus_is_cb_minor(dev)) 6065 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6066 #endif 6067 return (EINVAL); 6068 } 6069 6070 6071 static boolean_t 6072 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6073 { 6074 uint32_t present_state; 6075 dev_info_t *dip = pcic->dip; 6076 set_socket_t s; 6077 get_socket_t g; 6078 boolean_t retval; 6079 unsigned vccLevel; 6080 6081 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6082 6083 pcic_mutex_exit(&pcic->pc_lock); 6084 6085 bzero(&s, sizeof (set_socket_t)); 6086 s.socket = sockp->pcs_socket; 6087 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6088 s.IFType = IF_CARDBUS; 6089 s.State = (unsigned)~0; 6090 6091 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6092 if (present_state & PCIC_VCC_3VCARD) 6093 s.VccLevel = PCIC_VCC_3VLEVEL; 6094 else if (present_state & PCIC_VCC_5VCARD) 6095 s.VccLevel = PCIC_VCC_5VLEVEL; 6096 else { 6097 cmn_err(CE_CONT, 6098 "pcic_load_cardbus: unsupported card voltage\n"); 6099 goto failure; 6100 } 6101 vccLevel = s.VccLevel; 6102 s.Vpp1Level = s.Vpp2Level = 0; 6103 6104 if (pcic_set_socket(dip, &s) != SUCCESS) 6105 goto failure; 6106 6107 if (pcic_reset_socket(dip, sockp->pcs_socket, 6108 RESET_MODE_CARD_ONLY) != SUCCESS) 6109 goto failure; 6110 6111 bzero(&g, sizeof (get_socket_t)); 6112 g.socket = sockp->pcs_socket; 6113 if (pcic_get_socket(dip, &g) != SUCCESS) 6114 goto failure; 6115 6116 bzero(&s, sizeof (set_socket_t)); 6117 s.socket = sockp->pcs_socket; 6118 s.SCIntMask = SBM_CD; 6119 s.IREQRouting = g.IRQRouting; 6120 s.IFType = g.IFType; 6121 s.CtlInd = g.CtlInd; 6122 s.State = (unsigned)~0; 6123 s.VccLevel = vccLevel; 6124 s.Vpp1Level = s.Vpp2Level = 0; 6125 6126 if (pcic_set_socket(dip, &s) != SUCCESS) 6127 goto failure; 6128 6129 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6130 goto exit; 6131 6132 failure: 6133 retval = B_FALSE; 6134 6135 exit: 6136 pcic_mutex_enter(&pcic->pc_lock); 6137 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6138 retval ? "success" : "failure"); 6139 return (retval); 6140 } 6141 6142 static void 6143 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6144 { 6145 dev_info_t *dip = pcic->dip; 6146 set_socket_t s; 6147 6148 pcic_mutex_exit(&pcic->pc_lock); 6149 6150 cardbus_unload_cardbus(dip); 6151 6152 bzero(&s, sizeof (set_socket_t)); 6153 s.socket = sockp->pcs_socket; 6154 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6155 s.IREQRouting = 0; 6156 s.IFType = IF_MEMORY; 6157 s.CtlInd = 0; 6158 s.State = 0; 6159 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6160 6161 (void) pcic_set_socket(dip, &s); 6162 6163 pcic_mutex_enter(&pcic->pc_lock); 6164 } 6165 6166 static uint32_t 6167 pcic_getcb(pcicdev_t *pcic, int reg) 6168 { 6169 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6170 6171 return (ddi_get32(pcic->handle, 6172 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6173 } 6174 6175 static void 6176 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6177 { 6178 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6179 6180 ddi_put32(pcic->handle, 6181 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6182 } 6183 6184 static void 6185 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6186 { 6187 uint8_t value; 6188 uint16_t brdgctl; 6189 6190 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6191 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6192 6193 switch (pcic->pc_type) { 6194 case PCIC_INTEL_i82092: 6195 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6196 PCIC_82092_INT_ENABLE); 6197 break; 6198 case PCIC_O2_OZ6912: 6199 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6200 value |= 0x8; 6201 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6202 break; 6203 case PCIC_CL_PD6832: 6204 case PCIC_TI_PCI1250: 6205 case PCIC_TI_PCI1221: 6206 case PCIC_TI_PCI1225: 6207 case PCIC_TI_PCI1410: 6208 case PCIC_ENE_1410: 6209 case PCIC_TI_PCI1510: 6210 case PCIC_TI_PCI1520: 6211 case PCIC_TI_PCI1420: 6212 case PCIC_ENE_1420: 6213 /* route card functional interrupts to PCI interrupts */ 6214 brdgctl = ddi_get16(pcic->cfg_handle, 6215 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6216 pcic_err(NULL, 1, 6217 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6218 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6219 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6220 ddi_put16(pcic->cfg_handle, 6221 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6222 brdgctl); 6223 /* Flush the write */ 6224 (void) ddi_get16(pcic->cfg_handle, 6225 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6226 break; 6227 default: 6228 break; 6229 } 6230 } 6231 6232 static void 6233 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6234 { 6235 uint8_t value; 6236 uint16_t brdgctl; 6237 6238 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6239 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6240 6241 switch (pcic->pc_type) { 6242 case PCIC_INTEL_i82092: 6243 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6244 PCIC_82092_INT_DISABLE); 6245 break; 6246 case PCIC_O2_OZ6912: 6247 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6248 value &= ~0x8; 6249 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6250 /* Flush the write */ 6251 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6252 break; 6253 case PCIC_CL_PD6832: 6254 case PCIC_TI_PCI1250: 6255 case PCIC_TI_PCI1221: 6256 case PCIC_TI_PCI1225: 6257 case PCIC_TI_PCI1410: 6258 case PCIC_ENE_1410: 6259 case PCIC_TI_PCI1510: 6260 case PCIC_TI_PCI1520: 6261 case PCIC_TI_PCI1420: 6262 case PCIC_ENE_1420: 6263 /* 6264 * This maps I/O interrupts to ExCA which 6265 * have been turned off by the write to 6266 * PCIC_INTERRUPT above. It would appear to 6267 * be the only way to actually turn I/O Ints off 6268 * while retaining CS Ints. 6269 */ 6270 brdgctl = ddi_get16(pcic->cfg_handle, 6271 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6272 pcic_err(NULL, 1, 6273 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6274 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6275 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6276 ddi_put16(pcic->cfg_handle, 6277 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6278 brdgctl); 6279 /* Flush the write */ 6280 (void) ddi_get16(pcic->cfg_handle, 6281 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6282 break; 6283 default: 6284 break; 6285 } 6286 } 6287 6288 static void 6289 pcic_cb_enable_intr(dev_info_t *dip) 6290 { 6291 anp_t *anp = ddi_get_driver_private(dip); 6292 pcicdev_t *pcic = anp->an_private; 6293 6294 mutex_enter(&pcic->pc_lock); 6295 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6296 mutex_exit(&pcic->pc_lock); 6297 } 6298 6299 static void 6300 pcic_cb_disable_intr(dev_info_t *dip) 6301 { 6302 anp_t *anp = ddi_get_driver_private(dip); 6303 pcicdev_t *pcic = anp->an_private; 6304 6305 mutex_enter(&pcic->pc_lock); 6306 pcic_disable_io_intr(pcic, 0); 6307 mutex_exit(&pcic->pc_lock); 6308 } 6309 6310 static int 6311 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6312 { 6313 int nerr = 0; 6314 if (e & PCI_STAT_PERROR) { 6315 nerr++; 6316 cmn_err(CE_CONT, "detected parity error.\n"); 6317 } 6318 if (e & PCI_STAT_S_SYSERR) { 6319 nerr++; 6320 if (bridge_secondary) 6321 cmn_err(CE_CONT, "received system error.\n"); 6322 else 6323 cmn_err(CE_CONT, "signalled system error.\n"); 6324 } 6325 if (e & PCI_STAT_R_MAST_AB) { 6326 nerr++; 6327 cmn_err(CE_CONT, "received master abort.\n"); 6328 } 6329 if (e & PCI_STAT_R_TARG_AB) 6330 cmn_err(CE_CONT, "received target abort.\n"); 6331 if (e & PCI_STAT_S_TARG_AB) 6332 cmn_err(CE_CONT, "signalled target abort\n"); 6333 if (e & PCI_STAT_S_PERROR) { 6334 nerr++; 6335 cmn_err(CE_CONT, "signalled parity error\n"); 6336 } 6337 return (nerr); 6338 } 6339 6340 #if defined(__sparc) 6341 static int 6342 pcic_fault(enum pci_fault_ops op, void *arg) 6343 { 6344 pcicdev_t *pcic = (pcicdev_t *)arg; 6345 ushort_t pci_cfg_stat = 6346 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6347 ushort_t pci_cfg_sec_stat = 6348 pci_config_get16(pcic->cfg_handle, 0x16); 6349 char nm[24]; 6350 int nerr = 0; 6351 6352 cardbus_dump_pci_config(pcic->dip); 6353 6354 switch (op) { 6355 case FAULT_LOG: 6356 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6357 ddi_get_instance(pcic->dip)); 6358 6359 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6360 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6361 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6362 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6363 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6364 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6365 return (nerr); 6366 case FAULT_POKEFINI: 6367 case FAULT_RESET: 6368 pci_config_put16(pcic->cfg_handle, 6369 PCI_CONF_STAT, pci_cfg_stat); 6370 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6371 break; 6372 case FAULT_POKEFLT: 6373 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6374 return (1); 6375 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6376 return (1); 6377 break; 6378 default: 6379 break; 6380 } 6381 return (DDI_SUCCESS); 6382 } 6383 #endif 6384 6385 static void 6386 pcic_delayed_resume(void *arg) 6387 { 6388 int i, j, interrupt; 6389 anp_t *pcic_nexus; 6390 pcicdev_t *pcic; 6391 6392 _NOTE(ARGUNUSED(arg)) 6393 6394 #if defined(PCIC_DEBUG) 6395 pcic_err(NULL, 6, "pcic_delayed_resume(): entered\n"); 6396 #endif 6397 for (j = 0; j <= pcic_maxinst; j++) { 6398 6399 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, j); 6400 if (!pcic_nexus) 6401 continue; 6402 pcic = (pcicdev_t *)pcic_nexus->an_private; 6403 if (!pcic) 6404 continue; 6405 6406 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6407 for (i = 0; i < pcic->pc_numsockets; i++) { 6408 /* Enable interrupts on PCI if needs be */ 6409 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6410 if (pcic->pc_flags & PCF_USE_SMI) 6411 interrupt |= PCIC_INTR_ENABLE; 6412 pcic_putb(pcic, i, PCIC_INTERRUPT, 6413 PCIC_RESET | interrupt); 6414 pcic->pc_sockets[i].pcs_debounce_id = 6415 pcic_add_debqueue(&pcic->pc_sockets[i], 6416 drv_usectohz(pcic_debounce_time)); 6417 } 6418 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6419 if (pcic_do_pcmcia_sr) 6420 (void) pcmcia_wait_insert(pcic->dip); 6421 } 6422 } 6423 6424 static void 6425 pcic_debounce(pcic_socket_t *pcs) 6426 { 6427 uint8_t status, stschng; 6428 6429 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6430 pcs->pcs_flags &= ~PCS_STARTING; 6431 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6432 PCIC_CARD_STATUS_CHANGE); 6433 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6434 PCIC_INTERFACE_STATUS); 6435 #ifdef PCIC_DEBUG 6436 pcic_err(pcs->pcs_pcic->dip, 8, 6437 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6438 "chg 0x%x flg 0x%x\n", 6439 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6440 status, stschng, pcs->pcs_flags); 6441 #endif 6442 6443 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6444 PCIC_CD_DETECT); 6445 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6446 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6447 } 6448 6449 static void 6450 pcic_deb_thread() 6451 { 6452 callb_cpr_t cprinfo; 6453 struct debounce *debp; 6454 clock_t lastt; 6455 6456 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6457 callb_generic_cpr, "pcic debounce thread"); 6458 mutex_enter(&pcic_deb_mtx); 6459 while (pcic_deb_threadid) { 6460 while (pcic_deb_queue) { 6461 #ifdef PCIC_DEBUG 6462 pcic_dump_debqueue("Thread"); 6463 #endif 6464 debp = pcic_deb_queue; 6465 (void) drv_getparm(LBOLT, &lastt); 6466 if (lastt >= debp->expire) { 6467 pcic_deb_queue = debp->next; 6468 mutex_exit(&pcic_deb_mtx); 6469 pcic_debounce(debp->pcs); 6470 mutex_enter(&pcic_deb_mtx); 6471 kmem_free(debp, sizeof (*debp)); 6472 } else { 6473 (void) cv_timedwait(&pcic_deb_cv, 6474 &pcic_deb_mtx, debp->expire); 6475 } 6476 } 6477 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6478 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6479 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6480 } 6481 pcic_deb_threadid = (kthread_t *)1; 6482 cv_signal(&pcic_deb_cv); 6483 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6484 thread_exit(); 6485 } 6486 6487 static void * 6488 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6489 { 6490 clock_t lbolt; 6491 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6492 6493 (void) drv_getparm(LBOLT, &lbolt); 6494 dbp = kmem_alloc(sizeof (struct debounce), KM_NOSLEEP); 6495 6496 dbp->expire = lbolt + clocks; 6497 dbp->pcs = pcs; 6498 mutex_enter(&pcic_deb_mtx); 6499 while (*dbpp) { 6500 if (dbp->expire > (*dbpp)->expire) 6501 dbpp = &((*dbpp)->next); 6502 else 6503 break; 6504 } 6505 dbp->next = *dbpp; 6506 *dbpp = dbp; 6507 #ifdef PCIC_DEBUG 6508 pcic_dump_debqueue("Add"); 6509 #endif 6510 cv_signal(&pcic_deb_cv); 6511 mutex_exit(&pcic_deb_mtx); 6512 return (dbp); 6513 } 6514 6515 static void 6516 pcic_rm_debqueue(void *id) 6517 { 6518 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6519 6520 dbp = (struct debounce *)id; 6521 mutex_enter(&pcic_deb_mtx); 6522 while (*dbpp) { 6523 if (*dbpp == dbp) { 6524 *dbpp = dbp->next; 6525 kmem_free(dbp, sizeof (*dbp)); 6526 #ifdef PCIC_DEBUG 6527 pcic_dump_debqueue("Remove"); 6528 #endif 6529 cv_signal(&pcic_deb_cv); 6530 mutex_exit(&pcic_deb_mtx); 6531 return; 6532 } 6533 dbpp = &((*dbpp)->next); 6534 } 6535 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6536 mutex_exit(&pcic_deb_mtx); 6537 } 6538 6539 6540 static int pcic_powerdelay = 0; 6541 6542 static int 6543 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6544 { 6545 int ind, value, orig_pwrctl; 6546 6547 /* power setup -- if necessary */ 6548 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6549 6550 #if defined(PCIC_DEBUG) 6551 pcic_err(pcic->dip, 6, 6552 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6553 socket, powerlevel, orig_pwrctl); 6554 #endif 6555 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6556 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6557 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6558 if (powerlevel != orig_pwrctl) { 6559 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6560 int ifs; 6561 /* 6562 * set power to socket 6563 * note that the powerlevel was calculated earlier 6564 */ 6565 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6566 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6567 6568 /* 6569 * this second write to the power control register 6570 * is needed to resolve a problem on 6571 * the IBM ThinkPad 750 6572 * where the first write doesn't latch. 6573 * The second write appears to always work and 6574 * doesn't hurt the operation of other chips 6575 * so we can just use it -- this is good since we can't 6576 * determine what chip the 750 actually uses 6577 * (I suspect an early Ricoh). 6578 */ 6579 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6580 6581 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6582 pcic_mswait(pcic, socket, pcic_powerdelay); 6583 #if defined(PCIC_DEBUG) 6584 pcic_err(pcic->dip, 8, 6585 "\tpowerlevel reg = %x (ifs %x)\n", 6586 value, pcic_getb(pcic, socket, 6587 PCIC_INTERFACE_STATUS)); 6588 pcic_err(pcic->dip, 8, 6589 "CBus regs: PS 0x%x, Control 0x%x\n", 6590 pcic_getcb(pcic, CB_PRESENT_STATE), 6591 pcic_getcb(pcic, CB_CONTROL)); 6592 #endif 6593 /* 6594 * since power was touched, make sure it says it 6595 * is on. This lets it become stable. 6596 */ 6597 for (ind = 0; ind < 20; ind++) { 6598 ifs = pcic_getb(pcic, socket, 6599 PCIC_INTERFACE_STATUS); 6600 if (ifs & PCIC_POWER_ON) 6601 break; 6602 else { 6603 pcic_putb(pcic, socket, 6604 PCIC_POWER_CONTROL, 0); 6605 (void) pcic_getb(pcic, socket, 6606 PCIC_POWER_CONTROL); 6607 pcic_mswait(pcic, socket, 40); 6608 if (ind == 10) { 6609 pcic_putcb(pcic, CB_EVENT_FORCE, 6610 CB_EF_CVTEST); 6611 pcic_mswait(pcic, socket, 100); 6612 } 6613 pcic_putb(pcic, socket, 6614 PCIC_POWER_CONTROL, 6615 powerlevel & ~POWER_OUTPUT_ENABLE); 6616 (void) pcic_getb(pcic, socket, 6617 PCIC_POWER_CONTROL); 6618 pcic_mswait(pcic, socket, 6619 pcic_powerdelay); 6620 pcic_putb(pcic, socket, 6621 PCIC_POWER_CONTROL, powerlevel); 6622 (void) pcic_getb(pcic, socket, 6623 PCIC_POWER_CONTROL); 6624 pcic_mswait(pcic, socket, 6625 pcic_powerdelay); 6626 } 6627 } 6628 6629 if (!(ifs & PCIC_POWER_ON)) { 6630 cmn_err(CE_WARN, 6631 "pcic socket %d: Power didn't get turned" 6632 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6633 "misc1 0x%x igc 0x%x ind %d\n", 6634 socket, ifs, 6635 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6636 orig_pwrctl, 6637 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6638 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6639 ind); 6640 return (BAD_VCC); 6641 } 6642 #if defined(PCIC_DEBUG) 6643 pcic_err(pcic->dip, 8, 6644 "\tind = %d, if status %x pwrc 0x%x " 6645 "misc1 0x%x igc 0x%x\n", 6646 ind, ifs, 6647 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6648 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6649 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6650 #endif 6651 } else { 6652 /* explicitly turned off the power */ 6653 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6654 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6655 } 6656 } 6657 return (SUCCESS); 6658 } 6659 6660 static int pcic_cbdoreset_during_poweron = 1; 6661 static int 6662 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6663 { 6664 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6665 int ind, iobits; 6666 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6667 6668 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6669 6670 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6671 cbctl |= pcic_cbv_levels[ind]; 6672 6673 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6674 cbctl |= (pcic_cbv_levels[ind]<<4); 6675 6676 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6677 6678 #if defined(PCIC_DEBUG) 6679 pcic_err(pcic->dip, 6, 6680 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6681 "cbctl 0x%x->0x%x\n", 6682 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6683 #endif 6684 if (cbctl != orig_cbctl) { 6685 if (pcic_cbdoreset_during_poweron && 6686 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6687 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6688 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits & ~PCIC_RESET); 6689 } 6690 pcic_putcb(pcic, CB_CONTROL, cbctl); 6691 6692 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6693 pcic_mswait(pcic, socket, pcic_powerdelay); 6694 return (SUCCESS); 6695 } 6696 for (ind = 0; ind < 20; ind++) { 6697 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6698 6699 if (cbstev & CB_SE_POWER_CYCLE) { 6700 6701 /* 6702 * delay 400 ms: though the standard defines that the Vcc 6703 * set-up time is 20 ms, some PC-Card bridge requires longer 6704 * duration. 6705 * Note: We should check the status AFTER the delay to give time 6706 * for things to stabilize. 6707 */ 6708 pcic_mswait(pcic, socket, 400); 6709 6710 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6711 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6712 /* break; */ 6713 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6714 } 6715 if (cbctl & CB_PS_BADVCC) { 6716 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6717 break; 6718 } 6719 6720 #if defined(PCIC_DEBUG) 6721 pcic_err(pcic->dip, 8, 6722 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6723 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6724 cbctl, orig_cbctl); 6725 #endif 6726 if (pcic_cbdoreset_during_poweron && 6727 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6728 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6729 } 6730 return (SUCCESS); 6731 } 6732 pcic_mswait(pcic, socket, 40); 6733 } 6734 if (pcic_cbdoreset_during_poweron && 6735 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6736 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6737 } 6738 cmn_err(CE_WARN, 6739 "pcic socket %d: Power didn't get turned on/off!\n" 6740 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6741 "vcc %d vpp1 %d", socket, cbstev, 6742 pcic_getcb(pcic, CB_PRESENT_STATE), 6743 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6744 return (BAD_VCC); 6745 } 6746 return (SUCCESS); 6747 } 6748 6749 static int pcic_do_pprintf = 0; 6750 6751 static void 6752 pcic_dump_debqueue(char *msg) 6753 { 6754 struct debounce *debp = pcic_deb_queue; 6755 clock_t lbolt; 6756 6757 (void) drv_getparm(LBOLT, &lbolt); 6758 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6759 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6760 while (debp) { 6761 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6762 (void *) debp, (int)debp->expire, (void *) debp->next, 6763 debp->pcs->pcs_debounce_id); 6764 debp = debp->next; 6765 } 6766 } 6767 6768 6769 /* PRINTFLIKE3 */ 6770 static void 6771 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6772 { 6773 if (pcic_debug && (level <= pcic_debug)) { 6774 va_list adx; 6775 int instance; 6776 char buf[256]; 6777 const char *name; 6778 #if !defined(PCIC_DEBUG) 6779 int ce; 6780 char qmark = 0; 6781 6782 if (level <= 3) 6783 ce = CE_WARN; 6784 else 6785 ce = CE_CONT; 6786 if (level == 4) 6787 qmark = 1; 6788 #endif 6789 6790 if (dip) { 6791 instance = ddi_get_instance(dip); 6792 /* name = ddi_binding_name(dip); */ 6793 name = ddi_driver_name(dip); 6794 } else { 6795 instance = 0; 6796 name = ""; 6797 } 6798 6799 va_start(adx, fmt); 6800 (void) vsprintf(buf, fmt, adx); 6801 va_end(adx); 6802 6803 #if defined(PCIC_DEBUG) 6804 if (pcic_do_pprintf) { 6805 if (dip) { 6806 if (instance >= 0) 6807 prom_printf("%s(%d),0x%p: %s", name, 6808 instance, dip, buf); 6809 else 6810 prom_printf("%s,0x%p: %s", 6811 name, dip, buf); 6812 } else 6813 prom_printf(buf); 6814 } else { 6815 if (dip) { 6816 if (instance >= 0) 6817 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6818 name, instance, (void *) dip, buf); 6819 else 6820 cmn_err(CE_CONT, "%s,0x%p: %s", 6821 name, (void *) dip, buf); 6822 } else 6823 cmn_err(CE_CONT, buf); 6824 } 6825 #else 6826 if (dip) 6827 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6828 instance, buf); 6829 else 6830 cmn_err(ce, qmark ? "?%s" : buf, buf); 6831 #endif 6832 } 6833 } 6834 6835 6836 static void 6837 pcic_syshw_cardstate(syshw_t *item, void *arg) 6838 { 6839 pcic_socket_t *pcs = (pcic_socket_t *)arg; 6840 6841 if (pcs->pcs_flags & PCS_CARD_PRESENT) { 6842 item->state = B_TRUE; 6843 if (pcs->pcs_flags & PCS_CARD_IS16BIT) 6844 item->values[0] = 1; 6845 else if (pcs->pcs_flags & PCS_CARD_ISCARDBUS) 6846 item->values[0] = 2; 6847 else 6848 item->values[0] = 0; 6849 } else { 6850 item->state = B_FALSE; 6851 item->values[0] = 0; 6852 } 6853 } 6854 6855 /* 6856 * Tadpole additional for the syshw interface used to control the 6857 * start/stop switch which is physically linked to the GPIO1 pin 6858 * on the 1250a. 6859 */ 6860 6861 #define CLIENT_CALLED 0x8000000 6862 #define NCE_EVENT_MASK 0xffff 6863 6864 typedef struct _client { 6865 pid_t pid; /* set by kernel */ 6866 int flags; /* NCE_REGISTER... */ 6867 int priority; /* >100 unless root */ 6868 int events; /* pending event flags */ 6869 int event_sig; /* SIG... etc */ 6870 struct _client *next; /* set by kernel */ 6871 struct _client *prev; /* set by kernel */ 6872 } client_data; 6873 6874 static client_data *cl_data; 6875 static int n_clients; 6876 static kmutex_t client_mtx, intr_mtx; 6877 6878 static void delete_client(int); 6879 6880 #ifdef VOYAGER 6881 static uint32_t runstop_sig; 6882 static ddi_softintr_t softint_id; 6883 static uchar_t softint_flag; 6884 static int switch_debounce_time = 100; /* in milliseconds */ 6885 static timeout_id_t switch_to_id; 6886 6887 static syshw_t syshw_run_stop = { 6888 0, "Run/Stop", SH_SWITCH, 6889 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID, 6890 B_FALSE, { 0 } }; 6891 6892 static void 6893 syshw_get_run_stop(syshw_t *item, void *arg) 6894 { 6895 pcicdev_t *pcic = (pcicdev_t *)arg; 6896 6897 if (ddi_get8(pcic->cfg_handle, 6898 pcic->cfgaddr + PCIC_GPIO1_REG) & PCIC_GPIO_DIN) 6899 item->state = B_TRUE; 6900 else 6901 item->state = B_FALSE; 6902 } 6903 6904 6905 #endif 6906 6907 static void 6908 syshw_attach(pcicdev_t *pcic) 6909 { 6910 if (ddi_get_instance(pcic->dip) != 0) 6911 return; 6912 6913 #ifdef VOYAGER 6914 if (pcic->pc_type == PCIC_TI_PCI1250) { 6915 6916 /* 6917 * Only setup run/stop on a Voyager. 6918 * This is currently defined as 6919 * a TI1250 on a SPARC architecture. May have to make this a 6920 * property definition in the future. 6921 */ 6922 if (ddi_add_softintr(pcic->dip, 6923 DDI_SOFTINT_LOW, &softint_id, 6924 NULL, NULL, syshw_intr, 6925 (caddr_t)pcic) == DDI_SUCCESS) { 6926 runstop_sig = syshw_add2map(&syshw_run_stop, 6927 syshw_get_run_stop, pcic); 6928 mutex_init(&intr_mtx, NULL, MUTEX_DRIVER, 6929 pcic->pc_pri); 6930 ddi_put8(pcic->cfg_handle, 6931 pcic->cfgaddr + PCIC_GPIO1_REG, 6932 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | 6933 PCIC_GPIO_DELTA); 6934 } 6935 } 6936 #endif 6937 mutex_init(&client_mtx, "syshw client", MUTEX_DRIVER, NULL); 6938 (void) ddi_create_minor_node(pcic->dip, "syshw", S_IFCHR, 6939 SYSHW_MINOR, NULL, NULL); 6940 } 6941 6942 static void 6943 syshw_detach(pcicdev_t *pcic) 6944 { 6945 #ifdef VOYAGER 6946 if (pcic->pc_type == PCIC_TI_PCI1250) { 6947 pcic_mutex_enter(&intr_mtx); 6948 6949 /* 6950 * Turn off this interrupt. 6951 */ 6952 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6953 PCIC_GPIO_FINPUT); 6954 6955 if (switch_to_id) 6956 (void) untimeout(switch_to_id); 6957 switch_to_id = 0; 6958 softint_flag = 0; 6959 6960 pcic_mutex_exit(&intr_mtx); 6961 ddi_remove_softintr(softint_id); 6962 mutex_destroy(&intr_mtx); 6963 } 6964 #endif 6965 6966 ddi_remove_minor_node(pcic->dip, NULL); 6967 mutex_destroy(&client_mtx); 6968 } 6969 6970 static void 6971 syshw_resume(pcicdev_t *pcic) 6972 { 6973 #ifdef VOYAGER 6974 if (pcic->pc_type == PCIC_TI_PCI1250) { 6975 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6976 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | PCIC_GPIO_DELTA); 6977 } 6978 #else 6979 _NOTE(ARGUNUSED(pcic)) 6980 #endif 6981 } 6982 6983 #ifdef VOYAGER 6984 static uint_t 6985 syshw_intr_hi(pcicdev_t *pcic) 6986 { 6987 uchar_t regval; 6988 6989 if (pcic->pc_type != PCIC_TI_PCI1250) 6990 return (DDI_INTR_UNCLAIMED); 6991 6992 regval = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG); 6993 if (regval & PCIC_GPIO_DELTA) { 6994 pcic_mutex_enter(&intr_mtx); 6995 if (softint_flag == 0 && switch_to_id == 0) { 6996 softint_flag = 1; 6997 ddi_trigger_softintr(softint_id); 6998 } 6999 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 7000 regval); 7001 pcic_mutex_exit(&intr_mtx); 7002 return (DDI_INTR_CLAIMED); 7003 } 7004 7005 return (DDI_INTR_UNCLAIMED); 7006 } 7007 7008 /* 7009 * Don't deliver the signal until the debounce period has expired. 7010 * Unfortuately this means it end up as a three tier interrupt just 7011 * to indicate a bit change. 7012 */ 7013 static void 7014 syshw_debounce_to(void *arg) 7015 { 7016 _NOTE(ARGUNUSED(arg)) 7017 7018 if (switch_to_id) { 7019 pcic_mutex_enter(&intr_mtx); 7020 switch_to_id = 0; 7021 pcic_mutex_exit(&intr_mtx); 7022 syshw_send_signal(runstop_sig); 7023 return; 7024 } 7025 } 7026 7027 static uint_t 7028 syshw_intr(caddr_t arg) 7029 { 7030 _NOTE(ARGUNUSED(arg)) 7031 7032 if (softint_flag) { 7033 pcic_mutex_enter(&intr_mtx); 7034 softint_flag = 0; 7035 if (!switch_to_id) 7036 switch_to_id = timeout(syshw_debounce_to, arg, 7037 drv_usectohz(switch_debounce_time * 1000)); 7038 pcic_mutex_exit(&intr_mtx); 7039 return (DDI_INTR_CLAIMED); 7040 } 7041 return (DDI_INTR_UNCLAIMED); 7042 } 7043 #endif 7044 7045 /* 7046 * Send signals to the registered clients 7047 */ 7048 static void 7049 syshw_send_signal(int events) 7050 { 7051 client_data *ptr; 7052 proc_t *pr; 7053 int done_flag; 7054 7055 ptr = cl_data; 7056 while (ptr != NULL) { 7057 done_flag = CLIENT_CALLED; 7058 7059 if ((ptr->flags & events) && 7060 (ptr->event_sig != 0) && 7061 ((ptr->flags & done_flag) == 0)) { 7062 7063 /* 7064 * only call the process if: 7065 * it has not already received the nce signal 7066 * its signal was not zero (just in case) 7067 * and it is registered to receive this signal 7068 */ 7069 pcic_mutex_enter(&pidlock); 7070 pr = prfind(ptr->pid); 7071 pcic_mutex_exit(&pidlock); 7072 if (pr == NULL) { 7073 /* 7074 * This process has died, 7075 * so we free its memory and move on 7076 * start at the begining again: 7077 * a waste of cycles but it makes things easy.. 7078 */ 7079 delete_client(ptr->pid); 7080 ptr = cl_data; 7081 } else { 7082 ptr->events |= (events & ptr->flags & 7083 NCE_EVENT_MASK); 7084 psignal(pr, ptr->event_sig); 7085 ptr->flags |= done_flag; 7086 ptr = ptr->next; 7087 } 7088 } else { 7089 ptr = ptr->next; 7090 } 7091 } 7092 7093 ptr = cl_data; 7094 while (ptr != NULL) { 7095 ptr->flags &= ~done_flag; 7096 ptr = ptr->next; 7097 } 7098 } 7099 7100 static int 7101 syshw_open(dev_t *dev, int flag, int otyp, cred_t *cred) 7102 { 7103 _NOTE(ARGUNUSED(dev, flag, cred)) 7104 7105 if (otyp != OTYP_CHR) 7106 return (EINVAL); 7107 7108 return (0); 7109 } 7110 7111 static int 7112 syshw_close(dev_t dev, int flag, int otyp, cred_t *cred) 7113 { 7114 _NOTE(ARGUNUSED(dev, flag, otyp, cred)) 7115 7116 return (0); 7117 } 7118 7119 /* 7120 * Add a client to the list of interested processes 7121 */ 7122 static void 7123 add_client(client_data *new) 7124 { 7125 client_data * ptr; 7126 7127 n_clients++; 7128 if (cl_data == NULL) { 7129 cl_data = new; 7130 return; 7131 } 7132 7133 ptr = cl_data; 7134 while ((ptr->next != NULL) && (ptr->priority <= new->priority)) 7135 ptr = ptr->next; 7136 7137 if (ptr == cl_data) { 7138 /* at head of the list */ 7139 cl_data = new; 7140 new->next = ptr; 7141 new->prev = NULL; 7142 if (ptr != NULL) 7143 ptr->prev = new; 7144 } else { 7145 /* somewhere else in the list - insert after */ 7146 new->next = ptr->next; 7147 ptr->next = new; 7148 new->prev = ptr; 7149 if (new->next != NULL) 7150 (new->next)->prev = new; 7151 } 7152 } 7153 7154 /* 7155 * Locate a client data structure in the client list by looking for a PID match. 7156 */ 7157 static client_data * 7158 locate_client(pid_t pid) 7159 { 7160 client_data * ptr = cl_data; 7161 7162 while ((ptr != NULL) && (ptr->pid != pid)) 7163 ptr = ptr->next; 7164 7165 return (ptr); 7166 } 7167 7168 /* 7169 * Remove a client record from the client list 7170 */ 7171 static void 7172 delete_client(pid_t pid) 7173 { 7174 client_data * ptr; 7175 7176 ptr = locate_client(pid); 7177 if (ptr == NULL) 7178 return; /* hmmm!! */ 7179 7180 n_clients--; 7181 7182 if (ptr == cl_data) { 7183 /* remove the head of the list */ 7184 cl_data = ptr->next; 7185 } 7186 if (ptr->prev != NULL) 7187 (ptr->prev)->next = ptr->next; 7188 if (ptr->next != NULL) 7189 (ptr->next)->prev = ptr->prev; 7190 7191 kmem_free(ptr, sizeof (client_data)); 7192 } 7193 7194 static void 7195 unregister_event_client() 7196 { 7197 pcic_mutex_enter(&client_mtx); 7198 delete_client(ddi_get_pid()); 7199 pcic_mutex_exit(&client_mtx); 7200 } 7201 7202 static int 7203 register_event_client(client_data *u_client) 7204 { 7205 int error; 7206 client_data * client; 7207 7208 pcic_mutex_enter(&client_mtx); 7209 client = locate_client(ddi_get_pid()); 7210 if (client) { 7211 /* 7212 * we are re-registering ourself 7213 * so we delete the previous entry 7214 */ 7215 delete_client(ddi_get_pid()); 7216 } 7217 7218 client = (client_data *)kmem_alloc(sizeof (client_data), KM_SLEEP); 7219 7220 if (client) { 7221 client->pid = ddi_get_pid(); 7222 client->priority = u_client->priority; 7223 client->flags = u_client->flags & NCE_EVENT_MASK; 7224 client->events = 0; 7225 client->event_sig = u_client->event_sig; 7226 client->next = NULL; 7227 client->prev = NULL; 7228 add_client(client); 7229 error = 0; 7230 } else 7231 error = EIO; 7232 7233 pcic_mutex_exit(&client_mtx); 7234 return (error); 7235 } 7236 7237 /* 7238 * Read the currently pending event flags for the process in question 7239 */ 7240 static int 7241 check_events_pending(caddr_t data) 7242 { 7243 client_data * client; 7244 int error = 0; 7245 7246 pcic_mutex_enter(&client_mtx); 7247 client = locate_client(ddi_get_pid()); 7248 if (client) { 7249 if (copyout((caddr_t)&client->events, data, sizeof (int))) 7250 error = EFAULT; 7251 else 7252 client->events = 0; 7253 } else 7254 error = EINVAL; 7255 7256 pcic_mutex_exit(&client_mtx); 7257 return (error); 7258 } 7259 7260 7261 #define MAXITEMS 8 7262 static syshw_t *syshw_map[MAXITEMS]; 7263 static void (*syshw_getfuncs[MAXITEMS])(syshw_t *, void *); 7264 static void *syshw_getfunc_args[MAXITEMS]; 7265 static int nsyshw_items = 0; 7266 #define NSYSHW_ITEMS nsyshw_items 7267 7268 static uint32_t 7269 syshw_add2map(syshw_t *item, void (*getfunc)(syshw_t *, void *), void *getarg) 7270 { 7271 uint32_t rval = (1 << nsyshw_items); 7272 if (nsyshw_items == MAXITEMS) 7273 return (0); 7274 item->hw_id = nsyshw_items; 7275 syshw_map[nsyshw_items] = item; 7276 syshw_getfuncs[nsyshw_items] = getfunc; 7277 syshw_getfunc_args[nsyshw_items] = getarg; 7278 nsyshw_items++; 7279 return (rval); 7280 } 7281 7282 static int 7283 syshw_ioctl(dev_t dev, int cmd, intptr_t ioctldata, int mode, 7284 cred_t *cred, int *rval) 7285 { 7286 caddr_t data = (caddr_t)ioctldata; 7287 syshw_t sh; 7288 hwev_t hwev; 7289 client_data dummy_client; 7290 int rc = 0, i; 7291 7292 _NOTE(ARGUNUSED(dev, mode, cred, rval)) 7293 7294 switch (cmd) { 7295 default: 7296 rc = EINVAL; 7297 break; 7298 7299 case SYSHW_GET_ITEM: 7300 case SYSHW_GET_ITEM_MAXVALUES: 7301 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7302 rc = EFAULT; 7303 break; 7304 } 7305 7306 if (sh.hw_id >= NSYSHW_ITEMS) { 7307 rc = EINVAL; 7308 break; 7309 } 7310 7311 sh = *syshw_map[sh.hw_id]; 7312 if (!sh.id_string[0]) { 7313 rc = ENOTTY; 7314 break; 7315 } 7316 if (cmd == SYSHW_GET_ITEM) { 7317 if (syshw_getfuncs[sh.hw_id]) 7318 syshw_getfuncs[sh.hw_id](&sh, 7319 syshw_getfunc_args[sh.hw_id]); 7320 else 7321 rc = ENOTTY; 7322 } 7323 7324 if (copyout((caddr_t)&sh, data, sizeof (sh))) { 7325 rc = EFAULT; 7326 break; 7327 } 7328 break; 7329 7330 case SYSHW_SET_ITEM: 7331 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7332 rc = EFAULT; 7333 break; 7334 } 7335 7336 if (sh.hw_id >= NSYSHW_ITEMS || 7337 !syshw_map[sh.hw_id]->id_string[0] || 7338 !(syshw_map[sh.hw_id]->capabilities & 7339 (SYSHW_STATE_MODIFY | SYSHW_VAL0_MODIFY | 7340 SYSHW_VAL1_MODIFY | SYSHW_VAL2_MODIFY | 7341 SYSHW_VAL3_MODIFY))) { 7342 rc = EINVAL; 7343 break; 7344 } 7345 7346 switch (sh.hw_id) { 7347 default: 7348 rc = EINVAL; 7349 break; 7350 } 7351 break; 7352 7353 case SYSHW_EVREG: 7354 if (copyin(data, (caddr_t)&hwev, sizeof (hwev))) { 7355 rc = EFAULT; 7356 break; 7357 } 7358 7359 for (i = 0; i < NSYSHW_ITEMS; i++) { 7360 if (hwev.events & (1 << i) && 7361 !(syshw_map[i]->capabilities & 7362 SYSHW_CAN_SIGNAL_CHANGE)) { 7363 rc = EINVAL; 7364 break; 7365 } 7366 } 7367 if (hwev.event_sig != SIGUSR1 && hwev.event_sig != SIGUSR2) 7368 rc = EINVAL; 7369 7370 if (!rc) { 7371 dummy_client.priority = 100; 7372 dummy_client.flags = hwev.events; 7373 dummy_client.event_sig = hwev.event_sig; 7374 rc = register_event_client(&dummy_client); 7375 } 7376 break; 7377 7378 case SYSHW_EVUNREG: 7379 unregister_event_client(); 7380 break; 7381 7382 case SYSHW_CHKEV: 7383 rc = check_events_pending(data); 7384 break; 7385 } 7386 return (rc); 7387 } 7388