1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <sys/nxge/nxge_impl.h> 27 #include <sys/nxge/nxge_mac.h> 28 #include <sys/nxge/nxge_hio.h> 29 30 static void nxge_get_niu_property(dev_info_t *, niu_type_t *); 31 static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t); 32 static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t); 33 static void nxge_use_cfg_neptune_properties(p_nxge_t); 34 static void nxge_use_cfg_dma_config(p_nxge_t); 35 static void nxge_use_cfg_vlan_class_config(p_nxge_t); 36 static void nxge_use_cfg_mac_class_config(p_nxge_t); 37 static void nxge_use_cfg_class_config(p_nxge_t); 38 static void nxge_use_cfg_link_cfg(p_nxge_t); 39 static void nxge_set_hw_dma_config(p_nxge_t); 40 static void nxge_set_hw_vlan_class_config(p_nxge_t); 41 static void nxge_set_hw_mac_class_config(p_nxge_t); 42 static void nxge_set_hw_class_config(p_nxge_t); 43 static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t); 44 static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t, 45 uint8_t, int *); 46 static void nxge_init_mmac(p_nxge_t, boolean_t); 47 static void nxge_set_rdc_intr_property(p_nxge_t); 48 49 uint32_t nxge_use_hw_property = 1; 50 uint32_t nxge_groups_per_port = 2; 51 52 extern uint32_t nxge_use_partition; 53 extern uint32_t nxge_dma_obp_props_only; 54 55 extern uint16_t nxge_rcr_timeout; 56 extern uint16_t nxge_rcr_threshold; 57 58 extern uint_t nxge_rx_intr(void *, void *); 59 extern uint_t nxge_tx_intr(void *, void *); 60 extern uint_t nxge_mif_intr(void *, void *); 61 extern uint_t nxge_mac_intr(void *, void *); 62 extern uint_t nxge_syserr_intr(void *, void *); 63 extern void *nxge_list; 64 65 #define NXGE_SHARED_REG_SW_SIM 66 67 #ifdef NXGE_SHARED_REG_SW_SIM 68 uint64_t global_dev_ctrl = 0; 69 #endif 70 71 #define MAX_SIBLINGS NXGE_MAX_PORTS 72 73 extern uint32_t nxge_rbr_size; 74 extern uint32_t nxge_rcr_size; 75 extern uint32_t nxge_tx_ring_size; 76 extern uint32_t nxge_rbr_spare_size; 77 78 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 79 80 static uint8_t p2_tx_fair[2] = {12, 12}; 81 static uint8_t p2_tx_equal[2] = {12, 12}; 82 static uint8_t p4_tx_fair[4] = {6, 6, 6, 6}; 83 static uint8_t p4_tx_equal[4] = {6, 6, 6, 6}; 84 static uint8_t p2_rx_fair[2] = {8, 8}; 85 static uint8_t p2_rx_equal[2] = {8, 8}; 86 static uint8_t p4_rx_fair[4] = {4, 4, 4, 4}; 87 static uint8_t p4_rx_equal[4] = {4, 4, 4, 4}; 88 89 static uint8_t p2_rdcgrp_fair[2] = {4, 4}; 90 static uint8_t p2_rdcgrp_equal[2] = {4, 4}; 91 static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1}; 92 static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2}; 93 static uint8_t p2_rdcgrp_cls[2] = {1, 1}; 94 static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1}; 95 96 static uint8_t rx_4_1G[4] = {4, 4, 4, 4}; 97 static uint8_t rx_2_10G[2] = {8, 8}; 98 static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2}; 99 static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2}; 100 static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2}; 101 102 static uint8_t tx_4_1G[4] = {6, 6, 6, 6}; 103 static uint8_t tx_2_10G[2] = {12, 12}; 104 static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2}; 105 static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4}; 106 static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4}; 107 108 typedef enum { 109 DEFAULT = 0, 110 EQUAL, 111 FAIR, 112 CUSTOM, 113 CLASSIFY, 114 L2_CLASSIFY, 115 L3_DISTRIBUTE, 116 L3_CLASSIFY, 117 L3_TCAM, 118 CONFIG_TOKEN_NONE 119 } config_token_t; 120 121 static char *token_names[] = { 122 "default", 123 "equal", 124 "fair", 125 "custom", 126 "classify", 127 "l2_classify", 128 "l3_distribute", 129 "l3_classify", 130 "l3_tcam", 131 "none", 132 }; 133 134 void nxge_virint_regs_dump(p_nxge_t nxgep); 135 136 void 137 nxge_virint_regs_dump(p_nxge_t nxgep) 138 { 139 npi_handle_t handle; 140 141 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump")); 142 handle = NXGE_DEV_NPI_HANDLE(nxgep); 143 (void) npi_vir_dump_pio_fzc_regs_one(handle); 144 (void) npi_vir_dump_ldgnum(handle); 145 (void) npi_vir_dump_ldsv(handle); 146 (void) npi_vir_dump_imask0(handle); 147 (void) npi_vir_dump_sid(handle); 148 (void) npi_mac_dump_regs(handle, nxgep->function_num); 149 (void) npi_ipp_dump_regs(handle, nxgep->function_num); 150 (void) npi_fflp_dump_regs(handle); 151 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump")); 152 } 153 154 /* 155 * For now: we hard coded the DMA configurations. 156 * and assume for one partition only. 157 * 158 * OBP. Then OBP will pass this partition's 159 * Neptune configurations to fcode to create 160 * properties for them. 161 * 162 * Since Neptune(PCI-E) and NIU (Niagara-2) has 163 * different bus interfaces, the driver needs 164 * to know which bus it is connected to. 165 * Ravinder suggested: create a device property. 166 * In partitioning environment, we cannot 167 * use .conf file (need to check). If conf changes, 168 * need to reboot the system. 169 * The following function assumes that we will 170 * retrieve its properties from a virtualized nexus driver. 171 */ 172 173 nxge_status_t 174 nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result) 175 { 176 nxge_status_t status = NXGE_OK; 177 int instance; 178 p_nxge_t nxgep; 179 180 #ifndef NXGE_SHARED_REG_SW_SIM 181 npi_handle_t handle; 182 uint16_t sr16, cr16; 183 #endif 184 instance = ddi_get_instance(dip); 185 NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance)); 186 187 if (nxge_list == NULL) { 188 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 189 "nxge_cntlops: nxge_list null")); 190 return (NXGE_ERROR); 191 } 192 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 193 if (nxgep == NULL) { 194 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 195 "nxge_cntlops: nxgep null")); 196 return (NXGE_ERROR); 197 } 198 #ifndef NXGE_SHARED_REG_SW_SIM 199 handle = nxgep->npi_reg_handle; 200 #endif 201 switch (ctlop) { 202 case NXGE_CTLOPS_NIUTYPE: 203 nxge_get_niu_property(dip, (niu_type_t *)result); 204 return (status); 205 206 case NXGE_CTLOPS_GET_SHARED_REG: 207 #ifdef NXGE_SHARED_REG_SW_SIM 208 *(uint64_t *)result = global_dev_ctrl; 209 return (0); 210 #else 211 status = npi_dev_func_sr_sr_get(handle, &sr16); 212 *(uint16_t *)result = sr16; 213 NXGE_DEBUG_MSG((NULL, VIR_CTL, 214 "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG")); 215 return (0); 216 #endif 217 218 case NXGE_CTLOPS_SET_SHARED_REG_LOCK: 219 #ifdef NXGE_SHARED_REG_SW_SIM 220 global_dev_ctrl = *(uint64_t *)arg; 221 return (0); 222 #else 223 status = NPI_FAILURE; 224 while (status != NPI_SUCCESS) 225 status = npi_dev_func_sr_lock_enter(handle); 226 227 sr16 = *(uint16_t *)arg; 228 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 229 status = npi_dev_func_sr_lock_free(handle); 230 NXGE_DEBUG_MSG((NULL, VIR_CTL, 231 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 232 return (0); 233 #endif 234 235 case NXGE_CTLOPS_UPDATE_SHARED_REG: 236 #ifdef NXGE_SHARED_REG_SW_SIM 237 global_dev_ctrl |= *(uint64_t *)arg; 238 return (0); 239 #else 240 status = NPI_FAILURE; 241 while (status != NPI_SUCCESS) 242 status = npi_dev_func_sr_lock_enter(handle); 243 status = npi_dev_func_sr_sr_get(handle, &sr16); 244 sr16 |= *(uint16_t *)arg; 245 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 246 status = npi_dev_func_sr_lock_free(handle); 247 NXGE_DEBUG_MSG((NULL, VIR_CTL, 248 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 249 return (0); 250 #endif 251 252 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL: 253 #ifdef NXGE_SHARED_REG_SW_SIM 254 global_dev_ctrl |= *(uint64_t *)arg; 255 return (0); 256 #else 257 status = npi_dev_func_sr_sr_get(handle, &sr16); 258 cr16 = *(uint16_t *)arg; 259 sr16 &= ~cr16; 260 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 261 NXGE_DEBUG_MSG((NULL, VIR_CTL, 262 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 263 return (0); 264 #endif 265 266 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG: 267 #ifdef NXGE_SHARED_REG_SW_SIM 268 global_dev_ctrl |= *(uint64_t *)arg; 269 return (0); 270 #else 271 status = NPI_FAILURE; 272 while (status != NPI_SUCCESS) 273 status = npi_dev_func_sr_lock_enter(handle); 274 status = npi_dev_func_sr_sr_get(handle, &sr16); 275 cr16 = *(uint16_t *)arg; 276 sr16 &= ~cr16; 277 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 278 status = npi_dev_func_sr_lock_free(handle); 279 NXGE_DEBUG_MSG((NULL, VIR_CTL, 280 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 281 return (0); 282 #endif 283 284 case NXGE_CTLOPS_GET_LOCK_BLOCK: 285 #ifdef NXGE_SHARED_REG_SW_SIM 286 global_dev_ctrl |= *(uint64_t *)arg; 287 return (0); 288 #else 289 status = NPI_FAILURE; 290 while (status != NPI_SUCCESS) 291 status = npi_dev_func_sr_lock_enter(handle); 292 NXGE_DEBUG_MSG((NULL, VIR_CTL, 293 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK")); 294 return (0); 295 #endif 296 case NXGE_CTLOPS_GET_LOCK_TRY: 297 #ifdef NXGE_SHARED_REG_SW_SIM 298 global_dev_ctrl |= *(uint64_t *)arg; 299 return (0); 300 #else 301 status = npi_dev_func_sr_lock_enter(handle); 302 NXGE_DEBUG_MSG((NULL, VIR_CTL, 303 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY")); 304 if (status == NPI_SUCCESS) 305 return (NXGE_OK); 306 else 307 return (NXGE_ERROR); 308 #endif 309 case NXGE_CTLOPS_FREE_LOCK: 310 #ifdef NXGE_SHARED_REG_SW_SIM 311 global_dev_ctrl |= *(uint64_t *)arg; 312 return (0); 313 #else 314 status = npi_dev_func_sr_lock_free(handle); 315 NXGE_DEBUG_MSG((NULL, VIR_CTL, 316 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE")); 317 if (status == NPI_SUCCESS) 318 return (NXGE_OK); 319 else 320 return (NXGE_ERROR); 321 #endif 322 323 default: 324 status = NXGE_ERROR; 325 } 326 327 return (status); 328 } 329 330 void 331 nxge_common_lock_get(p_nxge_t nxgep) 332 { 333 uint32_t status = NPI_FAILURE; 334 npi_handle_t handle; 335 336 #if defined(NXGE_SHARE_REG_SW_SIM) 337 return; 338 #endif 339 handle = nxgep->npi_reg_handle; 340 while (status != NPI_SUCCESS) 341 status = npi_dev_func_sr_lock_enter(handle); 342 } 343 344 void 345 nxge_common_lock_free(p_nxge_t nxgep) 346 { 347 npi_handle_t handle; 348 349 #if defined(NXGE_SHARE_REG_SW_SIM) 350 return; 351 #endif 352 handle = nxgep->npi_reg_handle; 353 (void) npi_dev_func_sr_lock_free(handle); 354 } 355 356 357 static void 358 nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type) 359 { 360 uchar_t *prop_val; 361 uint_t prop_len; 362 363 *niu_type = NIU_TYPE_NONE; 364 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, 365 "niu-type", (uchar_t **)&prop_val, 366 &prop_len) == DDI_PROP_SUCCESS) { 367 if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) { 368 *niu_type = N2_NIU; 369 } 370 ddi_prop_free(prop_val); 371 } 372 } 373 374 static config_token_t 375 nxge_get_config_token(char *prop) 376 { 377 config_token_t token = DEFAULT; 378 379 while (token < CONFIG_TOKEN_NONE) { 380 if (strncmp(prop, token_names[token], 4) == 0) 381 break; 382 token++; 383 } 384 return (token); 385 } 386 387 /* per port */ 388 389 static nxge_status_t 390 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token, 391 dev_info_t *s_dip[]) 392 { 393 nxge_status_t status = NXGE_OK; 394 int ddi_status; 395 int num_ports = nxgep->nports; 396 int port, bits, j; 397 uint8_t start_grp = 0, num_grps = 0; 398 p_nxge_param_t param_arr; 399 uint32_t grp_bitmap[MAX_SIBLINGS]; 400 int custom_start_grp[MAX_SIBLINGS]; 401 int custom_num_grp[MAX_SIBLINGS]; 402 uint8_t bad_config = B_FALSE; 403 char *start_prop, *num_prop, *cfg_prop; 404 405 start_grp = 0; 406 param_arr = nxgep->param_arr; 407 start_prop = param_arr[param_rdc_grps_start].fcode_name; 408 num_prop = param_arr[param_rx_rdc_grps].fcode_name; 409 410 switch (token) { 411 case FAIR: 412 cfg_prop = "fair"; 413 for (port = 0; port < num_ports; port++) { 414 custom_num_grp[port] = 415 (num_ports == 4) ? 416 p4_rdcgrp_fair[port] : 417 p2_rdcgrp_fair[port]; 418 custom_start_grp[port] = start_grp; 419 start_grp += custom_num_grp[port]; 420 } 421 break; 422 423 case EQUAL: 424 cfg_prop = "equal"; 425 for (port = 0; port < num_ports; port++) { 426 custom_num_grp[port] = 427 (num_ports == 4) ? 428 p4_rdcgrp_equal[port] : 429 p2_rdcgrp_equal[port]; 430 custom_start_grp[port] = start_grp; 431 start_grp += custom_num_grp[port]; 432 } 433 break; 434 435 436 case CLASSIFY: 437 cfg_prop = "classify"; 438 for (port = 0; port < num_ports; port++) { 439 custom_num_grp[port] = (num_ports == 4) ? 440 p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port]; 441 custom_start_grp[port] = start_grp; 442 start_grp += custom_num_grp[port]; 443 } 444 break; 445 446 case CUSTOM: 447 cfg_prop = "custom"; 448 /* See if it is good config */ 449 num_grps = 0; 450 for (port = 0; port < num_ports; port++) { 451 custom_start_grp[port] = 452 ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port], 453 DDI_PROP_DONTPASS, start_prop, -1); 454 if ((custom_start_grp[port] == -1) || 455 (custom_start_grp[port] >= 456 NXGE_MAX_RDC_GRPS)) { 457 bad_config = B_TRUE; 458 break; 459 } 460 custom_num_grp[port] = ddi_prop_get_int( 461 DDI_DEV_T_NONE, 462 s_dip[port], 463 DDI_PROP_DONTPASS, 464 num_prop, -1); 465 466 if ((custom_num_grp[port] == -1) || 467 (custom_num_grp[port] > 468 NXGE_MAX_RDC_GRPS) || 469 ((custom_num_grp[port] + 470 custom_start_grp[port]) >= 471 NXGE_MAX_RDC_GRPS)) { 472 bad_config = B_TRUE; 473 break; 474 } 475 num_grps += custom_num_grp[port]; 476 if (num_grps > NXGE_MAX_RDC_GRPS) { 477 bad_config = B_TRUE; 478 break; 479 } 480 grp_bitmap[port] = 0; 481 for (bits = 0; 482 bits < custom_num_grp[port]; 483 bits++) { 484 grp_bitmap[port] |= 485 (1 << (bits + custom_start_grp[port])); 486 } 487 488 } 489 490 if (bad_config == B_FALSE) { 491 /* check for overlap */ 492 for (port = 0; port < num_ports - 1; port++) { 493 for (j = port + 1; j < num_ports; j++) { 494 if (grp_bitmap[port] & 495 grp_bitmap[j]) { 496 bad_config = B_TRUE; 497 break; 498 } 499 } 500 if (bad_config == B_TRUE) 501 break; 502 } 503 } 504 if (bad_config == B_TRUE) { 505 /* use default config */ 506 for (port = 0; port < num_ports; port++) { 507 custom_num_grp[port] = 508 (num_ports == 4) ? 509 p4_rx_fair[port] : p2_rx_fair[port]; 510 custom_start_grp[port] = start_grp; 511 start_grp += custom_num_grp[port]; 512 } 513 } 514 break; 515 516 default: 517 /* use default config */ 518 cfg_prop = "fair"; 519 for (port = 0; port < num_ports; port++) { 520 custom_num_grp[port] = (num_ports == 4) ? 521 p4_rx_fair[port] : p2_rx_fair[port]; 522 custom_start_grp[port] = start_grp; 523 start_grp += custom_num_grp[port]; 524 } 525 break; 526 } 527 528 /* Now Update the rx properties */ 529 for (port = 0; port < num_ports; port++) { 530 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 531 "rxdma-grp-cfg", cfg_prop); 532 if (ddi_status != DDI_PROP_SUCCESS) { 533 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 534 " property %s not updating", 535 cfg_prop)); 536 status |= NXGE_DDI_FAILED; 537 } 538 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 539 num_prop, custom_num_grp[port]); 540 541 if (ddi_status != DDI_PROP_SUCCESS) { 542 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 543 " property %s not updating", 544 num_prop)); 545 status |= NXGE_DDI_FAILED; 546 } 547 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 548 start_prop, custom_start_grp[port]); 549 550 if (ddi_status != DDI_PROP_SUCCESS) { 551 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 552 " property %s not updating", 553 start_prop)); 554 status |= NXGE_DDI_FAILED; 555 } 556 } 557 if (status & NXGE_DDI_FAILED) 558 status |= NXGE_ERROR; 559 560 return (status); 561 } 562 563 static nxge_status_t 564 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token, 565 dev_info_t *s_dip[]) 566 { 567 nxge_status_t status = NXGE_OK; 568 int ddi_status; 569 int num_ports = nxgep->nports; 570 int port, bits, j; 571 uint8_t start_rdc = 0, num_rdc = 0; 572 p_nxge_param_t param_arr; 573 uint32_t rdc_bitmap[MAX_SIBLINGS]; 574 int custom_start_rdc[MAX_SIBLINGS]; 575 int custom_num_rdc[MAX_SIBLINGS]; 576 uint8_t bad_config = B_FALSE; 577 int *prop_val; 578 uint_t prop_len; 579 char *start_rdc_prop, *num_rdc_prop, *cfg_prop; 580 581 start_rdc = 0; 582 param_arr = nxgep->param_arr; 583 start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name; 584 num_rdc_prop = param_arr[param_rxdma_channels].fcode_name; 585 586 switch (token) { 587 case FAIR: 588 cfg_prop = "fair"; 589 for (port = 0; port < num_ports; port++) { 590 custom_num_rdc[port] = (num_ports == 4) ? 591 p4_rx_fair[port] : p2_rx_fair[port]; 592 custom_start_rdc[port] = start_rdc; 593 start_rdc += custom_num_rdc[port]; 594 } 595 break; 596 597 case EQUAL: 598 cfg_prop = "equal"; 599 for (port = 0; port < num_ports; port++) { 600 custom_num_rdc[port] = (num_ports == 4) ? 601 p4_rx_equal[port] : 602 p2_rx_equal[port]; 603 custom_start_rdc[port] = start_rdc; 604 start_rdc += custom_num_rdc[port]; 605 } 606 break; 607 608 case CUSTOM: 609 cfg_prop = "custom"; 610 /* See if it is good config */ 611 num_rdc = 0; 612 for (port = 0; port < num_ports; port++) { 613 ddi_status = ddi_prop_lookup_int_array( 614 DDI_DEV_T_ANY, 615 s_dip[port], 0, 616 start_rdc_prop, 617 &prop_val, 618 &prop_len); 619 if (ddi_status == DDI_SUCCESS) 620 custom_start_rdc[port] = *prop_val; 621 else { 622 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 623 " %s custom start port %d" 624 " read failed ", 625 " rxdma-cfg", port)); 626 bad_config = B_TRUE; 627 status |= NXGE_DDI_FAILED; 628 } 629 if ((custom_start_rdc[port] == -1) || 630 (custom_start_rdc[port] >= 631 NXGE_MAX_RDCS)) { 632 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 633 " %s custom start %d" 634 " out of range %x ", 635 " rxdma-cfg", 636 port, 637 custom_start_rdc[port])); 638 bad_config = B_TRUE; 639 break; 640 } 641 ddi_status = ddi_prop_lookup_int_array( 642 DDI_DEV_T_ANY, 643 s_dip[port], 644 0, 645 num_rdc_prop, 646 &prop_val, 647 &prop_len); 648 649 if (ddi_status == DDI_SUCCESS) 650 custom_num_rdc[port] = *prop_val; 651 else { 652 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 653 " %s custom num port %d" 654 " read failed ", 655 "rxdma-cfg", port)); 656 bad_config = B_TRUE; 657 status |= NXGE_DDI_FAILED; 658 } 659 660 if ((custom_num_rdc[port] == -1) || 661 (custom_num_rdc[port] > 662 NXGE_MAX_RDCS) || 663 ((custom_num_rdc[port] + 664 custom_start_rdc[port]) > 665 NXGE_MAX_RDCS)) { 666 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 667 " %s custom num %d" 668 " out of range %x ", 669 " rxdma-cfg", 670 port, custom_num_rdc[port])); 671 bad_config = B_TRUE; 672 break; 673 } 674 num_rdc += custom_num_rdc[port]; 675 if (num_rdc > NXGE_MAX_RDCS) { 676 bad_config = B_TRUE; 677 break; 678 } 679 rdc_bitmap[port] = 0; 680 for (bits = 0; 681 bits < custom_num_rdc[port]; bits++) { 682 rdc_bitmap[port] |= 683 (1 << (bits + custom_start_rdc[port])); 684 } 685 } 686 687 if (bad_config == B_FALSE) { 688 /* check for overlap */ 689 for (port = 0; port < num_ports - 1; port++) { 690 for (j = port + 1; j < num_ports; j++) { 691 if (rdc_bitmap[port] & 692 rdc_bitmap[j]) { 693 NXGE_DEBUG_MSG((nxgep, 694 CFG_CTL, 695 " rxdma-cfg" 696 " property custom" 697 " bit overlap" 698 " %d %d ", 699 port, j)); 700 bad_config = B_TRUE; 701 break; 702 } 703 } 704 if (bad_config == B_TRUE) 705 break; 706 } 707 } 708 if (bad_config == B_TRUE) { 709 /* use default config */ 710 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 711 " rxdma-cfg property:" 712 " bad custom config:" 713 " use default")); 714 for (port = 0; port < num_ports; port++) { 715 custom_num_rdc[port] = 716 (num_ports == 4) ? 717 p4_rx_fair[port] : 718 p2_rx_fair[port]; 719 custom_start_rdc[port] = start_rdc; 720 start_rdc += custom_num_rdc[port]; 721 } 722 } 723 break; 724 725 default: 726 /* use default config */ 727 cfg_prop = "fair"; 728 for (port = 0; port < num_ports; port++) { 729 custom_num_rdc[port] = (num_ports == 4) ? 730 p4_rx_fair[port] : p2_rx_fair[port]; 731 custom_start_rdc[port] = start_rdc; 732 start_rdc += custom_num_rdc[port]; 733 } 734 break; 735 } 736 737 /* Now Update the rx properties */ 738 for (port = 0; port < num_ports; port++) { 739 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 740 " update property rxdma-cfg with %s ", cfg_prop)); 741 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 742 "rxdma-cfg", cfg_prop); 743 if (ddi_status != DDI_PROP_SUCCESS) { 744 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 745 " property rxdma-cfg is not updating to %s", 746 cfg_prop)); 747 status |= NXGE_DDI_FAILED; 748 } 749 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 750 num_rdc_prop, custom_num_rdc[port])); 751 752 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 753 num_rdc_prop, custom_num_rdc[port]); 754 755 if (ddi_status != DDI_PROP_SUCCESS) { 756 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 757 " property %s not updating with %d", 758 num_rdc_prop, custom_num_rdc[port])); 759 status |= NXGE_DDI_FAILED; 760 } 761 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 762 start_rdc_prop, custom_start_rdc[port])); 763 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 764 start_rdc_prop, custom_start_rdc[port]); 765 766 if (ddi_status != DDI_PROP_SUCCESS) { 767 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 768 " property %s not updating with %d ", 769 start_rdc_prop, custom_start_rdc[port])); 770 status |= NXGE_DDI_FAILED; 771 } 772 } 773 if (status & NXGE_DDI_FAILED) 774 status |= NXGE_ERROR; 775 return (status); 776 } 777 778 static nxge_status_t 779 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token, 780 dev_info_t *s_dip[]) 781 { 782 nxge_status_t status = NXGE_OK; 783 int ddi_status = DDI_SUCCESS; 784 int num_ports = nxgep->nports; 785 int port, bits, j; 786 uint8_t start_tdc = 0, num_tdc = 0; 787 p_nxge_param_t param_arr; 788 uint32_t tdc_bitmap[MAX_SIBLINGS]; 789 int custom_start_tdc[MAX_SIBLINGS]; 790 int custom_num_tdc[MAX_SIBLINGS]; 791 uint8_t bad_config = B_FALSE; 792 int *prop_val; 793 uint_t prop_len; 794 char *start_tdc_prop, *num_tdc_prop, *cfg_prop; 795 796 start_tdc = 0; 797 param_arr = nxgep->param_arr; 798 start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name; 799 num_tdc_prop = param_arr[param_txdma_channels].fcode_name; 800 801 switch (token) { 802 case FAIR: 803 cfg_prop = "fair"; 804 for (port = 0; port < num_ports; port++) { 805 custom_num_tdc[port] = (num_ports == 4) ? 806 p4_tx_fair[port] : p2_tx_fair[port]; 807 custom_start_tdc[port] = start_tdc; 808 start_tdc += custom_num_tdc[port]; 809 } 810 break; 811 812 case EQUAL: 813 cfg_prop = "equal"; 814 for (port = 0; port < num_ports; port++) { 815 custom_num_tdc[port] = (num_ports == 4) ? 816 p4_tx_equal[port] : p2_tx_equal[port]; 817 custom_start_tdc[port] = start_tdc; 818 start_tdc += custom_num_tdc[port]; 819 } 820 break; 821 822 case CUSTOM: 823 cfg_prop = "custom"; 824 /* See if it is good config */ 825 num_tdc = 0; 826 for (port = 0; port < num_ports; port++) { 827 ddi_status = ddi_prop_lookup_int_array( 828 DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop, 829 &prop_val, &prop_len); 830 if (ddi_status == DDI_SUCCESS) 831 custom_start_tdc[port] = *prop_val; 832 else { 833 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 834 " %s custom start port %d" 835 " read failed ", " txdma-cfg", port)); 836 bad_config = B_TRUE; 837 status |= NXGE_DDI_FAILED; 838 } 839 840 if ((custom_start_tdc[port] == -1) || 841 (custom_start_tdc[port] >= 842 NXGE_MAX_RDCS)) { 843 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 844 " %s custom start %d" 845 " out of range %x ", " txdma-cfg", 846 port, custom_start_tdc[port])); 847 bad_config = B_TRUE; 848 break; 849 } 850 851 ddi_status = ddi_prop_lookup_int_array( 852 DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop, 853 &prop_val, &prop_len); 854 if (ddi_status == DDI_SUCCESS) 855 custom_num_tdc[port] = *prop_val; 856 else { 857 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 858 " %s custom num port %d" 859 " read failed ", " txdma-cfg", port)); 860 bad_config = B_TRUE; 861 status |= NXGE_DDI_FAILED; 862 } 863 864 if ((custom_num_tdc[port] == -1) || 865 (custom_num_tdc[port] > 866 NXGE_MAX_TDCS) || 867 ((custom_num_tdc[port] + 868 custom_start_tdc[port]) > 869 NXGE_MAX_TDCS)) { 870 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 871 " %s custom num %d" 872 " out of range %x ", " rxdma-cfg", 873 port, custom_num_tdc[port])); 874 bad_config = B_TRUE; 875 break; 876 } 877 num_tdc += custom_num_tdc[port]; 878 if (num_tdc > NXGE_MAX_TDCS) { 879 bad_config = B_TRUE; 880 break; 881 } 882 tdc_bitmap[port] = 0; 883 for (bits = 0; 884 bits < custom_num_tdc[port]; bits++) { 885 tdc_bitmap[port] |= 886 (1 << 887 (bits + custom_start_tdc[port])); 888 } 889 890 } 891 892 if (bad_config == B_FALSE) { 893 /* check for overlap */ 894 for (port = 0; port < num_ports - 1; port++) { 895 for (j = port + 1; j < num_ports; j++) { 896 if (tdc_bitmap[port] & 897 tdc_bitmap[j]) { 898 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 899 " rxdma-cfg" 900 " property custom" 901 " bit overlap" 902 " %d %d ", 903 port, j)); 904 bad_config = B_TRUE; 905 break; 906 } 907 } 908 if (bad_config == B_TRUE) 909 break; 910 } 911 } 912 if (bad_config == B_TRUE) { 913 /* use default config */ 914 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 915 " txdma-cfg property:" 916 " bad custom config:" " use default")); 917 918 for (port = 0; port < num_ports; port++) { 919 custom_num_tdc[port] = (num_ports == 4) ? 920 p4_tx_fair[port] : p2_tx_fair[port]; 921 custom_start_tdc[port] = start_tdc; 922 start_tdc += custom_num_tdc[port]; 923 } 924 } 925 break; 926 927 default: 928 /* use default config */ 929 cfg_prop = "fair"; 930 for (port = 0; port < num_ports; port++) { 931 custom_num_tdc[port] = (num_ports == 4) ? 932 p4_tx_fair[port] : p2_tx_fair[port]; 933 custom_start_tdc[port] = start_tdc; 934 start_tdc += custom_num_tdc[port]; 935 } 936 break; 937 } 938 939 /* Now Update the tx properties */ 940 for (port = 0; port < num_ports; port++) { 941 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 942 " update property txdma-cfg with %s ", cfg_prop)); 943 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 944 "txdma-cfg", cfg_prop); 945 if (ddi_status != DDI_PROP_SUCCESS) { 946 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 947 " property txdma-cfg is not updating to %s", 948 cfg_prop)); 949 status |= NXGE_DDI_FAILED; 950 } 951 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 952 num_tdc_prop, custom_num_tdc[port])); 953 954 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 955 num_tdc_prop, custom_num_tdc[port]); 956 957 if (ddi_status != DDI_PROP_SUCCESS) { 958 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 959 " property %s not updating with %d", 960 num_tdc_prop, 961 custom_num_tdc[port])); 962 status |= NXGE_DDI_FAILED; 963 } 964 965 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 966 start_tdc_prop, custom_start_tdc[port])); 967 968 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 969 start_tdc_prop, custom_start_tdc[port]); 970 if (ddi_status != DDI_PROP_SUCCESS) { 971 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 972 " property %s not updating with %d ", 973 start_tdc_prop, custom_start_tdc[port])); 974 status |= NXGE_DDI_FAILED; 975 } 976 } 977 if (status & NXGE_DDI_FAILED) 978 status |= NXGE_ERROR; 979 return (status); 980 } 981 982 static nxge_status_t 983 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags, 984 config_token_t token, dev_info_t *s_dip[]) 985 { 986 nxge_status_t status = NXGE_OK; 987 988 switch (flags) { 989 case COMMON_TXDMA_CFG: 990 if (nxge_dma_obp_props_only == 0) 991 status = nxge_update_txdma_properties(nxgep, 992 token, s_dip); 993 break; 994 case COMMON_RXDMA_CFG: 995 if (nxge_dma_obp_props_only == 0) 996 status = nxge_update_rxdma_properties(nxgep, 997 token, s_dip); 998 999 break; 1000 case COMMON_RXDMA_GRP_CFG: 1001 status = nxge_update_rxdma_grp_properties(nxgep, 1002 token, s_dip); 1003 break; 1004 default: 1005 return (NXGE_ERROR); 1006 } 1007 return (status); 1008 } 1009 1010 /* 1011 * verify consistence. 1012 * (May require publishing the properties on all the ports. 1013 * 1014 * What if properties are published on function 0 device only? 1015 * 1016 * 1017 * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required ) 1018 * What about class configs? 1019 * 1020 * If consistent, update the property on all the siblings. 1021 * set a flag on hardware shared register 1022 * The rest of the siblings will check the flag 1023 * if the flag is set, they will use the updated property 1024 * without doing any validation. 1025 */ 1026 1027 nxge_status_t 1028 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop, 1029 uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[]) 1030 { 1031 nxge_status_t status = NXGE_OK; 1032 int ddi_status = DDI_SUCCESS; 1033 int i = 0, found = 0, update_prop = B_TRUE; 1034 int *cfg_val; 1035 uint_t new_value, cfg_value[MAX_SIBLINGS]; 1036 uint_t prop_len; 1037 uint_t known_cfg_value; 1038 1039 known_cfg_value = (uint_t)known_cfg; 1040 1041 if (override == B_TRUE) { 1042 new_value = known_cfg_value; 1043 for (i = 0; i < nxgep->nports; i++) { 1044 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1045 c_dip[i], prop, new_value); 1046 #ifdef NXGE_DEBUG_ERROR 1047 if (ddi_status != DDI_PROP_SUCCESS) 1048 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1049 " property %s failed update ", prop)); 1050 #endif 1051 } 1052 if (ddi_status != DDI_PROP_SUCCESS) 1053 return (NXGE_ERROR | NXGE_DDI_FAILED); 1054 } 1055 for (i = 0; i < nxgep->nports; i++) { 1056 cfg_value[i] = known_cfg_value; 1057 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0, 1058 prop, &cfg_val, 1059 &prop_len) == DDI_PROP_SUCCESS) { 1060 cfg_value[i] = *cfg_val; 1061 ddi_prop_free(cfg_val); 1062 found++; 1063 } 1064 } 1065 1066 if (found != i) { 1067 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1068 " property %s not specified on all ports", prop)); 1069 if (found == 0) { 1070 /* not specified: Use default */ 1071 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1072 " property %s not specified on any port:" 1073 " Using default", prop)); 1074 new_value = known_cfg_value; 1075 } else { 1076 /* specified on some */ 1077 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1078 " property %s not specified" 1079 " on some ports: Using default", prop)); 1080 /* ? use p0 value instead ? */ 1081 new_value = known_cfg_value; 1082 } 1083 } else { 1084 /* check type and consistence */ 1085 /* found on all devices */ 1086 for (i = 1; i < found; i++) { 1087 if (cfg_value[i] != cfg_value[i - 1]) { 1088 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1089 " property %s inconsistent:" 1090 " Using default", prop)); 1091 new_value = known_cfg_value; 1092 break; 1093 } 1094 /* 1095 * Found on all the ports and consistent. Nothing to 1096 * do. 1097 */ 1098 update_prop = B_FALSE; 1099 } 1100 } 1101 1102 if (update_prop == B_TRUE) { 1103 for (i = 0; i < nxgep->nports; i++) { 1104 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1105 c_dip[i], prop, new_value); 1106 #ifdef NXGE_DEBUG_ERROR 1107 if (ddi_status != DDI_SUCCESS) 1108 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1109 " property %s not updating with %d" 1110 " Using default", 1111 prop, new_value)); 1112 #endif 1113 if (ddi_status != DDI_PROP_SUCCESS) 1114 status |= NXGE_DDI_FAILED; 1115 } 1116 } 1117 if (status & NXGE_DDI_FAILED) 1118 status |= NXGE_ERROR; 1119 1120 return (status); 1121 } 1122 1123 static uint64_t 1124 nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg) 1125 { 1126 int start_prop; 1127 uint64_t cfg_value; 1128 p_nxge_param_t param_arr; 1129 1130 param_arr = nxgep->param_arr; 1131 cfg_value = param_arr[class_prop].value; 1132 start_prop = param_h1_init_value; 1133 1134 /* update the properties per quick config */ 1135 switch (rx_quick_cfg) { 1136 case CFG_L3_WEB: 1137 case CFG_L3_DISTRIBUTE: 1138 cfg_value = nxge_classify_get_cfg_value(nxgep, 1139 rx_quick_cfg, class_prop - start_prop); 1140 break; 1141 default: 1142 cfg_value = param_arr[class_prop].value; 1143 break; 1144 } 1145 return (cfg_value); 1146 } 1147 1148 static nxge_status_t 1149 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[]) 1150 { 1151 nxge_status_t status = NXGE_OK; 1152 int rx_quick_cfg, class_prop, start_prop, end_prop; 1153 char *prop_name; 1154 int override = B_TRUE; 1155 uint64_t cfg_value; 1156 p_nxge_param_t param_arr; 1157 1158 param_arr = nxgep->param_arr; 1159 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 1160 start_prop = param_h1_init_value; 1161 end_prop = param_class_opt_ipv6_sctp; 1162 1163 /* update the properties per quick config */ 1164 if (rx_quick_cfg == CFG_NOT_SPECIFIED) 1165 override = B_FALSE; 1166 1167 /* 1168 * these parameter affect the classification outcome. 1169 * these parameters are used to configure the Flow key and 1170 * the TCAM key for each of the IP classes. 1171 * Included here are also the H1 and H2 initial values 1172 * which affect the distribution as well as final hash value 1173 * (hence the offset into RDC table and FCRAM bucket location) 1174 * 1175 */ 1176 for (class_prop = start_prop; class_prop <= end_prop; class_prop++) { 1177 prop_name = param_arr[class_prop].fcode_name; 1178 cfg_value = nxge_class_get_known_cfg(nxgep, 1179 class_prop, rx_quick_cfg); 1180 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1181 cfg_value, override, c_dip); 1182 } 1183 1184 /* 1185 * these properties do not affect the actual classification outcome. 1186 * used to enable/disable or tune the fflp hardware 1187 * 1188 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable 1189 * 1190 */ 1191 override = B_FALSE; 1192 for (class_prop = param_fcram_access_ratio; 1193 class_prop <= param_llc_snap_enable; class_prop++) { 1194 prop_name = param_arr[class_prop].fcode_name; 1195 cfg_value = param_arr[class_prop].value; 1196 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1197 cfg_value, override, c_dip); 1198 } 1199 1200 return (status); 1201 } 1202 1203 nxge_status_t 1204 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag) 1205 { 1206 nxge_status_t status = NXGE_OK; 1207 int i = 0, found = 0; 1208 int num_siblings; 1209 dev_info_t *c_dip[MAX_SIBLINGS + 1]; 1210 char *prop_val[MAX_SIBLINGS]; 1211 config_token_t c_token[MAX_SIBLINGS]; 1212 char *prop; 1213 1214 if (nxge_dma_obp_props_only) 1215 return (NXGE_OK); 1216 1217 num_siblings = 0; 1218 c_dip[num_siblings] = ddi_get_child(nxgep->p_dip); 1219 while (c_dip[num_siblings]) { 1220 c_dip[num_siblings + 1] = 1221 ddi_get_next_sibling(c_dip[num_siblings]); 1222 num_siblings++; 1223 } 1224 1225 switch (flag) { 1226 case COMMON_TXDMA_CFG: 1227 prop = "txdma-cfg"; 1228 break; 1229 case COMMON_RXDMA_CFG: 1230 prop = "rxdma-cfg"; 1231 break; 1232 case COMMON_RXDMA_GRP_CFG: 1233 prop = "rxdma-grp-cfg"; 1234 break; 1235 case COMMON_CLASS_CFG: 1236 status = nxge_cfg_verify_set_classify(nxgep, c_dip); 1237 return (status); 1238 default: 1239 return (NXGE_ERROR); 1240 } 1241 1242 i = 0; 1243 while (i < num_siblings) { 1244 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop, 1245 (char **)&prop_val[i]) == DDI_PROP_SUCCESS) { 1246 c_token[i] = nxge_get_config_token(prop_val[i]); 1247 ddi_prop_free(prop_val[i]); 1248 found++; 1249 } else 1250 c_token[i] = CONFIG_TOKEN_NONE; 1251 i++; 1252 } 1253 1254 if (found != i) { 1255 if (found == 0) { 1256 /* not specified: Use default */ 1257 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1258 " property %s not specified on any port:" 1259 " Using default", prop)); 1260 1261 status = nxge_update_cfg_properties(nxgep, 1262 flag, FAIR, c_dip); 1263 return (status); 1264 } else { 1265 /* 1266 * if the convention is to use function 0 device then 1267 * populate the other devices with this configuration. 1268 * 1269 * The other alternative is to use the default config. 1270 */ 1271 /* not specified: Use default */ 1272 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1273 " property %s not specified on some ports:" 1274 " Using default", prop)); 1275 status = nxge_update_cfg_properties(nxgep, 1276 flag, FAIR, c_dip); 1277 return (status); 1278 } 1279 } 1280 1281 /* check type and consistence */ 1282 /* found on all devices */ 1283 for (i = 1; i < found; i++) { 1284 if (c_token[i] != c_token[i - 1]) { 1285 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1286 " property %s inconsistent:" 1287 " Using default", prop)); 1288 status = nxge_update_cfg_properties(nxgep, 1289 flag, FAIR, c_dip); 1290 return (status); 1291 } 1292 } 1293 1294 /* 1295 * Found on all the ports check if it is custom configuration. if 1296 * custom, then verify consistence 1297 * 1298 * finally create soft properties 1299 */ 1300 status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip); 1301 return (status); 1302 } 1303 1304 nxge_status_t 1305 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep) 1306 { 1307 nxge_status_t status = NXGE_OK; 1308 int ddi_status = DDI_SUCCESS; 1309 char *prop_val; 1310 char *rx_prop; 1311 char *prop; 1312 uint32_t cfg_value = CFG_NOT_SPECIFIED; 1313 p_nxge_param_t param_arr; 1314 1315 param_arr = nxgep->param_arr; 1316 rx_prop = param_arr[param_rx_quick_cfg].fcode_name; 1317 1318 prop = "rx-quick-cfg"; 1319 1320 /* 1321 * good value are 1322 * 1323 * "web-server" "generic-server" "l3-classify" "flow-classify" 1324 */ 1325 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0, 1326 prop, (char **)&prop_val) != DDI_PROP_SUCCESS) { 1327 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1328 " property %s not specified: using default ", prop)); 1329 cfg_value = CFG_NOT_SPECIFIED; 1330 } else { 1331 cfg_value = CFG_L3_DISTRIBUTE; 1332 if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) { 1333 cfg_value = CFG_L3_WEB; 1334 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1335 " %s: web server ", prop)); 1336 } 1337 if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) { 1338 cfg_value = CFG_L3_DISTRIBUTE; 1339 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1340 " %s: distribute ", prop)); 1341 } 1342 /* more */ 1343 ddi_prop_free(prop_val); 1344 } 1345 1346 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1347 rx_prop, cfg_value); 1348 if (ddi_status != DDI_PROP_SUCCESS) 1349 status |= NXGE_DDI_FAILED; 1350 1351 /* now handle specified cases: */ 1352 if (status & NXGE_DDI_FAILED) 1353 status |= NXGE_ERROR; 1354 return (status); 1355 } 1356 1357 /* 1358 * Device properties adv-autoneg-cap etc are defined by FWARC 1359 * http://sac.sfbay/FWARC/2002/345/20020610_asif.haswarey 1360 */ 1361 static void 1362 nxge_use_cfg_link_cfg(p_nxge_t nxgep) 1363 { 1364 int *prop_val; 1365 uint_t prop_len; 1366 dev_info_t *dip; 1367 int speed; 1368 int duplex; 1369 int adv_autoneg_cap; 1370 int adv_10gfdx_cap; 1371 int adv_10ghdx_cap; 1372 int adv_1000fdx_cap; 1373 int adv_1000hdx_cap; 1374 int adv_100fdx_cap; 1375 int adv_100hdx_cap; 1376 int adv_10fdx_cap; 1377 int adv_10hdx_cap; 1378 int status = DDI_SUCCESS; 1379 1380 dip = nxgep->dip; 1381 1382 /* 1383 * first find out the card type and the supported link speeds and 1384 * features 1385 */ 1386 /* add code for card type */ 1387 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap", 1388 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1389 ddi_prop_free(prop_val); 1390 return; 1391 } 1392 1393 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap", 1394 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1395 ddi_prop_free(prop_val); 1396 return; 1397 } 1398 1399 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap", 1400 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1401 ddi_prop_free(prop_val); 1402 return; 1403 } 1404 1405 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap", 1406 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1407 ddi_prop_free(prop_val); 1408 return; 1409 } 1410 1411 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap", 1412 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1413 ddi_prop_free(prop_val); 1414 return; 1415 } 1416 1417 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap", 1418 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1419 ddi_prop_free(prop_val); 1420 return; 1421 } 1422 1423 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap", 1424 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1425 ddi_prop_free(prop_val); 1426 return; 1427 } 1428 1429 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap", 1430 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1431 ddi_prop_free(prop_val); 1432 return; 1433 } 1434 1435 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed", 1436 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1437 if (strncmp("10000", (caddr_t)prop_val, 1438 (size_t)prop_len) == 0) { 1439 speed = 10000; 1440 } else if (strncmp("1000", (caddr_t)prop_val, 1441 (size_t)prop_len) == 0) { 1442 speed = 1000; 1443 } else if (strncmp("100", (caddr_t)prop_val, 1444 (size_t)prop_len) == 0) { 1445 speed = 100; 1446 } else if (strncmp("10", (caddr_t)prop_val, 1447 (size_t)prop_len) == 0) { 1448 speed = 10; 1449 } else if (strncmp("auto", (caddr_t)prop_val, 1450 (size_t)prop_len) == 0) { 1451 speed = 0; 1452 } else { 1453 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1454 "speed property is invalid reverting to auto")); 1455 speed = 0; 1456 } 1457 ddi_prop_free(prop_val); 1458 } else 1459 speed = 0; 1460 1461 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex", 1462 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1463 if (strncmp("full", (caddr_t)prop_val, 1464 (size_t)prop_len) == 0) { 1465 duplex = 2; 1466 } else if (strncmp("half", (caddr_t)prop_val, 1467 (size_t)prop_len) == 0) { 1468 duplex = 1; 1469 } else if (strncmp("auto", (caddr_t)prop_val, 1470 (size_t)prop_len) == 0) { 1471 duplex = 0; 1472 } else { 1473 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1474 "duplex property is invalid" 1475 " reverting to auto")); 1476 duplex = 0; 1477 } 1478 ddi_prop_free(prop_val); 1479 } else 1480 duplex = 0; 1481 1482 /* speed == 0 or duplex == 0 means auto negotiation. */ 1483 adv_autoneg_cap = (speed == 0) || (duplex == 0); 1484 if (adv_autoneg_cap == 0) { 1485 adv_10gfdx_cap = ((speed == 10000) && (duplex == 2)); 1486 adv_10ghdx_cap = adv_10gfdx_cap; 1487 adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1)); 1488 adv_1000fdx_cap = adv_10ghdx_cap; 1489 adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2)); 1490 adv_1000hdx_cap = adv_1000fdx_cap; 1491 adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1)); 1492 adv_100fdx_cap = adv_1000hdx_cap; 1493 adv_100fdx_cap |= ((speed == 100) && (duplex == 2)); 1494 adv_100hdx_cap = adv_100fdx_cap; 1495 adv_100hdx_cap |= ((speed == 100) && (duplex == 1)); 1496 adv_10fdx_cap = adv_100hdx_cap; 1497 adv_10fdx_cap |= ((speed == 10) && (duplex == 2)); 1498 adv_10hdx_cap = adv_10fdx_cap; 1499 adv_10hdx_cap |= ((speed == 10) && (duplex == 1)); 1500 } else if (speed == 0) { 1501 adv_10gfdx_cap = (duplex == 2); 1502 adv_10ghdx_cap = (duplex == 1); 1503 adv_1000fdx_cap = (duplex == 2); 1504 adv_1000hdx_cap = (duplex == 1); 1505 adv_100fdx_cap = (duplex == 2); 1506 adv_100hdx_cap = (duplex == 1); 1507 adv_10fdx_cap = (duplex == 2); 1508 adv_10hdx_cap = (duplex == 1); 1509 } 1510 if (duplex == 0) { 1511 adv_10gfdx_cap = (speed == 0); 1512 adv_10gfdx_cap |= (speed == 10000); 1513 adv_10ghdx_cap = adv_10gfdx_cap; 1514 adv_10ghdx_cap |= (speed == 10000); 1515 adv_1000fdx_cap = adv_10ghdx_cap; 1516 adv_1000fdx_cap |= (speed == 1000); 1517 adv_1000hdx_cap = adv_1000fdx_cap; 1518 adv_1000hdx_cap |= (speed == 1000); 1519 adv_100fdx_cap = adv_1000hdx_cap; 1520 adv_100fdx_cap |= (speed == 100); 1521 adv_100hdx_cap = adv_100fdx_cap; 1522 adv_100hdx_cap |= (speed == 100); 1523 adv_10fdx_cap = adv_100hdx_cap; 1524 adv_10fdx_cap |= (speed == 10); 1525 adv_10hdx_cap = adv_10fdx_cap; 1526 adv_10hdx_cap |= (speed == 10); 1527 } 1528 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1529 "adv-autoneg-cap", &adv_autoneg_cap, 1); 1530 if (status) 1531 return; 1532 1533 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1534 "adv-10gfdx-cap", &adv_10gfdx_cap, 1); 1535 if (status) 1536 goto nxge_map_myargs_to_gmii_fail1; 1537 1538 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1539 "adv-10ghdx-cap", &adv_10ghdx_cap, 1); 1540 if (status) 1541 goto nxge_map_myargs_to_gmii_fail2; 1542 1543 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1544 "adv-1000fdx-cap", &adv_1000fdx_cap, 1); 1545 if (status) 1546 goto nxge_map_myargs_to_gmii_fail3; 1547 1548 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1549 "adv-1000hdx-cap", &adv_1000hdx_cap, 1); 1550 if (status) 1551 goto nxge_map_myargs_to_gmii_fail4; 1552 1553 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1554 "adv-100fdx-cap", &adv_100fdx_cap, 1); 1555 if (status) 1556 goto nxge_map_myargs_to_gmii_fail5; 1557 1558 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1559 "adv-100hdx-cap", &adv_100hdx_cap, 1); 1560 if (status) 1561 goto nxge_map_myargs_to_gmii_fail6; 1562 1563 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1564 "adv-10fdx-cap", &adv_10fdx_cap, 1); 1565 if (status) 1566 goto nxge_map_myargs_to_gmii_fail7; 1567 1568 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1569 "adv-10hdx-cap", &adv_10hdx_cap, 1); 1570 if (status) 1571 goto nxge_map_myargs_to_gmii_fail8; 1572 1573 return; 1574 1575 nxge_map_myargs_to_gmii_fail9: 1576 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap"); 1577 1578 nxge_map_myargs_to_gmii_fail8: 1579 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap"); 1580 1581 nxge_map_myargs_to_gmii_fail7: 1582 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap"); 1583 1584 nxge_map_myargs_to_gmii_fail6: 1585 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap"); 1586 1587 nxge_map_myargs_to_gmii_fail5: 1588 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap"); 1589 1590 nxge_map_myargs_to_gmii_fail4: 1591 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap"); 1592 1593 nxge_map_myargs_to_gmii_fail3: 1594 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap"); 1595 1596 nxge_map_myargs_to_gmii_fail2: 1597 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap"); 1598 1599 nxge_map_myargs_to_gmii_fail1: 1600 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap"); 1601 } 1602 1603 nxge_status_t 1604 nxge_get_config_properties(p_nxge_t nxgep) 1605 { 1606 nxge_status_t status = NXGE_OK; 1607 p_nxge_hw_list_t hw_p; 1608 1609 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties")); 1610 1611 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 1612 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1613 " nxge_get_config_properties:" 1614 " common hardware not set", nxgep->niu_type)); 1615 return (NXGE_ERROR); 1616 } 1617 1618 /* 1619 * Get info on how many ports Neptune card has. 1620 */ 1621 nxgep->nports = nxge_get_nports(nxgep); 1622 if (nxgep->nports <= 0) { 1623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1624 "<==nxge_get_config_properties: Invalid Neptune type 0x%x", 1625 nxgep->niu_type)); 1626 return (NXGE_ERROR); 1627 } 1628 nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY; 1629 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1630 nxgep->classifier.tcam_size = TCAM_NXGE_TCAM_MAX_ENTRY; 1631 } 1632 if (nxgep->function_num >= nxgep->nports) { 1633 return (NXGE_ERROR); 1634 } 1635 1636 status = nxge_get_mac_addr_properties(nxgep); 1637 if (status != NXGE_OK) 1638 return (NXGE_ERROR); 1639 1640 /* 1641 * read the configuration type. If none is specified, used default. 1642 * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM 1643 * are shared equally across all the ports. 1644 * 1645 * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional 1646 * to the port speed. 1647 * 1648 * 1649 * custom: DMA channels, RDC groups, TCAM, FCRAM partition is 1650 * specified in nxge.conf. Need to read each parameter and set 1651 * up the parameters in nxge structures. 1652 * 1653 */ 1654 switch (nxgep->niu_type) { 1655 case N2_NIU: 1656 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1657 " ==> nxge_get_config_properties: N2")); 1658 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1659 if ((hw_p->flags & COMMON_CFG_VALID) != 1660 COMMON_CFG_VALID) { 1661 status = nxge_cfg_verify_set(nxgep, 1662 COMMON_RXDMA_GRP_CFG); 1663 status = nxge_cfg_verify_set(nxgep, 1664 COMMON_CLASS_CFG); 1665 hw_p->flags |= COMMON_CFG_VALID; 1666 } 1667 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1668 status = nxge_use_cfg_n2niu_properties(nxgep); 1669 break; 1670 default: 1671 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1672 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1673 " nxge_get_config_properties:" 1674 " unknown NIU type 0x%x", nxgep->niu_type)); 1675 return (NXGE_ERROR); 1676 } 1677 1678 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1679 " ==> nxge_get_config_properties: Neptune")); 1680 status = nxge_cfg_verify_set_quick_config(nxgep); 1681 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1682 if ((hw_p->flags & COMMON_CFG_VALID) != 1683 COMMON_CFG_VALID) { 1684 status = nxge_cfg_verify_set(nxgep, 1685 COMMON_TXDMA_CFG); 1686 status = nxge_cfg_verify_set(nxgep, 1687 COMMON_RXDMA_CFG); 1688 status = nxge_cfg_verify_set(nxgep, 1689 COMMON_RXDMA_GRP_CFG); 1690 status = nxge_cfg_verify_set(nxgep, 1691 COMMON_CLASS_CFG); 1692 hw_p->flags |= COMMON_CFG_VALID; 1693 } 1694 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1695 nxge_use_cfg_neptune_properties(nxgep); 1696 status = NXGE_OK; 1697 break; 1698 } 1699 1700 /* 1701 * Get the software LSO enable flag property from the 1702 * driver configuration file (nxge.conf). 1703 * This flag will be set to disable (0) if this property 1704 * does not exist. 1705 */ 1706 nxgep->soft_lso_enable = ddi_prop_get_int(DDI_DEV_T_ANY, nxgep->dip, 1707 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, "soft-lso-enable", 0); 1708 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1709 "nxge_get_config_properties: software lso %d\n", 1710 nxgep->soft_lso_enable)); 1711 1712 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties")); 1713 return (status); 1714 } 1715 1716 static nxge_status_t 1717 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep) 1718 { 1719 nxge_status_t status = NXGE_OK; 1720 1721 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties")); 1722 1723 status = nxge_use_default_dma_config_n2(nxgep); 1724 if (status != NXGE_OK) { 1725 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1726 " ==> nxge_use_cfg_n2niu_properties (err 0x%x)", 1727 status)); 1728 return (status | NXGE_ERROR); 1729 } 1730 1731 (void) nxge_use_cfg_vlan_class_config(nxgep); 1732 (void) nxge_use_cfg_mac_class_config(nxgep); 1733 (void) nxge_use_cfg_class_config(nxgep); 1734 (void) nxge_use_cfg_link_cfg(nxgep); 1735 1736 /* 1737 * Read in the hardware (fcode) properties. Use the ndd array to read 1738 * each property. 1739 */ 1740 (void) nxge_get_param_soft_properties(nxgep); 1741 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties")); 1742 1743 return (status); 1744 } 1745 1746 static void 1747 nxge_use_cfg_neptune_properties(p_nxge_t nxgep) 1748 { 1749 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties")); 1750 1751 (void) nxge_use_cfg_dma_config(nxgep); 1752 (void) nxge_use_cfg_vlan_class_config(nxgep); 1753 (void) nxge_use_cfg_mac_class_config(nxgep); 1754 (void) nxge_use_cfg_class_config(nxgep); 1755 (void) nxge_use_cfg_link_cfg(nxgep); 1756 1757 /* 1758 * Read in the hardware (fcode) properties. Use the ndd array to read 1759 * each property. 1760 */ 1761 (void) nxge_get_param_soft_properties(nxgep); 1762 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties")); 1763 } 1764 1765 /* 1766 * FWARC 2006/556 1767 */ 1768 1769 static nxge_status_t 1770 nxge_use_default_dma_config_n2(p_nxge_t nxgep) 1771 { 1772 int ndmas; 1773 uint8_t func; 1774 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1775 p_nxge_hw_pt_cfg_t p_cfgp; 1776 int *prop_val; 1777 uint_t prop_len; 1778 int i; 1779 nxge_status_t status = NXGE_OK; 1780 1781 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2")); 1782 1783 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1784 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1785 1786 func = nxgep->function_num; 1787 p_cfgp->function_number = func; 1788 ndmas = NXGE_TDMA_PER_NIU_PORT; 1789 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1790 "tx-dma-channels", (int **)&prop_val, 1791 &prop_len) == DDI_PROP_SUCCESS) { 1792 p_cfgp->tdc.start = prop_val[0]; 1793 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1794 "==> nxge_use_default_dma_config_n2: tdc starts %d " 1795 "(#%d)", p_cfgp->tdc.start, prop_len)); 1796 1797 ndmas = prop_val[1]; 1798 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1799 "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)", 1800 ndmas, prop_len)); 1801 ddi_prop_free(prop_val); 1802 } else { 1803 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1804 "==> nxge_use_default_dma_config_n2: " 1805 "get tx-dma-channels failed")); 1806 return (NXGE_DDI_FAILED); 1807 } 1808 1809 p_cfgp->tdc.count = nxgep->max_tdcs = ndmas; 1810 p_cfgp->tdc.owned = p_cfgp->tdc.count; 1811 1812 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1813 "p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d start %d", 1814 p_cfgp, p_cfgp->tdc.count, nxgep->max_tdcs, p_cfgp->tdc.start)); 1815 1816 /* Receive DMA */ 1817 ndmas = NXGE_RDMA_PER_NIU_PORT; 1818 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1819 "rx-dma-channels", (int **)&prop_val, 1820 &prop_len) == DDI_PROP_SUCCESS) { 1821 p_cfgp->start_rdc = prop_val[0]; 1822 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1823 "==> nxge_use_default_dma_config_n2(obp): rdc start %d" 1824 " (#%d)", p_cfgp->start_rdc, prop_len)); 1825 ndmas = prop_val[1]; 1826 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1827 "==> nxge_use_default_dma_config_n2(obp):#rdc %d (#%d)", 1828 ndmas, prop_len)); 1829 ddi_prop_free(prop_val); 1830 } else { 1831 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1832 "==> nxge_use_default_dma_config_n2: " 1833 "get rx-dma-channel failed")); 1834 return (NXGE_DDI_FAILED); 1835 } 1836 1837 p_cfgp->max_rdcs = nxgep->max_rdcs = ndmas; 1838 nxgep->rdc_mask = (ndmas - 1); 1839 1840 /* Hypervisor: rdc # and group # use the same # !! */ 1841 p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->tdc.owned; 1842 p_cfgp->start_grpid = 0; 1843 p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0; 1844 1845 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1846 "interrupts", (int **)&prop_val, 1847 &prop_len) == DDI_PROP_SUCCESS) { 1848 /* 1849 * For each device assigned, the content of each interrupts 1850 * property is its logical device group. 1851 * 1852 * Assignment of interrupts property is in the the following 1853 * order: 1854 * 1855 * MAC MIF (if configured) SYSTEM ERROR (if configured) first 1856 * receive channel next channel...... last receive channel 1857 * first transmit channel next channel...... last transmit 1858 * channel 1859 * 1860 * prop_len should be at least for one mac and total # of rx and 1861 * tx channels. Function 0 owns MIF and ERROR 1862 */ 1863 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1864 "==> nxge_use_default_dma_config_n2(obp): " 1865 "# interrupts %d", prop_len)); 1866 1867 switch (func) { 1868 case 0: 1869 p_cfgp->ldg_chn_start = 3; 1870 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0; 1871 p_cfgp->mif_ldvid = NXGE_MIF_LD; 1872 p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD; 1873 1874 break; 1875 case 1: 1876 p_cfgp->ldg_chn_start = 1; 1877 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1; 1878 1879 break; 1880 default: 1881 status = NXGE_DDI_FAILED; 1882 break; 1883 } 1884 1885 if (status != NXGE_OK) 1886 return (status); 1887 1888 for (i = 0; i < prop_len; i++) { 1889 p_cfgp->ldg[i] = prop_val[i]; 1890 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1891 "==> nxge_use_default_dma_config_n2(obp): " 1892 "F%d: interrupt #%d, ldg %d", 1893 nxgep->function_num, i, p_cfgp->ldg[i])); 1894 } 1895 1896 p_cfgp->max_grpids = prop_len; 1897 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1898 "==> nxge_use_default_dma_config_n2(obp): %d " 1899 "(#%d) maxgrpids %d channel starts %d", 1900 p_cfgp->mac_ldvid, i, p_cfgp->max_grpids, 1901 p_cfgp->ldg_chn_start)); 1902 ddi_prop_free(prop_val); 1903 } else { 1904 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1905 "==> nxge_use_default_dma_config_n2: " 1906 "get interrupts failed")); 1907 return (NXGE_DDI_FAILED); 1908 } 1909 1910 p_cfgp->max_ldgs = p_cfgp->max_grpids; 1911 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1912 "==> nxge_use_default_dma_config_n2: " 1913 "p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d" 1914 "start_grpid %d macid %d mifid %d serrid %d", 1915 p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids, 1916 p_cfgp->start_grpid, 1917 p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid)); 1918 1919 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1920 "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d", 1921 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs)); 1922 1923 /* 1924 * RDC groups and the beginning RDC group assigned to this function. 1925 */ 1926 p_cfgp->max_rdc_grpids = 1; 1927 p_cfgp->def_mac_rxdma_grpid = (nxgep->function_num * 1); 1928 1929 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind 1930 (nxgep, p_cfgp->def_mac_rxdma_grpid, B_TRUE)) 1931 >= NXGE_MAX_RDC_GRPS) { 1932 NXGE_ERROR_MSG((nxgep, CFG_CTL, 1933 "nxge_use_default_dma_config_n2(): " 1934 "nxge_fzc_rdc_tbl_bind failed")); 1935 return (NXGE_DDI_FAILED); 1936 } 1937 1938 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1939 "rx-rdc-grps", p_cfgp->max_rdc_grpids); 1940 if (status) { 1941 return (NXGE_DDI_FAILED); 1942 } 1943 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1944 "rx-rdc-grps-begin", p_cfgp->def_mac_rxdma_grpid); 1945 if (status) { 1946 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 1947 "rx-rdc-grps"); 1948 return (NXGE_DDI_FAILED); 1949 } 1950 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1951 "p_cfgp $%p # rdc groups %d start rdc group id %d", 1952 p_cfgp, p_cfgp->max_rdc_grpids, 1953 p_cfgp->def_mac_rxdma_grpid)); 1954 1955 nxge_set_hw_dma_config(nxgep); 1956 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2")); 1957 return (status); 1958 } 1959 1960 static void 1961 nxge_use_cfg_dma_config(p_nxge_t nxgep) 1962 { 1963 int tx_ndmas, rx_ndmas, nrxgp, st_txdma, st_rxdma; 1964 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1965 p_nxge_hw_pt_cfg_t p_cfgp; 1966 dev_info_t *dip; 1967 p_nxge_param_t param_arr; 1968 char *prop; 1969 int *prop_val; 1970 uint_t prop_len; 1971 int i; 1972 uint8_t *ch_arr_p; 1973 1974 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config")); 1975 param_arr = nxgep->param_arr; 1976 1977 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1978 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1979 dip = nxgep->dip; 1980 p_cfgp->function_number = nxgep->function_num; 1981 prop = param_arr[param_txdma_channels_begin].fcode_name; 1982 1983 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 1984 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1985 p_cfgp->tdc.start = *prop_val; 1986 ddi_prop_free(prop_val); 1987 } else { 1988 switch (nxgep->niu_type) { 1989 case NEPTUNE_4_1GC: 1990 ch_arr_p = &tx_4_1G[0]; 1991 break; 1992 case NEPTUNE_2_10GF: 1993 ch_arr_p = &tx_2_10G[0]; 1994 break; 1995 case NEPTUNE_2_10GF_2_1GC: 1996 case NEPTUNE_2_10GF_2_1GRF: 1997 ch_arr_p = &tx_2_10G_2_1G[0]; 1998 break; 1999 case NEPTUNE_1_10GF_3_1GC: 2000 ch_arr_p = &tx_1_10G_3_1G[0]; 2001 break; 2002 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2003 ch_arr_p = &tx_1_1G_1_10G_2_1G[0]; 2004 break; 2005 default: 2006 switch (nxgep->platform_type) { 2007 case P_NEPTUNE_ALONSO: 2008 ch_arr_p = &tx_2_10G_2_1G[0]; 2009 break; 2010 default: 2011 ch_arr_p = &p4_tx_equal[0]; 2012 break; 2013 } 2014 break; 2015 } 2016 st_txdma = 0; 2017 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++) 2018 st_txdma += *ch_arr_p; 2019 2020 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2021 prop, st_txdma); 2022 p_cfgp->tdc.start = st_txdma; 2023 } 2024 2025 prop = param_arr[param_txdma_channels].fcode_name; 2026 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2027 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2028 tx_ndmas = *prop_val; 2029 ddi_prop_free(prop_val); 2030 } else { 2031 switch (nxgep->niu_type) { 2032 case NEPTUNE_4_1GC: 2033 tx_ndmas = tx_4_1G[nxgep->function_num]; 2034 break; 2035 case NEPTUNE_2_10GF: 2036 tx_ndmas = tx_2_10G[nxgep->function_num]; 2037 break; 2038 case NEPTUNE_2_10GF_2_1GC: 2039 case NEPTUNE_2_10GF_2_1GRF: 2040 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num]; 2041 break; 2042 case NEPTUNE_1_10GF_3_1GC: 2043 tx_ndmas = tx_1_10G_3_1G[nxgep->function_num]; 2044 break; 2045 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2046 tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num]; 2047 break; 2048 default: 2049 switch (nxgep->platform_type) { 2050 case P_NEPTUNE_ALONSO: 2051 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num]; 2052 break; 2053 default: 2054 tx_ndmas = p4_tx_equal[nxgep->function_num]; 2055 break; 2056 } 2057 break; 2058 } 2059 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2060 prop, tx_ndmas); 2061 } 2062 2063 p_cfgp->tdc.count = nxgep->max_tdcs = tx_ndmas; 2064 p_cfgp->tdc.owned = p_cfgp->tdc.count; 2065 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2066 "p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d", 2067 p_cfgp, p_cfgp->tdc.count, nxgep->max_tdcs)); 2068 2069 prop = param_arr[param_rxdma_channels_begin].fcode_name; 2070 2071 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2072 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2073 p_cfgp->start_rdc = *prop_val; 2074 ddi_prop_free(prop_val); 2075 } else { 2076 switch (nxgep->niu_type) { 2077 case NEPTUNE_4_1GC: 2078 ch_arr_p = &rx_4_1G[0]; 2079 break; 2080 case NEPTUNE_2_10GF: 2081 ch_arr_p = &rx_2_10G[0]; 2082 break; 2083 case NEPTUNE_2_10GF_2_1GC: 2084 case NEPTUNE_2_10GF_2_1GRF: 2085 ch_arr_p = &rx_2_10G_2_1G[0]; 2086 break; 2087 case NEPTUNE_1_10GF_3_1GC: 2088 ch_arr_p = &rx_1_10G_3_1G[0]; 2089 break; 2090 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2091 ch_arr_p = &rx_1_1G_1_10G_2_1G[0]; 2092 break; 2093 default: 2094 switch (nxgep->platform_type) { 2095 case P_NEPTUNE_ALONSO: 2096 ch_arr_p = &rx_2_10G_2_1G[0]; 2097 break; 2098 default: 2099 ch_arr_p = &p4_rx_equal[0]; 2100 break; 2101 } 2102 break; 2103 } 2104 st_rxdma = 0; 2105 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++) 2106 st_rxdma += *ch_arr_p; 2107 2108 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2109 prop, st_rxdma); 2110 p_cfgp->start_rdc = st_rxdma; 2111 } 2112 2113 prop = param_arr[param_rxdma_channels].fcode_name; 2114 2115 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2116 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2117 rx_ndmas = *prop_val; 2118 ddi_prop_free(prop_val); 2119 } else { 2120 switch (nxgep->niu_type) { 2121 case NEPTUNE_4_1GC: 2122 rx_ndmas = rx_4_1G[nxgep->function_num]; 2123 break; 2124 case NEPTUNE_2_10GF: 2125 rx_ndmas = rx_2_10G[nxgep->function_num]; 2126 break; 2127 case NEPTUNE_2_10GF_2_1GC: 2128 case NEPTUNE_2_10GF_2_1GRF: 2129 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num]; 2130 break; 2131 case NEPTUNE_1_10GF_3_1GC: 2132 rx_ndmas = rx_1_10G_3_1G[nxgep->function_num]; 2133 break; 2134 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2135 rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num]; 2136 break; 2137 default: 2138 switch (nxgep->platform_type) { 2139 case P_NEPTUNE_ALONSO: 2140 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num]; 2141 break; 2142 default: 2143 rx_ndmas = p4_rx_equal[nxgep->function_num]; 2144 break; 2145 } 2146 break; 2147 } 2148 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2149 prop, rx_ndmas); 2150 } 2151 2152 p_cfgp->max_rdcs = nxgep->max_rdcs = rx_ndmas; 2153 2154 prop = param_arr[param_rdc_grps_start].fcode_name; 2155 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2156 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2157 p_cfgp->def_mac_rxdma_grpid = *prop_val; 2158 ddi_prop_free(prop_val); 2159 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind 2160 (nxgep, p_cfgp->def_mac_rxdma_grpid, B_TRUE)) 2161 >= NXGE_MAX_RDC_GRPS) { 2162 NXGE_ERROR_MSG((nxgep, CFG_CTL, 2163 "nxge_use_cfg_dma_config(): " 2164 "nxge_fzc_rdc_tbl_bind failed")); 2165 cmn_err(CE_CONT, "nxge%d: group not available!\n", 2166 nxgep->instance); 2167 goto nxge_use_cfg_dma_config_exit; 2168 } 2169 2170 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2171 "==> nxge_use_default_dma_config: " 2172 "use property " "start_grpid %d ", 2173 p_cfgp->start_grpid)); 2174 } else { 2175 p_cfgp->def_mac_rxdma_grpid = nxgep->function_num; 2176 if ((p_cfgp->def_mac_rxdma_grpid = nxge_fzc_rdc_tbl_bind( 2177 nxgep, p_cfgp->def_mac_rxdma_grpid, B_TRUE)) >= 2178 NXGE_MAX_RDC_GRPS) { 2179 cmn_err(CE_CONT, "nxge%d: group not available!\n", 2180 nxgep->instance); 2181 goto nxge_use_cfg_dma_config_exit; 2182 } 2183 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2184 prop, p_cfgp->def_mac_rxdma_grpid); 2185 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2186 "==> nxge_use_default_dma_config: " 2187 "use default " 2188 "start_grpid %d (same as function #)", 2189 p_cfgp->start_grpid)); 2190 } 2191 2192 prop = param_arr[param_rx_rdc_grps].fcode_name; 2193 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2194 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2195 nrxgp = *prop_val; 2196 ddi_prop_free(prop_val); 2197 } else { 2198 nrxgp = 1; 2199 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2200 prop, nrxgp); 2201 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2202 "==> nxge_use_default_dma_config: " 2203 "num_rdc_grpid not found: use def:# of " 2204 "rdc groups %d\n", nrxgp)); 2205 } 2206 2207 p_cfgp->max_rdc_grpids = nrxgp; 2208 2209 /* 2210 * 2/4 ports have the same hard-wired logical groups assigned. 2211 */ 2212 p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS; 2213 p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS; 2214 2215 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: " 2216 "p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d" 2217 "start_grpid %d", 2218 p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids, 2219 p_cfgp->start_grpid)); 2220 2221 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2222 "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d " 2223 "def_mac_rxdma_grpid %d", 2224 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs, 2225 p_cfgp->def_mac_rxdma_grpid)); 2226 2227 prop = param_arr[param_rxdma_intr_time].fcode_name; 2228 2229 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2230 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2231 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2232 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2233 nxgep->dip, prop, prop_val, prop_len); 2234 } 2235 ddi_prop_free(prop_val); 2236 } 2237 prop = param_arr[param_rxdma_intr_pkts].fcode_name; 2238 2239 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2240 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2241 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2242 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2243 nxgep->dip, prop, prop_val, prop_len); 2244 } 2245 ddi_prop_free(prop_val); 2246 } 2247 nxge_set_hw_dma_config(nxgep); 2248 2249 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: " 2250 "sTDC[%d] nTDC[%d] sRDC[%d] nRDC[%d]", 2251 p_cfgp->tdc.start, p_cfgp->tdc.count, 2252 p_cfgp->start_rdc, p_cfgp->max_rdcs)); 2253 2254 nxge_use_cfg_dma_config_exit: 2255 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config")); 2256 } 2257 2258 void 2259 nxge_get_logical_props(p_nxge_t nxgep) 2260 { 2261 nxge_dma_pt_cfg_t *port = &nxgep->pt_config; 2262 nxge_hw_pt_cfg_t *hardware; 2263 nxge_rdc_grp_t *group; 2264 2265 (void) memset(port, 0, sizeof (*port)); 2266 2267 port->mac_port = 0; /* := function number */ 2268 2269 /* 2270 * alloc_buf_size: 2271 * dead variables. 2272 */ 2273 port->rbr_size = nxge_rbr_size; 2274 port->rcr_size = nxge_rcr_size; 2275 2276 port->tx_dma_map = 0; /* Transmit DMA channel bit map */ 2277 2278 nxge_set_rdc_intr_property(nxgep); 2279 2280 port->rcr_full_header = NXGE_RCR_FULL_HEADER; 2281 port->rx_drr_weight = PT_DRR_WT_DEFAULT_10G; 2282 2283 /* ----------------------------------------------------- */ 2284 hardware = &port->hw_config; 2285 2286 (void) memset(hardware, 0, sizeof (*hardware)); 2287 2288 /* 2289 * partition_id, read_write_mode: 2290 * dead variables. 2291 */ 2292 2293 /* 2294 * drr_wt, rx_full_header, *_ldg?, start_mac_entry, 2295 * mac_pref, def_mac_rxdma_grpid, start_vlan, max_vlans, 2296 * start_ldgs, max_ldgs, max_ldvs, 2297 * vlan_pref, def_vlan_rxdma_grpid are meaningful only 2298 * in the service domain. 2299 */ 2300 2301 group = &port->rdc_grps[0]; 2302 2303 group->flag = 1; /* configured */ 2304 group->config_method = RDC_TABLE_ENTRY_METHOD_REP; 2305 2306 /* HIO futures: this is still an open question. */ 2307 hardware->max_macs = 1; 2308 } 2309 2310 static void 2311 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep) 2312 { 2313 uint_t vlan_cnt; 2314 int *vlan_cfg_val; 2315 int status; 2316 p_nxge_param_t param_arr; 2317 char *prop; 2318 2319 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config")); 2320 param_arr = nxgep->param_arr; 2321 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2322 2323 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2324 &vlan_cfg_val, &vlan_cnt); 2325 if (status == DDI_PROP_SUCCESS) { 2326 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2327 nxgep->dip, prop, vlan_cfg_val, vlan_cnt); 2328 ddi_prop_free(vlan_cfg_val); 2329 } 2330 nxge_set_hw_vlan_class_config(nxgep); 2331 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config")); 2332 } 2333 2334 static void 2335 nxge_use_cfg_mac_class_config(p_nxge_t nxgep) 2336 { 2337 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2338 p_nxge_hw_pt_cfg_t p_cfgp; 2339 uint_t mac_cnt; 2340 int *mac_cfg_val; 2341 int status; 2342 p_nxge_param_t param_arr; 2343 char *prop; 2344 2345 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config")); 2346 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2347 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2348 p_cfgp->start_mac_entry = 0; 2349 param_arr = nxgep->param_arr; 2350 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2351 2352 switch (nxgep->function_num) { 2353 case 0: 2354 case 1: 2355 /* 10G ports */ 2356 p_cfgp->max_macs = NXGE_MAX_MACS_XMACS; 2357 break; 2358 case 2: 2359 case 3: 2360 /* 1G ports */ 2361 default: 2362 p_cfgp->max_macs = NXGE_MAX_MACS_BMACS; 2363 break; 2364 } 2365 2366 p_cfgp->mac_pref = 1; 2367 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2368 "== nxge_use_cfg_mac_class_config: " 2369 " mac_pref bit set def_mac_rxdma_grpid %d", 2370 p_cfgp->def_mac_rxdma_grpid)); 2371 2372 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2373 &mac_cfg_val, &mac_cnt); 2374 if (status == DDI_PROP_SUCCESS) { 2375 if (mac_cnt <= p_cfgp->max_macs) 2376 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2377 nxgep->dip, prop, mac_cfg_val, mac_cnt); 2378 ddi_prop_free(mac_cfg_val); 2379 } 2380 nxge_set_hw_mac_class_config(nxgep); 2381 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config")); 2382 } 2383 2384 static void 2385 nxge_use_cfg_class_config(p_nxge_t nxgep) 2386 { 2387 nxge_set_hw_class_config(nxgep); 2388 } 2389 2390 static void 2391 nxge_set_rdc_intr_property(p_nxge_t nxgep) 2392 { 2393 int i; 2394 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2395 2396 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property")); 2397 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2398 2399 for (i = 0; i < NXGE_MAX_RDCS; i++) { 2400 p_dma_cfgp->rcr_timeout[i] = nxge_rcr_timeout; 2401 p_dma_cfgp->rcr_threshold[i] = nxge_rcr_threshold; 2402 } 2403 2404 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property")); 2405 } 2406 2407 static void 2408 nxge_set_hw_dma_config(p_nxge_t nxgep) 2409 { 2410 int i, ndmas, ngrps, bitmap, end, st_rdc; 2411 int32_t status; 2412 uint8_t rdcs_per_grp; 2413 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2414 p_nxge_hw_pt_cfg_t p_cfgp; 2415 p_nxge_rdc_grp_t rdc_grp_p; 2416 int rdcgrp_cfg = CFG_NOT_SPECIFIED, rx_quick_cfg; 2417 char *prop, *prop_val; 2418 p_nxge_param_t param_arr; 2419 config_token_t token; 2420 nxge_grp_t *group; 2421 2422 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config")); 2423 2424 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2425 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2426 rdc_grp_p = p_dma_cfgp->rdc_grps; 2427 2428 bitmap = 0; 2429 end = p_cfgp->tdc.start + p_cfgp->tdc.owned; 2430 p_dma_cfgp->tx_dma_map = 0; 2431 for (i = p_cfgp->tdc.start; i < end; i++) { 2432 bitmap |= (1 << i); 2433 } 2434 2435 nxgep->tx_set.owned.map |= bitmap; /* Owned, & not shared. */ 2436 2437 group = (nxge_grp_t *)nxge_grp_add(nxgep, NXGE_TRANSMIT_GROUP); 2438 group->map = bitmap; 2439 2440 p_dma_cfgp->tx_dma_map = bitmap; 2441 param_arr = nxgep->param_arr; 2442 2443 /* Assume RDCs are evenly distributed */ 2444 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 2445 switch (rx_quick_cfg) { 2446 case CFG_NOT_SPECIFIED: 2447 prop = "rxdma-grp-cfg"; 2448 status = ddi_prop_lookup_string(DDI_DEV_T_NONE, 2449 nxgep->dip, 0, prop, (char **)&prop_val); 2450 if (status != DDI_PROP_SUCCESS) { 2451 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2452 " property %s not found", prop)); 2453 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2454 } else { 2455 token = nxge_get_config_token(prop_val); 2456 switch (token) { 2457 case L2_CLASSIFY: 2458 break; 2459 case CLASSIFY: 2460 case L3_CLASSIFY: 2461 case L3_DISTRIBUTE: 2462 case L3_TCAM: 2463 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2464 break; 2465 default: 2466 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2467 break; 2468 } 2469 ddi_prop_free(prop_val); 2470 } 2471 break; 2472 case CFG_L3_WEB: 2473 case CFG_L3_DISTRIBUTE: 2474 case CFG_L2_CLASSIFY: 2475 case CFG_L3_TCAM: 2476 rdcgrp_cfg = rx_quick_cfg; 2477 break; 2478 default: 2479 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2480 break; 2481 } 2482 2483 st_rdc = p_cfgp->start_rdc; 2484 2485 switch (rdcgrp_cfg) { 2486 case CFG_L3_DISTRIBUTE: 2487 case CFG_L3_WEB: 2488 case CFG_L3_TCAM: 2489 ndmas = p_cfgp->max_rdcs; 2490 ngrps = 1; 2491 rdcs_per_grp = ndmas / ngrps; 2492 break; 2493 case CFG_L2_CLASSIFY: 2494 ndmas = p_cfgp->max_rdcs / 2; 2495 if (p_cfgp->max_rdcs < 2) 2496 ndmas = 1; 2497 ngrps = 1; 2498 rdcs_per_grp = ndmas / ngrps; 2499 break; 2500 default: 2501 ngrps = p_cfgp->max_rdc_grpids; 2502 ndmas = p_cfgp->max_rdcs; 2503 rdcs_per_grp = ndmas / ngrps; 2504 break; 2505 } 2506 2507 for (i = 0; i < ngrps; i++) { 2508 uint8_t count = rdcs_per_grp; 2509 dc_map_t map = 0; 2510 2511 rdc_grp_p = &p_dma_cfgp->rdc_grps[ 2512 p_cfgp->def_mac_rxdma_grpid + i]; 2513 rdc_grp_p->start_rdc = st_rdc + i * rdcs_per_grp; 2514 rdc_grp_p->max_rdcs = rdcs_per_grp; 2515 rdc_grp_p->def_rdc = rdc_grp_p->start_rdc; 2516 2517 /* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */ 2518 while (count) { 2519 map |= (1 << count); 2520 count--; 2521 } 2522 map >>= 1; /* In case <start_rdc> is zero (0) */ 2523 map <<= rdc_grp_p->start_rdc; 2524 rdc_grp_p->map = map; 2525 2526 nxgep->rx_set.owned.map |= map; /* Owned, & not shared. */ 2527 2528 group = (nxge_grp_t *)nxge_grp_add(nxgep, NXGE_RECEIVE_GROUP); 2529 group->map = rdc_grp_p->map; 2530 2531 rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ; 2532 rdc_grp_p->flag = 1; /* This group has been configured. */ 2533 } 2534 2535 2536 /* default RDC */ 2537 p_cfgp->def_rdc = p_cfgp->start_rdc; 2538 nxgep->def_rdc = p_cfgp->start_rdc; 2539 2540 /* full 18 byte header ? */ 2541 p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER; 2542 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G; 2543 if (nxgep->function_num > 1) 2544 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G; 2545 p_dma_cfgp->rbr_size = nxge_rbr_size; 2546 p_dma_cfgp->rcr_size = nxge_rcr_size; 2547 2548 nxge_set_rdc_intr_property(nxgep); 2549 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config")); 2550 } 2551 2552 boolean_t 2553 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc) 2554 { 2555 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2556 p_nxge_hw_pt_cfg_t p_cfgp; 2557 int status = B_TRUE; 2558 2559 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member")); 2560 2561 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2562 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2563 2564 /* Receive DMA Channels */ 2565 if (rdc < p_cfgp->max_rdcs) 2566 status = B_TRUE; 2567 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member")); 2568 return (status); 2569 } 2570 2571 boolean_t 2572 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc) 2573 { 2574 int status = B_FALSE; 2575 2576 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_txdma_port_member")); 2577 2578 if (tdc >= nxgep->pt_config.hw_config.tdc.start && 2579 tdc < nxgep->pt_config.hw_config.tdc.count) 2580 status = B_TRUE; 2581 2582 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_txdma_port_member")); 2583 return (status); 2584 } 2585 2586 boolean_t 2587 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc) 2588 { 2589 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2590 int status = B_TRUE; 2591 p_nxge_rdc_grp_t rdc_grp_p; 2592 2593 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2594 " ==> nxge_check_rxdma_rdcgrp_member")); 2595 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " nxge_check_rxdma_rdcgrp_member" 2596 " rdc %d group %d", rdc, rdc_grp)); 2597 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2598 2599 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 2600 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " max %d ", rdc_grp_p->max_rdcs)); 2601 if (rdc >= rdc_grp_p->max_rdcs) { 2602 status = B_FALSE; 2603 } 2604 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2605 " <== nxge_check_rxdma_rdcgrp_member")); 2606 return (status); 2607 } 2608 2609 boolean_t 2610 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp) 2611 { 2612 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2613 p_nxge_hw_pt_cfg_t p_cfgp; 2614 int status = B_TRUE; 2615 2616 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member")); 2617 2618 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2619 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2620 2621 if (rdc_grp >= p_cfgp->max_rdc_grpids) 2622 status = B_FALSE; 2623 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member")); 2624 return (status); 2625 } 2626 2627 static void 2628 nxge_set_hw_vlan_class_config(p_nxge_t nxgep) 2629 { 2630 int i; 2631 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2632 p_nxge_hw_pt_cfg_t p_cfgp; 2633 p_nxge_param_t param_arr; 2634 uint_t vlan_cnt; 2635 int *vlan_cfg_val; 2636 nxge_param_map_t *vmap; 2637 char *prop; 2638 p_nxge_class_pt_cfg_t p_class_cfgp; 2639 uint32_t good_cfg[32]; 2640 int good_count = 0; 2641 nxge_mv_cfg_t *vlan_tbl; 2642 2643 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config")); 2644 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2645 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2646 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2647 2648 param_arr = nxgep->param_arr; 2649 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2650 2651 /* 2652 * By default, VLAN to RDC group mapping is disabled Need to read HW or 2653 * .conf properties to find out if mapping is required 2654 * 2655 * Format 2656 * 2657 * uint32_t array, each array entry specifying the VLAN id and the 2658 * mapping 2659 * 2660 * bit[30] = add bit[29] = remove bit[28] = preference bits[23-16] = 2661 * rdcgrp bits[15-0] = VLAN ID ( ) 2662 */ 2663 2664 for (i = 0; i < NXGE_MAX_VLANS; i++) { 2665 p_class_cfgp->vlan_tbl[i].flag = 0; 2666 } 2667 2668 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 2669 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2670 &vlan_cfg_val, &vlan_cnt) == DDI_PROP_SUCCESS) { 2671 for (i = 0; i < vlan_cnt; i++) { 2672 vmap = (nxge_param_map_t *)&vlan_cfg_val[i]; 2673 if ((vmap->param_id) && 2674 (vmap->param_id < NXGE_MAX_VLANS) && 2675 (vmap->map_to < 2676 p_cfgp->max_rdc_grpids) && 2677 (vmap->map_to >= (uint8_t)0)) { 2678 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2679 " nxge_vlan_config mapping" 2680 " id %d grp %d", 2681 vmap->param_id, vmap->map_to)); 2682 good_cfg[good_count] = vlan_cfg_val[i]; 2683 if (vlan_tbl[vmap->param_id].flag == 0) 2684 good_count++; 2685 vlan_tbl[vmap->param_id].flag = 1; 2686 vlan_tbl[vmap->param_id].rdctbl = 2687 vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 2688 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 2689 } 2690 } 2691 ddi_prop_free(vlan_cfg_val); 2692 if (good_count != vlan_cnt) { 2693 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2694 nxgep->dip, prop, (int *)good_cfg, good_count); 2695 } 2696 } 2697 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config")); 2698 } 2699 2700 static void 2701 nxge_set_hw_mac_class_config(p_nxge_t nxgep) 2702 { 2703 int i; 2704 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2705 p_nxge_hw_pt_cfg_t p_cfgp; 2706 p_nxge_param_t param_arr; 2707 uint_t mac_cnt; 2708 int *mac_cfg_val; 2709 nxge_param_map_t *mac_map; 2710 char *prop; 2711 p_nxge_class_pt_cfg_t p_class_cfgp; 2712 int good_count = 0; 2713 int good_cfg[NXGE_MAX_MACS]; 2714 nxge_mv_cfg_t *mac_host_info; 2715 2716 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config")); 2717 2718 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2719 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2720 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2721 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 2722 2723 param_arr = nxgep->param_arr; 2724 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2725 2726 for (i = 0; i < NXGE_MAX_MACS; i++) { 2727 p_class_cfgp->mac_host_info[i].flag = 0; 2728 p_class_cfgp->mac_host_info[i].rdctbl = 2729 p_cfgp->def_mac_rxdma_grpid; 2730 } 2731 2732 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2733 &mac_cfg_val, &mac_cnt) == DDI_PROP_SUCCESS) { 2734 for (i = 0; i < mac_cnt; i++) { 2735 mac_map = (nxge_param_map_t *)&mac_cfg_val[i]; 2736 if ((mac_map->param_id < p_cfgp->max_macs) && 2737 (mac_map->map_to < 2738 p_cfgp->max_rdc_grpids) && 2739 (mac_map->map_to >= (uint8_t)0)) { 2740 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2741 " nxge_mac_config mapping" 2742 " id %d grp %d", 2743 mac_map->param_id, mac_map->map_to)); 2744 mac_host_info[mac_map->param_id].mpr_npr = 2745 mac_map->pref; 2746 mac_host_info[mac_map->param_id].rdctbl = 2747 mac_map->map_to + 2748 p_cfgp->def_mac_rxdma_grpid; 2749 good_cfg[good_count] = mac_cfg_val[i]; 2750 if (mac_host_info[mac_map->param_id].flag == 0) 2751 good_count++; 2752 mac_host_info[mac_map->param_id].flag = 1; 2753 } 2754 } 2755 ddi_prop_free(mac_cfg_val); 2756 if (good_count != mac_cnt) { 2757 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2758 nxgep->dip, prop, good_cfg, good_count); 2759 } 2760 } 2761 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config")); 2762 } 2763 2764 static void 2765 nxge_set_hw_class_config(p_nxge_t nxgep) 2766 { 2767 int i; 2768 p_nxge_param_t param_arr; 2769 int *int_prop_val; 2770 uint32_t cfg_value; 2771 char *prop; 2772 p_nxge_class_pt_cfg_t p_class_cfgp; 2773 int start_prop, end_prop; 2774 uint_t prop_cnt; 2775 2776 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config")); 2777 2778 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2779 param_arr = nxgep->param_arr; 2780 start_prop = param_class_opt_ip_usr4; 2781 end_prop = param_class_opt_ipv6_sctp; 2782 2783 for (i = start_prop; i <= end_prop; i++) { 2784 prop = param_arr[i].fcode_name; 2785 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 2786 0, prop, &int_prop_val, 2787 &prop_cnt) == DDI_PROP_SUCCESS) { 2788 cfg_value = (uint32_t)*int_prop_val; 2789 ddi_prop_free(int_prop_val); 2790 } else { 2791 cfg_value = (uint32_t)param_arr[i].value; 2792 } 2793 p_class_cfgp->class_cfg[i - start_prop] = cfg_value; 2794 } 2795 2796 prop = param_arr[param_h1_init_value].fcode_name; 2797 2798 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2799 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) { 2800 cfg_value = (uint32_t)*int_prop_val; 2801 ddi_prop_free(int_prop_val); 2802 } else { 2803 cfg_value = (uint32_t)param_arr[param_h1_init_value].value; 2804 } 2805 2806 p_class_cfgp->init_h1 = (uint32_t)cfg_value; 2807 prop = param_arr[param_h2_init_value].fcode_name; 2808 2809 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2810 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) { 2811 cfg_value = (uint32_t)*int_prop_val; 2812 ddi_prop_free(int_prop_val); 2813 } else { 2814 cfg_value = (uint32_t)param_arr[param_h2_init_value].value; 2815 } 2816 2817 p_class_cfgp->init_h2 = (uint16_t)cfg_value; 2818 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config")); 2819 } 2820 2821 nxge_status_t 2822 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 2823 { 2824 int i, maxldvs, maxldgs, nldvs; 2825 int ldv, endldg; 2826 uint8_t func; 2827 uint8_t channel; 2828 uint8_t chn_start; 2829 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 2830 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2831 p_nxge_hw_pt_cfg_t p_cfgp; 2832 p_nxge_ldgv_t ldgvp; 2833 p_nxge_ldg_t ldgp, ptr; 2834 p_nxge_ldv_t ldvp, sysldvp; 2835 nxge_status_t status = NXGE_OK; 2836 nxge_grp_set_t *set; 2837 2838 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2")); 2839 if (!*navail_p) { 2840 *nrequired_p = 0; 2841 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2842 "<== nxge_ldgv_init:no avail")); 2843 return (NXGE_ERROR); 2844 } 2845 /* 2846 * N2/NIU: one logical device owns one logical group. and each 2847 * device/group will be assigned one vector by Hypervisor. 2848 */ 2849 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2850 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2851 maxldgs = p_cfgp->max_ldgs; 2852 if (!maxldgs) { 2853 /* No devices configured. */ 2854 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: " 2855 "no logical groups configured.")); 2856 return (NXGE_ERROR); 2857 } else { 2858 maxldvs = maxldgs + 1; 2859 } 2860 2861 /* 2862 * If function zero instance, it needs to handle the system and MIF 2863 * error interrupts. MIF interrupt may not be needed for N2/NIU. 2864 */ 2865 func = nxgep->function_num; 2866 if (func == 0) { 2867 own_sys_err = B_TRUE; 2868 if (!p_cfgp->ser_ldvid) { 2869 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2870 "nxge_ldgv_init_n2: func 0, ERR ID not set!")); 2871 } 2872 /* MIF interrupt */ 2873 if (!p_cfgp->mif_ldvid) { 2874 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2875 "nxge_ldgv_init_n2: func 0, MIF ID not set!")); 2876 } 2877 } 2878 2879 /* 2880 * Assume single partition, each function owns mac. 2881 */ 2882 if (!nxge_use_partition) 2883 own_fzc = B_TRUE; 2884 2885 ldgvp = nxgep->ldgvp; 2886 if (ldgvp == NULL) { 2887 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 2888 nxgep->ldgvp = ldgvp; 2889 ldgvp->maxldgs = (uint8_t)maxldgs; 2890 ldgvp->maxldvs = (uint8_t)maxldvs; 2891 ldgp = ldgvp->ldgp = KMEM_ZALLOC( 2892 sizeof (nxge_ldg_t) * maxldgs, KM_SLEEP); 2893 ldvp = ldgvp->ldvp = KMEM_ZALLOC( 2894 sizeof (nxge_ldv_t) * maxldvs, KM_SLEEP); 2895 } else { 2896 ldgp = ldgvp->ldgp; 2897 ldvp = ldgvp->ldvp; 2898 } 2899 2900 ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs; 2901 ldgvp->tmres = NXGE_TIMER_RESO; 2902 2903 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2904 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d", 2905 maxldvs, maxldgs)); 2906 2907 /* logical start_ldg is ldv */ 2908 ptr = ldgp; 2909 for (i = 0; i < maxldgs; i++) { 2910 ptr->func = func; 2911 ptr->arm = B_TRUE; 2912 ptr->vldg_index = (uint8_t)i; 2913 ptr->ldg_timer = NXGE_TIMER_LDG; 2914 ptr->ldg = p_cfgp->ldg[i]; 2915 ptr->sys_intr_handler = nxge_intr; 2916 ptr->nldvs = 0; 2917 ptr->ldvp = NULL; 2918 ptr->nxgep = nxgep; 2919 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2920 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d " 2921 "ldg %d ldgptr $%p", 2922 maxldvs, maxldgs, ptr->ldg, ptr)); 2923 ptr++; 2924 } 2925 2926 endldg = NXGE_INT_MAX_LDG; 2927 nldvs = 0; 2928 ldgvp->nldvs = 0; 2929 ldgp->ldvp = NULL; 2930 *nrequired_p = 0; 2931 2932 /* 2933 * logical device group table is organized in the following order (same 2934 * as what interrupt property has). function 0: owns MAC, MIF, error, 2935 * rx, tx. function 1: owns MAC, rx, tx. 2936 */ 2937 2938 if (own_fzc && p_cfgp->mac_ldvid) { 2939 /* Each function should own MAC interrupt */ 2940 ldv = p_cfgp->mac_ldvid; 2941 ldvp->ldv = (uint8_t)ldv; 2942 ldvp->is_mac = B_TRUE; 2943 ldvp->ldv_intr_handler = nxge_mac_intr; 2944 ldvp->ldv_ldf_masks = 0; 2945 ldvp->nxgep = nxgep; 2946 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2947 "==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d " 2948 "ldg %d ldgptr $%p ldvptr $%p", 2949 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2950 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2951 nldvs++; 2952 } 2953 2954 if (own_fzc && p_cfgp->mif_ldvid) { 2955 ldv = p_cfgp->mif_ldvid; 2956 ldvp->ldv = (uint8_t)ldv; 2957 ldvp->is_mif = B_TRUE; 2958 ldvp->ldv_intr_handler = nxge_mif_intr; 2959 ldvp->ldv_ldf_masks = 0; 2960 ldvp->nxgep = nxgep; 2961 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2962 "==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d " 2963 "ldg %d ldgptr $%p ldvptr $%p", 2964 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2965 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2966 nldvs++; 2967 } 2968 2969 /* 2970 * Port0 uses the HW based syserr interrupt, and port1 uses the 2971 * SW based syserr interrupt. There is only one syserr and the 2972 * function zero device gets it. 2973 */ 2974 if (own_sys_err && p_cfgp->ser_ldvid) { 2975 ldv = p_cfgp->ser_ldvid; 2976 /* 2977 * Port0 - HW based: use an intr vector 2978 */ 2979 /* 2980 * Unmask the system interrupt states. 2981 */ 2982 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 2983 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 2984 SYS_ERR_ZCP_MASK); 2985 2986 ldvp->use_timer = B_TRUE; 2987 ldvp->ldv = (uint8_t)ldv; 2988 ldvp->is_syserr = B_TRUE; 2989 ldvp->ldv_intr_handler = nxge_syserr_intr; 2990 ldvp->ldv_ldf_masks = 0; 2991 ldvp->nxgep = nxgep; 2992 ldgvp->ldvp_syserr = ldvp; 2993 2994 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2995 "==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d " 2996 "ldg %d ldgptr $%p ldvptr p%p", 2997 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2998 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2999 nldvs++; 3000 } else { 3001 /* 3002 * Port1 - SW based: allocate the ldv for the syserr since 3003 * the vector should not be consumed for port1 3004 */ 3005 sysldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t), KM_SLEEP); 3006 sysldvp->use_timer = B_TRUE; 3007 sysldvp->ldv = NXGE_SYS_ERROR_LD; 3008 sysldvp->is_syserr = B_TRUE; 3009 sysldvp->ldv_intr_handler = nxge_syserr_intr; 3010 sysldvp->ldv_ldf_masks = 0; 3011 sysldvp->nxgep = nxgep; 3012 ldgvp->ldvp_syserr = sysldvp; 3013 ldgvp->ldvp_syserr_allocated = B_TRUE; 3014 } 3015 3016 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3017 "(before rx) func %d nldvs %d navail %d nrequired %d", 3018 func, nldvs, *navail_p, *nrequired_p)); 3019 3020 /* 3021 * Start with RDC to configure logical devices for each group. 3022 */ 3023 chn_start = p_cfgp->ldg_chn_start; 3024 set = &nxgep->rx_set; 3025 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 3026 if ((1 << channel) & set->owned.map) { 3027 ldvp->is_rxdma = B_TRUE; 3028 ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START; 3029 ldvp->channel = channel; 3030 ldvp->vdma_index = (uint8_t)channel; 3031 ldvp->ldv_intr_handler = nxge_rx_intr; 3032 ldvp->ldv_ldf_masks = 0; 3033 ldvp->nxgep = nxgep; 3034 ldgp->ldg = p_cfgp->ldg[chn_start]; 3035 3036 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3037 "==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d " 3038 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx", 3039 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3040 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv, 3041 endldg, nrequired_p); 3042 nldvs++; 3043 chn_start++; 3044 } 3045 } 3046 3047 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3048 "func %d nldvs %d navail %d nrequired %d", 3049 func, nldvs, *navail_p, *nrequired_p)); 3050 3051 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3052 "func %d nldvs %d navail %d nrequired %d ldgp 0x%llx " 3053 "ldvp 0x%llx", 3054 func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp)); 3055 /* 3056 * Transmit DMA channels. 3057 */ 3058 chn_start = p_cfgp->ldg_chn_start + 8; 3059 set = &nxgep->tx_set; 3060 for (channel = 0; channel < NXGE_MAX_TDCS; channel++) { 3061 if ((1 << channel) & set->owned.map) { 3062 ldvp->is_txdma = B_TRUE; 3063 ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START; 3064 ldvp->channel = channel; 3065 ldvp->vdma_index = (uint8_t)channel; 3066 ldvp->ldv_intr_handler = nxge_tx_intr; 3067 ldvp->ldv_ldf_masks = 0; 3068 ldgp->ldg = p_cfgp->ldg[chn_start]; 3069 ldvp->nxgep = nxgep; 3070 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3071 "==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d " 3072 "ldg %d ldgptr %p ldvptr %p", 3073 channel, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 3074 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv, 3075 endldg, nrequired_p); 3076 nldvs++; 3077 chn_start++; 3078 } 3079 } 3080 3081 ldgvp->ldg_intrs = *nrequired_p; 3082 ldgvp->nldvs = (uint8_t)nldvs; 3083 3084 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 3085 "func %d nldvs %d maxgrps %d navail %d nrequired %d", 3086 func, nldvs, maxldgs, *navail_p, *nrequired_p)); 3087 3088 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2")); 3089 return (status); 3090 } 3091 3092 /* 3093 * Interrupts related interface functions. 3094 */ 3095 3096 nxge_status_t 3097 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 3098 { 3099 int i, maxldvs, maxldgs, nldvs; 3100 int ldv, ldg, endldg, ngrps; 3101 uint8_t func; 3102 uint8_t channel; 3103 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 3104 p_nxge_dma_pt_cfg_t p_dma_cfgp; 3105 p_nxge_hw_pt_cfg_t p_cfgp; 3106 p_nxge_ldgv_t ldgvp; 3107 p_nxge_ldg_t ldgp, ptr; 3108 p_nxge_ldv_t ldvp; 3109 nxge_grp_set_t *set; 3110 3111 nxge_status_t status = NXGE_OK; 3112 3113 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init")); 3114 if (!*navail_p) { 3115 *nrequired_p = 0; 3116 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3117 "<== nxge_ldgv_init:no avail")); 3118 return (NXGE_ERROR); 3119 } 3120 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 3121 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 3122 3123 nldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs; 3124 3125 /* 3126 * If function zero instance, it needs to handle the system error 3127 * interrupts. 3128 */ 3129 func = nxgep->function_num; 3130 if (func == 0) { 3131 nldvs++; 3132 own_sys_err = B_TRUE; 3133 } else { 3134 /* use timer */ 3135 nldvs++; 3136 } 3137 3138 /* 3139 * Assume single partition, each function owns mac. 3140 */ 3141 if (!nxge_use_partition) { 3142 /* mac */ 3143 nldvs++; 3144 /* MIF */ 3145 nldvs++; 3146 own_fzc = B_TRUE; 3147 } 3148 maxldvs = nldvs; 3149 maxldgs = p_cfgp->max_ldgs; 3150 if (!maxldvs || !maxldgs) { 3151 /* No devices configured. */ 3152 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: " 3153 "no logical devices or groups configured.")); 3154 return (NXGE_ERROR); 3155 } 3156 ldgvp = nxgep->ldgvp; 3157 if (ldgvp == NULL) { 3158 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 3159 nxgep->ldgvp = ldgvp; 3160 ldgvp->maxldgs = (uint8_t)maxldgs; 3161 ldgvp->maxldvs = (uint8_t)maxldvs; 3162 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs, 3163 KM_SLEEP); 3164 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs, 3165 KM_SLEEP); 3166 } 3167 ldgvp->ndma_ldvs = p_cfgp->tdc.owned + p_cfgp->max_rdcs; 3168 ldgvp->tmres = NXGE_TIMER_RESO; 3169 3170 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3171 "==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d", 3172 maxldvs, maxldgs, nldvs)); 3173 ldg = p_cfgp->start_ldg; 3174 ptr = ldgp; 3175 for (i = 0; i < maxldgs; i++) { 3176 ptr->func = func; 3177 ptr->arm = B_TRUE; 3178 ptr->vldg_index = (uint8_t)i; 3179 ptr->ldg_timer = NXGE_TIMER_LDG; 3180 ptr->ldg = ldg++; 3181 ptr->sys_intr_handler = nxge_intr; 3182 ptr->nldvs = 0; 3183 ptr->nxgep = nxgep; 3184 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3185 "==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d", 3186 maxldvs, maxldgs, ptr->ldg)); 3187 ptr++; 3188 } 3189 3190 ldg = p_cfgp->start_ldg; 3191 if (maxldgs > *navail_p) { 3192 ngrps = *navail_p; 3193 } else { 3194 ngrps = maxldgs; 3195 } 3196 endldg = ldg + ngrps; 3197 3198 /* 3199 * Receive DMA channels. 3200 */ 3201 nldvs = 0; 3202 ldgvp->nldvs = 0; 3203 ldgp->ldvp = NULL; 3204 *nrequired_p = 0; 3205 3206 /* 3207 * Start with RDC to configure logical devices for each group. 3208 */ 3209 set = &nxgep->rx_set; 3210 for (channel = 0; channel < NXGE_MAX_RDCS; channel++) { 3211 if ((1 << channel) & set->owned.map) { 3212 /* For now, <channel & <vdma_index> are the same. */ 3213 ldvp->is_rxdma = B_TRUE; 3214 ldvp->ldv = (uint8_t)channel + NXGE_RDMA_LD_START; 3215 ldvp->channel = channel; 3216 ldvp->vdma_index = (uint8_t)channel; 3217 ldvp->ldv_intr_handler = nxge_rx_intr; 3218 ldvp->ldv_ldf_masks = 0; 3219 ldvp->use_timer = B_FALSE; 3220 ldvp->nxgep = nxgep; 3221 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv, 3222 endldg, nrequired_p); 3223 nldvs++; 3224 } 3225 } 3226 3227 /* 3228 * Transmit DMA channels. 3229 */ 3230 set = &nxgep->tx_set; 3231 for (channel = 0; channel < NXGE_MAX_TDCS; channel++) { 3232 if ((1 << channel) & set->owned.map) { 3233 /* For now, <channel & <vdma_index> are the same. */ 3234 ldvp->is_txdma = B_TRUE; 3235 ldvp->ldv = (uint8_t)channel + NXGE_TDMA_LD_START; 3236 ldvp->channel = channel; 3237 ldvp->vdma_index = (uint8_t)channel; 3238 ldvp->ldv_intr_handler = nxge_tx_intr; 3239 ldvp->ldv_ldf_masks = 0; 3240 ldvp->use_timer = B_FALSE; 3241 ldvp->nxgep = nxgep; 3242 nxge_ldgv_setup(&ldgp, &ldvp, ldvp->ldv, 3243 endldg, nrequired_p); 3244 nldvs++; 3245 } 3246 } 3247 3248 if (own_fzc) { 3249 ldv = NXGE_MIF_LD; 3250 ldvp->ldv = (uint8_t)ldv; 3251 ldvp->is_mif = B_TRUE; 3252 ldvp->ldv_intr_handler = nxge_mif_intr; 3253 ldvp->ldv_ldf_masks = 0; 3254 ldvp->use_timer = B_FALSE; 3255 ldvp->nxgep = nxgep; 3256 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3257 nldvs++; 3258 } 3259 /* 3260 * MAC port (function zero control) 3261 */ 3262 if (own_fzc) { 3263 ldvp->is_mac = B_TRUE; 3264 ldvp->ldv_intr_handler = nxge_mac_intr; 3265 ldvp->ldv_ldf_masks = 0; 3266 ldv = func + NXGE_MAC_LD_START; 3267 ldvp->ldv = (uint8_t)ldv; 3268 ldvp->use_timer = B_FALSE; 3269 ldvp->nxgep = nxgep; 3270 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3271 nldvs++; 3272 } 3273 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3274 "func %d nldvs %d navail %d nrequired %d", 3275 func, nldvs, *navail_p, *nrequired_p)); 3276 /* 3277 * Function 0 owns system error interrupts. 3278 */ 3279 ldvp->use_timer = B_TRUE; 3280 if (own_sys_err) { 3281 ldv = NXGE_SYS_ERROR_LD; 3282 ldvp->ldv = (uint8_t)ldv; 3283 ldvp->is_syserr = B_TRUE; 3284 ldvp->ldv_intr_handler = nxge_syserr_intr; 3285 ldvp->ldv_ldf_masks = 0; 3286 ldvp->nxgep = nxgep; 3287 ldgvp->ldvp_syserr = ldvp; 3288 /* 3289 * Unmask the system interrupt states. 3290 */ 3291 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 3292 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 3293 SYS_ERR_ZCP_MASK); 3294 3295 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3296 nldvs++; 3297 } else { 3298 ldv = NXGE_SYS_ERROR_LD; 3299 ldvp->ldv = (uint8_t)ldv; 3300 ldvp->is_syserr = B_TRUE; 3301 ldvp->ldv_intr_handler = nxge_syserr_intr; 3302 ldvp->nxgep = nxgep; 3303 ldvp->ldv_ldf_masks = 0; 3304 ldgvp->ldvp_syserr = ldvp; 3305 } 3306 3307 ldgvp->ldg_intrs = *nrequired_p; 3308 3309 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3310 "func %d nldvs %d navail %d nrequired %d", 3311 func, nldvs, *navail_p, *nrequired_p)); 3312 3313 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init")); 3314 return (status); 3315 } 3316 3317 nxge_status_t 3318 nxge_ldgv_uninit(p_nxge_t nxgep) 3319 { 3320 p_nxge_ldgv_t ldgvp; 3321 3322 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit")); 3323 ldgvp = nxgep->ldgvp; 3324 if (ldgvp == NULL) { 3325 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: " 3326 "no logical group configured.")); 3327 return (NXGE_OK); 3328 } 3329 if (ldgvp->ldvp_syserr_allocated == B_TRUE) { 3330 KMEM_FREE(ldgvp->ldvp_syserr, sizeof (nxge_ldv_t)); 3331 } 3332 if (ldgvp->ldgp) { 3333 KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs); 3334 } 3335 if (ldgvp->ldvp) { 3336 KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs); 3337 } 3338 KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t)); 3339 nxgep->ldgvp = NULL; 3340 3341 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit")); 3342 return (NXGE_OK); 3343 } 3344 3345 nxge_status_t 3346 nxge_intr_ldgv_init(p_nxge_t nxgep) 3347 { 3348 nxge_status_t status = NXGE_OK; 3349 3350 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init")); 3351 /* 3352 * Configure the logical device group numbers, state vectors and 3353 * interrupt masks for each logical device. 3354 */ 3355 status = nxge_fzc_intr_init(nxgep); 3356 3357 /* 3358 * Configure logical device masks and timers. 3359 */ 3360 status = nxge_intr_mask_mgmt(nxgep); 3361 3362 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init")); 3363 return (status); 3364 } 3365 3366 nxge_status_t 3367 nxge_intr_mask_mgmt(p_nxge_t nxgep) 3368 { 3369 p_nxge_ldgv_t ldgvp; 3370 p_nxge_ldg_t ldgp; 3371 p_nxge_ldv_t ldvp; 3372 npi_handle_t handle; 3373 int i, j; 3374 npi_status_t rs = NPI_SUCCESS; 3375 3376 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt")); 3377 3378 if ((ldgvp = nxgep->ldgvp) == NULL) { 3379 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3380 "<== nxge_intr_mask_mgmt: Null ldgvp")); 3381 return (NXGE_ERROR); 3382 } 3383 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3384 ldgp = ldgvp->ldgp; 3385 ldvp = ldgvp->ldvp; 3386 if (ldgp == NULL || ldvp == NULL) { 3387 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3388 "<== nxge_intr_mask_mgmt: Null ldgp or ldvp")); 3389 return (NXGE_ERROR); 3390 } 3391 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3392 "==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs)); 3393 /* Initialize masks. */ 3394 if (nxgep->niu_type != N2_NIU) { 3395 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3396 "==> nxge_intr_mask_mgmt(Neptune): # intrs %d ", 3397 ldgvp->ldg_intrs)); 3398 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3399 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3400 "==> nxge_intr_mask_mgmt(Neptune): # ldv %d " 3401 "in group %d", ldgp->nldvs, ldgp->ldg)); 3402 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3403 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3404 "==> nxge_intr_mask_mgmt: set ldv # %d " 3405 "for ldg %d", ldvp->ldv, ldgp->ldg)); 3406 rs = npi_intr_mask_set(handle, ldvp->ldv, 3407 ldvp->ldv_ldf_masks); 3408 if (rs != NPI_SUCCESS) { 3409 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3410 "<== nxge_intr_mask_mgmt: " 3411 "set mask failed " 3412 " rs 0x%x ldv %d mask 0x%x", 3413 rs, ldvp->ldv, 3414 ldvp->ldv_ldf_masks)); 3415 return (NXGE_ERROR | rs); 3416 } 3417 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3418 "==> nxge_intr_mask_mgmt: " 3419 "set mask OK " 3420 " rs 0x%x ldv %d mask 0x%x", 3421 rs, ldvp->ldv, 3422 ldvp->ldv_ldf_masks)); 3423 } 3424 } 3425 } 3426 ldgp = ldgvp->ldgp; 3427 /* Configure timer and arm bit */ 3428 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3429 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3430 ldgp->arm, ldgp->ldg_timer); 3431 if (rs != NPI_SUCCESS) { 3432 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3433 "<== nxge_intr_mask_mgmt: " 3434 "set timer failed " 3435 " rs 0x%x dg %d timer 0x%x", 3436 rs, ldgp->ldg, ldgp->ldg_timer)); 3437 return (NXGE_ERROR | rs); 3438 } 3439 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3440 "==> nxge_intr_mask_mgmt: " 3441 "set timer OK " 3442 " rs 0x%x ldg %d timer 0x%x", 3443 rs, ldgp->ldg, ldgp->ldg_timer)); 3444 } 3445 3446 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt")); 3447 return (NXGE_OK); 3448 } 3449 3450 nxge_status_t 3451 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on) 3452 { 3453 p_nxge_ldgv_t ldgvp; 3454 p_nxge_ldg_t ldgp; 3455 p_nxge_ldv_t ldvp; 3456 npi_handle_t handle; 3457 int i, j; 3458 npi_status_t rs = NPI_SUCCESS; 3459 3460 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3461 "==> nxge_intr_mask_mgmt_set (%d)", on)); 3462 3463 if (nxgep->niu_type == N2_NIU) { 3464 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3465 "<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)", 3466 on)); 3467 return (NXGE_ERROR); 3468 } 3469 3470 if ((ldgvp = nxgep->ldgvp) == NULL) { 3471 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3472 "==> nxge_intr_mask_mgmt_set: Null ldgvp")); 3473 return (NXGE_ERROR); 3474 } 3475 3476 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3477 ldgp = ldgvp->ldgp; 3478 ldvp = ldgvp->ldvp; 3479 if (ldgp == NULL || ldvp == NULL) { 3480 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3481 "<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp")); 3482 return (NXGE_ERROR); 3483 } 3484 /* set masks. */ 3485 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3486 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3487 "==> nxge_intr_mask_mgmt_set: flag %d ldg %d" 3488 "set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs)); 3489 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3490 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3491 "==> nxge_intr_mask_mgmt_set: " 3492 "for %d %d flag %d", i, j, on)); 3493 if (on) { 3494 ldvp->ldv_ldf_masks = 0; 3495 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3496 "==> nxge_intr_mask_mgmt_set: " 3497 "ON mask off")); 3498 } else if (!on) { 3499 ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK; 3500 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3501 "==> nxge_intr_mask_mgmt_set:mask on")); 3502 } 3503 rs = npi_intr_mask_set(handle, ldvp->ldv, 3504 ldvp->ldv_ldf_masks); 3505 if (rs != NPI_SUCCESS) { 3506 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3507 "==> nxge_intr_mask_mgmt_set: " 3508 "set mask failed " 3509 " rs 0x%x ldv %d mask 0x%x", 3510 rs, ldvp->ldv, ldvp->ldv_ldf_masks)); 3511 return (NXGE_ERROR | rs); 3512 } 3513 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3514 "==> nxge_intr_mask_mgmt_set: flag %d" 3515 "set mask OK " 3516 " ldv %d mask 0x%x", 3517 on, ldvp->ldv, ldvp->ldv_ldf_masks)); 3518 } 3519 } 3520 3521 ldgp = ldgvp->ldgp; 3522 /* set the arm bit */ 3523 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3524 if (on && !ldgp->arm) { 3525 ldgp->arm = B_TRUE; 3526 } else if (!on && ldgp->arm) { 3527 ldgp->arm = B_FALSE; 3528 } 3529 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3530 ldgp->arm, ldgp->ldg_timer); 3531 if (rs != NPI_SUCCESS) { 3532 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3533 "<== nxge_intr_mask_mgmt_set: " 3534 "set timer failed " 3535 " rs 0x%x ldg %d timer 0x%x", 3536 rs, ldgp->ldg, ldgp->ldg_timer)); 3537 return (NXGE_ERROR | rs); 3538 } 3539 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3540 "==> nxge_intr_mask_mgmt_set: OK (flag %d) " 3541 "set timer " 3542 " ldg %d timer 0x%x", 3543 on, ldgp->ldg, ldgp->ldg_timer)); 3544 } 3545 3546 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set")); 3547 return (NXGE_OK); 3548 } 3549 3550 static nxge_status_t 3551 nxge_get_mac_addr_properties(p_nxge_t nxgep) 3552 { 3553 #if defined(_BIG_ENDIAN) 3554 uchar_t *prop_val; 3555 uint_t prop_len; 3556 uint_t j; 3557 #endif 3558 uint_t i; 3559 uint8_t func_num; 3560 boolean_t compute_macs = B_TRUE; 3561 3562 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties ")); 3563 3564 #if defined(_BIG_ENDIAN) 3565 /* 3566 * Get the ethernet address. 3567 */ 3568 (void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr); 3569 3570 /* 3571 * Check if it is an adapter with its own local mac address If it is 3572 * present, override the system mac address. 3573 */ 3574 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3575 "local-mac-address", &prop_val, 3576 &prop_len) == DDI_PROP_SUCCESS) { 3577 if (prop_len == ETHERADDRL) { 3578 nxgep->factaddr = *(p_ether_addr_t)prop_val; 3579 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = " 3580 "%02x:%02x:%02x:%02x:%02x:%02x", 3581 prop_val[0], prop_val[1], prop_val[2], 3582 prop_val[3], prop_val[4], prop_val[5])); 3583 } 3584 ddi_prop_free(prop_val); 3585 } 3586 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3587 "local-mac-address?", &prop_val, 3588 &prop_len) == DDI_PROP_SUCCESS) { 3589 if (strncmp("true", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3590 nxgep->ouraddr = nxgep->factaddr; 3591 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3592 "Using local MAC address")); 3593 } 3594 ddi_prop_free(prop_val); 3595 } else { 3596 nxgep->ouraddr = nxgep->factaddr; 3597 } 3598 3599 if ((!nxgep->vpd_info.present) || 3600 (nxge_is_valid_local_mac(nxgep->factaddr))) 3601 goto got_mac_addr; 3602 3603 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: " 3604 "MAC address from properties is not valid...reading from PROM")); 3605 3606 #endif 3607 if (!nxgep->vpd_info.ver_valid) { 3608 (void) nxge_espc_mac_addrs_get(nxgep); 3609 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3610 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get " 3611 "MAC address")); 3612 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 3613 "[%s] invalid...please update", 3614 nxgep->vpd_info.ver)); 3615 return (NXGE_ERROR); 3616 } 3617 nxgep->ouraddr = nxgep->factaddr; 3618 goto got_mac_addr; 3619 } 3620 /* 3621 * First get the MAC address from the info in the VPD data read 3622 * from the EEPROM. 3623 */ 3624 nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr, 3625 nxgep->function_num, &nxgep->factaddr); 3626 3627 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3628 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3629 "nxge_get_mac_addr_properties: " 3630 "MAC address in EEPROM VPD data not valid" 3631 "...reading from NCR registers")); 3632 (void) nxge_espc_mac_addrs_get(nxgep); 3633 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3634 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Failed to get " 3635 "MAC address")); 3636 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 3637 "[%s] invalid...please update", 3638 nxgep->vpd_info.ver)); 3639 return (NXGE_ERROR); 3640 } 3641 } 3642 3643 nxgep->ouraddr = nxgep->factaddr; 3644 3645 got_mac_addr: 3646 func_num = nxgep->function_num; 3647 3648 /* 3649 * Note: mac-addresses property is the list of mac addresses for a 3650 * port. NXGE_MAX_MMAC_ADDRS is the total number of MAC addresses 3651 * allocated for a board. 3652 */ 3653 nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS; 3654 3655 #if defined(_BIG_ENDIAN) 3656 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3657 "mac-addresses", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3658 /* 3659 * XAUI may have up to 18 MACs, more than the XMAC can 3660 * use (1 unique MAC plus 16 alternate MACs) 3661 */ 3662 nxgep->nxge_mmac_info.num_factory_mmac = 3663 prop_len / ETHERADDRL - 1; 3664 if (nxgep->nxge_mmac_info.num_factory_mmac > 3665 XMAC_MAX_ALT_ADDR_ENTRY) { 3666 nxgep->nxge_mmac_info.num_factory_mmac = 3667 XMAC_MAX_ALT_ADDR_ENTRY; 3668 } 3669 3670 for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) { 3671 for (j = 0; j < ETHERADDRL; j++) { 3672 nxgep->nxge_mmac_info.factory_mac_pool[i][j] = 3673 *(prop_val + (i * ETHERADDRL) + j); 3674 } 3675 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3676 "nxge_get_mac_addr_properties: Alt mac[%d] from " 3677 "mac-addresses property[%2x:%2x:%2x:%2x:%2x:%2x]", 3678 i, nxgep->nxge_mmac_info.factory_mac_pool[i][0], 3679 nxgep->nxge_mmac_info.factory_mac_pool[i][1], 3680 nxgep->nxge_mmac_info.factory_mac_pool[i][2], 3681 nxgep->nxge_mmac_info.factory_mac_pool[i][3], 3682 nxgep->nxge_mmac_info.factory_mac_pool[i][4], 3683 nxgep->nxge_mmac_info.factory_mac_pool[i][5])); 3684 } 3685 3686 compute_macs = B_FALSE; 3687 ddi_prop_free(prop_val); 3688 goto got_mmac_info; 3689 } 3690 #endif 3691 /* 3692 * total_factory_macs = 32 3693 * num_factory_mmac = (32 >> (nports/2)) - 1 3694 * So if nports = 4, then num_factory_mmac = 7 3695 * if nports = 2, then num_factory_mmac = 15 3696 */ 3697 nxgep->nxge_mmac_info.num_factory_mmac = 3698 ((nxgep->nxge_mmac_info.total_factory_macs >> 3699 (nxgep->nports >> 1))) - 1; 3700 3701 got_mmac_info: 3702 3703 if ((nxgep->function_num < 2) && 3704 (nxgep->nxge_mmac_info.num_factory_mmac > 3705 XMAC_MAX_ALT_ADDR_ENTRY)) { 3706 nxgep->nxge_mmac_info.num_factory_mmac = 3707 XMAC_MAX_ALT_ADDR_ENTRY; 3708 } else if ((nxgep->function_num > 1) && 3709 (nxgep->nxge_mmac_info.num_factory_mmac > 3710 BMAC_MAX_ALT_ADDR_ENTRY)) { 3711 nxgep->nxge_mmac_info.num_factory_mmac = 3712 BMAC_MAX_ALT_ADDR_ENTRY; 3713 } 3714 3715 for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) { 3716 (void) npi_mac_altaddr_disable(nxgep->npi_handle, 3717 NXGE_GET_PORT_NUM(func_num), i); 3718 } 3719 3720 (void) nxge_init_mmac(nxgep, compute_macs); 3721 return (NXGE_OK); 3722 } 3723 3724 void 3725 nxge_get_xcvr_properties(p_nxge_t nxgep) 3726 { 3727 uchar_t *prop_val; 3728 uint_t prop_len; 3729 3730 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties")); 3731 3732 /* 3733 * Read the type of physical layer interface being used. 3734 */ 3735 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3736 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3737 "phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3738 if (strncmp("pcs", (caddr_t)prop_val, 3739 (size_t)prop_len) == 0) { 3740 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3741 } else { 3742 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3743 } 3744 ddi_prop_free(prop_val); 3745 } else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3746 "phy-interface", &prop_val, 3747 &prop_len) == DDI_PROP_SUCCESS) { 3748 if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3749 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3750 } else { 3751 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3752 } 3753 ddi_prop_free(prop_val); 3754 } 3755 } 3756 3757 /* 3758 * Static functions start here. 3759 */ 3760 3761 static void 3762 nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv, 3763 uint8_t endldg, int *ngrps) 3764 { 3765 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup")); 3766 /* Assign the group number for each device. */ 3767 (*ldvp)->ldg_assigned = (*ldgp)->ldg; 3768 (*ldvp)->ldgp = *ldgp; 3769 (*ldvp)->ldv = ldv; 3770 3771 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3772 "ldv %d endldg %d ldg %d, ldvp $%p", 3773 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3774 3775 (*ldgp)->nldvs++; 3776 if ((*ldgp)->ldg == (endldg - 1)) { 3777 if ((*ldgp)->ldvp == NULL) { 3778 (*ldgp)->ldvp = *ldvp; 3779 *ngrps += 1; 3780 NXGE_DEBUG_MSG((NULL, INT_CTL, 3781 "==> nxge_ldgv_setup: ngrps %d", *ngrps)); 3782 } 3783 NXGE_DEBUG_MSG((NULL, INT_CTL, 3784 "==> nxge_ldgv_setup: ldvp $%p ngrps %d", 3785 *ldvp, *ngrps)); 3786 ++*ldvp; 3787 } else { 3788 (*ldgp)->ldvp = *ldvp; 3789 *ngrps += 1; 3790 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): " 3791 "ldv %d endldg %d ldg %d, ldvp $%p", 3792 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3793 (*ldvp) = ++*ldvp; 3794 (*ldgp) = ++*ldgp; 3795 NXGE_DEBUG_MSG((NULL, INT_CTL, 3796 "==> nxge_ldgv_setup: new ngrps %d", *ngrps)); 3797 } 3798 3799 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3800 "ldv %d ldvp $%p endldg %d ngrps %d", 3801 ldv, ldvp, endldg, *ngrps)); 3802 3803 NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup")); 3804 } 3805 3806 /* 3807 * Note: This function assumes the following distribution of mac 3808 * addresses among 4 ports in neptune: 3809 * 3810 * ------------- 3811 * 0| |0 - local-mac-address for fn 0 3812 * ------------- 3813 * 1| |1 - local-mac-address for fn 1 3814 * ------------- 3815 * 2| |2 - local-mac-address for fn 2 3816 * ------------- 3817 * 3| |3 - local-mac-address for fn 3 3818 * ------------- 3819 * | |4 - Start of alt. mac addr. for fn 0 3820 * | | 3821 * | | 3822 * | |10 3823 * -------------- 3824 * | |11 - Start of alt. mac addr. for fn 1 3825 * | | 3826 * | | 3827 * | |17 3828 * -------------- 3829 * | |18 - Start of alt. mac addr. for fn 2 3830 * | | 3831 * | | 3832 * | |24 3833 * -------------- 3834 * | |25 - Start of alt. mac addr. for fn 3 3835 * | | 3836 * | | 3837 * | |31 3838 * -------------- 3839 * 3840 * For N2/NIU the mac addresses is from XAUI card. 3841 * 3842 * When 'compute_addrs' is true, the alternate mac addresses are computed 3843 * using the unique mac address as base. Otherwise the alternate addresses 3844 * are assigned from the list read off the 'mac-addresses' property. 3845 */ 3846 3847 static void 3848 nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs) 3849 { 3850 int slot; 3851 uint8_t func_num; 3852 uint16_t *base_mmac_addr; 3853 uint32_t alt_mac_ls4b; 3854 uint16_t *mmac_addr; 3855 uint32_t base_mac_ls4b; /* least significant 4 bytes */ 3856 nxge_mmac_t *mmac_info; 3857 npi_mac_addr_t mac_addr; 3858 3859 func_num = nxgep->function_num; 3860 base_mmac_addr = (uint16_t *)&nxgep->factaddr; 3861 mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info; 3862 3863 if (compute_addrs) { 3864 base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 | 3865 base_mmac_addr[2]; 3866 3867 if (nxgep->niu_type == N2_NIU) { 3868 /* ls4b of 1st altmac */ 3869 alt_mac_ls4b = base_mac_ls4b + 1; 3870 } else { /* Neptune */ 3871 alt_mac_ls4b = base_mac_ls4b + 3872 (nxgep->nports - func_num) + 3873 (func_num * (mmac_info->num_factory_mmac)); 3874 } 3875 } 3876 3877 /* Set flags for unique MAC */ 3878 mmac_info->mac_pool[0].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 3879 3880 /* Clear flags of all alternate MAC slots */ 3881 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 3882 if (slot <= mmac_info->num_factory_mmac) 3883 mmac_info->mac_pool[slot].flags = MMAC_VENDOR_ADDR; 3884 else 3885 mmac_info->mac_pool[slot].flags = 0; 3886 } 3887 3888 /* Generate and store factory alternate MACs */ 3889 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 3890 mmac_addr = (uint16_t *)&mmac_info->factory_mac_pool[slot]; 3891 if (compute_addrs) { 3892 mmac_addr[0] = base_mmac_addr[0]; 3893 mac_addr.w2 = mmac_addr[0]; 3894 3895 mmac_addr[1] = (alt_mac_ls4b >> 16) & 0x0FFFF; 3896 mac_addr.w1 = mmac_addr[1]; 3897 3898 mmac_addr[2] = alt_mac_ls4b & 0x0FFFF; 3899 mac_addr.w0 = mmac_addr[2]; 3900 3901 alt_mac_ls4b++; 3902 } else { 3903 mac_addr.w2 = mmac_addr[0]; 3904 mac_addr.w1 = mmac_addr[1]; 3905 mac_addr.w0 = mmac_addr[2]; 3906 } 3907 3908 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3909 "mac_pool_addr[%2x:%2x:%2x:%2x:%2x:%2x] npi_addr[%x%x%x]", 3910 mmac_info->factory_mac_pool[slot][0], 3911 mmac_info->factory_mac_pool[slot][1], 3912 mmac_info->factory_mac_pool[slot][2], 3913 mmac_info->factory_mac_pool[slot][3], 3914 mmac_info->factory_mac_pool[slot][4], 3915 mmac_info->factory_mac_pool[slot][5], 3916 mac_addr.w0, mac_addr.w1, mac_addr.w2)); 3917 /* 3918 * slot minus 1 because npi_mac_altaddr_entry expects 0 3919 * for the first alternate mac address. 3920 */ 3921 (void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 3922 NXGE_GET_PORT_NUM(func_num), slot - 1, &mac_addr); 3923 } 3924 /* Initialize the first two parameters for mmac kstat */ 3925 nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac; 3926 nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac; 3927 } 3928