1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_rxdma.h> 30 31 #define NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp) \ 32 (rdcgrp + nxgep->pt_config.hw_config.start_rdc_grpid) 33 #define NXGE_ACTUAL_RDC(nxgep, rdc) \ 34 (rdc + nxgep->pt_config.hw_config.start_rdc) 35 36 /* 37 * Globals: tunable parameters (/etc/system or adb) 38 * 39 */ 40 extern uint32_t nxge_rbr_size; 41 extern uint32_t nxge_rcr_size; 42 extern uint32_t nxge_rbr_spare_size; 43 44 extern uint32_t nxge_mblks_pending; 45 46 /* 47 * Tunable to reduce the amount of time spent in the 48 * ISR doing Rx Processing. 49 */ 50 extern uint32_t nxge_max_rx_pkts; 51 boolean_t nxge_jumbo_enable; 52 53 /* 54 * Tunables to manage the receive buffer blocks. 55 * 56 * nxge_rx_threshold_hi: copy all buffers. 57 * nxge_rx_bcopy_size_type: receive buffer block size type. 58 * nxge_rx_threshold_lo: copy only up to tunable block size type. 59 */ 60 extern nxge_rxbuf_threshold_t nxge_rx_threshold_hi; 61 extern nxge_rxbuf_type_t nxge_rx_buf_size_type; 62 extern nxge_rxbuf_threshold_t nxge_rx_threshold_lo; 63 64 static nxge_status_t nxge_map_rxdma(p_nxge_t); 65 static void nxge_unmap_rxdma(p_nxge_t); 66 67 static nxge_status_t nxge_rxdma_hw_start_common(p_nxge_t); 68 static void nxge_rxdma_hw_stop_common(p_nxge_t); 69 70 static nxge_status_t nxge_rxdma_hw_start(p_nxge_t); 71 static void nxge_rxdma_hw_stop(p_nxge_t); 72 73 static nxge_status_t nxge_map_rxdma_channel(p_nxge_t, uint16_t, 74 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 75 uint32_t, 76 p_nxge_dma_common_t *, p_rx_rcr_ring_t *, 77 p_rx_mbox_t *); 78 static void nxge_unmap_rxdma_channel(p_nxge_t, uint16_t, 79 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 80 81 static nxge_status_t nxge_map_rxdma_channel_cfg_ring(p_nxge_t, 82 uint16_t, 83 p_nxge_dma_common_t *, p_rx_rbr_ring_t *, 84 p_rx_rcr_ring_t *, p_rx_mbox_t *); 85 static void nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t, 86 p_rx_rcr_ring_t, p_rx_mbox_t); 87 88 static nxge_status_t nxge_map_rxdma_channel_buf_ring(p_nxge_t, 89 uint16_t, 90 p_nxge_dma_common_t *, 91 p_rx_rbr_ring_t *, uint32_t); 92 static void nxge_unmap_rxdma_channel_buf_ring(p_nxge_t, 93 p_rx_rbr_ring_t); 94 95 static nxge_status_t nxge_rxdma_start_channel(p_nxge_t, uint16_t, 96 p_rx_rbr_ring_t, p_rx_rcr_ring_t, p_rx_mbox_t); 97 static nxge_status_t nxge_rxdma_stop_channel(p_nxge_t, uint16_t); 98 99 mblk_t * 100 nxge_rx_pkts(p_nxge_t, uint_t, p_nxge_ldv_t, 101 p_rx_rcr_ring_t *, rx_dma_ctl_stat_t); 102 103 static void nxge_receive_packet(p_nxge_t, 104 p_rx_rcr_ring_t, 105 p_rcr_entry_t, 106 boolean_t *, 107 mblk_t **, mblk_t **); 108 109 nxge_status_t nxge_disable_rxdma_channel(p_nxge_t, uint16_t); 110 111 static p_rx_msg_t nxge_allocb(size_t, uint32_t, p_nxge_dma_common_t); 112 static void nxge_freeb(p_rx_msg_t); 113 static void nxge_rx_pkts_vring(p_nxge_t, uint_t, 114 p_nxge_ldv_t, rx_dma_ctl_stat_t); 115 static nxge_status_t nxge_rx_err_evnts(p_nxge_t, uint_t, 116 p_nxge_ldv_t, rx_dma_ctl_stat_t); 117 118 static nxge_status_t nxge_rxdma_handle_port_errors(p_nxge_t, 119 uint32_t, uint32_t); 120 121 static nxge_status_t nxge_rxbuf_index_info_init(p_nxge_t, 122 p_rx_rbr_ring_t); 123 124 125 static nxge_status_t 126 nxge_rxdma_fatal_err_recover(p_nxge_t, uint16_t); 127 128 nxge_status_t 129 nxge_rx_port_fatal_err_recover(p_nxge_t); 130 131 static uint16_t 132 nxge_get_pktbuf_size(p_nxge_t nxgep, int bufsz_type, rbr_cfig_b_t rbr_cfgb); 133 134 nxge_status_t 135 nxge_init_rxdma_channels(p_nxge_t nxgep) 136 { 137 nxge_status_t status = NXGE_OK; 138 139 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_init_rxdma_channels")); 140 141 status = nxge_map_rxdma(nxgep); 142 if (status != NXGE_OK) { 143 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 144 "<== nxge_init_rxdma: status 0x%x", status)); 145 return (status); 146 } 147 148 status = nxge_rxdma_hw_start_common(nxgep); 149 if (status != NXGE_OK) { 150 nxge_unmap_rxdma(nxgep); 151 } 152 153 status = nxge_rxdma_hw_start(nxgep); 154 if (status != NXGE_OK) { 155 nxge_unmap_rxdma(nxgep); 156 } 157 158 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 159 "<== nxge_init_rxdma_channels: status 0x%x", status)); 160 161 return (status); 162 } 163 164 void 165 nxge_uninit_rxdma_channels(p_nxge_t nxgep) 166 { 167 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_uninit_rxdma_channels")); 168 169 nxge_rxdma_hw_stop(nxgep); 170 nxge_rxdma_hw_stop_common(nxgep); 171 nxge_unmap_rxdma(nxgep); 172 173 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 174 "<== nxge_uinit_rxdma_channels")); 175 } 176 177 nxge_status_t 178 nxge_reset_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 179 { 180 npi_handle_t handle; 181 npi_status_t rs = NPI_SUCCESS; 182 nxge_status_t status = NXGE_OK; 183 184 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_reset_rxdma_channel")); 185 186 handle = NXGE_DEV_NPI_HANDLE(nxgep); 187 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 188 189 if (rs != NPI_SUCCESS) { 190 status = NXGE_ERROR | rs; 191 } 192 193 return (status); 194 } 195 196 void 197 nxge_rxdma_regs_dump_channels(p_nxge_t nxgep) 198 { 199 int i, ndmas; 200 uint16_t channel; 201 p_rx_rbr_rings_t rx_rbr_rings; 202 p_rx_rbr_ring_t *rbr_rings; 203 npi_handle_t handle; 204 205 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_regs_dump_channels")); 206 207 handle = NXGE_DEV_NPI_HANDLE(nxgep); 208 (void) npi_rxdma_dump_fzc_regs(handle); 209 210 rx_rbr_rings = nxgep->rx_rbr_rings; 211 if (rx_rbr_rings == NULL) { 212 NXGE_DEBUG_MSG((nxgep, RX_CTL, 213 "<== nxge_rxdma_regs_dump_channels: " 214 "NULL ring pointer")); 215 return; 216 } 217 if (rx_rbr_rings->rbr_rings == NULL) { 218 NXGE_DEBUG_MSG((nxgep, RX_CTL, 219 "<== nxge_rxdma_regs_dump_channels: " 220 " NULL rbr rings pointer")); 221 return; 222 } 223 224 ndmas = rx_rbr_rings->ndmas; 225 if (!ndmas) { 226 NXGE_DEBUG_MSG((nxgep, RX_CTL, 227 "<== nxge_rxdma_regs_dump_channels: no channel")); 228 return; 229 } 230 231 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 232 "==> nxge_rxdma_regs_dump_channels (ndmas %d)", ndmas)); 233 234 rbr_rings = rx_rbr_rings->rbr_rings; 235 for (i = 0; i < ndmas; i++) { 236 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 237 continue; 238 } 239 channel = rbr_rings[i]->rdc; 240 (void) nxge_dump_rxdma_channel(nxgep, channel); 241 } 242 243 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_regs_dump")); 244 245 } 246 247 nxge_status_t 248 nxge_dump_rxdma_channel(p_nxge_t nxgep, uint8_t channel) 249 { 250 npi_handle_t handle; 251 npi_status_t rs = NPI_SUCCESS; 252 nxge_status_t status = NXGE_OK; 253 254 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_dump_rxdma_channel")); 255 256 handle = NXGE_DEV_NPI_HANDLE(nxgep); 257 rs = npi_rxdma_dump_rdc_regs(handle, channel); 258 259 if (rs != NPI_SUCCESS) { 260 status = NXGE_ERROR | rs; 261 } 262 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dump_rxdma_channel")); 263 return (status); 264 } 265 266 nxge_status_t 267 nxge_init_rxdma_channel_event_mask(p_nxge_t nxgep, uint16_t channel, 268 p_rx_dma_ent_msk_t mask_p) 269 { 270 npi_handle_t handle; 271 npi_status_t rs = NPI_SUCCESS; 272 nxge_status_t status = NXGE_OK; 273 274 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 275 "<== nxge_init_rxdma_channel_event_mask")); 276 277 handle = NXGE_DEV_NPI_HANDLE(nxgep); 278 rs = npi_rxdma_event_mask(handle, OP_SET, channel, mask_p); 279 if (rs != NPI_SUCCESS) { 280 status = NXGE_ERROR | rs; 281 } 282 283 return (status); 284 } 285 286 nxge_status_t 287 nxge_init_rxdma_channel_cntl_stat(p_nxge_t nxgep, uint16_t channel, 288 p_rx_dma_ctl_stat_t cs_p) 289 { 290 npi_handle_t handle; 291 npi_status_t rs = NPI_SUCCESS; 292 nxge_status_t status = NXGE_OK; 293 294 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 295 "<== nxge_init_rxdma_channel_cntl_stat")); 296 297 handle = NXGE_DEV_NPI_HANDLE(nxgep); 298 rs = npi_rxdma_control_status(handle, OP_SET, channel, cs_p); 299 300 if (rs != NPI_SUCCESS) { 301 status = NXGE_ERROR | rs; 302 } 303 304 return (status); 305 } 306 307 nxge_status_t 308 nxge_rxdma_cfg_rdcgrp_default_rdc(p_nxge_t nxgep, uint8_t rdcgrp, 309 uint8_t rdc) 310 { 311 npi_handle_t handle; 312 npi_status_t rs = NPI_SUCCESS; 313 p_nxge_dma_pt_cfg_t p_dma_cfgp; 314 p_nxge_rdc_grp_t rdc_grp_p; 315 uint8_t actual_rdcgrp, actual_rdc; 316 317 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 318 " ==> nxge_rxdma_cfg_rdcgrp_default_rdc")); 319 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 320 321 handle = NXGE_DEV_NPI_HANDLE(nxgep); 322 323 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdcgrp]; 324 rdc_grp_p->rdc[0] = rdc; 325 326 actual_rdcgrp = NXGE_ACTUAL_RDCGRP(nxgep, rdcgrp); 327 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 328 329 rs = npi_rxdma_cfg_rdc_table_default_rdc(handle, actual_rdcgrp, 330 actual_rdc); 331 332 if (rs != NPI_SUCCESS) { 333 return (NXGE_ERROR | rs); 334 } 335 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 336 " <== nxge_rxdma_cfg_rdcgrp_default_rdc")); 337 return (NXGE_OK); 338 } 339 340 nxge_status_t 341 nxge_rxdma_cfg_port_default_rdc(p_nxge_t nxgep, uint8_t port, uint8_t rdc) 342 { 343 npi_handle_t handle; 344 345 uint8_t actual_rdc; 346 npi_status_t rs = NPI_SUCCESS; 347 348 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 349 " ==> nxge_rxdma_cfg_port_default_rdc")); 350 351 handle = NXGE_DEV_NPI_HANDLE(nxgep); 352 actual_rdc = NXGE_ACTUAL_RDC(nxgep, rdc); 353 rs = npi_rxdma_cfg_default_port_rdc(handle, port, actual_rdc); 354 355 356 if (rs != NPI_SUCCESS) { 357 return (NXGE_ERROR | rs); 358 } 359 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 360 " <== nxge_rxdma_cfg_port_default_rdc")); 361 362 return (NXGE_OK); 363 } 364 365 nxge_status_t 366 nxge_rxdma_cfg_rcr_threshold(p_nxge_t nxgep, uint8_t channel, 367 uint16_t pkts) 368 { 369 npi_status_t rs = NPI_SUCCESS; 370 npi_handle_t handle; 371 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 372 " ==> nxge_rxdma_cfg_rcr_threshold")); 373 handle = NXGE_DEV_NPI_HANDLE(nxgep); 374 375 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, pkts); 376 377 if (rs != NPI_SUCCESS) { 378 return (NXGE_ERROR | rs); 379 } 380 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_threshold")); 381 return (NXGE_OK); 382 } 383 384 nxge_status_t 385 nxge_rxdma_cfg_rcr_timeout(p_nxge_t nxgep, uint8_t channel, 386 uint16_t tout, uint8_t enable) 387 { 388 npi_status_t rs = NPI_SUCCESS; 389 npi_handle_t handle; 390 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " ==> nxge_rxdma_cfg_rcr_timeout")); 391 handle = NXGE_DEV_NPI_HANDLE(nxgep); 392 if (enable == 0) { 393 rs = npi_rxdma_cfg_rdc_rcr_timeout_disable(handle, channel); 394 } else { 395 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 396 tout); 397 } 398 399 if (rs != NPI_SUCCESS) { 400 return (NXGE_ERROR | rs); 401 } 402 NXGE_DEBUG_MSG((nxgep, RX2_CTL, " <== nxge_rxdma_cfg_rcr_timeout")); 403 return (NXGE_OK); 404 } 405 406 nxge_status_t 407 nxge_enable_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 408 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 409 { 410 npi_handle_t handle; 411 rdc_desc_cfg_t rdc_desc; 412 p_rcrcfig_b_t cfgb_p; 413 npi_status_t rs = NPI_SUCCESS; 414 415 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel")); 416 handle = NXGE_DEV_NPI_HANDLE(nxgep); 417 /* 418 * Use configuration data composed at init time. 419 * Write to hardware the receive ring configurations. 420 */ 421 rdc_desc.mbox_enable = 1; 422 rdc_desc.mbox_addr = mbox_p->mbox_addr; 423 NXGE_DEBUG_MSG((nxgep, RX_CTL, 424 "==> nxge_enable_rxdma_channel: mboxp $%p($%p)", 425 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 426 427 rdc_desc.rbr_len = rbr_p->rbb_max; 428 rdc_desc.rbr_addr = rbr_p->rbr_addr; 429 430 switch (nxgep->rx_bksize_code) { 431 case RBR_BKSIZE_4K: 432 rdc_desc.page_size = SIZE_4KB; 433 break; 434 case RBR_BKSIZE_8K: 435 rdc_desc.page_size = SIZE_8KB; 436 break; 437 case RBR_BKSIZE_16K: 438 rdc_desc.page_size = SIZE_16KB; 439 break; 440 case RBR_BKSIZE_32K: 441 rdc_desc.page_size = SIZE_32KB; 442 break; 443 } 444 445 rdc_desc.size0 = rbr_p->npi_pkt_buf_size0; 446 rdc_desc.valid0 = 1; 447 448 rdc_desc.size1 = rbr_p->npi_pkt_buf_size1; 449 rdc_desc.valid1 = 1; 450 451 rdc_desc.size2 = rbr_p->npi_pkt_buf_size2; 452 rdc_desc.valid2 = 1; 453 454 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 455 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 456 457 rdc_desc.rcr_len = rcr_p->comp_size; 458 rdc_desc.rcr_addr = rcr_p->rcr_addr; 459 460 cfgb_p = &(rcr_p->rcr_cfgb); 461 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; 462 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; 463 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; 464 465 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 466 "rbr_len qlen %d pagesize code %d rcr_len %d", 467 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 468 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_enable_rxdma_channel: " 469 "size 0 %d size 1 %d size 2 %d", 470 rbr_p->npi_pkt_buf_size0, rbr_p->npi_pkt_buf_size1, 471 rbr_p->npi_pkt_buf_size2)); 472 473 rs = npi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 474 if (rs != NPI_SUCCESS) { 475 return (NXGE_ERROR | rs); 476 } 477 478 /* 479 * Enable the timeout and threshold. 480 */ 481 rs = npi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 482 rdc_desc.rcr_threshold); 483 if (rs != NPI_SUCCESS) { 484 return (NXGE_ERROR | rs); 485 } 486 487 rs = npi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 488 rdc_desc.rcr_timeout); 489 if (rs != NPI_SUCCESS) { 490 return (NXGE_ERROR | rs); 491 } 492 493 /* Enable the DMA */ 494 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 495 if (rs != NPI_SUCCESS) { 496 return (NXGE_ERROR | rs); 497 } 498 499 /* Kick the DMA engine. */ 500 npi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 501 /* Clear the rbr empty bit */ 502 (void) npi_rxdma_channel_rbr_empty_clear(handle, channel); 503 504 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_enable_rxdma_channel")); 505 506 return (NXGE_OK); 507 } 508 509 nxge_status_t 510 nxge_disable_rxdma_channel(p_nxge_t nxgep, uint16_t channel) 511 { 512 npi_handle_t handle; 513 npi_status_t rs = NPI_SUCCESS; 514 515 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_disable_rxdma_channel")); 516 handle = NXGE_DEV_NPI_HANDLE(nxgep); 517 518 /* disable the DMA */ 519 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 520 if (rs != NPI_SUCCESS) { 521 NXGE_DEBUG_MSG((nxgep, RX_CTL, 522 "<== nxge_disable_rxdma_channel:failed (0x%x)", 523 rs)); 524 return (NXGE_ERROR | rs); 525 } 526 527 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_disable_rxdma_channel")); 528 return (NXGE_OK); 529 } 530 531 nxge_status_t 532 nxge_rxdma_channel_rcrflush(p_nxge_t nxgep, uint8_t channel) 533 { 534 npi_handle_t handle; 535 nxge_status_t status = NXGE_OK; 536 537 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 538 "<== nxge_init_rxdma_channel_rcrflush")); 539 540 handle = NXGE_DEV_NPI_HANDLE(nxgep); 541 npi_rxdma_rdc_rcr_flush(handle, channel); 542 543 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 544 "<== nxge_init_rxdma_channel_rcrflsh")); 545 return (status); 546 547 } 548 549 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 550 551 #define TO_LEFT -1 552 #define TO_RIGHT 1 553 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 554 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 555 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 556 #define NO_HINT 0xffffffff 557 558 /*ARGSUSED*/ 559 nxge_status_t 560 nxge_rxbuf_pp_to_vp(p_nxge_t nxgep, p_rx_rbr_ring_t rbr_p, 561 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 562 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 563 { 564 int bufsize; 565 uint64_t pktbuf_pp; 566 uint64_t dvma_addr; 567 rxring_info_t *ring_info; 568 int base_side, end_side; 569 int r_index, l_index, anchor_index; 570 int found, search_done; 571 uint32_t offset, chunk_size, block_size, page_size_mask; 572 uint32_t chunk_index, block_index, total_index; 573 int max_iterations, iteration; 574 rxbuf_index_info_t *bufinfo; 575 576 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_rxbuf_pp_to_vp")); 577 578 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 579 "==> nxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 580 pkt_buf_addr_pp, 581 pktbufsz_type)); 582 583 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 584 585 switch (pktbufsz_type) { 586 case 0: 587 bufsize = rbr_p->pkt_buf_size0; 588 break; 589 case 1: 590 bufsize = rbr_p->pkt_buf_size1; 591 break; 592 case 2: 593 bufsize = rbr_p->pkt_buf_size2; 594 break; 595 case RCR_SINGLE_BLOCK: 596 bufsize = 0; 597 anchor_index = 0; 598 break; 599 default: 600 return (NXGE_ERROR); 601 } 602 603 if (rbr_p->num_blocks == 1) { 604 anchor_index = 0; 605 ring_info = rbr_p->ring_info; 606 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 607 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 608 "==> nxge_rxbuf_pp_to_vp: (found, 1 block) " 609 "buf_pp $%p btype %d anchor_index %d " 610 "bufinfo $%p", 611 pkt_buf_addr_pp, 612 pktbufsz_type, 613 anchor_index, 614 bufinfo)); 615 616 goto found_index; 617 } 618 619 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 620 "==> nxge_rxbuf_pp_to_vp: " 621 "buf_pp $%p btype %d anchor_index %d", 622 pkt_buf_addr_pp, 623 pktbufsz_type, 624 anchor_index)); 625 626 ring_info = rbr_p->ring_info; 627 found = B_FALSE; 628 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 629 iteration = 0; 630 max_iterations = ring_info->max_iterations; 631 /* 632 * First check if this block has been seen 633 * recently. This is indicated by a hint which 634 * is initialized when the first buffer of the block 635 * is seen. The hint is reset when the last buffer of 636 * the block has been processed. 637 * As three block sizes are supported, three hints 638 * are kept. The idea behind the hints is that once 639 * the hardware uses a block for a buffer of that 640 * size, it will use it exclusively for that size 641 * and will use it until it is exhausted. It is assumed 642 * that there would a single block being used for the same 643 * buffer sizes at any given time. 644 */ 645 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 646 anchor_index = ring_info->hint[pktbufsz_type]; 647 dvma_addr = bufinfo[anchor_index].dvma_addr; 648 chunk_size = bufinfo[anchor_index].buf_size; 649 if ((pktbuf_pp >= dvma_addr) && 650 (pktbuf_pp < (dvma_addr + chunk_size))) { 651 found = B_TRUE; 652 /* 653 * check if this is the last buffer in the block 654 * If so, then reset the hint for the size; 655 */ 656 657 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 658 ring_info->hint[pktbufsz_type] = NO_HINT; 659 } 660 } 661 662 if (found == B_FALSE) { 663 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 664 "==> nxge_rxbuf_pp_to_vp: (!found)" 665 "buf_pp $%p btype %d anchor_index %d", 666 pkt_buf_addr_pp, 667 pktbufsz_type, 668 anchor_index)); 669 670 /* 671 * This is the first buffer of the block of this 672 * size. Need to search the whole information 673 * array. 674 * the search algorithm uses a binary tree search 675 * algorithm. It assumes that the information is 676 * already sorted with increasing order 677 * info[0] < info[1] < info[2] .... < info[n-1] 678 * where n is the size of the information array 679 */ 680 r_index = rbr_p->num_blocks - 1; 681 l_index = 0; 682 search_done = B_FALSE; 683 anchor_index = MID_INDEX(r_index, l_index); 684 while (search_done == B_FALSE) { 685 if ((r_index == l_index) || 686 (iteration >= max_iterations)) 687 search_done = B_TRUE; 688 end_side = TO_RIGHT; /* to the right */ 689 base_side = TO_LEFT; /* to the left */ 690 /* read the DVMA address information and sort it */ 691 dvma_addr = bufinfo[anchor_index].dvma_addr; 692 chunk_size = bufinfo[anchor_index].buf_size; 693 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 694 "==> nxge_rxbuf_pp_to_vp: (searching)" 695 "buf_pp $%p btype %d " 696 "anchor_index %d chunk_size %d dvmaaddr $%p", 697 pkt_buf_addr_pp, 698 pktbufsz_type, 699 anchor_index, 700 chunk_size, 701 dvma_addr)); 702 703 if (pktbuf_pp >= dvma_addr) 704 base_side = TO_RIGHT; /* to the right */ 705 if (pktbuf_pp < (dvma_addr + chunk_size)) 706 end_side = TO_LEFT; /* to the left */ 707 708 switch (base_side + end_side) { 709 case IN_MIDDLE: 710 /* found */ 711 found = B_TRUE; 712 search_done = B_TRUE; 713 if ((pktbuf_pp + bufsize) < 714 (dvma_addr + chunk_size)) 715 ring_info->hint[pktbufsz_type] = 716 bufinfo[anchor_index].buf_index; 717 break; 718 case BOTH_RIGHT: 719 /* not found: go to the right */ 720 l_index = anchor_index + 1; 721 anchor_index = 722 MID_INDEX(r_index, l_index); 723 break; 724 725 case BOTH_LEFT: 726 /* not found: go to the left */ 727 r_index = anchor_index - 1; 728 anchor_index = MID_INDEX(r_index, 729 l_index); 730 break; 731 default: /* should not come here */ 732 return (NXGE_ERROR); 733 } 734 iteration++; 735 } 736 737 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 738 "==> nxge_rxbuf_pp_to_vp: (search done)" 739 "buf_pp $%p btype %d anchor_index %d", 740 pkt_buf_addr_pp, 741 pktbufsz_type, 742 anchor_index)); 743 } 744 745 if (found == B_FALSE) { 746 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 747 "==> nxge_rxbuf_pp_to_vp: (search failed)" 748 "buf_pp $%p btype %d anchor_index %d", 749 pkt_buf_addr_pp, 750 pktbufsz_type, 751 anchor_index)); 752 return (NXGE_ERROR); 753 } 754 755 found_index: 756 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 757 "==> nxge_rxbuf_pp_to_vp: (FOUND1)" 758 "buf_pp $%p btype %d bufsize %d anchor_index %d", 759 pkt_buf_addr_pp, 760 pktbufsz_type, 761 bufsize, 762 anchor_index)); 763 764 /* index of the first block in this chunk */ 765 chunk_index = bufinfo[anchor_index].start_index; 766 dvma_addr = bufinfo[anchor_index].dvma_addr; 767 page_size_mask = ring_info->block_size_mask; 768 769 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 770 "==> nxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 771 "buf_pp $%p btype %d bufsize %d " 772 "anchor_index %d chunk_index %d dvma $%p", 773 pkt_buf_addr_pp, 774 pktbufsz_type, 775 bufsize, 776 anchor_index, 777 chunk_index, 778 dvma_addr)); 779 780 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 781 block_size = rbr_p->block_size; /* System block(page) size */ 782 783 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 784 "==> nxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 785 "buf_pp $%p btype %d bufsize %d " 786 "anchor_index %d chunk_index %d dvma $%p " 787 "offset %d block_size %d", 788 pkt_buf_addr_pp, 789 pktbufsz_type, 790 bufsize, 791 anchor_index, 792 chunk_index, 793 dvma_addr, 794 offset, 795 block_size)); 796 797 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> getting total index")); 798 799 block_index = (offset / block_size); /* index within chunk */ 800 total_index = chunk_index + block_index; 801 802 803 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 804 "==> nxge_rxbuf_pp_to_vp: " 805 "total_index %d dvma_addr $%p " 806 "offset %d block_size %d " 807 "block_index %d ", 808 total_index, dvma_addr, 809 offset, block_size, 810 block_index)); 811 812 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr 813 + offset); 814 815 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 816 "==> nxge_rxbuf_pp_to_vp: " 817 "total_index %d dvma_addr $%p " 818 "offset %d block_size %d " 819 "block_index %d " 820 "*pkt_buf_addr_p $%p", 821 total_index, dvma_addr, 822 offset, block_size, 823 block_index, 824 *pkt_buf_addr_p)); 825 826 827 *msg_index = total_index; 828 *bufoffset = (offset & page_size_mask); 829 830 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 831 "==> nxge_rxbuf_pp_to_vp: get msg index: " 832 "msg_index %d bufoffset_index %d", 833 *msg_index, 834 *bufoffset)); 835 836 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rxbuf_pp_to_vp")); 837 838 return (NXGE_OK); 839 } 840 841 /* 842 * used by quick sort (qsort) function 843 * to perform comparison 844 */ 845 static int 846 nxge_sort_compare(const void *p1, const void *p2) 847 { 848 849 rxbuf_index_info_t *a, *b; 850 851 a = (rxbuf_index_info_t *)p1; 852 b = (rxbuf_index_info_t *)p2; 853 854 if (a->dvma_addr > b->dvma_addr) 855 return (1); 856 if (a->dvma_addr < b->dvma_addr) 857 return (-1); 858 return (0); 859 } 860 861 862 863 /* 864 * grabbed this sort implementation from common/syscall/avl.c 865 * 866 */ 867 /* 868 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 869 * v = Ptr to array/vector of objs 870 * n = # objs in the array 871 * s = size of each obj (must be multiples of a word size) 872 * f = ptr to function to compare two objs 873 * returns (-1 = less than, 0 = equal, 1 = greater than 874 */ 875 void 876 nxge_ksort(caddr_t v, int n, int s, int (*f)()) 877 { 878 int g, i, j, ii; 879 unsigned int *p1, *p2; 880 unsigned int tmp; 881 882 /* No work to do */ 883 if (v == NULL || n <= 1) 884 return; 885 /* Sanity check on arguments */ 886 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 887 ASSERT(s > 0); 888 889 for (g = n / 2; g > 0; g /= 2) { 890 for (i = g; i < n; i++) { 891 for (j = i - g; j >= 0 && 892 (*f)(v + j * s, v + (j + g) * s) == 1; 893 j -= g) { 894 p1 = (unsigned *)(v + j * s); 895 p2 = (unsigned *)(v + (j + g) * s); 896 for (ii = 0; ii < s / 4; ii++) { 897 tmp = *p1; 898 *p1++ = *p2; 899 *p2++ = tmp; 900 } 901 } 902 } 903 } 904 } 905 906 /* 907 * Initialize data structures required for rxdma 908 * buffer dvma->vmem address lookup 909 */ 910 /*ARGSUSED*/ 911 static nxge_status_t 912 nxge_rxbuf_index_info_init(p_nxge_t nxgep, p_rx_rbr_ring_t rbrp) 913 { 914 915 int index; 916 rxring_info_t *ring_info; 917 int max_iteration = 0, max_index = 0; 918 919 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_rxbuf_index_info_init")); 920 921 ring_info = rbrp->ring_info; 922 ring_info->hint[0] = NO_HINT; 923 ring_info->hint[1] = NO_HINT; 924 ring_info->hint[2] = NO_HINT; 925 max_index = rbrp->num_blocks; 926 927 /* read the DVMA address information and sort it */ 928 /* do init of the information array */ 929 930 931 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 932 " nxge_rxbuf_index_info_init Sort ptrs")); 933 934 /* sort the array */ 935 nxge_ksort((void *)ring_info->buffer, max_index, 936 sizeof (rxbuf_index_info_t), nxge_sort_compare); 937 938 939 940 for (index = 0; index < max_index; index++) { 941 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 942 " nxge_rxbuf_index_info_init: sorted chunk %d " 943 " ioaddr $%p kaddr $%p size %x", 944 index, ring_info->buffer[index].dvma_addr, 945 ring_info->buffer[index].kaddr, 946 ring_info->buffer[index].buf_size)); 947 } 948 949 max_iteration = 0; 950 while (max_index >= (1ULL << max_iteration)) 951 max_iteration++; 952 ring_info->max_iterations = max_iteration + 1; 953 NXGE_DEBUG_MSG((nxgep, DMA2_CTL, 954 " nxge_rxbuf_index_info_init Find max iter %d", 955 ring_info->max_iterations)); 956 957 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxbuf_index_info_init")); 958 return (NXGE_OK); 959 } 960 961 /* ARGSUSED */ 962 void 963 nxge_dump_rcr_entry(p_nxge_t nxgep, p_rcr_entry_t entry_p) 964 { 965 #ifdef NXGE_DEBUG 966 967 uint32_t bptr; 968 uint64_t pp; 969 970 bptr = entry_p->bits.hdw.pkt_buf_addr; 971 972 NXGE_DEBUG_MSG((nxgep, RX_CTL, 973 "\trcr entry $%p " 974 "\trcr entry 0x%0llx " 975 "\trcr entry 0x%08x " 976 "\trcr entry 0x%08x " 977 "\tvalue 0x%0llx\n" 978 "\tmulti = %d\n" 979 "\tpkt_type = 0x%x\n" 980 "\tzero_copy = %d\n" 981 "\tnoport = %d\n" 982 "\tpromis = %d\n" 983 "\terror = 0x%04x\n" 984 "\tdcf_err = 0x%01x\n" 985 "\tl2_len = %d\n" 986 "\tpktbufsize = %d\n" 987 "\tpkt_buf_addr = $%p\n" 988 "\tpkt_buf_addr (<< 6) = $%p\n", 989 entry_p, 990 *(int64_t *)entry_p, 991 *(int32_t *)entry_p, 992 *(int32_t *)((char *)entry_p + 32), 993 entry_p->value, 994 entry_p->bits.hdw.multi, 995 entry_p->bits.hdw.pkt_type, 996 entry_p->bits.hdw.zero_copy, 997 entry_p->bits.hdw.noport, 998 entry_p->bits.hdw.promis, 999 entry_p->bits.hdw.error, 1000 entry_p->bits.hdw.dcf_err, 1001 entry_p->bits.hdw.l2_len, 1002 entry_p->bits.hdw.pktbufsz, 1003 bptr, 1004 entry_p->bits.ldw.pkt_buf_addr)); 1005 1006 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 1007 RCR_PKT_BUF_ADDR_SHIFT; 1008 1009 NXGE_DEBUG_MSG((nxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 1010 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 1011 #endif 1012 } 1013 1014 void 1015 nxge_rxdma_regs_dump(p_nxge_t nxgep, int rdc) 1016 { 1017 npi_handle_t handle; 1018 rbr_stat_t rbr_stat; 1019 addr44_t hd_addr; 1020 addr44_t tail_addr; 1021 uint16_t qlen; 1022 1023 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1024 "==> nxge_rxdma_regs_dump: rdc channel %d", rdc)); 1025 1026 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1027 1028 /* RBR head */ 1029 hd_addr.addr = 0; 1030 (void) npi_rxdma_rdc_rbr_head_get(handle, rdc, &hd_addr); 1031 printf("nxge_rxdma_regs_dump: got hdptr $%p \n", 1032 (void *)hd_addr.addr); 1033 1034 /* RBR stats */ 1035 (void) npi_rxdma_rdc_rbr_stat_get(handle, rdc, &rbr_stat); 1036 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); 1037 1038 /* RCR tail */ 1039 tail_addr.addr = 0; 1040 (void) npi_rxdma_rdc_rcr_tail_get(handle, rdc, &tail_addr); 1041 printf("nxge_rxdma_regs_dump: got tail ptr $%p \n", 1042 (void *)tail_addr.addr); 1043 1044 /* RCR qlen */ 1045 (void) npi_rxdma_rdc_rcr_qlen_get(handle, rdc, &qlen); 1046 printf("nxge_rxdma_regs_dump: rcr len %x \n", qlen); 1047 1048 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1049 "<== nxge_rxdma_regs_dump: rdc rdc %d", rdc)); 1050 } 1051 1052 void 1053 nxge_rxdma_stop(p_nxge_t nxgep) 1054 { 1055 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop")); 1056 1057 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1058 (void) nxge_rx_mac_disable(nxgep); 1059 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1060 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop")); 1061 } 1062 1063 void 1064 nxge_rxdma_stop_reinit(p_nxge_t nxgep) 1065 { 1066 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_reinit")); 1067 1068 (void) nxge_rxdma_stop(nxgep); 1069 (void) nxge_uninit_rxdma_channels(nxgep); 1070 (void) nxge_init_rxdma_channels(nxgep); 1071 1072 #ifndef AXIS_DEBUG_LB 1073 (void) nxge_xcvr_init(nxgep); 1074 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1075 #endif 1076 (void) nxge_rx_mac_enable(nxgep); 1077 1078 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_reinit")); 1079 } 1080 1081 nxge_status_t 1082 nxge_rxdma_hw_mode(p_nxge_t nxgep, boolean_t enable) 1083 { 1084 int i, ndmas; 1085 uint16_t channel; 1086 p_rx_rbr_rings_t rx_rbr_rings; 1087 p_rx_rbr_ring_t *rbr_rings; 1088 npi_handle_t handle; 1089 npi_status_t rs = NPI_SUCCESS; 1090 nxge_status_t status = NXGE_OK; 1091 1092 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1093 "==> nxge_rxdma_hw_mode: mode %d", enable)); 1094 1095 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1096 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1097 "<== nxge_rxdma_mode: not initialized")); 1098 return (NXGE_ERROR); 1099 } 1100 1101 rx_rbr_rings = nxgep->rx_rbr_rings; 1102 if (rx_rbr_rings == NULL) { 1103 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1104 "<== nxge_rxdma_mode: NULL ring pointer")); 1105 return (NXGE_ERROR); 1106 } 1107 if (rx_rbr_rings->rbr_rings == NULL) { 1108 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1109 "<== nxge_rxdma_mode: NULL rbr rings pointer")); 1110 return (NXGE_ERROR); 1111 } 1112 1113 ndmas = rx_rbr_rings->ndmas; 1114 if (!ndmas) { 1115 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1116 "<== nxge_rxdma_mode: no channel")); 1117 return (NXGE_ERROR); 1118 } 1119 1120 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1121 "==> nxge_rxdma_mode (ndmas %d)", ndmas)); 1122 1123 rbr_rings = rx_rbr_rings->rbr_rings; 1124 1125 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1126 for (i = 0; i < ndmas; i++) { 1127 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 1128 continue; 1129 } 1130 channel = rbr_rings[i]->rdc; 1131 if (enable) { 1132 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1133 "==> nxge_rxdma_hw_mode: channel %d (enable)", 1134 channel)); 1135 rs = npi_rxdma_cfg_rdc_enable(handle, channel); 1136 } else { 1137 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1138 "==> nxge_rxdma_hw_mode: channel %d (disable)", 1139 channel)); 1140 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 1141 } 1142 } 1143 1144 status = ((rs == NPI_SUCCESS) ? NXGE_OK : NXGE_ERROR | rs); 1145 1146 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1147 "<== nxge_rxdma_hw_mode: status 0x%x", status)); 1148 1149 return (status); 1150 } 1151 1152 void 1153 nxge_rxdma_enable_channel(p_nxge_t nxgep, uint16_t channel) 1154 { 1155 npi_handle_t handle; 1156 1157 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1158 "==> nxge_rxdma_enable_channel: channel %d", channel)); 1159 1160 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1161 (void) npi_rxdma_cfg_rdc_enable(handle, channel); 1162 1163 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_enable_channel")); 1164 } 1165 1166 void 1167 nxge_rxdma_disable_channel(p_nxge_t nxgep, uint16_t channel) 1168 { 1169 npi_handle_t handle; 1170 1171 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 1172 "==> nxge_rxdma_disable_channel: channel %d", channel)); 1173 1174 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1175 (void) npi_rxdma_cfg_rdc_disable(handle, channel); 1176 1177 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_rxdma_disable_channel")); 1178 } 1179 1180 void 1181 nxge_hw_start_rx(p_nxge_t nxgep) 1182 { 1183 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_start_rx")); 1184 1185 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1186 (void) nxge_rx_mac_enable(nxgep); 1187 1188 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_start_rx")); 1189 } 1190 1191 /*ARGSUSED*/ 1192 void 1193 nxge_fixup_rxdma_rings(p_nxge_t nxgep) 1194 { 1195 int i, ndmas; 1196 uint16_t rdc; 1197 p_rx_rbr_rings_t rx_rbr_rings; 1198 p_rx_rbr_ring_t *rbr_rings; 1199 p_rx_rcr_rings_t rx_rcr_rings; 1200 1201 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_fixup_rxdma_rings")); 1202 1203 rx_rbr_rings = nxgep->rx_rbr_rings; 1204 if (rx_rbr_rings == NULL) { 1205 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1206 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1207 return; 1208 } 1209 ndmas = rx_rbr_rings->ndmas; 1210 if (!ndmas) { 1211 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1212 "<== nxge_fixup_rxdma_rings: no channel")); 1213 return; 1214 } 1215 1216 rx_rcr_rings = nxgep->rx_rcr_rings; 1217 if (rx_rcr_rings == NULL) { 1218 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1219 "<== nxge_fixup_rxdma_rings: NULL ring pointer")); 1220 return; 1221 } 1222 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1223 "==> nxge_fixup_rxdma_rings (ndmas %d)", ndmas)); 1224 1225 nxge_rxdma_hw_stop(nxgep); 1226 1227 rbr_rings = rx_rbr_rings->rbr_rings; 1228 for (i = 0; i < ndmas; i++) { 1229 rdc = rbr_rings[i]->rdc; 1230 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1231 "==> nxge_fixup_rxdma_rings: channel %d " 1232 "ring $%px", rdc, rbr_rings[i])); 1233 (void) nxge_rxdma_fixup_channel(nxgep, rdc, i); 1234 } 1235 1236 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_fixup_rxdma_rings")); 1237 } 1238 1239 void 1240 nxge_rxdma_fix_channel(p_nxge_t nxgep, uint16_t channel) 1241 { 1242 int i; 1243 1244 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fix_channel")); 1245 i = nxge_rxdma_get_ring_index(nxgep, channel); 1246 if (i < 0) { 1247 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1248 "<== nxge_rxdma_fix_channel: no entry found")); 1249 return; 1250 } 1251 1252 nxge_rxdma_fixup_channel(nxgep, channel, i); 1253 1254 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_txdma_fix_channel")); 1255 } 1256 1257 void 1258 nxge_rxdma_fixup_channel(p_nxge_t nxgep, uint16_t channel, int entry) 1259 { 1260 int ndmas; 1261 p_rx_rbr_rings_t rx_rbr_rings; 1262 p_rx_rbr_ring_t *rbr_rings; 1263 p_rx_rcr_rings_t rx_rcr_rings; 1264 p_rx_rcr_ring_t *rcr_rings; 1265 p_rx_mbox_areas_t rx_mbox_areas_p; 1266 p_rx_mbox_t *rx_mbox_p; 1267 p_nxge_dma_pool_t dma_buf_poolp; 1268 p_nxge_dma_pool_t dma_cntl_poolp; 1269 p_rx_rbr_ring_t rbrp; 1270 p_rx_rcr_ring_t rcrp; 1271 p_rx_mbox_t mboxp; 1272 p_nxge_dma_common_t dmap; 1273 nxge_status_t status = NXGE_OK; 1274 1275 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fixup_channel")); 1276 1277 (void) nxge_rxdma_stop_channel(nxgep, channel); 1278 1279 dma_buf_poolp = nxgep->rx_buf_pool_p; 1280 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 1281 1282 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 1283 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1284 "<== nxge_rxdma_fixup_channel: buf not allocated")); 1285 return; 1286 } 1287 1288 ndmas = dma_buf_poolp->ndmas; 1289 if (!ndmas) { 1290 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 1291 "<== nxge_rxdma_fixup_channel: no dma allocated")); 1292 return; 1293 } 1294 1295 rx_rbr_rings = nxgep->rx_rbr_rings; 1296 rx_rcr_rings = nxgep->rx_rcr_rings; 1297 rbr_rings = rx_rbr_rings->rbr_rings; 1298 rcr_rings = rx_rcr_rings->rcr_rings; 1299 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 1300 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 1301 1302 /* Reinitialize the receive block and completion rings */ 1303 rbrp = (p_rx_rbr_ring_t)rbr_rings[entry], 1304 rcrp = (p_rx_rcr_ring_t)rcr_rings[entry], 1305 mboxp = (p_rx_mbox_t)rx_mbox_p[entry]; 1306 1307 1308 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 1309 rbrp->rbr_rd_index = 0; 1310 rcrp->comp_rd_index = 0; 1311 rcrp->comp_wt_index = 0; 1312 1313 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 1314 bzero((caddr_t)dmap->kaddrp, dmap->alength); 1315 1316 status = nxge_rxdma_start_channel(nxgep, channel, 1317 rbrp, rcrp, mboxp); 1318 if (status != NXGE_OK) { 1319 goto nxge_rxdma_fixup_channel_fail; 1320 } 1321 if (status != NXGE_OK) { 1322 goto nxge_rxdma_fixup_channel_fail; 1323 } 1324 1325 nxge_rxdma_fixup_channel_fail: 1326 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1327 "==> nxge_rxdma_fixup_channel: failed (0x%08x)", status)); 1328 1329 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fixup_channel")); 1330 } 1331 1332 int 1333 nxge_rxdma_get_ring_index(p_nxge_t nxgep, uint16_t channel) 1334 { 1335 int i, ndmas; 1336 uint16_t rdc; 1337 p_rx_rbr_rings_t rx_rbr_rings; 1338 p_rx_rbr_ring_t *rbr_rings; 1339 1340 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1341 "==> nxge_rxdma_get_ring_index: channel %d", channel)); 1342 1343 rx_rbr_rings = nxgep->rx_rbr_rings; 1344 if (rx_rbr_rings == NULL) { 1345 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1346 "<== nxge_rxdma_get_ring_index: NULL ring pointer")); 1347 return (-1); 1348 } 1349 ndmas = rx_rbr_rings->ndmas; 1350 if (!ndmas) { 1351 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1352 "<== nxge_rxdma_get_ring_index: no channel")); 1353 return (-1); 1354 } 1355 1356 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1357 "==> nxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 1358 1359 rbr_rings = rx_rbr_rings->rbr_rings; 1360 for (i = 0; i < ndmas; i++) { 1361 rdc = rbr_rings[i]->rdc; 1362 if (channel == rdc) { 1363 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1364 "==> nxge_rxdma_get_rbr_ring: " 1365 "channel %d (index %d) " 1366 "ring %d", channel, i, 1367 rbr_rings[i])); 1368 return (i); 1369 } 1370 } 1371 1372 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1373 "<== nxge_rxdma_get_rbr_ring_index: not found")); 1374 1375 return (-1); 1376 } 1377 1378 p_rx_rbr_ring_t 1379 nxge_rxdma_get_rbr_ring(p_nxge_t nxgep, uint16_t channel) 1380 { 1381 int i, ndmas; 1382 uint16_t rdc; 1383 p_rx_rbr_rings_t rx_rbr_rings; 1384 p_rx_rbr_ring_t *rbr_rings; 1385 1386 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1387 "==> nxge_rxdma_get_rbr_ring: channel %d", channel)); 1388 1389 rx_rbr_rings = nxgep->rx_rbr_rings; 1390 if (rx_rbr_rings == NULL) { 1391 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1392 "<== nxge_rxdma_get_rbr_ring: NULL ring pointer")); 1393 return (NULL); 1394 } 1395 ndmas = rx_rbr_rings->ndmas; 1396 if (!ndmas) { 1397 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1398 "<== nxge_rxdma_get_rbr_ring: no channel")); 1399 return (NULL); 1400 } 1401 1402 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1403 "==> nxge_rxdma_get_ring (ndmas %d)", ndmas)); 1404 1405 rbr_rings = rx_rbr_rings->rbr_rings; 1406 for (i = 0; i < ndmas; i++) { 1407 rdc = rbr_rings[i]->rdc; 1408 if (channel == rdc) { 1409 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1410 "==> nxge_rxdma_get_rbr_ring: channel %d " 1411 "ring $%p", channel, rbr_rings[i])); 1412 return (rbr_rings[i]); 1413 } 1414 } 1415 1416 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1417 "<== nxge_rxdma_get_rbr_ring: not found")); 1418 1419 return (NULL); 1420 } 1421 1422 p_rx_rcr_ring_t 1423 nxge_rxdma_get_rcr_ring(p_nxge_t nxgep, uint16_t channel) 1424 { 1425 int i, ndmas; 1426 uint16_t rdc; 1427 p_rx_rcr_rings_t rx_rcr_rings; 1428 p_rx_rcr_ring_t *rcr_rings; 1429 1430 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1431 "==> nxge_rxdma_get_rcr_ring: channel %d", channel)); 1432 1433 rx_rcr_rings = nxgep->rx_rcr_rings; 1434 if (rx_rcr_rings == NULL) { 1435 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1436 "<== nxge_rxdma_get_rcr_ring: NULL ring pointer")); 1437 return (NULL); 1438 } 1439 ndmas = rx_rcr_rings->ndmas; 1440 if (!ndmas) { 1441 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1442 "<== nxge_rxdma_get_rcr_ring: no channel")); 1443 return (NULL); 1444 } 1445 1446 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1447 "==> nxge_rxdma_get_rcr_ring (ndmas %d)", ndmas)); 1448 1449 rcr_rings = rx_rcr_rings->rcr_rings; 1450 for (i = 0; i < ndmas; i++) { 1451 rdc = rcr_rings[i]->rdc; 1452 if (channel == rdc) { 1453 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1454 "==> nxge_rxdma_get_rcr_ring: channel %d " 1455 "ring $%p", channel, rcr_rings[i])); 1456 return (rcr_rings[i]); 1457 } 1458 } 1459 1460 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1461 "<== nxge_rxdma_get_rcr_ring: not found")); 1462 1463 return (NULL); 1464 } 1465 1466 /* 1467 * Static functions start here. 1468 */ 1469 static p_rx_msg_t 1470 nxge_allocb(size_t size, uint32_t pri, p_nxge_dma_common_t dmabuf_p) 1471 { 1472 p_rx_msg_t nxge_mp = NULL; 1473 p_nxge_dma_common_t dmamsg_p; 1474 uchar_t *buffer; 1475 1476 nxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 1477 if (nxge_mp == NULL) { 1478 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1479 "Allocation of a rx msg failed.")); 1480 goto nxge_allocb_exit; 1481 } 1482 1483 nxge_mp->use_buf_pool = B_FALSE; 1484 if (dmabuf_p) { 1485 nxge_mp->use_buf_pool = B_TRUE; 1486 dmamsg_p = (p_nxge_dma_common_t)&nxge_mp->buf_dma; 1487 *dmamsg_p = *dmabuf_p; 1488 dmamsg_p->nblocks = 1; 1489 dmamsg_p->block_size = size; 1490 dmamsg_p->alength = size; 1491 buffer = (uchar_t *)dmabuf_p->kaddrp; 1492 1493 dmabuf_p->kaddrp = (void *) 1494 ((char *)dmabuf_p->kaddrp + size); 1495 dmabuf_p->ioaddr_pp = (void *) 1496 ((char *)dmabuf_p->ioaddr_pp + size); 1497 dmabuf_p->alength -= size; 1498 dmabuf_p->offset += size; 1499 dmabuf_p->dma_cookie.dmac_laddress += size; 1500 dmabuf_p->dma_cookie.dmac_size -= size; 1501 1502 } else { 1503 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 1504 if (buffer == NULL) { 1505 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 1506 "Allocation of a receive page failed.")); 1507 goto nxge_allocb_fail1; 1508 } 1509 } 1510 1511 nxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &nxge_mp->freeb); 1512 if (nxge_mp->rx_mblk_p == NULL) { 1513 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "desballoc failed.")); 1514 goto nxge_allocb_fail2; 1515 } 1516 1517 nxge_mp->buffer = buffer; 1518 nxge_mp->block_size = size; 1519 nxge_mp->freeb.free_func = (void (*)())nxge_freeb; 1520 nxge_mp->freeb.free_arg = (caddr_t)nxge_mp; 1521 nxge_mp->ref_cnt = 1; 1522 nxge_mp->free = B_TRUE; 1523 nxge_mp->rx_use_bcopy = B_FALSE; 1524 1525 atomic_inc_32(&nxge_mblks_pending); 1526 1527 goto nxge_allocb_exit; 1528 1529 nxge_allocb_fail2: 1530 if (!nxge_mp->use_buf_pool) { 1531 KMEM_FREE(buffer, size); 1532 } 1533 1534 nxge_allocb_fail1: 1535 KMEM_FREE(nxge_mp, sizeof (rx_msg_t)); 1536 nxge_mp = NULL; 1537 1538 nxge_allocb_exit: 1539 return (nxge_mp); 1540 } 1541 1542 p_mblk_t 1543 nxge_dupb(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1544 { 1545 p_mblk_t mp; 1546 1547 NXGE_DEBUG_MSG((NULL, MEM_CTL, "==> nxge_dupb")); 1548 NXGE_DEBUG_MSG((NULL, MEM_CTL, "nxge_mp = $%p " 1549 "offset = 0x%08X " 1550 "size = 0x%08X", 1551 nxge_mp, offset, size)); 1552 1553 mp = desballoc(&nxge_mp->buffer[offset], size, 1554 0, &nxge_mp->freeb); 1555 if (mp == NULL) { 1556 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1557 goto nxge_dupb_exit; 1558 } 1559 atomic_inc_32(&nxge_mp->ref_cnt); 1560 atomic_inc_32(&nxge_mblks_pending); 1561 1562 1563 nxge_dupb_exit: 1564 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1565 nxge_mp)); 1566 return (mp); 1567 } 1568 1569 p_mblk_t 1570 nxge_dupb_bcopy(p_rx_msg_t nxge_mp, uint_t offset, size_t size) 1571 { 1572 p_mblk_t mp; 1573 uchar_t *dp; 1574 1575 mp = allocb(size + NXGE_RXBUF_EXTRA, 0); 1576 if (mp == NULL) { 1577 NXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 1578 goto nxge_dupb_bcopy_exit; 1579 } 1580 dp = mp->b_rptr = mp->b_rptr + NXGE_RXBUF_EXTRA; 1581 bcopy((void *)&nxge_mp->buffer[offset], dp, size); 1582 mp->b_wptr = dp + size; 1583 1584 nxge_dupb_bcopy_exit: 1585 NXGE_DEBUG_MSG((NULL, MEM_CTL, "<== nxge_dupb mp = $%p", 1586 nxge_mp)); 1587 return (mp); 1588 } 1589 1590 void nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, 1591 p_rx_msg_t rx_msg_p); 1592 1593 void 1594 nxge_post_page(p_nxge_t nxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 1595 { 1596 1597 npi_handle_t handle; 1598 1599 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_post_page")); 1600 1601 /* Reuse this buffer */ 1602 rx_msg_p->free = B_FALSE; 1603 rx_msg_p->cur_usage_cnt = 0; 1604 rx_msg_p->max_usage_cnt = 0; 1605 rx_msg_p->pkt_buf_size = 0; 1606 1607 if (rx_rbr_p->rbr_use_bcopy) { 1608 rx_msg_p->rx_use_bcopy = B_FALSE; 1609 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1610 } 1611 1612 /* 1613 * Get the rbr header pointer and its offset index. 1614 */ 1615 MUTEX_ENTER(&rx_rbr_p->post_lock); 1616 1617 1618 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1619 rx_rbr_p->rbr_wrap_mask); 1620 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1621 MUTEX_EXIT(&rx_rbr_p->post_lock); 1622 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1623 npi_rxdma_rdc_rbr_kick(handle, rx_rbr_p->rdc, 1); 1624 1625 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1626 "<== nxge_post_page (channel %d post_next_index %d)", 1627 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1628 1629 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_post_page")); 1630 } 1631 1632 void 1633 nxge_freeb(p_rx_msg_t rx_msg_p) 1634 { 1635 size_t size; 1636 uchar_t *buffer = NULL; 1637 int ref_cnt; 1638 1639 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> nxge_freeb")); 1640 NXGE_DEBUG_MSG((NULL, MEM2_CTL, 1641 "nxge_freeb:rx_msg_p = $%p (block pending %d)", 1642 rx_msg_p, nxge_mblks_pending)); 1643 1644 1645 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1646 atomic_dec_32(&nxge_mblks_pending); 1647 if (!ref_cnt) { 1648 buffer = rx_msg_p->buffer; 1649 size = rx_msg_p->block_size; 1650 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "nxge_freeb: " 1651 "will free: rx_msg_p = $%p (block pending %d)", 1652 rx_msg_p, nxge_mblks_pending)); 1653 1654 if (!rx_msg_p->use_buf_pool) { 1655 KMEM_FREE(buffer, size); 1656 } 1657 1658 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1659 return; 1660 } 1661 1662 /* 1663 * Repost buffer. 1664 */ 1665 if ((ref_cnt == 1) && (rx_msg_p->free == B_TRUE)) { 1666 NXGE_DEBUG_MSG((NULL, RX_CTL, 1667 "nxge_freeb: post page $%p:", rx_msg_p)); 1668 nxge_post_page(rx_msg_p->nxgep, rx_msg_p->rx_rbr_p, 1669 rx_msg_p); 1670 } 1671 1672 NXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== nxge_freeb")); 1673 } 1674 1675 uint_t 1676 nxge_rx_intr(void *arg1, void *arg2) 1677 { 1678 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 1679 p_nxge_t nxgep = (p_nxge_t)arg2; 1680 p_nxge_ldg_t ldgp; 1681 uint8_t channel; 1682 npi_handle_t handle; 1683 rx_dma_ctl_stat_t cs; 1684 1685 #ifdef NXGE_DEBUG 1686 rxdma_cfig1_t cfg; 1687 #endif 1688 uint_t serviced = DDI_INTR_UNCLAIMED; 1689 1690 if (ldvp == NULL) { 1691 NXGE_DEBUG_MSG((NULL, INT_CTL, 1692 "<== nxge_rx_intr: arg2 $%p arg1 $%p", 1693 nxgep, ldvp)); 1694 1695 return (DDI_INTR_CLAIMED); 1696 } 1697 1698 if (arg2 == NULL || (void *)ldvp->nxgep != arg2) { 1699 nxgep = ldvp->nxgep; 1700 } 1701 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1702 "==> nxge_rx_intr: arg2 $%p arg1 $%p", 1703 nxgep, ldvp)); 1704 1705 /* 1706 * This interrupt handler is for a specific 1707 * receive dma channel. 1708 */ 1709 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1710 /* 1711 * Get the control and status for this channel. 1712 */ 1713 channel = ldvp->channel; 1714 ldgp = ldvp->ldgp; 1715 RXDMA_REG_READ64(handle, RX_DMA_CTL_STAT_REG, channel, &cs.value); 1716 1717 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_intr:channel %d " 1718 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1719 channel, 1720 cs.value, 1721 cs.bits.hdw.rcrto, 1722 cs.bits.hdw.rcrthres)); 1723 1724 nxge_rx_pkts_vring(nxgep, ldvp->vdma_index, ldvp, cs); 1725 serviced = DDI_INTR_CLAIMED; 1726 1727 /* error events. */ 1728 if (cs.value & RX_DMA_CTL_STAT_ERROR) { 1729 (void) nxge_rx_err_evnts(nxgep, ldvp->vdma_index, ldvp, cs); 1730 } 1731 1732 nxge_intr_exit: 1733 1734 1735 /* 1736 * Enable the mailbox update interrupt if we want 1737 * to use mailbox. We probably don't need to use 1738 * mailbox as it only saves us one pio read. 1739 * Also write 1 to rcrthres and rcrto to clear 1740 * these two edge triggered bits. 1741 */ 1742 1743 cs.value &= RX_DMA_CTL_STAT_WR1C; 1744 cs.bits.hdw.mex = 1; 1745 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, 1746 cs.value); 1747 1748 /* 1749 * Rearm this logical group if this is a single device 1750 * group. 1751 */ 1752 if (ldgp->nldvs == 1) { 1753 ldgimgm_t mgm; 1754 mgm.value = 0; 1755 mgm.bits.ldw.arm = 1; 1756 mgm.bits.ldw.timer = ldgp->ldg_timer; 1757 NXGE_REG_WR64(handle, 1758 LDGIMGN_REG + LDSV_OFFSET(ldgp->ldg), 1759 mgm.value); 1760 } 1761 1762 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_intr: serviced %d", 1763 serviced)); 1764 return (serviced); 1765 } 1766 1767 /* 1768 * Process the packets received in the specified logical device 1769 * and pass up a chain of message blocks to the upper layer. 1770 */ 1771 static void 1772 nxge_rx_pkts_vring(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1773 rx_dma_ctl_stat_t cs) 1774 { 1775 p_mblk_t mp; 1776 p_rx_rcr_ring_t rcrp; 1777 1778 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring")); 1779 if ((mp = nxge_rx_pkts(nxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1780 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1781 "<== nxge_rx_pkts_vring: no mp")); 1782 return; 1783 } 1784 1785 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts_vring: $%p", 1786 mp)); 1787 1788 #ifdef NXGE_DEBUG 1789 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1790 "==> nxge_rx_pkts_vring:calling mac_rx " 1791 "LEN %d mp $%p mp->b_cont $%p mp->b_next $%p rcrp $%p " 1792 "mac_handle $%p", 1793 mp->b_wptr - mp->b_rptr, 1794 mp, mp->b_cont, mp->b_next, 1795 rcrp, rcrp->rcr_mac_handle)); 1796 1797 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1798 "==> nxge_rx_pkts_vring: dump packets " 1799 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1800 mp, 1801 mp->b_rptr, 1802 mp->b_wptr, 1803 nxge_dump_packet((char *)mp->b_rptr, 1804 mp->b_wptr - mp->b_rptr))); 1805 if (mp->b_cont) { 1806 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1807 "==> nxge_rx_pkts_vring: dump b_cont packets " 1808 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1809 mp->b_cont, 1810 mp->b_cont->b_rptr, 1811 mp->b_cont->b_wptr, 1812 nxge_dump_packet((char *)mp->b_cont->b_rptr, 1813 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1814 } 1815 if (mp->b_next) { 1816 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1817 "==> nxge_rx_pkts_vring: dump next packets " 1818 "(b_rptr $%p): %s", 1819 mp->b_next->b_rptr, 1820 nxge_dump_packet((char *)mp->b_next->b_rptr, 1821 mp->b_next->b_wptr - mp->b_next->b_rptr))); 1822 } 1823 #endif 1824 1825 mac_rx(nxgep->mach, rcrp->rcr_mac_handle, mp); 1826 } 1827 1828 1829 /* 1830 * This routine is the main packet receive processing function. 1831 * It gets the packet type, error code, and buffer related 1832 * information from the receive completion entry. 1833 * How many completion entries to process is based on the number of packets 1834 * queued by the hardware, a hardware maintained tail pointer 1835 * and a configurable receive packet count. 1836 * 1837 * A chain of message blocks will be created as result of processing 1838 * the completion entries. This chain of message blocks will be returned and 1839 * a hardware control status register will be updated with the number of 1840 * packets were removed from the hardware queue. 1841 * 1842 */ 1843 mblk_t * 1844 nxge_rx_pkts(p_nxge_t nxgep, uint_t vindex, p_nxge_ldv_t ldvp, 1845 p_rx_rcr_ring_t *rcrp, rx_dma_ctl_stat_t cs) 1846 { 1847 npi_handle_t handle; 1848 uint8_t channel; 1849 p_rx_rcr_rings_t rx_rcr_rings; 1850 p_rx_rcr_ring_t rcr_p; 1851 uint32_t comp_rd_index; 1852 p_rcr_entry_t rcr_desc_rd_head_p; 1853 p_rcr_entry_t rcr_desc_rd_head_pp; 1854 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1855 uint16_t qlen, nrcr_read, npkt_read; 1856 uint32_t qlen_hw; 1857 boolean_t multi; 1858 rcrcfig_b_t rcr_cfg_b; 1859 #if defined(_BIG_ENDIAN) 1860 npi_status_t rs = NPI_SUCCESS; 1861 #endif 1862 1863 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:vindex %d " 1864 "channel %d", vindex, ldvp->channel)); 1865 1866 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1867 return (NULL); 1868 } 1869 handle = NXGE_DEV_NPI_HANDLE(nxgep); 1870 rx_rcr_rings = nxgep->rx_rcr_rings; 1871 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1872 channel = rcr_p->rdc; 1873 if (channel != ldvp->channel) { 1874 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1875 "channel %d, and rcr channel %d not matched.", 1876 vindex, ldvp->channel, channel)); 1877 return (NULL); 1878 } 1879 1880 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1881 "==> nxge_rx_pkts: START: rcr channel %d " 1882 "head_p $%p head_pp $%p index %d ", 1883 channel, rcr_p->rcr_desc_rd_head_p, 1884 rcr_p->rcr_desc_rd_head_pp, 1885 rcr_p->comp_rd_index)); 1886 1887 1888 #if !defined(_BIG_ENDIAN) 1889 qlen = RXDMA_REG_READ32(handle, RCRSTAT_A_REG, channel) & 0xffff; 1890 #else 1891 rs = npi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1892 if (rs != NPI_SUCCESS) { 1893 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:index %d " 1894 "channel %d, get qlen failed 0x%08x", 1895 vindex, ldvp->channel, rs)); 1896 return (NULL); 1897 } 1898 #endif 1899 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rx_pkts:rcr channel %d " 1900 "qlen %d", channel, qlen)); 1901 1902 1903 1904 if (!qlen) { 1905 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1906 "==> nxge_rx_pkts:rcr channel %d " 1907 "qlen %d (no pkts)", channel, qlen)); 1908 1909 return (NULL); 1910 } 1911 1912 comp_rd_index = rcr_p->comp_rd_index; 1913 1914 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1915 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1916 nrcr_read = npkt_read = 0; 1917 1918 /* 1919 * Number of packets queued 1920 * (The jumbo or multi packet will be counted as only one 1921 * packets and it may take up more than one completion entry). 1922 */ 1923 qlen_hw = (qlen < nxge_max_rx_pkts) ? 1924 qlen : nxge_max_rx_pkts; 1925 head_mp = NULL; 1926 tail_mp = &head_mp; 1927 nmp = mp_cont = NULL; 1928 multi = B_FALSE; 1929 1930 while (qlen_hw) { 1931 1932 #ifdef NXGE_DEBUG 1933 nxge_dump_rcr_entry(nxgep, rcr_desc_rd_head_p); 1934 #endif 1935 /* 1936 * Process one completion ring entry. 1937 */ 1938 nxge_receive_packet(nxgep, 1939 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont); 1940 1941 /* 1942 * message chaining modes 1943 */ 1944 if (nmp) { 1945 nmp->b_next = NULL; 1946 if (!multi && !mp_cont) { /* frame fits a partition */ 1947 *tail_mp = nmp; 1948 tail_mp = &nmp->b_next; 1949 nmp = NULL; 1950 } else if (multi && !mp_cont) { /* first segment */ 1951 *tail_mp = nmp; 1952 tail_mp = &nmp->b_cont; 1953 } else if (multi && mp_cont) { /* mid of multi segs */ 1954 *tail_mp = mp_cont; 1955 tail_mp = &mp_cont->b_cont; 1956 } else if (!multi && mp_cont) { /* last segment */ 1957 *tail_mp = mp_cont; 1958 tail_mp = &nmp->b_next; 1959 nmp = NULL; 1960 } 1961 } 1962 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1963 "==> nxge_rx_pkts: loop: rcr channel %d " 1964 "before updating: multi %d " 1965 "nrcr_read %d " 1966 "npk read %d " 1967 "head_pp $%p index %d ", 1968 channel, 1969 multi, 1970 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1971 comp_rd_index)); 1972 1973 if (!multi) { 1974 qlen_hw--; 1975 npkt_read++; 1976 } 1977 1978 /* 1979 * Update the next read entry. 1980 */ 1981 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1982 rcr_p->comp_wrap_mask); 1983 1984 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1985 rcr_p->rcr_desc_first_p, 1986 rcr_p->rcr_desc_last_p); 1987 1988 nrcr_read++; 1989 1990 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1991 "<== nxge_rx_pkts: (SAM, process one packet) " 1992 "nrcr_read %d", 1993 nrcr_read)); 1994 NXGE_DEBUG_MSG((nxgep, RX_CTL, 1995 "==> nxge_rx_pkts: loop: rcr channel %d " 1996 "multi %d " 1997 "nrcr_read %d " 1998 "npk read %d " 1999 "head_pp $%p index %d ", 2000 channel, 2001 multi, 2002 nrcr_read, npkt_read, rcr_desc_rd_head_pp, 2003 comp_rd_index)); 2004 2005 } 2006 2007 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 2008 rcr_p->comp_rd_index = comp_rd_index; 2009 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 2010 2011 if ((nxgep->intr_timeout != rcr_p->intr_timeout) || 2012 (nxgep->intr_threshold != rcr_p->intr_threshold)) { 2013 rcr_p->intr_timeout = nxgep->intr_timeout; 2014 rcr_p->intr_threshold = nxgep->intr_threshold; 2015 rcr_cfg_b.value = 0x0ULL; 2016 if (rcr_p->intr_timeout) 2017 rcr_cfg_b.bits.ldw.entout = 1; 2018 rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout; 2019 rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold; 2020 RXDMA_REG_WRITE64(handle, RCRCFIG_B_REG, 2021 channel, rcr_cfg_b.value); 2022 } 2023 2024 cs.bits.ldw.pktread = npkt_read; 2025 cs.bits.ldw.ptrread = nrcr_read; 2026 RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, 2027 channel, cs.value); 2028 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2029 "==> nxge_rx_pkts: EXIT: rcr channel %d " 2030 "head_pp $%p index %016llx ", 2031 channel, 2032 rcr_p->rcr_desc_rd_head_pp, 2033 rcr_p->comp_rd_index)); 2034 /* 2035 * Update RCR buffer pointer read and number of packets 2036 * read. 2037 */ 2038 2039 *rcrp = rcr_p; 2040 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_pkts")); 2041 return (head_mp); 2042 } 2043 2044 void 2045 nxge_receive_packet(p_nxge_t nxgep, 2046 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 2047 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont) 2048 { 2049 p_mblk_t nmp = NULL; 2050 uint64_t multi; 2051 uint64_t dcf_err; 2052 uint8_t channel; 2053 2054 boolean_t first_entry = B_TRUE; 2055 boolean_t is_tcp_udp = B_FALSE; 2056 boolean_t buffer_free = B_FALSE; 2057 boolean_t error_send_up = B_FALSE; 2058 uint8_t error_type; 2059 uint16_t l2_len; 2060 uint16_t skip_len; 2061 uint8_t pktbufsz_type; 2062 uint16_t pktbufsz; 2063 uint64_t rcr_entry; 2064 uint64_t *pkt_buf_addr_pp; 2065 uint64_t *pkt_buf_addr_p; 2066 uint32_t buf_offset; 2067 uint32_t bsize; 2068 uint32_t error_disp_cnt; 2069 uint32_t msg_index; 2070 p_rx_rbr_ring_t rx_rbr_p; 2071 p_rx_msg_t *rx_msg_ring_p; 2072 p_rx_msg_t rx_msg_p; 2073 uint16_t sw_offset_bytes = 0, hdr_size = 0; 2074 nxge_status_t status = NXGE_OK; 2075 boolean_t is_valid = B_FALSE; 2076 p_nxge_rx_ring_stats_t rdc_stats; 2077 uint32_t bytes_read; 2078 uint64_t pkt_type; 2079 uint64_t frag; 2080 #ifdef NXGE_DEBUG 2081 int dump_len; 2082 #endif 2083 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "==> nxge_receive_packet")); 2084 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 2085 2086 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 2087 2088 multi = (rcr_entry & RCR_MULTI_MASK); 2089 dcf_err = (rcr_entry & RCR_DCF_ERROR_MASK); 2090 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 2091 2092 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 2093 frag = (rcr_entry & RCR_FRAG_MASK); 2094 2095 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 2096 2097 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 2098 RCR_PKTBUFSZ_SHIFT); 2099 2100 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 2101 RCR_PKT_BUF_ADDR_SHIFT); 2102 2103 channel = rcr_p->rdc; 2104 2105 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2106 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2107 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2108 "error_type 0x%x pkt_type 0x%x " 2109 "pktbufsz_type %d ", 2110 rcr_desc_rd_head_p, 2111 rcr_entry, pkt_buf_addr_pp, l2_len, 2112 multi, 2113 error_type, 2114 pkt_type, 2115 pktbufsz_type)); 2116 2117 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2118 "==> nxge_receive_packet: entryp $%p entry 0x%0llx " 2119 "pkt_buf_addr_pp $%p l2_len %d multi 0x%llx " 2120 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 2121 rcr_entry, pkt_buf_addr_pp, l2_len, 2122 multi, 2123 error_type, 2124 pkt_type)); 2125 2126 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2127 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2128 "full pkt_buf_addr_pp $%p l2_len %d", 2129 rcr_entry, pkt_buf_addr_pp, l2_len)); 2130 2131 /* get the stats ptr */ 2132 rdc_stats = rcr_p->rdc_stats; 2133 2134 if (!l2_len) { 2135 2136 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2137 "<== nxge_receive_packet: failed: l2 length is 0.")); 2138 return; 2139 } 2140 2141 /* Hardware sends us 4 bytes of CRC as no stripping is done. */ 2142 l2_len -= ETHERFCSL; 2143 2144 /* shift 6 bits to get the full io address */ 2145 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 2146 RCR_PKT_BUF_ADDR_SHIFT_FULL); 2147 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2148 "==> (rbr) nxge_receive_packet: entry 0x%0llx " 2149 "full pkt_buf_addr_pp $%p l2_len %d", 2150 rcr_entry, pkt_buf_addr_pp, l2_len)); 2151 2152 rx_rbr_p = rcr_p->rx_rbr_p; 2153 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 2154 2155 if (first_entry) { 2156 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 2157 RXDMA_HDR_SIZE_DEFAULT); 2158 2159 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2160 "==> nxge_receive_packet: first entry 0x%016llx " 2161 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 2162 rcr_entry, pkt_buf_addr_pp, l2_len, 2163 hdr_size)); 2164 } 2165 2166 MUTEX_ENTER(&rcr_p->lock); 2167 MUTEX_ENTER(&rx_rbr_p->lock); 2168 2169 bytes_read = rcr_p->rcvd_pkt_bytes; 2170 2171 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2172 "==> (rbr 1) nxge_receive_packet: entry 0x%0llx " 2173 "full pkt_buf_addr_pp $%p l2_len %d", 2174 rcr_entry, pkt_buf_addr_pp, l2_len)); 2175 2176 /* 2177 * Packet buffer address in the completion entry points 2178 * to the starting buffer address (offset 0). 2179 * Use the starting buffer address to locate the corresponding 2180 * kernel address. 2181 */ 2182 status = nxge_rxbuf_pp_to_vp(nxgep, rx_rbr_p, 2183 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 2184 &buf_offset, 2185 &msg_index); 2186 2187 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2188 "==> (rbr 2) nxge_receive_packet: entry 0x%0llx " 2189 "full pkt_buf_addr_pp $%p l2_len %d", 2190 rcr_entry, pkt_buf_addr_pp, l2_len)); 2191 2192 if (status != NXGE_OK) { 2193 MUTEX_EXIT(&rx_rbr_p->lock); 2194 MUTEX_EXIT(&rcr_p->lock); 2195 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2196 "<== nxge_receive_packet: found vaddr failed %d", 2197 status)); 2198 return; 2199 } 2200 2201 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2202 "==> (rbr 3) nxge_receive_packet: entry 0x%0llx " 2203 "full pkt_buf_addr_pp $%p l2_len %d", 2204 rcr_entry, pkt_buf_addr_pp, l2_len)); 2205 2206 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2207 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2208 "full pkt_buf_addr_pp $%p l2_len %d", 2209 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2210 2211 rx_msg_p = rx_msg_ring_p[msg_index]; 2212 2213 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2214 "==> (rbr 4 msgindex %d) nxge_receive_packet: entry 0x%0llx " 2215 "full pkt_buf_addr_pp $%p l2_len %d", 2216 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 2217 2218 switch (pktbufsz_type) { 2219 case RCR_PKTBUFSZ_0: 2220 bsize = rx_rbr_p->pkt_buf_size0_bytes; 2221 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2222 "==> nxge_receive_packet: 0 buf %d", bsize)); 2223 break; 2224 case RCR_PKTBUFSZ_1: 2225 bsize = rx_rbr_p->pkt_buf_size1_bytes; 2226 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2227 "==> nxge_receive_packet: 1 buf %d", bsize)); 2228 break; 2229 case RCR_PKTBUFSZ_2: 2230 bsize = rx_rbr_p->pkt_buf_size2_bytes; 2231 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2232 "==> nxge_receive_packet: 2 buf %d", bsize)); 2233 break; 2234 case RCR_SINGLE_BLOCK: 2235 bsize = rx_msg_p->block_size; 2236 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2237 "==> nxge_receive_packet: single %d", bsize)); 2238 2239 break; 2240 default: 2241 MUTEX_EXIT(&rx_rbr_p->lock); 2242 MUTEX_EXIT(&rcr_p->lock); 2243 return; 2244 } 2245 2246 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 2247 (buf_offset + sw_offset_bytes), 2248 (hdr_size + l2_len), 2249 DDI_DMA_SYNC_FORCPU); 2250 2251 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2252 "==> nxge_receive_packet: after first dump:usage count")); 2253 2254 if (rx_msg_p->cur_usage_cnt == 0) { 2255 if (rx_rbr_p->rbr_use_bcopy) { 2256 atomic_inc_32(&rx_rbr_p->rbr_consumed); 2257 if (rx_rbr_p->rbr_consumed < 2258 rx_rbr_p->rbr_threshold_hi) { 2259 if (rx_rbr_p->rbr_threshold_lo == 0 || 2260 ((rx_rbr_p->rbr_consumed >= 2261 rx_rbr_p->rbr_threshold_lo) && 2262 (rx_rbr_p->rbr_bufsize_type >= 2263 pktbufsz_type))) { 2264 rx_msg_p->rx_use_bcopy = B_TRUE; 2265 } 2266 } else { 2267 rx_msg_p->rx_use_bcopy = B_TRUE; 2268 } 2269 } 2270 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2271 "==> nxge_receive_packet: buf %d (new block) ", 2272 bsize)); 2273 2274 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 2275 rx_msg_p->pkt_buf_size = bsize; 2276 rx_msg_p->cur_usage_cnt = 1; 2277 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 2278 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2279 "==> nxge_receive_packet: buf %d " 2280 "(single block) ", 2281 bsize)); 2282 /* 2283 * Buffer can be reused once the free function 2284 * is called. 2285 */ 2286 rx_msg_p->max_usage_cnt = 1; 2287 buffer_free = B_TRUE; 2288 } else { 2289 rx_msg_p->max_usage_cnt = rx_msg_p->block_size/bsize; 2290 if (rx_msg_p->max_usage_cnt == 1) { 2291 buffer_free = B_TRUE; 2292 } 2293 } 2294 } else { 2295 rx_msg_p->cur_usage_cnt++; 2296 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 2297 buffer_free = B_TRUE; 2298 } 2299 } 2300 2301 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2302 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 2303 msg_index, l2_len, 2304 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 2305 2306 if ((error_type) || (dcf_err)) { 2307 rdc_stats->ierrors++; 2308 if (dcf_err) { 2309 rdc_stats->dcf_err++; 2310 #ifdef NXGE_DEBUG 2311 if (!rdc_stats->dcf_err) { 2312 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2313 "nxge_receive_packet: channel %d dcf_err rcr" 2314 " 0x%llx", channel, rcr_entry)); 2315 } 2316 #endif 2317 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2318 NXGE_FM_EREPORT_RDMC_DCF_ERR); 2319 } else { 2320 /* Update error stats */ 2321 error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2322 rdc_stats->errlog.compl_err_type = error_type; 2323 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 2324 NXGE_FM_EREPORT_RDMC_COMPLETION_ERR); 2325 2326 switch (error_type) { 2327 case RCR_L2_ERROR: 2328 rdc_stats->l2_err++; 2329 if (rdc_stats->l2_err < 2330 error_disp_cnt) 2331 NXGE_ERROR_MSG((nxgep, 2332 NXGE_ERR_CTL, 2333 " nxge_receive_packet:" 2334 " channel %d RCR L2_ERROR", 2335 channel)); 2336 break; 2337 case RCR_L4_CSUM_ERROR: 2338 error_send_up = B_TRUE; 2339 rdc_stats->l4_cksum_err++; 2340 if (rdc_stats->l4_cksum_err < 2341 error_disp_cnt) 2342 NXGE_ERROR_MSG((nxgep, 2343 NXGE_ERR_CTL, 2344 " nxge_receive_packet:" 2345 " channel %d" 2346 " RCR L4_CSUM_ERROR", 2347 channel)); 2348 break; 2349 case RCR_FFLP_SOFT_ERROR: 2350 error_send_up = B_TRUE; 2351 rdc_stats->fflp_soft_err++; 2352 if (rdc_stats->fflp_soft_err < 2353 error_disp_cnt) 2354 NXGE_ERROR_MSG((nxgep, 2355 NXGE_ERR_CTL, 2356 " nxge_receive_packet:" 2357 " channel %d" 2358 " RCR FFLP_SOFT_ERROR", 2359 channel)); 2360 break; 2361 case RCR_ZCP_SOFT_ERROR: 2362 error_send_up = B_TRUE; 2363 rdc_stats->fflp_soft_err++; 2364 if (rdc_stats->zcp_soft_err < 2365 error_disp_cnt) 2366 NXGE_ERROR_MSG((nxgep, 2367 NXGE_ERR_CTL, 2368 " nxge_receive_packet:" 2369 " Channel %d" 2370 " RCR ZCP_SOFT_ERROR", 2371 channel)); 2372 break; 2373 default: 2374 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2375 " nxge_receive_packet:" 2376 " Channel %d" 2377 " RCR entry 0x%llx" 2378 " error 0x%x", 2379 rcr_entry, channel, 2380 error_type)); 2381 break; 2382 } 2383 } 2384 2385 /* 2386 * Update and repost buffer block if max usage 2387 * count is reached. 2388 */ 2389 if (error_send_up == B_FALSE) { 2390 if (buffer_free == B_TRUE) { 2391 rx_msg_p->free = B_TRUE; 2392 } 2393 2394 atomic_inc_32(&rx_msg_p->ref_cnt); 2395 MUTEX_EXIT(&rx_rbr_p->lock); 2396 MUTEX_EXIT(&rcr_p->lock); 2397 nxge_freeb(rx_msg_p); 2398 return; 2399 } 2400 } 2401 2402 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2403 "==> nxge_receive_packet: DMA sync second ")); 2404 2405 skip_len = sw_offset_bytes + hdr_size; 2406 if (!rx_msg_p->rx_use_bcopy) { 2407 nmp = nxge_dupb(rx_msg_p, buf_offset, bsize); 2408 } else { 2409 nmp = nxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, l2_len); 2410 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2411 "==> nxge_receive_packet: use bcopy " 2412 "rbr consumed %d " 2413 "pktbufsz_type %d " 2414 "offset %d " 2415 "hdr_size %d l2_len %d " 2416 "nmp->b_rptr $%p", 2417 rx_rbr_p->rbr_consumed, 2418 pktbufsz_type, 2419 buf_offset, hdr_size, l2_len, 2420 nmp->b_rptr)); 2421 } 2422 if (nmp != NULL) { 2423 pktbufsz = nxge_get_pktbuf_size(nxgep, pktbufsz_type, 2424 rx_rbr_p->rbr_cfgb); 2425 if (!rx_msg_p->rx_use_bcopy) { 2426 if (first_entry) { 2427 bytes_read = 0; 2428 nmp->b_rptr = &nmp->b_rptr[skip_len]; 2429 if (l2_len > pktbufsz - skip_len) 2430 nmp->b_wptr = &nmp->b_rptr[pktbufsz 2431 - skip_len]; 2432 else 2433 nmp->b_wptr = &nmp->b_rptr[l2_len]; 2434 } else { 2435 if (l2_len - bytes_read > pktbufsz) 2436 nmp->b_wptr = &nmp->b_rptr[pktbufsz]; 2437 else 2438 nmp->b_wptr = 2439 &nmp->b_rptr[l2_len - bytes_read]; 2440 } 2441 bytes_read += nmp->b_wptr - nmp->b_rptr; 2442 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2443 "==> nxge_receive_packet after dupb: " 2444 "rbr consumed %d " 2445 "pktbufsz_type %d " 2446 "nmp $%p rptr $%p wptr $%p " 2447 "buf_offset %d bzise %d l2_len %d skip_len %d", 2448 rx_rbr_p->rbr_consumed, 2449 pktbufsz_type, 2450 nmp, nmp->b_rptr, nmp->b_wptr, 2451 buf_offset, bsize, l2_len, skip_len)); 2452 } 2453 } else { 2454 cmn_err(CE_WARN, "!nxge_receive_packet: " 2455 "update stats (error)"); 2456 } 2457 if (buffer_free == B_TRUE) { 2458 rx_msg_p->free = B_TRUE; 2459 } 2460 2461 /* 2462 * ERROR, FRAG and PKT_TYPE are only reported 2463 * in the first entry. 2464 * If a packet is not fragmented and no error bit is set, then 2465 * L4 checksum is OK. 2466 */ 2467 is_valid = (nmp != NULL); 2468 rdc_stats->ibytes += l2_len; 2469 rdc_stats->ipackets++; 2470 MUTEX_EXIT(&rx_rbr_p->lock); 2471 MUTEX_EXIT(&rcr_p->lock); 2472 2473 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 2474 atomic_inc_32(&rx_msg_p->ref_cnt); 2475 atomic_inc_32(&nxge_mblks_pending); 2476 nxge_freeb(rx_msg_p); 2477 } 2478 2479 if (is_valid) { 2480 nmp->b_cont = NULL; 2481 if (first_entry) { 2482 *mp = nmp; 2483 *mp_cont = NULL; 2484 } else 2485 *mp_cont = nmp; 2486 } 2487 2488 /* 2489 * Update stats and hardware checksuming. 2490 */ 2491 if (is_valid && !multi) { 2492 2493 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 2494 pkt_type == RCR_PKT_IS_UDP) ? 2495 B_TRUE: B_FALSE); 2496 2497 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_receive_packet: " 2498 "is_valid 0x%x multi 0x%llx pkt %d frag %d error %d", 2499 is_valid, multi, is_tcp_udp, frag, error_type)); 2500 2501 if (is_tcp_udp && !frag && !error_type) { 2502 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 2503 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 2504 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2505 "==> nxge_receive_packet: Full tcp/udp cksum " 2506 "is_valid 0x%x multi 0x%llx pkt %d frag %d " 2507 "error %d", 2508 is_valid, multi, is_tcp_udp, frag, error_type)); 2509 } 2510 } 2511 2512 NXGE_DEBUG_MSG((nxgep, RX2_CTL, 2513 "==> nxge_receive_packet: *mp 0x%016llx", *mp)); 2514 2515 *multi_p = (multi == RCR_MULTI_MASK); 2516 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_receive_packet: " 2517 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 2518 *multi_p, nmp, *mp, *mp_cont)); 2519 } 2520 2521 /*ARGSUSED*/ 2522 static nxge_status_t 2523 nxge_rx_err_evnts(p_nxge_t nxgep, uint_t index, p_nxge_ldv_t ldvp, 2524 rx_dma_ctl_stat_t cs) 2525 { 2526 p_nxge_rx_ring_stats_t rdc_stats; 2527 npi_handle_t handle; 2528 npi_status_t rs; 2529 boolean_t rxchan_fatal = B_FALSE; 2530 boolean_t rxport_fatal = B_FALSE; 2531 uint8_t channel; 2532 uint8_t portn; 2533 nxge_status_t status = NXGE_OK; 2534 uint32_t error_disp_cnt = NXGE_ERROR_SHOW_MAX; 2535 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_err_evnts")); 2536 2537 handle = NXGE_DEV_NPI_HANDLE(nxgep); 2538 channel = ldvp->channel; 2539 portn = nxgep->mac.portnum; 2540 rdc_stats = &nxgep->statsp->rdc_stats[ldvp->vdma_index]; 2541 2542 if (cs.bits.hdw.rbr_tmout) { 2543 rdc_stats->rx_rbr_tmout++; 2544 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2545 NXGE_FM_EREPORT_RDMC_RBR_TMOUT); 2546 rxchan_fatal = B_TRUE; 2547 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2548 "==> nxge_rx_err_evnts: rx_rbr_timeout")); 2549 } 2550 if (cs.bits.hdw.rsp_cnt_err) { 2551 rdc_stats->rsp_cnt_err++; 2552 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2553 NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR); 2554 rxchan_fatal = B_TRUE; 2555 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2556 "==> nxge_rx_err_evnts(channel %d): " 2557 "rsp_cnt_err", channel)); 2558 } 2559 if (cs.bits.hdw.byte_en_bus) { 2560 rdc_stats->byte_en_bus++; 2561 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2562 NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS); 2563 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2564 "==> nxge_rx_err_evnts(channel %d): " 2565 "fatal error: byte_en_bus", channel)); 2566 rxchan_fatal = B_TRUE; 2567 } 2568 if (cs.bits.hdw.rsp_dat_err) { 2569 rdc_stats->rsp_dat_err++; 2570 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2571 NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR); 2572 rxchan_fatal = B_TRUE; 2573 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2574 "==> nxge_rx_err_evnts(channel %d): " 2575 "fatal error: rsp_dat_err", channel)); 2576 } 2577 if (cs.bits.hdw.rcr_ack_err) { 2578 rdc_stats->rcr_ack_err++; 2579 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2580 NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR); 2581 rxchan_fatal = B_TRUE; 2582 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2583 "==> nxge_rx_err_evnts(channel %d): " 2584 "fatal error: rcr_ack_err", channel)); 2585 } 2586 if (cs.bits.hdw.dc_fifo_err) { 2587 rdc_stats->dc_fifo_err++; 2588 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2589 NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR); 2590 /* This is not a fatal error! */ 2591 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2592 "==> nxge_rx_err_evnts(channel %d): " 2593 "dc_fifo_err", channel)); 2594 rxport_fatal = B_TRUE; 2595 } 2596 if ((cs.bits.hdw.rcr_sha_par) || (cs.bits.hdw.rbr_pre_par)) { 2597 if ((rs = npi_rxdma_ring_perr_stat_get(handle, 2598 &rdc_stats->errlog.pre_par, 2599 &rdc_stats->errlog.sha_par)) 2600 != NPI_SUCCESS) { 2601 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2602 "==> nxge_rx_err_evnts(channel %d): " 2603 "rcr_sha_par: get perr", channel)); 2604 return (NXGE_ERROR | rs); 2605 } 2606 if (cs.bits.hdw.rcr_sha_par) { 2607 rdc_stats->rcr_sha_par++; 2608 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2609 NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 2610 rxchan_fatal = B_TRUE; 2611 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2612 "==> nxge_rx_err_evnts(channel %d): " 2613 "fatal error: rcr_sha_par", channel)); 2614 } 2615 if (cs.bits.hdw.rbr_pre_par) { 2616 rdc_stats->rbr_pre_par++; 2617 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2618 NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 2619 rxchan_fatal = B_TRUE; 2620 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2621 "==> nxge_rx_err_evnts(channel %d): " 2622 "fatal error: rbr_pre_par", channel)); 2623 } 2624 } 2625 if (cs.bits.hdw.port_drop_pkt) { 2626 rdc_stats->port_drop_pkt++; 2627 if (rdc_stats->port_drop_pkt < error_disp_cnt) 2628 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2629 "==> nxge_rx_err_evnts (channel %d): " 2630 "port_drop_pkt", channel)); 2631 } 2632 if (cs.bits.hdw.wred_drop) { 2633 rdc_stats->wred_drop++; 2634 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 2635 "==> nxge_rx_err_evnts(channel %d): " 2636 "wred_drop", channel)); 2637 } 2638 if (cs.bits.hdw.rbr_pre_empty) { 2639 rdc_stats->rbr_pre_empty++; 2640 if (rdc_stats->rbr_pre_empty < error_disp_cnt) 2641 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2642 "==> nxge_rx_err_evnts(channel %d): " 2643 "rbr_pre_empty", channel)); 2644 } 2645 if (cs.bits.hdw.rcr_shadow_full) { 2646 rdc_stats->rcr_shadow_full++; 2647 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2648 "==> nxge_rx_err_evnts(channel %d): " 2649 "rcr_shadow_full", channel)); 2650 } 2651 if (cs.bits.hdw.config_err) { 2652 rdc_stats->config_err++; 2653 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2654 NXGE_FM_EREPORT_RDMC_CONFIG_ERR); 2655 rxchan_fatal = B_TRUE; 2656 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2657 "==> nxge_rx_err_evnts(channel %d): " 2658 "config error", channel)); 2659 } 2660 if (cs.bits.hdw.rcrincon) { 2661 rdc_stats->rcrincon++; 2662 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2663 NXGE_FM_EREPORT_RDMC_RCRINCON); 2664 rxchan_fatal = B_TRUE; 2665 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2666 "==> nxge_rx_err_evnts(channel %d): " 2667 "fatal error: rcrincon error", channel)); 2668 } 2669 if (cs.bits.hdw.rcrfull) { 2670 rdc_stats->rcrfull++; 2671 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2672 NXGE_FM_EREPORT_RDMC_RCRFULL); 2673 rxchan_fatal = B_TRUE; 2674 if (rdc_stats->rcrfull < error_disp_cnt) 2675 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2676 "==> nxge_rx_err_evnts(channel %d): " 2677 "fatal error: rcrfull error", channel)); 2678 } 2679 if (cs.bits.hdw.rbr_empty) { 2680 rdc_stats->rbr_empty++; 2681 if (rdc_stats->rbr_empty < error_disp_cnt) 2682 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2683 "==> nxge_rx_err_evnts(channel %d): " 2684 "rbr empty error", channel)); 2685 } 2686 if (cs.bits.hdw.rbrfull) { 2687 rdc_stats->rbrfull++; 2688 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2689 NXGE_FM_EREPORT_RDMC_RBRFULL); 2690 rxchan_fatal = B_TRUE; 2691 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2692 "==> nxge_rx_err_evnts(channel %d): " 2693 "fatal error: rbr_full error", channel)); 2694 } 2695 if (cs.bits.hdw.rbrlogpage) { 2696 rdc_stats->rbrlogpage++; 2697 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2698 NXGE_FM_EREPORT_RDMC_RBRLOGPAGE); 2699 rxchan_fatal = B_TRUE; 2700 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2701 "==> nxge_rx_err_evnts(channel %d): " 2702 "fatal error: rbr logical page error", channel)); 2703 } 2704 if (cs.bits.hdw.cfiglogpage) { 2705 rdc_stats->cfiglogpage++; 2706 NXGE_FM_REPORT_ERROR(nxgep, portn, channel, 2707 NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE); 2708 rxchan_fatal = B_TRUE; 2709 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2710 "==> nxge_rx_err_evnts(channel %d): " 2711 "fatal error: cfig logical page error", channel)); 2712 } 2713 2714 if (rxport_fatal) { 2715 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2716 " nxge_rx_err_evnts: " 2717 " fatal error on Port #%d\n", 2718 portn)); 2719 status = nxge_ipp_fatal_err_recover(nxgep); 2720 if (status == NXGE_OK) { 2721 FM_SERVICE_RESTORED(nxgep); 2722 } 2723 } 2724 2725 if (rxchan_fatal) { 2726 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2727 " nxge_rx_err_evnts: " 2728 " fatal error on Channel #%d\n", 2729 channel)); 2730 status = nxge_rxdma_fatal_err_recover(nxgep, channel); 2731 if (status == NXGE_OK) { 2732 FM_SERVICE_RESTORED(nxgep); 2733 } 2734 } 2735 2736 NXGE_DEBUG_MSG((nxgep, RX2_CTL, "<== nxge_rx_err_evnts")); 2737 2738 return (status); 2739 } 2740 2741 static nxge_status_t 2742 nxge_map_rxdma(p_nxge_t nxgep) 2743 { 2744 int i, ndmas; 2745 uint16_t channel; 2746 p_rx_rbr_rings_t rx_rbr_rings; 2747 p_rx_rbr_ring_t *rbr_rings; 2748 p_rx_rcr_rings_t rx_rcr_rings; 2749 p_rx_rcr_ring_t *rcr_rings; 2750 p_rx_mbox_areas_t rx_mbox_areas_p; 2751 p_rx_mbox_t *rx_mbox_p; 2752 p_nxge_dma_pool_t dma_buf_poolp; 2753 p_nxge_dma_pool_t dma_cntl_poolp; 2754 p_nxge_dma_common_t *dma_buf_p; 2755 p_nxge_dma_common_t *dma_cntl_p; 2756 uint32_t *num_chunks; 2757 nxge_status_t status = NXGE_OK; 2758 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2759 p_nxge_dma_common_t t_dma_buf_p; 2760 p_nxge_dma_common_t t_dma_cntl_p; 2761 #endif 2762 2763 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_map_rxdma")); 2764 2765 dma_buf_poolp = nxgep->rx_buf_pool_p; 2766 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 2767 2768 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2769 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2770 "<== nxge_map_rxdma: buf not allocated")); 2771 return (NXGE_ERROR); 2772 } 2773 2774 ndmas = dma_buf_poolp->ndmas; 2775 if (!ndmas) { 2776 NXGE_DEBUG_MSG((nxgep, RX_CTL, 2777 "<== nxge_map_rxdma: no dma allocated")); 2778 return (NXGE_ERROR); 2779 } 2780 2781 num_chunks = dma_buf_poolp->num_chunks; 2782 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2783 dma_cntl_p = dma_cntl_poolp->dma_buf_pool_p; 2784 2785 rx_rbr_rings = (p_rx_rbr_rings_t) 2786 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2787 rbr_rings = (p_rx_rbr_ring_t *) 2788 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2789 rx_rcr_rings = (p_rx_rcr_rings_t) 2790 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2791 rcr_rings = (p_rx_rcr_ring_t *) 2792 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2793 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2794 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2795 rx_mbox_p = (p_rx_mbox_t *) 2796 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2797 2798 /* 2799 * Timeout should be set based on the system clock divider. 2800 * The following timeout value of 1 assumes that the 2801 * granularity (1000) is 3 microseconds running at 300MHz. 2802 */ 2803 2804 nxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2805 nxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2806 2807 /* 2808 * Map descriptors from the buffer polls for each dam channel. 2809 */ 2810 for (i = 0; i < ndmas; i++) { 2811 /* 2812 * Set up and prepare buffer blocks, descriptors 2813 * and mailbox. 2814 */ 2815 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2816 status = nxge_map_rxdma_channel(nxgep, channel, 2817 (p_nxge_dma_common_t *)&dma_buf_p[i], 2818 (p_rx_rbr_ring_t *)&rbr_rings[i], 2819 num_chunks[i], 2820 (p_nxge_dma_common_t *)&dma_cntl_p[i], 2821 (p_rx_rcr_ring_t *)&rcr_rings[i], 2822 (p_rx_mbox_t *)&rx_mbox_p[i]); 2823 if (status != NXGE_OK) { 2824 goto nxge_map_rxdma_fail1; 2825 } 2826 rbr_rings[i]->index = (uint16_t)i; 2827 rcr_rings[i]->index = (uint16_t)i; 2828 rcr_rings[i]->rdc_stats = &nxgep->statsp->rdc_stats[i]; 2829 2830 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2831 if (nxgep->niu_type == N2_NIU && NXGE_DMA_BLOCK == 1) { 2832 rbr_rings[i]->hv_set = B_FALSE; 2833 t_dma_buf_p = (p_nxge_dma_common_t)dma_buf_p[i]; 2834 t_dma_cntl_p = 2835 (p_nxge_dma_common_t)dma_cntl_p[i]; 2836 2837 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp = 2838 (uint64_t)t_dma_buf_p->orig_ioaddr_pp; 2839 rbr_rings[i]->hv_rx_buf_ioaddr_size = 2840 (uint64_t)t_dma_buf_p->orig_alength; 2841 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2842 "==> nxge_map_rxdma_channel: " 2843 "channel %d " 2844 "data buf base io $%p ($%p) " 2845 "size 0x%llx (%d 0x%x)", 2846 channel, 2847 rbr_rings[i]->hv_rx_buf_base_ioaddr_pp, 2848 t_dma_cntl_p->ioaddr_pp, 2849 rbr_rings[i]->hv_rx_buf_ioaddr_size, 2850 t_dma_buf_p->orig_alength, 2851 t_dma_buf_p->orig_alength)); 2852 2853 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp = 2854 (uint64_t)t_dma_cntl_p->orig_ioaddr_pp; 2855 rbr_rings[i]->hv_rx_cntl_ioaddr_size = 2856 (uint64_t)t_dma_cntl_p->orig_alength; 2857 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2858 "==> nxge_map_rxdma_channel: " 2859 "channel %d " 2860 "cntl base io $%p ($%p) " 2861 "size 0x%llx (%d 0x%x)", 2862 channel, 2863 rbr_rings[i]->hv_rx_cntl_base_ioaddr_pp, 2864 t_dma_cntl_p->ioaddr_pp, 2865 rbr_rings[i]->hv_rx_cntl_ioaddr_size, 2866 t_dma_cntl_p->orig_alength, 2867 t_dma_cntl_p->orig_alength)); 2868 } 2869 2870 #endif /* sun4v and NIU_LP_WORKAROUND */ 2871 } 2872 2873 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2874 rx_rbr_rings->rbr_rings = rbr_rings; 2875 nxgep->rx_rbr_rings = rx_rbr_rings; 2876 rx_rcr_rings->rcr_rings = rcr_rings; 2877 nxgep->rx_rcr_rings = rx_rcr_rings; 2878 2879 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2880 nxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2881 2882 goto nxge_map_rxdma_exit; 2883 2884 nxge_map_rxdma_fail1: 2885 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2886 "==> nxge_map_rxdma: unmap rbr,rcr " 2887 "(status 0x%x channel %d i %d)", 2888 status, channel, i)); 2889 i--; 2890 for (; i >= 0; i--) { 2891 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2892 nxge_unmap_rxdma_channel(nxgep, channel, 2893 rbr_rings[i], 2894 rcr_rings[i], 2895 rx_mbox_p[i]); 2896 } 2897 2898 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2899 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2900 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2901 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2902 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2903 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2904 2905 nxge_map_rxdma_exit: 2906 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2907 "<== nxge_map_rxdma: " 2908 "(status 0x%x channel %d)", 2909 status, channel)); 2910 2911 return (status); 2912 } 2913 2914 static void 2915 nxge_unmap_rxdma(p_nxge_t nxgep) 2916 { 2917 int i, ndmas; 2918 uint16_t channel; 2919 p_rx_rbr_rings_t rx_rbr_rings; 2920 p_rx_rbr_ring_t *rbr_rings; 2921 p_rx_rcr_rings_t rx_rcr_rings; 2922 p_rx_rcr_ring_t *rcr_rings; 2923 p_rx_mbox_areas_t rx_mbox_areas_p; 2924 p_rx_mbox_t *rx_mbox_p; 2925 p_nxge_dma_pool_t dma_buf_poolp; 2926 p_nxge_dma_pool_t dma_cntl_poolp; 2927 p_nxge_dma_common_t *dma_buf_p; 2928 2929 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_unmap_rxdma")); 2930 2931 dma_buf_poolp = nxgep->rx_buf_pool_p; 2932 dma_cntl_poolp = nxgep->rx_cntl_pool_p; 2933 2934 if (!dma_buf_poolp->buf_allocated || !dma_cntl_poolp->buf_allocated) { 2935 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2936 "<== nxge_unmap_rxdma: NULL buf pointers")); 2937 return; 2938 } 2939 2940 rx_rbr_rings = nxgep->rx_rbr_rings; 2941 rx_rcr_rings = nxgep->rx_rcr_rings; 2942 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2943 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2944 "<== nxge_unmap_rxdma: NULL ring pointers")); 2945 return; 2946 } 2947 ndmas = rx_rbr_rings->ndmas; 2948 if (!ndmas) { 2949 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2950 "<== nxge_unmap_rxdma: no channel")); 2951 return; 2952 } 2953 2954 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2955 "==> nxge_unmap_rxdma (ndmas %d)", ndmas)); 2956 rbr_rings = rx_rbr_rings->rbr_rings; 2957 rcr_rings = rx_rcr_rings->rcr_rings; 2958 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 2959 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2960 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2961 2962 for (i = 0; i < ndmas; i++) { 2963 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 2964 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2965 "==> nxge_unmap_rxdma (ndmas %d) channel %d", 2966 ndmas, channel)); 2967 (void) nxge_unmap_rxdma_channel(nxgep, channel, 2968 (p_rx_rbr_ring_t)rbr_rings[i], 2969 (p_rx_rcr_ring_t)rcr_rings[i], 2970 (p_rx_mbox_t)rx_mbox_p[i]); 2971 } 2972 2973 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2974 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2975 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2976 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2977 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2978 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2979 2980 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2981 "<== nxge_unmap_rxdma")); 2982 } 2983 2984 nxge_status_t 2985 nxge_map_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 2986 p_nxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2987 uint32_t num_chunks, 2988 p_nxge_dma_common_t *dma_cntl_p, p_rx_rcr_ring_t *rcr_p, 2989 p_rx_mbox_t *rx_mbox_p) 2990 { 2991 int status = NXGE_OK; 2992 2993 /* 2994 * Set up and prepare buffer blocks, descriptors 2995 * and mailbox. 2996 */ 2997 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2998 "==> nxge_map_rxdma_channel (channel %d)", channel)); 2999 /* 3000 * Receive buffer blocks 3001 */ 3002 status = nxge_map_rxdma_channel_buf_ring(nxgep, channel, 3003 dma_buf_p, rbr_p, num_chunks); 3004 if (status != NXGE_OK) { 3005 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3006 "==> nxge_map_rxdma_channel (channel %d): " 3007 "map buffer failed 0x%x", channel, status)); 3008 goto nxge_map_rxdma_channel_exit; 3009 } 3010 3011 /* 3012 * Receive block ring, completion ring and mailbox. 3013 */ 3014 status = nxge_map_rxdma_channel_cfg_ring(nxgep, channel, 3015 dma_cntl_p, rbr_p, rcr_p, rx_mbox_p); 3016 if (status != NXGE_OK) { 3017 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3018 "==> nxge_map_rxdma_channel (channel %d): " 3019 "map config failed 0x%x", channel, status)); 3020 goto nxge_map_rxdma_channel_fail2; 3021 } 3022 3023 goto nxge_map_rxdma_channel_exit; 3024 3025 nxge_map_rxdma_channel_fail3: 3026 /* Free rbr, rcr */ 3027 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3028 "==> nxge_map_rxdma_channel: free rbr/rcr " 3029 "(status 0x%x channel %d)", 3030 status, channel)); 3031 nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3032 *rcr_p, *rx_mbox_p); 3033 3034 nxge_map_rxdma_channel_fail2: 3035 /* Free buffer blocks */ 3036 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3037 "==> nxge_map_rxdma_channel: free rx buffers" 3038 "(nxgep 0x%x status 0x%x channel %d)", 3039 nxgep, status, channel)); 3040 nxge_unmap_rxdma_channel_buf_ring(nxgep, *rbr_p); 3041 3042 status = NXGE_ERROR; 3043 3044 nxge_map_rxdma_channel_exit: 3045 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3046 "<== nxge_map_rxdma_channel: " 3047 "(nxgep 0x%x status 0x%x channel %d)", 3048 nxgep, status, channel)); 3049 3050 return (status); 3051 } 3052 3053 /*ARGSUSED*/ 3054 static void 3055 nxge_unmap_rxdma_channel(p_nxge_t nxgep, uint16_t channel, 3056 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3057 { 3058 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3059 "==> nxge_unmap_rxdma_channel (channel %d)", channel)); 3060 3061 /* 3062 * unmap receive block ring, completion ring and mailbox. 3063 */ 3064 (void) nxge_unmap_rxdma_channel_cfg_ring(nxgep, 3065 rcr_p, rx_mbox_p); 3066 3067 /* unmap buffer blocks */ 3068 (void) nxge_unmap_rxdma_channel_buf_ring(nxgep, rbr_p); 3069 3070 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_unmap_rxdma_channel")); 3071 } 3072 3073 /*ARGSUSED*/ 3074 static nxge_status_t 3075 nxge_map_rxdma_channel_cfg_ring(p_nxge_t nxgep, uint16_t dma_channel, 3076 p_nxge_dma_common_t *dma_cntl_p, p_rx_rbr_ring_t *rbr_p, 3077 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 3078 { 3079 p_rx_rbr_ring_t rbrp; 3080 p_rx_rcr_ring_t rcrp; 3081 p_rx_mbox_t mboxp; 3082 p_nxge_dma_common_t cntl_dmap; 3083 p_nxge_dma_common_t dmap; 3084 p_rx_msg_t *rx_msg_ring; 3085 p_rx_msg_t rx_msg_p; 3086 p_rbr_cfig_a_t rcfga_p; 3087 p_rbr_cfig_b_t rcfgb_p; 3088 p_rcrcfig_a_t cfga_p; 3089 p_rcrcfig_b_t cfgb_p; 3090 p_rxdma_cfig1_t cfig1_p; 3091 p_rxdma_cfig2_t cfig2_p; 3092 p_rbr_kick_t kick_p; 3093 uint32_t dmaaddrp; 3094 uint32_t *rbr_vaddrp; 3095 uint32_t bkaddr; 3096 nxge_status_t status = NXGE_OK; 3097 int i; 3098 uint32_t nxge_port_rcr_size; 3099 3100 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3101 "==> nxge_map_rxdma_channel_cfg_ring")); 3102 3103 cntl_dmap = *dma_cntl_p; 3104 3105 /* Map in the receive block ring */ 3106 rbrp = *rbr_p; 3107 dmap = (p_nxge_dma_common_t)&rbrp->rbr_desc; 3108 nxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 3109 /* 3110 * Zero out buffer block ring descriptors. 3111 */ 3112 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3113 3114 rcfga_p = &(rbrp->rbr_cfga); 3115 rcfgb_p = &(rbrp->rbr_cfgb); 3116 kick_p = &(rbrp->rbr_kick); 3117 rcfga_p->value = 0; 3118 rcfgb_p->value = 0; 3119 kick_p->value = 0; 3120 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 3121 rcfga_p->value = (rbrp->rbr_addr & 3122 (RBR_CFIG_A_STDADDR_MASK | 3123 RBR_CFIG_A_STDADDR_BASE_MASK)); 3124 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 3125 3126 rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0; 3127 rcfgb_p->bits.ldw.vld0 = 1; 3128 rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1; 3129 rcfgb_p->bits.ldw.vld1 = 1; 3130 rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2; 3131 rcfgb_p->bits.ldw.vld2 = 1; 3132 rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code; 3133 3134 /* 3135 * For each buffer block, enter receive block address to the ring. 3136 */ 3137 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 3138 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 3139 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3140 "==> nxge_map_rxdma_channel_cfg_ring: channel %d " 3141 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 3142 3143 rx_msg_ring = rbrp->rx_msg_ring; 3144 for (i = 0; i < rbrp->tnblocks; i++) { 3145 rx_msg_p = rx_msg_ring[i]; 3146 rx_msg_p->nxgep = nxgep; 3147 rx_msg_p->rx_rbr_p = rbrp; 3148 bkaddr = (uint32_t) 3149 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress 3150 >> RBR_BKADDR_SHIFT)); 3151 rx_msg_p->free = B_FALSE; 3152 rx_msg_p->max_usage_cnt = 0xbaddcafe; 3153 3154 *rbr_vaddrp++ = bkaddr; 3155 } 3156 3157 kick_p->bits.ldw.bkadd = rbrp->rbb_max; 3158 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3159 3160 rbrp->rbr_rd_index = 0; 3161 3162 rbrp->rbr_consumed = 0; 3163 rbrp->rbr_use_bcopy = B_TRUE; 3164 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 3165 /* 3166 * Do bcopy on packets greater than bcopy size once 3167 * the lo threshold is reached. 3168 * This lo threshold should be less than the hi threshold. 3169 * 3170 * Do bcopy on every packet once the hi threshold is reached. 3171 */ 3172 if (nxge_rx_threshold_lo >= nxge_rx_threshold_hi) { 3173 /* default it to use hi */ 3174 nxge_rx_threshold_lo = nxge_rx_threshold_hi; 3175 } 3176 3177 if (nxge_rx_buf_size_type > NXGE_RBR_TYPE2) { 3178 nxge_rx_buf_size_type = NXGE_RBR_TYPE2; 3179 } 3180 rbrp->rbr_bufsize_type = nxge_rx_buf_size_type; 3181 3182 switch (nxge_rx_threshold_hi) { 3183 default: 3184 case NXGE_RX_COPY_NONE: 3185 /* Do not do bcopy at all */ 3186 rbrp->rbr_use_bcopy = B_FALSE; 3187 rbrp->rbr_threshold_hi = rbrp->rbb_max; 3188 break; 3189 3190 case NXGE_RX_COPY_1: 3191 case NXGE_RX_COPY_2: 3192 case NXGE_RX_COPY_3: 3193 case NXGE_RX_COPY_4: 3194 case NXGE_RX_COPY_5: 3195 case NXGE_RX_COPY_6: 3196 case NXGE_RX_COPY_7: 3197 rbrp->rbr_threshold_hi = 3198 rbrp->rbb_max * 3199 (nxge_rx_threshold_hi)/NXGE_RX_BCOPY_SCALE; 3200 break; 3201 3202 case NXGE_RX_COPY_ALL: 3203 rbrp->rbr_threshold_hi = 0; 3204 break; 3205 } 3206 3207 switch (nxge_rx_threshold_lo) { 3208 default: 3209 case NXGE_RX_COPY_NONE: 3210 /* Do not do bcopy at all */ 3211 if (rbrp->rbr_use_bcopy) { 3212 rbrp->rbr_use_bcopy = B_FALSE; 3213 } 3214 rbrp->rbr_threshold_lo = rbrp->rbb_max; 3215 break; 3216 3217 case NXGE_RX_COPY_1: 3218 case NXGE_RX_COPY_2: 3219 case NXGE_RX_COPY_3: 3220 case NXGE_RX_COPY_4: 3221 case NXGE_RX_COPY_5: 3222 case NXGE_RX_COPY_6: 3223 case NXGE_RX_COPY_7: 3224 rbrp->rbr_threshold_lo = 3225 rbrp->rbb_max * 3226 (nxge_rx_threshold_lo)/NXGE_RX_BCOPY_SCALE; 3227 break; 3228 3229 case NXGE_RX_COPY_ALL: 3230 rbrp->rbr_threshold_lo = 0; 3231 break; 3232 } 3233 3234 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3235 "nxge_map_rxdma_channel_cfg_ring: channel %d " 3236 "rbb_max %d " 3237 "rbrp->rbr_bufsize_type %d " 3238 "rbb_threshold_hi %d " 3239 "rbb_threshold_lo %d", 3240 dma_channel, 3241 rbrp->rbb_max, 3242 rbrp->rbr_bufsize_type, 3243 rbrp->rbr_threshold_hi, 3244 rbrp->rbr_threshold_lo)); 3245 3246 rbrp->page_valid.value = 0; 3247 rbrp->page_mask_1.value = rbrp->page_mask_2.value = 0; 3248 rbrp->page_value_1.value = rbrp->page_value_2.value = 0; 3249 rbrp->page_reloc_1.value = rbrp->page_reloc_2.value = 0; 3250 rbrp->page_hdl.value = 0; 3251 3252 rbrp->page_valid.bits.ldw.page0 = 1; 3253 rbrp->page_valid.bits.ldw.page1 = 1; 3254 3255 /* Map in the receive completion ring */ 3256 rcrp = (p_rx_rcr_ring_t) 3257 KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 3258 rcrp->rdc = dma_channel; 3259 3260 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 3261 rcrp->comp_size = nxge_port_rcr_size; 3262 rcrp->comp_wrap_mask = nxge_port_rcr_size - 1; 3263 3264 rcrp->max_receive_pkts = nxge_max_rx_pkts; 3265 3266 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 3267 nxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 3268 sizeof (rcr_entry_t)); 3269 rcrp->comp_rd_index = 0; 3270 rcrp->comp_wt_index = 0; 3271 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3272 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3273 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3274 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3275 3276 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3277 (nxge_port_rcr_size - 1); 3278 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3279 (nxge_port_rcr_size - 1); 3280 3281 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3282 "==> nxge_map_rxdma_channel_cfg_ring: " 3283 "channel %d " 3284 "rbr_vaddrp $%p " 3285 "rcr_desc_rd_head_p $%p " 3286 "rcr_desc_rd_head_pp $%p " 3287 "rcr_desc_rd_last_p $%p " 3288 "rcr_desc_rd_last_pp $%p ", 3289 dma_channel, 3290 rbr_vaddrp, 3291 rcrp->rcr_desc_rd_head_p, 3292 rcrp->rcr_desc_rd_head_pp, 3293 rcrp->rcr_desc_last_p, 3294 rcrp->rcr_desc_last_pp)); 3295 3296 /* 3297 * Zero out buffer block ring descriptors. 3298 */ 3299 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3300 rcrp->intr_timeout = nxgep->intr_timeout; 3301 rcrp->intr_threshold = nxgep->intr_threshold; 3302 rcrp->full_hdr_flag = B_FALSE; 3303 rcrp->sw_priv_hdr_len = 0; 3304 3305 cfga_p = &(rcrp->rcr_cfga); 3306 cfgb_p = &(rcrp->rcr_cfgb); 3307 cfga_p->value = 0; 3308 cfgb_p->value = 0; 3309 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 3310 cfga_p->value = (rcrp->rcr_addr & 3311 (RCRCFIG_A_STADDR_MASK | 3312 RCRCFIG_A_STADDR_BASE_MASK)); 3313 3314 rcfga_p->value |= ((uint64_t)rcrp->comp_size << 3315 RCRCFIG_A_LEN_SHIF); 3316 3317 /* 3318 * Timeout should be set based on the system clock divider. 3319 * The following timeout value of 1 assumes that the 3320 * granularity (1000) is 3 microseconds running at 300MHz. 3321 */ 3322 cfgb_p->bits.ldw.pthres = rcrp->intr_threshold; 3323 cfgb_p->bits.ldw.timeout = rcrp->intr_timeout; 3324 cfgb_p->bits.ldw.entout = 1; 3325 3326 /* Map in the mailbox */ 3327 mboxp = (p_rx_mbox_t) 3328 KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 3329 dmap = (p_nxge_dma_common_t)&mboxp->rx_mbox; 3330 nxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 3331 cfig1_p = (p_rxdma_cfig1_t)&mboxp->rx_cfg1; 3332 cfig2_p = (p_rxdma_cfig2_t)&mboxp->rx_cfg2; 3333 cfig1_p->value = cfig2_p->value = 0; 3334 3335 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 3336 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3337 "==> nxge_map_rxdma_channel_cfg_ring: " 3338 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 3339 dma_channel, cfig1_p->value, cfig2_p->value, 3340 mboxp->mbox_addr)); 3341 3342 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress >> 32 3343 & 0xfff); 3344 cfig1_p->bits.ldw.mbaddr_h = dmaaddrp; 3345 3346 3347 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 3348 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 3349 RXDMA_CFIG2_MBADDR_L_MASK); 3350 3351 cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 3352 3353 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3354 "==> nxge_map_rxdma_channel_cfg_ring: " 3355 "channel %d damaddrp $%p " 3356 "cfg1 0x%016llx cfig2 0x%016llx", 3357 dma_channel, dmaaddrp, 3358 cfig1_p->value, cfig2_p->value)); 3359 3360 cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag; 3361 cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len; 3362 3363 rbrp->rx_rcr_p = rcrp; 3364 rcrp->rx_rbr_p = rbrp; 3365 *rcr_p = rcrp; 3366 *rx_mbox_p = mboxp; 3367 3368 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3369 "<== nxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 3370 3371 return (status); 3372 } 3373 3374 /*ARGSUSED*/ 3375 static void 3376 nxge_unmap_rxdma_channel_cfg_ring(p_nxge_t nxgep, 3377 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 3378 { 3379 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3380 "==> nxge_unmap_rxdma_channel_cfg_ring: channel %d", 3381 rcr_p->rdc)); 3382 3383 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 3384 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 3385 3386 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3387 "<== nxge_unmap_rxdma_channel_cfg_ring")); 3388 } 3389 3390 static nxge_status_t 3391 nxge_map_rxdma_channel_buf_ring(p_nxge_t nxgep, uint16_t channel, 3392 p_nxge_dma_common_t *dma_buf_p, 3393 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 3394 { 3395 p_rx_rbr_ring_t rbrp; 3396 p_nxge_dma_common_t dma_bufp, tmp_bufp; 3397 p_rx_msg_t *rx_msg_ring; 3398 p_rx_msg_t rx_msg_p; 3399 p_mblk_t mblk_p; 3400 3401 rxring_info_t *ring_info; 3402 nxge_status_t status = NXGE_OK; 3403 int i, j, index; 3404 uint32_t size, bsize, nblocks, nmsgs; 3405 3406 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3407 "==> nxge_map_rxdma_channel_buf_ring: channel %d", 3408 channel)); 3409 3410 dma_bufp = tmp_bufp = *dma_buf_p; 3411 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3412 " nxge_map_rxdma_channel_buf_ring: channel %d to map %d " 3413 "chunks bufp 0x%016llx", 3414 channel, num_chunks, dma_bufp)); 3415 3416 nmsgs = 0; 3417 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 3418 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3419 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3420 "bufp 0x%016llx nblocks %d nmsgs %d", 3421 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 3422 nmsgs += tmp_bufp->nblocks; 3423 } 3424 if (!nmsgs) { 3425 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3426 "<== nxge_map_rxdma_channel_buf_ring: channel %d " 3427 "no msg blocks", 3428 channel)); 3429 status = NXGE_ERROR; 3430 goto nxge_map_rxdma_channel_buf_ring_exit; 3431 } 3432 3433 rbrp = (p_rx_rbr_ring_t) 3434 KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 3435 3436 size = nmsgs * sizeof (p_rx_msg_t); 3437 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 3438 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 3439 KM_SLEEP); 3440 3441 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 3442 (void *)nxgep->interrupt_cookie); 3443 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 3444 (void *)nxgep->interrupt_cookie); 3445 rbrp->rdc = channel; 3446 rbrp->num_blocks = num_chunks; 3447 rbrp->tnblocks = nmsgs; 3448 rbrp->rbb_max = nmsgs; 3449 rbrp->rbr_max_size = nmsgs; 3450 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 3451 3452 /* 3453 * Buffer sizes suggested by NIU architect. 3454 * 256, 512 and 2K. 3455 */ 3456 3457 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 3458 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 3459 rbrp->npi_pkt_buf_size0 = SIZE_256B; 3460 3461 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 3462 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 3463 rbrp->npi_pkt_buf_size1 = SIZE_1KB; 3464 3465 rbrp->block_size = nxgep->rx_default_block_size; 3466 3467 if (!nxge_jumbo_enable && !nxgep->param_arr[param_accept_jumbo].value) { 3468 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 3469 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 3470 rbrp->npi_pkt_buf_size2 = SIZE_2KB; 3471 } else { 3472 if (rbrp->block_size >= 0x2000) { 3473 rbrp->pkt_buf_size2 = RBR_BUFSZ2_8K; 3474 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_8K_BYTES; 3475 rbrp->npi_pkt_buf_size2 = SIZE_8KB; 3476 } else { 3477 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 3478 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 3479 rbrp->npi_pkt_buf_size2 = SIZE_4KB; 3480 } 3481 } 3482 3483 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3484 "==> nxge_map_rxdma_channel_buf_ring: channel %d " 3485 "actual rbr max %d rbb_max %d nmsgs %d " 3486 "rbrp->block_size %d default_block_size %d " 3487 "(config nxge_rbr_size %d nxge_rbr_spare_size %d)", 3488 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 3489 rbrp->block_size, nxgep->rx_default_block_size, 3490 nxge_rbr_size, nxge_rbr_spare_size)); 3491 3492 /* Map in buffers from the buffer pool. */ 3493 index = 0; 3494 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 3495 bsize = dma_bufp->block_size; 3496 nblocks = dma_bufp->nblocks; 3497 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 3498 ring_info->buffer[i].buf_index = i; 3499 ring_info->buffer[i].buf_size = dma_bufp->alength; 3500 ring_info->buffer[i].start_index = index; 3501 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 3502 3503 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3504 " nxge_map_rxdma_channel_buf_ring: map channel %d " 3505 "chunk %d" 3506 " nblocks %d chunk_size %x block_size 0x%x " 3507 "dma_bufp $%p", channel, i, 3508 dma_bufp->nblocks, ring_info->buffer[i].buf_size, bsize, 3509 dma_bufp)); 3510 3511 for (j = 0; j < nblocks; j++) { 3512 if ((rx_msg_p = nxge_allocb(bsize, BPRI_LO, 3513 dma_bufp)) == NULL) { 3514 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3515 "allocb failed (index %d i %d j %d)", 3516 index, i, j)); 3517 goto nxge_map_rxdma_channel_buf_ring_fail1; 3518 } 3519 rx_msg_ring[index] = rx_msg_p; 3520 rx_msg_p->block_index = index; 3521 rx_msg_p->shifted_addr = (uint32_t) 3522 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 3523 RBR_BKADDR_SHIFT)); 3524 3525 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3526 "index %d j %d rx_msg_p $%p mblk %p", 3527 index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 3528 3529 mblk_p = rx_msg_p->rx_mblk_p; 3530 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 3531 index++; 3532 rx_msg_p->buf_dma.dma_channel = channel; 3533 } 3534 } 3535 if (i < rbrp->num_blocks) { 3536 goto nxge_map_rxdma_channel_buf_ring_fail1; 3537 } 3538 3539 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3540 "nxge_map_rxdma_channel_buf_ring: done buf init " 3541 "channel %d msg block entries %d", 3542 channel, index)); 3543 ring_info->block_size_mask = bsize - 1; 3544 rbrp->rx_msg_ring = rx_msg_ring; 3545 rbrp->dma_bufp = dma_buf_p; 3546 rbrp->ring_info = ring_info; 3547 3548 status = nxge_rxbuf_index_info_init(nxgep, rbrp); 3549 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3550 " nxge_map_rxdma_channel_buf_ring: " 3551 "channel %d done buf info init", channel)); 3552 3553 *rbr_p = rbrp; 3554 goto nxge_map_rxdma_channel_buf_ring_exit; 3555 3556 nxge_map_rxdma_channel_buf_ring_fail1: 3557 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3558 " nxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 3559 channel, status)); 3560 3561 index--; 3562 for (; index >= 0; index--) { 3563 rx_msg_p = rx_msg_ring[index]; 3564 if (rx_msg_p != NULL) { 3565 freeb(rx_msg_p->rx_mblk_p); 3566 rx_msg_ring[index] = NULL; 3567 } 3568 } 3569 nxge_map_rxdma_channel_buf_ring_fail: 3570 MUTEX_DESTROY(&rbrp->post_lock); 3571 MUTEX_DESTROY(&rbrp->lock); 3572 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3573 KMEM_FREE(rx_msg_ring, size); 3574 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 3575 3576 status = NXGE_ERROR; 3577 3578 nxge_map_rxdma_channel_buf_ring_exit: 3579 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3580 "<== nxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 3581 3582 return (status); 3583 } 3584 3585 /*ARGSUSED*/ 3586 static void 3587 nxge_unmap_rxdma_channel_buf_ring(p_nxge_t nxgep, 3588 p_rx_rbr_ring_t rbr_p) 3589 { 3590 p_rx_msg_t *rx_msg_ring; 3591 p_rx_msg_t rx_msg_p; 3592 rxring_info_t *ring_info; 3593 int i; 3594 uint32_t size; 3595 #ifdef NXGE_DEBUG 3596 int num_chunks; 3597 #endif 3598 3599 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3600 "==> nxge_unmap_rxdma_channel_buf_ring")); 3601 if (rbr_p == NULL) { 3602 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3603 "<== nxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 3604 return; 3605 } 3606 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3607 "==> nxge_unmap_rxdma_channel_buf_ring: channel %d", 3608 rbr_p->rdc)); 3609 3610 rx_msg_ring = rbr_p->rx_msg_ring; 3611 ring_info = rbr_p->ring_info; 3612 3613 if (rx_msg_ring == NULL || ring_info == NULL) { 3614 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3615 "<== nxge_unmap_rxdma_channel_buf_ring: " 3616 "rx_msg_ring $%p ring_info $%p", 3617 rx_msg_p, ring_info)); 3618 return; 3619 } 3620 3621 #ifdef NXGE_DEBUG 3622 num_chunks = rbr_p->num_blocks; 3623 #endif 3624 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 3625 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3626 " nxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 3627 "tnblocks %d (max %d) size ptrs %d ", 3628 rbr_p->rdc, num_chunks, 3629 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 3630 3631 for (i = 0; i < rbr_p->tnblocks; i++) { 3632 rx_msg_p = rx_msg_ring[i]; 3633 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3634 " nxge_unmap_rxdma_channel_buf_ring: " 3635 "rx_msg_p $%p", 3636 rx_msg_p)); 3637 if (rx_msg_p != NULL) { 3638 freeb(rx_msg_p->rx_mblk_p); 3639 rx_msg_ring[i] = NULL; 3640 } 3641 } 3642 3643 MUTEX_DESTROY(&rbr_p->post_lock); 3644 MUTEX_DESTROY(&rbr_p->lock); 3645 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 3646 KMEM_FREE(rx_msg_ring, size); 3647 KMEM_FREE(rbr_p, sizeof (rx_rbr_ring_t)); 3648 3649 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3650 "<== nxge_unmap_rxdma_channel_buf_ring")); 3651 } 3652 3653 static nxge_status_t 3654 nxge_rxdma_hw_start_common(p_nxge_t nxgep) 3655 { 3656 nxge_status_t status = NXGE_OK; 3657 3658 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3659 3660 /* 3661 * Load the sharable parameters by writing to the 3662 * function zero control registers. These FZC registers 3663 * should be initialized only once for the entire chip. 3664 */ 3665 (void) nxge_init_fzc_rx_common(nxgep); 3666 3667 /* 3668 * Initialize the RXDMA port specific FZC control configurations. 3669 * These FZC registers are pertaining to each port. 3670 */ 3671 (void) nxge_init_fzc_rxdma_port(nxgep); 3672 3673 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start_common")); 3674 3675 return (status); 3676 } 3677 3678 /*ARGSUSED*/ 3679 static void 3680 nxge_rxdma_hw_stop_common(p_nxge_t nxgep) 3681 { 3682 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3683 3684 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop_common")); 3685 } 3686 3687 static nxge_status_t 3688 nxge_rxdma_hw_start(p_nxge_t nxgep) 3689 { 3690 int i, ndmas; 3691 uint16_t channel; 3692 p_rx_rbr_rings_t rx_rbr_rings; 3693 p_rx_rbr_ring_t *rbr_rings; 3694 p_rx_rcr_rings_t rx_rcr_rings; 3695 p_rx_rcr_ring_t *rcr_rings; 3696 p_rx_mbox_areas_t rx_mbox_areas_p; 3697 p_rx_mbox_t *rx_mbox_p; 3698 nxge_status_t status = NXGE_OK; 3699 3700 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start")); 3701 3702 rx_rbr_rings = nxgep->rx_rbr_rings; 3703 rx_rcr_rings = nxgep->rx_rcr_rings; 3704 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3705 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3706 "<== nxge_rxdma_hw_start: NULL ring pointers")); 3707 return (NXGE_ERROR); 3708 } 3709 ndmas = rx_rbr_rings->ndmas; 3710 if (ndmas == 0) { 3711 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3712 "<== nxge_rxdma_hw_start: no dma channel allocated")); 3713 return (NXGE_ERROR); 3714 } 3715 3716 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3717 "==> nxge_rxdma_hw_start (ndmas %d)", ndmas)); 3718 3719 rbr_rings = rx_rbr_rings->rbr_rings; 3720 rcr_rings = rx_rcr_rings->rcr_rings; 3721 rx_mbox_areas_p = nxgep->rx_mbox_areas_p; 3722 if (rx_mbox_areas_p) { 3723 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3724 } 3725 3726 for (i = 0; i < ndmas; i++) { 3727 channel = rbr_rings[i]->rdc; 3728 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3729 "==> nxge_rxdma_hw_start (ndmas %d) channel %d", 3730 ndmas, channel)); 3731 status = nxge_rxdma_start_channel(nxgep, channel, 3732 (p_rx_rbr_ring_t)rbr_rings[i], 3733 (p_rx_rcr_ring_t)rcr_rings[i], 3734 (p_rx_mbox_t)rx_mbox_p[i]); 3735 if (status != NXGE_OK) { 3736 goto nxge_rxdma_hw_start_fail1; 3737 } 3738 } 3739 3740 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_start: " 3741 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3742 rx_rbr_rings, rx_rcr_rings)); 3743 3744 goto nxge_rxdma_hw_start_exit; 3745 3746 nxge_rxdma_hw_start_fail1: 3747 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3748 "==> nxge_rxdma_hw_start: disable " 3749 "(status 0x%x channel %d i %d)", status, channel, i)); 3750 for (; i >= 0; i--) { 3751 channel = rbr_rings[i]->rdc; 3752 (void) nxge_rxdma_stop_channel(nxgep, channel); 3753 } 3754 3755 nxge_rxdma_hw_start_exit: 3756 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3757 "==> nxge_rxdma_hw_start: (status 0x%x)", status)); 3758 3759 return (status); 3760 } 3761 3762 static void 3763 nxge_rxdma_hw_stop(p_nxge_t nxgep) 3764 { 3765 int i, ndmas; 3766 uint16_t channel; 3767 p_rx_rbr_rings_t rx_rbr_rings; 3768 p_rx_rbr_ring_t *rbr_rings; 3769 p_rx_rcr_rings_t rx_rcr_rings; 3770 3771 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop")); 3772 3773 rx_rbr_rings = nxgep->rx_rbr_rings; 3774 rx_rcr_rings = nxgep->rx_rcr_rings; 3775 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3776 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3777 "<== nxge_rxdma_hw_stop: NULL ring pointers")); 3778 return; 3779 } 3780 ndmas = rx_rbr_rings->ndmas; 3781 if (!ndmas) { 3782 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3783 "<== nxge_rxdma_hw_stop: no dma channel allocated")); 3784 return; 3785 } 3786 3787 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3788 "==> nxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3789 3790 rbr_rings = rx_rbr_rings->rbr_rings; 3791 3792 for (i = 0; i < ndmas; i++) { 3793 channel = rbr_rings[i]->rdc; 3794 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3795 "==> nxge_rxdma_hw_stop (ndmas %d) channel %d", 3796 ndmas, channel)); 3797 (void) nxge_rxdma_stop_channel(nxgep, channel); 3798 } 3799 3800 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_hw_stop: " 3801 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3802 rx_rbr_rings, rx_rcr_rings)); 3803 3804 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_hw_stop")); 3805 } 3806 3807 3808 static nxge_status_t 3809 nxge_rxdma_start_channel(p_nxge_t nxgep, uint16_t channel, 3810 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3811 3812 { 3813 npi_handle_t handle; 3814 npi_status_t rs = NPI_SUCCESS; 3815 rx_dma_ctl_stat_t cs; 3816 rx_dma_ent_msk_t ent_mask; 3817 nxge_status_t status = NXGE_OK; 3818 3819 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel")); 3820 3821 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3822 3823 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "nxge_rxdma_start_channel: " 3824 "npi handle addr $%p acc $%p", 3825 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3826 3827 /* Reset RXDMA channel */ 3828 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3829 if (rs != NPI_SUCCESS) { 3830 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3831 "==> nxge_rxdma_start_channel: " 3832 "reset rxdma failed (0x%08x channel %d)", 3833 status, channel)); 3834 return (NXGE_ERROR | rs); 3835 } 3836 3837 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3838 "==> nxge_rxdma_start_channel: reset done: channel %d", 3839 channel)); 3840 3841 /* 3842 * Initialize the RXDMA channel specific FZC control 3843 * configurations. These FZC registers are pertaining 3844 * to each RX channel (logical pages). 3845 */ 3846 status = nxge_init_fzc_rxdma_channel(nxgep, 3847 channel, rbr_p, rcr_p, mbox_p); 3848 if (status != NXGE_OK) { 3849 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3850 "==> nxge_rxdma_start_channel: " 3851 "init fzc rxdma failed (0x%08x channel %d)", 3852 status, channel)); 3853 return (status); 3854 } 3855 3856 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3857 "==> nxge_rxdma_start_channel: fzc done")); 3858 3859 /* 3860 * Zero out the shadow and prefetch ram. 3861 */ 3862 3863 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3864 "ram done")); 3865 3866 /* Set up the interrupt event masks. */ 3867 ent_mask.value = 0; 3868 ent_mask.value |= RX_DMA_ENT_MSK_RBREMPTY_MASK; 3869 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3870 &ent_mask); 3871 if (rs != NPI_SUCCESS) { 3872 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3873 "==> nxge_rxdma_start_channel: " 3874 "init rxdma event masks failed (0x%08x channel %d)", 3875 status, channel)); 3876 return (NXGE_ERROR | rs); 3877 } 3878 3879 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3880 "event done: channel %d (mask 0x%016llx)", 3881 channel, ent_mask.value)); 3882 3883 /* Initialize the receive DMA control and status register */ 3884 cs.value = 0; 3885 cs.bits.hdw.mex = 1; 3886 cs.bits.hdw.rcrthres = 1; 3887 cs.bits.hdw.rcrto = 1; 3888 cs.bits.hdw.rbr_empty = 1; 3889 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, &cs); 3890 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3891 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3892 if (status != NXGE_OK) { 3893 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3894 "==> nxge_rxdma_start_channel: " 3895 "init rxdma control register failed (0x%08x channel %d", 3896 status, channel)); 3897 return (status); 3898 } 3899 3900 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3901 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3902 3903 /* 3904 * Load RXDMA descriptors, buffers, mailbox, 3905 * initialise the receive DMA channels and 3906 * enable each DMA channel. 3907 */ 3908 status = nxge_enable_rxdma_channel(nxgep, 3909 channel, rbr_p, rcr_p, mbox_p); 3910 3911 if (status != NXGE_OK) { 3912 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3913 " nxge_rxdma_start_channel: " 3914 " init enable rxdma failed (0x%08x channel %d)", 3915 status, channel)); 3916 return (status); 3917 } 3918 3919 ent_mask.value = 0; 3920 ent_mask.value |= (RX_DMA_ENT_MSK_WRED_DROP_MASK | 3921 RX_DMA_ENT_MSK_PTDROP_PKT_MASK); 3922 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3923 &ent_mask); 3924 if (rs != NPI_SUCCESS) { 3925 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3926 "==> nxge_rxdma_start_channel: " 3927 "init rxdma event masks failed (0x%08x channel %d)", 3928 status, channel)); 3929 return (NXGE_ERROR | rs); 3930 } 3931 3932 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_rxdma_start_channel: " 3933 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3934 3935 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3936 "==> nxge_rxdma_start_channel: enable done")); 3937 3938 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_rxdma_start_channel")); 3939 3940 return (NXGE_OK); 3941 } 3942 3943 static nxge_status_t 3944 nxge_rxdma_stop_channel(p_nxge_t nxgep, uint16_t channel) 3945 { 3946 npi_handle_t handle; 3947 npi_status_t rs = NPI_SUCCESS; 3948 rx_dma_ctl_stat_t cs; 3949 rx_dma_ent_msk_t ent_mask; 3950 nxge_status_t status = NXGE_OK; 3951 3952 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel")); 3953 3954 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3955 3956 NXGE_DEBUG_MSG((nxgep, RX_CTL, "nxge_rxdma_stop_channel: " 3957 "npi handle addr $%p acc $%p", 3958 nxgep->npi_handle.regp, nxgep->npi_handle.regh)); 3959 3960 /* Reset RXDMA channel */ 3961 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 3962 if (rs != NPI_SUCCESS) { 3963 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3964 " nxge_rxdma_stop_channel: " 3965 " reset rxdma failed (0x%08x channel %d)", 3966 rs, channel)); 3967 return (NXGE_ERROR | rs); 3968 } 3969 3970 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3971 "==> nxge_rxdma_stop_channel: reset done")); 3972 3973 /* Set up the interrupt event masks. */ 3974 ent_mask.value = RX_DMA_ENT_MSK_ALL; 3975 rs = npi_rxdma_event_mask(handle, OP_SET, channel, 3976 &ent_mask); 3977 if (rs != NPI_SUCCESS) { 3978 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3979 "==> nxge_rxdma_stop_channel: " 3980 "set rxdma event masks failed (0x%08x channel %d)", 3981 rs, channel)); 3982 return (NXGE_ERROR | rs); 3983 } 3984 3985 NXGE_DEBUG_MSG((nxgep, RX_CTL, 3986 "==> nxge_rxdma_stop_channel: event done")); 3987 3988 /* Initialize the receive DMA control and status register */ 3989 cs.value = 0; 3990 status = nxge_init_rxdma_channel_cntl_stat(nxgep, channel, 3991 &cs); 3992 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_stop_channel: control " 3993 " to default (all 0s) 0x%08x", cs.value)); 3994 if (status != NXGE_OK) { 3995 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3996 " nxge_rxdma_stop_channel: init rxdma" 3997 " control register failed (0x%08x channel %d", 3998 status, channel)); 3999 return (status); 4000 } 4001 4002 NXGE_DEBUG_MSG((nxgep, RX_CTL, 4003 "==> nxge_rxdma_stop_channel: control done")); 4004 4005 /* disable dma channel */ 4006 status = nxge_disable_rxdma_channel(nxgep, channel); 4007 4008 if (status != NXGE_OK) { 4009 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4010 " nxge_rxdma_stop_channel: " 4011 " init enable rxdma failed (0x%08x channel %d)", 4012 status, channel)); 4013 return (status); 4014 } 4015 4016 NXGE_DEBUG_MSG((nxgep, 4017 RX_CTL, "==> nxge_rxdma_stop_channel: disable done")); 4018 4019 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_stop_channel")); 4020 4021 return (NXGE_OK); 4022 } 4023 4024 nxge_status_t 4025 nxge_rxdma_handle_sys_errors(p_nxge_t nxgep) 4026 { 4027 npi_handle_t handle; 4028 p_nxge_rdc_sys_stats_t statsp; 4029 rx_ctl_dat_fifo_stat_t stat; 4030 uint32_t zcp_err_status; 4031 uint32_t ipp_err_status; 4032 nxge_status_t status = NXGE_OK; 4033 npi_status_t rs = NPI_SUCCESS; 4034 boolean_t my_err = B_FALSE; 4035 4036 handle = nxgep->npi_handle; 4037 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4038 4039 rs = npi_rxdma_rxctl_fifo_error_intr_get(handle, &stat); 4040 4041 if (rs != NPI_SUCCESS) 4042 return (NXGE_ERROR | rs); 4043 4044 if (stat.bits.ldw.id_mismatch) { 4045 statsp->id_mismatch++; 4046 NXGE_FM_REPORT_ERROR(nxgep, nxgep->mac.portnum, NULL, 4047 NXGE_FM_EREPORT_RDMC_ID_MISMATCH); 4048 /* Global fatal error encountered */ 4049 } 4050 4051 if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) { 4052 switch (nxgep->mac.portnum) { 4053 case 0: 4054 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) || 4055 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) { 4056 my_err = B_TRUE; 4057 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4058 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4059 } 4060 break; 4061 case 1: 4062 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) || 4063 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) { 4064 my_err = B_TRUE; 4065 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4066 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4067 } 4068 break; 4069 case 2: 4070 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) || 4071 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) { 4072 my_err = B_TRUE; 4073 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4074 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4075 } 4076 break; 4077 case 3: 4078 if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) || 4079 (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) { 4080 my_err = B_TRUE; 4081 zcp_err_status = stat.bits.ldw.zcp_eop_err; 4082 ipp_err_status = stat.bits.ldw.ipp_eop_err; 4083 } 4084 break; 4085 default: 4086 return (NXGE_ERROR); 4087 } 4088 } 4089 4090 if (my_err) { 4091 status = nxge_rxdma_handle_port_errors(nxgep, ipp_err_status, 4092 zcp_err_status); 4093 if (status != NXGE_OK) 4094 return (status); 4095 } 4096 4097 return (NXGE_OK); 4098 } 4099 4100 static nxge_status_t 4101 nxge_rxdma_handle_port_errors(p_nxge_t nxgep, uint32_t ipp_status, 4102 uint32_t zcp_status) 4103 { 4104 boolean_t rxport_fatal = B_FALSE; 4105 p_nxge_rdc_sys_stats_t statsp; 4106 nxge_status_t status = NXGE_OK; 4107 uint8_t portn; 4108 4109 portn = nxgep->mac.portnum; 4110 statsp = (p_nxge_rdc_sys_stats_t)&nxgep->statsp->rdc_sys_stats; 4111 4112 if (ipp_status & (0x1 << portn)) { 4113 statsp->ipp_eop_err++; 4114 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4115 NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR); 4116 rxport_fatal = B_TRUE; 4117 } 4118 4119 if (zcp_status & (0x1 << portn)) { 4120 statsp->zcp_eop_err++; 4121 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 4122 NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR); 4123 rxport_fatal = B_TRUE; 4124 } 4125 4126 if (rxport_fatal) { 4127 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4128 " nxge_rxdma_handle_port_error: " 4129 " fatal error on Port #%d\n", 4130 portn)); 4131 status = nxge_rx_port_fatal_err_recover(nxgep); 4132 if (status == NXGE_OK) { 4133 FM_SERVICE_RESTORED(nxgep); 4134 } 4135 } 4136 4137 return (status); 4138 } 4139 4140 static nxge_status_t 4141 nxge_rxdma_fatal_err_recover(p_nxge_t nxgep, uint16_t channel) 4142 { 4143 npi_handle_t handle; 4144 npi_status_t rs = NPI_SUCCESS; 4145 nxge_status_t status = NXGE_OK; 4146 p_rx_rbr_ring_t rbrp; 4147 p_rx_rcr_ring_t rcrp; 4148 p_rx_mbox_t mboxp; 4149 rx_dma_ent_msk_t ent_mask; 4150 p_nxge_dma_common_t dmap; 4151 int ring_idx; 4152 uint32_t ref_cnt; 4153 p_rx_msg_t rx_msg_p; 4154 int i; 4155 uint32_t nxge_port_rcr_size; 4156 4157 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rxdma_fatal_err_recover")); 4158 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4159 "Recovering from RxDMAChannel#%d error...", channel)); 4160 4161 /* 4162 * Stop the dma channel waits for the stop done. 4163 * If the stop done bit is not set, then create 4164 * an error. 4165 */ 4166 4167 handle = NXGE_DEV_NPI_HANDLE(nxgep); 4168 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Rx DMA stop...")); 4169 4170 ring_idx = nxge_rxdma_get_ring_index(nxgep, channel); 4171 rbrp = (p_rx_rbr_ring_t)nxgep->rx_rbr_rings->rbr_rings[ring_idx]; 4172 rcrp = (p_rx_rcr_ring_t)nxgep->rx_rcr_rings->rcr_rings[ring_idx]; 4173 4174 MUTEX_ENTER(&rcrp->lock); 4175 MUTEX_ENTER(&rbrp->lock); 4176 MUTEX_ENTER(&rbrp->post_lock); 4177 4178 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA channel...")); 4179 4180 rs = npi_rxdma_cfg_rdc_disable(handle, channel); 4181 if (rs != NPI_SUCCESS) { 4182 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4183 "nxge_disable_rxdma_channel:failed")); 4184 goto fail; 4185 } 4186 4187 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxDMA interrupt...")); 4188 4189 /* Disable interrupt */ 4190 ent_mask.value = RX_DMA_ENT_MSK_ALL; 4191 rs = npi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 4192 if (rs != NPI_SUCCESS) { 4193 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4194 "nxge_rxdma_stop_channel: " 4195 "set rxdma event masks failed (channel %d)", 4196 channel)); 4197 } 4198 4199 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel reset...")); 4200 4201 /* Reset RXDMA channel */ 4202 rs = npi_rxdma_cfg_rdc_reset(handle, channel); 4203 if (rs != NPI_SUCCESS) { 4204 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4205 "nxge_rxdma_fatal_err_recover: " 4206 " reset rxdma failed (channel %d)", channel)); 4207 goto fail; 4208 } 4209 4210 nxge_port_rcr_size = nxgep->nxge_port_rcr_size; 4211 4212 mboxp = 4213 (p_rx_mbox_t)nxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 4214 4215 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 4216 rbrp->rbr_rd_index = 0; 4217 4218 rcrp->comp_rd_index = 0; 4219 rcrp->comp_wt_index = 0; 4220 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 4221 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 4222 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 4223 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 4224 4225 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 4226 (nxge_port_rcr_size - 1); 4227 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 4228 (nxge_port_rcr_size - 1); 4229 4230 dmap = (p_nxge_dma_common_t)&rcrp->rcr_desc; 4231 bzero((caddr_t)dmap->kaddrp, dmap->alength); 4232 4233 cmn_err(CE_NOTE, "!rbr entries = %d\n", rbrp->rbr_max_size); 4234 4235 for (i = 0; i < rbrp->rbr_max_size; i++) { 4236 rx_msg_p = rbrp->rx_msg_ring[i]; 4237 ref_cnt = rx_msg_p->ref_cnt; 4238 if (ref_cnt != 1) { 4239 if (rx_msg_p->cur_usage_cnt != 4240 rx_msg_p->max_usage_cnt) { 4241 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4242 "buf[%d]: cur_usage_cnt = %d " 4243 "max_usage_cnt = %d\n", i, 4244 rx_msg_p->cur_usage_cnt, 4245 rx_msg_p->max_usage_cnt)); 4246 } else { 4247 /* Buffer can be re-posted */ 4248 rx_msg_p->free = B_TRUE; 4249 rx_msg_p->cur_usage_cnt = 0; 4250 rx_msg_p->max_usage_cnt = 0xbaddcafe; 4251 rx_msg_p->pkt_buf_size = 0; 4252 } 4253 } 4254 } 4255 4256 NXGE_DEBUG_MSG((nxgep, RX_CTL, "RxDMA channel re-start...")); 4257 4258 status = nxge_rxdma_start_channel(nxgep, channel, rbrp, rcrp, mboxp); 4259 if (status != NXGE_OK) { 4260 goto fail; 4261 } 4262 4263 MUTEX_EXIT(&rbrp->post_lock); 4264 MUTEX_EXIT(&rbrp->lock); 4265 MUTEX_EXIT(&rcrp->lock); 4266 4267 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4268 "Recovery Successful, RxDMAChannel#%d Restored", 4269 channel)); 4270 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_rxdma_fatal_err_recover")); 4271 4272 return (NXGE_OK); 4273 fail: 4274 MUTEX_EXIT(&rbrp->post_lock); 4275 MUTEX_EXIT(&rbrp->lock); 4276 MUTEX_EXIT(&rcrp->lock); 4277 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4278 4279 return (NXGE_ERROR | rs); 4280 } 4281 4282 nxge_status_t 4283 nxge_rx_port_fatal_err_recover(p_nxge_t nxgep) 4284 { 4285 nxge_status_t status = NXGE_OK; 4286 p_nxge_dma_common_t *dma_buf_p; 4287 uint16_t channel; 4288 int ndmas; 4289 int i; 4290 4291 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_rx_port_fatal_err_recover")); 4292 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4293 "Recovering from RxPort error...")); 4294 /* Disable RxMAC */ 4295 4296 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Disable RxMAC...\n")); 4297 if (nxge_rx_mac_disable(nxgep) != NXGE_OK) 4298 goto fail; 4299 4300 NXGE_DELAY(1000); 4301 4302 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Stop all RxDMA channels...")); 4303 4304 ndmas = nxgep->rx_buf_pool_p->ndmas; 4305 dma_buf_p = nxgep->rx_buf_pool_p->dma_buf_pool_p; 4306 4307 for (i = 0; i < ndmas; i++) { 4308 channel = ((p_nxge_dma_common_t)dma_buf_p[i])->dma_channel; 4309 if (nxge_rxdma_fatal_err_recover(nxgep, channel) != NXGE_OK) { 4310 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4311 "Could not recover channel %d", 4312 channel)); 4313 } 4314 } 4315 4316 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset IPP...")); 4317 4318 /* Reset IPP */ 4319 if (nxge_ipp_reset(nxgep) != NXGE_OK) { 4320 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4321 "nxge_rx_port_fatal_err_recover: " 4322 "Failed to reset IPP")); 4323 goto fail; 4324 } 4325 4326 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Reset RxMAC...")); 4327 4328 /* Reset RxMAC */ 4329 if (nxge_rx_mac_reset(nxgep) != NXGE_OK) { 4330 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4331 "nxge_rx_port_fatal_err_recover: " 4332 "Failed to reset RxMAC")); 4333 goto fail; 4334 } 4335 4336 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize IPP...")); 4337 4338 /* Re-Initialize IPP */ 4339 if (nxge_ipp_init(nxgep) != NXGE_OK) { 4340 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4341 "nxge_rx_port_fatal_err_recover: " 4342 "Failed to init IPP")); 4343 goto fail; 4344 } 4345 4346 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-initialize RxMAC...")); 4347 4348 /* Re-Initialize RxMAC */ 4349 if ((status = nxge_rx_mac_init(nxgep)) != NXGE_OK) { 4350 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4351 "nxge_rx_port_fatal_err_recover: " 4352 "Failed to reset RxMAC")); 4353 goto fail; 4354 } 4355 4356 NXGE_DEBUG_MSG((nxgep, RX_CTL, "Re-enable RxMAC...")); 4357 4358 /* Re-enable RxMAC */ 4359 if ((status = nxge_rx_mac_enable(nxgep)) != NXGE_OK) { 4360 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4361 "nxge_rx_port_fatal_err_recover: " 4362 "Failed to enable RxMAC")); 4363 goto fail; 4364 } 4365 4366 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4367 "Recovery Successful, RxPort Restored")); 4368 4369 return (NXGE_OK); 4370 fail: 4371 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "Recovery failed")); 4372 return (status); 4373 } 4374 4375 void 4376 nxge_rxdma_inject_err(p_nxge_t nxgep, uint32_t err_id, uint8_t chan) 4377 { 4378 rx_dma_ctl_stat_t cs; 4379 rx_ctl_dat_fifo_stat_t cdfs; 4380 4381 switch (err_id) { 4382 case NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR: 4383 case NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR: 4384 case NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR: 4385 case NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR: 4386 case NXGE_FM_EREPORT_RDMC_RBR_TMOUT: 4387 case NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR: 4388 case NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS: 4389 case NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR: 4390 case NXGE_FM_EREPORT_RDMC_RCRINCON: 4391 case NXGE_FM_EREPORT_RDMC_RCRFULL: 4392 case NXGE_FM_EREPORT_RDMC_RBRFULL: 4393 case NXGE_FM_EREPORT_RDMC_RBRLOGPAGE: 4394 case NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE: 4395 case NXGE_FM_EREPORT_RDMC_CONFIG_ERR: 4396 RXDMA_REG_READ64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4397 chan, &cs.value); 4398 if (err_id == NXGE_FM_EREPORT_RDMC_RCR_ACK_ERR) 4399 cs.bits.hdw.rcr_ack_err = 1; 4400 else if (err_id == NXGE_FM_EREPORT_RDMC_DC_FIFO_ERR) 4401 cs.bits.hdw.dc_fifo_err = 1; 4402 else if (err_id == NXGE_FM_EREPORT_RDMC_RCR_SHA_PAR) 4403 cs.bits.hdw.rcr_sha_par = 1; 4404 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_PRE_PAR) 4405 cs.bits.hdw.rbr_pre_par = 1; 4406 else if (err_id == NXGE_FM_EREPORT_RDMC_RBR_TMOUT) 4407 cs.bits.hdw.rbr_tmout = 1; 4408 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_CNT_ERR) 4409 cs.bits.hdw.rsp_cnt_err = 1; 4410 else if (err_id == NXGE_FM_EREPORT_RDMC_BYTE_EN_BUS) 4411 cs.bits.hdw.byte_en_bus = 1; 4412 else if (err_id == NXGE_FM_EREPORT_RDMC_RSP_DAT_ERR) 4413 cs.bits.hdw.rsp_dat_err = 1; 4414 else if (err_id == NXGE_FM_EREPORT_RDMC_CONFIG_ERR) 4415 cs.bits.hdw.config_err = 1; 4416 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRINCON) 4417 cs.bits.hdw.rcrincon = 1; 4418 else if (err_id == NXGE_FM_EREPORT_RDMC_RCRFULL) 4419 cs.bits.hdw.rcrfull = 1; 4420 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRFULL) 4421 cs.bits.hdw.rbrfull = 1; 4422 else if (err_id == NXGE_FM_EREPORT_RDMC_RBRLOGPAGE) 4423 cs.bits.hdw.rbrlogpage = 1; 4424 else if (err_id == NXGE_FM_EREPORT_RDMC_CFIGLOGPAGE) 4425 cs.bits.hdw.cfiglogpage = 1; 4426 cmn_err(CE_NOTE, "!Write 0x%lx to RX_DMA_CTL_STAT_DBG_REG\n", 4427 cs.value); 4428 RXDMA_REG_WRITE64(nxgep->npi_handle, RX_DMA_CTL_STAT_DBG_REG, 4429 chan, cs.value); 4430 break; 4431 case NXGE_FM_EREPORT_RDMC_ID_MISMATCH: 4432 case NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR: 4433 case NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR: 4434 cdfs.value = 0; 4435 if (err_id == NXGE_FM_EREPORT_RDMC_ID_MISMATCH) 4436 cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum); 4437 else if (err_id == NXGE_FM_EREPORT_RDMC_ZCP_EOP_ERR) 4438 cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum); 4439 else if (err_id == NXGE_FM_EREPORT_RDMC_IPP_EOP_ERR) 4440 cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum); 4441 cmn_err(CE_NOTE, 4442 "!Write 0x%lx to RX_CTL_DAT_FIFO_STAT_DBG_REG\n", 4443 cdfs.value); 4444 RXDMA_REG_WRITE64(nxgep->npi_handle, 4445 RX_CTL_DAT_FIFO_STAT_DBG_REG, chan, cdfs.value); 4446 break; 4447 case NXGE_FM_EREPORT_RDMC_DCF_ERR: 4448 break; 4449 case NXGE_FM_EREPORT_RDMC_COMPLETION_ERR: 4450 break; 4451 } 4452 } 4453 4454 4455 static uint16_t 4456 nxge_get_pktbuf_size(p_nxge_t nxgep, int bufsz_type, rbr_cfig_b_t rbr_cfgb) 4457 { 4458 uint16_t sz = RBR_BKSIZE_8K_BYTES; 4459 4460 switch (bufsz_type) { 4461 case RCR_PKTBUFSZ_0: 4462 switch (rbr_cfgb.bits.ldw.bufsz0) { 4463 case RBR_BUFSZ0_256B: 4464 sz = RBR_BUFSZ0_256_BYTES; 4465 break; 4466 case RBR_BUFSZ0_512B: 4467 sz = RBR_BUFSZ0_512B_BYTES; 4468 break; 4469 case RBR_BUFSZ0_1K: 4470 sz = RBR_BUFSZ0_1K_BYTES; 4471 break; 4472 case RBR_BUFSZ0_2K: 4473 sz = RBR_BUFSZ0_2K_BYTES; 4474 break; 4475 default: 4476 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4477 "nxge_get_pktbug_size: bad bufsz0")); 4478 break; 4479 } 4480 break; 4481 case RCR_PKTBUFSZ_1: 4482 switch (rbr_cfgb.bits.ldw.bufsz1) { 4483 case RBR_BUFSZ1_1K: 4484 sz = RBR_BUFSZ1_1K_BYTES; 4485 break; 4486 case RBR_BUFSZ1_2K: 4487 sz = RBR_BUFSZ1_2K_BYTES; 4488 break; 4489 case RBR_BUFSZ1_4K: 4490 sz = RBR_BUFSZ1_4K_BYTES; 4491 break; 4492 case RBR_BUFSZ1_8K: 4493 sz = RBR_BUFSZ1_8K_BYTES; 4494 break; 4495 default: 4496 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4497 "nxge_get_pktbug_size: bad bufsz1")); 4498 break; 4499 } 4500 break; 4501 case RCR_PKTBUFSZ_2: 4502 switch (rbr_cfgb.bits.ldw.bufsz2) { 4503 case RBR_BUFSZ2_2K: 4504 sz = RBR_BUFSZ2_2K_BYTES; 4505 break; 4506 case RBR_BUFSZ2_4K: 4507 sz = RBR_BUFSZ2_4K_BYTES; 4508 break; 4509 case RBR_BUFSZ2_8K: 4510 sz = RBR_BUFSZ2_8K_BYTES; 4511 break; 4512 case RBR_BUFSZ2_16K: 4513 sz = RBR_BUFSZ2_16K_BYTES; 4514 break; 4515 default: 4516 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4517 "nxge_get_pktbug_size: bad bufsz2")); 4518 break; 4519 } 4520 break; 4521 case RCR_SINGLE_BLOCK: 4522 switch (rbr_cfgb.bits.ldw.bksize) { 4523 case BKSIZE_4K: 4524 sz = RBR_BKSIZE_4K_BYTES; 4525 break; 4526 case BKSIZE_8K: 4527 sz = RBR_BKSIZE_8K_BYTES; 4528 break; 4529 case BKSIZE_16K: 4530 sz = RBR_BKSIZE_16K_BYTES; 4531 break; 4532 case BKSIZE_32K: 4533 sz = RBR_BKSIZE_32K_BYTES; 4534 break; 4535 default: 4536 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4537 "nxge_get_pktbug_size: bad bksize")); 4538 break; 4539 } 4540 break; 4541 default: 4542 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 4543 "nxge_get_pktbug_size: bad bufsz_type")); 4544 break; 4545 } 4546 return (sz); 4547 } 4548