1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 30 */ 31 #include <sys/nxge/nxge_impl.h> 32 #include <sys/nxge/nxge_hio.h> 33 #include <sys/nxge/nxge_rxdma.h> 34 #include <sys/pcie.h> 35 36 uint32_t nxge_use_partition = 0; /* debug partition flag */ 37 uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 38 uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 39 /* 40 * PSARC/2007/453 MSI-X interrupt limit override 41 * (This PSARC case is limited to MSI-X vectors 42 * and SPARC platforms only). 43 */ 44 #if defined(_BIG_ENDIAN) 45 uint32_t nxge_msi_enable = 2; 46 #else 47 uint32_t nxge_msi_enable = 1; 48 #endif 49 50 /* 51 * Software workaround for a Neptune (PCI-E) 52 * hardware interrupt bug which the hardware 53 * may generate spurious interrupts after the 54 * device interrupt handler was removed. If this flag 55 * is enabled, the driver will reset the 56 * hardware when devices are being detached. 57 */ 58 uint32_t nxge_peu_reset_enable = 0; 59 60 /* 61 * Software workaround for the hardware 62 * checksum bugs that affect packet transmission 63 * and receive: 64 * 65 * Usage of nxge_cksum_offload: 66 * 67 * (1) nxge_cksum_offload = 0 (default): 68 * - transmits packets: 69 * TCP: uses the hardware checksum feature. 70 * UDP: driver will compute the software checksum 71 * based on the partial checksum computed 72 * by the IP layer. 73 * - receives packets 74 * TCP: marks packets checksum flags based on hardware result. 75 * UDP: will not mark checksum flags. 76 * 77 * (2) nxge_cksum_offload = 1: 78 * - transmit packets: 79 * TCP/UDP: uses the hardware checksum feature. 80 * - receives packets 81 * TCP/UDP: marks packet checksum flags based on hardware result. 82 * 83 * (3) nxge_cksum_offload = 2: 84 * - The driver will not register its checksum capability. 85 * Checksum for both TCP and UDP will be computed 86 * by the stack. 87 * - The software LSO is not allowed in this case. 88 * 89 * (4) nxge_cksum_offload > 2: 90 * - Will be treated as it is set to 2 91 * (stack will compute the checksum). 92 * 93 * (5) If the hardware bug is fixed, this workaround 94 * needs to be updated accordingly to reflect 95 * the new hardware revision. 96 */ 97 uint32_t nxge_cksum_offload = 0; 98 99 /* 100 * Globals: tunable parameters (/etc/system or adb) 101 * 102 */ 103 uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 104 uint32_t nxge_rbr_spare_size = 0; 105 uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 106 uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 107 boolean_t nxge_no_msg = B_TRUE; /* control message display */ 108 uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 109 uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 110 uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 111 uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 112 uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 113 boolean_t nxge_jumbo_enable = B_FALSE; 114 uint16_t nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT; 115 uint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD; 116 nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 117 118 /* MAX LSO size */ 119 #define NXGE_LSO_MAXLEN 65535 120 uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 121 122 /* 123 * Debugging flags: 124 * nxge_no_tx_lb : transmit load balancing 125 * nxge_tx_lb_policy: 0 - TCP port (default) 126 * 3 - DEST MAC 127 */ 128 uint32_t nxge_no_tx_lb = 0; 129 uint32_t nxge_tx_lb_policy = NXGE_TX_LB_TCPUDP; 130 131 /* 132 * Add tunable to reduce the amount of time spent in the 133 * ISR doing Rx Processing. 134 */ 135 uint32_t nxge_max_rx_pkts = 1024; 136 137 /* 138 * Tunables to manage the receive buffer blocks. 139 * 140 * nxge_rx_threshold_hi: copy all buffers. 141 * nxge_rx_bcopy_size_type: receive buffer block size type. 142 * nxge_rx_threshold_lo: copy only up to tunable block size type. 143 */ 144 nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 145 nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 146 nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 147 148 /* Use kmem_alloc() to allocate data buffers. */ 149 #if defined(_BIG_ENDIAN) 150 uint32_t nxge_use_kmem_alloc = 1; 151 #else 152 uint32_t nxge_use_kmem_alloc = 0; 153 #endif 154 155 rtrace_t npi_rtracebuf; 156 157 /* 158 * The hardware sometimes fails to allow enough time for the link partner 159 * to send an acknowledgement for packets that the hardware sent to it. The 160 * hardware resends the packets earlier than it should be in those instances. 161 * This behavior caused some switches to acknowledge the wrong packets 162 * and it triggered the fatal error. 163 * This software workaround is to set the replay timer to a value 164 * suggested by the hardware team. 165 * 166 * PCI config space replay timer register: 167 * The following replay timeout value is 0xc 168 * for bit 14:18. 169 */ 170 #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 171 #define PCI_REPLAY_TIMEOUT_SHIFT 14 172 173 uint32_t nxge_set_replay_timer = 1; 174 uint32_t nxge_replay_timeout = 0xc; 175 176 /* 177 * The transmit serialization sometimes causes 178 * longer sleep before calling the driver transmit 179 * function as it sleeps longer than it should. 180 * The performace group suggests that a time wait tunable 181 * can be used to set the maximum wait time when needed 182 * and the default is set to 1 tick. 183 */ 184 uint32_t nxge_tx_serial_maxsleep = 1; 185 186 #if defined(sun4v) 187 /* 188 * Hypervisor N2/NIU services information. 189 */ 190 static hsvc_info_t niu_hsvc = { 191 HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 192 NIU_MINOR_VER, "nxge" 193 }; 194 195 static int nxge_hsvc_register(p_nxge_t); 196 #endif 197 198 /* 199 * Function Prototypes 200 */ 201 static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 202 static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 203 static void nxge_unattach(p_nxge_t); 204 205 #if NXGE_PROPERTY 206 static void nxge_remove_hard_properties(p_nxge_t); 207 #endif 208 209 /* 210 * These two functions are required by nxge_hio.c 211 */ 212 extern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr); 213 extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 214 215 static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 216 217 static nxge_status_t nxge_setup_mutexes(p_nxge_t); 218 static void nxge_destroy_mutexes(p_nxge_t); 219 220 static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 221 static void nxge_unmap_regs(p_nxge_t nxgep); 222 #ifdef NXGE_DEBUG 223 static void nxge_test_map_regs(p_nxge_t nxgep); 224 #endif 225 226 static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 227 static nxge_status_t nxge_add_soft_intrs(p_nxge_t nxgep); 228 static void nxge_remove_intrs(p_nxge_t nxgep); 229 static void nxge_remove_soft_intrs(p_nxge_t nxgep); 230 231 static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 232 static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 233 static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 234 static void nxge_intrs_enable(p_nxge_t nxgep); 235 static void nxge_intrs_disable(p_nxge_t nxgep); 236 237 static void nxge_suspend(p_nxge_t); 238 static nxge_status_t nxge_resume(p_nxge_t); 239 240 static nxge_status_t nxge_setup_dev(p_nxge_t); 241 static void nxge_destroy_dev(p_nxge_t); 242 243 static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 244 static void nxge_free_mem_pool(p_nxge_t); 245 246 nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 247 static void nxge_free_rx_mem_pool(p_nxge_t); 248 249 nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 250 static void nxge_free_tx_mem_pool(p_nxge_t); 251 252 static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 253 struct ddi_dma_attr *, 254 size_t, ddi_device_acc_attr_t *, uint_t, 255 p_nxge_dma_common_t); 256 257 static void nxge_dma_mem_free(p_nxge_dma_common_t); 258 static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 259 260 static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 261 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 262 static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 263 264 static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 265 p_nxge_dma_common_t *, size_t); 266 static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 267 268 extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 269 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 270 static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 271 272 extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 273 p_nxge_dma_common_t *, 274 size_t); 275 static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 276 277 static int nxge_init_common_dev(p_nxge_t); 278 static void nxge_uninit_common_dev(p_nxge_t); 279 extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 280 char *, caddr_t); 281 282 /* 283 * The next declarations are for the GLDv3 interface. 284 */ 285 static int nxge_m_start(void *); 286 static void nxge_m_stop(void *); 287 static int nxge_m_unicst(void *, const uint8_t *); 288 static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 289 static int nxge_m_promisc(void *, boolean_t); 290 static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 291 static void nxge_m_resources(void *); 292 mblk_t *nxge_m_tx(void *arg, mblk_t *); 293 static nxge_status_t nxge_mac_register(p_nxge_t); 294 static int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 295 mac_addr_slot_t slot); 296 void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, 297 boolean_t factory); 298 static int nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr); 299 static int nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr); 300 static int nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr); 301 static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 302 static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 303 uint_t, const void *); 304 static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 305 uint_t, uint_t, void *); 306 static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 307 const void *); 308 static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 309 void *); 310 static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 311 312 static void nxge_niu_peu_reset(p_nxge_t nxgep); 313 static void nxge_set_pci_replay_timeout(nxge_t *); 314 315 mac_priv_prop_t nxge_priv_props[] = { 316 {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 317 {"_adv_pause_cap", MAC_PROP_PERM_RW}, 318 {"_function_number", MAC_PROP_PERM_READ}, 319 {"_fw_version", MAC_PROP_PERM_READ}, 320 {"_port_mode", MAC_PROP_PERM_READ}, 321 {"_hot_swap_phy", MAC_PROP_PERM_READ}, 322 {"_accept_jumbo", MAC_PROP_PERM_RW}, 323 {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 324 {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 325 {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 326 {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 327 {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 328 {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 329 {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 330 {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 331 {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 332 {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 333 {"_soft_lso_enable", MAC_PROP_PERM_RW} 334 }; 335 336 #define NXGE_MAX_PRIV_PROPS \ 337 (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 338 339 #define NXGE_M_CALLBACK_FLAGS\ 340 (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 341 342 343 #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 344 #define MAX_DUMP_SZ 256 345 346 #define NXGE_M_CALLBACK_FLAGS \ 347 (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 348 349 mac_callbacks_t nxge_m_callbacks = { 350 NXGE_M_CALLBACK_FLAGS, 351 nxge_m_stat, 352 nxge_m_start, 353 nxge_m_stop, 354 nxge_m_promisc, 355 nxge_m_multicst, 356 nxge_m_unicst, 357 nxge_m_tx, 358 nxge_m_resources, 359 nxge_m_ioctl, 360 nxge_m_getcapab, 361 NULL, 362 NULL, 363 nxge_m_setprop, 364 nxge_m_getprop 365 }; 366 367 void 368 nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 369 370 /* PSARC/2007/453 MSI-X interrupt limit override. */ 371 #define NXGE_MSIX_REQUEST_10G 8 372 #define NXGE_MSIX_REQUEST_1G 2 373 static int nxge_create_msi_property(p_nxge_t); 374 375 /* 376 * These global variables control the message 377 * output. 378 */ 379 out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 380 uint64_t nxge_debug_level; 381 382 /* 383 * This list contains the instance structures for the Neptune 384 * devices present in the system. The lock exists to guarantee 385 * mutually exclusive access to the list. 386 */ 387 void *nxge_list = NULL; 388 389 void *nxge_hw_list = NULL; 390 nxge_os_mutex_t nxge_common_lock; 391 392 extern uint64_t npi_debug_level; 393 394 extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 395 extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 396 extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 397 extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 398 extern void nxge_fm_init(p_nxge_t, 399 ddi_device_acc_attr_t *, 400 ddi_device_acc_attr_t *, 401 ddi_dma_attr_t *); 402 extern void nxge_fm_fini(p_nxge_t); 403 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 404 405 /* 406 * Count used to maintain the number of buffers being used 407 * by Neptune instances and loaned up to the upper layers. 408 */ 409 uint32_t nxge_mblks_pending = 0; 410 411 /* 412 * Device register access attributes for PIO. 413 */ 414 static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 415 DDI_DEVICE_ATTR_V0, 416 DDI_STRUCTURE_LE_ACC, 417 DDI_STRICTORDER_ACC, 418 }; 419 420 /* 421 * Device descriptor access attributes for DMA. 422 */ 423 static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 424 DDI_DEVICE_ATTR_V0, 425 DDI_STRUCTURE_LE_ACC, 426 DDI_STRICTORDER_ACC 427 }; 428 429 /* 430 * Device buffer access attributes for DMA. 431 */ 432 static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 433 DDI_DEVICE_ATTR_V0, 434 DDI_STRUCTURE_BE_ACC, 435 DDI_STRICTORDER_ACC 436 }; 437 438 ddi_dma_attr_t nxge_desc_dma_attr = { 439 DMA_ATTR_V0, /* version number. */ 440 0, /* low address */ 441 0xffffffffffffffff, /* high address */ 442 0xffffffffffffffff, /* address counter max */ 443 #ifndef NIU_PA_WORKAROUND 444 0x100000, /* alignment */ 445 #else 446 0x2000, 447 #endif 448 0xfc00fc, /* dlim_burstsizes */ 449 0x1, /* minimum transfer size */ 450 0xffffffffffffffff, /* maximum transfer size */ 451 0xffffffffffffffff, /* maximum segment size */ 452 1, /* scatter/gather list length */ 453 (unsigned int) 1, /* granularity */ 454 0 /* attribute flags */ 455 }; 456 457 ddi_dma_attr_t nxge_tx_dma_attr = { 458 DMA_ATTR_V0, /* version number. */ 459 0, /* low address */ 460 0xffffffffffffffff, /* high address */ 461 0xffffffffffffffff, /* address counter max */ 462 #if defined(_BIG_ENDIAN) 463 0x2000, /* alignment */ 464 #else 465 0x1000, /* alignment */ 466 #endif 467 0xfc00fc, /* dlim_burstsizes */ 468 0x1, /* minimum transfer size */ 469 0xffffffffffffffff, /* maximum transfer size */ 470 0xffffffffffffffff, /* maximum segment size */ 471 5, /* scatter/gather list length */ 472 (unsigned int) 1, /* granularity */ 473 0 /* attribute flags */ 474 }; 475 476 ddi_dma_attr_t nxge_rx_dma_attr = { 477 DMA_ATTR_V0, /* version number. */ 478 0, /* low address */ 479 0xffffffffffffffff, /* high address */ 480 0xffffffffffffffff, /* address counter max */ 481 0x2000, /* alignment */ 482 0xfc00fc, /* dlim_burstsizes */ 483 0x1, /* minimum transfer size */ 484 0xffffffffffffffff, /* maximum transfer size */ 485 0xffffffffffffffff, /* maximum segment size */ 486 1, /* scatter/gather list length */ 487 (unsigned int) 1, /* granularity */ 488 DDI_DMA_RELAXED_ORDERING /* attribute flags */ 489 }; 490 491 ddi_dma_lim_t nxge_dma_limits = { 492 (uint_t)0, /* dlim_addr_lo */ 493 (uint_t)0xffffffff, /* dlim_addr_hi */ 494 (uint_t)0xffffffff, /* dlim_cntr_max */ 495 (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 496 0x1, /* dlim_minxfer */ 497 1024 /* dlim_speed */ 498 }; 499 500 dma_method_t nxge_force_dma = DVMA; 501 502 /* 503 * dma chunk sizes. 504 * 505 * Try to allocate the largest possible size 506 * so that fewer number of dma chunks would be managed 507 */ 508 #ifdef NIU_PA_WORKAROUND 509 size_t alloc_sizes [] = {0x2000}; 510 #else 511 size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 512 0x10000, 0x20000, 0x40000, 0x80000, 513 0x100000, 0x200000, 0x400000, 0x800000, 514 0x1000000, 0x2000000, 0x4000000}; 515 #endif 516 517 /* 518 * Translate "dev_t" to a pointer to the associated "dev_info_t". 519 */ 520 521 extern void nxge_get_environs(nxge_t *); 522 523 static int 524 nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 525 { 526 p_nxge_t nxgep = NULL; 527 int instance; 528 int status = DDI_SUCCESS; 529 uint8_t portn; 530 nxge_mmac_t *mmac_info; 531 532 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 533 534 /* 535 * Get the device instance since we'll need to setup 536 * or retrieve a soft state for this instance. 537 */ 538 instance = ddi_get_instance(dip); 539 540 switch (cmd) { 541 case DDI_ATTACH: 542 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 543 break; 544 545 case DDI_RESUME: 546 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 547 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 548 if (nxgep == NULL) { 549 status = DDI_FAILURE; 550 break; 551 } 552 if (nxgep->dip != dip) { 553 status = DDI_FAILURE; 554 break; 555 } 556 if (nxgep->suspended == DDI_PM_SUSPEND) { 557 status = ddi_dev_is_needed(nxgep->dip, 0, 1); 558 } else { 559 status = nxge_resume(nxgep); 560 } 561 goto nxge_attach_exit; 562 563 case DDI_PM_RESUME: 564 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 565 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 566 if (nxgep == NULL) { 567 status = DDI_FAILURE; 568 break; 569 } 570 if (nxgep->dip != dip) { 571 status = DDI_FAILURE; 572 break; 573 } 574 status = nxge_resume(nxgep); 575 goto nxge_attach_exit; 576 577 default: 578 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 579 status = DDI_FAILURE; 580 goto nxge_attach_exit; 581 } 582 583 584 if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 585 status = DDI_FAILURE; 586 goto nxge_attach_exit; 587 } 588 589 nxgep = ddi_get_soft_state(nxge_list, instance); 590 if (nxgep == NULL) { 591 status = NXGE_ERROR; 592 goto nxge_attach_fail2; 593 } 594 595 nxgep->nxge_magic = NXGE_MAGIC; 596 597 nxgep->drv_state = 0; 598 nxgep->dip = dip; 599 nxgep->instance = instance; 600 nxgep->p_dip = ddi_get_parent(dip); 601 nxgep->nxge_debug_level = nxge_debug_level; 602 npi_debug_level = nxge_debug_level; 603 604 /* Are we a guest running in a Hybrid I/O environment? */ 605 nxge_get_environs(nxgep); 606 607 status = nxge_map_regs(nxgep); 608 609 if (status != NXGE_OK) { 610 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 611 goto nxge_attach_fail3; 612 } 613 614 nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, 615 &nxge_dev_desc_dma_acc_attr, 616 &nxge_rx_dma_attr); 617 618 /* Create & initialize the per-Neptune data structure */ 619 /* (even if we're a guest). */ 620 status = nxge_init_common_dev(nxgep); 621 if (status != NXGE_OK) { 622 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 623 "nxge_init_common_dev failed")); 624 goto nxge_attach_fail4; 625 } 626 627 /* 628 * Software workaround: set the replay timer. 629 */ 630 if (nxgep->niu_type != N2_NIU) { 631 nxge_set_pci_replay_timeout(nxgep); 632 } 633 634 #if defined(sun4v) 635 /* This is required by nxge_hio_init(), which follows. */ 636 if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 637 goto nxge_attach_fail; 638 #endif 639 640 if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 641 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 642 "nxge_hio_init failed")); 643 goto nxge_attach_fail4; 644 } 645 646 if (nxgep->niu_type == NEPTUNE_2_10GF) { 647 if (nxgep->function_num > 1) { 648 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 649 " function %d. Only functions 0 and 1 are " 650 "supported for this card.", nxgep->function_num)); 651 status = NXGE_ERROR; 652 goto nxge_attach_fail4; 653 } 654 } 655 656 if (isLDOMguest(nxgep)) { 657 /* 658 * Use the function number here. 659 */ 660 nxgep->mac.portnum = nxgep->function_num; 661 nxgep->mac.porttype = PORT_TYPE_LOGICAL; 662 663 /* XXX We'll set the MAC address counts to 1 for now. */ 664 mmac_info = &nxgep->nxge_mmac_info; 665 mmac_info->num_mmac = 1; 666 mmac_info->naddrfree = 1; 667 } else { 668 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 669 nxgep->mac.portnum = portn; 670 if ((portn == 0) || (portn == 1)) 671 nxgep->mac.porttype = PORT_TYPE_XMAC; 672 else 673 nxgep->mac.porttype = PORT_TYPE_BMAC; 674 /* 675 * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 676 * internally, the rest 2 ports use BMAC (1G "Big" MAC). 677 * The two types of MACs have different characterizations. 678 */ 679 mmac_info = &nxgep->nxge_mmac_info; 680 if (nxgep->function_num < 2) { 681 mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 682 mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 683 } else { 684 mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 685 mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 686 } 687 } 688 /* 689 * Setup the Ndd parameters for the this instance. 690 */ 691 nxge_init_param(nxgep); 692 693 /* 694 * Setup Register Tracing Buffer. 695 */ 696 npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 697 698 /* init stats ptr */ 699 nxge_init_statsp(nxgep); 700 701 /* 702 * Copy the vpd info from eeprom to a local data 703 * structure, and then check its validity. 704 */ 705 if (!isLDOMguest(nxgep)) { 706 int *regp; 707 uint_t reglen; 708 int rv; 709 710 nxge_vpd_info_get(nxgep); 711 712 /* Find the NIU config handle. */ 713 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 714 ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 715 "reg", ®p, ®len); 716 717 if (rv != DDI_PROP_SUCCESS) { 718 goto nxge_attach_fail5; 719 } 720 /* 721 * The address_hi, that is the first int, in the reg 722 * property consists of config handle, but need to remove 723 * the bits 28-31 which are OBP specific info. 724 */ 725 nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 726 ddi_prop_free(regp); 727 } 728 729 if (isLDOMguest(nxgep)) { 730 uchar_t *prop_val; 731 uint_t prop_len; 732 733 extern void nxge_get_logical_props(p_nxge_t); 734 735 nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 736 nxgep->mac.portmode = PORT_LOGICAL; 737 (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 738 "phy-type", "virtual transceiver"); 739 740 nxgep->nports = 1; 741 nxgep->board_ver = 0; /* XXX What? */ 742 743 /* 744 * local-mac-address property gives us info on which 745 * specific MAC address the Hybrid resource is associated 746 * with. 747 */ 748 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 749 "local-mac-address", &prop_val, 750 &prop_len) != DDI_PROP_SUCCESS) { 751 goto nxge_attach_fail5; 752 } 753 if (prop_len != ETHERADDRL) { 754 ddi_prop_free(prop_val); 755 goto nxge_attach_fail5; 756 } 757 ether_copy(prop_val, nxgep->hio_mac_addr); 758 ddi_prop_free(prop_val); 759 nxge_get_logical_props(nxgep); 760 761 } else { 762 status = nxge_xcvr_find(nxgep); 763 764 if (status != NXGE_OK) { 765 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 766 " Couldn't determine card type" 767 " .... exit ")); 768 goto nxge_attach_fail5; 769 } 770 771 status = nxge_get_config_properties(nxgep); 772 773 if (status != NXGE_OK) { 774 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 775 "get_hw create failed")); 776 goto nxge_attach_fail; 777 } 778 } 779 780 /* 781 * Setup the Kstats for the driver. 782 */ 783 nxge_setup_kstats(nxgep); 784 785 if (!isLDOMguest(nxgep)) 786 nxge_setup_param(nxgep); 787 788 status = nxge_setup_system_dma_pages(nxgep); 789 if (status != NXGE_OK) { 790 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 791 goto nxge_attach_fail; 792 } 793 794 nxge_hw_id_init(nxgep); 795 796 if (!isLDOMguest(nxgep)) 797 nxge_hw_init_niu_common(nxgep); 798 799 status = nxge_setup_mutexes(nxgep); 800 if (status != NXGE_OK) { 801 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 802 goto nxge_attach_fail; 803 } 804 805 #if defined(sun4v) 806 if (isLDOMguest(nxgep)) { 807 /* Find our VR & channel sets. */ 808 status = nxge_hio_vr_add(nxgep); 809 goto nxge_attach_exit; 810 } 811 #endif 812 813 status = nxge_setup_dev(nxgep); 814 if (status != DDI_SUCCESS) { 815 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 816 goto nxge_attach_fail; 817 } 818 819 status = nxge_add_intrs(nxgep); 820 if (status != DDI_SUCCESS) { 821 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 822 goto nxge_attach_fail; 823 } 824 status = nxge_add_soft_intrs(nxgep); 825 if (status != DDI_SUCCESS) { 826 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 827 "add_soft_intr failed")); 828 goto nxge_attach_fail; 829 } 830 831 /* 832 * Enable interrupts. 833 */ 834 nxge_intrs_enable(nxgep); 835 836 /* If a guest, register with vio_net instead. */ 837 if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 838 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 839 "unable to register to mac layer (%d)", status)); 840 goto nxge_attach_fail; 841 } 842 843 mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 844 845 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 846 "registered to mac (instance %d)", instance)); 847 848 /* nxge_link_monitor calls xcvr.check_link recursively */ 849 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 850 851 goto nxge_attach_exit; 852 853 nxge_attach_fail: 854 nxge_unattach(nxgep); 855 goto nxge_attach_fail1; 856 857 nxge_attach_fail5: 858 /* 859 * Tear down the ndd parameters setup. 860 */ 861 nxge_destroy_param(nxgep); 862 863 /* 864 * Tear down the kstat setup. 865 */ 866 nxge_destroy_kstats(nxgep); 867 868 nxge_attach_fail4: 869 if (nxgep->nxge_hw_p) { 870 nxge_uninit_common_dev(nxgep); 871 nxgep->nxge_hw_p = NULL; 872 } 873 874 nxge_attach_fail3: 875 /* 876 * Unmap the register setup. 877 */ 878 nxge_unmap_regs(nxgep); 879 880 nxge_fm_fini(nxgep); 881 882 nxge_attach_fail2: 883 ddi_soft_state_free(nxge_list, nxgep->instance); 884 885 nxge_attach_fail1: 886 if (status != NXGE_OK) 887 status = (NXGE_ERROR | NXGE_DDI_FAILED); 888 nxgep = NULL; 889 890 nxge_attach_exit: 891 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 892 status)); 893 894 return (status); 895 } 896 897 static int 898 nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 899 { 900 int status = DDI_SUCCESS; 901 int instance; 902 p_nxge_t nxgep = NULL; 903 904 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 905 instance = ddi_get_instance(dip); 906 nxgep = ddi_get_soft_state(nxge_list, instance); 907 if (nxgep == NULL) { 908 status = DDI_FAILURE; 909 goto nxge_detach_exit; 910 } 911 912 switch (cmd) { 913 case DDI_DETACH: 914 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 915 break; 916 917 case DDI_PM_SUSPEND: 918 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 919 nxgep->suspended = DDI_PM_SUSPEND; 920 nxge_suspend(nxgep); 921 break; 922 923 case DDI_SUSPEND: 924 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 925 if (nxgep->suspended != DDI_PM_SUSPEND) { 926 nxgep->suspended = DDI_SUSPEND; 927 nxge_suspend(nxgep); 928 } 929 break; 930 931 default: 932 status = DDI_FAILURE; 933 } 934 935 if (cmd != DDI_DETACH) 936 goto nxge_detach_exit; 937 938 /* 939 * Stop the xcvr polling. 940 */ 941 nxgep->suspended = cmd; 942 943 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 944 945 if (isLDOMguest(nxgep)) { 946 nxge_hio_unregister(nxgep); 947 } else if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 948 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 949 "<== nxge_detach status = 0x%08X", status)); 950 return (DDI_FAILURE); 951 } 952 953 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 954 "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 955 956 nxge_unattach(nxgep); 957 nxgep = NULL; 958 959 nxge_detach_exit: 960 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 961 status)); 962 963 return (status); 964 } 965 966 static void 967 nxge_unattach(p_nxge_t nxgep) 968 { 969 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 970 971 if (nxgep == NULL || nxgep->dev_regs == NULL) { 972 return; 973 } 974 975 nxgep->nxge_magic = 0; 976 977 if (nxgep->nxge_timerid) { 978 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 979 nxgep->nxge_timerid = 0; 980 } 981 982 /* 983 * If this flag is set, it will affect the Neptune 984 * only. 985 */ 986 if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 987 nxge_niu_peu_reset(nxgep); 988 } 989 990 #if defined(sun4v) 991 if (isLDOMguest(nxgep)) { 992 (void) nxge_hio_vr_release(nxgep); 993 } 994 #endif 995 996 if (nxgep->nxge_hw_p) { 997 nxge_uninit_common_dev(nxgep); 998 nxgep->nxge_hw_p = NULL; 999 } 1000 1001 #if defined(sun4v) 1002 if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 1003 (void) hsvc_unregister(&nxgep->niu_hsvc); 1004 nxgep->niu_hsvc_available = B_FALSE; 1005 } 1006 #endif 1007 /* 1008 * Stop any further interrupts. 1009 */ 1010 nxge_remove_intrs(nxgep); 1011 1012 /* remove soft interrups */ 1013 nxge_remove_soft_intrs(nxgep); 1014 1015 /* 1016 * Stop the device and free resources. 1017 */ 1018 if (!isLDOMguest(nxgep)) { 1019 nxge_destroy_dev(nxgep); 1020 } 1021 1022 /* 1023 * Tear down the ndd parameters setup. 1024 */ 1025 nxge_destroy_param(nxgep); 1026 1027 /* 1028 * Tear down the kstat setup. 1029 */ 1030 nxge_destroy_kstats(nxgep); 1031 1032 /* 1033 * Destroy all mutexes. 1034 */ 1035 nxge_destroy_mutexes(nxgep); 1036 1037 /* 1038 * Remove the list of ndd parameters which 1039 * were setup during attach. 1040 */ 1041 if (nxgep->dip) { 1042 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1043 " nxge_unattach: remove all properties")); 1044 1045 (void) ddi_prop_remove_all(nxgep->dip); 1046 } 1047 1048 #if NXGE_PROPERTY 1049 nxge_remove_hard_properties(nxgep); 1050 #endif 1051 1052 /* 1053 * Unmap the register setup. 1054 */ 1055 nxge_unmap_regs(nxgep); 1056 1057 nxge_fm_fini(nxgep); 1058 1059 ddi_soft_state_free(nxge_list, nxgep->instance); 1060 1061 NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 1062 } 1063 1064 #if defined(sun4v) 1065 int 1066 nxge_hsvc_register( 1067 nxge_t *nxgep) 1068 { 1069 nxge_status_t status; 1070 1071 if (nxgep->niu_type == N2_NIU) { 1072 nxgep->niu_hsvc_available = B_FALSE; 1073 bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t)); 1074 if ((status = hsvc_register(&nxgep->niu_hsvc, 1075 &nxgep->niu_min_ver)) != 0) { 1076 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1077 "nxge_attach: %s: cannot negotiate " 1078 "hypervisor services revision %d group: 0x%lx " 1079 "major: 0x%lx minor: 0x%lx errno: %d", 1080 niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1081 niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1082 niu_hsvc.hsvc_minor, status)); 1083 return (DDI_FAILURE); 1084 } 1085 nxgep->niu_hsvc_available = B_TRUE; 1086 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1087 "NIU Hypervisor service enabled")); 1088 } 1089 1090 return (DDI_SUCCESS); 1091 } 1092 #endif 1093 1094 static char n2_siu_name[] = "niu"; 1095 1096 static nxge_status_t 1097 nxge_map_regs(p_nxge_t nxgep) 1098 { 1099 int ddi_status = DDI_SUCCESS; 1100 p_dev_regs_t dev_regs; 1101 char buf[MAXPATHLEN + 1]; 1102 char *devname; 1103 #ifdef NXGE_DEBUG 1104 char *sysname; 1105 #endif 1106 off_t regsize; 1107 nxge_status_t status = NXGE_OK; 1108 #if !defined(_BIG_ENDIAN) 1109 off_t pci_offset; 1110 uint16_t pcie_devctl; 1111 #endif 1112 1113 if (isLDOMguest(nxgep)) { 1114 return (nxge_guest_regs_map(nxgep)); 1115 } 1116 1117 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 1118 nxgep->dev_regs = NULL; 1119 dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 1120 dev_regs->nxge_regh = NULL; 1121 dev_regs->nxge_pciregh = NULL; 1122 dev_regs->nxge_msix_regh = NULL; 1123 dev_regs->nxge_vir_regh = NULL; 1124 dev_regs->nxge_vir2_regh = NULL; 1125 nxgep->niu_type = NIU_TYPE_NONE; 1126 1127 devname = ddi_pathname(nxgep->dip, buf); 1128 ASSERT(strlen(devname) > 0); 1129 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1130 "nxge_map_regs: pathname devname %s", devname)); 1131 1132 /* 1133 * The driver is running on a N2-NIU system if devname is something 1134 * like "/niu@80/network@0" 1135 */ 1136 if (strstr(devname, n2_siu_name)) { 1137 /* N2/NIU */ 1138 nxgep->niu_type = N2_NIU; 1139 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1140 "nxge_map_regs: N2/NIU devname %s", devname)); 1141 /* get function number */ 1142 nxgep->function_num = 1143 (devname[strlen(devname) -1] == '1' ? 1 : 0); 1144 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1145 "nxge_map_regs: N2/NIU function number %d", 1146 nxgep->function_num)); 1147 } else { 1148 int *prop_val; 1149 uint_t prop_len; 1150 uint8_t func_num; 1151 1152 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 1153 0, "reg", 1154 &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 1155 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1156 "Reg property not found")); 1157 ddi_status = DDI_FAILURE; 1158 goto nxge_map_regs_fail0; 1159 1160 } else { 1161 func_num = (prop_val[0] >> 8) & 0x7; 1162 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1163 "Reg property found: fun # %d", 1164 func_num)); 1165 nxgep->function_num = func_num; 1166 if (isLDOMguest(nxgep)) { 1167 nxgep->function_num /= 2; 1168 return (NXGE_OK); 1169 } 1170 ddi_prop_free(prop_val); 1171 } 1172 } 1173 1174 switch (nxgep->niu_type) { 1175 default: 1176 (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 1177 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1178 "nxge_map_regs: pci config size 0x%x", regsize)); 1179 1180 ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 1181 (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 1182 &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 1183 if (ddi_status != DDI_SUCCESS) { 1184 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1185 "ddi_map_regs, nxge bus config regs failed")); 1186 goto nxge_map_regs_fail0; 1187 } 1188 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1189 "nxge_map_reg: PCI config addr 0x%0llx " 1190 " handle 0x%0llx", dev_regs->nxge_pciregp, 1191 dev_regs->nxge_pciregh)); 1192 /* 1193 * IMP IMP 1194 * workaround for bit swapping bug in HW 1195 * which ends up in no-snoop = yes 1196 * resulting, in DMA not synched properly 1197 */ 1198 #if !defined(_BIG_ENDIAN) 1199 /* workarounds for x86 systems */ 1200 pci_offset = 0x80 + PCIE_DEVCTL; 1201 pcie_devctl = 0x0; 1202 pcie_devctl &= PCIE_DEVCTL_ENABLE_NO_SNOOP; 1203 pcie_devctl |= PCIE_DEVCTL_RO_EN; 1204 pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 1205 pcie_devctl); 1206 #endif 1207 1208 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1209 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1210 "nxge_map_regs: pio size 0x%x", regsize)); 1211 /* set up the device mapped register */ 1212 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1213 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1214 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1215 if (ddi_status != DDI_SUCCESS) { 1216 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1217 "ddi_map_regs for Neptune global reg failed")); 1218 goto nxge_map_regs_fail1; 1219 } 1220 1221 /* set up the msi/msi-x mapped register */ 1222 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1223 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1224 "nxge_map_regs: msix size 0x%x", regsize)); 1225 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1226 (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 1227 &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 1228 if (ddi_status != DDI_SUCCESS) { 1229 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1230 "ddi_map_regs for msi reg failed")); 1231 goto nxge_map_regs_fail2; 1232 } 1233 1234 /* set up the vio region mapped register */ 1235 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1236 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1237 "nxge_map_regs: vio size 0x%x", regsize)); 1238 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1239 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1240 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1241 1242 if (ddi_status != DDI_SUCCESS) { 1243 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1244 "ddi_map_regs for nxge vio reg failed")); 1245 goto nxge_map_regs_fail3; 1246 } 1247 nxgep->dev_regs = dev_regs; 1248 1249 NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 1250 NPI_PCI_ADD_HANDLE_SET(nxgep, 1251 (npi_reg_ptr_t)dev_regs->nxge_pciregp); 1252 NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 1253 NPI_MSI_ADD_HANDLE_SET(nxgep, 1254 (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 1255 1256 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1257 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1258 1259 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1260 NPI_REG_ADD_HANDLE_SET(nxgep, 1261 (npi_reg_ptr_t)dev_regs->nxge_regp); 1262 1263 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1264 NPI_VREG_ADD_HANDLE_SET(nxgep, 1265 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1266 1267 break; 1268 1269 case N2_NIU: 1270 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 1271 /* 1272 * Set up the device mapped register (FWARC 2006/556) 1273 * (changed back to 1: reg starts at 1!) 1274 */ 1275 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1276 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1277 "nxge_map_regs: dev size 0x%x", regsize)); 1278 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1279 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1280 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1281 1282 if (ddi_status != DDI_SUCCESS) { 1283 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1284 "ddi_map_regs for N2/NIU, global reg failed ")); 1285 goto nxge_map_regs_fail1; 1286 } 1287 1288 /* set up the first vio region mapped register */ 1289 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1290 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1291 "nxge_map_regs: vio (1) size 0x%x", regsize)); 1292 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1293 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1294 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1295 1296 if (ddi_status != DDI_SUCCESS) { 1297 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1298 "ddi_map_regs for nxge vio reg failed")); 1299 goto nxge_map_regs_fail2; 1300 } 1301 /* set up the second vio region mapped register */ 1302 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1303 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1304 "nxge_map_regs: vio (3) size 0x%x", regsize)); 1305 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1306 (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 1307 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 1308 1309 if (ddi_status != DDI_SUCCESS) { 1310 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1311 "ddi_map_regs for nxge vio2 reg failed")); 1312 goto nxge_map_regs_fail3; 1313 } 1314 nxgep->dev_regs = dev_regs; 1315 1316 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1317 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1318 1319 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1320 NPI_REG_ADD_HANDLE_SET(nxgep, 1321 (npi_reg_ptr_t)dev_regs->nxge_regp); 1322 1323 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1324 NPI_VREG_ADD_HANDLE_SET(nxgep, 1325 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1326 1327 NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 1328 NPI_V2REG_ADD_HANDLE_SET(nxgep, 1329 (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 1330 1331 break; 1332 } 1333 1334 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 1335 " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 1336 1337 goto nxge_map_regs_exit; 1338 nxge_map_regs_fail3: 1339 if (dev_regs->nxge_msix_regh) { 1340 ddi_regs_map_free(&dev_regs->nxge_msix_regh); 1341 } 1342 if (dev_regs->nxge_vir_regh) { 1343 ddi_regs_map_free(&dev_regs->nxge_regh); 1344 } 1345 nxge_map_regs_fail2: 1346 if (dev_regs->nxge_regh) { 1347 ddi_regs_map_free(&dev_regs->nxge_regh); 1348 } 1349 nxge_map_regs_fail1: 1350 if (dev_regs->nxge_pciregh) { 1351 ddi_regs_map_free(&dev_regs->nxge_pciregh); 1352 } 1353 nxge_map_regs_fail0: 1354 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 1355 kmem_free(dev_regs, sizeof (dev_regs_t)); 1356 1357 nxge_map_regs_exit: 1358 if (ddi_status != DDI_SUCCESS) 1359 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1360 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 1361 return (status); 1362 } 1363 1364 static void 1365 nxge_unmap_regs(p_nxge_t nxgep) 1366 { 1367 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1368 1369 if (isLDOMguest(nxgep)) { 1370 nxge_guest_regs_map_free(nxgep); 1371 return; 1372 } 1373 1374 if (nxgep->dev_regs) { 1375 if (nxgep->dev_regs->nxge_pciregh) { 1376 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1377 "==> nxge_unmap_regs: bus")); 1378 ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 1379 nxgep->dev_regs->nxge_pciregh = NULL; 1380 } 1381 if (nxgep->dev_regs->nxge_regh) { 1382 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1383 "==> nxge_unmap_regs: device registers")); 1384 ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 1385 nxgep->dev_regs->nxge_regh = NULL; 1386 } 1387 if (nxgep->dev_regs->nxge_msix_regh) { 1388 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1389 "==> nxge_unmap_regs: device interrupts")); 1390 ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 1391 nxgep->dev_regs->nxge_msix_regh = NULL; 1392 } 1393 if (nxgep->dev_regs->nxge_vir_regh) { 1394 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1395 "==> nxge_unmap_regs: vio region")); 1396 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 1397 nxgep->dev_regs->nxge_vir_regh = NULL; 1398 } 1399 if (nxgep->dev_regs->nxge_vir2_regh) { 1400 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1401 "==> nxge_unmap_regs: vio2 region")); 1402 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 1403 nxgep->dev_regs->nxge_vir2_regh = NULL; 1404 } 1405 1406 kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 1407 nxgep->dev_regs = NULL; 1408 } 1409 1410 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 1411 } 1412 1413 static nxge_status_t 1414 nxge_setup_mutexes(p_nxge_t nxgep) 1415 { 1416 int ddi_status = DDI_SUCCESS; 1417 nxge_status_t status = NXGE_OK; 1418 nxge_classify_t *classify_ptr; 1419 int partition; 1420 1421 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 1422 1423 /* 1424 * Get the interrupt cookie so the mutexes can be 1425 * Initialized. 1426 */ 1427 if (isLDOMguest(nxgep)) { 1428 nxgep->interrupt_cookie = 0; 1429 } else { 1430 ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1431 &nxgep->interrupt_cookie); 1432 1433 if (ddi_status != DDI_SUCCESS) { 1434 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1435 "<== nxge_setup_mutexes: failed 0x%x", 1436 ddi_status)); 1437 goto nxge_setup_mutexes_exit; 1438 } 1439 } 1440 1441 cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 1442 MUTEX_INIT(&nxgep->poll_lock, NULL, 1443 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1444 1445 /* 1446 * Initialize mutexes for this device. 1447 */ 1448 MUTEX_INIT(nxgep->genlock, NULL, 1449 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1450 MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 1451 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1452 MUTEX_INIT(&nxgep->mif_lock, NULL, 1453 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1454 MUTEX_INIT(&nxgep->group_lock, NULL, 1455 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1456 RW_INIT(&nxgep->filter_lock, NULL, 1457 RW_DRIVER, (void *)nxgep->interrupt_cookie); 1458 1459 classify_ptr = &nxgep->classifier; 1460 /* 1461 * FFLP Mutexes are never used in interrupt context 1462 * as fflp operation can take very long time to 1463 * complete and hence not suitable to invoke from interrupt 1464 * handlers. 1465 */ 1466 MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 1467 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1468 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1469 MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 1470 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1471 for (partition = 0; partition < MAX_PARTITION; partition++) { 1472 MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 1473 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1474 } 1475 } 1476 1477 nxge_setup_mutexes_exit: 1478 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1479 "<== nxge_setup_mutexes status = %x", status)); 1480 1481 if (ddi_status != DDI_SUCCESS) 1482 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1483 1484 return (status); 1485 } 1486 1487 static void 1488 nxge_destroy_mutexes(p_nxge_t nxgep) 1489 { 1490 int partition; 1491 nxge_classify_t *classify_ptr; 1492 1493 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 1494 RW_DESTROY(&nxgep->filter_lock); 1495 MUTEX_DESTROY(&nxgep->group_lock); 1496 MUTEX_DESTROY(&nxgep->mif_lock); 1497 MUTEX_DESTROY(&nxgep->ouraddr_lock); 1498 MUTEX_DESTROY(nxgep->genlock); 1499 1500 classify_ptr = &nxgep->classifier; 1501 MUTEX_DESTROY(&classify_ptr->tcam_lock); 1502 1503 /* Destroy all polling resources. */ 1504 MUTEX_DESTROY(&nxgep->poll_lock); 1505 cv_destroy(&nxgep->poll_cv); 1506 1507 /* free data structures, based on HW type */ 1508 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1509 MUTEX_DESTROY(&classify_ptr->fcram_lock); 1510 for (partition = 0; partition < MAX_PARTITION; partition++) { 1511 MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 1512 } 1513 } 1514 1515 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 1516 } 1517 1518 nxge_status_t 1519 nxge_init(p_nxge_t nxgep) 1520 { 1521 nxge_status_t status = NXGE_OK; 1522 1523 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 1524 1525 if (nxgep->drv_state & STATE_HW_INITIALIZED) { 1526 return (status); 1527 } 1528 1529 /* 1530 * Allocate system memory for the receive/transmit buffer blocks 1531 * and receive/transmit descriptor rings. 1532 */ 1533 status = nxge_alloc_mem_pool(nxgep); 1534 if (status != NXGE_OK) { 1535 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 1536 goto nxge_init_fail1; 1537 } 1538 1539 if (!isLDOMguest(nxgep)) { 1540 /* 1541 * Initialize and enable the TXC registers. 1542 * (Globally enable the Tx controller, 1543 * enable the port, configure the dma channel bitmap, 1544 * configure the max burst size). 1545 */ 1546 status = nxge_txc_init(nxgep); 1547 if (status != NXGE_OK) { 1548 NXGE_ERROR_MSG((nxgep, 1549 NXGE_ERR_CTL, "init txc failed\n")); 1550 goto nxge_init_fail2; 1551 } 1552 } 1553 1554 /* 1555 * Initialize and enable TXDMA channels. 1556 */ 1557 status = nxge_init_txdma_channels(nxgep); 1558 if (status != NXGE_OK) { 1559 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 1560 goto nxge_init_fail3; 1561 } 1562 1563 /* 1564 * Initialize and enable RXDMA channels. 1565 */ 1566 status = nxge_init_rxdma_channels(nxgep); 1567 if (status != NXGE_OK) { 1568 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 1569 goto nxge_init_fail4; 1570 } 1571 1572 /* 1573 * The guest domain is now done. 1574 */ 1575 if (isLDOMguest(nxgep)) { 1576 nxgep->drv_state |= STATE_HW_INITIALIZED; 1577 goto nxge_init_exit; 1578 } 1579 1580 /* 1581 * Initialize TCAM and FCRAM (Neptune). 1582 */ 1583 status = nxge_classify_init(nxgep); 1584 if (status != NXGE_OK) { 1585 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 1586 goto nxge_init_fail5; 1587 } 1588 1589 /* 1590 * Initialize ZCP 1591 */ 1592 status = nxge_zcp_init(nxgep); 1593 if (status != NXGE_OK) { 1594 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 1595 goto nxge_init_fail5; 1596 } 1597 1598 /* 1599 * Initialize IPP. 1600 */ 1601 status = nxge_ipp_init(nxgep); 1602 if (status != NXGE_OK) { 1603 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 1604 goto nxge_init_fail5; 1605 } 1606 1607 /* 1608 * Initialize the MAC block. 1609 */ 1610 status = nxge_mac_init(nxgep); 1611 if (status != NXGE_OK) { 1612 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 1613 goto nxge_init_fail5; 1614 } 1615 1616 nxge_intrs_enable(nxgep); /* XXX What changes do I need to make here? */ 1617 1618 /* 1619 * Enable hardware interrupts. 1620 */ 1621 nxge_intr_hw_enable(nxgep); 1622 nxgep->drv_state |= STATE_HW_INITIALIZED; 1623 1624 goto nxge_init_exit; 1625 1626 nxge_init_fail5: 1627 nxge_uninit_rxdma_channels(nxgep); 1628 nxge_init_fail4: 1629 nxge_uninit_txdma_channels(nxgep); 1630 nxge_init_fail3: 1631 if (!isLDOMguest(nxgep)) { 1632 (void) nxge_txc_uninit(nxgep); 1633 } 1634 nxge_init_fail2: 1635 nxge_free_mem_pool(nxgep); 1636 nxge_init_fail1: 1637 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1638 "<== nxge_init status (failed) = 0x%08x", status)); 1639 return (status); 1640 1641 nxge_init_exit: 1642 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 1643 status)); 1644 return (status); 1645 } 1646 1647 1648 timeout_id_t 1649 nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 1650 { 1651 if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 1652 return (timeout(func, (caddr_t)nxgep, 1653 drv_usectohz(1000 * msec))); 1654 } 1655 return (NULL); 1656 } 1657 1658 /*ARGSUSED*/ 1659 void 1660 nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 1661 { 1662 if (timerid) { 1663 (void) untimeout(timerid); 1664 } 1665 } 1666 1667 void 1668 nxge_uninit(p_nxge_t nxgep) 1669 { 1670 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 1671 1672 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1673 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1674 "==> nxge_uninit: not initialized")); 1675 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1676 "<== nxge_uninit")); 1677 return; 1678 } 1679 1680 /* stop timer */ 1681 if (nxgep->nxge_timerid) { 1682 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 1683 nxgep->nxge_timerid = 0; 1684 } 1685 1686 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1687 (void) nxge_intr_hw_disable(nxgep); 1688 1689 /* 1690 * Reset the receive MAC side. 1691 */ 1692 (void) nxge_rx_mac_disable(nxgep); 1693 1694 /* Disable and soft reset the IPP */ 1695 if (!isLDOMguest(nxgep)) 1696 (void) nxge_ipp_disable(nxgep); 1697 1698 /* Free classification resources */ 1699 (void) nxge_classify_uninit(nxgep); 1700 1701 /* 1702 * Reset the transmit/receive DMA side. 1703 */ 1704 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 1705 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1706 1707 nxge_uninit_txdma_channels(nxgep); 1708 nxge_uninit_rxdma_channels(nxgep); 1709 1710 /* 1711 * Reset the transmit MAC side. 1712 */ 1713 (void) nxge_tx_mac_disable(nxgep); 1714 1715 nxge_free_mem_pool(nxgep); 1716 1717 /* 1718 * Start the timer if the reset flag is not set. 1719 * If this reset flag is set, the link monitor 1720 * will not be started in order to stop furthur bus 1721 * activities coming from this interface. 1722 * The driver will start the monitor function 1723 * if the interface was initialized again later. 1724 */ 1725 if (!nxge_peu_reset_enable) { 1726 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1727 } 1728 1729 nxgep->drv_state &= ~STATE_HW_INITIALIZED; 1730 1731 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 1732 "nxge_mblks_pending %d", nxge_mblks_pending)); 1733 } 1734 1735 void 1736 nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 1737 { 1738 #if defined(__i386) 1739 size_t reg; 1740 #else 1741 uint64_t reg; 1742 #endif 1743 uint64_t regdata; 1744 int i, retry; 1745 1746 bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 1747 regdata = 0; 1748 retry = 1; 1749 1750 for (i = 0; i < retry; i++) { 1751 NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 1752 } 1753 bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 1754 } 1755 1756 void 1757 nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 1758 { 1759 #if defined(__i386) 1760 size_t reg; 1761 #else 1762 uint64_t reg; 1763 #endif 1764 uint64_t buf[2]; 1765 1766 bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 1767 #if defined(__i386) 1768 reg = (size_t)buf[0]; 1769 #else 1770 reg = buf[0]; 1771 #endif 1772 1773 NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 1774 } 1775 1776 1777 nxge_os_mutex_t nxgedebuglock; 1778 int nxge_debug_init = 0; 1779 1780 /*ARGSUSED*/ 1781 /*VARARGS*/ 1782 void 1783 nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 1784 { 1785 char msg_buffer[1048]; 1786 char prefix_buffer[32]; 1787 int instance; 1788 uint64_t debug_level; 1789 int cmn_level = CE_CONT; 1790 va_list ap; 1791 1792 if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1793 /* In case a developer has changed nxge_debug_level. */ 1794 if (nxgep->nxge_debug_level != nxge_debug_level) 1795 nxgep->nxge_debug_level = nxge_debug_level; 1796 } 1797 1798 debug_level = (nxgep == NULL) ? nxge_debug_level : 1799 nxgep->nxge_debug_level; 1800 1801 if ((level & debug_level) || 1802 (level == NXGE_NOTE) || 1803 (level == NXGE_ERR_CTL)) { 1804 /* do the msg processing */ 1805 if (nxge_debug_init == 0) { 1806 MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 1807 nxge_debug_init = 1; 1808 } 1809 1810 MUTEX_ENTER(&nxgedebuglock); 1811 1812 if ((level & NXGE_NOTE)) { 1813 cmn_level = CE_NOTE; 1814 } 1815 1816 if (level & NXGE_ERR_CTL) { 1817 cmn_level = CE_WARN; 1818 } 1819 1820 va_start(ap, fmt); 1821 (void) vsprintf(msg_buffer, fmt, ap); 1822 va_end(ap); 1823 if (nxgep == NULL) { 1824 instance = -1; 1825 (void) sprintf(prefix_buffer, "%s :", "nxge"); 1826 } else { 1827 instance = nxgep->instance; 1828 (void) sprintf(prefix_buffer, 1829 "%s%d :", "nxge", instance); 1830 } 1831 1832 MUTEX_EXIT(&nxgedebuglock); 1833 cmn_err(cmn_level, "!%s %s\n", 1834 prefix_buffer, msg_buffer); 1835 1836 } 1837 } 1838 1839 char * 1840 nxge_dump_packet(char *addr, int size) 1841 { 1842 uchar_t *ap = (uchar_t *)addr; 1843 int i; 1844 static char etherbuf[1024]; 1845 char *cp = etherbuf; 1846 char digits[] = "0123456789abcdef"; 1847 1848 if (!size) 1849 size = 60; 1850 1851 if (size > MAX_DUMP_SZ) { 1852 /* Dump the leading bytes */ 1853 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1854 if (*ap > 0x0f) 1855 *cp++ = digits[*ap >> 4]; 1856 *cp++ = digits[*ap++ & 0xf]; 1857 *cp++ = ':'; 1858 } 1859 for (i = 0; i < 20; i++) 1860 *cp++ = '.'; 1861 /* Dump the last MAX_DUMP_SZ/2 bytes */ 1862 ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 1863 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1864 if (*ap > 0x0f) 1865 *cp++ = digits[*ap >> 4]; 1866 *cp++ = digits[*ap++ & 0xf]; 1867 *cp++ = ':'; 1868 } 1869 } else { 1870 for (i = 0; i < size; i++) { 1871 if (*ap > 0x0f) 1872 *cp++ = digits[*ap >> 4]; 1873 *cp++ = digits[*ap++ & 0xf]; 1874 *cp++ = ':'; 1875 } 1876 } 1877 *--cp = 0; 1878 return (etherbuf); 1879 } 1880 1881 #ifdef NXGE_DEBUG 1882 static void 1883 nxge_test_map_regs(p_nxge_t nxgep) 1884 { 1885 ddi_acc_handle_t cfg_handle; 1886 p_pci_cfg_t cfg_ptr; 1887 ddi_acc_handle_t dev_handle; 1888 char *dev_ptr; 1889 ddi_acc_handle_t pci_config_handle; 1890 uint32_t regval; 1891 int i; 1892 1893 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 1894 1895 dev_handle = nxgep->dev_regs->nxge_regh; 1896 dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 1897 1898 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1899 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1900 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1901 1902 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1903 "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 1904 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1905 "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 1906 &cfg_ptr->vendorid)); 1907 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1908 "\tvendorid 0x%x devid 0x%x", 1909 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 1910 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 1911 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1912 "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 1913 "bar1c 0x%x", 1914 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 1915 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 1916 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 1917 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 1918 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1919 "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 1920 "base 28 0x%x bar2c 0x%x\n", 1921 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 1922 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 1923 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 1924 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 1925 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1926 "\nNeptune PCI BAR: base30 0x%x\n", 1927 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 1928 1929 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1930 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1931 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1932 "first 0x%llx second 0x%llx third 0x%llx " 1933 "last 0x%llx ", 1934 NXGE_PIO_READ64(dev_handle, 1935 (uint64_t *)(dev_ptr + 0), 0), 1936 NXGE_PIO_READ64(dev_handle, 1937 (uint64_t *)(dev_ptr + 8), 0), 1938 NXGE_PIO_READ64(dev_handle, 1939 (uint64_t *)(dev_ptr + 16), 0), 1940 NXGE_PIO_READ64(cfg_handle, 1941 (uint64_t *)(dev_ptr + 24), 0))); 1942 } 1943 } 1944 1945 #endif 1946 1947 static void 1948 nxge_suspend(p_nxge_t nxgep) 1949 { 1950 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 1951 1952 nxge_intrs_disable(nxgep); 1953 nxge_destroy_dev(nxgep); 1954 1955 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 1956 } 1957 1958 static nxge_status_t 1959 nxge_resume(p_nxge_t nxgep) 1960 { 1961 nxge_status_t status = NXGE_OK; 1962 1963 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 1964 1965 nxgep->suspended = DDI_RESUME; 1966 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1967 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1968 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 1969 (void) nxge_rx_mac_enable(nxgep); 1970 (void) nxge_tx_mac_enable(nxgep); 1971 nxge_intrs_enable(nxgep); 1972 nxgep->suspended = 0; 1973 1974 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1975 "<== nxge_resume status = 0x%x", status)); 1976 return (status); 1977 } 1978 1979 static nxge_status_t 1980 nxge_setup_dev(p_nxge_t nxgep) 1981 { 1982 nxge_status_t status = NXGE_OK; 1983 1984 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 1985 nxgep->mac.portnum)); 1986 1987 status = nxge_link_init(nxgep); 1988 1989 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 1990 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1991 "port%d Bad register acc handle", nxgep->mac.portnum)); 1992 status = NXGE_ERROR; 1993 } 1994 1995 if (status != NXGE_OK) { 1996 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1997 " nxge_setup_dev status " 1998 "(xcvr init 0x%08x)", status)); 1999 goto nxge_setup_dev_exit; 2000 } 2001 2002 nxge_setup_dev_exit: 2003 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2004 "<== nxge_setup_dev port %d status = 0x%08x", 2005 nxgep->mac.portnum, status)); 2006 2007 return (status); 2008 } 2009 2010 static void 2011 nxge_destroy_dev(p_nxge_t nxgep) 2012 { 2013 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 2014 2015 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2016 2017 (void) nxge_hw_stop(nxgep); 2018 2019 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 2020 } 2021 2022 static nxge_status_t 2023 nxge_setup_system_dma_pages(p_nxge_t nxgep) 2024 { 2025 int ddi_status = DDI_SUCCESS; 2026 uint_t count; 2027 ddi_dma_cookie_t cookie; 2028 uint_t iommu_pagesize; 2029 nxge_status_t status = NXGE_OK; 2030 2031 NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 2032 nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 2033 if (nxgep->niu_type != N2_NIU) { 2034 iommu_pagesize = dvma_pagesize(nxgep->dip); 2035 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2036 " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2037 " default_block_size %d iommu_pagesize %d", 2038 nxgep->sys_page_sz, 2039 ddi_ptob(nxgep->dip, (ulong_t)1), 2040 nxgep->rx_default_block_size, 2041 iommu_pagesize)); 2042 2043 if (iommu_pagesize != 0) { 2044 if (nxgep->sys_page_sz == iommu_pagesize) { 2045 if (iommu_pagesize > 0x4000) 2046 nxgep->sys_page_sz = 0x4000; 2047 } else { 2048 if (nxgep->sys_page_sz > iommu_pagesize) 2049 nxgep->sys_page_sz = iommu_pagesize; 2050 } 2051 } 2052 } 2053 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2054 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2055 "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2056 "default_block_size %d page mask %d", 2057 nxgep->sys_page_sz, 2058 ddi_ptob(nxgep->dip, (ulong_t)1), 2059 nxgep->rx_default_block_size, 2060 nxgep->sys_page_mask)); 2061 2062 2063 switch (nxgep->sys_page_sz) { 2064 default: 2065 nxgep->sys_page_sz = 0x1000; 2066 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2067 nxgep->rx_default_block_size = 0x1000; 2068 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2069 break; 2070 case 0x1000: 2071 nxgep->rx_default_block_size = 0x1000; 2072 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2073 break; 2074 case 0x2000: 2075 nxgep->rx_default_block_size = 0x2000; 2076 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2077 break; 2078 case 0x4000: 2079 nxgep->rx_default_block_size = 0x4000; 2080 nxgep->rx_bksize_code = RBR_BKSIZE_16K; 2081 break; 2082 case 0x8000: 2083 nxgep->rx_default_block_size = 0x8000; 2084 nxgep->rx_bksize_code = RBR_BKSIZE_32K; 2085 break; 2086 } 2087 2088 #ifndef USE_RX_BIG_BUF 2089 nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 2090 #else 2091 nxgep->rx_default_block_size = 0x2000; 2092 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2093 #endif 2094 /* 2095 * Get the system DMA burst size. 2096 */ 2097 ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 2098 DDI_DMA_DONTWAIT, 0, 2099 &nxgep->dmasparehandle); 2100 if (ddi_status != DDI_SUCCESS) { 2101 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2102 "ddi_dma_alloc_handle: failed " 2103 " status 0x%x", ddi_status)); 2104 goto nxge_get_soft_properties_exit; 2105 } 2106 2107 ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 2108 (caddr_t)nxgep->dmasparehandle, 2109 sizeof (nxgep->dmasparehandle), 2110 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2111 DDI_DMA_DONTWAIT, 0, 2112 &cookie, &count); 2113 if (ddi_status != DDI_DMA_MAPPED) { 2114 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2115 "Binding spare handle to find system" 2116 " burstsize failed.")); 2117 ddi_status = DDI_FAILURE; 2118 goto nxge_get_soft_properties_fail1; 2119 } 2120 2121 nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 2122 (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 2123 2124 nxge_get_soft_properties_fail1: 2125 ddi_dma_free_handle(&nxgep->dmasparehandle); 2126 2127 nxge_get_soft_properties_exit: 2128 2129 if (ddi_status != DDI_SUCCESS) 2130 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2131 2132 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2133 "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 2134 return (status); 2135 } 2136 2137 static nxge_status_t 2138 nxge_alloc_mem_pool(p_nxge_t nxgep) 2139 { 2140 nxge_status_t status = NXGE_OK; 2141 2142 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 2143 2144 status = nxge_alloc_rx_mem_pool(nxgep); 2145 if (status != NXGE_OK) { 2146 return (NXGE_ERROR); 2147 } 2148 2149 status = nxge_alloc_tx_mem_pool(nxgep); 2150 if (status != NXGE_OK) { 2151 nxge_free_rx_mem_pool(nxgep); 2152 return (NXGE_ERROR); 2153 } 2154 2155 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 2156 return (NXGE_OK); 2157 } 2158 2159 static void 2160 nxge_free_mem_pool(p_nxge_t nxgep) 2161 { 2162 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 2163 2164 nxge_free_rx_mem_pool(nxgep); 2165 nxge_free_tx_mem_pool(nxgep); 2166 2167 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 2168 } 2169 2170 nxge_status_t 2171 nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 2172 { 2173 uint32_t rdc_max; 2174 p_nxge_dma_pt_cfg_t p_all_cfgp; 2175 p_nxge_hw_pt_cfg_t p_cfgp; 2176 p_nxge_dma_pool_t dma_poolp; 2177 p_nxge_dma_common_t *dma_buf_p; 2178 p_nxge_dma_pool_t dma_cntl_poolp; 2179 p_nxge_dma_common_t *dma_cntl_p; 2180 uint32_t *num_chunks; /* per dma */ 2181 nxge_status_t status = NXGE_OK; 2182 2183 uint32_t nxge_port_rbr_size; 2184 uint32_t nxge_port_rbr_spare_size; 2185 uint32_t nxge_port_rcr_size; 2186 uint32_t rx_cntl_alloc_size; 2187 2188 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 2189 2190 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2191 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2192 rdc_max = NXGE_MAX_RDCS; 2193 2194 /* 2195 * Allocate memory for the common DMA data structures. 2196 */ 2197 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2198 KM_SLEEP); 2199 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2200 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2201 2202 dma_cntl_poolp = (p_nxge_dma_pool_t) 2203 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2204 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2205 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2206 2207 num_chunks = (uint32_t *)KMEM_ZALLOC( 2208 sizeof (uint32_t) * rdc_max, KM_SLEEP); 2209 2210 /* 2211 * Assume that each DMA channel will be configured with 2212 * the default block size. 2213 * rbr block counts are modulo the batch count (16). 2214 */ 2215 nxge_port_rbr_size = p_all_cfgp->rbr_size; 2216 nxge_port_rcr_size = p_all_cfgp->rcr_size; 2217 2218 if (!nxge_port_rbr_size) { 2219 nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 2220 } 2221 if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 2222 nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 2223 (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 2224 } 2225 2226 p_all_cfgp->rbr_size = nxge_port_rbr_size; 2227 nxge_port_rbr_spare_size = nxge_rbr_spare_size; 2228 2229 if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 2230 nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 2231 (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 2232 } 2233 if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 2234 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2235 "nxge_alloc_rx_mem_pool: RBR size too high %d, " 2236 "set to default %d", 2237 nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 2238 nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 2239 } 2240 if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 2241 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2242 "nxge_alloc_rx_mem_pool: RCR too high %d, " 2243 "set to default %d", 2244 nxge_port_rcr_size, RCR_DEFAULT_MAX)); 2245 nxge_port_rcr_size = RCR_DEFAULT_MAX; 2246 } 2247 2248 /* 2249 * N2/NIU has limitation on the descriptor sizes (contiguous 2250 * memory allocation on data buffers to 4M (contig_mem_alloc) 2251 * and little endian for control buffers (must use the ddi/dki mem alloc 2252 * function). 2253 */ 2254 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2255 if (nxgep->niu_type == N2_NIU) { 2256 nxge_port_rbr_spare_size = 0; 2257 if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 2258 (!ISP2(nxge_port_rbr_size))) { 2259 nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 2260 } 2261 if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 2262 (!ISP2(nxge_port_rcr_size))) { 2263 nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 2264 } 2265 } 2266 #endif 2267 2268 /* 2269 * Addresses of receive block ring, receive completion ring and the 2270 * mailbox must be all cache-aligned (64 bytes). 2271 */ 2272 rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 2273 rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 2274 rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 2275 rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 2276 2277 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 2278 "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 2279 "nxge_port_rcr_size = %d " 2280 "rx_cntl_alloc_size = %d", 2281 nxge_port_rbr_size, nxge_port_rbr_spare_size, 2282 nxge_port_rcr_size, 2283 rx_cntl_alloc_size)); 2284 2285 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2286 if (nxgep->niu_type == N2_NIU) { 2287 uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2288 (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2289 2290 if (!ISP2(rx_buf_alloc_size)) { 2291 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2292 "==> nxge_alloc_rx_mem_pool: " 2293 " must be power of 2")); 2294 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2295 goto nxge_alloc_rx_mem_pool_exit; 2296 } 2297 2298 if (rx_buf_alloc_size > (1 << 22)) { 2299 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2300 "==> nxge_alloc_rx_mem_pool: " 2301 " limit size to 4M")); 2302 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2303 goto nxge_alloc_rx_mem_pool_exit; 2304 } 2305 2306 if (rx_cntl_alloc_size < 0x2000) { 2307 rx_cntl_alloc_size = 0x2000; 2308 } 2309 } 2310 #endif 2311 nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 2312 nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2313 nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2314 nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 2315 2316 dma_poolp->ndmas = p_cfgp->max_rdcs; 2317 dma_poolp->num_chunks = num_chunks; 2318 dma_poolp->buf_allocated = B_TRUE; 2319 nxgep->rx_buf_pool_p = dma_poolp; 2320 dma_poolp->dma_buf_pool_p = dma_buf_p; 2321 2322 dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 2323 dma_cntl_poolp->buf_allocated = B_TRUE; 2324 nxgep->rx_cntl_pool_p = dma_cntl_poolp; 2325 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 2326 2327 /* Allocate the receive rings, too. */ 2328 nxgep->rx_rbr_rings = 2329 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2330 nxgep->rx_rbr_rings->rbr_rings = 2331 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2332 nxgep->rx_rcr_rings = 2333 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2334 nxgep->rx_rcr_rings->rcr_rings = 2335 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2336 nxgep->rx_mbox_areas_p = 2337 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2338 nxgep->rx_mbox_areas_p->rxmbox_areas = 2339 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2340 2341 nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2342 p_cfgp->max_rdcs; 2343 2344 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2345 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2346 2347 nxge_alloc_rx_mem_pool_exit: 2348 return (status); 2349 } 2350 2351 /* 2352 * nxge_alloc_rxb 2353 * 2354 * Allocate buffers for an RDC. 2355 * 2356 * Arguments: 2357 * nxgep 2358 * channel The channel to map into our kernel space. 2359 * 2360 * Notes: 2361 * 2362 * NPI function calls: 2363 * 2364 * NXGE function calls: 2365 * 2366 * Registers accessed: 2367 * 2368 * Context: 2369 * 2370 * Taking apart: 2371 * 2372 * Open questions: 2373 * 2374 */ 2375 nxge_status_t 2376 nxge_alloc_rxb( 2377 p_nxge_t nxgep, 2378 int channel) 2379 { 2380 size_t rx_buf_alloc_size; 2381 nxge_status_t status = NXGE_OK; 2382 2383 nxge_dma_common_t **data; 2384 nxge_dma_common_t **control; 2385 uint32_t *num_chunks; 2386 2387 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2388 2389 /* 2390 * Allocate memory for the receive buffers and descriptor rings. 2391 * Replace these allocation functions with the interface functions 2392 * provided by the partition manager if/when they are available. 2393 */ 2394 2395 /* 2396 * Allocate memory for the receive buffer blocks. 2397 */ 2398 rx_buf_alloc_size = (nxgep->rx_default_block_size * 2399 (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2400 2401 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2402 num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2403 2404 if ((status = nxge_alloc_rx_buf_dma( 2405 nxgep, channel, data, rx_buf_alloc_size, 2406 nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2407 return (status); 2408 } 2409 2410 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2411 "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2412 2413 /* 2414 * Allocate memory for descriptor rings and mailbox. 2415 */ 2416 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2417 2418 if ((status = nxge_alloc_rx_cntl_dma( 2419 nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2420 != NXGE_OK) { 2421 nxge_free_rx_cntl_dma(nxgep, *control); 2422 (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2423 nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2424 return (status); 2425 } 2426 2427 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2428 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2429 2430 return (status); 2431 } 2432 2433 void 2434 nxge_free_rxb( 2435 p_nxge_t nxgep, 2436 int channel) 2437 { 2438 nxge_dma_common_t *data; 2439 nxge_dma_common_t *control; 2440 uint32_t num_chunks; 2441 2442 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2443 2444 data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2445 num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2446 nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2447 2448 nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2449 nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2450 2451 control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2452 nxge_free_rx_cntl_dma(nxgep, control); 2453 2454 nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2455 2456 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2457 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2458 2459 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2460 } 2461 2462 static void 2463 nxge_free_rx_mem_pool(p_nxge_t nxgep) 2464 { 2465 int rdc_max = NXGE_MAX_RDCS; 2466 2467 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 2468 2469 if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 2470 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2471 "<== nxge_free_rx_mem_pool " 2472 "(null rx buf pool or buf not allocated")); 2473 return; 2474 } 2475 if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 2476 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2477 "<== nxge_free_rx_mem_pool " 2478 "(null rx cntl buf pool or cntl buf not allocated")); 2479 return; 2480 } 2481 2482 KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2483 sizeof (p_nxge_dma_common_t) * rdc_max); 2484 KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 2485 2486 KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2487 sizeof (uint32_t) * rdc_max); 2488 KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2489 sizeof (p_nxge_dma_common_t) * rdc_max); 2490 KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 2491 2492 nxgep->rx_buf_pool_p = 0; 2493 nxgep->rx_cntl_pool_p = 0; 2494 2495 KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2496 sizeof (p_rx_rbr_ring_t) * rdc_max); 2497 KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2498 KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2499 sizeof (p_rx_rcr_ring_t) * rdc_max); 2500 KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2501 KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2502 sizeof (p_rx_mbox_t) * rdc_max); 2503 KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2504 2505 nxgep->rx_rbr_rings = 0; 2506 nxgep->rx_rcr_rings = 0; 2507 nxgep->rx_mbox_areas_p = 0; 2508 2509 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 2510 } 2511 2512 2513 static nxge_status_t 2514 nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 2515 p_nxge_dma_common_t *dmap, 2516 size_t alloc_size, size_t block_size, uint32_t *num_chunks) 2517 { 2518 p_nxge_dma_common_t rx_dmap; 2519 nxge_status_t status = NXGE_OK; 2520 size_t total_alloc_size; 2521 size_t allocated = 0; 2522 int i, size_index, array_size; 2523 boolean_t use_kmem_alloc = B_FALSE; 2524 2525 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 2526 2527 rx_dmap = (p_nxge_dma_common_t) 2528 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 2529 KM_SLEEP); 2530 2531 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2532 " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 2533 dma_channel, alloc_size, block_size, dmap)); 2534 2535 total_alloc_size = alloc_size; 2536 2537 #if defined(RX_USE_RECLAIM_POST) 2538 total_alloc_size = alloc_size + alloc_size/4; 2539 #endif 2540 2541 i = 0; 2542 size_index = 0; 2543 array_size = sizeof (alloc_sizes)/sizeof (size_t); 2544 while ((alloc_sizes[size_index] < alloc_size) && 2545 (size_index < array_size)) 2546 size_index++; 2547 if (size_index >= array_size) { 2548 size_index = array_size - 1; 2549 } 2550 2551 /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2552 if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2553 use_kmem_alloc = B_TRUE; 2554 #if defined(__i386) || defined(__amd64) 2555 size_index = 0; 2556 #endif 2557 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2558 "==> nxge_alloc_rx_buf_dma: " 2559 "Neptune use kmem_alloc() - size_index %d", 2560 size_index)); 2561 } 2562 2563 while ((allocated < total_alloc_size) && 2564 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 2565 rx_dmap[i].dma_chunk_index = i; 2566 rx_dmap[i].block_size = block_size; 2567 rx_dmap[i].alength = alloc_sizes[size_index]; 2568 rx_dmap[i].orig_alength = rx_dmap[i].alength; 2569 rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 2570 rx_dmap[i].dma_channel = dma_channel; 2571 rx_dmap[i].contig_alloc_type = B_FALSE; 2572 rx_dmap[i].kmem_alloc_type = B_FALSE; 2573 rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 2574 2575 /* 2576 * N2/NIU: data buffers must be contiguous as the driver 2577 * needs to call Hypervisor api to set up 2578 * logical pages. 2579 */ 2580 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 2581 rx_dmap[i].contig_alloc_type = B_TRUE; 2582 rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2583 } else if (use_kmem_alloc) { 2584 /* For Neptune, use kmem_alloc */ 2585 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2586 "==> nxge_alloc_rx_buf_dma: " 2587 "Neptune use kmem_alloc()")); 2588 rx_dmap[i].kmem_alloc_type = B_TRUE; 2589 rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 2590 } 2591 2592 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2593 "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 2594 "i %d nblocks %d alength %d", 2595 dma_channel, i, &rx_dmap[i], block_size, 2596 i, rx_dmap[i].nblocks, 2597 rx_dmap[i].alength)); 2598 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2599 &nxge_rx_dma_attr, 2600 rx_dmap[i].alength, 2601 &nxge_dev_buf_dma_acc_attr, 2602 DDI_DMA_READ | DDI_DMA_STREAMING, 2603 (p_nxge_dma_common_t)(&rx_dmap[i])); 2604 if (status != NXGE_OK) { 2605 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2606 "nxge_alloc_rx_buf_dma: Alloc Failed: " 2607 "dma %d size_index %d size requested %d", 2608 dma_channel, 2609 size_index, 2610 rx_dmap[i].alength)); 2611 size_index--; 2612 } else { 2613 rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2614 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2615 " nxge_alloc_rx_buf_dma DONE alloc mem: " 2616 "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2617 "buf_alloc_state %d alloc_type %d", 2618 dma_channel, 2619 &rx_dmap[i], 2620 rx_dmap[i].kaddrp, 2621 rx_dmap[i].alength, 2622 rx_dmap[i].buf_alloc_state, 2623 rx_dmap[i].buf_alloc_type)); 2624 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2625 " alloc_rx_buf_dma allocated rdc %d " 2626 "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2627 dma_channel, i, rx_dmap[i].alength, 2628 rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2629 rx_dmap[i].kaddrp)); 2630 i++; 2631 allocated += alloc_sizes[size_index]; 2632 } 2633 } 2634 2635 if (allocated < total_alloc_size) { 2636 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2637 "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 2638 "allocated 0x%x requested 0x%x", 2639 dma_channel, 2640 allocated, total_alloc_size)); 2641 status = NXGE_ERROR; 2642 goto nxge_alloc_rx_mem_fail1; 2643 } 2644 2645 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2646 "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 2647 "allocated 0x%x requested 0x%x", 2648 dma_channel, 2649 allocated, total_alloc_size)); 2650 2651 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2652 " alloc_rx_buf_dma rdc %d allocated %d chunks", 2653 dma_channel, i)); 2654 *num_chunks = i; 2655 *dmap = rx_dmap; 2656 2657 goto nxge_alloc_rx_mem_exit; 2658 2659 nxge_alloc_rx_mem_fail1: 2660 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2661 2662 nxge_alloc_rx_mem_exit: 2663 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2664 "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 2665 2666 return (status); 2667 } 2668 2669 /*ARGSUSED*/ 2670 static void 2671 nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 2672 uint32_t num_chunks) 2673 { 2674 int i; 2675 2676 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2677 "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 2678 2679 if (dmap == 0) 2680 return; 2681 2682 for (i = 0; i < num_chunks; i++) { 2683 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2684 "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 2685 i, dmap)); 2686 nxge_dma_free_rx_data_buf(dmap++); 2687 } 2688 2689 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 2690 } 2691 2692 /*ARGSUSED*/ 2693 static nxge_status_t 2694 nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 2695 p_nxge_dma_common_t *dmap, size_t size) 2696 { 2697 p_nxge_dma_common_t rx_dmap; 2698 nxge_status_t status = NXGE_OK; 2699 2700 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 2701 2702 rx_dmap = (p_nxge_dma_common_t) 2703 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 2704 2705 rx_dmap->contig_alloc_type = B_FALSE; 2706 rx_dmap->kmem_alloc_type = B_FALSE; 2707 2708 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2709 &nxge_desc_dma_attr, 2710 size, 2711 &nxge_dev_desc_dma_acc_attr, 2712 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2713 rx_dmap); 2714 if (status != NXGE_OK) { 2715 goto nxge_alloc_rx_cntl_dma_fail1; 2716 } 2717 2718 *dmap = rx_dmap; 2719 goto nxge_alloc_rx_cntl_dma_exit; 2720 2721 nxge_alloc_rx_cntl_dma_fail1: 2722 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 2723 2724 nxge_alloc_rx_cntl_dma_exit: 2725 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2726 "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 2727 2728 return (status); 2729 } 2730 2731 /*ARGSUSED*/ 2732 static void 2733 nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2734 { 2735 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2736 2737 if (dmap == 0) 2738 return; 2739 2740 nxge_dma_mem_free(dmap); 2741 2742 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2743 } 2744 2745 typedef struct { 2746 size_t tx_size; 2747 size_t cr_size; 2748 size_t threshhold; 2749 } nxge_tdc_sizes_t; 2750 2751 static 2752 nxge_status_t 2753 nxge_tdc_sizes( 2754 nxge_t *nxgep, 2755 nxge_tdc_sizes_t *sizes) 2756 { 2757 uint32_t threshhold; /* The bcopy() threshhold */ 2758 size_t tx_size; /* Transmit buffer size */ 2759 size_t cr_size; /* Completion ring size */ 2760 2761 /* 2762 * Assume that each DMA channel will be configured with the 2763 * default transmit buffer size for copying transmit data. 2764 * (If a packet is bigger than this, it will not be copied.) 2765 */ 2766 if (nxgep->niu_type == N2_NIU) { 2767 threshhold = TX_BCOPY_SIZE; 2768 } else { 2769 threshhold = nxge_bcopy_thresh; 2770 } 2771 tx_size = nxge_tx_ring_size * threshhold; 2772 2773 cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2774 cr_size += sizeof (txdma_mailbox_t); 2775 2776 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2777 if (nxgep->niu_type == N2_NIU) { 2778 if (!ISP2(tx_size)) { 2779 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2780 "==> nxge_tdc_sizes: Tx size" 2781 " must be power of 2")); 2782 return (NXGE_ERROR); 2783 } 2784 2785 if (tx_size > (1 << 22)) { 2786 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2787 "==> nxge_tdc_sizes: Tx size" 2788 " limited to 4M")); 2789 return (NXGE_ERROR); 2790 } 2791 2792 if (cr_size < 0x2000) 2793 cr_size = 0x2000; 2794 } 2795 #endif 2796 2797 sizes->threshhold = threshhold; 2798 sizes->tx_size = tx_size; 2799 sizes->cr_size = cr_size; 2800 2801 return (NXGE_OK); 2802 } 2803 /* 2804 * nxge_alloc_txb 2805 * 2806 * Allocate buffers for an TDC. 2807 * 2808 * Arguments: 2809 * nxgep 2810 * channel The channel to map into our kernel space. 2811 * 2812 * Notes: 2813 * 2814 * NPI function calls: 2815 * 2816 * NXGE function calls: 2817 * 2818 * Registers accessed: 2819 * 2820 * Context: 2821 * 2822 * Taking apart: 2823 * 2824 * Open questions: 2825 * 2826 */ 2827 nxge_status_t 2828 nxge_alloc_txb( 2829 p_nxge_t nxgep, 2830 int channel) 2831 { 2832 nxge_dma_common_t **dma_buf_p; 2833 nxge_dma_common_t **dma_cntl_p; 2834 uint32_t *num_chunks; 2835 nxge_status_t status = NXGE_OK; 2836 2837 nxge_tdc_sizes_t sizes; 2838 2839 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2840 2841 if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2842 return (NXGE_ERROR); 2843 2844 /* 2845 * Allocate memory for transmit buffers and descriptor rings. 2846 * Replace these allocation functions with the interface functions 2847 * provided by the partition manager Real Soon Now. 2848 */ 2849 dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2850 num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2851 2852 dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2853 2854 /* 2855 * Allocate memory for transmit buffers and descriptor rings. 2856 * Replace allocation functions with interface functions provided 2857 * by the partition manager when it is available. 2858 * 2859 * Allocate memory for the transmit buffer pool. 2860 */ 2861 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2862 "sizes: tx: %ld, cr:%ld, th:%ld", 2863 sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2864 2865 *num_chunks = 0; 2866 status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2867 sizes.tx_size, sizes.threshhold, num_chunks); 2868 if (status != NXGE_OK) { 2869 cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2870 return (status); 2871 } 2872 2873 /* 2874 * Allocate memory for descriptor rings and mailbox. 2875 */ 2876 status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2877 sizes.cr_size); 2878 if (status != NXGE_OK) { 2879 nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2880 cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2881 return (status); 2882 } 2883 2884 return (NXGE_OK); 2885 } 2886 2887 void 2888 nxge_free_txb( 2889 p_nxge_t nxgep, 2890 int channel) 2891 { 2892 nxge_dma_common_t *data; 2893 nxge_dma_common_t *control; 2894 uint32_t num_chunks; 2895 2896 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2897 2898 data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2899 num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2900 nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2901 2902 nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2903 nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2904 2905 control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2906 nxge_free_tx_cntl_dma(nxgep, control); 2907 2908 nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2909 2910 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2911 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2912 2913 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 2914 } 2915 2916 /* 2917 * nxge_alloc_tx_mem_pool 2918 * 2919 * This function allocates all of the per-port TDC control data structures. 2920 * The per-channel (TDC) data structures are allocated when needed. 2921 * 2922 * Arguments: 2923 * nxgep 2924 * 2925 * Notes: 2926 * 2927 * Context: 2928 * Any domain 2929 */ 2930 nxge_status_t 2931 nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 2932 { 2933 nxge_hw_pt_cfg_t *p_cfgp; 2934 nxge_dma_pool_t *dma_poolp; 2935 nxge_dma_common_t **dma_buf_p; 2936 nxge_dma_pool_t *dma_cntl_poolp; 2937 nxge_dma_common_t **dma_cntl_p; 2938 uint32_t *num_chunks; /* per dma */ 2939 int tdc_max; 2940 2941 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 2942 2943 p_cfgp = &nxgep->pt_config.hw_config; 2944 tdc_max = NXGE_MAX_TDCS; 2945 2946 /* 2947 * Allocate memory for each transmit DMA channel. 2948 */ 2949 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2950 KM_SLEEP); 2951 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2952 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2953 2954 dma_cntl_poolp = (p_nxge_dma_pool_t) 2955 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2956 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2957 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2958 2959 if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 2960 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2961 "nxge_alloc_tx_mem_pool: TDC too high %d, " 2962 "set to default %d", 2963 nxge_tx_ring_size, TDC_DEFAULT_MAX)); 2964 nxge_tx_ring_size = TDC_DEFAULT_MAX; 2965 } 2966 2967 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2968 /* 2969 * N2/NIU has limitation on the descriptor sizes (contiguous 2970 * memory allocation on data buffers to 4M (contig_mem_alloc) 2971 * and little endian for control buffers (must use the ddi/dki mem alloc 2972 * function). The transmit ring is limited to 8K (includes the 2973 * mailbox). 2974 */ 2975 if (nxgep->niu_type == N2_NIU) { 2976 if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 2977 (!ISP2(nxge_tx_ring_size))) { 2978 nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 2979 } 2980 } 2981 #endif 2982 2983 nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 2984 2985 num_chunks = (uint32_t *)KMEM_ZALLOC( 2986 sizeof (uint32_t) * tdc_max, KM_SLEEP); 2987 2988 dma_poolp->ndmas = p_cfgp->tdc.owned; 2989 dma_poolp->num_chunks = num_chunks; 2990 dma_poolp->dma_buf_pool_p = dma_buf_p; 2991 nxgep->tx_buf_pool_p = dma_poolp; 2992 2993 dma_poolp->buf_allocated = B_TRUE; 2994 2995 dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 2996 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 2997 nxgep->tx_cntl_pool_p = dma_cntl_poolp; 2998 2999 dma_cntl_poolp->buf_allocated = B_TRUE; 3000 3001 nxgep->tx_rings = 3002 KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3003 nxgep->tx_rings->rings = 3004 KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3005 nxgep->tx_mbox_areas_p = 3006 KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3007 nxgep->tx_mbox_areas_p->txmbox_areas_p = 3008 KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 3009 3010 nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 3011 3012 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 3013 "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 3014 tdc_max, dma_poolp->ndmas)); 3015 3016 return (NXGE_OK); 3017 } 3018 3019 nxge_status_t 3020 nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 3021 p_nxge_dma_common_t *dmap, size_t alloc_size, 3022 size_t block_size, uint32_t *num_chunks) 3023 { 3024 p_nxge_dma_common_t tx_dmap; 3025 nxge_status_t status = NXGE_OK; 3026 size_t total_alloc_size; 3027 size_t allocated = 0; 3028 int i, size_index, array_size; 3029 3030 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 3031 3032 tx_dmap = (p_nxge_dma_common_t) 3033 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 3034 KM_SLEEP); 3035 3036 total_alloc_size = alloc_size; 3037 i = 0; 3038 size_index = 0; 3039 array_size = sizeof (alloc_sizes) / sizeof (size_t); 3040 while ((alloc_sizes[size_index] < alloc_size) && 3041 (size_index < array_size)) 3042 size_index++; 3043 if (size_index >= array_size) { 3044 size_index = array_size - 1; 3045 } 3046 3047 while ((allocated < total_alloc_size) && 3048 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 3049 3050 tx_dmap[i].dma_chunk_index = i; 3051 tx_dmap[i].block_size = block_size; 3052 tx_dmap[i].alength = alloc_sizes[size_index]; 3053 tx_dmap[i].orig_alength = tx_dmap[i].alength; 3054 tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 3055 tx_dmap[i].dma_channel = dma_channel; 3056 tx_dmap[i].contig_alloc_type = B_FALSE; 3057 tx_dmap[i].kmem_alloc_type = B_FALSE; 3058 3059 /* 3060 * N2/NIU: data buffers must be contiguous as the driver 3061 * needs to call Hypervisor api to set up 3062 * logical pages. 3063 */ 3064 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 3065 tx_dmap[i].contig_alloc_type = B_TRUE; 3066 } 3067 3068 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3069 &nxge_tx_dma_attr, 3070 tx_dmap[i].alength, 3071 &nxge_dev_buf_dma_acc_attr, 3072 DDI_DMA_WRITE | DDI_DMA_STREAMING, 3073 (p_nxge_dma_common_t)(&tx_dmap[i])); 3074 if (status != NXGE_OK) { 3075 size_index--; 3076 } else { 3077 i++; 3078 allocated += alloc_sizes[size_index]; 3079 } 3080 } 3081 3082 if (allocated < total_alloc_size) { 3083 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3084 "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 3085 "allocated 0x%x requested 0x%x", 3086 dma_channel, 3087 allocated, total_alloc_size)); 3088 status = NXGE_ERROR; 3089 goto nxge_alloc_tx_mem_fail1; 3090 } 3091 3092 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3093 "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 3094 "allocated 0x%x requested 0x%x", 3095 dma_channel, 3096 allocated, total_alloc_size)); 3097 3098 *num_chunks = i; 3099 *dmap = tx_dmap; 3100 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3101 "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 3102 *dmap, i)); 3103 goto nxge_alloc_tx_mem_exit; 3104 3105 nxge_alloc_tx_mem_fail1: 3106 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 3107 3108 nxge_alloc_tx_mem_exit: 3109 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3110 "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 3111 3112 return (status); 3113 } 3114 3115 /*ARGSUSED*/ 3116 static void 3117 nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 3118 uint32_t num_chunks) 3119 { 3120 int i; 3121 3122 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 3123 3124 if (dmap == 0) 3125 return; 3126 3127 for (i = 0; i < num_chunks; i++) { 3128 nxge_dma_mem_free(dmap++); 3129 } 3130 3131 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 3132 } 3133 3134 /*ARGSUSED*/ 3135 nxge_status_t 3136 nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 3137 p_nxge_dma_common_t *dmap, size_t size) 3138 { 3139 p_nxge_dma_common_t tx_dmap; 3140 nxge_status_t status = NXGE_OK; 3141 3142 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 3143 tx_dmap = (p_nxge_dma_common_t) 3144 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 3145 3146 tx_dmap->contig_alloc_type = B_FALSE; 3147 tx_dmap->kmem_alloc_type = B_FALSE; 3148 3149 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3150 &nxge_desc_dma_attr, 3151 size, 3152 &nxge_dev_desc_dma_acc_attr, 3153 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3154 tx_dmap); 3155 if (status != NXGE_OK) { 3156 goto nxge_alloc_tx_cntl_dma_fail1; 3157 } 3158 3159 *dmap = tx_dmap; 3160 goto nxge_alloc_tx_cntl_dma_exit; 3161 3162 nxge_alloc_tx_cntl_dma_fail1: 3163 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 3164 3165 nxge_alloc_tx_cntl_dma_exit: 3166 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3167 "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 3168 3169 return (status); 3170 } 3171 3172 /*ARGSUSED*/ 3173 static void 3174 nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 3175 { 3176 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 3177 3178 if (dmap == 0) 3179 return; 3180 3181 nxge_dma_mem_free(dmap); 3182 3183 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 3184 } 3185 3186 /* 3187 * nxge_free_tx_mem_pool 3188 * 3189 * This function frees all of the per-port TDC control data structures. 3190 * The per-channel (TDC) data structures are freed when the channel 3191 * is stopped. 3192 * 3193 * Arguments: 3194 * nxgep 3195 * 3196 * Notes: 3197 * 3198 * Context: 3199 * Any domain 3200 */ 3201 static void 3202 nxge_free_tx_mem_pool(p_nxge_t nxgep) 3203 { 3204 int tdc_max = NXGE_MAX_TDCS; 3205 3206 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 3207 3208 if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3209 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3210 "<== nxge_free_tx_mem_pool " 3211 "(null tx buf pool or buf not allocated")); 3212 return; 3213 } 3214 if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3215 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3216 "<== nxge_free_tx_mem_pool " 3217 "(null tx cntl buf pool or cntl buf not allocated")); 3218 return; 3219 } 3220 3221 /* 1. Free the mailboxes. */ 3222 KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3223 sizeof (p_tx_mbox_t) * tdc_max); 3224 KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 3225 3226 nxgep->tx_mbox_areas_p = 0; 3227 3228 /* 2. Free the transmit ring arrays. */ 3229 KMEM_FREE(nxgep->tx_rings->rings, 3230 sizeof (p_tx_ring_t) * tdc_max); 3231 KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 3232 3233 nxgep->tx_rings = 0; 3234 3235 /* 3. Free the completion ring data structures. */ 3236 KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3237 sizeof (p_nxge_dma_common_t) * tdc_max); 3238 KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 3239 3240 nxgep->tx_cntl_pool_p = 0; 3241 3242 /* 4. Free the data ring data structures. */ 3243 KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3244 sizeof (uint32_t) * tdc_max); 3245 KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3246 sizeof (p_nxge_dma_common_t) * tdc_max); 3247 KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 3248 3249 nxgep->tx_buf_pool_p = 0; 3250 3251 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 3252 } 3253 3254 /*ARGSUSED*/ 3255 static nxge_status_t 3256 nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 3257 struct ddi_dma_attr *dma_attrp, 3258 size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 3259 p_nxge_dma_common_t dma_p) 3260 { 3261 caddr_t kaddrp; 3262 int ddi_status = DDI_SUCCESS; 3263 boolean_t contig_alloc_type; 3264 boolean_t kmem_alloc_type; 3265 3266 contig_alloc_type = dma_p->contig_alloc_type; 3267 3268 if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 3269 /* 3270 * contig_alloc_type for contiguous memory only allowed 3271 * for N2/NIU. 3272 */ 3273 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3274 "nxge_dma_mem_alloc: alloc type not allowed (%d)", 3275 dma_p->contig_alloc_type)); 3276 return (NXGE_ERROR | NXGE_DDI_FAILED); 3277 } 3278 3279 dma_p->dma_handle = NULL; 3280 dma_p->acc_handle = NULL; 3281 dma_p->kaddrp = dma_p->last_kaddrp = NULL; 3282 dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 3283 ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 3284 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 3285 if (ddi_status != DDI_SUCCESS) { 3286 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3287 "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 3288 return (NXGE_ERROR | NXGE_DDI_FAILED); 3289 } 3290 3291 kmem_alloc_type = dma_p->kmem_alloc_type; 3292 3293 switch (contig_alloc_type) { 3294 case B_FALSE: 3295 switch (kmem_alloc_type) { 3296 case B_FALSE: 3297 ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 3298 length, 3299 acc_attr_p, 3300 xfer_flags, 3301 DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 3302 &dma_p->acc_handle); 3303 if (ddi_status != DDI_SUCCESS) { 3304 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3305 "nxge_dma_mem_alloc: " 3306 "ddi_dma_mem_alloc failed")); 3307 ddi_dma_free_handle(&dma_p->dma_handle); 3308 dma_p->dma_handle = NULL; 3309 return (NXGE_ERROR | NXGE_DDI_FAILED); 3310 } 3311 if (dma_p->alength < length) { 3312 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3313 "nxge_dma_mem_alloc:di_dma_mem_alloc " 3314 "< length.")); 3315 ddi_dma_mem_free(&dma_p->acc_handle); 3316 ddi_dma_free_handle(&dma_p->dma_handle); 3317 dma_p->acc_handle = NULL; 3318 dma_p->dma_handle = NULL; 3319 return (NXGE_ERROR); 3320 } 3321 3322 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3323 NULL, 3324 kaddrp, dma_p->alength, xfer_flags, 3325 DDI_DMA_DONTWAIT, 3326 0, &dma_p->dma_cookie, &dma_p->ncookies); 3327 if (ddi_status != DDI_DMA_MAPPED) { 3328 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3329 "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3330 "failed " 3331 "(staus 0x%x ncookies %d.)", ddi_status, 3332 dma_p->ncookies)); 3333 if (dma_p->acc_handle) { 3334 ddi_dma_mem_free(&dma_p->acc_handle); 3335 dma_p->acc_handle = NULL; 3336 } 3337 ddi_dma_free_handle(&dma_p->dma_handle); 3338 dma_p->dma_handle = NULL; 3339 return (NXGE_ERROR | NXGE_DDI_FAILED); 3340 } 3341 3342 if (dma_p->ncookies != 1) { 3343 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3344 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3345 "> 1 cookie" 3346 "(staus 0x%x ncookies %d.)", ddi_status, 3347 dma_p->ncookies)); 3348 if (dma_p->acc_handle) { 3349 ddi_dma_mem_free(&dma_p->acc_handle); 3350 dma_p->acc_handle = NULL; 3351 } 3352 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3353 ddi_dma_free_handle(&dma_p->dma_handle); 3354 dma_p->dma_handle = NULL; 3355 return (NXGE_ERROR); 3356 } 3357 break; 3358 3359 case B_TRUE: 3360 kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3361 if (kaddrp == NULL) { 3362 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3363 "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3364 "kmem alloc failed")); 3365 return (NXGE_ERROR); 3366 } 3367 3368 dma_p->alength = length; 3369 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3370 NULL, kaddrp, dma_p->alength, xfer_flags, 3371 DDI_DMA_DONTWAIT, 0, 3372 &dma_p->dma_cookie, &dma_p->ncookies); 3373 if (ddi_status != DDI_DMA_MAPPED) { 3374 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3375 "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3376 "(kmem_alloc) failed kaddrp $%p length %d " 3377 "(staus 0x%x (%d) ncookies %d.)", 3378 kaddrp, length, 3379 ddi_status, ddi_status, dma_p->ncookies)); 3380 KMEM_FREE(kaddrp, length); 3381 dma_p->acc_handle = NULL; 3382 ddi_dma_free_handle(&dma_p->dma_handle); 3383 dma_p->dma_handle = NULL; 3384 dma_p->kaddrp = NULL; 3385 return (NXGE_ERROR | NXGE_DDI_FAILED); 3386 } 3387 3388 if (dma_p->ncookies != 1) { 3389 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3390 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3391 "(kmem_alloc) > 1 cookie" 3392 "(staus 0x%x ncookies %d.)", ddi_status, 3393 dma_p->ncookies)); 3394 KMEM_FREE(kaddrp, length); 3395 dma_p->acc_handle = NULL; 3396 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3397 ddi_dma_free_handle(&dma_p->dma_handle); 3398 dma_p->dma_handle = NULL; 3399 dma_p->kaddrp = NULL; 3400 return (NXGE_ERROR); 3401 } 3402 3403 dma_p->kaddrp = kaddrp; 3404 3405 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 3406 "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 3407 "kaddr $%p alength %d", 3408 dma_p, 3409 kaddrp, 3410 dma_p->alength)); 3411 break; 3412 } 3413 break; 3414 3415 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3416 case B_TRUE: 3417 kaddrp = (caddr_t)contig_mem_alloc(length); 3418 if (kaddrp == NULL) { 3419 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3420 "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 3421 ddi_dma_free_handle(&dma_p->dma_handle); 3422 return (NXGE_ERROR | NXGE_DDI_FAILED); 3423 } 3424 3425 dma_p->alength = length; 3426 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 3427 kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 3428 &dma_p->dma_cookie, &dma_p->ncookies); 3429 if (ddi_status != DDI_DMA_MAPPED) { 3430 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3431 "nxge_dma_mem_alloc:di_dma_addr_bind failed " 3432 "(status 0x%x ncookies %d.)", ddi_status, 3433 dma_p->ncookies)); 3434 3435 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3436 "==> nxge_dma_mem_alloc: (not mapped)" 3437 "length %lu (0x%x) " 3438 "free contig kaddrp $%p " 3439 "va_to_pa $%p", 3440 length, length, 3441 kaddrp, 3442 va_to_pa(kaddrp))); 3443 3444 3445 contig_mem_free((void *)kaddrp, length); 3446 ddi_dma_free_handle(&dma_p->dma_handle); 3447 3448 dma_p->dma_handle = NULL; 3449 dma_p->acc_handle = NULL; 3450 dma_p->alength = NULL; 3451 dma_p->kaddrp = NULL; 3452 3453 return (NXGE_ERROR | NXGE_DDI_FAILED); 3454 } 3455 3456 if (dma_p->ncookies != 1 || 3457 (dma_p->dma_cookie.dmac_laddress == NULL)) { 3458 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3459 "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 3460 "cookie or " 3461 "dmac_laddress is NULL $%p size %d " 3462 " (status 0x%x ncookies %d.)", 3463 ddi_status, 3464 dma_p->dma_cookie.dmac_laddress, 3465 dma_p->dma_cookie.dmac_size, 3466 dma_p->ncookies)); 3467 3468 contig_mem_free((void *)kaddrp, length); 3469 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3470 ddi_dma_free_handle(&dma_p->dma_handle); 3471 3472 dma_p->alength = 0; 3473 dma_p->dma_handle = NULL; 3474 dma_p->acc_handle = NULL; 3475 dma_p->kaddrp = NULL; 3476 3477 return (NXGE_ERROR | NXGE_DDI_FAILED); 3478 } 3479 break; 3480 3481 #else 3482 case B_TRUE: 3483 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3484 "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 3485 return (NXGE_ERROR | NXGE_DDI_FAILED); 3486 #endif 3487 } 3488 3489 dma_p->kaddrp = kaddrp; 3490 dma_p->last_kaddrp = (unsigned char *)kaddrp + 3491 dma_p->alength - RXBUF_64B_ALIGNED; 3492 #if defined(__i386) 3493 dma_p->ioaddr_pp = 3494 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3495 #else 3496 dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3497 #endif 3498 dma_p->last_ioaddr_pp = 3499 #if defined(__i386) 3500 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3501 #else 3502 (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3503 #endif 3504 dma_p->alength - RXBUF_64B_ALIGNED; 3505 3506 NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 3507 3508 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3509 dma_p->orig_ioaddr_pp = 3510 (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3511 dma_p->orig_alength = length; 3512 dma_p->orig_kaddrp = kaddrp; 3513 dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 3514 #endif 3515 3516 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 3517 "dma buffer allocated: dma_p $%p " 3518 "return dmac_ladress from cookie $%p cookie dmac_size %d " 3519 "dma_p->ioaddr_p $%p " 3520 "dma_p->orig_ioaddr_p $%p " 3521 "orig_vatopa $%p " 3522 "alength %d (0x%x) " 3523 "kaddrp $%p " 3524 "length %d (0x%x)", 3525 dma_p, 3526 dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 3527 dma_p->ioaddr_pp, 3528 dma_p->orig_ioaddr_pp, 3529 dma_p->orig_vatopa, 3530 dma_p->alength, dma_p->alength, 3531 kaddrp, 3532 length, length)); 3533 3534 return (NXGE_OK); 3535 } 3536 3537 static void 3538 nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 3539 { 3540 if (dma_p->dma_handle != NULL) { 3541 if (dma_p->ncookies) { 3542 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3543 dma_p->ncookies = 0; 3544 } 3545 ddi_dma_free_handle(&dma_p->dma_handle); 3546 dma_p->dma_handle = NULL; 3547 } 3548 3549 if (dma_p->acc_handle != NULL) { 3550 ddi_dma_mem_free(&dma_p->acc_handle); 3551 dma_p->acc_handle = NULL; 3552 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3553 } 3554 3555 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3556 if (dma_p->contig_alloc_type && 3557 dma_p->orig_kaddrp && dma_p->orig_alength) { 3558 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 3559 "kaddrp $%p (orig_kaddrp $%p)" 3560 "mem type %d ", 3561 "orig_alength %d " 3562 "alength 0x%x (%d)", 3563 dma_p->kaddrp, 3564 dma_p->orig_kaddrp, 3565 dma_p->contig_alloc_type, 3566 dma_p->orig_alength, 3567 dma_p->alength, dma_p->alength)); 3568 3569 contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 3570 dma_p->orig_alength = NULL; 3571 dma_p->orig_kaddrp = NULL; 3572 dma_p->contig_alloc_type = B_FALSE; 3573 } 3574 #endif 3575 dma_p->kaddrp = NULL; 3576 dma_p->alength = NULL; 3577 } 3578 3579 static void 3580 nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3581 { 3582 uint64_t kaddr; 3583 uint32_t buf_size; 3584 3585 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3586 3587 if (dma_p->dma_handle != NULL) { 3588 if (dma_p->ncookies) { 3589 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3590 dma_p->ncookies = 0; 3591 } 3592 ddi_dma_free_handle(&dma_p->dma_handle); 3593 dma_p->dma_handle = NULL; 3594 } 3595 3596 if (dma_p->acc_handle != NULL) { 3597 ddi_dma_mem_free(&dma_p->acc_handle); 3598 dma_p->acc_handle = NULL; 3599 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3600 } 3601 3602 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3603 "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3604 dma_p, 3605 dma_p->buf_alloc_state)); 3606 3607 if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3608 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3609 "<== nxge_dma_free_rx_data_buf: " 3610 "outstanding data buffers")); 3611 return; 3612 } 3613 3614 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3615 if (dma_p->contig_alloc_type && 3616 dma_p->orig_kaddrp && dma_p->orig_alength) { 3617 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3618 "kaddrp $%p (orig_kaddrp $%p)" 3619 "mem type %d ", 3620 "orig_alength %d " 3621 "alength 0x%x (%d)", 3622 dma_p->kaddrp, 3623 dma_p->orig_kaddrp, 3624 dma_p->contig_alloc_type, 3625 dma_p->orig_alength, 3626 dma_p->alength, dma_p->alength)); 3627 3628 kaddr = (uint64_t)dma_p->orig_kaddrp; 3629 buf_size = dma_p->orig_alength; 3630 nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3631 dma_p->orig_alength = NULL; 3632 dma_p->orig_kaddrp = NULL; 3633 dma_p->contig_alloc_type = B_FALSE; 3634 dma_p->kaddrp = NULL; 3635 dma_p->alength = NULL; 3636 return; 3637 } 3638 #endif 3639 3640 if (dma_p->kmem_alloc_type) { 3641 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3642 "nxge_dma_free_rx_data_buf: free kmem " 3643 "kaddrp $%p (orig_kaddrp $%p)" 3644 "alloc type %d " 3645 "orig_alength %d " 3646 "alength 0x%x (%d)", 3647 dma_p->kaddrp, 3648 dma_p->orig_kaddrp, 3649 dma_p->kmem_alloc_type, 3650 dma_p->orig_alength, 3651 dma_p->alength, dma_p->alength)); 3652 #if defined(__i386) 3653 kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3654 #else 3655 kaddr = (uint64_t)dma_p->kaddrp; 3656 #endif 3657 buf_size = dma_p->orig_alength; 3658 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3659 "nxge_dma_free_rx_data_buf: free dmap $%p " 3660 "kaddr $%p buf_size %d", 3661 dma_p, 3662 kaddr, buf_size)); 3663 nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3664 dma_p->alength = 0; 3665 dma_p->orig_alength = 0; 3666 dma_p->kaddrp = NULL; 3667 dma_p->kmem_alloc_type = B_FALSE; 3668 } 3669 3670 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3671 } 3672 3673 /* 3674 * nxge_m_start() -- start transmitting and receiving. 3675 * 3676 * This function is called by the MAC layer when the first 3677 * stream is open to prepare the hardware ready for sending 3678 * and transmitting packets. 3679 */ 3680 static int 3681 nxge_m_start(void *arg) 3682 { 3683 p_nxge_t nxgep = (p_nxge_t)arg; 3684 3685 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 3686 3687 if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 3688 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 3689 } 3690 3691 MUTEX_ENTER(nxgep->genlock); 3692 if (nxge_init(nxgep) != NXGE_OK) { 3693 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3694 "<== nxge_m_start: initialization failed")); 3695 MUTEX_EXIT(nxgep->genlock); 3696 return (EIO); 3697 } 3698 3699 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 3700 goto nxge_m_start_exit; 3701 /* 3702 * Start timer to check the system error and tx hangs 3703 */ 3704 if (!isLDOMguest(nxgep)) 3705 nxgep->nxge_timerid = nxge_start_timer(nxgep, 3706 nxge_check_hw_state, NXGE_CHECK_TIMER); 3707 #if defined(sun4v) 3708 else 3709 nxge_hio_start_timer(nxgep); 3710 #endif 3711 3712 nxgep->link_notify = B_TRUE; 3713 3714 nxgep->nxge_mac_state = NXGE_MAC_STARTED; 3715 3716 nxge_m_start_exit: 3717 MUTEX_EXIT(nxgep->genlock); 3718 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 3719 return (0); 3720 } 3721 3722 /* 3723 * nxge_m_stop(): stop transmitting and receiving. 3724 */ 3725 static void 3726 nxge_m_stop(void *arg) 3727 { 3728 p_nxge_t nxgep = (p_nxge_t)arg; 3729 3730 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 3731 3732 if (nxgep->nxge_timerid) { 3733 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 3734 nxgep->nxge_timerid = 0; 3735 } 3736 3737 MUTEX_ENTER(nxgep->genlock); 3738 nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 3739 nxge_uninit(nxgep); 3740 3741 nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 3742 3743 MUTEX_EXIT(nxgep->genlock); 3744 3745 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 3746 } 3747 3748 static int 3749 nxge_m_unicst(void *arg, const uint8_t *macaddr) 3750 { 3751 p_nxge_t nxgep = (p_nxge_t)arg; 3752 struct ether_addr addrp; 3753 3754 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_m_unicst")); 3755 3756 bcopy(macaddr, (uint8_t *)&addrp, ETHERADDRL); 3757 if (nxge_set_mac_addr(nxgep, &addrp)) { 3758 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3759 "<== nxge_m_unicst: set unitcast failed")); 3760 return (EINVAL); 3761 } 3762 3763 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_unicst")); 3764 3765 return (0); 3766 } 3767 3768 static int 3769 nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 3770 { 3771 p_nxge_t nxgep = (p_nxge_t)arg; 3772 struct ether_addr addrp; 3773 3774 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3775 "==> nxge_m_multicst: add %d", add)); 3776 3777 bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 3778 if (add) { 3779 if (nxge_add_mcast_addr(nxgep, &addrp)) { 3780 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3781 "<== nxge_m_multicst: add multicast failed")); 3782 return (EINVAL); 3783 } 3784 } else { 3785 if (nxge_del_mcast_addr(nxgep, &addrp)) { 3786 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3787 "<== nxge_m_multicst: del multicast failed")); 3788 return (EINVAL); 3789 } 3790 } 3791 3792 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 3793 3794 return (0); 3795 } 3796 3797 static int 3798 nxge_m_promisc(void *arg, boolean_t on) 3799 { 3800 p_nxge_t nxgep = (p_nxge_t)arg; 3801 3802 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3803 "==> nxge_m_promisc: on %d", on)); 3804 3805 if (nxge_set_promisc(nxgep, on)) { 3806 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3807 "<== nxge_m_promisc: set promisc failed")); 3808 return (EINVAL); 3809 } 3810 3811 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3812 "<== nxge_m_promisc: on %d", on)); 3813 3814 return (0); 3815 } 3816 3817 static void 3818 nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 3819 { 3820 p_nxge_t nxgep = (p_nxge_t)arg; 3821 struct iocblk *iocp; 3822 boolean_t need_privilege; 3823 int err; 3824 int cmd; 3825 3826 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 3827 3828 iocp = (struct iocblk *)mp->b_rptr; 3829 iocp->ioc_error = 0; 3830 need_privilege = B_TRUE; 3831 cmd = iocp->ioc_cmd; 3832 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 3833 switch (cmd) { 3834 default: 3835 miocnak(wq, mp, 0, EINVAL); 3836 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 3837 return; 3838 3839 case LB_GET_INFO_SIZE: 3840 case LB_GET_INFO: 3841 case LB_GET_MODE: 3842 need_privilege = B_FALSE; 3843 break; 3844 case LB_SET_MODE: 3845 break; 3846 3847 3848 case NXGE_GET_MII: 3849 case NXGE_PUT_MII: 3850 case NXGE_GET64: 3851 case NXGE_PUT64: 3852 case NXGE_GET_TX_RING_SZ: 3853 case NXGE_GET_TX_DESC: 3854 case NXGE_TX_SIDE_RESET: 3855 case NXGE_RX_SIDE_RESET: 3856 case NXGE_GLOBAL_RESET: 3857 case NXGE_RESET_MAC: 3858 case NXGE_TX_REGS_DUMP: 3859 case NXGE_RX_REGS_DUMP: 3860 case NXGE_INT_REGS_DUMP: 3861 case NXGE_VIR_INT_REGS_DUMP: 3862 case NXGE_PUT_TCAM: 3863 case NXGE_GET_TCAM: 3864 case NXGE_RTRACE: 3865 case NXGE_RDUMP: 3866 3867 need_privilege = B_FALSE; 3868 break; 3869 case NXGE_INJECT_ERR: 3870 cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 3871 nxge_err_inject(nxgep, wq, mp); 3872 break; 3873 } 3874 3875 if (need_privilege) { 3876 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 3877 if (err != 0) { 3878 miocnak(wq, mp, 0, err); 3879 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3880 "<== nxge_m_ioctl: no priv")); 3881 return; 3882 } 3883 } 3884 3885 switch (cmd) { 3886 3887 case LB_GET_MODE: 3888 case LB_SET_MODE: 3889 case LB_GET_INFO_SIZE: 3890 case LB_GET_INFO: 3891 nxge_loopback_ioctl(nxgep, wq, mp, iocp); 3892 break; 3893 3894 case NXGE_GET_MII: 3895 case NXGE_PUT_MII: 3896 case NXGE_PUT_TCAM: 3897 case NXGE_GET_TCAM: 3898 case NXGE_GET64: 3899 case NXGE_PUT64: 3900 case NXGE_GET_TX_RING_SZ: 3901 case NXGE_GET_TX_DESC: 3902 case NXGE_TX_SIDE_RESET: 3903 case NXGE_RX_SIDE_RESET: 3904 case NXGE_GLOBAL_RESET: 3905 case NXGE_RESET_MAC: 3906 case NXGE_TX_REGS_DUMP: 3907 case NXGE_RX_REGS_DUMP: 3908 case NXGE_INT_REGS_DUMP: 3909 case NXGE_VIR_INT_REGS_DUMP: 3910 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 3911 "==> nxge_m_ioctl: cmd 0x%x", cmd)); 3912 nxge_hw_ioctl(nxgep, wq, mp, iocp); 3913 break; 3914 } 3915 3916 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 3917 } 3918 3919 extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 3920 3921 static void 3922 nxge_m_resources(void *arg) 3923 { 3924 p_nxge_t nxgep = arg; 3925 mac_rx_fifo_t mrf; 3926 3927 nxge_grp_set_t *set = &nxgep->rx_set; 3928 uint8_t rdc; 3929 3930 rx_rcr_ring_t *ring; 3931 3932 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_m_resources")); 3933 3934 MUTEX_ENTER(nxgep->genlock); 3935 3936 if (set->owned.map == 0) { 3937 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 3938 "nxge_m_resources: no receive resources")); 3939 goto nxge_m_resources_exit; 3940 } 3941 3942 /* 3943 * CR 6492541 Check to see if the drv_state has been initialized, 3944 * if not * call nxge_init(). 3945 */ 3946 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 3947 if (nxge_init(nxgep) != NXGE_OK) 3948 goto nxge_m_resources_exit; 3949 } 3950 3951 mrf.mrf_type = MAC_RX_FIFO; 3952 mrf.mrf_blank = nxge_rx_hw_blank; 3953 mrf.mrf_arg = (void *)nxgep; 3954 3955 mrf.mrf_normal_blank_time = 128; 3956 mrf.mrf_normal_pkt_count = 8; 3957 3958 /* 3959 * Export our receive resources to the MAC layer. 3960 */ 3961 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 3962 if ((1 << rdc) & set->owned.map) { 3963 ring = nxgep->rx_rcr_rings->rcr_rings[rdc]; 3964 if (ring == 0) { 3965 /* 3966 * This is a big deal only if we are 3967 * *not* in an LDOMs environment. 3968 */ 3969 if (nxgep->environs == SOLARIS_DOMAIN) { 3970 cmn_err(CE_NOTE, 3971 "==> nxge_m_resources: " 3972 "ring %d == 0", rdc); 3973 } 3974 continue; 3975 } 3976 ring->rcr_mac_handle = mac_resource_add 3977 (nxgep->mach, (mac_resource_t *)&mrf); 3978 3979 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 3980 "==> nxge_m_resources: RDC %d RCR %p MAC handle %p", 3981 rdc, ring, ring->rcr_mac_handle)); 3982 } 3983 } 3984 3985 nxge_m_resources_exit: 3986 MUTEX_EXIT(nxgep->genlock); 3987 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_m_resources")); 3988 } 3989 3990 void 3991 nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, boolean_t factory) 3992 { 3993 p_nxge_mmac_stats_t mmac_stats; 3994 int i; 3995 nxge_mmac_t *mmac_info; 3996 3997 mmac_info = &nxgep->nxge_mmac_info; 3998 3999 mmac_stats = &nxgep->statsp->mmac_stats; 4000 mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 4001 mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 4002 4003 for (i = 0; i < ETHERADDRL; i++) { 4004 if (factory) { 4005 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4006 = mmac_info->factory_mac_pool[slot][ 4007 (ETHERADDRL-1) - i]; 4008 } else { 4009 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4010 = mmac_info->mac_pool[slot].addr[ 4011 (ETHERADDRL - 1) - i]; 4012 } 4013 } 4014 } 4015 4016 /* 4017 * nxge_altmac_set() -- Set an alternate MAC address 4018 */ 4019 static int 4020 nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, mac_addr_slot_t slot) 4021 { 4022 uint8_t addrn; 4023 uint8_t portn; 4024 npi_mac_addr_t altmac; 4025 hostinfo_t mac_rdc; 4026 p_nxge_class_pt_cfg_t clscfgp; 4027 4028 altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 4029 altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 4030 altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 4031 4032 portn = nxgep->mac.portnum; 4033 addrn = (uint8_t)slot - 1; 4034 4035 if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, portn, 4036 addrn, &altmac) != NPI_SUCCESS) 4037 return (EIO); 4038 4039 /* 4040 * Set the rdc table number for the host info entry 4041 * for this mac address slot. 4042 */ 4043 clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 4044 mac_rdc.value = 0; 4045 mac_rdc.bits.w0.rdc_tbl_num = clscfgp->mac_host_info[addrn].rdctbl; 4046 mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 4047 4048 if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 4049 nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 4050 return (EIO); 4051 } 4052 4053 /* 4054 * Enable comparison with the alternate MAC address. 4055 * While the first alternate addr is enabled by bit 1 of register 4056 * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 4057 * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 4058 * accordingly before calling npi_mac_altaddr_entry. 4059 */ 4060 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4061 addrn = (uint8_t)slot - 1; 4062 else 4063 addrn = (uint8_t)slot; 4064 4065 if (npi_mac_altaddr_enable(nxgep->npi_handle, portn, addrn) 4066 != NPI_SUCCESS) 4067 return (EIO); 4068 4069 return (0); 4070 } 4071 4072 /* 4073 * nxeg_m_mmac_add() - find an unused address slot, set the address 4074 * value to the one specified, enable the port to start filtering on 4075 * the new MAC address. Returns 0 on success. 4076 */ 4077 int 4078 nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr) 4079 { 4080 p_nxge_t nxgep = arg; 4081 mac_addr_slot_t slot; 4082 nxge_mmac_t *mmac_info; 4083 int err; 4084 nxge_status_t status; 4085 4086 mutex_enter(nxgep->genlock); 4087 4088 /* 4089 * Make sure that nxge is initialized, if _start() has 4090 * not been called. 4091 */ 4092 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4093 status = nxge_init(nxgep); 4094 if (status != NXGE_OK) { 4095 mutex_exit(nxgep->genlock); 4096 return (ENXIO); 4097 } 4098 } 4099 4100 mmac_info = &nxgep->nxge_mmac_info; 4101 if (mmac_info->naddrfree == 0) { 4102 mutex_exit(nxgep->genlock); 4103 return (ENOSPC); 4104 } 4105 if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 4106 maddr->mma_addrlen)) { 4107 mutex_exit(nxgep->genlock); 4108 return (EINVAL); 4109 } 4110 /* 4111 * Search for the first available slot. Because naddrfree 4112 * is not zero, we are guaranteed to find one. 4113 * Slot 0 is for unique (primary) MAC. The first alternate 4114 * MAC slot is slot 1. 4115 * Each of the first two ports of Neptune has 16 alternate 4116 * MAC slots but only the first 7 (of 15) slots have assigned factory 4117 * MAC addresses. We first search among the slots without bundled 4118 * factory MACs. If we fail to find one in that range, then we 4119 * search the slots with bundled factory MACs. A factory MAC 4120 * will be wasted while the slot is used with a user MAC address. 4121 * But the slot could be used by factory MAC again after calling 4122 * nxge_m_mmac_remove and nxge_m_mmac_reserve. 4123 */ 4124 if (mmac_info->num_factory_mmac < mmac_info->num_mmac) { 4125 for (slot = mmac_info->num_factory_mmac + 1; 4126 slot <= mmac_info->num_mmac; slot++) { 4127 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4128 break; 4129 } 4130 if (slot > mmac_info->num_mmac) { 4131 for (slot = 1; slot <= mmac_info->num_factory_mmac; 4132 slot++) { 4133 if (!(mmac_info->mac_pool[slot].flags 4134 & MMAC_SLOT_USED)) 4135 break; 4136 } 4137 } 4138 } else { 4139 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 4140 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4141 break; 4142 } 4143 } 4144 ASSERT(slot <= mmac_info->num_mmac); 4145 if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) != 0) { 4146 mutex_exit(nxgep->genlock); 4147 return (err); 4148 } 4149 bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 4150 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 4151 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4152 mmac_info->naddrfree--; 4153 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4154 4155 maddr->mma_slot = slot; 4156 4157 mutex_exit(nxgep->genlock); 4158 return (0); 4159 } 4160 4161 /* 4162 * This function reserves an unused slot and programs the slot and the HW 4163 * with a factory mac address. 4164 */ 4165 static int 4166 nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr) 4167 { 4168 p_nxge_t nxgep = arg; 4169 mac_addr_slot_t slot; 4170 nxge_mmac_t *mmac_info; 4171 int err; 4172 nxge_status_t status; 4173 4174 mutex_enter(nxgep->genlock); 4175 4176 /* 4177 * Make sure that nxge is initialized, if _start() has 4178 * not been called. 4179 */ 4180 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4181 status = nxge_init(nxgep); 4182 if (status != NXGE_OK) { 4183 mutex_exit(nxgep->genlock); 4184 return (ENXIO); 4185 } 4186 } 4187 4188 mmac_info = &nxgep->nxge_mmac_info; 4189 if (mmac_info->naddrfree == 0) { 4190 mutex_exit(nxgep->genlock); 4191 return (ENOSPC); 4192 } 4193 4194 slot = maddr->mma_slot; 4195 if (slot == -1) { /* -1: Take the first available slot */ 4196 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 4197 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4198 break; 4199 } 4200 if (slot > mmac_info->num_factory_mmac) { 4201 mutex_exit(nxgep->genlock); 4202 return (ENOSPC); 4203 } 4204 } 4205 if (slot < 1 || slot > mmac_info->num_factory_mmac) { 4206 /* 4207 * Do not support factory MAC at a slot greater than 4208 * num_factory_mmac even when there are available factory 4209 * MAC addresses because the alternate MACs are bundled with 4210 * slot[1] through slot[num_factory_mmac] 4211 */ 4212 mutex_exit(nxgep->genlock); 4213 return (EINVAL); 4214 } 4215 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4216 mutex_exit(nxgep->genlock); 4217 return (EBUSY); 4218 } 4219 /* Verify the address to be reserved */ 4220 if (!mac_unicst_verify(nxgep->mach, 4221 mmac_info->factory_mac_pool[slot], ETHERADDRL)) { 4222 mutex_exit(nxgep->genlock); 4223 return (EINVAL); 4224 } 4225 if (err = nxge_altmac_set(nxgep, 4226 mmac_info->factory_mac_pool[slot], slot)) { 4227 mutex_exit(nxgep->genlock); 4228 return (err); 4229 } 4230 bcopy(mmac_info->factory_mac_pool[slot], maddr->mma_addr, ETHERADDRL); 4231 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 4232 mmac_info->naddrfree--; 4233 4234 nxge_mmac_kstat_update(nxgep, slot, B_TRUE); 4235 mutex_exit(nxgep->genlock); 4236 4237 /* Pass info back to the caller */ 4238 maddr->mma_slot = slot; 4239 maddr->mma_addrlen = ETHERADDRL; 4240 maddr->mma_flags = MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 4241 4242 return (0); 4243 } 4244 4245 /* 4246 * Remove the specified mac address and update the HW not to filter 4247 * the mac address anymore. 4248 */ 4249 int 4250 nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot) 4251 { 4252 p_nxge_t nxgep = arg; 4253 nxge_mmac_t *mmac_info; 4254 uint8_t addrn; 4255 uint8_t portn; 4256 int err = 0; 4257 nxge_status_t status; 4258 4259 mutex_enter(nxgep->genlock); 4260 4261 /* 4262 * Make sure that nxge is initialized, if _start() has 4263 * not been called. 4264 */ 4265 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4266 status = nxge_init(nxgep); 4267 if (status != NXGE_OK) { 4268 mutex_exit(nxgep->genlock); 4269 return (ENXIO); 4270 } 4271 } 4272 4273 mmac_info = &nxgep->nxge_mmac_info; 4274 if (slot < 1 || slot > mmac_info->num_mmac) { 4275 mutex_exit(nxgep->genlock); 4276 return (EINVAL); 4277 } 4278 4279 portn = nxgep->mac.portnum; 4280 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4281 addrn = (uint8_t)slot - 1; 4282 else 4283 addrn = (uint8_t)slot; 4284 4285 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4286 if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 4287 == NPI_SUCCESS) { 4288 mmac_info->naddrfree++; 4289 mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 4290 /* 4291 * Regardless if the MAC we just stopped filtering 4292 * is a user addr or a facory addr, we must set 4293 * the MMAC_VENDOR_ADDR flag if this slot has an 4294 * associated factory MAC to indicate that a factory 4295 * MAC is available. 4296 */ 4297 if (slot <= mmac_info->num_factory_mmac) { 4298 mmac_info->mac_pool[slot].flags 4299 |= MMAC_VENDOR_ADDR; 4300 } 4301 /* 4302 * Clear mac_pool[slot].addr so that kstat shows 0 4303 * alternate MAC address if the slot is not used. 4304 * (But nxge_m_mmac_get returns the factory MAC even 4305 * when the slot is not used!) 4306 */ 4307 bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 4308 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4309 } else { 4310 err = EIO; 4311 } 4312 } else { 4313 err = EINVAL; 4314 } 4315 4316 mutex_exit(nxgep->genlock); 4317 return (err); 4318 } 4319 4320 /* 4321 * Modify a mac address added by nxge_m_mmac_add or nxge_m_mmac_reserve(). 4322 */ 4323 static int 4324 nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr) 4325 { 4326 p_nxge_t nxgep = arg; 4327 mac_addr_slot_t slot; 4328 nxge_mmac_t *mmac_info; 4329 int err = 0; 4330 nxge_status_t status; 4331 4332 if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 4333 maddr->mma_addrlen)) 4334 return (EINVAL); 4335 4336 slot = maddr->mma_slot; 4337 4338 mutex_enter(nxgep->genlock); 4339 4340 /* 4341 * Make sure that nxge is initialized, if _start() has 4342 * not been called. 4343 */ 4344 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4345 status = nxge_init(nxgep); 4346 if (status != NXGE_OK) { 4347 mutex_exit(nxgep->genlock); 4348 return (ENXIO); 4349 } 4350 } 4351 4352 mmac_info = &nxgep->nxge_mmac_info; 4353 if (slot < 1 || slot > mmac_info->num_mmac) { 4354 mutex_exit(nxgep->genlock); 4355 return (EINVAL); 4356 } 4357 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4358 if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot)) 4359 != 0) { 4360 bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, 4361 ETHERADDRL); 4362 /* 4363 * Assume that the MAC passed down from the caller 4364 * is not a factory MAC address (The user should 4365 * call mmac_remove followed by mmac_reserve if 4366 * he wants to use the factory MAC for this slot). 4367 */ 4368 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4369 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4370 } 4371 } else { 4372 err = EINVAL; 4373 } 4374 mutex_exit(nxgep->genlock); 4375 return (err); 4376 } 4377 4378 /* 4379 * nxge_m_mmac_get() - Get the MAC address and other information 4380 * related to the slot. mma_flags should be set to 0 in the call. 4381 * Note: although kstat shows MAC address as zero when a slot is 4382 * not used, Crossbow expects nxge_m_mmac_get to copy factory MAC 4383 * to the caller as long as the slot is not using a user MAC address. 4384 * The following table shows the rules, 4385 * 4386 * USED VENDOR mma_addr 4387 * ------------------------------------------------------------ 4388 * (1) Slot uses a user MAC: yes no user MAC 4389 * (2) Slot uses a factory MAC: yes yes factory MAC 4390 * (3) Slot is not used but is 4391 * factory MAC capable: no yes factory MAC 4392 * (4) Slot is not used and is 4393 * not factory MAC capable: no no 0 4394 * ------------------------------------------------------------ 4395 */ 4396 static int 4397 nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr) 4398 { 4399 nxge_t *nxgep = arg; 4400 mac_addr_slot_t slot; 4401 nxge_mmac_t *mmac_info; 4402 nxge_status_t status; 4403 4404 slot = maddr->mma_slot; 4405 4406 mutex_enter(nxgep->genlock); 4407 4408 /* 4409 * Make sure that nxge is initialized, if _start() has 4410 * not been called. 4411 */ 4412 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4413 status = nxge_init(nxgep); 4414 if (status != NXGE_OK) { 4415 mutex_exit(nxgep->genlock); 4416 return (ENXIO); 4417 } 4418 } 4419 4420 mmac_info = &nxgep->nxge_mmac_info; 4421 4422 if (slot < 1 || slot > mmac_info->num_mmac) { 4423 mutex_exit(nxgep->genlock); 4424 return (EINVAL); 4425 } 4426 maddr->mma_flags = 0; 4427 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) 4428 maddr->mma_flags |= MMAC_SLOT_USED; 4429 4430 if (mmac_info->mac_pool[slot].flags & MMAC_VENDOR_ADDR) { 4431 maddr->mma_flags |= MMAC_VENDOR_ADDR; 4432 bcopy(mmac_info->factory_mac_pool[slot], 4433 maddr->mma_addr, ETHERADDRL); 4434 maddr->mma_addrlen = ETHERADDRL; 4435 } else { 4436 if (maddr->mma_flags & MMAC_SLOT_USED) { 4437 bcopy(mmac_info->mac_pool[slot].addr, 4438 maddr->mma_addr, ETHERADDRL); 4439 maddr->mma_addrlen = ETHERADDRL; 4440 } else { 4441 bzero(maddr->mma_addr, ETHERADDRL); 4442 maddr->mma_addrlen = 0; 4443 } 4444 } 4445 mutex_exit(nxgep->genlock); 4446 return (0); 4447 } 4448 4449 static boolean_t 4450 nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 4451 { 4452 nxge_t *nxgep = arg; 4453 uint32_t *txflags = cap_data; 4454 multiaddress_capab_t *mmacp = cap_data; 4455 4456 switch (cap) { 4457 case MAC_CAPAB_HCKSUM: 4458 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4459 "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4460 if (nxge_cksum_offload <= 1) { 4461 *txflags = HCKSUM_INET_PARTIAL; 4462 } 4463 break; 4464 4465 case MAC_CAPAB_POLL: 4466 /* 4467 * There's nothing for us to fill in, simply returning 4468 * B_TRUE stating that we support polling is sufficient. 4469 */ 4470 break; 4471 4472 case MAC_CAPAB_MULTIADDRESS: 4473 mmacp = (multiaddress_capab_t *)cap_data; 4474 mutex_enter(nxgep->genlock); 4475 4476 mmacp->maddr_naddr = nxgep->nxge_mmac_info.num_mmac; 4477 mmacp->maddr_naddrfree = nxgep->nxge_mmac_info.naddrfree; 4478 mmacp->maddr_flag = 0; /* 0 is required by PSARC2006/265 */ 4479 /* 4480 * maddr_handle is driver's private data, passed back to 4481 * entry point functions as arg. 4482 */ 4483 mmacp->maddr_handle = nxgep; 4484 mmacp->maddr_add = nxge_m_mmac_add; 4485 mmacp->maddr_remove = nxge_m_mmac_remove; 4486 mmacp->maddr_modify = nxge_m_mmac_modify; 4487 mmacp->maddr_get = nxge_m_mmac_get; 4488 mmacp->maddr_reserve = nxge_m_mmac_reserve; 4489 4490 mutex_exit(nxgep->genlock); 4491 break; 4492 4493 case MAC_CAPAB_LSO: { 4494 mac_capab_lso_t *cap_lso = cap_data; 4495 4496 if (nxgep->soft_lso_enable) { 4497 if (nxge_cksum_offload <= 1) { 4498 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4499 if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4500 nxge_lso_max = NXGE_LSO_MAXLEN; 4501 } 4502 cap_lso->lso_basic_tcp_ipv4.lso_max = 4503 nxge_lso_max; 4504 } 4505 break; 4506 } else { 4507 return (B_FALSE); 4508 } 4509 } 4510 4511 #if defined(sun4v) 4512 case MAC_CAPAB_RINGS: { 4513 mac_capab_rings_t *mrings = (mac_capab_rings_t *)cap_data; 4514 4515 /* 4516 * Only the service domain driver responds to 4517 * this capability request. 4518 */ 4519 if (isLDOMservice(nxgep)) { 4520 mrings->mr_handle = (void *)nxgep; 4521 4522 /* 4523 * No dynamic allocation of groups and 4524 * rings at this time. Shares dictate the 4525 * configuration. 4526 */ 4527 mrings->mr_gadd_ring = NULL; 4528 mrings->mr_grem_ring = NULL; 4529 mrings->mr_rget = NULL; 4530 mrings->mr_gget = nxge_hio_group_get; 4531 4532 if (mrings->mr_type == MAC_RING_TYPE_RX) { 4533 mrings->mr_rnum = 8; /* XXX */ 4534 mrings->mr_gnum = 6; /* XXX */ 4535 } else { 4536 mrings->mr_rnum = 8; /* XXX */ 4537 mrings->mr_gnum = 0; /* XXX */ 4538 } 4539 } else 4540 return (B_FALSE); 4541 break; 4542 } 4543 4544 case MAC_CAPAB_SHARES: { 4545 mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4546 4547 /* 4548 * Only the service domain driver responds to 4549 * this capability request. 4550 */ 4551 if (isLDOMservice(nxgep)) { 4552 mshares->ms_snum = 3; 4553 mshares->ms_handle = (void *)nxgep; 4554 mshares->ms_salloc = nxge_hio_share_alloc; 4555 mshares->ms_sfree = nxge_hio_share_free; 4556 mshares->ms_sadd = NULL; 4557 mshares->ms_sremove = NULL; 4558 mshares->ms_squery = nxge_hio_share_query; 4559 } else 4560 return (B_FALSE); 4561 break; 4562 } 4563 #endif 4564 default: 4565 return (B_FALSE); 4566 } 4567 return (B_TRUE); 4568 } 4569 4570 static boolean_t 4571 nxge_param_locked(mac_prop_id_t pr_num) 4572 { 4573 /* 4574 * All adv_* parameters are locked (read-only) while 4575 * the device is in any sort of loopback mode ... 4576 */ 4577 switch (pr_num) { 4578 case MAC_PROP_ADV_1000FDX_CAP: 4579 case MAC_PROP_EN_1000FDX_CAP: 4580 case MAC_PROP_ADV_1000HDX_CAP: 4581 case MAC_PROP_EN_1000HDX_CAP: 4582 case MAC_PROP_ADV_100FDX_CAP: 4583 case MAC_PROP_EN_100FDX_CAP: 4584 case MAC_PROP_ADV_100HDX_CAP: 4585 case MAC_PROP_EN_100HDX_CAP: 4586 case MAC_PROP_ADV_10FDX_CAP: 4587 case MAC_PROP_EN_10FDX_CAP: 4588 case MAC_PROP_ADV_10HDX_CAP: 4589 case MAC_PROP_EN_10HDX_CAP: 4590 case MAC_PROP_AUTONEG: 4591 case MAC_PROP_FLOWCTRL: 4592 return (B_TRUE); 4593 } 4594 return (B_FALSE); 4595 } 4596 4597 /* 4598 * callback functions for set/get of properties 4599 */ 4600 static int 4601 nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4602 uint_t pr_valsize, const void *pr_val) 4603 { 4604 nxge_t *nxgep = barg; 4605 p_nxge_param_t param_arr; 4606 p_nxge_stats_t statsp; 4607 int err = 0; 4608 uint8_t val; 4609 uint32_t cur_mtu, new_mtu, old_framesize; 4610 link_flowctrl_t fl; 4611 4612 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 4613 param_arr = nxgep->param_arr; 4614 statsp = nxgep->statsp; 4615 mutex_enter(nxgep->genlock); 4616 if (statsp->port_stats.lb_mode != nxge_lb_normal && 4617 nxge_param_locked(pr_num)) { 4618 /* 4619 * All adv_* parameters are locked (read-only) 4620 * while the device is in any sort of loopback mode. 4621 */ 4622 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4623 "==> nxge_m_setprop: loopback mode: read only")); 4624 mutex_exit(nxgep->genlock); 4625 return (EBUSY); 4626 } 4627 4628 val = *(uint8_t *)pr_val; 4629 switch (pr_num) { 4630 case MAC_PROP_EN_1000FDX_CAP: 4631 nxgep->param_en_1000fdx = val; 4632 param_arr[param_anar_1000fdx].value = val; 4633 4634 goto reprogram; 4635 4636 case MAC_PROP_EN_100FDX_CAP: 4637 nxgep->param_en_100fdx = val; 4638 param_arr[param_anar_100fdx].value = val; 4639 4640 goto reprogram; 4641 4642 case MAC_PROP_EN_10FDX_CAP: 4643 nxgep->param_en_10fdx = val; 4644 param_arr[param_anar_10fdx].value = val; 4645 4646 goto reprogram; 4647 4648 case MAC_PROP_EN_1000HDX_CAP: 4649 case MAC_PROP_EN_100HDX_CAP: 4650 case MAC_PROP_EN_10HDX_CAP: 4651 case MAC_PROP_ADV_1000FDX_CAP: 4652 case MAC_PROP_ADV_1000HDX_CAP: 4653 case MAC_PROP_ADV_100FDX_CAP: 4654 case MAC_PROP_ADV_100HDX_CAP: 4655 case MAC_PROP_ADV_10FDX_CAP: 4656 case MAC_PROP_ADV_10HDX_CAP: 4657 case MAC_PROP_STATUS: 4658 case MAC_PROP_SPEED: 4659 case MAC_PROP_DUPLEX: 4660 err = EINVAL; /* cannot set read-only properties */ 4661 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4662 "==> nxge_m_setprop: read only property %d", 4663 pr_num)); 4664 break; 4665 4666 case MAC_PROP_AUTONEG: 4667 param_arr[param_autoneg].value = val; 4668 4669 goto reprogram; 4670 4671 case MAC_PROP_MTU: 4672 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 4673 err = EBUSY; 4674 break; 4675 } 4676 4677 cur_mtu = nxgep->mac.default_mtu; 4678 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 4679 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4680 "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 4681 new_mtu, nxgep->mac.is_jumbo)); 4682 4683 if (new_mtu == cur_mtu) { 4684 err = 0; 4685 break; 4686 } 4687 if (new_mtu < NXGE_DEFAULT_MTU || 4688 new_mtu > NXGE_MAXIMUM_MTU) { 4689 err = EINVAL; 4690 break; 4691 } 4692 4693 if ((new_mtu > NXGE_DEFAULT_MTU) && 4694 !nxgep->mac.is_jumbo) { 4695 err = EINVAL; 4696 break; 4697 } 4698 4699 old_framesize = (uint32_t)nxgep->mac.maxframesize; 4700 nxgep->mac.maxframesize = (uint16_t) 4701 (new_mtu + NXGE_EHEADER_VLAN_CRC); 4702 if (nxge_mac_set_framesize(nxgep)) { 4703 nxgep->mac.maxframesize = 4704 (uint16_t)old_framesize; 4705 err = EINVAL; 4706 break; 4707 } 4708 4709 err = mac_maxsdu_update(nxgep->mach, new_mtu); 4710 if (err) { 4711 nxgep->mac.maxframesize = 4712 (uint16_t)old_framesize; 4713 err = EINVAL; 4714 break; 4715 } 4716 4717 nxgep->mac.default_mtu = new_mtu; 4718 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4719 "==> nxge_m_setprop: set MTU: %d maxframe %d", 4720 new_mtu, nxgep->mac.maxframesize)); 4721 break; 4722 4723 case MAC_PROP_FLOWCTRL: 4724 bcopy(pr_val, &fl, sizeof (fl)); 4725 switch (fl) { 4726 default: 4727 err = EINVAL; 4728 break; 4729 4730 case LINK_FLOWCTRL_NONE: 4731 param_arr[param_anar_pause].value = 0; 4732 break; 4733 4734 case LINK_FLOWCTRL_RX: 4735 param_arr[param_anar_pause].value = 1; 4736 break; 4737 4738 case LINK_FLOWCTRL_TX: 4739 case LINK_FLOWCTRL_BI: 4740 err = EINVAL; 4741 break; 4742 } 4743 4744 reprogram: 4745 if (err == 0) { 4746 if (!nxge_param_link_update(nxgep)) { 4747 err = EINVAL; 4748 } 4749 } 4750 break; 4751 case MAC_PROP_PRIVATE: 4752 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4753 "==> nxge_m_setprop: private property")); 4754 err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 4755 pr_val); 4756 break; 4757 4758 default: 4759 err = ENOTSUP; 4760 break; 4761 } 4762 4763 mutex_exit(nxgep->genlock); 4764 4765 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4766 "<== nxge_m_setprop (return %d)", err)); 4767 return (err); 4768 } 4769 4770 static int 4771 nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4772 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 4773 { 4774 nxge_t *nxgep = barg; 4775 p_nxge_param_t param_arr = nxgep->param_arr; 4776 p_nxge_stats_t statsp = nxgep->statsp; 4777 int err = 0; 4778 link_flowctrl_t fl; 4779 uint64_t tmp = 0; 4780 link_state_t ls; 4781 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 4782 4783 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4784 "==> nxge_m_getprop: pr_num %d", pr_num)); 4785 4786 if (pr_valsize == 0) 4787 return (EINVAL); 4788 4789 if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 4790 err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 4791 return (err); 4792 } 4793 4794 bzero(pr_val, pr_valsize); 4795 switch (pr_num) { 4796 case MAC_PROP_DUPLEX: 4797 *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 4798 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4799 "==> nxge_m_getprop: duplex mode %d", 4800 *(uint8_t *)pr_val)); 4801 break; 4802 4803 case MAC_PROP_SPEED: 4804 if (pr_valsize < sizeof (uint64_t)) 4805 return (EINVAL); 4806 tmp = statsp->mac_stats.link_speed * 1000000ull; 4807 bcopy(&tmp, pr_val, sizeof (tmp)); 4808 break; 4809 4810 case MAC_PROP_STATUS: 4811 if (pr_valsize < sizeof (link_state_t)) 4812 return (EINVAL); 4813 if (!statsp->mac_stats.link_up) 4814 ls = LINK_STATE_DOWN; 4815 else 4816 ls = LINK_STATE_UP; 4817 bcopy(&ls, pr_val, sizeof (ls)); 4818 break; 4819 4820 case MAC_PROP_AUTONEG: 4821 *(uint8_t *)pr_val = 4822 param_arr[param_autoneg].value; 4823 break; 4824 4825 case MAC_PROP_FLOWCTRL: 4826 if (pr_valsize < sizeof (link_flowctrl_t)) 4827 return (EINVAL); 4828 4829 fl = LINK_FLOWCTRL_NONE; 4830 if (param_arr[param_anar_pause].value) { 4831 fl = LINK_FLOWCTRL_RX; 4832 } 4833 bcopy(&fl, pr_val, sizeof (fl)); 4834 break; 4835 4836 case MAC_PROP_ADV_1000FDX_CAP: 4837 *(uint8_t *)pr_val = 4838 param_arr[param_anar_1000fdx].value; 4839 break; 4840 4841 case MAC_PROP_EN_1000FDX_CAP: 4842 *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 4843 break; 4844 4845 case MAC_PROP_ADV_100FDX_CAP: 4846 *(uint8_t *)pr_val = 4847 param_arr[param_anar_100fdx].value; 4848 break; 4849 4850 case MAC_PROP_EN_100FDX_CAP: 4851 *(uint8_t *)pr_val = nxgep->param_en_100fdx; 4852 break; 4853 4854 case MAC_PROP_ADV_10FDX_CAP: 4855 *(uint8_t *)pr_val = 4856 param_arr[param_anar_10fdx].value; 4857 break; 4858 4859 case MAC_PROP_EN_10FDX_CAP: 4860 *(uint8_t *)pr_val = nxgep->param_en_10fdx; 4861 break; 4862 4863 case MAC_PROP_EN_1000HDX_CAP: 4864 case MAC_PROP_EN_100HDX_CAP: 4865 case MAC_PROP_EN_10HDX_CAP: 4866 case MAC_PROP_ADV_1000HDX_CAP: 4867 case MAC_PROP_ADV_100HDX_CAP: 4868 case MAC_PROP_ADV_10HDX_CAP: 4869 err = ENOTSUP; 4870 break; 4871 4872 case MAC_PROP_PRIVATE: 4873 err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 4874 pr_valsize, pr_val); 4875 break; 4876 default: 4877 err = EINVAL; 4878 break; 4879 } 4880 4881 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 4882 4883 return (err); 4884 } 4885 4886 /* ARGSUSED */ 4887 static int 4888 nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 4889 const void *pr_val) 4890 { 4891 p_nxge_param_t param_arr = nxgep->param_arr; 4892 int err = 0; 4893 long result; 4894 4895 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4896 "==> nxge_set_priv_prop: name %s", pr_name)); 4897 4898 if (strcmp(pr_name, "_accept_jumbo") == 0) { 4899 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4900 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4901 "<== nxge_set_priv_prop: name %s " 4902 "pr_val %s result %d " 4903 "param %d is_jumbo %d", 4904 pr_name, pr_val, result, 4905 param_arr[param_accept_jumbo].value, 4906 nxgep->mac.is_jumbo)); 4907 4908 if (result > 1 || result < 0) { 4909 err = EINVAL; 4910 } else { 4911 if (nxgep->mac.is_jumbo == 4912 (uint32_t)result) { 4913 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4914 "no change (%d %d)", 4915 nxgep->mac.is_jumbo, 4916 result)); 4917 return (0); 4918 } 4919 } 4920 4921 param_arr[param_accept_jumbo].value = result; 4922 nxgep->mac.is_jumbo = B_FALSE; 4923 if (result) { 4924 nxgep->mac.is_jumbo = B_TRUE; 4925 } 4926 4927 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4928 "<== nxge_set_priv_prop: name %s (value %d) is_jumbo %d", 4929 pr_name, result, nxgep->mac.is_jumbo)); 4930 4931 return (err); 4932 } 4933 4934 /* Blanking */ 4935 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 4936 err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 4937 (char *)pr_val, 4938 (caddr_t)¶m_arr[param_rxdma_intr_time]); 4939 if (err) { 4940 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4941 "<== nxge_set_priv_prop: " 4942 "unable to set (%s)", pr_name)); 4943 err = EINVAL; 4944 } else { 4945 err = 0; 4946 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4947 "<== nxge_set_priv_prop: " 4948 "set (%s)", pr_name)); 4949 } 4950 4951 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4952 "<== nxge_set_priv_prop: name %s (value %d)", 4953 pr_name, result)); 4954 4955 return (err); 4956 } 4957 4958 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 4959 err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 4960 (char *)pr_val, 4961 (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 4962 if (err) { 4963 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4964 "<== nxge_set_priv_prop: " 4965 "unable to set (%s)", pr_name)); 4966 err = EINVAL; 4967 } else { 4968 err = 0; 4969 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4970 "<== nxge_set_priv_prop: " 4971 "set (%s)", pr_name)); 4972 } 4973 4974 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4975 "<== nxge_set_priv_prop: name %s (value %d)", 4976 pr_name, result)); 4977 4978 return (err); 4979 } 4980 4981 /* Classification */ 4982 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 4983 if (pr_val == NULL) { 4984 err = EINVAL; 4985 return (err); 4986 } 4987 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4988 4989 err = nxge_param_set_ip_opt(nxgep, NULL, 4990 NULL, (char *)pr_val, 4991 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 4992 4993 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4994 "<== nxge_set_priv_prop: name %s (value 0x%x)", 4995 pr_name, result)); 4996 4997 return (err); 4998 } 4999 5000 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5001 if (pr_val == NULL) { 5002 err = EINVAL; 5003 return (err); 5004 } 5005 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5006 5007 err = nxge_param_set_ip_opt(nxgep, NULL, 5008 NULL, (char *)pr_val, 5009 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5010 5011 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5012 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5013 pr_name, result)); 5014 5015 return (err); 5016 } 5017 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5018 if (pr_val == NULL) { 5019 err = EINVAL; 5020 return (err); 5021 } 5022 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5023 5024 err = nxge_param_set_ip_opt(nxgep, NULL, 5025 NULL, (char *)pr_val, 5026 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5027 5028 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5029 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5030 pr_name, result)); 5031 5032 return (err); 5033 } 5034 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5035 if (pr_val == NULL) { 5036 err = EINVAL; 5037 return (err); 5038 } 5039 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5040 5041 err = nxge_param_set_ip_opt(nxgep, NULL, 5042 NULL, (char *)pr_val, 5043 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5044 5045 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5046 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5047 pr_name, result)); 5048 5049 return (err); 5050 } 5051 5052 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5053 if (pr_val == NULL) { 5054 err = EINVAL; 5055 return (err); 5056 } 5057 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5058 5059 err = nxge_param_set_ip_opt(nxgep, NULL, 5060 NULL, (char *)pr_val, 5061 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5062 5063 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5064 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5065 pr_name, result)); 5066 5067 return (err); 5068 } 5069 5070 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5071 if (pr_val == NULL) { 5072 err = EINVAL; 5073 return (err); 5074 } 5075 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5076 5077 err = nxge_param_set_ip_opt(nxgep, NULL, 5078 NULL, (char *)pr_val, 5079 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5080 5081 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5082 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5083 pr_name, result)); 5084 5085 return (err); 5086 } 5087 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5088 if (pr_val == NULL) { 5089 err = EINVAL; 5090 return (err); 5091 } 5092 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5093 5094 err = nxge_param_set_ip_opt(nxgep, NULL, 5095 NULL, (char *)pr_val, 5096 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5097 5098 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5099 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5100 pr_name, result)); 5101 5102 return (err); 5103 } 5104 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5105 if (pr_val == NULL) { 5106 err = EINVAL; 5107 return (err); 5108 } 5109 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5110 5111 err = nxge_param_set_ip_opt(nxgep, NULL, 5112 NULL, (char *)pr_val, 5113 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5114 5115 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5116 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5117 pr_name, result)); 5118 5119 return (err); 5120 } 5121 5122 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5123 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 5124 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5125 "==> nxge_set_priv_prop: name %s (busy)", pr_name)); 5126 err = EBUSY; 5127 return (err); 5128 } 5129 if (pr_val == NULL) { 5130 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5131 "==> nxge_set_priv_prop: name %s (null)", pr_name)); 5132 err = EINVAL; 5133 return (err); 5134 } 5135 5136 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5137 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5138 "<== nxge_set_priv_prop: name %s " 5139 "(lso %d pr_val %s value %d)", 5140 pr_name, nxgep->soft_lso_enable, pr_val, result)); 5141 5142 if (result > 1 || result < 0) { 5143 err = EINVAL; 5144 } else { 5145 if (nxgep->soft_lso_enable == (uint32_t)result) { 5146 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5147 "no change (%d %d)", 5148 nxgep->soft_lso_enable, result)); 5149 return (0); 5150 } 5151 } 5152 5153 nxgep->soft_lso_enable = (int)result; 5154 5155 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5156 "<== nxge_set_priv_prop: name %s (value %d)", 5157 pr_name, result)); 5158 5159 return (err); 5160 } 5161 /* 5162 * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 5163 * following code to be executed. 5164 */ 5165 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5166 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 5167 (caddr_t)¶m_arr[param_anar_10gfdx]); 5168 return (err); 5169 } 5170 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5171 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 5172 (caddr_t)¶m_arr[param_anar_pause]); 5173 return (err); 5174 } 5175 5176 return (EINVAL); 5177 } 5178 5179 static int 5180 nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 5181 uint_t pr_valsize, void *pr_val) 5182 { 5183 p_nxge_param_t param_arr = nxgep->param_arr; 5184 char valstr[MAXNAMELEN]; 5185 int err = EINVAL; 5186 uint_t strsize; 5187 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 5188 5189 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5190 "==> nxge_get_priv_prop: property %s", pr_name)); 5191 5192 /* function number */ 5193 if (strcmp(pr_name, "_function_number") == 0) { 5194 if (is_default) 5195 return (ENOTSUP); 5196 (void) snprintf(valstr, sizeof (valstr), "%d", 5197 nxgep->function_num); 5198 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5199 "==> nxge_get_priv_prop: name %s " 5200 "(value %d valstr %s)", 5201 pr_name, nxgep->function_num, valstr)); 5202 5203 err = 0; 5204 goto done; 5205 } 5206 5207 /* Neptune firmware version */ 5208 if (strcmp(pr_name, "_fw_version") == 0) { 5209 if (is_default) 5210 return (ENOTSUP); 5211 (void) snprintf(valstr, sizeof (valstr), "%s", 5212 nxgep->vpd_info.ver); 5213 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5214 "==> nxge_get_priv_prop: name %s " 5215 "(value %d valstr %s)", 5216 pr_name, nxgep->vpd_info.ver, valstr)); 5217 5218 err = 0; 5219 goto done; 5220 } 5221 5222 /* port PHY mode */ 5223 if (strcmp(pr_name, "_port_mode") == 0) { 5224 if (is_default) 5225 return (ENOTSUP); 5226 switch (nxgep->mac.portmode) { 5227 case PORT_1G_COPPER: 5228 (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 5229 nxgep->hot_swappable_phy ? 5230 "[Hot Swappable]" : ""); 5231 break; 5232 case PORT_1G_FIBER: 5233 (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 5234 nxgep->hot_swappable_phy ? 5235 "[hot swappable]" : ""); 5236 break; 5237 case PORT_10G_COPPER: 5238 (void) snprintf(valstr, sizeof (valstr), 5239 "10G copper %s", 5240 nxgep->hot_swappable_phy ? 5241 "[hot swappable]" : ""); 5242 break; 5243 case PORT_10G_FIBER: 5244 (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 5245 nxgep->hot_swappable_phy ? 5246 "[hot swappable]" : ""); 5247 break; 5248 case PORT_10G_SERDES: 5249 (void) snprintf(valstr, sizeof (valstr), 5250 "10G serdes %s", nxgep->hot_swappable_phy ? 5251 "[hot swappable]" : ""); 5252 break; 5253 case PORT_1G_SERDES: 5254 (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 5255 nxgep->hot_swappable_phy ? 5256 "[hot swappable]" : ""); 5257 break; 5258 case PORT_1G_TN1010: 5259 (void) snprintf(valstr, sizeof (valstr), 5260 "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 5261 "[hot swappable]" : ""); 5262 break; 5263 case PORT_10G_TN1010: 5264 (void) snprintf(valstr, sizeof (valstr), 5265 "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 5266 "[hot swappable]" : ""); 5267 break; 5268 case PORT_1G_RGMII_FIBER: 5269 (void) snprintf(valstr, sizeof (valstr), 5270 "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 5271 "[hot swappable]" : ""); 5272 break; 5273 case PORT_HSP_MODE: 5274 (void) snprintf(valstr, sizeof (valstr), 5275 "phy not present[hot swappable]"); 5276 break; 5277 default: 5278 (void) snprintf(valstr, sizeof (valstr), "unknown %s", 5279 nxgep->hot_swappable_phy ? 5280 "[hot swappable]" : ""); 5281 break; 5282 } 5283 5284 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5285 "==> nxge_get_priv_prop: name %s (value %s)", 5286 pr_name, valstr)); 5287 5288 err = 0; 5289 goto done; 5290 } 5291 5292 /* Hot swappable PHY */ 5293 if (strcmp(pr_name, "_hot_swap_phy") == 0) { 5294 if (is_default) 5295 return (ENOTSUP); 5296 (void) snprintf(valstr, sizeof (valstr), "%s", 5297 nxgep->hot_swappable_phy ? 5298 "yes" : "no"); 5299 5300 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5301 "==> nxge_get_priv_prop: name %s " 5302 "(value %d valstr %s)", 5303 pr_name, nxgep->hot_swappable_phy, valstr)); 5304 5305 err = 0; 5306 goto done; 5307 } 5308 5309 5310 /* accept jumbo */ 5311 if (strcmp(pr_name, "_accept_jumbo") == 0) { 5312 if (is_default) 5313 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5314 else 5315 (void) snprintf(valstr, sizeof (valstr), 5316 "%d", nxgep->mac.is_jumbo); 5317 err = 0; 5318 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5319 "==> nxge_get_priv_prop: name %s (value %d (%d, %d))", 5320 pr_name, 5321 (uint32_t)param_arr[param_accept_jumbo].value, 5322 nxgep->mac.is_jumbo, 5323 nxge_jumbo_enable)); 5324 5325 goto done; 5326 } 5327 5328 /* Receive Interrupt Blanking Parameters */ 5329 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 5330 err = 0; 5331 if (is_default) { 5332 (void) snprintf(valstr, sizeof (valstr), 5333 "%d", RXDMA_RCR_TO_DEFAULT); 5334 goto done; 5335 } 5336 5337 (void) snprintf(valstr, sizeof (valstr), "%d", 5338 nxgep->intr_timeout); 5339 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5340 "==> nxge_get_priv_prop: name %s (value %d)", 5341 pr_name, 5342 (uint32_t)nxgep->intr_timeout)); 5343 goto done; 5344 } 5345 5346 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 5347 err = 0; 5348 if (is_default) { 5349 (void) snprintf(valstr, sizeof (valstr), 5350 "%d", RXDMA_RCR_PTHRES_DEFAULT); 5351 goto done; 5352 } 5353 (void) snprintf(valstr, sizeof (valstr), "%d", 5354 nxgep->intr_threshold); 5355 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5356 "==> nxge_get_priv_prop: name %s (value %d)", 5357 pr_name, (uint32_t)nxgep->intr_threshold)); 5358 5359 goto done; 5360 } 5361 5362 /* Classification and Load Distribution Configuration */ 5363 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 5364 if (is_default) { 5365 (void) snprintf(valstr, sizeof (valstr), "%x", 5366 NXGE_CLASS_FLOW_GEN_SERVER); 5367 err = 0; 5368 goto done; 5369 } 5370 err = nxge_dld_get_ip_opt(nxgep, 5371 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 5372 5373 (void) snprintf(valstr, sizeof (valstr), "%x", 5374 (int)param_arr[param_class_opt_ipv4_tcp].value); 5375 5376 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5377 "==> nxge_get_priv_prop: %s", valstr)); 5378 goto done; 5379 } 5380 5381 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5382 if (is_default) { 5383 (void) snprintf(valstr, sizeof (valstr), "%x", 5384 NXGE_CLASS_FLOW_GEN_SERVER); 5385 err = 0; 5386 goto done; 5387 } 5388 err = nxge_dld_get_ip_opt(nxgep, 5389 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5390 5391 (void) snprintf(valstr, sizeof (valstr), "%x", 5392 (int)param_arr[param_class_opt_ipv4_udp].value); 5393 5394 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5395 "==> nxge_get_priv_prop: %s", valstr)); 5396 goto done; 5397 } 5398 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5399 if (is_default) { 5400 (void) snprintf(valstr, sizeof (valstr), "%x", 5401 NXGE_CLASS_FLOW_GEN_SERVER); 5402 err = 0; 5403 goto done; 5404 } 5405 err = nxge_dld_get_ip_opt(nxgep, 5406 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5407 5408 (void) snprintf(valstr, sizeof (valstr), "%x", 5409 (int)param_arr[param_class_opt_ipv4_ah].value); 5410 5411 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5412 "==> nxge_get_priv_prop: %s", valstr)); 5413 goto done; 5414 } 5415 5416 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5417 if (is_default) { 5418 (void) snprintf(valstr, sizeof (valstr), "%x", 5419 NXGE_CLASS_FLOW_GEN_SERVER); 5420 err = 0; 5421 goto done; 5422 } 5423 err = nxge_dld_get_ip_opt(nxgep, 5424 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5425 5426 (void) snprintf(valstr, sizeof (valstr), "%x", 5427 (int)param_arr[param_class_opt_ipv4_sctp].value); 5428 5429 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5430 "==> nxge_get_priv_prop: %s", valstr)); 5431 goto done; 5432 } 5433 5434 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5435 if (is_default) { 5436 (void) snprintf(valstr, sizeof (valstr), "%x", 5437 NXGE_CLASS_FLOW_GEN_SERVER); 5438 err = 0; 5439 goto done; 5440 } 5441 err = nxge_dld_get_ip_opt(nxgep, 5442 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5443 5444 (void) snprintf(valstr, sizeof (valstr), "%x", 5445 (int)param_arr[param_class_opt_ipv6_tcp].value); 5446 5447 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5448 "==> nxge_get_priv_prop: %s", valstr)); 5449 goto done; 5450 } 5451 5452 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5453 if (is_default) { 5454 (void) snprintf(valstr, sizeof (valstr), "%x", 5455 NXGE_CLASS_FLOW_GEN_SERVER); 5456 err = 0; 5457 goto done; 5458 } 5459 err = nxge_dld_get_ip_opt(nxgep, 5460 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5461 5462 (void) snprintf(valstr, sizeof (valstr), "%x", 5463 (int)param_arr[param_class_opt_ipv6_udp].value); 5464 5465 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5466 "==> nxge_get_priv_prop: %s", valstr)); 5467 goto done; 5468 } 5469 5470 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5471 if (is_default) { 5472 (void) snprintf(valstr, sizeof (valstr), "%x", 5473 NXGE_CLASS_FLOW_GEN_SERVER); 5474 err = 0; 5475 goto done; 5476 } 5477 err = nxge_dld_get_ip_opt(nxgep, 5478 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5479 5480 (void) snprintf(valstr, sizeof (valstr), "%x", 5481 (int)param_arr[param_class_opt_ipv6_ah].value); 5482 5483 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5484 "==> nxge_get_priv_prop: %s", valstr)); 5485 goto done; 5486 } 5487 5488 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5489 if (is_default) { 5490 (void) snprintf(valstr, sizeof (valstr), "%x", 5491 NXGE_CLASS_FLOW_GEN_SERVER); 5492 err = 0; 5493 goto done; 5494 } 5495 err = nxge_dld_get_ip_opt(nxgep, 5496 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5497 5498 (void) snprintf(valstr, sizeof (valstr), "%x", 5499 (int)param_arr[param_class_opt_ipv6_sctp].value); 5500 5501 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5502 "==> nxge_get_priv_prop: %s", valstr)); 5503 goto done; 5504 } 5505 5506 /* Software LSO */ 5507 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5508 if (is_default) { 5509 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5510 err = 0; 5511 goto done; 5512 } 5513 (void) snprintf(valstr, sizeof (valstr), 5514 "%d", nxgep->soft_lso_enable); 5515 err = 0; 5516 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5517 "==> nxge_get_priv_prop: name %s (value %d)", 5518 pr_name, nxgep->soft_lso_enable)); 5519 5520 goto done; 5521 } 5522 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5523 err = 0; 5524 if (is_default || 5525 nxgep->param_arr[param_anar_10gfdx].value != 0) { 5526 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5527 goto done; 5528 } else { 5529 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5530 goto done; 5531 } 5532 } 5533 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5534 err = 0; 5535 if (is_default || 5536 nxgep->param_arr[param_anar_pause].value != 0) { 5537 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5538 goto done; 5539 } else { 5540 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5541 goto done; 5542 } 5543 } 5544 5545 done: 5546 if (err == 0) { 5547 strsize = (uint_t)strlen(valstr); 5548 if (pr_valsize < strsize) { 5549 err = ENOBUFS; 5550 } else { 5551 (void) strlcpy(pr_val, valstr, pr_valsize); 5552 } 5553 } 5554 5555 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5556 "<== nxge_get_priv_prop: return %d", err)); 5557 return (err); 5558 } 5559 5560 /* 5561 * Module loading and removing entry points. 5562 */ 5563 5564 DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 5565 nodev, NULL, D_MP, NULL); 5566 5567 #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 5568 5569 /* 5570 * Module linkage information for the kernel. 5571 */ 5572 static struct modldrv nxge_modldrv = { 5573 &mod_driverops, 5574 NXGE_DESC_VER, 5575 &nxge_dev_ops 5576 }; 5577 5578 static struct modlinkage modlinkage = { 5579 MODREV_1, (void *) &nxge_modldrv, NULL 5580 }; 5581 5582 int 5583 _init(void) 5584 { 5585 int status; 5586 5587 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 5588 mac_init_ops(&nxge_dev_ops, "nxge"); 5589 status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 5590 if (status != 0) { 5591 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 5592 "failed to init device soft state")); 5593 goto _init_exit; 5594 } 5595 status = mod_install(&modlinkage); 5596 if (status != 0) { 5597 ddi_soft_state_fini(&nxge_list); 5598 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 5599 goto _init_exit; 5600 } 5601 5602 MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 5603 5604 _init_exit: 5605 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status)); 5606 5607 return (status); 5608 } 5609 5610 int 5611 _fini(void) 5612 { 5613 int status; 5614 5615 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 5616 5617 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5618 5619 if (nxge_mblks_pending) 5620 return (EBUSY); 5621 5622 status = mod_remove(&modlinkage); 5623 if (status != DDI_SUCCESS) { 5624 NXGE_DEBUG_MSG((NULL, MOD_CTL, 5625 "Module removal failed 0x%08x", 5626 status)); 5627 goto _fini_exit; 5628 } 5629 5630 mac_fini_ops(&nxge_dev_ops); 5631 5632 ddi_soft_state_fini(&nxge_list); 5633 5634 MUTEX_DESTROY(&nxge_common_lock); 5635 _fini_exit: 5636 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status)); 5637 5638 return (status); 5639 } 5640 5641 int 5642 _info(struct modinfo *modinfop) 5643 { 5644 int status; 5645 5646 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 5647 status = mod_info(&modlinkage, modinfop); 5648 NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 5649 5650 return (status); 5651 } 5652 5653 /*ARGSUSED*/ 5654 static nxge_status_t 5655 nxge_add_intrs(p_nxge_t nxgep) 5656 { 5657 5658 int intr_types; 5659 int type = 0; 5660 int ddi_status = DDI_SUCCESS; 5661 nxge_status_t status = NXGE_OK; 5662 5663 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 5664 5665 nxgep->nxge_intr_type.intr_registered = B_FALSE; 5666 nxgep->nxge_intr_type.intr_enabled = B_FALSE; 5667 nxgep->nxge_intr_type.msi_intx_cnt = 0; 5668 nxgep->nxge_intr_type.intr_added = 0; 5669 nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 5670 nxgep->nxge_intr_type.intr_type = 0; 5671 5672 if (nxgep->niu_type == N2_NIU) { 5673 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5674 } else if (nxge_msi_enable) { 5675 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5676 } 5677 5678 /* Get the supported interrupt types */ 5679 if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 5680 != DDI_SUCCESS) { 5681 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 5682 "ddi_intr_get_supported_types failed: status 0x%08x", 5683 ddi_status)); 5684 return (NXGE_ERROR | NXGE_DDI_FAILED); 5685 } 5686 nxgep->nxge_intr_type.intr_types = intr_types; 5687 5688 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5689 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5690 5691 /* 5692 * Solaris MSIX is not supported yet. use MSI for now. 5693 * nxge_msi_enable (1): 5694 * 1 - MSI 2 - MSI-X others - FIXED 5695 */ 5696 switch (nxge_msi_enable) { 5697 default: 5698 type = DDI_INTR_TYPE_FIXED; 5699 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5700 "use fixed (intx emulation) type %08x", 5701 type)); 5702 break; 5703 5704 case 2: 5705 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5706 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5707 if (intr_types & DDI_INTR_TYPE_MSIX) { 5708 type = DDI_INTR_TYPE_MSIX; 5709 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5710 "ddi_intr_get_supported_types: MSIX 0x%08x", 5711 type)); 5712 } else if (intr_types & DDI_INTR_TYPE_MSI) { 5713 type = DDI_INTR_TYPE_MSI; 5714 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5715 "ddi_intr_get_supported_types: MSI 0x%08x", 5716 type)); 5717 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5718 type = DDI_INTR_TYPE_FIXED; 5719 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5720 "ddi_intr_get_supported_types: MSXED0x%08x", 5721 type)); 5722 } 5723 break; 5724 5725 case 1: 5726 if (intr_types & DDI_INTR_TYPE_MSI) { 5727 type = DDI_INTR_TYPE_MSI; 5728 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5729 "ddi_intr_get_supported_types: MSI 0x%08x", 5730 type)); 5731 } else if (intr_types & DDI_INTR_TYPE_MSIX) { 5732 type = DDI_INTR_TYPE_MSIX; 5733 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5734 "ddi_intr_get_supported_types: MSIX 0x%08x", 5735 type)); 5736 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5737 type = DDI_INTR_TYPE_FIXED; 5738 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5739 "ddi_intr_get_supported_types: MSXED0x%08x", 5740 type)); 5741 } 5742 } 5743 5744 nxgep->nxge_intr_type.intr_type = type; 5745 if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 5746 type == DDI_INTR_TYPE_FIXED) && 5747 nxgep->nxge_intr_type.niu_msi_enable) { 5748 if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 5749 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5750 " nxge_add_intrs: " 5751 " nxge_add_intrs_adv failed: status 0x%08x", 5752 status)); 5753 return (status); 5754 } else { 5755 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5756 "interrupts registered : type %d", type)); 5757 nxgep->nxge_intr_type.intr_registered = B_TRUE; 5758 5759 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 5760 "\nAdded advanced nxge add_intr_adv " 5761 "intr type 0x%x\n", type)); 5762 5763 return (status); 5764 } 5765 } 5766 5767 if (!nxgep->nxge_intr_type.intr_registered) { 5768 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 5769 "failed to register interrupts")); 5770 return (NXGE_ERROR | NXGE_DDI_FAILED); 5771 } 5772 5773 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 5774 return (status); 5775 } 5776 5777 /*ARGSUSED*/ 5778 static nxge_status_t 5779 nxge_add_soft_intrs(p_nxge_t nxgep) 5780 { 5781 5782 int ddi_status = DDI_SUCCESS; 5783 nxge_status_t status = NXGE_OK; 5784 5785 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_soft_intrs")); 5786 5787 nxgep->resched_id = NULL; 5788 nxgep->resched_running = B_FALSE; 5789 ddi_status = ddi_add_softintr(nxgep->dip, DDI_SOFTINT_LOW, 5790 &nxgep->resched_id, 5791 NULL, NULL, nxge_reschedule, (caddr_t)nxgep); 5792 if (ddi_status != DDI_SUCCESS) { 5793 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_soft_intrs: " 5794 "ddi_add_softintrs failed: status 0x%08x", 5795 ddi_status)); 5796 return (NXGE_ERROR | NXGE_DDI_FAILED); 5797 } 5798 5799 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_ddi_add_soft_intrs")); 5800 5801 return (status); 5802 } 5803 5804 static nxge_status_t 5805 nxge_add_intrs_adv(p_nxge_t nxgep) 5806 { 5807 int intr_type; 5808 p_nxge_intr_t intrp; 5809 5810 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 5811 5812 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5813 intr_type = intrp->intr_type; 5814 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 5815 intr_type)); 5816 5817 switch (intr_type) { 5818 case DDI_INTR_TYPE_MSI: /* 0x2 */ 5819 case DDI_INTR_TYPE_MSIX: /* 0x4 */ 5820 return (nxge_add_intrs_adv_type(nxgep, intr_type)); 5821 5822 case DDI_INTR_TYPE_FIXED: /* 0x1 */ 5823 return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 5824 5825 default: 5826 return (NXGE_ERROR); 5827 } 5828 } 5829 5830 5831 /*ARGSUSED*/ 5832 static nxge_status_t 5833 nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 5834 { 5835 dev_info_t *dip = nxgep->dip; 5836 p_nxge_ldg_t ldgp; 5837 p_nxge_intr_t intrp; 5838 uint_t *inthandler; 5839 void *arg1, *arg2; 5840 int behavior; 5841 int nintrs, navail, nrequest; 5842 int nactual, nrequired; 5843 int inum = 0; 5844 int x, y; 5845 int ddi_status = DDI_SUCCESS; 5846 nxge_status_t status = NXGE_OK; 5847 5848 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 5849 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5850 intrp->start_inum = 0; 5851 5852 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 5853 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 5854 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5855 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 5856 "nintrs: %d", ddi_status, nintrs)); 5857 return (NXGE_ERROR | NXGE_DDI_FAILED); 5858 } 5859 5860 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 5861 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 5862 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5863 "ddi_intr_get_navail() failed, status: 0x%x%, " 5864 "nintrs: %d", ddi_status, navail)); 5865 return (NXGE_ERROR | NXGE_DDI_FAILED); 5866 } 5867 5868 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5869 "ddi_intr_get_navail() returned: nintrs %d, navail %d", 5870 nintrs, navail)); 5871 5872 /* PSARC/2007/453 MSI-X interrupt limit override */ 5873 if (int_type == DDI_INTR_TYPE_MSIX) { 5874 nrequest = nxge_create_msi_property(nxgep); 5875 if (nrequest < navail) { 5876 navail = nrequest; 5877 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5878 "nxge_add_intrs_adv_type: nintrs %d " 5879 "navail %d (nrequest %d)", 5880 nintrs, navail, nrequest)); 5881 } 5882 } 5883 5884 if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 5885 /* MSI must be power of 2 */ 5886 if ((navail & 16) == 16) { 5887 navail = 16; 5888 } else if ((navail & 8) == 8) { 5889 navail = 8; 5890 } else if ((navail & 4) == 4) { 5891 navail = 4; 5892 } else if ((navail & 2) == 2) { 5893 navail = 2; 5894 } else { 5895 navail = 1; 5896 } 5897 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5898 "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 5899 "navail %d", nintrs, navail)); 5900 } 5901 5902 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 5903 DDI_INTR_ALLOC_NORMAL); 5904 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 5905 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 5906 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 5907 navail, &nactual, behavior); 5908 if (ddi_status != DDI_SUCCESS || nactual == 0) { 5909 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5910 " ddi_intr_alloc() failed: %d", 5911 ddi_status)); 5912 kmem_free(intrp->htable, intrp->intr_size); 5913 return (NXGE_ERROR | NXGE_DDI_FAILED); 5914 } 5915 5916 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 5917 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 5918 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5919 " ddi_intr_get_pri() failed: %d", 5920 ddi_status)); 5921 /* Free already allocated interrupts */ 5922 for (y = 0; y < nactual; y++) { 5923 (void) ddi_intr_free(intrp->htable[y]); 5924 } 5925 5926 kmem_free(intrp->htable, intrp->intr_size); 5927 return (NXGE_ERROR | NXGE_DDI_FAILED); 5928 } 5929 5930 nrequired = 0; 5931 switch (nxgep->niu_type) { 5932 default: 5933 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 5934 break; 5935 5936 case N2_NIU: 5937 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 5938 break; 5939 } 5940 5941 if (status != NXGE_OK) { 5942 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5943 "nxge_add_intrs_adv_typ:nxge_ldgv_init " 5944 "failed: 0x%x", status)); 5945 /* Free already allocated interrupts */ 5946 for (y = 0; y < nactual; y++) { 5947 (void) ddi_intr_free(intrp->htable[y]); 5948 } 5949 5950 kmem_free(intrp->htable, intrp->intr_size); 5951 return (status); 5952 } 5953 5954 ldgp = nxgep->ldgvp->ldgp; 5955 for (x = 0; x < nrequired; x++, ldgp++) { 5956 ldgp->vector = (uint8_t)x; 5957 ldgp->intdata = SID_DATA(ldgp->func, x); 5958 arg1 = ldgp->ldvp; 5959 arg2 = nxgep; 5960 if (ldgp->nldvs == 1) { 5961 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 5962 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5963 "nxge_add_intrs_adv_type: " 5964 "arg1 0x%x arg2 0x%x: " 5965 "1-1 int handler (entry %d intdata 0x%x)\n", 5966 arg1, arg2, 5967 x, ldgp->intdata)); 5968 } else if (ldgp->nldvs > 1) { 5969 inthandler = (uint_t *)ldgp->sys_intr_handler; 5970 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5971 "nxge_add_intrs_adv_type: " 5972 "arg1 0x%x arg2 0x%x: " 5973 "nldevs %d int handler " 5974 "(entry %d intdata 0x%x)\n", 5975 arg1, arg2, 5976 ldgp->nldvs, x, ldgp->intdata)); 5977 } 5978 5979 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5980 "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 5981 "htable 0x%llx", x, intrp->htable[x])); 5982 5983 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 5984 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 5985 != DDI_SUCCESS) { 5986 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5987 "==> nxge_add_intrs_adv_type: failed #%d " 5988 "status 0x%x", x, ddi_status)); 5989 for (y = 0; y < intrp->intr_added; y++) { 5990 (void) ddi_intr_remove_handler( 5991 intrp->htable[y]); 5992 } 5993 /* Free already allocated intr */ 5994 for (y = 0; y < nactual; y++) { 5995 (void) ddi_intr_free(intrp->htable[y]); 5996 } 5997 kmem_free(intrp->htable, intrp->intr_size); 5998 5999 (void) nxge_ldgv_uninit(nxgep); 6000 6001 return (NXGE_ERROR | NXGE_DDI_FAILED); 6002 } 6003 intrp->intr_added++; 6004 } 6005 6006 intrp->msi_intx_cnt = nactual; 6007 6008 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6009 "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 6010 navail, nactual, 6011 intrp->msi_intx_cnt, 6012 intrp->intr_added)); 6013 6014 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6015 6016 (void) nxge_intr_ldgv_init(nxgep); 6017 6018 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 6019 6020 return (status); 6021 } 6022 6023 /*ARGSUSED*/ 6024 static nxge_status_t 6025 nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 6026 { 6027 dev_info_t *dip = nxgep->dip; 6028 p_nxge_ldg_t ldgp; 6029 p_nxge_intr_t intrp; 6030 uint_t *inthandler; 6031 void *arg1, *arg2; 6032 int behavior; 6033 int nintrs, navail; 6034 int nactual, nrequired; 6035 int inum = 0; 6036 int x, y; 6037 int ddi_status = DDI_SUCCESS; 6038 nxge_status_t status = NXGE_OK; 6039 6040 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 6041 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6042 intrp->start_inum = 0; 6043 6044 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 6045 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 6046 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6047 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 6048 "nintrs: %d", status, nintrs)); 6049 return (NXGE_ERROR | NXGE_DDI_FAILED); 6050 } 6051 6052 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 6053 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 6054 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6055 "ddi_intr_get_navail() failed, status: 0x%x%, " 6056 "nintrs: %d", ddi_status, navail)); 6057 return (NXGE_ERROR | NXGE_DDI_FAILED); 6058 } 6059 6060 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6061 "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 6062 nintrs, navail)); 6063 6064 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 6065 DDI_INTR_ALLOC_NORMAL); 6066 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 6067 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 6068 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 6069 navail, &nactual, behavior); 6070 if (ddi_status != DDI_SUCCESS || nactual == 0) { 6071 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6072 " ddi_intr_alloc() failed: %d", 6073 ddi_status)); 6074 kmem_free(intrp->htable, intrp->intr_size); 6075 return (NXGE_ERROR | NXGE_DDI_FAILED); 6076 } 6077 6078 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 6079 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 6080 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6081 " ddi_intr_get_pri() failed: %d", 6082 ddi_status)); 6083 /* Free already allocated interrupts */ 6084 for (y = 0; y < nactual; y++) { 6085 (void) ddi_intr_free(intrp->htable[y]); 6086 } 6087 6088 kmem_free(intrp->htable, intrp->intr_size); 6089 return (NXGE_ERROR | NXGE_DDI_FAILED); 6090 } 6091 6092 nrequired = 0; 6093 switch (nxgep->niu_type) { 6094 default: 6095 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 6096 break; 6097 6098 case N2_NIU: 6099 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 6100 break; 6101 } 6102 6103 if (status != NXGE_OK) { 6104 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6105 "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 6106 "failed: 0x%x", status)); 6107 /* Free already allocated interrupts */ 6108 for (y = 0; y < nactual; y++) { 6109 (void) ddi_intr_free(intrp->htable[y]); 6110 } 6111 6112 kmem_free(intrp->htable, intrp->intr_size); 6113 return (status); 6114 } 6115 6116 ldgp = nxgep->ldgvp->ldgp; 6117 for (x = 0; x < nrequired; x++, ldgp++) { 6118 ldgp->vector = (uint8_t)x; 6119 if (nxgep->niu_type != N2_NIU) { 6120 ldgp->intdata = SID_DATA(ldgp->func, x); 6121 } 6122 6123 arg1 = ldgp->ldvp; 6124 arg2 = nxgep; 6125 if (ldgp->nldvs == 1) { 6126 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 6127 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6128 "nxge_add_intrs_adv_type_fix: " 6129 "1-1 int handler(%d) ldg %d ldv %d " 6130 "arg1 $%p arg2 $%p\n", 6131 x, ldgp->ldg, ldgp->ldvp->ldv, 6132 arg1, arg2)); 6133 } else if (ldgp->nldvs > 1) { 6134 inthandler = (uint_t *)ldgp->sys_intr_handler; 6135 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6136 "nxge_add_intrs_adv_type_fix: " 6137 "shared ldv %d int handler(%d) ldv %d ldg %d" 6138 "arg1 0x%016llx arg2 0x%016llx\n", 6139 x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 6140 arg1, arg2)); 6141 } 6142 6143 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6144 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6145 != DDI_SUCCESS) { 6146 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6147 "==> nxge_add_intrs_adv_type_fix: failed #%d " 6148 "status 0x%x", x, ddi_status)); 6149 for (y = 0; y < intrp->intr_added; y++) { 6150 (void) ddi_intr_remove_handler( 6151 intrp->htable[y]); 6152 } 6153 for (y = 0; y < nactual; y++) { 6154 (void) ddi_intr_free(intrp->htable[y]); 6155 } 6156 /* Free already allocated intr */ 6157 kmem_free(intrp->htable, intrp->intr_size); 6158 6159 (void) nxge_ldgv_uninit(nxgep); 6160 6161 return (NXGE_ERROR | NXGE_DDI_FAILED); 6162 } 6163 intrp->intr_added++; 6164 } 6165 6166 intrp->msi_intx_cnt = nactual; 6167 6168 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6169 6170 status = nxge_intr_ldgv_init(nxgep); 6171 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 6172 6173 return (status); 6174 } 6175 6176 static void 6177 nxge_remove_intrs(p_nxge_t nxgep) 6178 { 6179 int i, inum; 6180 p_nxge_intr_t intrp; 6181 6182 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 6183 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6184 if (!intrp->intr_registered) { 6185 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6186 "<== nxge_remove_intrs: interrupts not registered")); 6187 return; 6188 } 6189 6190 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 6191 6192 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6193 (void) ddi_intr_block_disable(intrp->htable, 6194 intrp->intr_added); 6195 } else { 6196 for (i = 0; i < intrp->intr_added; i++) { 6197 (void) ddi_intr_disable(intrp->htable[i]); 6198 } 6199 } 6200 6201 for (inum = 0; inum < intrp->intr_added; inum++) { 6202 if (intrp->htable[inum]) { 6203 (void) ddi_intr_remove_handler(intrp->htable[inum]); 6204 } 6205 } 6206 6207 for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 6208 if (intrp->htable[inum]) { 6209 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6210 "nxge_remove_intrs: ddi_intr_free inum %d " 6211 "msi_intx_cnt %d intr_added %d", 6212 inum, 6213 intrp->msi_intx_cnt, 6214 intrp->intr_added)); 6215 6216 (void) ddi_intr_free(intrp->htable[inum]); 6217 } 6218 } 6219 6220 kmem_free(intrp->htable, intrp->intr_size); 6221 intrp->intr_registered = B_FALSE; 6222 intrp->intr_enabled = B_FALSE; 6223 intrp->msi_intx_cnt = 0; 6224 intrp->intr_added = 0; 6225 6226 (void) nxge_ldgv_uninit(nxgep); 6227 6228 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6229 "#msix-request"); 6230 6231 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 6232 } 6233 6234 /*ARGSUSED*/ 6235 static void 6236 nxge_remove_soft_intrs(p_nxge_t nxgep) 6237 { 6238 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_soft_intrs")); 6239 if (nxgep->resched_id) { 6240 ddi_remove_softintr(nxgep->resched_id); 6241 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6242 "==> nxge_remove_soft_intrs: removed")); 6243 nxgep->resched_id = NULL; 6244 } 6245 6246 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_soft_intrs")); 6247 } 6248 6249 /*ARGSUSED*/ 6250 static void 6251 nxge_intrs_enable(p_nxge_t nxgep) 6252 { 6253 p_nxge_intr_t intrp; 6254 int i; 6255 int status; 6256 6257 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 6258 6259 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6260 6261 if (!intrp->intr_registered) { 6262 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 6263 "interrupts are not registered")); 6264 return; 6265 } 6266 6267 if (intrp->intr_enabled) { 6268 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6269 "<== nxge_intrs_enable: already enabled")); 6270 return; 6271 } 6272 6273 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6274 status = ddi_intr_block_enable(intrp->htable, 6275 intrp->intr_added); 6276 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6277 "block enable - status 0x%x total inums #%d\n", 6278 status, intrp->intr_added)); 6279 } else { 6280 for (i = 0; i < intrp->intr_added; i++) { 6281 status = ddi_intr_enable(intrp->htable[i]); 6282 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6283 "ddi_intr_enable:enable - status 0x%x " 6284 "total inums %d enable inum #%d\n", 6285 status, intrp->intr_added, i)); 6286 if (status == DDI_SUCCESS) { 6287 intrp->intr_enabled = B_TRUE; 6288 } 6289 } 6290 } 6291 6292 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 6293 } 6294 6295 /*ARGSUSED*/ 6296 static void 6297 nxge_intrs_disable(p_nxge_t nxgep) 6298 { 6299 p_nxge_intr_t intrp; 6300 int i; 6301 6302 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 6303 6304 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6305 6306 if (!intrp->intr_registered) { 6307 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 6308 "interrupts are not registered")); 6309 return; 6310 } 6311 6312 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6313 (void) ddi_intr_block_disable(intrp->htable, 6314 intrp->intr_added); 6315 } else { 6316 for (i = 0; i < intrp->intr_added; i++) { 6317 (void) ddi_intr_disable(intrp->htable[i]); 6318 } 6319 } 6320 6321 intrp->intr_enabled = B_FALSE; 6322 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 6323 } 6324 6325 static nxge_status_t 6326 nxge_mac_register(p_nxge_t nxgep) 6327 { 6328 mac_register_t *macp; 6329 int status; 6330 6331 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 6332 6333 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 6334 return (NXGE_ERROR); 6335 6336 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 6337 macp->m_driver = nxgep; 6338 macp->m_dip = nxgep->dip; 6339 macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 6340 macp->m_callbacks = &nxge_m_callbacks; 6341 macp->m_min_sdu = 0; 6342 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 6343 NXGE_EHEADER_VLAN_CRC; 6344 macp->m_max_sdu = nxgep->mac.default_mtu; 6345 macp->m_margin = VLAN_TAGSZ; 6346 macp->m_priv_props = nxge_priv_props; 6347 macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 6348 6349 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6350 "==> nxge_mac_register: instance %d " 6351 "max_sdu %d margin %d maxframe %d (header %d)", 6352 nxgep->instance, 6353 macp->m_max_sdu, macp->m_margin, 6354 nxgep->mac.maxframesize, 6355 NXGE_EHEADER_VLAN_CRC)); 6356 6357 status = mac_register(macp, &nxgep->mach); 6358 mac_free(macp); 6359 6360 if (status != 0) { 6361 cmn_err(CE_WARN, 6362 "!nxge_mac_register failed (status %d instance %d)", 6363 status, nxgep->instance); 6364 return (NXGE_ERROR); 6365 } 6366 6367 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 6368 "(instance %d)", nxgep->instance)); 6369 6370 return (NXGE_OK); 6371 } 6372 6373 void 6374 nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 6375 { 6376 ssize_t size; 6377 mblk_t *nmp; 6378 uint8_t blk_id; 6379 uint8_t chan; 6380 uint32_t err_id; 6381 err_inject_t *eip; 6382 6383 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 6384 6385 size = 1024; 6386 nmp = mp->b_cont; 6387 eip = (err_inject_t *)nmp->b_rptr; 6388 blk_id = eip->blk_id; 6389 err_id = eip->err_id; 6390 chan = eip->chan; 6391 cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 6392 cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 6393 cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 6394 switch (blk_id) { 6395 case MAC_BLK_ID: 6396 break; 6397 case TXMAC_BLK_ID: 6398 break; 6399 case RXMAC_BLK_ID: 6400 break; 6401 case MIF_BLK_ID: 6402 break; 6403 case IPP_BLK_ID: 6404 nxge_ipp_inject_err(nxgep, err_id); 6405 break; 6406 case TXC_BLK_ID: 6407 nxge_txc_inject_err(nxgep, err_id); 6408 break; 6409 case TXDMA_BLK_ID: 6410 nxge_txdma_inject_err(nxgep, err_id, chan); 6411 break; 6412 case RXDMA_BLK_ID: 6413 nxge_rxdma_inject_err(nxgep, err_id, chan); 6414 break; 6415 case ZCP_BLK_ID: 6416 nxge_zcp_inject_err(nxgep, err_id); 6417 break; 6418 case ESPC_BLK_ID: 6419 break; 6420 case FFLP_BLK_ID: 6421 break; 6422 case PHY_BLK_ID: 6423 break; 6424 case ETHER_SERDES_BLK_ID: 6425 break; 6426 case PCIE_SERDES_BLK_ID: 6427 break; 6428 case VIR_BLK_ID: 6429 break; 6430 } 6431 6432 nmp->b_wptr = nmp->b_rptr + size; 6433 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 6434 6435 miocack(wq, mp, (int)size, 0); 6436 } 6437 6438 static int 6439 nxge_init_common_dev(p_nxge_t nxgep) 6440 { 6441 p_nxge_hw_list_t hw_p; 6442 dev_info_t *p_dip; 6443 6444 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 6445 6446 p_dip = nxgep->p_dip; 6447 MUTEX_ENTER(&nxge_common_lock); 6448 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6449 "==> nxge_init_common_dev:func # %d", 6450 nxgep->function_num)); 6451 /* 6452 * Loop through existing per neptune hardware list. 6453 */ 6454 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6455 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6456 "==> nxge_init_common_device:func # %d " 6457 "hw_p $%p parent dip $%p", 6458 nxgep->function_num, 6459 hw_p, 6460 p_dip)); 6461 if (hw_p->parent_devp == p_dip) { 6462 nxgep->nxge_hw_p = hw_p; 6463 hw_p->ndevs++; 6464 hw_p->nxge_p[nxgep->function_num] = nxgep; 6465 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6466 "==> nxge_init_common_device:func # %d " 6467 "hw_p $%p parent dip $%p " 6468 "ndevs %d (found)", 6469 nxgep->function_num, 6470 hw_p, 6471 p_dip, 6472 hw_p->ndevs)); 6473 break; 6474 } 6475 } 6476 6477 if (hw_p == NULL) { 6478 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6479 "==> nxge_init_common_device:func # %d " 6480 "parent dip $%p (new)", 6481 nxgep->function_num, 6482 p_dip)); 6483 hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 6484 hw_p->parent_devp = p_dip; 6485 hw_p->magic = NXGE_NEPTUNE_MAGIC; 6486 nxgep->nxge_hw_p = hw_p; 6487 hw_p->ndevs++; 6488 hw_p->nxge_p[nxgep->function_num] = nxgep; 6489 hw_p->next = nxge_hw_list; 6490 if (nxgep->niu_type == N2_NIU) { 6491 hw_p->niu_type = N2_NIU; 6492 hw_p->platform_type = P_NEPTUNE_NIU; 6493 } else { 6494 hw_p->niu_type = NIU_TYPE_NONE; 6495 hw_p->platform_type = P_NEPTUNE_NONE; 6496 } 6497 6498 MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 6499 MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 6500 MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 6501 MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 6502 6503 nxge_hw_list = hw_p; 6504 6505 (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 6506 } 6507 6508 MUTEX_EXIT(&nxge_common_lock); 6509 6510 nxgep->platform_type = hw_p->platform_type; 6511 if (nxgep->niu_type != N2_NIU) { 6512 nxgep->niu_type = hw_p->niu_type; 6513 } 6514 6515 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6516 "==> nxge_init_common_device (nxge_hw_list) $%p", 6517 nxge_hw_list)); 6518 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 6519 6520 return (NXGE_OK); 6521 } 6522 6523 static void 6524 nxge_uninit_common_dev(p_nxge_t nxgep) 6525 { 6526 p_nxge_hw_list_t hw_p, h_hw_p; 6527 p_nxge_dma_pt_cfg_t p_dma_cfgp; 6528 p_nxge_hw_pt_cfg_t p_cfgp; 6529 dev_info_t *p_dip; 6530 6531 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 6532 if (nxgep->nxge_hw_p == NULL) { 6533 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6534 "<== nxge_uninit_common_device (no common)")); 6535 return; 6536 } 6537 6538 MUTEX_ENTER(&nxge_common_lock); 6539 h_hw_p = nxge_hw_list; 6540 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6541 p_dip = hw_p->parent_devp; 6542 if (nxgep->nxge_hw_p == hw_p && 6543 p_dip == nxgep->p_dip && 6544 nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 6545 hw_p->magic == NXGE_NEPTUNE_MAGIC) { 6546 6547 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6548 "==> nxge_uninit_common_device:func # %d " 6549 "hw_p $%p parent dip $%p " 6550 "ndevs %d (found)", 6551 nxgep->function_num, 6552 hw_p, 6553 p_dip, 6554 hw_p->ndevs)); 6555 6556 /* 6557 * Release the RDC table, a shared resoruce 6558 * of the nxge hardware. The RDC table was 6559 * assigned to this instance of nxge in 6560 * nxge_use_cfg_dma_config(). 6561 */ 6562 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 6563 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 6564 (void) nxge_fzc_rdc_tbl_unbind(nxgep, 6565 p_cfgp->def_mac_rxdma_grpid); 6566 6567 if (hw_p->ndevs) { 6568 hw_p->ndevs--; 6569 } 6570 hw_p->nxge_p[nxgep->function_num] = NULL; 6571 if (!hw_p->ndevs) { 6572 MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 6573 MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 6574 MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 6575 MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 6576 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6577 "==> nxge_uninit_common_device: " 6578 "func # %d " 6579 "hw_p $%p parent dip $%p " 6580 "ndevs %d (last)", 6581 nxgep->function_num, 6582 hw_p, 6583 p_dip, 6584 hw_p->ndevs)); 6585 6586 nxge_hio_uninit(nxgep); 6587 6588 if (hw_p == nxge_hw_list) { 6589 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6590 "==> nxge_uninit_common_device:" 6591 "remove head func # %d " 6592 "hw_p $%p parent dip $%p " 6593 "ndevs %d (head)", 6594 nxgep->function_num, 6595 hw_p, 6596 p_dip, 6597 hw_p->ndevs)); 6598 nxge_hw_list = hw_p->next; 6599 } else { 6600 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6601 "==> nxge_uninit_common_device:" 6602 "remove middle func # %d " 6603 "hw_p $%p parent dip $%p " 6604 "ndevs %d (middle)", 6605 nxgep->function_num, 6606 hw_p, 6607 p_dip, 6608 hw_p->ndevs)); 6609 h_hw_p->next = hw_p->next; 6610 } 6611 6612 nxgep->nxge_hw_p = NULL; 6613 KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 6614 } 6615 break; 6616 } else { 6617 h_hw_p = hw_p; 6618 } 6619 } 6620 6621 MUTEX_EXIT(&nxge_common_lock); 6622 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6623 "==> nxge_uninit_common_device (nxge_hw_list) $%p", 6624 nxge_hw_list)); 6625 6626 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 6627 } 6628 6629 /* 6630 * Determines the number of ports from the niu_type or the platform type. 6631 * Returns the number of ports, or returns zero on failure. 6632 */ 6633 6634 int 6635 nxge_get_nports(p_nxge_t nxgep) 6636 { 6637 int nports = 0; 6638 6639 switch (nxgep->niu_type) { 6640 case N2_NIU: 6641 case NEPTUNE_2_10GF: 6642 nports = 2; 6643 break; 6644 case NEPTUNE_4_1GC: 6645 case NEPTUNE_2_10GF_2_1GC: 6646 case NEPTUNE_1_10GF_3_1GC: 6647 case NEPTUNE_1_1GC_1_10GF_2_1GC: 6648 case NEPTUNE_2_10GF_2_1GRF: 6649 nports = 4; 6650 break; 6651 default: 6652 switch (nxgep->platform_type) { 6653 case P_NEPTUNE_NIU: 6654 case P_NEPTUNE_ATLAS_2PORT: 6655 nports = 2; 6656 break; 6657 case P_NEPTUNE_ATLAS_4PORT: 6658 case P_NEPTUNE_MARAMBA_P0: 6659 case P_NEPTUNE_MARAMBA_P1: 6660 case P_NEPTUNE_ALONSO: 6661 nports = 4; 6662 break; 6663 default: 6664 break; 6665 } 6666 break; 6667 } 6668 6669 return (nports); 6670 } 6671 6672 /* 6673 * The following two functions are to support 6674 * PSARC/2007/453 MSI-X interrupt limit override. 6675 */ 6676 static int 6677 nxge_create_msi_property(p_nxge_t nxgep) 6678 { 6679 int nmsi; 6680 extern int ncpus; 6681 6682 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6683 6684 switch (nxgep->mac.portmode) { 6685 case PORT_10G_COPPER: 6686 case PORT_10G_FIBER: 6687 case PORT_10G_TN1010: 6688 (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6689 DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6690 /* 6691 * The maximum MSI-X requested will be 8. 6692 * If the # of CPUs is less than 8, we will reqeust 6693 * # MSI-X based on the # of CPUs. 6694 */ 6695 if (ncpus >= NXGE_MSIX_REQUEST_10G) { 6696 nmsi = NXGE_MSIX_REQUEST_10G; 6697 } else { 6698 nmsi = ncpus; 6699 } 6700 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6701 "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6702 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6703 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6704 break; 6705 6706 default: 6707 nmsi = NXGE_MSIX_REQUEST_1G; 6708 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6709 "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6710 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6711 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6712 break; 6713 } 6714 6715 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6716 return (nmsi); 6717 } 6718 6719 /* ARGSUSED */ 6720 static int 6721 nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 6722 void *pr_val) 6723 { 6724 int err = 0; 6725 link_flowctrl_t fl; 6726 6727 switch (pr_num) { 6728 case MAC_PROP_AUTONEG: 6729 *(uint8_t *)pr_val = 1; 6730 break; 6731 case MAC_PROP_FLOWCTRL: 6732 if (pr_valsize < sizeof (link_flowctrl_t)) 6733 return (EINVAL); 6734 fl = LINK_FLOWCTRL_RX; 6735 bcopy(&fl, pr_val, sizeof (fl)); 6736 break; 6737 case MAC_PROP_ADV_1000FDX_CAP: 6738 case MAC_PROP_EN_1000FDX_CAP: 6739 *(uint8_t *)pr_val = 1; 6740 break; 6741 case MAC_PROP_ADV_100FDX_CAP: 6742 case MAC_PROP_EN_100FDX_CAP: 6743 *(uint8_t *)pr_val = 1; 6744 break; 6745 default: 6746 err = ENOTSUP; 6747 break; 6748 } 6749 return (err); 6750 } 6751 6752 6753 /* 6754 * The following is a software around for the Neptune hardware's 6755 * interrupt bugs; The Neptune hardware may generate spurious interrupts when 6756 * an interrupr handler is removed. 6757 */ 6758 #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 6759 #define NXGE_PIM_RESET (1ULL << 29) 6760 #define NXGE_GLU_RESET (1ULL << 30) 6761 #define NXGE_NIU_RESET (1ULL << 31) 6762 #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 6763 NXGE_GLU_RESET | \ 6764 NXGE_NIU_RESET) 6765 6766 #define NXGE_WAIT_QUITE_TIME 200000 6767 #define NXGE_WAIT_QUITE_RETRY 40 6768 #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 6769 6770 static void 6771 nxge_niu_peu_reset(p_nxge_t nxgep) 6772 { 6773 uint32_t rvalue; 6774 p_nxge_hw_list_t hw_p; 6775 p_nxge_t fnxgep; 6776 int i, j; 6777 6778 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 6779 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 6780 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6781 "==> nxge_niu_peu_reset: NULL hardware pointer")); 6782 return; 6783 } 6784 6785 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6786 "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 6787 hw_p->flags, nxgep->nxge_link_poll_timerid, 6788 nxgep->nxge_timerid)); 6789 6790 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 6791 /* 6792 * Make sure other instances from the same hardware 6793 * stop sending PIO and in quiescent state. 6794 */ 6795 for (i = 0; i < NXGE_MAX_PORTS; i++) { 6796 fnxgep = hw_p->nxge_p[i]; 6797 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6798 "==> nxge_niu_peu_reset: checking entry %d " 6799 "nxgep $%p", i, fnxgep)); 6800 #ifdef NXGE_DEBUG 6801 if (fnxgep) { 6802 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6803 "==> nxge_niu_peu_reset: entry %d (function %d) " 6804 "link timer id %d hw timer id %d", 6805 i, fnxgep->function_num, 6806 fnxgep->nxge_link_poll_timerid, 6807 fnxgep->nxge_timerid)); 6808 } 6809 #endif 6810 if (fnxgep && fnxgep != nxgep && 6811 (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 6812 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6813 "==> nxge_niu_peu_reset: checking $%p " 6814 "(function %d) timer ids", 6815 fnxgep, fnxgep->function_num)); 6816 for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 6817 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6818 "==> nxge_niu_peu_reset: waiting")); 6819 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6820 if (!fnxgep->nxge_timerid && 6821 !fnxgep->nxge_link_poll_timerid) { 6822 break; 6823 } 6824 } 6825 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6826 if (fnxgep->nxge_timerid || 6827 fnxgep->nxge_link_poll_timerid) { 6828 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6829 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6830 "<== nxge_niu_peu_reset: cannot reset " 6831 "hardware (devices are still in use)")); 6832 return; 6833 } 6834 } 6835 } 6836 6837 if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 6838 hw_p->flags |= COMMON_RESET_NIU_PCI; 6839 rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 6840 NXGE_PCI_PORT_LOGIC_OFFSET); 6841 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6842 "nxge_niu_peu_reset: read offset 0x%x (%d) " 6843 "(data 0x%x)", 6844 NXGE_PCI_PORT_LOGIC_OFFSET, 6845 NXGE_PCI_PORT_LOGIC_OFFSET, 6846 rvalue)); 6847 6848 rvalue |= NXGE_PCI_RESET_ALL; 6849 pci_config_put32(nxgep->dev_regs->nxge_pciregh, 6850 NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 6851 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6852 "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 6853 rvalue)); 6854 6855 NXGE_DELAY(NXGE_PCI_RESET_WAIT); 6856 } 6857 6858 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6859 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 6860 } 6861 6862 static void 6863 nxge_set_pci_replay_timeout(p_nxge_t nxgep) 6864 { 6865 p_dev_regs_t dev_regs; 6866 uint32_t value; 6867 6868 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 6869 6870 if (!nxge_set_replay_timer) { 6871 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6872 "==> nxge_set_pci_replay_timeout: will not change " 6873 "the timeout")); 6874 return; 6875 } 6876 6877 dev_regs = nxgep->dev_regs; 6878 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6879 "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 6880 dev_regs, dev_regs->nxge_pciregh)); 6881 6882 if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 6883 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6884 "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 6885 "no PCI handle", 6886 dev_regs)); 6887 return; 6888 } 6889 value = (pci_config_get32(dev_regs->nxge_pciregh, 6890 PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 6891 (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 6892 6893 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6894 "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 6895 "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 6896 pci_config_get32(dev_regs->nxge_pciregh, 6897 PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 6898 PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 6899 6900 pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 6901 value); 6902 6903 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6904 "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 6905 pci_config_get32(dev_regs->nxge_pciregh, 6906 PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 6907 6908 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 6909 } 6910