1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/nxge/nxge_impl.h> 28 29 /* 30 * Tunable Receive Completion Ring Configuration B parameters. 31 */ 32 uint16_t nxge_rx_pkt_thres; /* 16 bits */ 33 uint8_t nxge_rx_pkt_timeout; /* 6 bits based on DMA clock divider */ 34 35 lb_property_t lb_normal = {normal, "normal", nxge_lb_normal}; 36 lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g}; 37 lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000}; 38 lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100}; 39 lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10}; 40 lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g}; 41 lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000}; 42 lb_property_t lb_phy = {internal, "phy", nxge_lb_phy}; 43 lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g}; 44 lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000}; 45 lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g}; 46 lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000}; 47 lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac}; 48 49 uint32_t nxge_lb_dbg = 1; 50 void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp); 51 void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp); 52 static nxge_status_t nxge_check_xaui_xfp(p_nxge_t nxgep); 53 54 extern uint32_t nxge_rx_mode; 55 extern uint32_t nxge_jumbo_mtu; 56 extern uint16_t nxge_rdc_buf_offset; 57 58 static void 59 nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 60 61 /* ARGSUSED */ 62 nxge_status_t 63 nxge_global_reset(p_nxge_t nxgep) 64 { 65 nxge_status_t status = NXGE_OK; 66 67 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset")); 68 69 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 70 return (status); 71 (void) nxge_intr_hw_disable(nxgep); 72 73 if ((nxgep->suspended) || 74 ((nxgep->statsp->port_stats.lb_mode == 75 nxge_lb_phy1000) || 76 (nxgep->statsp->port_stats.lb_mode == 77 nxge_lb_phy10g) || 78 (nxgep->statsp->port_stats.lb_mode == 79 nxge_lb_serdes1000) || 80 (nxgep->statsp->port_stats.lb_mode == 81 nxge_lb_serdes10g))) { 82 if ((status = nxge_link_init(nxgep)) != NXGE_OK) 83 return (status); 84 } 85 86 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_START)) != NXGE_OK) 87 return (status); 88 if ((status = nxge_mac_init(nxgep)) != NXGE_OK) 89 return (status); 90 (void) nxge_intr_hw_enable(nxgep); 91 92 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset")); 93 return (status); 94 } 95 96 /* ARGSUSED */ 97 void 98 nxge_hw_id_init(p_nxge_t nxgep) 99 { 100 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init")); 101 102 /* 103 * Set up initial hardware parameters required such as mac mtu size. 104 */ 105 nxgep->mac.is_jumbo = B_FALSE; 106 107 /* 108 * Set the maxframe size to 1522 (1518 + 4) to account for 109 * VLAN tagged packets. 110 */ 111 nxgep->mac.minframesize = NXGE_MIN_MAC_FRAMESIZE; /* 64 */ 112 nxgep->mac.maxframesize = NXGE_MAX_MAC_FRAMESIZE; /* 1522 */ 113 114 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init: maxframesize %d", 115 nxgep->mac.maxframesize)); 116 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init")); 117 } 118 119 /* ARGSUSED */ 120 void 121 nxge_hw_init_niu_common(p_nxge_t nxgep) 122 { 123 p_nxge_hw_list_t hw_p; 124 125 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common")); 126 127 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 128 return; 129 } 130 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 131 if (hw_p->flags & COMMON_INIT_DONE) { 132 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 133 "nxge_hw_init_niu_common" 134 " already done for dip $%p function %d exiting", 135 hw_p->parent_devp, nxgep->function_num)); 136 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 137 return; 138 } 139 140 hw_p->flags = COMMON_INIT_START; 141 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 142 " Started for device id %x with function %d", 143 hw_p->parent_devp, nxgep->function_num)); 144 145 /* per neptune common block init */ 146 (void) nxge_fflp_hw_reset(nxgep); 147 148 if (nxgep->niu_hw_type != NIU_HW_TYPE_RF) { 149 switch (nxge_rdc_buf_offset) { 150 case SW_OFFSET_NO_OFFSET: 151 case SW_OFFSET_64: 152 case SW_OFFSET_128: 153 break; 154 default: 155 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 156 "nxge_hw_init_niu_common: Unsupported RDC buffer" 157 " offset code %d, setting to %d", 158 nxge_rdc_buf_offset, SW_OFFSET_NO_OFFSET)); 159 nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET; 160 break; 161 } 162 } else { 163 switch (nxge_rdc_buf_offset) { 164 case SW_OFFSET_NO_OFFSET: 165 case SW_OFFSET_64: 166 case SW_OFFSET_128: 167 case SW_OFFSET_192: 168 case SW_OFFSET_256: 169 case SW_OFFSET_320: 170 case SW_OFFSET_384: 171 case SW_OFFSET_448: 172 break; 173 default: 174 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 175 "nxge_hw_init_niu_common: Unsupported RDC buffer" 176 " offset code %d, setting to %d", 177 nxge_rdc_buf_offset, SW_OFFSET_NO_OFFSET)); 178 nxge_rdc_buf_offset = SW_OFFSET_NO_OFFSET; 179 break; 180 } 181 } 182 183 hw_p->flags = COMMON_INIT_DONE; 184 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 185 186 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 187 " Done for device id %x with function %d", 188 hw_p->parent_devp, nxgep->function_num)); 189 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common")); 190 } 191 192 /* ARGSUSED */ 193 uint_t 194 nxge_intr(void *arg1, void *arg2) 195 { 196 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 197 p_nxge_t nxgep = (p_nxge_t)arg2; 198 uint_t serviced = DDI_INTR_UNCLAIMED; 199 uint8_t ldv; 200 npi_handle_t handle; 201 p_nxge_ldgv_t ldgvp; 202 p_nxge_ldg_t ldgp, t_ldgp; 203 p_nxge_ldv_t t_ldvp; 204 uint64_t vector0 = 0, vector1 = 0, vector2 = 0; 205 int i, j, nldvs, nintrs = 1; 206 npi_status_t rs = NPI_SUCCESS; 207 208 /* DDI interface returns second arg as NULL (n2 niumx driver) !!! */ 209 if (arg2 == NULL || (void *) ldvp->nxgep != arg2) { 210 nxgep = ldvp->nxgep; 211 } 212 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr")); 213 214 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 215 NXGE_ERROR_MSG((nxgep, INT_CTL, 216 "<== nxge_intr: not initialized 0x%x", serviced)); 217 return (serviced); 218 } 219 220 ldgvp = nxgep->ldgvp; 221 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp)); 222 if (ldvp == NULL && ldgvp) { 223 t_ldvp = ldvp = ldgvp->ldvp; 224 } 225 if (ldvp) { 226 ldgp = t_ldgp = ldvp->ldgp; 227 } 228 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 229 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 230 if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) { 231 NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: " 232 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 233 NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready")); 234 return (DDI_INTR_UNCLAIMED); 235 } 236 /* 237 * This interrupt handler will have to go through all the logical 238 * devices to find out which logical device interrupts us and then call 239 * its handler to process the events. 240 */ 241 handle = NXGE_DEV_NPI_HANDLE(nxgep); 242 t_ldgp = ldgp; 243 t_ldvp = ldgp->ldvp; 244 245 nldvs = ldgp->nldvs; 246 247 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d", 248 nldvs, ldgvp->ldg_intrs)); 249 250 serviced = DDI_INTR_CLAIMED; 251 for (i = 0; i < nintrs; i++, t_ldgp++) { 252 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d " 253 " #intrs %d", i, nldvs, nintrs)); 254 /* Get this group's flag bits. */ 255 rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg, 256 &vector0, &vector1, &vector2); 257 if (rs) { 258 continue; 259 } 260 if (!vector0 && !vector1 && !vector2) { 261 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 262 "no interrupts on group %d", t_ldgp->ldg)); 263 continue; 264 } 265 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 266 "vector0 0x%llx vector1 0x%llx vector2 0x%llx", 267 vector0, vector1, vector2)); 268 nldvs = t_ldgp->nldvs; 269 for (j = 0; j < nldvs; j++, t_ldvp++) { 270 /* 271 * Call device's handler if flag bits are on. 272 */ 273 ldv = t_ldvp->ldv; 274 if (((ldv < NXGE_MAC_LD_START) && 275 (LDV_ON(ldv, vector0) | 276 (LDV_ON(ldv, vector1)))) || 277 (ldv >= NXGE_MAC_LD_START && 278 ((LDV2_ON_1(ldv, vector2)) || 279 (LDV2_ON_2(ldv, vector2))))) { 280 (void) (t_ldvp->ldv_intr_handler)( 281 (caddr_t)t_ldvp, arg2); 282 NXGE_DEBUG_MSG((nxgep, INT_CTL, 283 "==> nxge_intr: " 284 "calling device %d #ldvs %d #intrs %d", 285 j, nldvs, nintrs)); 286 } 287 } 288 } 289 290 t_ldgp = ldgp; 291 for (i = 0; i < nintrs; i++, t_ldgp++) { 292 /* rearm group interrupts */ 293 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm " 294 "group %d", t_ldgp->ldg)); 295 (void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg, 296 t_ldgp->arm, t_ldgp->ldg_timer); 297 } 298 299 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x", 300 serviced)); 301 return (serviced); 302 } 303 304 305 /* 306 * XFP Related Status Register Values Under 3 Different Conditions 307 * 308 * -------------+-------------------------+------------------------- 309 * | Intel XFP and Avago | Picolight XFP 310 * -------------+---------+---------------+---------+--------------- 311 * | STATUS0 | TX_ALARM_STAT | STATUS0 | TX_ALARM_STAT 312 * -------------+---------+---------------+---------+--------------- 313 * No XFP | 0x639C | 0x40 | 0x639C | 0x40 314 * -------------+---------+---------------+---------+--------------- 315 * XFP,linkdown | 0x43BC | 0x40 | 0x639C | 0x40 316 * -------------+---------+---------------+---------+--------------- 317 * XFP,linkup | 0x03FC | 0x0 | 0x03FC | 0x0 318 * -------------+---------+---------------+---------+--------------- 319 * Note: 320 * STATUS0 = BCM8704_USER_ANALOG_STATUS0_REG 321 * TX_ALARM_STAT = BCM8704_USER_TX_ALARM_STATUS_REG 322 */ 323 /* ARGSUSED */ 324 static nxge_status_t 325 nxge_check_xaui_xfp(p_nxge_t nxgep) 326 { 327 nxge_status_t status = NXGE_OK; 328 uint8_t phy_port_addr; 329 uint16_t val; 330 uint16_t val1; 331 uint8_t portn; 332 333 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_check_xaui_xfp")); 334 335 portn = nxgep->mac.portnum; 336 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 337 338 /* 339 * Keep the val1 code even though it is not used. Could be 340 * used to differenciate the "No XFP" case and "XFP,linkdown" 341 * case when a Intel XFP is used. 342 */ 343 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 344 BCM8704_USER_DEV3_ADDR, 345 BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) { 346 status = nxge_mdio_read(nxgep, phy_port_addr, 347 BCM8704_USER_DEV3_ADDR, 348 BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 349 } 350 351 if (status != NXGE_OK) { 352 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 353 NXGE_FM_EREPORT_XAUI_ERR); 354 if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 355 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 356 "XAUI is bad or absent on port<%d>\n", portn)); 357 } 358 #ifdef NXGE_DEBUG 359 /* 360 * As a workaround for CR6693529, do not execute this block of 361 * code for non-debug driver. When a Picolight XFP transceiver 362 * is used, register BCM8704_USER_ANALOG_STATUS0_REG returns 363 * the same 0x639C value in normal link down case, which causes 364 * false FMA messages and link reconnection problem. 365 */ 366 } else if (nxgep->mac.portmode == PORT_10G_FIBER) { 367 /* 368 * 0x03FC = 0000 0011 1111 1100 (XFP is normal) 369 * 0x639C = 0110 0011 1001 1100 (XFP has problem) 370 * bit14 = 1: PDM loss-of-light indicator 371 * bit13 = 1: PDM Rx loss-of-signal 372 * bit6 = 0: Light is NOT ok 373 * bit5 = 0: PMD Rx signal is NOT ok 374 */ 375 if (val == 0x639C) { 376 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 377 NXGE_FM_EREPORT_XFP_ERR); 378 if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 379 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 380 "XFP is bad or absent on port<%d>\n", 381 portn)); 382 } 383 status = NXGE_ERROR; 384 } 385 #endif 386 } 387 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_check_xaui_xfp")); 388 return (status); 389 } 390 391 392 /* ARGSUSED */ 393 uint_t 394 nxge_syserr_intr(void *arg1, void *arg2) 395 { 396 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 397 p_nxge_t nxgep = (p_nxge_t)arg2; 398 p_nxge_ldg_t ldgp = NULL; 399 npi_handle_t handle; 400 sys_err_stat_t estat; 401 uint_t serviced = DDI_INTR_UNCLAIMED; 402 403 if (arg1 == NULL && arg2 == NULL) { 404 return (serviced); 405 } 406 if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) { 407 if (ldvp != NULL) { 408 nxgep = ldvp->nxgep; 409 } 410 } 411 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 412 "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp)); 413 if (ldvp != NULL && ldvp->use_timer == B_FALSE) { 414 ldgp = ldvp->ldgp; 415 if (ldgp == NULL) { 416 NXGE_ERROR_MSG((nxgep, SYSERR_CTL, 417 "<== nxge_syserrintr(no logical group): " 418 "arg2 $%p arg1 $%p", nxgep, ldvp)); 419 return (DDI_INTR_UNCLAIMED); 420 } 421 /* 422 * Get the logical device state if the function uses interrupt. 423 */ 424 } 425 426 /* This interrupt handler is for system error interrupts. */ 427 handle = NXGE_DEV_NPI_HANDLE(nxgep); 428 estat.value = 0; 429 (void) npi_fzc_sys_err_stat_get(handle, &estat); 430 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 431 "==> nxge_syserr_intr: device error 0x%016llx", estat.value)); 432 433 if (estat.bits.ldw.smx) { 434 /* SMX */ 435 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 436 "==> nxge_syserr_intr: device error - SMX")); 437 } else if (estat.bits.ldw.mac) { 438 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 439 "==> nxge_syserr_intr: device error - MAC")); 440 /* 441 * There is nothing to be done here. All MAC errors go to per 442 * MAC port interrupt. MIF interrupt is the only MAC sub-block 443 * that can generate status here. MIF status reported will be 444 * ignored here. It is checked by per port timer instead. 445 */ 446 } else if (estat.bits.ldw.ipp) { 447 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 448 "==> nxge_syserr_intr: device error - IPP")); 449 (void) nxge_ipp_handle_sys_errors(nxgep); 450 } else if (estat.bits.ldw.zcp) { 451 /* ZCP */ 452 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 453 "==> nxge_syserr_intr: device error - ZCP")); 454 (void) nxge_zcp_handle_sys_errors(nxgep); 455 } else if (estat.bits.ldw.tdmc) { 456 /* TDMC */ 457 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 458 "==> nxge_syserr_intr: device error - TDMC")); 459 /* 460 * There is no TDMC system errors defined in the PRM. All TDMC 461 * channel specific errors are reported on a per channel basis. 462 */ 463 } else if (estat.bits.ldw.rdmc) { 464 /* RDMC */ 465 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 466 "==> nxge_syserr_intr: device error - RDMC")); 467 (void) nxge_rxdma_handle_sys_errors(nxgep); 468 } else if (estat.bits.ldw.txc) { 469 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 470 "==> nxge_syserr_intr: device error - TXC")); 471 (void) nxge_txc_handle_sys_errors(nxgep); 472 } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { 473 /* PCI-E */ 474 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 475 "==> nxge_syserr_intr: device error - PCI-E")); 476 } else if (estat.bits.ldw.meta1) { 477 /* META1 */ 478 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 479 "==> nxge_syserr_intr: device error - META1")); 480 } else if (estat.bits.ldw.meta2) { 481 /* META2 */ 482 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 483 "==> nxge_syserr_intr: device error - META2")); 484 } else if (estat.bits.ldw.fflp) { 485 /* FFLP */ 486 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 487 "==> nxge_syserr_intr: device error - FFLP")); 488 (void) nxge_fflp_handle_sys_errors(nxgep); 489 } 490 491 /* 492 * nxge_check_xaui_xfg checks XAUI for all of the following 493 * portmodes, but checks XFP only if portmode == PORT_10G_FIBER. 494 */ 495 if (nxgep->mac.portmode == PORT_10G_FIBER || 496 nxgep->mac.portmode == PORT_10G_COPPER || 497 nxgep->mac.portmode == PORT_10G_TN1010 || 498 nxgep->mac.portmode == PORT_1G_TN1010) { 499 if (nxge_check_xaui_xfp(nxgep) != NXGE_OK) { 500 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 501 "==> nxge_syserr_intr: device error - XAUI")); 502 } 503 } 504 505 serviced = DDI_INTR_CLAIMED; 506 507 if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 && 508 !ldvp->use_timer) { 509 (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 510 B_TRUE, ldgp->ldg_timer); 511 } 512 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr")); 513 return (serviced); 514 } 515 516 /* ARGSUSED */ 517 void 518 nxge_intr_hw_enable(p_nxge_t nxgep) 519 { 520 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable")); 521 (void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE); 522 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable")); 523 } 524 525 /* ARGSUSED */ 526 void 527 nxge_intr_hw_disable(p_nxge_t nxgep) 528 { 529 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable")); 530 (void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE); 531 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable")); 532 } 533 534 /* ARGSUSED */ 535 void 536 nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count) 537 { 538 p_nxge_t nxgep = (p_nxge_t)arg; 539 uint8_t channel; 540 npi_handle_t handle; 541 p_nxge_ldgv_t ldgvp; 542 p_nxge_ldv_t ldvp; 543 int i; 544 545 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank")); 546 handle = NXGE_DEV_NPI_HANDLE(nxgep); 547 548 if ((ldgvp = nxgep->ldgvp) == NULL) { 549 NXGE_ERROR_MSG((nxgep, INT_CTL, 550 "<== nxge_rx_hw_blank (not enabled)")); 551 return; 552 } 553 ldvp = nxgep->ldgvp->ldvp; 554 if (ldvp == NULL) { 555 return; 556 } 557 for (i = 0; i < ldgvp->nldvs; i++, ldvp++) { 558 if (ldvp->is_rxdma) { 559 channel = ldvp->channel; 560 (void) npi_rxdma_cfg_rdc_rcr_threshold(handle, 561 channel, count); 562 (void) npi_rxdma_cfg_rdc_rcr_timeout(handle, 563 channel, ticks); 564 } 565 } 566 567 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank")); 568 } 569 570 /* ARGSUSED */ 571 void 572 nxge_hw_stop(p_nxge_t nxgep) 573 { 574 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop")); 575 576 (void) nxge_tx_mac_disable(nxgep); 577 (void) nxge_rx_mac_disable(nxgep); 578 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 579 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 580 581 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop")); 582 } 583 584 /* ARGSUSED */ 585 void 586 nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 587 { 588 int cmd; 589 590 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl")); 591 592 if (nxgep == NULL) { 593 miocnak(wq, mp, 0, EINVAL); 594 return; 595 } 596 iocp->ioc_error = 0; 597 cmd = iocp->ioc_cmd; 598 599 switch (cmd) { 600 default: 601 miocnak(wq, mp, 0, EINVAL); 602 return; 603 604 case NXGE_GET_MII: 605 nxge_get_mii(nxgep, mp->b_cont); 606 miocack(wq, mp, sizeof (uint16_t), 0); 607 break; 608 609 case NXGE_PUT_MII: 610 nxge_put_mii(nxgep, mp->b_cont); 611 miocack(wq, mp, 0, 0); 612 break; 613 614 case NXGE_GET64: 615 nxge_get64(nxgep, mp->b_cont); 616 miocack(wq, mp, sizeof (uint32_t), 0); 617 break; 618 619 case NXGE_PUT64: 620 nxge_put64(nxgep, mp->b_cont); 621 miocack(wq, mp, 0, 0); 622 break; 623 624 case NXGE_PUT_TCAM: 625 nxge_put_tcam(nxgep, mp->b_cont); 626 miocack(wq, mp, 0, 0); 627 break; 628 629 case NXGE_GET_TCAM: 630 nxge_get_tcam(nxgep, mp->b_cont); 631 miocack(wq, mp, 0, 0); 632 break; 633 634 case NXGE_TX_REGS_DUMP: 635 nxge_txdma_regs_dump_channels(nxgep); 636 miocack(wq, mp, 0, 0); 637 break; 638 case NXGE_RX_REGS_DUMP: 639 nxge_rxdma_regs_dump_channels(nxgep); 640 miocack(wq, mp, 0, 0); 641 break; 642 case NXGE_VIR_INT_REGS_DUMP: 643 case NXGE_INT_REGS_DUMP: 644 nxge_virint_regs_dump(nxgep); 645 miocack(wq, mp, 0, 0); 646 break; 647 case NXGE_RTRACE: 648 nxge_rtrace_ioctl(nxgep, wq, mp, iocp); 649 break; 650 } 651 } 652 653 /* ARGSUSED */ 654 void 655 nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 656 struct iocblk *iocp) 657 { 658 p_lb_property_t lb_props; 659 660 size_t size; 661 int i; 662 663 if (mp->b_cont == NULL) { 664 miocnak(wq, mp, 0, EINVAL); 665 } 666 switch (iocp->ioc_cmd) { 667 case LB_GET_MODE: 668 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command")); 669 if (nxgep != NULL) { 670 *(lb_info_sz_t *)mp->b_cont->b_rptr = 671 nxgep->statsp->port_stats.lb_mode; 672 miocack(wq, mp, sizeof (nxge_lb_t), 0); 673 } else { 674 miocnak(wq, mp, 0, EINVAL); 675 } 676 break; 677 case LB_SET_MODE: 678 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command")); 679 if (iocp->ioc_count != sizeof (uint32_t)) { 680 miocack(wq, mp, 0, 0); 681 break; 682 } 683 if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) { 684 miocack(wq, mp, 0, 0); 685 } else { 686 miocnak(wq, mp, 0, EPROTO); 687 } 688 break; 689 case LB_GET_INFO_SIZE: 690 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command")); 691 if (nxgep != NULL) { 692 size = sizeof (lb_normal); 693 if (nxgep->statsp->mac_stats.cap_10gfdx) { 694 /* TN1010 does not support external loopback */ 695 if (nxgep->mac.portmode != PORT_1G_TN1010 && 696 nxgep->mac.portmode != PORT_10G_TN1010) { 697 size += sizeof (lb_external10g); 698 } 699 size += sizeof (lb_mac10g); 700 /* Publish PHY loopback if PHY is present */ 701 if (nxgep->mac.portmode == PORT_10G_COPPER || 702 nxgep->mac.portmode == PORT_10G_TN1010 || 703 nxgep->mac.portmode == PORT_10G_FIBER) 704 size += sizeof (lb_phy10g); 705 } 706 707 /* 708 * Even if cap_10gfdx is false, we still do 10G 709 * serdes loopback as a part of SunVTS xnetlbtest 710 * internal loopback test. 711 */ 712 if (nxgep->mac.portmode == PORT_10G_FIBER || 713 nxgep->mac.portmode == PORT_10G_TN1010 || 714 nxgep->mac.portmode == PORT_10G_SERDES) 715 size += sizeof (lb_serdes10g); 716 717 if (nxgep->statsp->mac_stats.cap_1000fdx) { 718 /* TN1010 does not support external loopback */ 719 if (nxgep->mac.portmode != PORT_1G_TN1010 && 720 nxgep->mac.portmode != PORT_10G_TN1010) { 721 size += sizeof (lb_external1000); 722 } 723 size += sizeof (lb_mac1000); 724 if (nxgep->mac.portmode == PORT_1G_COPPER || 725 nxgep->mac.portmode == PORT_1G_TN1010 || 726 nxgep->mac.portmode == 727 PORT_1G_RGMII_FIBER) 728 size += sizeof (lb_phy1000); 729 } 730 if (nxgep->statsp->mac_stats.cap_100fdx) 731 size += sizeof (lb_external100); 732 if (nxgep->statsp->mac_stats.cap_10fdx) 733 size += sizeof (lb_external10); 734 if (nxgep->mac.portmode == PORT_1G_FIBER || 735 nxgep->mac.portmode == PORT_1G_TN1010 || 736 nxgep->mac.portmode == PORT_1G_SERDES) 737 size += sizeof (lb_serdes1000); 738 739 *(lb_info_sz_t *)mp->b_cont->b_rptr = size; 740 741 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 742 "NXGE_GET_LB_INFO command: size %d", size)); 743 miocack(wq, mp, sizeof (lb_info_sz_t), 0); 744 } else 745 miocnak(wq, mp, 0, EINVAL); 746 break; 747 748 case LB_GET_INFO: 749 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command")); 750 if (nxgep != NULL) { 751 size = sizeof (lb_normal); 752 if (nxgep->statsp->mac_stats.cap_10gfdx) { 753 /* TN1010 does not support external loopback */ 754 if (nxgep->mac.portmode != PORT_1G_TN1010 && 755 nxgep->mac.portmode != PORT_10G_TN1010) { 756 size += sizeof (lb_external10g); 757 } 758 size += sizeof (lb_mac10g); 759 /* Publish PHY loopback if PHY is present */ 760 if (nxgep->mac.portmode == PORT_10G_COPPER || 761 nxgep->mac.portmode == PORT_10G_TN1010 || 762 nxgep->mac.portmode == PORT_10G_FIBER) 763 size += sizeof (lb_phy10g); 764 } 765 if (nxgep->mac.portmode == PORT_10G_FIBER || 766 nxgep->mac.portmode == PORT_10G_TN1010 || 767 nxgep->mac.portmode == PORT_10G_SERDES) 768 size += sizeof (lb_serdes10g); 769 770 if (nxgep->statsp->mac_stats.cap_1000fdx) { 771 /* TN1010 does not support external loopback */ 772 if (nxgep->mac.portmode != PORT_1G_TN1010 && 773 nxgep->mac.portmode != PORT_10G_TN1010) { 774 size += sizeof (lb_external1000); 775 } 776 size += sizeof (lb_mac1000); 777 if (nxgep->mac.portmode == PORT_1G_COPPER || 778 nxgep->mac.portmode == PORT_1G_TN1010 || 779 nxgep->mac.portmode == 780 PORT_1G_RGMII_FIBER) 781 size += sizeof (lb_phy1000); 782 } 783 if (nxgep->statsp->mac_stats.cap_100fdx) 784 size += sizeof (lb_external100); 785 786 if (nxgep->statsp->mac_stats.cap_10fdx) 787 size += sizeof (lb_external10); 788 789 if (nxgep->mac.portmode == PORT_1G_FIBER || 790 nxgep->mac.portmode == PORT_1G_TN1010 || 791 nxgep->mac.portmode == PORT_1G_SERDES) 792 size += sizeof (lb_serdes1000); 793 794 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 795 "NXGE_GET_LB_INFO command: size %d", size)); 796 if (size == iocp->ioc_count) { 797 i = 0; 798 lb_props = (p_lb_property_t)mp->b_cont->b_rptr; 799 lb_props[i++] = lb_normal; 800 801 if (nxgep->statsp->mac_stats.cap_10gfdx) { 802 lb_props[i++] = lb_mac10g; 803 if (nxgep->mac.portmode == 804 PORT_10G_COPPER || 805 nxgep->mac.portmode == 806 PORT_10G_TN1010 || 807 nxgep->mac.portmode == 808 PORT_10G_FIBER) { 809 lb_props[i++] = lb_phy10g; 810 } 811 /* TN1010 does not support ext lb */ 812 if (nxgep->mac.portmode != 813 PORT_10G_TN1010 && 814 nxgep->mac.portmode != 815 PORT_1G_TN1010) { 816 lb_props[i++] = lb_external10g; 817 } 818 } 819 820 if (nxgep->mac.portmode == PORT_10G_FIBER || 821 nxgep->mac.portmode == PORT_10G_TN1010 || 822 nxgep->mac.portmode == PORT_10G_SERDES) 823 lb_props[i++] = lb_serdes10g; 824 825 if (nxgep->statsp->mac_stats.cap_1000fdx) { 826 /* TN1010 does not support ext lb */ 827 if (nxgep->mac.portmode != 828 PORT_10G_TN1010 && 829 nxgep->mac.portmode != 830 PORT_1G_TN1010) { 831 lb_props[i++] = lb_external1000; 832 } 833 } 834 835 if (nxgep->statsp->mac_stats.cap_100fdx) 836 lb_props[i++] = lb_external100; 837 838 if (nxgep->statsp->mac_stats.cap_10fdx) 839 lb_props[i++] = lb_external10; 840 841 if (nxgep->statsp->mac_stats.cap_1000fdx) 842 lb_props[i++] = lb_mac1000; 843 844 if (nxgep->mac.portmode == PORT_1G_COPPER || 845 nxgep->mac.portmode == PORT_1G_TN1010 || 846 nxgep->mac.portmode == 847 PORT_1G_RGMII_FIBER) { 848 if (nxgep->statsp->mac_stats. 849 cap_1000fdx) 850 lb_props[i++] = lb_phy1000; 851 } else if (nxgep->mac.portmode == 852 PORT_1G_FIBER || 853 nxgep->mac.portmode == PORT_1G_TN1010 || 854 nxgep->mac.portmode == PORT_1G_SERDES) { 855 lb_props[i++] = lb_serdes1000; 856 } 857 miocack(wq, mp, size, 0); 858 } else 859 miocnak(wq, mp, 0, EINVAL); 860 } else { 861 miocnak(wq, mp, 0, EINVAL); 862 cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x", 863 iocp->ioc_cmd); 864 } 865 break; 866 } 867 } 868 869 /* 870 * DMA channel interfaces to access various channel specific 871 * hardware functions. 872 */ 873 /* ARGSUSED */ 874 void 875 nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp, 876 uint32_t reg_base, uint16_t channel, uint64_t reg_data) 877 { 878 uint64_t reg_offset; 879 880 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 881 882 /* 883 * Channel is assumed to be from 0 to the maximum DMA channel #. If we 884 * use the virtual DMA CSR address space from the config space (in PCI 885 * case), then the following code need to be use different offset 886 * computation macro. 887 */ 888 reg_offset = reg_base + DMC_OFFSET(channel); 889 NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data); 890 891 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 892 } 893 894 /* ARGSUSED */ 895 uint64_t 896 nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp, 897 uint32_t reg_base, uint16_t channel) 898 { 899 uint64_t reg_offset; 900 901 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 902 903 /* 904 * Channel is assumed to be from 0 to the maximum DMA channel #. If we 905 * use the virtual DMA CSR address space from the config space (in PCI 906 * case), then the following code need to be use different offset 907 * computation macro. 908 */ 909 reg_offset = reg_base + DMC_OFFSET(channel); 910 911 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 912 913 return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset)); 914 } 915 916 /* ARGSUSED */ 917 void 918 nxge_get32(p_nxge_t nxgep, p_mblk_t mp) 919 { 920 nxge_os_acc_handle_t nxge_regh; 921 922 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 923 nxge_regh = nxgep->dev_regs->nxge_regh; 924 925 *(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh, 926 nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr); 927 928 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X", 929 *(uint32_t *)mp->b_rptr)); 930 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 931 } 932 933 /* ARGSUSED */ 934 void 935 nxge_put32(p_nxge_t nxgep, p_mblk_t mp) 936 { 937 nxge_os_acc_handle_t nxge_regh; 938 uint32_t *buf; 939 uint8_t *reg; 940 941 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 942 nxge_regh = nxgep->dev_regs->nxge_regh; 943 944 buf = (uint32_t *)mp->b_rptr; 945 reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0]; 946 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 947 "reg = 0x%016llX index = 0x%08X value = 0x%08X", 948 reg, buf[0], buf[1])); 949 NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]); 950 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 951 } 952 953 /*ARGSUSED*/ 954 boolean_t 955 nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp) 956 { 957 boolean_t status = B_TRUE; 958 uint32_t lb_mode; 959 lb_property_t *lb_info; 960 961 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb")); 962 lb_mode = nxgep->statsp->port_stats.lb_mode; 963 if (lb_mode == *(uint32_t *)mp->b_rptr) { 964 cmn_err(CE_NOTE, 965 "!nxge%d: Loopback mode already set (lb_mode %d).\n", 966 nxgep->instance, lb_mode); 967 status = B_FALSE; 968 goto nxge_set_lb_exit; 969 } 970 lb_mode = *(uint32_t *)mp->b_rptr; 971 lb_info = NULL; 972 if (lb_mode == lb_normal.value) 973 lb_info = &lb_normal; 974 else if ((lb_mode == lb_external10g.value) && 975 (nxgep->statsp->mac_stats.cap_10gfdx)) 976 lb_info = &lb_external10g; 977 else if ((lb_mode == lb_external1000.value) && 978 (nxgep->statsp->mac_stats.cap_1000fdx)) 979 lb_info = &lb_external1000; 980 else if ((lb_mode == lb_external100.value) && 981 (nxgep->statsp->mac_stats.cap_100fdx)) 982 lb_info = &lb_external100; 983 else if ((lb_mode == lb_external10.value) && 984 (nxgep->statsp->mac_stats.cap_10fdx)) 985 lb_info = &lb_external10; 986 else if ((lb_mode == lb_phy10g.value) && 987 (nxgep->mac.portmode == PORT_10G_COPPER || 988 nxgep->mac.portmode == PORT_10G_TN1010 || 989 nxgep->mac.portmode == PORT_10G_FIBER)) 990 lb_info = &lb_phy10g; 991 else if ((lb_mode == lb_phy1000.value) && 992 (nxgep->mac.portmode == PORT_1G_COPPER || 993 nxgep->mac.portmode == PORT_1G_TN1010 || 994 nxgep->mac.portmode == PORT_1G_RGMII_FIBER)) 995 lb_info = &lb_phy1000; 996 else if ((lb_mode == lb_phy.value) && 997 (nxgep->mac.portmode == PORT_1G_COPPER)) 998 lb_info = &lb_phy; 999 else if ((lb_mode == lb_serdes10g.value) && 1000 (nxgep->mac.portmode == PORT_10G_FIBER || 1001 nxgep->mac.portmode == PORT_10G_COPPER || 1002 nxgep->mac.portmode == PORT_10G_TN1010 || 1003 nxgep->mac.portmode == PORT_10G_SERDES)) 1004 lb_info = &lb_serdes10g; 1005 else if ((lb_mode == lb_serdes1000.value) && 1006 (nxgep->mac.portmode == PORT_1G_FIBER || 1007 nxgep->mac.portmode == PORT_1G_TN1010 || 1008 nxgep->mac.portmode == PORT_1G_SERDES)) 1009 lb_info = &lb_serdes1000; 1010 else if (lb_mode == lb_mac10g.value) 1011 lb_info = &lb_mac10g; 1012 else if (lb_mode == lb_mac1000.value) 1013 lb_info = &lb_mac1000; 1014 else if (lb_mode == lb_mac.value) 1015 lb_info = &lb_mac; 1016 else { 1017 cmn_err(CE_NOTE, 1018 "!nxge%d: Loopback mode not supported(mode %d).\n", 1019 nxgep->instance, lb_mode); 1020 status = B_FALSE; 1021 goto nxge_set_lb_exit; 1022 } 1023 1024 if (lb_mode == nxge_lb_normal) { 1025 if (nxge_lb_dbg) { 1026 cmn_err(CE_NOTE, 1027 "!nxge%d: Returning to normal operation", 1028 nxgep->instance); 1029 } 1030 if (nxge_set_lb_normal(nxgep) != NXGE_OK) { 1031 status = B_FALSE; 1032 cmn_err(CE_NOTE, 1033 "!nxge%d: Failed to return to normal operation", 1034 nxgep->instance); 1035 } 1036 goto nxge_set_lb_exit; 1037 } 1038 nxgep->statsp->port_stats.lb_mode = lb_mode; 1039 1040 if (nxge_lb_dbg) 1041 cmn_err(CE_NOTE, 1042 "!nxge%d: Adapter now in %s loopback mode", 1043 nxgep->instance, lb_info->key); 1044 nxgep->param_arr[param_autoneg].value = 0; 1045 nxgep->param_arr[param_anar_10gfdx].value = 1046 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 1047 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1048 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 1049 (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g); 1050 nxgep->param_arr[param_anar_10ghdx].value = 0; 1051 nxgep->param_arr[param_anar_1000fdx].value = 1052 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 1053 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) || 1054 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 1055 (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000); 1056 nxgep->param_arr[param_anar_1000hdx].value = 0; 1057 nxgep->param_arr[param_anar_100fdx].value = 1058 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) || 1059 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 1060 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100); 1061 nxgep->param_arr[param_anar_100hdx].value = 0; 1062 nxgep->param_arr[param_anar_10fdx].value = 1063 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 1064 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10); 1065 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) { 1066 nxgep->param_arr[param_master_cfg_enable].value = 1; 1067 nxgep->param_arr[param_master_cfg_value].value = 1; 1068 } 1069 if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 1070 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 1071 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) || 1072 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) || 1073 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 1074 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 1075 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) { 1076 1077 if (nxge_link_monitor(nxgep, LINK_MONITOR_STOP) != NXGE_OK) 1078 goto nxge_set_lb_err; 1079 if (nxge_xcvr_find(nxgep) != NXGE_OK) 1080 goto nxge_set_lb_err; 1081 if (nxge_link_init(nxgep) != NXGE_OK) 1082 goto nxge_set_lb_err; 1083 if (nxge_link_monitor(nxgep, LINK_MONITOR_START) != NXGE_OK) 1084 goto nxge_set_lb_err; 1085 } 1086 if (lb_info->lb_type == internal) { 1087 if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1088 (nxgep->statsp->port_stats.lb_mode == 1089 nxge_lb_phy10g) || 1090 (nxgep->statsp->port_stats.lb_mode == 1091 nxge_lb_serdes10g)) { 1092 nxgep->statsp->mac_stats.link_speed = 10000; 1093 } else if ((nxgep->statsp->port_stats.lb_mode 1094 == nxge_lb_mac1000) || 1095 (nxgep->statsp->port_stats.lb_mode == 1096 nxge_lb_phy1000) || 1097 (nxgep->statsp->port_stats.lb_mode == 1098 nxge_lb_serdes1000)) { 1099 nxgep->statsp->mac_stats.link_speed = 1000; 1100 } else { 1101 nxgep->statsp->mac_stats.link_speed = 100; 1102 } 1103 nxgep->statsp->mac_stats.link_duplex = 2; 1104 nxgep->statsp->mac_stats.link_up = 1; 1105 } 1106 if (nxge_global_reset(nxgep) != NXGE_OK) 1107 goto nxge_set_lb_err; 1108 1109 nxge_set_lb_exit: 1110 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1111 "<== nxge_set_lb status = 0x%08x", status)); 1112 return (status); 1113 nxge_set_lb_err: 1114 status = B_FALSE; 1115 cmn_err(CE_NOTE, 1116 "!nxge%d: Failed to put adapter in %s loopback mode", 1117 nxgep->instance, lb_info->key); 1118 return (status); 1119 } 1120 1121 /* Return to normal (no loopback) mode */ 1122 /* ARGSUSED */ 1123 nxge_status_t 1124 nxge_set_lb_normal(p_nxge_t nxgep) 1125 { 1126 nxge_status_t status = NXGE_OK; 1127 1128 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal")); 1129 1130 nxgep->statsp->port_stats.lb_mode = nxge_lb_normal; 1131 nxgep->param_arr[param_autoneg].value = 1132 nxgep->param_arr[param_autoneg].old_value; 1133 nxgep->param_arr[param_anar_1000fdx].value = 1134 nxgep->param_arr[param_anar_1000fdx].old_value; 1135 nxgep->param_arr[param_anar_1000hdx].value = 1136 nxgep->param_arr[param_anar_1000hdx].old_value; 1137 nxgep->param_arr[param_anar_100fdx].value = 1138 nxgep->param_arr[param_anar_100fdx].old_value; 1139 nxgep->param_arr[param_anar_100hdx].value = 1140 nxgep->param_arr[param_anar_100hdx].old_value; 1141 nxgep->param_arr[param_anar_10fdx].value = 1142 nxgep->param_arr[param_anar_10fdx].old_value; 1143 nxgep->param_arr[param_master_cfg_enable].value = 1144 nxgep->param_arr[param_master_cfg_enable].old_value; 1145 nxgep->param_arr[param_master_cfg_value].value = 1146 nxgep->param_arr[param_master_cfg_value].old_value; 1147 1148 if ((status = nxge_global_reset(nxgep)) != NXGE_OK) 1149 return (status); 1150 1151 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 1152 return (status); 1153 if ((status = nxge_xcvr_find(nxgep)) != NXGE_OK) 1154 return (status); 1155 if ((status = nxge_link_init(nxgep)) != NXGE_OK) 1156 return (status); 1157 status = nxge_link_monitor(nxgep, LINK_MONITOR_START); 1158 1159 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal")); 1160 1161 return (status); 1162 } 1163 1164 /* ARGSUSED */ 1165 void 1166 nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp) 1167 { 1168 uint16_t reg; 1169 1170 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii")); 1171 1172 reg = *(uint16_t *)mp->b_rptr; 1173 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg, 1174 (uint16_t *)mp->b_rptr); 1175 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X", 1176 reg, *(uint16_t *)mp->b_rptr)); 1177 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii")); 1178 } 1179 1180 /* ARGSUSED */ 1181 void 1182 nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp) 1183 { 1184 uint16_t *buf; 1185 uint8_t reg; 1186 1187 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii")); 1188 buf = (uint16_t *)mp->b_rptr; 1189 reg = (uint8_t)buf[0]; 1190 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 1191 "reg = 0x%08X index = 0x%08X value = 0x%08X", 1192 reg, buf[0], buf[1])); 1193 (void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 1194 reg, buf[1]); 1195 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii")); 1196 } 1197 1198 /* ARGSUSED */ 1199 void 1200 nxge_check_hw_state(p_nxge_t nxgep) 1201 { 1202 p_nxge_ldgv_t ldgvp; 1203 p_nxge_ldv_t t_ldvp; 1204 1205 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state")); 1206 1207 MUTEX_ENTER(nxgep->genlock); 1208 nxgep->nxge_timerid = 0; 1209 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1210 goto nxge_check_hw_state_exit; 1211 } 1212 nxge_check_tx_hang(nxgep); 1213 1214 ldgvp = nxgep->ldgvp; 1215 if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) { 1216 NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1217 "NULL ldgvp (interrupt not ready).")); 1218 goto nxge_check_hw_state_exit; 1219 } 1220 t_ldvp = ldgvp->ldvp_syserr; 1221 if (!t_ldvp->use_timer) { 1222 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1223 "ldgvp $%p t_ldvp $%p use_timer flag %d", 1224 ldgvp, t_ldvp, t_ldvp->use_timer)); 1225 goto nxge_check_hw_state_exit; 1226 } 1227 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 1228 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1229 "port%d Bad register acc handle", nxgep->mac.portnum)); 1230 } 1231 (void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep); 1232 1233 nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state, 1234 NXGE_CHECK_TIMER); 1235 1236 nxge_check_hw_state_exit: 1237 MUTEX_EXIT(nxgep->genlock); 1238 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state")); 1239 } 1240 1241 /*ARGSUSED*/ 1242 static void 1243 nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 1244 struct iocblk *iocp) 1245 { 1246 ssize_t size; 1247 rtrace_t *rtp; 1248 mblk_t *nmp; 1249 uint32_t i, j; 1250 uint32_t start_blk; 1251 uint32_t base_entry; 1252 uint32_t num_entries; 1253 1254 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl")); 1255 1256 size = 1024; 1257 if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) { 1258 NXGE_DEBUG_MSG((nxgep, STR_CTL, 1259 "malformed M_IOCTL MBLKL = %d size = %d", 1260 MBLKL(mp->b_cont), size)); 1261 miocnak(wq, mp, 0, EINVAL); 1262 return; 1263 } 1264 nmp = mp->b_cont; 1265 rtp = (rtrace_t *)nmp->b_rptr; 1266 start_blk = rtp->next_idx; 1267 num_entries = rtp->last_idx; 1268 base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES; 1269 1270 NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk)); 1271 NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries)); 1272 NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry)); 1273 1274 rtp->next_idx = npi_rtracebuf.next_idx; 1275 rtp->last_idx = npi_rtracebuf.last_idx; 1276 rtp->wrapped = npi_rtracebuf.wrapped; 1277 for (i = 0, j = base_entry; i < num_entries; i++, j++) { 1278 rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr; 1279 rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32; 1280 rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32; 1281 } 1282 1283 nmp->b_wptr = nmp->b_rptr + size; 1284 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl")); 1285 miocack(wq, mp, (int)size, 0); 1286 } 1287