1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_NGE_CHIP_H 28 #define _SYS_NGE_CHIP_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include "nge.h" 37 38 #define VENDOR_ID_NVIDIA 0x10de 39 40 #define DEVICE_ID_MCP04_37 0x37 41 #define DEVICE_ID_MCP04_38 0x38 42 #define DEVICE_ID_CK804_56 0x56 43 #define DEVICE_ID_CK804_57 0x57 44 #define DEVICE_ID_MCP51_269 0x269 45 #define DEVICE_ID_MCP51_268 0x268 46 #define DEVICE_ID_MCP55_373 0x373 47 #define DEVICE_ID_MCP55_372 0x372 48 #define DEVICE_ID_MCP61_3EE 0x3ee 49 #define DEVICE_ID_MCP61_3EF 0x3ef 50 #define DEVICE_ID_NF3_E6 0xe6 51 #define DEVICE_ID_NF3_DF 0xdf 52 53 /* Private PCI configuration register for bus config of ck804/mcp55 */ 54 #define PCI_CONF_HT_INTERNAL 0x4c 55 56 typedef union _nge_interbus_conf { 57 uint32_t conf_val; 58 struct { 59 uint32_t unit_id:5; 60 uint32_t resv5_23:19; 61 uint32_t aux_val:3; 62 uint32_t resv27:1; 63 uint32_t msi_off:1; 64 uint32_t msix_off:1; /* mcp55 only */ 65 uint32_t resv30_31:2; 66 } conf_bits; 67 } nge_interbus_conf; 68 69 /* Private PCI configuration register for MSI mask of mcp55 */ 70 #define PCI_CONF_HT_MSI_MASK 0x60 71 72 typedef union _nge_msi_mask_conf { 73 uint32_t msi_mask_conf_val; 74 struct { 75 uint32_t vec0_off:1; 76 uint32_t vec1_off:1; 77 uint32_t vec2_off:1; 78 uint32_t vec3_off:1; 79 uint32_t vec4_off:1; 80 uint32_t vec5_off:1; 81 uint32_t vec6_off:1; 82 uint32_t vec7_off:1; 83 uint32_t resv8_31:24; 84 } msi_mask_bits; 85 } nge_msi_mask_conf; 86 87 /* Private PCI configuration register for MSI map capability of mcp55 */ 88 #define PCI_CONF_HT_MSI_MAP_CAP 0x6c 89 90 typedef union _nge_msi_map_cap_conf { 91 uint32_t msi_map_cap_conf_val; 92 struct { 93 uint32_t cap_id:8; 94 uint32_t next_ptr:8; 95 uint32_t map_en:1; 96 uint32_t map_fixed:1; 97 uint32_t resv18_26:9; 98 uint32_t cap_type:5; 99 } map_cap_conf_bits; 100 } nge_msi_map_cap_conf; 101 102 /* 103 * Master interrupt 104 */ 105 #define NGE_INTR_SRC 0x000 106 #define INTR_SRC_ALL 0x00007fff 107 typedef union _nge_intr_src { 108 uint32_t intr_val; 109 struct { 110 uint32_t reint:1; 111 uint32_t rcint:1; 112 uint32_t miss:1; 113 uint32_t teint:1; 114 uint32_t tcint:1; 115 uint32_t stint:1; 116 uint32_t mint:1; 117 uint32_t rfint:1; 118 uint32_t tfint:1; 119 uint32_t feint:1; 120 uint32_t resv10:1; 121 uint32_t resv11:1; 122 uint32_t resv12:1; 123 uint32_t resv13:1; 124 uint32_t phyint:1; 125 uint32_t resv15_31:17; 126 } int_bits; 127 } nge_intr_src; 128 129 /* 130 * Master interrupt Mask 131 */ 132 #define NGE_INTR_MASK 0x004 133 #define NGE_INTR_ALL_EN 0x00007fff 134 typedef union _nge_intr_mask { 135 uint32_t mask_val; 136 struct { 137 uint32_t reint:1; 138 uint32_t rcint:1; 139 uint32_t miss:1; 140 uint32_t teint:1; 141 uint32_t tcint:1; 142 uint32_t stint:1; 143 uint32_t mint:1; 144 uint32_t rfint:1; 145 uint32_t tfint:1; 146 uint32_t feint:1; 147 uint32_t resv10:1; 148 uint32_t resv11:1; 149 uint32_t resv12:1; 150 uint32_t resv13:1; 151 uint32_t phyint:1; 152 uint32_t resv15_31:17; 153 } mask_bits; 154 } nge_intr_mask; 155 156 /* 157 * Software timer control register 158 */ 159 #define NGE_SWTR_CNTL 0x008 160 typedef union _nge_swtr_cntl { 161 uint8_t ctrl_val; 162 struct { 163 uint8_t stren:1; 164 uint8_t sten:1; 165 uint8_t resv2_7:6; 166 } cntl_bits; 167 } nge_swtr_cntl; 168 169 /* 170 * Software Timer Interval 171 */ 172 #define NGE_SWTR_ITC 0x00c 173 174 /* Default timer interval, 97 would mean 1 ms */ 175 #define SWTR_ITC 0x8 176 typedef union _nge_itc { 177 uint32_t itc_val; 178 struct { 179 uint32_t sw_intv:16; 180 uint32_t sw_cur_val:16; 181 } itc_bits; 182 } nge_itc; 183 184 /* 185 * Fatal error register 186 */ 187 #define NGE_REG010 0x010 188 typedef union _nge_reg010 { 189 uint32_t reg010_val; 190 struct { 191 uint32_t resv0:1; 192 uint32_t resv1:1; 193 uint32_t resv2:1; 194 uint32_t resv3:1; 195 uint32_t resv4:1; 196 uint32_t resv5:1; 197 uint32_t resv6:1; 198 uint32_t resv7:1; 199 uint32_t resv8:1; 200 uint32_t resv9:1; 201 uint32_t resv10:1; 202 uint32_t resv11_31:21; 203 } reg010_bits; 204 } nge_reg010; 205 206 /* 207 * MSI vector map register 0 208 */ 209 #define NGE_MSI_MAP0 0x020 210 typedef union _nge_msi_map0_vec { 211 uint32_t msi_map0_val; 212 struct { 213 uint32_t reint_vec:4; 214 uint32_t rcint_vec:4; 215 uint32_t miss_vec:4; 216 uint32_t teint_vec:4; 217 uint32_t tcint_vec:4; 218 uint32_t stint_vec:4; 219 uint32_t mint_vec:4; 220 uint32_t rfint_vec:4; 221 } vecs_bits; 222 } nge_msi_map0_vec; 223 224 /* 225 * MSI vector map register 1 226 */ 227 #define NGE_MSI_MAP1 0x024 228 typedef union _nge_msi_map1_vec { 229 uint32_t msi_map1_val; 230 struct { 231 uint32_t tfint_vec:4; 232 uint32_t feint_vec:4; 233 uint32_t resv8_11:4; 234 uint32_t resv12_15:4; 235 uint32_t resv16_19:4; 236 uint32_t resv20_23:4; 237 uint32_t resv24_31:8; 238 } vecs_bits; 239 } nge_msi_map1_vec; 240 241 242 /* 243 * MSI vector map register 2 244 */ 245 #define NGE_MSI_MAP2 0x028 246 247 /* 248 * MSI vector map register 2 249 */ 250 #define NGE_MSI_MAP3 0x02c 251 252 /* 253 * MSI mask register for mcp55 254 */ 255 #define NGE_MSI_MASK 0x30 256 typedef union _nge_msi_mask { 257 uint32_t msi_mask_val; 258 struct { 259 uint32_t vec0:1; 260 uint32_t vec1:1; 261 uint32_t vec2:1; 262 uint32_t vec3:1; 263 uint32_t vec4:1; 264 uint32_t vec5:1; 265 uint32_t vec6:1; 266 uint32_t vec7:1; 267 uint32_t resv8_31:24; 268 }msi_msk_bits; 269 }nge_msi_mask; 270 271 /* 272 * Software misc register for mcp51 273 */ 274 #define NGE_SOFT_MISC 0x034 275 typedef union _nge_soft_misc { 276 uint32_t misc_val; 277 struct { 278 uint32_t rx_clk_vx_rst:1; 279 uint32_t tx_clk_vx_rst:1; 280 uint32_t clk12m_vx_rst:1; 281 uint32_t fpci_clk_vx_rst:1; 282 uint32_t rx_clk_vc_rst:1; 283 uint32_t tx_clk_vc_rst:1; 284 uint32_t fs_clk_vc_rst:1; 285 uint32_t rst_ex_m2pintf:1; 286 uint32_t resv8_31:24; 287 } misc_bits; 288 } nge_soft_misc; 289 290 /* 291 * DMA configuration 292 */ 293 #define NGE_DMA_CFG 0x040 294 typedef union _nge_dma_cfg { 295 uint32_t cfg_val; 296 struct { 297 uint32_t tx_start_pri:3; 298 uint32_t tx_start_pri_flag:1; 299 uint32_t tx_prd_rpri:3; 300 uint32_t tx_prd_rpri_flag:1; 301 uint32_t tx_prd_wpri:3; 302 uint32_t tx_prd_wpri_flag:1; 303 uint32_t rx_start_pri:3; 304 uint32_t rx_start_pri_flag:1; 305 uint32_t rx_prd_rpri:3; 306 uint32_t rx_prd_rpri_flag:1; 307 uint32_t rx_prd_wpri:3; 308 uint32_t rx_prd_wpri_flag:1; 309 uint32_t dma_max_pri:3; 310 uint32_t dma_wrr_disable:1; 311 uint32_t dma_pri_disable:1; 312 } cfg_bits; 313 } nge_dma_cfg; 314 315 /* 316 * Request DMA configuration 317 */ 318 #define NGE_DMA_RCFG 0x044 319 typedef union _nge_dma_rcfg { 320 uint32_t dma_rcfg_val; 321 struct { 322 uint32_t tx_prd_coh_state:2; 323 uint32_t tx_data_coh_state:2; 324 uint32_t rx_prd_coh_state:2; 325 uint32_t rx_data_coh_state:2; 326 uint32_t max_roffset:5; 327 uint32_t resv13_31:19; 328 } rcfg_bis; 329 } nge_dma_rcfg; 330 331 /* 332 * Hot DMA configuration 333 */ 334 #define NGE_DMA_HOT_CFG 0x048 335 typedef union _nge_dma_hcfg { 336 uint32_t dma_hcfg_val; 337 struct { 338 uint32_t resv0_3:4; 339 uint32_t noti_wstart_pri:3; 340 uint32_t noti_wstart_pri_flag:1; 341 uint32_t cmd_rstart_pri:3; 342 uint32_t cmd_rstart_pri_flag:1; 343 uint32_t cmd_wstart_pri:3; 344 uint32_t cmd_wstart_pri_flag:1; 345 uint32_t resv16_31:16; 346 } hcfg_bits; 347 } nge_dma_hcfg; 348 349 /* 350 * PMU control register 0 for mcp51 351 */ 352 #define NGE_PMU_CNTL0 0x060 353 #define NGE_PMU_CORE_SPD10_BUSY 0x8 354 #define NGE_PMU_CORE_SPD10_IDLE 0xB 355 #define NGE_PMU_CORE_SPD100_BUSY 0x4 356 #define NGE_PMU_CORE_SPD100_IDLE 0x7 357 #define NGE_PMU_CORE_SPD1000_BUSY 0x0 358 #define NGE_PMU_CORE_SPD1000_IDLE 0x3 359 360 typedef union _nge_pmu_cntl0 { 361 uint32_t cntl0_val; 362 struct { 363 uint32_t core_spd10_fp:4; 364 uint32_t core_spd10_idle:4; 365 uint32_t core_spd100_fp:4; 366 uint32_t core_spd100_idle:4; 367 uint32_t core_spd1000_fp:4; 368 uint32_t core_spd1000_idle:4; 369 uint32_t core_sts_cur:8; 370 } cntl0_bits; 371 } nge_pmu_cntl0; 372 373 /* 374 * PMU control register 1 for mcp51 375 */ 376 #define NGE_PMU_CNTL1 0x064 377 typedef union _nge_pmu_cntl1 { 378 uint32_t cntl1_val; 379 struct { 380 uint32_t dev_fp:4; 381 uint32_t dev_idle:4; 382 uint32_t resv8_27:20; 383 uint32_t dev_sts_cur:4; 384 } cntl1_bits; 385 } nge_pmu_cntl1; 386 387 /* 388 * PMU control register 2 for mcp51 389 */ 390 #define NGE_PMU_CNTL2 0x068 391 typedef union _nge_pmu_cntl2 { 392 uint32_t cntl2_val; 393 struct { 394 uint32_t core_override:4; 395 uint32_t resv4_7:4; 396 uint32_t dev_override:4; 397 uint32_t resv12_15:4; 398 uint32_t core_override_en:1; 399 uint32_t dev_override_en:1; 400 uint32_t core_enable:1; 401 uint32_t dev_enable:1; 402 uint32_t rx_wake_dis:1; 403 uint32_t cidle_timer:1; 404 uint32_t didle_timer:1; 405 uint32_t resv23_31:9; 406 } cntl2_bits; 407 } nge_pmu_cntl2; 408 409 /* 410 * PMU core idle limit register for mcp51 411 */ 412 #define NGE_PMU_CIDLE_LIMIT 0x06c 413 #define NGE_PMU_CIDLE_LIMIT_DEF 0xffff 414 415 /* 416 * PMU device idle limit register for mcp51 417 */ 418 #define NGE_PMU_DIDLE_LIMIT 0x070 419 #define NGE_PMU_DIDLE_LIMIT_DEF 0xffff 420 421 /* 422 * PMU core idle count value register for mcp51 423 */ 424 #define NGE_PMU_CIDLE_COUNT 0x074 425 #define NGE_PMU_CIDEL_COUNT_DEF 0xffff 426 427 /* 428 * PMU device idle count value register for mcp51 429 */ 430 #define NGE_PMU_DIDLE_COUNT 0x078 431 #define NGE_PMU_DIDEL_COUNT_DEF 0xffff 432 433 /* 434 * Transmit control 435 */ 436 #define NGE_TX_CNTL 0x080 437 typedef union _nge_tx_cntl { 438 uint32_t cntl_val; 439 struct { 440 uint32_t paen:1; /* only for mcp55, otherwise reserve */ 441 uint32_t resv1:1; 442 uint32_t retry_en:1; 443 uint32_t pad_en:1; 444 uint32_t fappend_en:1; 445 uint32_t two_def_en:1; 446 uint32_t resv6_7:2; 447 uint32_t max_retry:4; 448 uint32_t burst_en:1; 449 uint32_t resv13_15:3; 450 uint32_t retry_emask:1; 451 uint32_t exdef_mask:1; 452 uint32_t def_mask:1; 453 uint32_t lcar_mask:1; 454 uint32_t tlcol_mask:1; 455 uint32_t uflo_err_mask:1; 456 uint32_t resv22_23:2; 457 uint32_t jam_seq_en:1; 458 uint32_t resv25_31:7; 459 } cntl_bits; 460 } nge_tx_cntl; 461 462 /* 463 * Transmit enable 464 * Note: for ck804 or mcp51, this is 8-bit register; 465 * for mcp55, it is a 32-bit register. 466 */ 467 #define NGE_TX_EN 0x084 468 typedef union _nge_tx_en { 469 uint8_t val; 470 struct { 471 uint8_t tx_en:1; 472 uint8_t resv1_7:7; 473 } bits; 474 } nge_tx_en; 475 476 /* 477 * Transmit status 478 */ 479 #define NGE_TX_STA 0x088 480 typedef union _nge_tx_sta { 481 uint32_t sta_val; 482 struct { 483 uint32_t tx_chan_sta:1; 484 uint32_t resv1_15:15; 485 uint32_t retry_err:1; 486 uint32_t exdef:1; 487 uint32_t def:1; 488 uint32_t lcar:1; 489 uint32_t tlcol:1; 490 uint32_t uflo:1; 491 uint32_t resv22_31:10; 492 } sta_bits; 493 } nge_tx_sta; 494 495 /* 496 * Receive control 497 */ 498 #define NGE_RX_CNTL0 0x08c 499 typedef union _nge_rx_cntrl0 { 500 uint32_t cntl_val; 501 struct { 502 uint32_t resv0:1; 503 uint32_t padsen:1; 504 uint32_t fcsren:1; 505 uint32_t paen:1; 506 uint32_t lben:1; 507 uint32_t afen:1; 508 uint32_t runten:1; 509 uint32_t brdis:1; 510 uint32_t rdfen:1; 511 uint32_t slfb:1; 512 uint32_t resv10_15:6; 513 uint32_t runtm:1; 514 uint32_t rlcolm:1; 515 uint32_t maxerm:1; 516 uint32_t lferm:1; 517 uint32_t crcm:1; 518 uint32_t ofolm:1; 519 uint32_t framerm:1; 520 uint32_t resv23_31:9; 521 } cntl_bits; 522 } nge_rx_cntrl0; 523 524 /* 525 * Maximum receive Frame size 526 */ 527 #define NGE_RX_CNTL1 0x090 528 typedef union _nge_rx_cntl1 { 529 uint32_t cntl_val; 530 struct { 531 uint32_t length:14; 532 uint32_t resv14_31:18; 533 } cntl_bits; 534 } nge_rx_cntl1; 535 536 /* 537 * Receive enable register 538 * Note: for ck804 and mcp51, this is a 8-bit register; 539 * for mcp55, it is a 32-bit register. 540 */ 541 #define NGE_RX_EN 0x094 542 typedef union _nge_rx_en { 543 uint8_t val; 544 struct { 545 uint8_t rx_en:1; 546 uint8_t resv1_7:7; 547 } bits; 548 } nge_rx_en; 549 550 /* 551 * Receive status register 552 */ 553 #define NGE_RX_STA 0x098 554 typedef union _nge_rx_sta { 555 uint32_t sta_val; 556 struct { 557 uint32_t rx_chan_sta:1; 558 uint32_t resv1_15:15; 559 uint32_t runt_sta:1; 560 uint32_t rlcol_sta:1; 561 uint32_t mlen_err:1; 562 uint32_t lf_err:1; 563 uint32_t crc_err:1; 564 uint32_t ofol_err:1; 565 uint32_t fram_err:1; 566 uint32_t resv23_31:9; 567 } sta_bits; 568 } nge_rx_sta; 569 570 /* 571 * Backoff Control 572 */ 573 #define NGE_BKOFF_CNTL 0x09c 574 #define BKOFF_RSEED 0x8 575 #define BKOFF_SLIM_GMII 0x3ff 576 #define BKOFF_SLIM_MII 0x7f 577 typedef union _nge_bkoff_cntl { 578 uint32_t cntl_val; 579 struct { 580 uint32_t rseed:8; 581 uint32_t sltm:10; 582 uint32_t resv18_30:13; 583 uint32_t leg_bk_en:1; 584 } bkoff_bits; 585 } nge_bkoff_cntl; 586 587 /* 588 * Transmit defferral timing 589 */ 590 #define NGE_TX_DEF 0x0a0 591 #define TX_TIFG_MII 0x15 592 #define TX_IFG_RGMII_1000_FD 0x14 593 #define TX_IFG_RGMII_OTHER 0x16 594 #define TX_IFG2_MII 0x5 595 #define TX_IFG2_RGMII_10_100 0x7 596 #define TX_IFG2_RGMII_1000 0x5 597 #define TX_IFG2_DEFAULT 0X0 598 #define TX_IFG1_DEFAULT 0xf 599 typedef union _nge_tx_def { 600 uint32_t def_val; 601 struct { 602 uint32_t ifg1_def:8; 603 uint32_t ifg2_def:8; 604 uint32_t if_def:8; 605 uint32_t resv24_31:8; 606 } def_bits; 607 } nge_tx_def; 608 609 /* 610 * Receive defferral timing 611 */ 612 #define NGE_RX_DEf 0x0a4 613 #define RX_DEF_DEFAULT 0x16 614 typedef union _nge_rx_def { 615 uint8_t def_val; 616 struct { 617 uint8_t rifg; 618 } def_bits; 619 } nge_rx_def; 620 621 /* 622 * Low 32 bit unicast address 623 */ 624 #define NGE_UNI_ADDR0 0x0a8 625 union { 626 uint32_t addr_val; 627 struct { 628 uint32_t addr; 629 } addr_bits; 630 } nge_uni_addr0; 631 632 /* 633 * High 32 bit unicast address 634 */ 635 #define NGE_UNI_ADDR1 0x0ac 636 typedef union _nge_uni_addr1 { 637 uint32_t addr_val; 638 struct { 639 uint32_t addr:16; 640 uint32_t resv16_31:16; 641 } addr_bits; 642 } nge_uni_addr1; 643 644 /* 645 * Low 32 bit multicast address 646 */ 647 #define NGE_MUL_ADDR0 0x0b0 648 union { 649 uint32_t addr_val; 650 struct { 651 uint32_t addr; 652 }addr_bits; 653 }nge_mul_addr0; 654 655 /* 656 * High 32 bit multicast address 657 */ 658 #define NGE_MUL_ADDR1 0x0b4 659 typedef union _nge_mul_addr1 { 660 uint32_t addr_val; 661 struct { 662 uint32_t addr:16; 663 uint32_t resv16_31:16; 664 }addr_bits; 665 }nge_mul_addr1; 666 667 /* 668 * Low 32 bit multicast mask 669 */ 670 #define NGE_MUL_MASK 0x0b8 671 union { 672 uint32_t mask_val; 673 struct { 674 uint32_t mask; 675 } mask_bits; 676 } nge_mul_mask0; 677 678 /* 679 * High 32 bit multicast mask 680 */ 681 #define NGE_MUL_MASK1 0x0bc 682 union { 683 uint32_t mask_val; 684 struct { 685 uint32_t mask:16; 686 uint32_t resv16_31:16; 687 } mask_bits; 688 } nge_mul_mask1; 689 690 /* 691 * Mac-to Phy Interface 692 */ 693 #define NGE_MAC2PHY 0x0c0 694 #define low_speed 0x0 695 #define fast_speed 0x1 696 #define giga_speed 0x2 697 #define err_speed 0x4 698 #define MII_IN 0x0 699 #define RGMII_IN 0x1 700 #define ERR_IN1 0x3 701 #define ERR_IN2 0x4 702 typedef union _nge_mac2phy { 703 uint32_t m2p_val; 704 struct { 705 uint32_t speed:2; 706 uint32_t resv2_7:6; 707 uint32_t hdup_en:1; 708 uint32_t resv9:1; 709 uint32_t phyintr:1; /* for mcp55 only */ 710 uint32_t phyintrlvl:1; /* for mcp55 only */ 711 uint32_t resv12_27:16; 712 uint32_t in_type:2; 713 uint32_t resv30_31:2; 714 } m2p_bits; 715 } nge_mac2phy; 716 717 /* 718 * Transmit Descriptor Ring address 719 */ 720 #define NGE_TX_DADR 0x100 721 typedef union _nge_tx_addr { 722 uint32_t addr_val; 723 struct { 724 uint32_t resv0_2:3; 725 uint32_t addr:29; 726 } addr_bits; 727 } nge_tx_addr; 728 729 /* 730 * Receive Descriptor Ring address 731 */ 732 #define NGE_RX_DADR 0x104 733 typedef union _nge_rx_addr { 734 uint32_t addr_val; 735 struct { 736 uint32_t resv0_2:3; 737 uint32_t addr:29; 738 } addr_bits; 739 } nge_rx_addr; 740 741 /* 742 * Rx/tx descriptor ring leng 743 * Note: for mcp55, tdlen/rdlen are 14 bit. 744 */ 745 #define NGE_RXTX_DLEN 0x108 746 typedef union _nge_rxtx_dlen { 747 uint32_t dlen_val; 748 struct { 749 uint32_t tdlen:14; 750 uint32_t resv14_15:2; 751 uint32_t rdlen:14; 752 uint32_t resv30_31:2; 753 } dlen_bits; 754 } nge_rxtx_dlen; 755 756 /* 757 * Transmit polling register 758 */ 759 #define NGE_TX_POLL 0x10c 760 #define TX_POLL_INTV_1G 10 761 #define TX_POLL_INTV_100M 100 762 #define TX_POLL_INTV_10M 1000 763 764 typedef union _nge_tx_poll { 765 uint32_t poll_val; 766 struct { 767 uint32_t tpi:16; 768 uint32_t tpen:1; 769 uint32_t resv17_31:15; 770 } poll_bits; 771 } nge_tx_poll; 772 773 /* 774 * Receive polling register 775 */ 776 #define NGE_RX_POLL 0x110 777 #define RX_POLL_INTV_1G 10 778 #define RX_POLL_INTV_100M 100 779 #define RX_POLL_INTV_10M 1000 780 typedef union _nge_rx_poll { 781 uint32_t poll_val; 782 struct { 783 uint32_t rpi:16; 784 uint32_t rpen:1; 785 uint32_t resv17_31:15; 786 } poll_bits; 787 } nge_rx_poll; 788 789 /* 790 * Transmit polling count 791 */ 792 #define NGE_TX_PCNT 0x114 793 union { 794 uint32_t cnt_val; 795 struct { 796 uint32_t pcnt:32; 797 } cnt_bits; 798 } nge_tx_pcnt; 799 800 /* 801 * Receive polling count 802 */ 803 #define NGE_RX_PCNT 0x118 804 union { 805 uint32_t cnt_val; 806 struct { 807 uint32_t pcnt:32; 808 } cnt_bits; 809 } nge_rx_pcnt; 810 811 812 /* 813 * Current tx's descriptor address 814 */ 815 #define NGE_TX_CUR_DADR 0x11c 816 union { 817 uint32_t addr_val; 818 struct { 819 uint32_t resv0_2:3; 820 uint32_t addr:29; 821 } addr_bits; 822 } nge_tx_cur_addr; 823 824 /* 825 * Current rx's descriptor address 826 */ 827 #define NGE_RX_CUR_DADR 0x120 828 union { 829 uint32_t addr_val; 830 struct { 831 uint32_t resv0_2:3; 832 uint32_t addr:29; 833 } addr_bits; 834 } nge_rx_cur_addr; 835 836 /* 837 * Current tx's data buffer address 838 */ 839 #define NGE_TX_CUR_PRD0 0x124 840 union { 841 uint32_t prd0_val; 842 struct { 843 uint32_t prd0:32; 844 } prd0_bits; 845 } nge_tx_cur_prd0; 846 847 /* 848 * Current tx's data buffer status 849 */ 850 #define NGE_TX_CUR_PRD1 0x128 851 union { 852 uint32_t prd1_val; 853 struct { 854 uint32_t rebytes:16; 855 uint32_t status:16; 856 } prd1_bits; 857 } nge_tx_cur_prd1; 858 859 /* 860 * Current rx's data buffer address 861 */ 862 #define NGE_RX_CUR_PRD0 0x12c 863 union { 864 uint32_t prd0_val; 865 struct { 866 uint32_t prd0:32; 867 }prd0_bits; 868 }nge_rx_cur_prd0; 869 870 /* 871 * Current rx's data buffer status 872 */ 873 #define NGE_RX_CUR_PRD1 0x130 874 875 /* 876 * Next tx's descriptor address 877 */ 878 #define NGE_TX_NXT_DADR 0x134 879 union { 880 uint32_t dadr_val; 881 struct { 882 uint32_t addr:32; 883 }addr_bits; 884 }nge_tx_nxt_dadr; 885 886 /* 887 * Next rx's descriptor address 888 */ 889 #define NGE_RX_NXT_DADR 0x138 890 union { 891 uint32_t dadr_val; 892 struct { 893 uint32_t addr:32; 894 } addr_bits; 895 } nge_rx_nxt_dadr; 896 897 /* 898 * Transmit fifo watermark 899 */ 900 #define NGE_TX_FIFO_WM 0x13c 901 #define TX_FIFO_TBFW 0 902 #define TX_FIFO_NOB_WM_MII 1 903 #define TX_FIFO_NOB_WM_GMII 8 904 #define TX_FIFO_DATA_LWM 0x20 905 #define TX_FIFO_PRD_LWM 0x8 906 #define TX_FIFO_PRD_HWM 0x38 907 typedef union _nge_tx_fifo_wm { 908 uint32_t wm_val; 909 struct { 910 uint32_t data_lwm:9; 911 uint32_t resv8_11:3; 912 uint32_t prd_lwm:6; 913 uint32_t uprd_hwm:6; 914 uint32_t nbfb_wm:4; 915 uint32_t fb_wm:4; 916 } wm_bits; 917 } nge_tx_fifo_wm; 918 919 /* 920 * Receive fifo watermark 921 */ 922 #define NGE_RX_FIFO_WM 0x140 923 typedef union _nge_rx_fifo_wm { 924 uint32_t wm_val; 925 struct { 926 uint32_t data_hwm:9; 927 uint32_t resv9_11:3; 928 uint32_t prd_lwm:4; 929 uint32_t resv16_17:2; 930 uint32_t prd_hwm:4; 931 uint32_t resv22_31:10; 932 } wm_bits; 933 } nge_rx_fifo_wm; 934 935 /* 936 * Chip mode control 937 */ 938 #define NGE_MODE_CNTL 0x144 939 #define DESC_MCP1 0x0 940 #define DESC_OFFLOAD 0x1 941 #define DESC_HOT 0x2 942 #define DESC_RESV 0x3 943 #define MACHINE_BUSY 0x0 944 #define MACHINE_IDLE 0x1 945 typedef union _nge_mode_cntl { 946 uint32_t mode_val; 947 struct { 948 uint32_t txdm:1; 949 uint32_t rxdm:1; 950 uint32_t dma_dis:1; 951 uint32_t dma_status:1; 952 uint32_t bm_reset:1; 953 uint32_t resv5:1; 954 uint32_t vlan_strip:1; /* mcp55 chip only */ 955 uint32_t vlan_ins:1; /* mcp55 chip only */ 956 uint32_t desc_type:2; 957 uint32_t rx_sum_en:1; 958 uint32_t tx_prd_cu_en:1; 959 uint32_t w64_dis:1; 960 uint32_t tx_rcom_en:1; 961 uint32_t rx_filter_en:1; 962 uint32_t resv15:1; 963 uint32_t resv16:1; /* ck804 and mcp51 only */ 964 uint32_t resv17:1; /* ck804 and mcp51 only */ 965 uint32_t resv18:1; /* ck804 and mcp51 only */ 966 uint32_t resv19_21:3; 967 uint32_t tx_fetch_prd:1; /* mcp51/mcp55 only */ 968 uint32_t rx_fetch_prd:1; /* mcp51/mcp55 only */ 969 uint32_t resv24_29:6; 970 uint32_t rx_status:1; 971 uint32_t tx_status:1; 972 } mode_bits; 973 } nge_mode_cntl; 974 975 #define NGE_TX_DADR_HI 0x148 976 #define NGE_RX_DADR_HI 0x14c 977 978 /* 979 * Mii interrupt register 980 * Note: for mcp55, this is a 32-bit register. 981 */ 982 #define NGE_MINTR_SRC 0x180 983 typedef union _nge_mintr_src { 984 uint8_t src_val; 985 struct { 986 uint8_t mrei:1; 987 uint8_t mcc2:1; 988 uint8_t mcc1:1; 989 uint8_t mapi:1; 990 uint8_t mpdi:1; 991 uint8_t resv5_7:3; 992 } src_bits; 993 } nge_mintr_src; 994 995 /* 996 * Mii interrupt mask 997 * Note: for mcp55, this is a 32-bit register. 998 */ 999 #define NGE_MINTR_MASK 0x184 1000 typedef union _nge_mintr_mask { 1001 uint8_t mask_val; 1002 struct { 1003 uint8_t mrei:1; 1004 uint8_t mcc2:1; 1005 uint8_t mcc1:1; 1006 uint8_t mapi:1; 1007 uint8_t mpdi:1; 1008 uint8_t resv5_7:3; 1009 } mask_bits; 1010 } nge_mintr_mask; 1011 1012 /* 1013 * Mii control and status 1014 */ 1015 #define NGE_MII_CS 0x188 1016 #define MII_POLL_INTV 0x4 1017 typedef union _nge_mii_cs { 1018 uint32_t cs_val; 1019 struct { 1020 uint32_t excap:1; 1021 uint32_t jab_dec:1; 1022 uint32_t lk_up:1; 1023 uint32_t ana_cap:1; 1024 uint32_t rfault:1; 1025 uint32_t auto_neg:1; 1026 uint32_t mfps:1; 1027 uint32_t resv7:1; 1028 uint32_t exst:1; 1029 uint32_t hdup_100m_t2:1; 1030 uint32_t fdup_100m_t2:1; 1031 uint32_t hdup_10m:1; 1032 uint32_t fdup_10m:1; 1033 uint32_t hdup_100m_x:1; 1034 uint32_t fdup_100m_x:1; 1035 uint32_t cap_100m_t4:1; 1036 uint32_t ap_intv:4; 1037 uint32_t ap_en:1; 1038 uint32_t resv21_23:3; 1039 uint32_t ap_paddr:5; 1040 uint32_t resv29_31:3; 1041 } cs_bits; 1042 } nge_mii_cs; 1043 1044 /* 1045 * Mii Clock timer register 1046 */ 1047 #define NGE_MII_TM 0x18c 1048 typedef union _nge_mii_tm { 1049 uint16_t tm_val; 1050 struct { 1051 uint16_t timer_interv:8; 1052 uint16_t timer_en:1; 1053 uint16_t resv9_14:6; 1054 uint16_t timer_status:1; 1055 } tm_bits; 1056 } nge_mii_tm; 1057 1058 /* 1059 * Mdio address 1060 */ 1061 #define NGE_MDIO_ADR 0x190 1062 typedef union _nge_mdio_adr { 1063 uint16_t adr_val; 1064 struct { 1065 uint16_t phy_reg:5; 1066 uint16_t phy_adr:5; 1067 uint16_t mdio_rw:1; 1068 uint16_t resv11_14:4; 1069 uint16_t mdio_clc:1; 1070 } adr_bits; 1071 } nge_mdio_adr; 1072 1073 /* 1074 * Mdio data 1075 */ 1076 #define NGE_MDIO_DATA 0x194 1077 1078 /* 1079 * Power Management and Control 1080 */ 1081 #define NGE_PM_CNTL 0x200 1082 typedef union _nge_pm_cntl { 1083 uint32_t cntl_val; 1084 struct { 1085 /* 1086 * mp_en: Magic Packet Enable 1087 * pm_en: Pattern Match Enable 1088 * lc_en: Link Change Enable 1089 */ 1090 uint32_t mp_en_d0:1; 1091 uint32_t pm_en_d0:1; 1092 uint32_t lc_en_d0:1; 1093 uint32_t resv3:1; 1094 uint32_t mp_en_d1:1; 1095 uint32_t pm_en_d1:1; 1096 uint32_t lc_en_d1:1; 1097 uint32_t resv7:1; 1098 uint32_t mp_en_d2:1; 1099 uint32_t pm_en_d2:1; 1100 uint32_t lc_en_d2:1; 1101 uint32_t resv11:1; 1102 uint32_t mp_en_d3:1; 1103 uint32_t pm_en_d3:1; 1104 uint32_t lc_en_d3:1; 1105 uint32_t resv15:1; 1106 uint32_t pat_match_en:5; 1107 uint32_t resv21_23:3; 1108 uint32_t pat_match_stat:5; 1109 uint32_t magic_status:1; 1110 uint32_t netman_status:1; 1111 uint32_t resv31:1; 1112 } cntl_bits; 1113 } nge_pm_cntl; 1114 1115 #define NGE_MPT_CRC0 0x204 1116 #define NGE_PMC_MK00 0x208 1117 #define NGE_PMC_MK01 0x20C 1118 #define NGE_PMC_MK02 0x210 1119 #define NGE_PMC_MK03 0x214 1120 #define NGE_MPT_CRC1 0x218 1121 #define NGE_PMC_MK10 0x21c 1122 #define NGE_PMC_MK11 0x220 1123 #define NGE_PMC_MK12 0x224 1124 #define NGE_PMC_MK13 0x228 1125 #define NGE_MPT_CRC2 0x22c 1126 #define NGE_PMC_MK20 0x230 1127 #define NGE_PMC_MK21 0x234 1128 #define NGE_PMC_MK22 0x238 1129 #define NGE_PMC_MK23 0x23c 1130 #define NGE_MPT_CRC3 0x240 1131 #define NGE_PMC_MK30 0x244 1132 #define NGE_PMC_MK31 0x248 1133 #define NGE_PMC_MK32 0x24c 1134 #define NGE_PMC_MK33 0x250 1135 #define NGE_MPT_CRC4 0x254 1136 #define NGE_PMC_MK40 0x258 1137 #define NGE_PMC_MK41 0x25c 1138 #define NGE_PMC_MK42 0x260 1139 #define NGE_PMC_MK43 0x264 1140 #define NGE_PMC_ALIAS 0x268 1141 #define NGE_PMCSR_ALIAS 0x26c 1142 1143 /* 1144 * Seeprom control 1145 */ 1146 #define NGE_EP_CNTL 0x500 1147 #define EEPROM_CLKDIV 249 1148 #define EEPROM_WAITCLK 0x7 1149 typedef union _nge_cp_cntl { 1150 uint32_t cntl_val; 1151 struct { 1152 uint32_t clkdiv:8; 1153 uint32_t rom_size:3; 1154 uint32_t resv11:1; 1155 uint32_t word_wid:1; 1156 uint32_t resv13_15:3; 1157 uint32_t wait_slots:4; 1158 uint32_t resv20_31:12; 1159 } cntl_bits; 1160 } nge_cp_cntl; 1161 1162 /* 1163 * Seeprom cmd control 1164 */ 1165 #define NGE_EP_CMD 0x504 1166 #define SEEPROM_CMD_READ 0x0 1167 #define SEEPROM_CMD_WRITE_ENABLE 0x1 1168 #define SEEPROM_CMD_ERASE 0x2 1169 #define SEEPROM_CMD_WRITE 0x3 1170 #define SEEPROM_CMD_ERALSE_ALL 0x4 1171 #define SEEPROM_CMD_WRITE_ALL 0x5 1172 #define SEEPROM_CMD_WRITE_DIS 0x6 1173 #define SEEPROM_READY 0x1 1174 typedef union _nge_ep_cmd { 1175 uint32_t cmd_val; 1176 struct { 1177 uint32_t addr:16; 1178 uint32_t cmd:3; 1179 uint32_t resv19_30:12; 1180 uint32_t sts:1; 1181 } cmd_bits; 1182 } nge_ep_cmd; 1183 1184 /* 1185 * Seeprom data register 1186 */ 1187 #define NGE_EP_DATA 0x508 1188 typedef union _nge_ep_data { 1189 uint32_t data_val; 1190 struct { 1191 uint32_t data:16; 1192 uint32_t resv16_31:16; 1193 } data_bits; 1194 } nge_ep_data; 1195 1196 /* 1197 * Power management control 2nd register (since MCP51) 1198 */ 1199 #define NGE_PM_CNTL2 0x600 1200 typedef union _nge_pm_cntl2 { 1201 uint32_t cntl_val; 1202 struct { 1203 uint32_t phy_coma_set:1; 1204 uint32_t phy_coma_status:1; 1205 uint32_t resv2_3:2; 1206 uint32_t resv4:1; 1207 uint32_t resv5_7:3; 1208 uint32_t resv8_11:4; 1209 uint32_t resv12_15:4; 1210 uint32_t pmt5_en:1; 1211 uint32_t pmt6_en:1; 1212 uint32_t pmt7_en:1; 1213 uint32_t resv19_23:5; 1214 uint32_t pmt5_status:1; 1215 uint32_t pmt6_status:1; 1216 uint32_t pmt7_status:1; 1217 uint32_t resv27_31:5; 1218 } cntl_bits; 1219 } nge_pm_cntl2; 1220 1221 1222 /* 1223 * ASF RAM 0x800-0xfff 1224 */ 1225 1226 /* 1227 * Hardware-defined Statistics Block Offsets 1228 * 1229 * These are given in the manual as addresses in NIC memory, starting 1230 * from the NIC statistics area base address of 0x2000; 1231 */ 1232 1233 #define KS_BASE 0x0280 1234 #define KS_ADDR(x) (((x)-KS_BASE)/sizeof (uint32_t)) 1235 1236 typedef enum { 1237 KS_ifHOutOctets = KS_ADDR(0x0280), 1238 KS_ifHOutZeroRetranCount, 1239 KS_ifHOutOneRetranCount, 1240 KS_ifHOutMoreRetranCount, 1241 KS_ifHOutColCount, 1242 KS_ifHOutFifoovCount, 1243 KS_ifHOutLOCCount, 1244 KS_ifHOutExDecCount, 1245 KS_ifHOutRetryCount, 1246 1247 KS_ifHInFrameErrCount, 1248 KS_ifHInExtraOctErrCount, 1249 KS_ifHInLColErrCount, 1250 KS_ifHInRuntCount, 1251 KS_ifHInOversizeErrCount, 1252 KS_ifHInFovErrCount, 1253 KS_ifHInFCSErrCount, 1254 KS_ifHInAlignErrCount, 1255 KS_ifHInLenErrCount, 1256 KS_ifHInUniPktsCount, 1257 KS_ifHInBroadPksCount, 1258 KS_ifHInMulPksCount, 1259 KS_STATS_SIZE = KS_ADDR(0x2d0) 1260 1261 } nge_stats_offset_t; 1262 1263 /* 1264 * Hardware-defined Statistics Block 1265 * 1266 * Another view of the statistic block, as a array and a structure ... 1267 */ 1268 1269 typedef union { 1270 uint64_t a[KS_STATS_SIZE]; 1271 struct { 1272 uint64_t OutOctets; 1273 uint64_t OutZeroRetranCount; 1274 uint64_t OutOneRetranCount; 1275 uint64_t OutMoreRetranCount; 1276 uint64_t OutColCount; 1277 uint64_t OutFifoovCount; 1278 uint64_t OutLOCCount; 1279 uint64_t OutExDecCount; 1280 uint64_t OutRetryCount; 1281 1282 uint64_t InFrameErrCount; 1283 uint64_t InExtraOctErrCount; 1284 uint64_t InLColErrCount; 1285 uint64_t InRuntCount; 1286 uint64_t InOversizeErrCount; 1287 uint64_t InFovErrCount; 1288 uint64_t InFCSErrCount; 1289 uint64_t InAlignErrCount; 1290 uint64_t InLenErrCount; 1291 uint64_t InUniPktsCount; 1292 uint64_t InBroadPksCount; 1293 uint64_t InMulPksCount; 1294 } s; 1295 } nge_hw_statistics_t; 1296 1297 /* 1298 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 1299 */ 1300 1301 #define NGE_PHY_NUMBER 32 1302 #define MII_LP_ASYM_PAUSE 0x0800 1303 #define MII_LP_PAUSE 0x0400 1304 1305 #define MII_100BASE_T4 0x0200 1306 #define MII_100BASET_FD 0x0100 1307 #define MII_100BASET_HD 0x0080 1308 #define MII_10BASET_FD 0x0040 1309 #define MII_10BASET_HD 0x0020 1310 1311 #define MII_ID_MARVELL 0x5043 1312 #define MII_ID_CICADA 0x03f1 1313 #define MII_IDL_MASK 0xfc00 1314 #define MII_AN_LPNXTPG 8 1315 1316 1317 #define MII_IEEE_EXT_STATUS 15 1318 1319 /* 1320 * New bits in the MII_CONTROL register 1321 */ 1322 #define MII_CONTROL_1000MB 0x0040 1323 1324 /* 1325 * New bits in the MII_AN_ADVERT register 1326 */ 1327 #define MII_ABILITY_ASYM_PAUSE 0x0800 1328 #define MII_ABILITY_PAUSE 0x0400 1329 1330 /* 1331 * Values for the <selector> field of the MII_AN_ADVERT register 1332 */ 1333 #define MII_AN_SELECTOR_8023 0x0001 1334 1335 /* 1336 * Bits in the MII_1000BASE_T_CONTROL register 1337 * 1338 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 1339 * (otherwise, roles are automatically negotiated). When this bit is set, 1340 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 1341 */ 1342 #define MII_1000BASE_T_CONTROL 9 1343 #define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 1344 #define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 1345 #define MII_1000BT_CTL_ADV_FDX 0x0200 1346 #define MII_1000BT_CTL_ADV_HDX 0x0100 1347 1348 /* 1349 * Bits in the MII_1000BASE_T_STATUS register 1350 */ 1351 #define MII_1000BASE_T_STATUS 10 1352 #define MII_1000BT_STAT_MASTER_FAULT 0x8000 1353 #define MII_1000BT_STAT_MASTER_MODE 0x4000 1354 #define MII_1000BT_STAT_LCL_RCV_OK 0x2000 1355 #define MII_1000BT_STAT_RMT_RCV_OK 0x1000 1356 #define MII_1000BT_STAT_LP_FDX_CAP 0x0800 1357 #define MII_1000BT_STAT_LP_HDX_CAP 0x0400 1358 1359 #define MII_CICADA_BYPASS_CONTROL MII_VENDOR(2) 1360 #define CICADA_125MHZ_CLOCK_ENABLE 0x0001 1361 1362 #define MII_CICADA_10BASET_CONTROL MII_VENDOR(6) 1363 #define MII_CICADA_DISABLE_ECHO_MODE 0x2000 1364 1365 #define MII_CICADA_EXT_CONTROL MII_VENDOR(7) 1366 #define MII_CICADA_MODE_SELECT_BITS 0xf000 1367 #define MII_CICADA_MODE_SELECT_RGMII 0x1000 1368 #define MII_CICADA_POWER_SUPPLY_BITS 0x0e00 1369 #define MII_CICADA_POWER_SUPPLY_3_3V 0x0000 1370 #define MII_CICADA_POWER_SUPPLY_2_5V 0x0200 1371 1372 #define MII_CICADA_AUXCTRL_STATUS MII_VENDOR(12) 1373 #define MII_CICADA_PIN_PRORITY_SETTING 0x0004 1374 #define MII_CICADA_PIN_PRORITY_DEFAULT 0x0000 1375 1376 1377 #define NGE_REG_SIZE 0xfff 1378 #define NGE_MII_SIZE 0x20 1379 #define NGE_SEEROM_SIZE 0x800 1380 /* 1381 * Legacy rx's bd which does not support 1382 * any hardware offload 1383 */ 1384 typedef struct _legacy_rx_bd { 1385 uint32_t host_buf_addr; 1386 union { 1387 uint32_t cntl_val; 1388 struct { 1389 uint32_t bcnt:16; 1390 uint32_t end:1; 1391 uint32_t miss:1; 1392 uint32_t extra:1; 1393 uint32_t inten:1; 1394 uint32_t bam:1; 1395 uint32_t mam:1; 1396 uint32_t pam:1; 1397 uint32_t runt:1; 1398 uint32_t lcol:1; 1399 uint32_t max:1; 1400 uint32_t lfer:1; 1401 uint32_t crc:1; 1402 uint32_t ofol:1; 1403 uint32_t fram:1; 1404 uint32_t err:1; 1405 uint32_t own:1; 1406 } cntl_bits; 1407 } cntl_status; 1408 } legacy_rx_bd, *plegacy_rx_bd; 1409 1410 /* 1411 * Stand offload rx's bd which supports hareware checksum 1412 * for tcp/ip 1413 */ 1414 #define CK8G_NO_HSUM 0x0 1415 #define CK8G_TCP_SUM_ERR 0x1 1416 #define CK8G_UDP_SUM_ERR 0x2 1417 #define CK8G_IP_HSUM_ERR 0x3 1418 #define CK8G_IP_HSUM 0x4 1419 #define CK8G_TCP_SUM 0x5 1420 #define CK8G_UDP_SUM 0x6 1421 #define CK8G_RESV 0x7 1422 typedef struct _sum_rx_bd { 1423 uint32_t host_buf_addr; 1424 union { 1425 uint32_t cntl_val; 1426 struct { 1427 uint32_t bcnt:14; 1428 uint32_t resv14_29:16; 1429 uint32_t inten:1; 1430 uint32_t own:1; 1431 } control_bits; 1432 struct { 1433 uint32_t bcnt:14; 1434 uint32_t resv14:1; 1435 uint32_t bam:1; 1436 uint32_t mam:1; 1437 uint32_t pam:1; 1438 uint32_t runt:1; 1439 uint32_t lcol:1; 1440 uint32_t max:1; 1441 uint32_t lfer:1; 1442 uint32_t crc:1; 1443 uint32_t ofol:1; 1444 uint32_t fram:1; 1445 uint32_t extra:1; 1446 uint32_t l3_l4_sum:3; 1447 uint32_t rend:1; 1448 uint32_t err:1; 1449 uint32_t own:1; 1450 } status_bits; 1451 } cntl_status; 1452 } sum_rx_bd, *psum_rx_bd; 1453 /* 1454 * Hot offload rx's bd which support 64bit access and 1455 * full-tcp hardware offload 1456 */ 1457 typedef struct _hot_rx_bd { 1458 uint32_t host_buf_addr_hi; 1459 uint32_t host_buf_addr_lo; 1460 uint32_t sw_tag; 1461 union { 1462 uint32_t cntl_val; 1463 struct { 1464 uint32_t bcnt:14; 1465 uint32_t resv14_29:16; 1466 uint32_t inten:1; 1467 uint32_t own:1; 1468 } control_bits; 1469 1470 struct { 1471 uint32_t bcnt:14; 1472 uint32_t ctmach_rd:1; 1473 uint32_t bam:1; 1474 uint32_t mam:1; 1475 uint32_t pam:1; 1476 uint32_t runt:1; 1477 uint32_t lcol:1; 1478 uint32_t max:1; 1479 uint32_t lfer:1; 1480 uint32_t crc:1; 1481 uint32_t ofol:1; 1482 uint32_t fram:1; 1483 uint32_t extra:1; 1484 uint32_t l3_l4_sum:3; 1485 uint32_t rend:1; 1486 uint32_t err:1; 1487 uint32_t own:1; 1488 } status_bits_legacy; 1489 } cntl_status; 1490 } hot_rx_bd, *phot_rx_bd; 1491 1492 /* 1493 * Legacy tx's bd which does not support 1494 * any hardware offload 1495 */ 1496 typedef struct _legacy_tx_bd { 1497 uint32_t host_buf_addr; 1498 union { 1499 uint32_t cntl_val; 1500 struct { 1501 uint32_t bcnt:16; 1502 uint32_t end:1; 1503 uint32_t resv17_23:7; 1504 uint32_t inten:1; 1505 uint32_t resv25_30:6; 1506 uint32_t own:1; 1507 } control_bits; 1508 1509 struct { 1510 uint32_t bcnt:16; 1511 uint32_t end:1; 1512 uint32_t rtry:1; 1513 uint32_t trc:4; 1514 uint32_t inten:1; 1515 uint32_t exdef:1; 1516 uint32_t def:1; 1517 uint32_t lcar:1; 1518 uint32_t lcol:1; 1519 uint32_t uflo:1; 1520 uint32_t err:1; 1521 uint32_t own:1; 1522 } status_bits; 1523 } cntl_status; 1524 } legacy_tx_bd, *plegacy_tx_bd; 1525 1526 /* 1527 * Stand offload tx's bd which supports hareware checksum 1528 * for tcp/ip 1529 */ 1530 typedef struct _sum_tx_bd { 1531 uint32_t host_buf_addr; 1532 union { 1533 uint32_t cntl_val; 1534 struct { 1535 uint32_t bcnt:14; 1536 uint32_t resv14_25:12; 1537 uint32_t tcp_hsum:1; 1538 uint32_t ip_hsum:1; 1539 uint32_t segen:1; 1540 uint32_t end:1; 1541 uint32_t inten:1; 1542 uint32_t own:1; 1543 } control_sum_bits; 1544 1545 struct { 1546 uint32_t bcnt:14; 1547 uint32_t mss:14; 1548 uint32_t segen:1; 1549 uint32_t end:1; 1550 uint32_t inten:1; 1551 uint32_t own:1; 1552 } control_tso_bits; 1553 1554 struct { 1555 uint32_t bcnt:14; 1556 uint32_t resv14_17:4; 1557 uint32_t rtry:1; 1558 uint32_t trc:4; 1559 uint32_t inten:1; 1560 uint32_t exdef:1; 1561 uint32_t def:1; 1562 uint32_t lcar:1; 1563 uint32_t lcol:1; 1564 uint32_t uflo:1; 1565 uint32_t end:1; 1566 uint32_t err:1; 1567 uint32_t own:1; 1568 } status_bits; 1569 } control_status; 1570 } sum_tx_bd, *psum_tx_bd; 1571 1572 /* 1573 * Hot offload tx's bd which support 64bit access and 1574 * full-tcp hardware offload 1575 */ 1576 1577 typedef struct _hot_tx_bd { 1578 uint32_t host_buf_addr_hi; 1579 uint32_t host_buf_addr_lo; 1580 union { 1581 uint32_t parm_val; 1582 struct { 1583 uint32_t resv0_15:16; 1584 uint32_t resv16:1; 1585 uint32_t resv17:1; 1586 uint32_t resv18_31:14; 1587 } parm_bits; 1588 } hot_parms; 1589 1590 union { 1591 uint32_t cntl_val; 1592 struct { 1593 uint32_t bcnt:14; 1594 uint32_t resv14_25:12; 1595 uint32_t tcp_hsum:1; 1596 uint32_t ip_hsum:1; 1597 uint32_t segen:1; 1598 uint32_t end:1; 1599 uint32_t inten:1; 1600 uint32_t own:1; 1601 } control_sum_bits; 1602 1603 struct { 1604 uint32_t bcnt:14; 1605 uint32_t mss:14; 1606 uint32_t segen:1; 1607 uint32_t end:1; 1608 uint32_t inten:1; 1609 uint32_t own:1; 1610 } control_tso_bits; 1611 1612 struct { 1613 uint32_t bcnt:14; 1614 uint32_t resv14_17:4; 1615 uint32_t rtry:1; 1616 uint32_t trc:4; 1617 uint32_t inten:1; 1618 uint32_t exdef:1; 1619 uint32_t def:1; 1620 uint32_t lcar:1; 1621 uint32_t lcol:1; 1622 uint32_t uflo:1; 1623 uint32_t end:1; 1624 uint32_t err:1; 1625 uint32_t own:1; 1626 } status_bits; 1627 } control_status; 1628 } hot_tx_bd, *phot_tx_bd; 1629 1630 #ifdef __cplusplus 1631 } 1632 #endif 1633 1634 #endif /* _SYS_NGE_CHIP_H */ 1635