xref: /titanic_52/usr/src/uts/common/io/ixgbe/ixgbe_osdep.c (revision 0b656ad124c7fc1cd1ef064be05678da7a056a13)
19da57d7bSbt150084 /*
29da57d7bSbt150084  * CDDL HEADER START
39da57d7bSbt150084  *
473cd555cSBin Tu - Sun Microsystems - Beijing China  * Copyright(c) 2007-2009 Intel Corporation. All rights reserved.
59da57d7bSbt150084  * The contents of this file are subject to the terms of the
69da57d7bSbt150084  * Common Development and Distribution License (the "License").
79da57d7bSbt150084  * You may not use this file except in compliance with the License.
89da57d7bSbt150084  *
99da57d7bSbt150084  * You can obtain a copy of the license at:
109da57d7bSbt150084  *      http://www.opensolaris.org/os/licensing.
119da57d7bSbt150084  * See the License for the specific language governing permissions
129da57d7bSbt150084  * and limitations under the License.
139da57d7bSbt150084  *
149da57d7bSbt150084  * When using or redistributing this file, you may do so under the
159da57d7bSbt150084  * License only. No other modification of this header is permitted.
169da57d7bSbt150084  *
179da57d7bSbt150084  * If applicable, add the following below this CDDL HEADER, with the
189da57d7bSbt150084  * fields enclosed by brackets "[]" replaced with your own identifying
199da57d7bSbt150084  * information: Portions Copyright [yyyy] [name of copyright owner]
209da57d7bSbt150084  *
219da57d7bSbt150084  * CDDL HEADER END
229da57d7bSbt150084  */
239da57d7bSbt150084 
249da57d7bSbt150084 /*
2573cd555cSBin Tu - Sun Microsystems - Beijing China  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
2673cd555cSBin Tu - Sun Microsystems - Beijing China  * Use is subject to license terms.
27*0b656ad1SRobert Mustacchi  * Copyright (c) 2017, Joyent, Inc.
289da57d7bSbt150084  */
299da57d7bSbt150084 
30*0b656ad1SRobert Mustacchi #include "ixgbe_sw.h"
319da57d7bSbt150084 
329da57d7bSbt150084 uint16_t
339da57d7bSbt150084 ixgbe_read_pci_cfg(struct ixgbe_hw *hw, uint32_t reg)
349da57d7bSbt150084 {
359da57d7bSbt150084 	return (pci_config_get16(OS_DEP(hw)->cfg_handle, reg));
369da57d7bSbt150084 }
3773cd555cSBin Tu - Sun Microsystems - Beijing China 
3873cd555cSBin Tu - Sun Microsystems - Beijing China void
3973cd555cSBin Tu - Sun Microsystems - Beijing China ixgbe_write_pci_cfg(struct ixgbe_hw *hw, uint32_t reg, uint32_t val)
4073cd555cSBin Tu - Sun Microsystems - Beijing China {
4173cd555cSBin Tu - Sun Microsystems - Beijing China 	pci_config_put16(OS_DEP(hw)->cfg_handle, reg, val);
4273cd555cSBin Tu - Sun Microsystems - Beijing China }
43*0b656ad1SRobert Mustacchi 
44*0b656ad1SRobert Mustacchi /*
45*0b656ad1SRobert Mustacchi  * This is our last line of defense against a hardware device that has decided
46*0b656ad1SRobert Mustacchi  * to somehow disappear without our knowledge of it. To try and deal with this,
47*0b656ad1SRobert Mustacchi  * we'll read the status register and see if it returns all 1s, indicating an
48*0b656ad1SRobert Mustacchi  * invalid read. Note the status register is defined to have bits in all current
49*0b656ad1SRobert Mustacchi  * revisions that are hardwired to zero.
50*0b656ad1SRobert Mustacchi  */
51*0b656ad1SRobert Mustacchi boolean_t
52*0b656ad1SRobert Mustacchi ixgbe_removed(struct ixgbe_hw *hw)
53*0b656ad1SRobert Mustacchi {
54*0b656ad1SRobert Mustacchi 	uint32_t val;
55*0b656ad1SRobert Mustacchi 
56*0b656ad1SRobert Mustacchi 	val = IXGBE_READ_REG(hw, IXGBE_STATUS);
57*0b656ad1SRobert Mustacchi 	if (val == PCI_EINVAL32) {
58*0b656ad1SRobert Mustacchi 		ixgbe_t *ixgbe = OS_DEP(hw)->ixgbe;
59*0b656ad1SRobert Mustacchi 
60*0b656ad1SRobert Mustacchi 		ixgbe_error(ixgbe, "failed to read status register: device "
61*0b656ad1SRobert Mustacchi 		    "may be gone");
62*0b656ad1SRobert Mustacchi 		if (ixgbe->ixgbe_ks != NULL) {
63*0b656ad1SRobert Mustacchi 			ixgbe_stat_t *s = ixgbe->ixgbe_ks->ks_data;
64*0b656ad1SRobert Mustacchi 			s->dev_gone.value.ui64++;
65*0b656ad1SRobert Mustacchi 		}
66*0b656ad1SRobert Mustacchi 		return (B_TRUE);
67*0b656ad1SRobert Mustacchi 	}
68*0b656ad1SRobert Mustacchi 	return (B_FALSE);
69*0b656ad1SRobert Mustacchi }
70