1bb5e3b2fSeh146360 /* 2922d2c76Seh146360 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 3bb5e3b2fSeh146360 * Use is subject to license terms. 4bb5e3b2fSeh146360 */ 5bb5e3b2fSeh146360 6bb5e3b2fSeh146360 /* 7bb5e3b2fSeh146360 * Copyright (c) 2004, 2005 8bb5e3b2fSeh146360 * Damien Bergamini <damien.bergamini@free.fr>. All rights reserved. 9bb5e3b2fSeh146360 * 10bb5e3b2fSeh146360 * Redistribution and use in source and binary forms, with or without 11bb5e3b2fSeh146360 * modification, are permitted provided that the following conditions 12bb5e3b2fSeh146360 * are met: 13bb5e3b2fSeh146360 * 1. Redistributions of source code must retain the above copyright 14bb5e3b2fSeh146360 * notice unmodified, this list of conditions, and the following 15bb5e3b2fSeh146360 * disclaimer. 16bb5e3b2fSeh146360 * 2. Redistributions in binary form must reproduce the above copyright 17bb5e3b2fSeh146360 * notice, this list of conditions and the following disclaimer in the 18bb5e3b2fSeh146360 * documentation and/or other materials provided with the distribution. 19bb5e3b2fSeh146360 * 20bb5e3b2fSeh146360 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21bb5e3b2fSeh146360 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22bb5e3b2fSeh146360 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23bb5e3b2fSeh146360 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24bb5e3b2fSeh146360 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25bb5e3b2fSeh146360 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26bb5e3b2fSeh146360 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27bb5e3b2fSeh146360 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28bb5e3b2fSeh146360 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29bb5e3b2fSeh146360 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30bb5e3b2fSeh146360 * SUCH DAMAGE. 31bb5e3b2fSeh146360 */ 32bb5e3b2fSeh146360 33bb5e3b2fSeh146360 #ifndef _SYS_IPW2200_IMPL_H 34bb5e3b2fSeh146360 #define _SYS_IPW2200_IMPL_H 35bb5e3b2fSeh146360 36bb5e3b2fSeh146360 #ifdef __cplusplus 37bb5e3b2fSeh146360 extern "C" { 38bb5e3b2fSeh146360 #endif 39bb5e3b2fSeh146360 40bb5e3b2fSeh146360 /* 41bb5e3b2fSeh146360 * Intel Wireless PRO/2200 mini-pci adapter driver 42bb5e3b2fSeh146360 * ipw2200_impl.h includes: 43bb5e3b2fSeh146360 * . implementation of ipw2200 44bb5e3b2fSeh146360 * . hardware operations and interface definations for ipw2200 45bb5e3b2fSeh146360 * . firmware operations and interface definations for ipw2200 46bb5e3b2fSeh146360 */ 47bb5e3b2fSeh146360 #include <sys/ddi.h> 48bb5e3b2fSeh146360 #include <sys/sunddi.h> 49bb5e3b2fSeh146360 #include <sys/mac.h> 50bb5e3b2fSeh146360 #include <sys/mac_wifi.h> 51bb5e3b2fSeh146360 #include <sys/net80211.h> 52bb5e3b2fSeh146360 53bb5e3b2fSeh146360 /* 54bb5e3b2fSeh146360 * Implementation of ipw2200 55bb5e3b2fSeh146360 */ 56bb5e3b2fSeh146360 #define IPW2200_PCI_CFG_RNUM (0) /* pci config space */ 57bb5e3b2fSeh146360 #define IPW2200_PCI_CSR_RNUM (1) /* device CSR space */ 58bb5e3b2fSeh146360 #define IPW2200_PCI_INTR_NUM (0) /* interrupt number */ 59bb5e3b2fSeh146360 60bb5e3b2fSeh146360 #define IPW2200_TX_RING_SIZE (64) 61bb5e3b2fSeh146360 #define IPW2200_CMD_RING_SIZE (16) 62bb5e3b2fSeh146360 #define IPW2200_RX_RING_SIZE (32) 63bb5e3b2fSeh146360 64bb5e3b2fSeh146360 struct dma_region { 65bb5e3b2fSeh146360 ddi_dma_handle_t dr_hnd; 66bb5e3b2fSeh146360 ddi_acc_handle_t dr_acc; 67bb5e3b2fSeh146360 ddi_dma_cookie_t dr_cookie; 68bb5e3b2fSeh146360 uint_t dr_ccnt; 69bb5e3b2fSeh146360 uint32_t dr_pbase; 70bb5e3b2fSeh146360 caddr_t dr_base; 71bb5e3b2fSeh146360 size_t dr_size; 72bb5e3b2fSeh146360 const char *dr_name; 73bb5e3b2fSeh146360 }; 74bb5e3b2fSeh146360 75bb5e3b2fSeh146360 struct ipw2200_firmware { 76bb5e3b2fSeh146360 uint8_t *boot_base; /* boot code */ 77bb5e3b2fSeh146360 size_t boot_size; 78bb5e3b2fSeh146360 uint8_t *uc_base; /* u-controller code */ 79bb5e3b2fSeh146360 size_t uc_size; 80bb5e3b2fSeh146360 uint8_t *fw_base; /* firmware code */ 81bb5e3b2fSeh146360 size_t fw_size; 82bb5e3b2fSeh146360 }; 83bb5e3b2fSeh146360 84bb5e3b2fSeh146360 /* 85922d2c76Seh146360 * besides the statistic counted by net80211, driver can also record 86922d2c76Seh146360 * statistic data while process 87922d2c76Seh146360 */ 88922d2c76Seh146360 struct ipw2200_stats { 89922d2c76Seh146360 uint32_t sc_rx_len_err; 90922d2c76Seh146360 uint32_t sc_tx_discard; 91922d2c76Seh146360 uint32_t sc_tx_alloc_fail; 92922d2c76Seh146360 uint32_t sc_tx_encap_fail; 93922d2c76Seh146360 uint32_t sc_tx_crypto_fail; 94922d2c76Seh146360 }; 95922d2c76Seh146360 96922d2c76Seh146360 /* 97bb5e3b2fSeh146360 * per-instance soft-state structure 98bb5e3b2fSeh146360 */ 99bb5e3b2fSeh146360 struct ipw2200_softc { 100bb5e3b2fSeh146360 struct ieee80211com sc_ic; 101bb5e3b2fSeh146360 dev_info_t *sc_dip; 102bb5e3b2fSeh146360 int (*sc_newstate)(struct ieee80211com *, 103bb5e3b2fSeh146360 enum ieee80211_state, int); 104bb5e3b2fSeh146360 void (*sc_node_free)(struct ieee80211com *); 105bb5e3b2fSeh146360 int sc_authmode; 106bb5e3b2fSeh146360 107bb5e3b2fSeh146360 /* CSR */ 108bb5e3b2fSeh146360 ddi_acc_handle_t sc_ioh; 109bb5e3b2fSeh146360 caddr_t sc_regs; 110bb5e3b2fSeh146360 /* mutex to protect interrupt handler */ 111bb5e3b2fSeh146360 kmutex_t sc_ilock; 112bb5e3b2fSeh146360 /* interrupt iblock cookie */ 113bb5e3b2fSeh146360 ddi_iblock_cookie_t sc_iblk; 114bb5e3b2fSeh146360 /* soft interrupt */ 115bb5e3b2fSeh146360 ddi_softintr_t sc_link_softint; 116bb5e3b2fSeh146360 /* link status */ 117bb5e3b2fSeh146360 int32_t sc_linkstate; 118bb5e3b2fSeh146360 /* flags */ 119bb5e3b2fSeh146360 uint32_t sc_flags; 120bb5e3b2fSeh146360 #define IPW2200_FLAG_FW_CACHED (1 << 0) 121bb5e3b2fSeh146360 #define IPW2200_FLAG_FW_INITED (1 << 1) 122bb5e3b2fSeh146360 #define IPW2200_FLAG_RUNNING (1 << 2) 123bb5e3b2fSeh146360 #define IPW2200_FLAG_LINK_CHANGE (1 << 3) 124bb5e3b2fSeh146360 #define IPW2200_FLAG_TX_SCHED (1 << 4) 125bb5e3b2fSeh146360 #define IPW2200_FLAG_SCANNING (1 << 5) 126bb5e3b2fSeh146360 #define IPW2200_FLAG_HW_ERR_RECOVER (1 << 6) 127924f3e72Seh146360 #define IPW2200_FLAG_ASSOCIATED (1 << 7) 128922d2c76Seh146360 #define IPW2200_FLAG_SUSPEND (1 << 8) 129*14d91224Sfei feng - Sun Microsystems - Beijing China #define IPW2200_FLAG_QUIESCED (1 << 9) 130bb5e3b2fSeh146360 #define IPW2200_FLAG_HAS_RADIO_SWITCH (1 << 16) 131bb5e3b2fSeh146360 /* firmware download */ 132bb5e3b2fSeh146360 int sc_fw_ok; 133bb5e3b2fSeh146360 kcondvar_t sc_fw_cond; 134bb5e3b2fSeh146360 135bb5e3b2fSeh146360 /* command desc ring */ 136bb5e3b2fSeh146360 kmutex_t sc_cmd_lock; 137bb5e3b2fSeh146360 kcondvar_t sc_cmd_cond; 138bb5e3b2fSeh146360 uint32_t sc_cmd_cur; 139bb5e3b2fSeh146360 uint32_t sc_cmd_free; 140bb5e3b2fSeh146360 struct ipw2200_cmd_desc *sc_cmdsc; 141bb5e3b2fSeh146360 142bb5e3b2fSeh146360 /* command status */ 143bb5e3b2fSeh146360 int sc_done[IPW2200_CMD_RING_SIZE]; 144bb5e3b2fSeh146360 kcondvar_t sc_cmd_status_cond; 145bb5e3b2fSeh146360 146bb5e3b2fSeh146360 /* tx ring, bd->hdr&buf */ 147bb5e3b2fSeh146360 kmutex_t sc_tx_lock; 148bb5e3b2fSeh146360 uint32_t sc_tx_cur; 149bb5e3b2fSeh146360 uint32_t sc_tx_free; 150bb5e3b2fSeh146360 struct ipw2200_tx_desc *sc_txdsc; 151bb5e3b2fSeh146360 uint8_t *sc_txbufs[IPW2200_TX_RING_SIZE]; 152bb5e3b2fSeh146360 153bb5e3b2fSeh146360 /* rx ring */ 154bb5e3b2fSeh146360 uint32_t sc_rx_cur; 155bb5e3b2fSeh146360 uint32_t sc_rx_free; 156bb5e3b2fSeh146360 uint8_t *sc_rxbufs[IPW2200_RX_RING_SIZE]; 157bb5e3b2fSeh146360 158bb5e3b2fSeh146360 /* tx-desc & tx-buffer array */ 159bb5e3b2fSeh146360 struct dma_region sc_dma_txdsc; 160bb5e3b2fSeh146360 struct dma_region sc_dma_txbufs[IPW2200_TX_RING_SIZE]; 161bb5e3b2fSeh146360 struct dma_region sc_dma_cmdsc; 162bb5e3b2fSeh146360 /* rx-buffer array */ 163bb5e3b2fSeh146360 struct dma_region sc_dma_rxbufs[IPW2200_RX_RING_SIZE]; 164bb5e3b2fSeh146360 165bb5e3b2fSeh146360 /* hw configuration values */ 166bb5e3b2fSeh146360 uint8_t sc_macaddr[IEEE80211_ADDR_LEN]; 167bb5e3b2fSeh146360 /* MAC address string */ 168bb5e3b2fSeh146360 char sc_macstr[32]; 169bb5e3b2fSeh146360 170bb5e3b2fSeh146360 /* firmware */ 171bb5e3b2fSeh146360 struct ipw2200_firmware sc_fw; 172bb5e3b2fSeh146360 173924f3e72Seh146360 /* reschedule lock */ 174924f3e72Seh146360 kmutex_t sc_resched_lock; 175924f3e72Seh146360 176922d2c76Seh146360 /* pci information */ 177922d2c76Seh146360 uint16_t sc_vendor, sc_device, sc_subven, sc_subdev; 178922d2c76Seh146360 179922d2c76Seh146360 /* statistic counting by driver */ 180922d2c76Seh146360 struct ipw2200_stats sc_stats; 181922d2c76Seh146360 182bb5e3b2fSeh146360 /* mfthread related, mfthread is used to handle asynchronous task */ 183bb5e3b2fSeh146360 kthread_t *sc_mf_thread; 184bb5e3b2fSeh146360 kmutex_t sc_mflock; 185bb5e3b2fSeh146360 int sc_mfthread_switch; 186bb5e3b2fSeh146360 kcondvar_t sc_mfthread_req; 187bb5e3b2fSeh146360 kcondvar_t sc_mfthread_cv; 188bb5e3b2fSeh146360 189bb5e3b2fSeh146360 }; 190bb5e3b2fSeh146360 191bb5e3b2fSeh146360 /* 192bb5e3b2fSeh146360 * RING_BACKWARD - move 'x' backward 's' steps in a 'b'- sized ring 193bb5e3b2fSeh146360 * RING_FORWARD - move 'x' forward 's' steps in a 'b'- sized ring 194bb5e3b2fSeh146360 * 195bb5e3b2fSeh146360 * note that there must be 0 <= 'x' < 'b' && 0 <= 's' < 'b' 196bb5e3b2fSeh146360 */ 197bb5e3b2fSeh146360 #define RING_FLEN(x, y, b) ((((x) > (y)) ? ((b)+(y)-(x)) : ((y)-(x)))) 198bb5e3b2fSeh146360 #define RING_FORWARD(x, s, b) (((x)+(s))%(b)) 199bb5e3b2fSeh146360 #define RING_BACKWARD(x, s, b) RING_FORWARD((x), (b)-(s), (b)) 200bb5e3b2fSeh146360 201bb5e3b2fSeh146360 extern int ipw2200_init(struct ipw2200_softc *sc); 202bb5e3b2fSeh146360 extern void ipw2200_wifi_ioctl(struct ipw2200_softc *, queue_t *, 203bb5e3b2fSeh146360 mblk_t *, uint32_t); 204bb5e3b2fSeh146360 extern int ipw2200_dma_region_alloc(struct ipw2200_softc *sc, 205bb5e3b2fSeh146360 struct dma_region *dr, size_t size, uint_t dir, uint_t flags); 206bb5e3b2fSeh146360 extern void ipw2200_dma_region_free(struct dma_region *dr); 207bb5e3b2fSeh146360 extern int ipw2200_disable(struct ipw2200_softc *sc); 208bb5e3b2fSeh146360 extern int ipw2200_start_scan(struct ipw2200_softc *sc); 209bb5e3b2fSeh146360 210bb5e3b2fSeh146360 /* 211bb5e3b2fSeh146360 * get radio off/on status 212bb5e3b2fSeh146360 */ 213bb5e3b2fSeh146360 extern int ipw2200_radio_status(struct ipw2200_softc *sc); 214bb5e3b2fSeh146360 215bb5e3b2fSeh146360 /* 216bb5e3b2fSeh146360 * Below structure and functions will be used for statistic, which will be 217bb5e3b2fSeh146360 * displayed when the wificonfig running... 218bb5e3b2fSeh146360 */ 219bb5e3b2fSeh146360 struct statistic { 220bb5e3b2fSeh146360 int index; 221bb5e3b2fSeh146360 const char *desc; 222bb5e3b2fSeh146360 }; 223bb5e3b2fSeh146360 extern void ipw2200_get_statistics(struct ipw2200_softc *sc); 224bb5e3b2fSeh146360 225bb5e3b2fSeh146360 /* 226bb5e3b2fSeh146360 * Hardware related definations and interfaces. 227bb5e3b2fSeh146360 */ 228bb5e3b2fSeh146360 #define IPW2200_CSR_INTR (0x0008) 229bb5e3b2fSeh146360 #define IPW2200_CSR_INTR_MASK (0x000c) 230bb5e3b2fSeh146360 #define IPW2200_CSR_INDIRECT_ADDR (0x0010) 231bb5e3b2fSeh146360 #define IPW2200_CSR_INDIRECT_DATA (0x0014) 232bb5e3b2fSeh146360 #define IPW2200_CSR_AUTOINC_ADDR (0x0018) 233bb5e3b2fSeh146360 #define IPW2200_CSR_AUTOINC_DATA (0x001c) 234bb5e3b2fSeh146360 #define IPW2200_CSR_RST (0x0020) 235bb5e3b2fSeh146360 #define IPW2200_CSR_CTL (0x0024) 236bb5e3b2fSeh146360 #define IPW2200_CSR_IO (0x0030) 237bb5e3b2fSeh146360 #define IPW2200_CSR_CMD_BASE (0x0200) 238bb5e3b2fSeh146360 #define IPW2200_CSR_CMD_SIZE (0x0204) 239bb5e3b2fSeh146360 #define IPW2200_CSR_TX1_BASE (0x0208) 240bb5e3b2fSeh146360 #define IPW2200_CSR_TX1_SIZE (0x020c) 241bb5e3b2fSeh146360 #define IPW2200_CSR_TX2_BASE (0x0210) 242bb5e3b2fSeh146360 #define IPW2200_CSR_TX2_SIZE (0x0214) 243bb5e3b2fSeh146360 #define IPW2200_CSR_TX3_BASE (0x0218) 244bb5e3b2fSeh146360 #define IPW2200_CSR_TX3_SIZE (0x021c) 245bb5e3b2fSeh146360 #define IPW2200_CSR_TX4_BASE (0x0220) 246bb5e3b2fSeh146360 #define IPW2200_CSR_TX4_SIZE (0x0224) 247bb5e3b2fSeh146360 #define IPW2200_CSR_CMD_READ_INDEX (0x0280) 248bb5e3b2fSeh146360 #define IPW2200_CSR_TX1_READ_INDEX (0x0284) 249bb5e3b2fSeh146360 #define IPW2200_CSR_TX2_READ_INDEX (0x0288) 250bb5e3b2fSeh146360 #define IPW2200_CSR_TX3_READ_INDEX (0x028c) 251bb5e3b2fSeh146360 #define IPW2200_CSR_TX4_READ_INDEX (0x0290) 252bb5e3b2fSeh146360 #define IPW2200_CSR_RX_READ_INDEX (0x02a0) 253bb5e3b2fSeh146360 #define IPW2200_CSR_RX_BASE (0x0500) 254bb5e3b2fSeh146360 #define IPW2200_CSR_TABLE0_SIZE (0x0700) 255bb5e3b2fSeh146360 #define IPW2200_CSR_TABLE0_BASE (0x0704) 256bb5e3b2fSeh146360 #define IPW2200_CSR_NODE_BASE (0x0c0c) 257bb5e3b2fSeh146360 #define IPW2200_CSR_CMD_WRITE_INDEX (0x0f80) 258bb5e3b2fSeh146360 #define IPW2200_CSR_TX1_WRITE_INDEX (0x0f84) 259bb5e3b2fSeh146360 #define IPW2200_CSR_TX2_WRITE_INDEX (0x0f88) 260bb5e3b2fSeh146360 #define IPW2200_CSR_TX3_WRITE_INDEX (0x0f8c) 261bb5e3b2fSeh146360 #define IPW2200_CSR_TX4_WRITE_INDEX (0x0f90) 262bb5e3b2fSeh146360 #define IPW2200_CSR_RX_WRITE_INDEX (0x0fa0) 263bb5e3b2fSeh146360 #define IPW2200_CSR_READ_INT (0x0ff4) 264bb5e3b2fSeh146360 265bb5e3b2fSeh146360 #define IPW2200_CSR_CURRENTT_TX_RATE IPW2200_CSR_TABLE0_BASE 266bb5e3b2fSeh146360 267bb5e3b2fSeh146360 /* 268bb5e3b2fSeh146360 * CSR flags: IPW2200_CSR_INTR 269bb5e3b2fSeh146360 */ 270bb5e3b2fSeh146360 #define IPW2200_INTR_RX_TRANSFER (0x00000002) 271bb5e3b2fSeh146360 #define IPW2200_INTR_CMD_TRANSFER (0x00000800) 272bb5e3b2fSeh146360 #define IPW2200_INTR_TX1_TRANSFER (0x00001000) 273bb5e3b2fSeh146360 #define IPW2200_INTR_TX2_TRANSFER (0x00002000) 274bb5e3b2fSeh146360 #define IPW2200_INTR_TX3_TRANSFER (0x00004000) 275bb5e3b2fSeh146360 #define IPW2200_INTR_TX4_TRANSFER (0x00008000) 276bb5e3b2fSeh146360 #define IPW2200_INTR_FW_INITED (0x01000000) 277bb5e3b2fSeh146360 #define IPW2200_INTR_RADIO_OFF (0x04000000) 278bb5e3b2fSeh146360 #define IPW2200_INTR_FATAL_ERROR (0x40000000) 279bb5e3b2fSeh146360 #define IPW2200_INTR_PARITY_ERROR (0x80000000) 280bb5e3b2fSeh146360 281bb5e3b2fSeh146360 #define IPW2200_INTR_MASK_ALL (IPW2200_INTR_RX_TRANSFER | \ 282bb5e3b2fSeh146360 IPW2200_INTR_CMD_TRANSFER | \ 283bb5e3b2fSeh146360 IPW2200_INTR_TX1_TRANSFER | \ 284bb5e3b2fSeh146360 IPW2200_INTR_TX2_TRANSFER | \ 285bb5e3b2fSeh146360 IPW2200_INTR_TX3_TRANSFER | \ 286bb5e3b2fSeh146360 IPW2200_INTR_TX4_TRANSFER | \ 287bb5e3b2fSeh146360 IPW2200_INTR_FW_INITED | \ 288bb5e3b2fSeh146360 IPW2200_INTR_RADIO_OFF | \ 289bb5e3b2fSeh146360 IPW2200_INTR_FATAL_ERROR | \ 290bb5e3b2fSeh146360 IPW2200_INTR_PARITY_ERROR) 291bb5e3b2fSeh146360 292bb5e3b2fSeh146360 #define IPW2200_INTR_MASK_ERR (IPW2200_INTR_FATAL_ERROR | \ 293bb5e3b2fSeh146360 IPW2200_INTR_PARITY_ERROR) 294bb5e3b2fSeh146360 295bb5e3b2fSeh146360 /* 296bb5e3b2fSeh146360 * CSR flags for register: IPW2200_CSR_RST, which is used to reset h/w 297bb5e3b2fSeh146360 */ 298bb5e3b2fSeh146360 #define IPW2200_RST_PRINCETON_RESET (0x00000001) 299bb5e3b2fSeh146360 #define IPW2200_RST_STANDBY (0x00000004) 300bb5e3b2fSeh146360 #define IPW2200_RST_LED_ACTIVITY (0x00000010) 301bb5e3b2fSeh146360 #define IPW2200_RST_LED_ASSOCIATED (0x00000020) 302bb5e3b2fSeh146360 #define IPW2200_RST_LED_OFDM (0x00000040) 303bb5e3b2fSeh146360 #define IPW2200_RST_SW_RESET (0x00000080) 304bb5e3b2fSeh146360 #define IPW2200_RST_MASTER_DISABLED (0x00000100) 305bb5e3b2fSeh146360 #define IPW2200_RST_STOP_MASTER (0x00000200) 306bb5e3b2fSeh146360 #define IPW2200_RST_GATE_ODMA (0x02000000) 307bb5e3b2fSeh146360 #define IPW2200_RST_GATE_IDMA (0x04000000) 308bb5e3b2fSeh146360 #define IPW2200_RST_GATE_ADMA (0x20000000) 309bb5e3b2fSeh146360 310bb5e3b2fSeh146360 /* 311bb5e3b2fSeh146360 * CSR flags for register: IPW2200_CSR_CTL 312bb5e3b2fSeh146360 */ 313bb5e3b2fSeh146360 #define IPW2200_CTL_CLOCK_READY (0x00000001) 314bb5e3b2fSeh146360 #define IPW2200_CTL_ALLOW_STANDBY (0x00000002) 315bb5e3b2fSeh146360 #define IPW2200_CTL_INIT (0x00000004) 316bb5e3b2fSeh146360 317bb5e3b2fSeh146360 /* 318bb5e3b2fSeh146360 * CSR flags for register: IPW2200_CSR_IO 319bb5e3b2fSeh146360 */ 320bb5e3b2fSeh146360 #define IPW2200_IO_RADIO_ENABLED (0x00010000) 321bb5e3b2fSeh146360 322bb5e3b2fSeh146360 /* 323bb5e3b2fSeh146360 * CSR flags for register: IPW2200_CSR_READ_INT 324bb5e3b2fSeh146360 */ 325bb5e3b2fSeh146360 #define IPW2200_READ_INT_INIT_HOST (0x20000000) 326bb5e3b2fSeh146360 327bb5e3b2fSeh146360 /* table2 offsets */ 328bb5e3b2fSeh146360 #define IPW2200_INFO_ADAPTER_MAC (40) 329bb5e3b2fSeh146360 330bb5e3b2fSeh146360 /* constants for command blocks */ 331bb5e3b2fSeh146360 #define IPW2200_CB_DEFAULT_CTL (0x8cea0000) 332bb5e3b2fSeh146360 #define IPW2200_CB_MAXDATALEN (8191) 333bb5e3b2fSeh146360 334bb5e3b2fSeh146360 /* supported rates */ 335bb5e3b2fSeh146360 #define IPW2200_RATE_DS1 (10) 336bb5e3b2fSeh146360 #define IPW2200_RATE_DS2 (20) 337bb5e3b2fSeh146360 #define IPW2200_RATE_DS5 (55) 338bb5e3b2fSeh146360 #define IPW2200_RATE_DS11 (110) 339bb5e3b2fSeh146360 #define IPW2200_RATE_OFDM6 (13) 340bb5e3b2fSeh146360 #define IPW2200_RATE_OFDM9 (15) 341bb5e3b2fSeh146360 #define IPW2200_RATE_OFDM12 (5) 342bb5e3b2fSeh146360 #define IPW2200_RATE_OFDM18 (7) 343bb5e3b2fSeh146360 #define IPW2200_RATE_OFDM24 (9) 344bb5e3b2fSeh146360 #define IPW2200_RATE_OFDM36 (11) 345bb5e3b2fSeh146360 #define IPW2200_RATE_OFDM48 (1) 346bb5e3b2fSeh146360 #define IPW2200_RATE_OFDM54 (3) 347bb5e3b2fSeh146360 348bb5e3b2fSeh146360 #pragma pack(1) 349bb5e3b2fSeh146360 /* HW structures, packed */ 350bb5e3b2fSeh146360 351bb5e3b2fSeh146360 struct ipw2200_hdr { 352bb5e3b2fSeh146360 uint8_t type; 353bb5e3b2fSeh146360 #define IPW2200_HDR_TYPE_DATA (0) 354bb5e3b2fSeh146360 #define IPW2200_HDR_TYPE_COMMAND (1) 355bb5e3b2fSeh146360 #define IPW2200_HDR_TYPE_NOTIF (3) 356bb5e3b2fSeh146360 #define IPW2200_HDR_TYPE_FRAME (9) 357bb5e3b2fSeh146360 uint8_t seq; 358bb5e3b2fSeh146360 uint8_t flags; 359bb5e3b2fSeh146360 #define IPW2200_HDR_FLAG_IRQ (0x04) 360bb5e3b2fSeh146360 uint8_t reserved; 361bb5e3b2fSeh146360 }; 362bb5e3b2fSeh146360 363bb5e3b2fSeh146360 struct ipw2200_notif { 364bb5e3b2fSeh146360 uint32_t reserved[2]; 365bb5e3b2fSeh146360 uint8_t type; 366bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_SUCCESS (0) 367bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_UNSPECIFIED (1) 368bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_ASSOCIATION (10) 369bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_AUTHENTICATION (11) 370bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_SCAN_CHANNEL (12) 371bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_SCAN_COMPLETE (13) 372bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_FRAG_LENGTH (14) 373bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_LINK_QUALITY (15) 374bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_BEACON (17) 375bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_TGI_TX_KEY (18) 376bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_CALIBRATION (20) 377bb5e3b2fSeh146360 #define IPW2200_NOTIF_TYPE_NOISE (25) 378bb5e3b2fSeh146360 uint8_t flags; 379bb5e3b2fSeh146360 uint16_t len; 380bb5e3b2fSeh146360 }; 381bb5e3b2fSeh146360 382bb5e3b2fSeh146360 /* 383bb5e3b2fSeh146360 * structure for notification IPW2200_NOTIF_TYPE_AUTHENTICATION 384bb5e3b2fSeh146360 */ 385bb5e3b2fSeh146360 struct ipw2200_notif_authentication { 386bb5e3b2fSeh146360 uint8_t state; 387bb5e3b2fSeh146360 #define IPW2200_AUTH_FAIL (0) 388bb5e3b2fSeh146360 #define IPW2200_AUTH_SENT_1 (1) 389bb5e3b2fSeh146360 #define IPW2200_AUTH_RECV_2 (2) 390bb5e3b2fSeh146360 #define IPW2200_AUTH_SEQ1_PASS (3) 391bb5e3b2fSeh146360 #define IPW2200_AUTH_SEQ1_FAIL (4) 392bb5e3b2fSeh146360 #define IPW2200_AUTH_SUCCESS (9) 393bb5e3b2fSeh146360 }; 394bb5e3b2fSeh146360 395bb5e3b2fSeh146360 /* 396bb5e3b2fSeh146360 * structure for notification IPW2200_NOTIF_TYPE_ASSOCIATION 397bb5e3b2fSeh146360 */ 398bb5e3b2fSeh146360 struct ipw2200_notif_association { 399bb5e3b2fSeh146360 uint8_t state; 400bb5e3b2fSeh146360 #define IPW2200_ASSOC_FAIL (0) 401bb5e3b2fSeh146360 #define IPW2200_ASSOC_SUCCESS (12) 402bb5e3b2fSeh146360 struct ieee80211_frame frame; 403bb5e3b2fSeh146360 uint16_t capinfo; 404bb5e3b2fSeh146360 uint16_t status; 405bb5e3b2fSeh146360 uint16_t associd; 406bb5e3b2fSeh146360 }; 407bb5e3b2fSeh146360 408bb5e3b2fSeh146360 /* 409bb5e3b2fSeh146360 * structure for notification BACAON 410bb5e3b2fSeh146360 */ 411bb5e3b2fSeh146360 struct ipw2200_notif_beacon_state { 412bb5e3b2fSeh146360 uint32_t state; 413bb5e3b2fSeh146360 #define IPW2200_BEACON_MISS (1) 414bb5e3b2fSeh146360 uint32_t number; 415bb5e3b2fSeh146360 }; 416bb5e3b2fSeh146360 417bb5e3b2fSeh146360 /* 418bb5e3b2fSeh146360 * structure for notification IPW2200_NOTIF_TYPE_SCAN_CHANNEL 419bb5e3b2fSeh146360 */ 420bb5e3b2fSeh146360 struct ipw2200_notif_scan_channel { 421bb5e3b2fSeh146360 uint8_t nchan; 422bb5e3b2fSeh146360 uint8_t reserved[47]; 423bb5e3b2fSeh146360 }; 424bb5e3b2fSeh146360 425bb5e3b2fSeh146360 /* 426bb5e3b2fSeh146360 * structure for notification IPW2200_NOTIF_TYPE_SCAN_COMPLETE 427bb5e3b2fSeh146360 */ 428bb5e3b2fSeh146360 struct ipw2200_notif_scan_complete { 429bb5e3b2fSeh146360 uint8_t type; 430bb5e3b2fSeh146360 uint8_t nchan; 431bb5e3b2fSeh146360 uint8_t status; 432bb5e3b2fSeh146360 uint8_t reserved; 433bb5e3b2fSeh146360 }; 434bb5e3b2fSeh146360 435bb5e3b2fSeh146360 /* 436bb5e3b2fSeh146360 * received frame header 437bb5e3b2fSeh146360 */ 438bb5e3b2fSeh146360 struct ipw2200_frame { 439bb5e3b2fSeh146360 uint32_t reserved1[2]; 440bb5e3b2fSeh146360 uint8_t chan; 441bb5e3b2fSeh146360 uint8_t status; 442bb5e3b2fSeh146360 uint8_t rate; 443bb5e3b2fSeh146360 uint8_t rssi; /* receiver signal strength indicator */ 444bb5e3b2fSeh146360 uint8_t agc; /* automatic gain control */ 445bb5e3b2fSeh146360 uint8_t rssi_dbm; 446bb5e3b2fSeh146360 uint16_t signal; 447bb5e3b2fSeh146360 uint16_t noise; 448bb5e3b2fSeh146360 uint8_t antenna; 449bb5e3b2fSeh146360 uint8_t control; 450bb5e3b2fSeh146360 uint8_t reserved3[2]; 451bb5e3b2fSeh146360 uint16_t len; 452bb5e3b2fSeh146360 }; 453bb5e3b2fSeh146360 454bb5e3b2fSeh146360 /* 455bb5e3b2fSeh146360 * header for transmission 456bb5e3b2fSeh146360 */ 457bb5e3b2fSeh146360 struct ipw2200_tx_desc { 458bb5e3b2fSeh146360 struct ipw2200_hdr hdr; 459bb5e3b2fSeh146360 uint32_t reserved1; 460bb5e3b2fSeh146360 uint8_t station; 461bb5e3b2fSeh146360 uint8_t reserved2[3]; 462bb5e3b2fSeh146360 uint8_t cmd; 463bb5e3b2fSeh146360 #define IPW2200_DATA_CMD_TX (0x0b) 464bb5e3b2fSeh146360 uint8_t seq; 465bb5e3b2fSeh146360 uint16_t len; 466bb5e3b2fSeh146360 uint8_t priority; 467bb5e3b2fSeh146360 uint8_t flags; 468bb5e3b2fSeh146360 #define IPW2200_DATA_FLAG_SHPREAMBLE (0x04) 469bb5e3b2fSeh146360 #define IPW2200_DATA_FLAG_NO_WEP (0x20) 470bb5e3b2fSeh146360 #define IPW2200_DATA_FLAG_NEED_ACK (0x80) 471bb5e3b2fSeh146360 uint8_t xflags; 472bb5e3b2fSeh146360 #define IPW2200_DATA_XFLAG_QOS (0x10) 473bb5e3b2fSeh146360 uint8_t wep_txkey; 474bb5e3b2fSeh146360 uint8_t wepkey[IEEE80211_KEYBUF_SIZE]; 475bb5e3b2fSeh146360 uint8_t rate; 476bb5e3b2fSeh146360 uint8_t antenna; 477bb5e3b2fSeh146360 uint8_t reserved3[10]; 478bb5e3b2fSeh146360 479bb5e3b2fSeh146360 struct ieee80211_frame_addr4 wh; 480bb5e3b2fSeh146360 uint8_t reserved4[2]; 481bb5e3b2fSeh146360 uint32_t iv; 482bb5e3b2fSeh146360 uint32_t eiv; 483bb5e3b2fSeh146360 484bb5e3b2fSeh146360 uint32_t nseg; 485bb5e3b2fSeh146360 #define IPW2200_MAX_NSEG (6) 486bb5e3b2fSeh146360 uint32_t seg_addr[IPW2200_MAX_NSEG]; 487bb5e3b2fSeh146360 uint16_t seg_len[IPW2200_MAX_NSEG]; 488bb5e3b2fSeh146360 }; 489bb5e3b2fSeh146360 490bb5e3b2fSeh146360 /* 491bb5e3b2fSeh146360 * command 492bb5e3b2fSeh146360 */ 493bb5e3b2fSeh146360 struct ipw2200_cmd_desc { 494bb5e3b2fSeh146360 struct ipw2200_hdr hdr; 495bb5e3b2fSeh146360 uint8_t type; 496bb5e3b2fSeh146360 #define IPW2200_CMD_ENABLE (2) 497bb5e3b2fSeh146360 #define IPW2200_CMD_SET_CONFIG (6) 498bb5e3b2fSeh146360 #define IPW2200_CMD_SET_ESSID (8) 499bb5e3b2fSeh146360 #define IPW2200_CMD_SET_MAC_ADDRESS (11) 500bb5e3b2fSeh146360 #define IPW2200_CMD_SET_RTS_THRESHOLD (15) 501bb5e3b2fSeh146360 #define IPW2200_CMD_SET_FRAG_THRESHOLD (16) 502bb5e3b2fSeh146360 #define IPW2200_CMD_SET_POWER_MODE (17) 503bb5e3b2fSeh146360 #define IPW2200_CMD_SET_WEP_KEY (18) 504bb5e3b2fSeh146360 #define IPW2200_CMD_SCAN (20) 505bb5e3b2fSeh146360 #define IPW2200_CMD_ASSOCIATE (21) 506bb5e3b2fSeh146360 #define IPW2200_CMD_SET_RATES (22) 507bb5e3b2fSeh146360 #define IPW2200_CMD_ABORT_SCAN (23) 508bb5e3b2fSeh146360 #define IPW2200_CMD_SET_WME_PARAMS (25) 509bb5e3b2fSeh146360 #define IPW2200_CMD_SCAN_EXT (26) 510bb5e3b2fSeh146360 #define IPW2200_CMD_SET_OPTIE (31) 511bb5e3b2fSeh146360 #define IPW2200_CMD_DISABLE (33) 512bb5e3b2fSeh146360 #define IPW2200_CMD_SET_IV (34) 513bb5e3b2fSeh146360 #define IPW2200_CMD_SET_TX_POWER (35) 514bb5e3b2fSeh146360 #define IPW2200_CMD_SET_SENSITIVITY (42) 515bb5e3b2fSeh146360 #define IPW2200_CMD_SET_WMEIE (84) 516bb5e3b2fSeh146360 uint8_t len; 517bb5e3b2fSeh146360 uint16_t reserved; 518bb5e3b2fSeh146360 uint8_t data[120]; 519bb5e3b2fSeh146360 }; 520bb5e3b2fSeh146360 521bb5e3b2fSeh146360 /* 522bb5e3b2fSeh146360 * node information (IBSS) 523bb5e3b2fSeh146360 */ 524bb5e3b2fSeh146360 struct ipw2200_ibssnode { 525bb5e3b2fSeh146360 uint8_t bssid[IEEE80211_ADDR_LEN]; 526bb5e3b2fSeh146360 uint8_t reserved[2]; 527bb5e3b2fSeh146360 }; 528bb5e3b2fSeh146360 529bb5e3b2fSeh146360 /* 530bb5e3b2fSeh146360 * constants for 'mode' fields 531bb5e3b2fSeh146360 */ 532bb5e3b2fSeh146360 #define IPW2200_MODE_11A (0) 533bb5e3b2fSeh146360 #define IPW2200_MODE_11B (1) 534bb5e3b2fSeh146360 #define IPW2200_MODE_11G (2) 535bb5e3b2fSeh146360 536bb5e3b2fSeh146360 /* 537bb5e3b2fSeh146360 * macro for command IPW2200_CMD_SET_SENSITIVITY 538bb5e3b2fSeh146360 */ 539bb5e3b2fSeh146360 #define IPW2200_RSSIDBM2RAW(rssi)((rssi) - 112) 540bb5e3b2fSeh146360 541bb5e3b2fSeh146360 /* 542bb5e3b2fSeh146360 * possible values for command IPW2200_CMD_SET_POWER_MODE 543bb5e3b2fSeh146360 */ 544bb5e3b2fSeh146360 #define IPW2200_POWER_MODE_CAM (0) 545bb5e3b2fSeh146360 #define IPW2200_POWER_MODE_PSP (3) 546bb5e3b2fSeh146360 #define IPW2200_POWER_MODE_MAX (5) 547bb5e3b2fSeh146360 548bb5e3b2fSeh146360 /* 549bb5e3b2fSeh146360 * structure for command IPW2200_CMD_SET_RATES 550bb5e3b2fSeh146360 */ 551bb5e3b2fSeh146360 struct ipw2200_rateset { 552bb5e3b2fSeh146360 uint8_t mode; 553bb5e3b2fSeh146360 uint8_t nrates; 554bb5e3b2fSeh146360 uint8_t type; 555bb5e3b2fSeh146360 #define IPW2200_RATESET_TYPE_NEGOCIATED (0) 556bb5e3b2fSeh146360 #define IPW2200_RATESET_TYPE_SUPPORTED (1) 557bb5e3b2fSeh146360 uint8_t reserved; 558bb5e3b2fSeh146360 uint8_t rates[12]; 559bb5e3b2fSeh146360 }; 560bb5e3b2fSeh146360 561bb5e3b2fSeh146360 /* 562bb5e3b2fSeh146360 * structure for command IPW2200_CMD_SET_TX_POWER 563bb5e3b2fSeh146360 */ 564bb5e3b2fSeh146360 struct ipw2200_txpower { 565bb5e3b2fSeh146360 uint8_t nchan; 566bb5e3b2fSeh146360 uint8_t mode; 567bb5e3b2fSeh146360 struct { 568bb5e3b2fSeh146360 uint8_t chan; 569bb5e3b2fSeh146360 uint8_t power; 570bb5e3b2fSeh146360 #define IPW2200_TXPOWER_MAX (20) 571bb5e3b2fSeh146360 #define IPW2200_TXPOWER_RATIO (IEEE80211_TXPOWER_MAX / IPW2200_TXPOWER_MAX) 572bb5e3b2fSeh146360 } chan[37]; 573bb5e3b2fSeh146360 }; 574bb5e3b2fSeh146360 575bb5e3b2fSeh146360 /* 576bb5e3b2fSeh146360 * structure for command IPW2200_CMD_ASSOCIATE 577bb5e3b2fSeh146360 */ 578bb5e3b2fSeh146360 struct ipw2200_associate { 579bb5e3b2fSeh146360 uint8_t chan; 580bb5e3b2fSeh146360 uint8_t auth; 581bb5e3b2fSeh146360 #define IPW2200_AUTH_OPEN (0) 582bb5e3b2fSeh146360 #define IPW2200_AUTH_SHARED (1) 583bb5e3b2fSeh146360 #define IPW2200_AUTH_NONE (3) 584bb5e3b2fSeh146360 uint8_t type; 585bb5e3b2fSeh146360 #define IPW2200_HC_ASSOC (0) 586bb5e3b2fSeh146360 #define IPW2200_HC_REASSOC (1) 587bb5e3b2fSeh146360 #define IPW2200_HC_DISASSOC (2) 588bb5e3b2fSeh146360 #define IPW2200_HC_IBSS_START (3) 589bb5e3b2fSeh146360 #define IPW2200_HC_IBSS_RECONF (4) 590bb5e3b2fSeh146360 #define IPW2200_HC_DISASSOC_QUIET (5) 591bb5e3b2fSeh146360 uint8_t reserved1; 592bb5e3b2fSeh146360 uint16_t policy; 593bb5e3b2fSeh146360 #define IPW2200_POLICY_WME (1) 594bb5e3b2fSeh146360 #define IPW2200_POLICY_WPA (2) 595bb5e3b2fSeh146360 uint8_t plen; 596bb5e3b2fSeh146360 uint8_t mode; 597bb5e3b2fSeh146360 uint8_t bssid[IEEE80211_ADDR_LEN]; 598bb5e3b2fSeh146360 uint8_t tstamp[8]; 599bb5e3b2fSeh146360 600bb5e3b2fSeh146360 uint16_t capinfo; 601bb5e3b2fSeh146360 uint16_t lintval; 602bb5e3b2fSeh146360 uint16_t intval; 603bb5e3b2fSeh146360 uint8_t dst[IEEE80211_ADDR_LEN]; 604bb5e3b2fSeh146360 uint32_t reserved3; 605bb5e3b2fSeh146360 uint16_t reserved4; 606bb5e3b2fSeh146360 }; 607bb5e3b2fSeh146360 608bb5e3b2fSeh146360 #define IPW2200_SCAN_CHANNELS (54) 609bb5e3b2fSeh146360 610bb5e3b2fSeh146360 /* 611bb5e3b2fSeh146360 * structure for command IPW2200_CMD_SCAN 612bb5e3b2fSeh146360 */ 613bb5e3b2fSeh146360 struct ipw2200_scan { 614bb5e3b2fSeh146360 uint8_t type; 615bb5e3b2fSeh146360 #define IPW2200_SCAN_TYPE_PASSIVE_STOP (0) /* passive, stop on first beacon */ 616bb5e3b2fSeh146360 #define IPW2200_SCAN_TYPE_PASSIVE (1) /* passive, full dwell on channel */ 617bb5e3b2fSeh146360 #define IPW2200_SCAN_TYPE_DIRECTED (2) /* active, directed probe seq */ 618bb5e3b2fSeh146360 #define IPW2200_SCAN_TYPE_BROADCAST (3) /* active, bcast probe seq */ 619bb5e3b2fSeh146360 #define IPW2200_SCAN_TYPE_BDIRECTED (4) /* active, directed+bcast probe */ 620bb5e3b2fSeh146360 #define IPW2200_SCAN_TYPES (5) 621bb5e3b2fSeh146360 uint16_t dwelltime; 622bb5e3b2fSeh146360 uint8_t channels[IPW2200_SCAN_CHANNELS]; 623bb5e3b2fSeh146360 #define IPW2200_CHAN_5GHZ (0 << 6) 624bb5e3b2fSeh146360 #define IPW2200_CHAN_2GHZ (1 << 6) 625bb5e3b2fSeh146360 uint8_t reserved[3]; 626bb5e3b2fSeh146360 }; 627bb5e3b2fSeh146360 628bb5e3b2fSeh146360 /* 629bb5e3b2fSeh146360 * structure for command IPW2200_CMD_SCAN_EXT 630bb5e3b2fSeh146360 */ 631bb5e3b2fSeh146360 struct ipw2200_scan_ext { 632bb5e3b2fSeh146360 uint32_t full_scan_index; 633bb5e3b2fSeh146360 uint8_t channels[IPW2200_SCAN_CHANNELS]; 634bb5e3b2fSeh146360 uint8_t scan_type[IPW2200_SCAN_CHANNELS/2]; 635bb5e3b2fSeh146360 uint8_t reserved; 636bb5e3b2fSeh146360 uint16_t dwell_time[IPW2200_SCAN_TYPES]; 637bb5e3b2fSeh146360 }; 638bb5e3b2fSeh146360 639bb5e3b2fSeh146360 /* 640bb5e3b2fSeh146360 * structure for command IPW2200_CMD_SET_CONFIGURATION 641bb5e3b2fSeh146360 */ 642bb5e3b2fSeh146360 struct ipw2200_configuration { 643bb5e3b2fSeh146360 uint8_t bluetooth_coexistence; 644bb5e3b2fSeh146360 uint8_t reserved1; 645bb5e3b2fSeh146360 uint8_t answer_pbreq; 646bb5e3b2fSeh146360 uint8_t allow_invalid_frames; 647bb5e3b2fSeh146360 uint8_t multicast_enabled; 648bb5e3b2fSeh146360 uint8_t drop_unicast_unencrypted; 649bb5e3b2fSeh146360 uint8_t disable_unicast_decryption; 650bb5e3b2fSeh146360 uint8_t drop_multicast_unencrypted; 651bb5e3b2fSeh146360 uint8_t disable_multicast_decryption; 652bb5e3b2fSeh146360 uint8_t antenna; 653bb5e3b2fSeh146360 #define IPW2200_ANTENNA_AUTO (0) /* firmware selects best antenna */ 654bb5e3b2fSeh146360 #define IPW2200_ANTENNA_A (1) /* use antenna A only */ 655bb5e3b2fSeh146360 #define IPW2200_ANTENNA_B (3) /* use antenna B only */ 656bb5e3b2fSeh146360 #define IPW2200_ANTENNA_SLOWDIV (2) /* slow diversity algorithm */ 657bb5e3b2fSeh146360 uint8_t include_crc; 658bb5e3b2fSeh146360 uint8_t use_protection; 659bb5e3b2fSeh146360 uint8_t protection_ctsonly; 660bb5e3b2fSeh146360 uint8_t enable_multicast_filtering; 661bb5e3b2fSeh146360 uint8_t bluetooth_threshold; 662bb5e3b2fSeh146360 uint8_t reserved4; 663bb5e3b2fSeh146360 uint8_t allow_beacon_and_probe_resp; 664bb5e3b2fSeh146360 uint8_t allow_mgt; 665bb5e3b2fSeh146360 uint8_t noise_reported; 666bb5e3b2fSeh146360 uint8_t reserved5; 667bb5e3b2fSeh146360 }; 668bb5e3b2fSeh146360 669bb5e3b2fSeh146360 /* 670bb5e3b2fSeh146360 * structure for command IPW2200_CMD_SET_WEP_KEY 671bb5e3b2fSeh146360 */ 672bb5e3b2fSeh146360 struct ipw2200_wep_key { 673bb5e3b2fSeh146360 uint8_t cmd; 674bb5e3b2fSeh146360 #define IPW2200_WEP_KEY_CMD_SETKEY (0x08) 675bb5e3b2fSeh146360 uint8_t seq; 676bb5e3b2fSeh146360 uint8_t idx; 677bb5e3b2fSeh146360 uint8_t len; 678bb5e3b2fSeh146360 uint8_t key[IEEE80211_KEYBUF_SIZE]; 679bb5e3b2fSeh146360 }; 680bb5e3b2fSeh146360 681bb5e3b2fSeh146360 /* 682bb5e3b2fSeh146360 * the following two structures are for future WME support 683bb5e3b2fSeh146360 */ 684bb5e3b2fSeh146360 struct ipw2200_wme_params { 685bb5e3b2fSeh146360 uint16_t cwmin[WME_NUM_AC]; 686bb5e3b2fSeh146360 uint16_t cwmax[WME_NUM_AC]; 687bb5e3b2fSeh146360 uint8_t aifsn[WME_NUM_AC]; 688bb5e3b2fSeh146360 uint8_t acm[WME_NUM_AC]; 689bb5e3b2fSeh146360 uint16_t burst[WME_NUM_AC]; 690bb5e3b2fSeh146360 }; 691bb5e3b2fSeh146360 692bb5e3b2fSeh146360 struct ipw2200_sensitivity { 693bb5e3b2fSeh146360 uint16_t rssi; 694bb5e3b2fSeh146360 #define IPW2200_RSSI_TO_DBM (112) 695bb5e3b2fSeh146360 uint16_t reserved; 696bb5e3b2fSeh146360 }; 697bb5e3b2fSeh146360 698bb5e3b2fSeh146360 #pragma pack() 699bb5e3b2fSeh146360 700bb5e3b2fSeh146360 /* 701bb5e3b2fSeh146360 * ROM entries 702bb5e3b2fSeh146360 */ 703bb5e3b2fSeh146360 #define IPW2200_EEPROM_MAC (0x21) 704bb5e3b2fSeh146360 #define IPW2200_EEPROM_NIC (0x25) /* nic type (lsb) */ 705bb5e3b2fSeh146360 #define IPW2200_EEPROM_SKU (0x25) /* nic type (msb) */ 706bb5e3b2fSeh146360 707bb5e3b2fSeh146360 /* 708bb5e3b2fSeh146360 * EVENT controls 709bb5e3b2fSeh146360 */ 710bb5e3b2fSeh146360 #define IPW2200_IMEM_EVENT_CTL (0x00300004) 711bb5e3b2fSeh146360 /* 712bb5e3b2fSeh146360 * EEPROM controls 713bb5e3b2fSeh146360 */ 714bb5e3b2fSeh146360 #define IPW2200_IMEM_EEPROM_CTL (0x00300040) 715bb5e3b2fSeh146360 716bb5e3b2fSeh146360 #define IPW2200_EEPROM_DELAY (1) /* minimum hold time(microsecond) */ 717bb5e3b2fSeh146360 718bb5e3b2fSeh146360 /* 719bb5e3b2fSeh146360 * possible flags for register IWI_MEM_EVENT 720bb5e3b2fSeh146360 */ 721bb5e3b2fSeh146360 #define IPW2200_LED_ASSOC (1 << 5) 722bb5e3b2fSeh146360 #define IPW2200_LED_MASK (0xd9fffffb) 723bb5e3b2fSeh146360 724bb5e3b2fSeh146360 /* 725bb5e3b2fSeh146360 * control and status registers access macros 726bb5e3b2fSeh146360 */ 727bb5e3b2fSeh146360 extern uint8_t ipw2200_csr_get8(struct ipw2200_softc *sc, uint32_t off); 728bb5e3b2fSeh146360 extern uint16_t ipw2200_csr_get16(struct ipw2200_softc *sc, uint32_t off); 729bb5e3b2fSeh146360 extern uint32_t ipw2200_csr_get32(struct ipw2200_softc *sc, uint32_t off); 730bb5e3b2fSeh146360 extern void ipw2200_csr_getbuf32(struct ipw2200_softc *sc, uint32_t off, 731bb5e3b2fSeh146360 uint32_t *buf, size_t cnt); 732bb5e3b2fSeh146360 extern void ipw2200_csr_put8(struct ipw2200_softc *sc, uint32_t off, 733bb5e3b2fSeh146360 uint8_t val); 734bb5e3b2fSeh146360 extern void ipw2200_csr_put16(struct ipw2200_softc *sc, uint32_t off, 735bb5e3b2fSeh146360 uint16_t val); 736bb5e3b2fSeh146360 extern void ipw2200_csr_put32(struct ipw2200_softc *sc, uint32_t off, 737bb5e3b2fSeh146360 uint32_t val); 738bb5e3b2fSeh146360 /* 739bb5e3b2fSeh146360 * indirect memory space access macros 740bb5e3b2fSeh146360 */ 741bb5e3b2fSeh146360 extern uint8_t ipw2200_imem_get8(struct ipw2200_softc *sc, uint32_t addr); 742bb5e3b2fSeh146360 extern uint16_t ipw2200_imem_get16(struct ipw2200_softc *sc, 743bb5e3b2fSeh146360 uint32_t addr); 744bb5e3b2fSeh146360 extern uint32_t ipw2200_imem_get32(struct ipw2200_softc *sc, 745bb5e3b2fSeh146360 uint32_t addr); 746bb5e3b2fSeh146360 extern void ipw2200_imem_put8(struct ipw2200_softc *sc, uint32_t addr, 747bb5e3b2fSeh146360 uint8_t val); 748bb5e3b2fSeh146360 extern void ipw2200_imem_put16(struct ipw2200_softc *sc, uint32_t addr, 749bb5e3b2fSeh146360 uint16_t val); 750bb5e3b2fSeh146360 extern void ipw2200_imem_put32(struct ipw2200_softc *sc, uint32_t addr, 751bb5e3b2fSeh146360 uint32_t val); 752bb5e3b2fSeh146360 /* 753bb5e3b2fSeh146360 * EEPROM access macro 754bb5e3b2fSeh146360 */ 755bb5e3b2fSeh146360 extern void ipw2200_rom_control(struct ipw2200_softc *sc, uint32_t val); 756bb5e3b2fSeh146360 extern uint16_t ipw2200_rom_get16(struct ipw2200_softc *sc, uint8_t addr); 757bb5e3b2fSeh146360 758bb5e3b2fSeh146360 /* 759bb5e3b2fSeh146360 * Firmware related definations and interfaces. 760bb5e3b2fSeh146360 */ 761bb5e3b2fSeh146360 extern int ipw2200_cache_firmware(struct ipw2200_softc *sc); 762bb5e3b2fSeh146360 extern int ipw2200_free_firmware(struct ipw2200_softc *sc); 763bb5e3b2fSeh146360 extern int ipw2200_load_uc(struct ipw2200_softc *sc, uint8_t *buf, size_t size); 764bb5e3b2fSeh146360 extern int ipw2200_load_fw(struct ipw2200_softc *sc, uint8_t *buf, size_t size); 765bb5e3b2fSeh146360 766bb5e3b2fSeh146360 #ifdef __cplusplus 767bb5e3b2fSeh146360 } 768bb5e3b2fSeh146360 #endif 769bb5e3b2fSeh146360 770bb5e3b2fSeh146360 #endif /* _SYS_IPW2200_IMPL_H */ 771