1 /* 2 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 /* 7 * Copyright (c) 2009, Intel Corporation 8 * All rights reserved. 9 */ 10 11 /* 12 * Sun elects to use this software under the BSD license. 13 */ 14 15 /* 16 * This file is provided under a dual BSD/GPLv2 license. When using or 17 * redistributing this file, you may do so under either license. 18 * 19 * GPL LICENSE SUMMARY 20 * 21 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. 22 * 23 * This program is free software; you can redistribute it and/or modify 24 * it under the terms of version 2 of the GNU General Public License as 25 * published by the Free Software Foundation. 26 * 27 * This program is distributed in the hope that it will be useful, but 28 * WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 30 * General Public License for more details. 31 * 32 * You should have received a copy of the GNU General Public License 33 * along with this program; if not, write to the Free Software 34 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 35 * USA 36 * 37 * The full GNU General Public License is included in this distribution 38 * in the file called LICENSE.GPL. 39 * 40 * Contact Information: 41 * James P. Ketrenos <ipw2100-admin@linux.intel.com> 42 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 43 * 44 * BSD LICENSE 45 * 46 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved. 47 * All rights reserved. 48 * 49 * Redistribution and use in source and binary forms, with or without 50 * modification, are permitted provided that the following conditions 51 * are met: 52 * 53 * * Redistributions of source code must retain the above copyright 54 * notice, this list of conditions and the following disclaimer. 55 * * Redistributions in binary form must reproduce the above copyright 56 * notice, this list of conditions and the following disclaimer in 57 * the documentation and/or other materials provided with the 58 * distribution. 59 * * Neither the name Intel Corporation nor the names of its 60 * contributors may be used to endorse or promote products derived 61 * from this software without specific prior written permission. 62 * 63 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 64 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 65 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 66 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 67 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 68 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 69 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 70 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 71 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 72 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 73 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 74 */ 75 76 #ifndef _IWH_EEPROM_H_ 77 #define _IWH_EEPROM_H_ 78 79 /* 80 * This file defines EEPROM related constants, enums, and inline functions. 81 */ 82 83 /* 84 * EEPROM field values 85 */ 86 #define ANTENNA_SWITCH_NORMAL 0 87 #define ANTENNA_SWITCH_INVERSE 1 88 89 enum { 90 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */ 91 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */ 92 /* Bit 2 Reserved */ 93 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */ 94 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */ 95 EEPROM_CHANNEL_WIDE = (1 << 5), 96 EEPROM_CHANNEL_NARROW = (1 << 6), 97 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */ 98 }; 99 100 /* 101 * EEPROM field lengths 102 */ 103 #define EEPROM_BOARD_PBA_NUMBER_LENGTH 11 104 105 /* 106 * EEPROM field lengths 107 */ 108 #define EEPROM_BOARD_PBA_NUMBER_LENGTH 11 109 #define EEPROM_REGULATORY_SKU_ID_LENGTH 4 110 #define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14 111 #define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13 112 #define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12 113 #define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11 114 #define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6 115 116 117 #define EEPROM_REGULATORY_NUMBER_OF_BANDS 5 118 119 /* 120 * SKU Capabilities 121 */ 122 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0) 123 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1) 124 #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7) 125 126 /* 127 * *regulatory* channel data from eeprom, one for each channel 128 */ 129 struct iwl_eeprom_channel { 130 uint8_t flags; /* flags copied from EEPROM */ 131 int8_t max_power_avg; /* max power (dBm) on this chnl, limit 31 */ 132 }; 133 134 /* 135 * Mapping of a Tx power level, at factory calibration temperature, 136 * to a radio/DSP gain table index. 137 * One for each of 5 "sample" power levels in each band. 138 * v_det is measured at the factory, using the 3945's built-in power amplifier 139 * (PA) output voltage detector. This same detector is used during Tx of 140 * long packets in normal operation to provide feedback as to proper output 141 * level. 142 * Data copied from EEPROM. 143 */ 144 struct iwl_eeprom_txpower_sample { 145 uint8_t gain_index; /* index into power (gain) setup table ... */ 146 int8_t power; /* ... for this pwr level for this chnl group */ 147 uint16_t v_det; /* PA output voltage */ 148 }; 149 150 /* 151 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes. 152 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A). 153 * Tx power setup code interpolates between the 5 "sample" power levels 154 * to determine the nominal setup for a requested power level. 155 * Data copied from EEPROM. 156 * DO NOT ALTER THIS STRUCTURE!!! 157 */ 158 struct iwl_eeprom_txpower_group { 159 /* 5 power levels */ 160 struct iwl_eeprom_txpower_sample samples[5]; 161 /* coefficients for voltage->power formula (signed) */ 162 uint32_t a, b, c, d, e; 163 /* these modify coeffs based on frequency (signed) */ 164 uint32_t Fa, Fb, Fc, Fd, Fe; 165 /* highest power possible by h/w in this * band */ 166 int8_t saturation_power; 167 /* "representative" channel # in this band */ 168 uint8_t group_channel; 169 /* h/w temperature at factory calib this band (signed) */ 170 uint16_t temperature; 171 }; 172 173 /* 174 * Temperature-based Tx-power compensation data, not band-specific. 175 * These coefficients are use to modify a/b/c/d/e coeffs based on 176 * difference between current temperature and factory calib temperature. 177 * Data copied from EEPROM. 178 */ 179 struct iwl_eeprom_temperature_corr { 180 uint32_t Ta; 181 uint32_t Tb; 182 uint32_t Tc; 183 uint32_t Td; 184 uint32_t Te; 185 }; 186 187 188 /* 189 * eeprom map 190 */ 191 #define EEP_MAC_ADDRESS 42 /* chipset's MAC address 6 bytes */ 192 #define EEP_VERSION 136 /* eeprom version 2 bytes */ 193 #define EEP_SP_RADIO_CONFIGURATION 144 /* SP's radio configuration */ 194 195 196 197 #define CSR_EEPROM_REG (CSR_BASE+0x02c) 198 #define CSR_EEPROM_GP (CSR_BASE+0x030) 199 #define CSR_EEPROM_GP_VALID_MSK 0x00000006 200 #define CSR_EEPROM_GP_BAD_SIGNATURE 0x00000000 201 #define IWH_SP_EEPROM_SIZE 2048 202 203 #define IWH_READ_EEP_SHORT(sc, addr) ((((uint16_t)sc->sc_eep_map[addr + 1])\ 204 << 8) |\ 205 ((uint16_t)sc->sc_eep_map[addr])) 206 207 #define SP_RADIO_TYPE_3x3 (0) 208 #define SP_RADIO_TYPE_2x2 (1) 209 #define SP_RADIO_TYPE_1x2 (2) 210 #define SP_RADIO_TYPE_MAX (3) 211 212 #define SP_RADIO_TYPE_MSK(x) (x & 3) 213 #define SP_RADIO_STEP_MSK(x) ((x>>2) & 3) 214 #define SP_RADIO_DASH_MSK(x) ((x>>4) & 3) 215 #define SP_RADIO_PNUM_MSK(x) ((x>>6) & 3) 216 #define SP_RADIO_TX_CHAIN_MSK(x) ((x>>8) & 0xf) 217 #define SP_RADIO_RX_CHAIN_MSK(x) ((x>>12) & 0xf) 218 219 #define ADDRESS_MSK 0x0000ffff 220 #define INDIRECT_TYPE_MSK 0x000f0000 221 #define INDIRECT_HOST 0x00010000 222 #define INDIRECT_GENERAL 0x00020000 223 #define INDIRECT_REGULATORY 0x00030000 224 #define INDIRECT_CALIBRATION 0x00040000 225 #define INDIRECT_PROCESS_ADJST 0x00050000 226 #define INDIRECT_OTHERS 0x00060000 227 #define INDIRECT_ADDRESS 0x00100000 228 229 #define EEP_LINK_HOST (200) 230 #define EEP_LINK_GENERAL (202) 231 #define EEP_LINK_REGULATORY (204) 232 #define EEP_LINK_CALIBRATION (206) 233 #define EEP_LINK_PROCESS_ADJST (208) 234 #define EEP_LINK_OTHERS (210) 235 236 #define EEP_CALIBRATION ((0x00) | INDIRECT_ADDRESS |\ 237 INDIRECT_CALIBRATION) 238 239 #define EEP_TX_POWER_TX_CHAINS (3) 240 #define EEP_RXIQ_CAL_CHANNELS (7) 241 #define EEP_CAL_CHANNEL_GROUP (7) 242 #define EEP_RXIQ_DRIVER_MODES (12) 243 244 245 246 #endif /* _IWH_EEPROM_H_ */ 247