1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _IGB_SW_H 30 #define _IGB_SW_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strsun.h> 42 #include <sys/strlog.h> 43 #include <sys/kmem.h> 44 #include <sys/stat.h> 45 #include <sys/kstat.h> 46 #include <sys/modctl.h> 47 #include <sys/errno.h> 48 #include <sys/dlpi.h> 49 #include <sys/mac_provider.h> 50 #include <sys/mac_ether.h> 51 #include <sys/vlan.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/pci.h> 55 #include <sys/pcie.h> 56 #include <sys/sdt.h> 57 #include <sys/ethernet.h> 58 #include <sys/pattr.h> 59 #include <sys/strsubr.h> 60 #include <sys/netlb.h> 61 #include <sys/random.h> 62 #include <inet/common.h> 63 #include <inet/tcp.h> 64 #include <inet/ip.h> 65 #include <inet/mi.h> 66 #include <inet/nd.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/fm/io/ddi.h> 71 #include "igb_api.h" 72 #include "igb_82575.h" 73 74 75 #define MODULE_NAME "igb" /* module name */ 76 77 #define IGB_SUCCESS DDI_SUCCESS 78 #define IGB_FAILURE DDI_FAILURE 79 80 #define IGB_UNKNOWN 0x00 81 #define IGB_INITIALIZED 0x01 82 #define IGB_STARTED 0x02 83 #define IGB_SUSPENDED 0x04 84 #define IGB_STALL 0x08 85 #define IGB_ERROR 0x80 86 87 #define IGB_RX_STOPPED 0x1 88 89 #define IGB_INTR_NONE 0 90 #define IGB_INTR_MSIX 1 91 #define IGB_INTR_MSI 2 92 #define IGB_INTR_LEGACY 3 93 94 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 95 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 96 97 #define IGB_NO_POLL -1 98 #define IGB_NO_FREE_SLOT -1 99 100 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 101 #define MCAST_ALLOC_COUNT 256 102 #define MAX_COOKIE 18 103 #define MIN_NUM_TX_DESC 2 104 105 /* 106 * Number of settings for interrupt throttle rate (ITR). There is one of 107 * these per msi-x vector and it needs to be the maximum of all silicon 108 * types supported by this driver. 109 */ 110 #define MAX_NUM_EITR 25 111 112 /* 113 * Maximum values for user configurable parameters 114 */ 115 #define MAX_TX_RING_SIZE 4096 116 #define MAX_RX_RING_SIZE 4096 117 #define MAX_RX_GROUP_NUM 4 118 119 #define MAX_MTU 9000 120 #define MAX_RX_LIMIT_PER_INTR 4096 121 122 #define MAX_RX_COPY_THRESHOLD 9216 123 #define MAX_TX_COPY_THRESHOLD 9216 124 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 125 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 126 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 127 #define MAX_MCAST_NUM 8192 128 129 /* 130 * Minimum values for user configurable parameters 131 */ 132 #define MIN_TX_RING_SIZE 64 133 #define MIN_RX_RING_SIZE 64 134 #define MIN_RX_GROUP_NUM 1 135 136 #define MIN_MTU ETHERMIN 137 #define MIN_RX_LIMIT_PER_INTR 16 138 139 #define MIN_RX_COPY_THRESHOLD 0 140 #define MIN_TX_COPY_THRESHOLD 0 141 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 142 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 143 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 144 #define MIN_MCAST_NUM 8 145 146 /* 147 * Default values for user configurable parameters 148 */ 149 #define DEFAULT_TX_RING_SIZE 512 150 #define DEFAULT_RX_RING_SIZE 512 151 #define DEFAULT_RX_GROUP_NUM 1 152 153 #define DEFAULT_MTU ETHERMTU 154 #define DEFAULT_RX_LIMIT_PER_INTR 256 155 156 #define DEFAULT_RX_COPY_THRESHOLD 128 157 #define DEFAULT_TX_COPY_THRESHOLD 512 158 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 159 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 160 #define DEFAULT_TX_RESCHED_THRESHOLD 128 161 #define DEFAULT_MCAST_NUM 4096 162 163 #define IGB_LSO_MAXLEN 65535 164 165 #define TX_DRAIN_TIME 200 166 #define RX_DRAIN_TIME 200 167 168 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 169 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 170 171 /* 172 * Defined for IP header alignment. 173 */ 174 #define IPHDR_ALIGN_ROOM 2 175 176 /* 177 * Bit flags for attach_progress 178 */ 179 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 180 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 181 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 182 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 183 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 184 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 185 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 186 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 187 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 188 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 189 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 190 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 191 192 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 193 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 194 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 195 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 196 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 197 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 198 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 199 #define PROP_DEFAULT_MTU "default_mtu" 200 #define PROP_FLOW_CONTROL "flow_control" 201 #define PROP_TX_RING_SIZE "tx_ring_size" 202 #define PROP_RX_RING_SIZE "rx_ring_size" 203 #define PROP_MR_ENABLE "mr_enable" 204 #define PROP_RX_GROUP_NUM "rx_group_number" 205 206 #define PROP_INTR_FORCE "intr_force" 207 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 208 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 209 #define PROP_LSO_ENABLE "lso_enable" 210 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 211 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 212 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 213 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 214 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 215 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 216 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 217 #define PROP_INTR_THROTTLING "intr_throttling" 218 #define PROP_MCAST_MAX_NUM "mcast_max_num" 219 220 #define IGB_LB_NONE 0 221 #define IGB_LB_EXTERNAL 1 222 #define IGB_LB_INTERNAL_PHY 3 223 #define IGB_LB_INTERNAL_SERDES 4 224 225 enum ioc_reply { 226 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 227 IOC_DONE, /* OK, reply sent */ 228 IOC_ACK, /* OK, just send ACK */ 229 IOC_REPLY /* OK, just send reply */ 230 }; 231 232 /* 233 * For s/w context extraction from a tx frame 234 */ 235 #define TX_CXT_SUCCESS 0 236 #define TX_CXT_E_LSO_CSUM (-1) 237 #define TX_CXT_E_ETHER_TYPE (-2) 238 239 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 240 0, 0, (flag))) 241 242 /* 243 * Defined for ring index operations 244 * ASSERT(index < limit) 245 * ASSERT(step < limit) 246 * ASSERT(index1 < limit) 247 * ASSERT(index2 < limit) 248 */ 249 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 250 (index) + (step) : (index) + (step) - (limit)) 251 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 252 (index) - (step) : (index) + (limit) - (step)) 253 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 254 (index2) - (index1) : (index2) + (limit) - (index1)) 255 256 #define LINK_LIST_INIT(_LH) \ 257 (_LH)->head = (_LH)->tail = NULL 258 259 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 260 261 #define LIST_POP_HEAD(_LH) \ 262 (single_link_t *)(_LH)->head; \ 263 { \ 264 if ((_LH)->head != NULL) { \ 265 (_LH)->head = (_LH)->head->link; \ 266 if ((_LH)->head == NULL) \ 267 (_LH)->tail = NULL; \ 268 } \ 269 } 270 271 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 272 273 #define LIST_PUSH_TAIL(_LH, _E) \ 274 if ((_LH)->tail != NULL) { \ 275 (_LH)->tail->link = (single_link_t *)(_E); \ 276 (_LH)->tail = (single_link_t *)(_E); \ 277 } else { \ 278 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 279 } \ 280 (_E)->link = NULL; 281 282 #define LIST_GET_NEXT(_LH, _E) \ 283 (((_LH)->tail == (single_link_t *)(_E)) ? \ 284 NULL : ((single_link_t *)(_E))->link) 285 286 287 typedef struct single_link { 288 struct single_link *link; 289 } single_link_t; 290 291 typedef struct link_list { 292 single_link_t *head; 293 single_link_t *tail; 294 } link_list_t; 295 296 /* 297 * Property lookups 298 */ 299 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 300 DDI_PROP_DONTPASS, (n)) 301 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 302 DDI_PROP_DONTPASS, (n), -1) 303 304 305 /* capability/feature flags */ 306 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 307 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 308 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 309 310 /* function pointer for nic-specific functions */ 311 typedef void (*igb_nic_func_t)(struct igb *); 312 313 /* adapter-specific info for each supported device type */ 314 typedef struct adapter_info { 315 /* limits */ 316 uint32_t max_rx_que_num; /* maximum number of rx queues */ 317 uint32_t min_rx_que_num; /* minimum number of rx queues */ 318 uint32_t def_rx_que_num; /* default number of rx queues */ 319 uint32_t max_tx_que_num; /* maximum number of tx queues */ 320 uint32_t min_tx_que_num; /* minimum number of tx queues */ 321 uint32_t def_tx_que_num; /* default number of tx queues */ 322 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 323 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 324 uint32_t def_intr_throttle; /* default interrupt throttle */ 325 /* function pointers */ 326 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 327 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 328 /* capabilities */ 329 uint32_t flags; /* capability flags */ 330 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 331 } adapter_info_t; 332 333 typedef union igb_ether_addr { 334 struct { 335 uint32_t high; 336 uint32_t low; 337 } reg; 338 struct { 339 uint8_t set; 340 uint8_t group_index; 341 uint8_t addr[ETHERADDRL]; 342 } mac; 343 } igb_ether_addr_t; 344 345 typedef enum { 346 USE_NONE, 347 USE_COPY, 348 USE_DMA 349 } tx_type_t; 350 351 typedef struct tx_context { 352 uint32_t hcksum_flags; 353 uint32_t ip_hdr_len; 354 uint32_t mac_hdr_len; 355 uint32_t l4_proto; 356 uint32_t mss; 357 uint32_t l4_hdr_len; 358 boolean_t lso_flag; 359 } tx_context_t; 360 361 /* Hold address/length of each DMA segment */ 362 typedef struct sw_desc { 363 uint64_t address; 364 size_t length; 365 } sw_desc_t; 366 367 /* Handles and addresses of DMA buffer */ 368 typedef struct dma_buffer { 369 caddr_t address; /* Virtual address */ 370 uint64_t dma_address; /* DMA (Hardware) address */ 371 ddi_acc_handle_t acc_handle; /* Data access handle */ 372 ddi_dma_handle_t dma_handle; /* DMA handle */ 373 size_t size; /* Buffer size */ 374 size_t len; /* Data length in the buffer */ 375 } dma_buffer_t; 376 377 /* 378 * Tx Control Block 379 */ 380 typedef struct tx_control_block { 381 single_link_t link; 382 uint32_t frag_num; 383 uint32_t desc_num; 384 mblk_t *mp; 385 tx_type_t tx_type; 386 ddi_dma_handle_t tx_dma_handle; 387 dma_buffer_t tx_buf; 388 sw_desc_t desc[MAX_COOKIE]; 389 } tx_control_block_t; 390 391 /* 392 * RX Control Block 393 */ 394 typedef struct rx_control_block { 395 mblk_t *mp; 396 uint32_t ref_cnt; 397 dma_buffer_t rx_buf; 398 frtn_t free_rtn; 399 struct igb_rx_data *rx_data; 400 } rx_control_block_t; 401 402 /* 403 * Software Data Structure for Tx Ring 404 */ 405 typedef struct igb_tx_ring { 406 uint32_t index; /* Ring index */ 407 uint32_t intr_vector; /* Interrupt vector index */ 408 409 /* 410 * Mutexes 411 */ 412 kmutex_t tx_lock; 413 kmutex_t recycle_lock; 414 kmutex_t tcb_head_lock; 415 kmutex_t tcb_tail_lock; 416 417 /* 418 * Tx descriptor ring definitions 419 */ 420 dma_buffer_t tbd_area; 421 union e1000_adv_tx_desc *tbd_ring; 422 uint32_t tbd_head; /* Index of next tbd to recycle */ 423 uint32_t tbd_tail; /* Index of next tbd to transmit */ 424 uint32_t tbd_free; /* Number of free tbd */ 425 426 /* 427 * Tx control block list definitions 428 */ 429 tx_control_block_t *tcb_area; 430 tx_control_block_t **work_list; 431 tx_control_block_t **free_list; 432 uint32_t tcb_head; /* Head index of free list */ 433 uint32_t tcb_tail; /* Tail index of free list */ 434 uint32_t tcb_free; /* Number of free tcb in free list */ 435 436 uint32_t *tbd_head_wb; /* Head write-back */ 437 uint32_t (*tx_recycle)(struct igb_tx_ring *); 438 439 /* 440 * s/w context structure for TCP/UDP checksum offload and LSO. 441 */ 442 tx_context_t tx_context; 443 444 /* 445 * Tx ring settings and status 446 */ 447 uint32_t ring_size; /* Tx descriptor ring size */ 448 uint32_t free_list_size; /* Tx free list size */ 449 450 boolean_t reschedule; 451 uint32_t recycle_fail; 452 uint32_t stall_watchdog; 453 454 #ifdef IGB_DEBUG 455 /* 456 * Debug statistics 457 */ 458 uint32_t stat_overload; 459 uint32_t stat_fail_no_tbd; 460 uint32_t stat_fail_no_tcb; 461 uint32_t stat_fail_dma_bind; 462 uint32_t stat_reschedule; 463 uint32_t stat_pkt_cnt; 464 #endif 465 466 /* 467 * Pointer to the igb struct 468 */ 469 struct igb *igb; 470 mac_ring_handle_t ring_handle; /* call back ring handle */ 471 } igb_tx_ring_t; 472 473 /* 474 * Software Receive Ring 475 */ 476 typedef struct igb_rx_data { 477 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 478 479 /* 480 * Rx descriptor ring definitions 481 */ 482 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 483 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 484 uint32_t rbd_next; /* Index of next rx desc */ 485 486 /* 487 * Rx control block list definitions 488 */ 489 rx_control_block_t *rcb_area; 490 rx_control_block_t **work_list; /* Work list of rcbs */ 491 rx_control_block_t **free_list; /* Free list of rcbs */ 492 uint32_t rcb_head; /* Index of next free rcb */ 493 uint32_t rcb_tail; /* Index to put recycled rcb */ 494 uint32_t rcb_free; /* Number of free rcbs */ 495 496 /* 497 * Rx sw ring settings and status 498 */ 499 uint32_t ring_size; /* Rx descriptor ring size */ 500 uint32_t free_list_size; /* Rx free list size */ 501 502 uint32_t rcb_pending; 503 uint32_t flag; 504 505 struct igb_rx_ring *rx_ring; /* Pointer to rx ring */ 506 } igb_rx_data_t; 507 508 /* 509 * Software Data Structure for Rx Ring 510 */ 511 typedef struct igb_rx_ring { 512 uint32_t index; /* Ring index */ 513 uint32_t intr_vector; /* Interrupt vector index */ 514 515 igb_rx_data_t *rx_data; /* Rx software ring */ 516 517 kmutex_t rx_lock; /* Rx access lock */ 518 519 #ifdef IGB_DEBUG 520 /* 521 * Debug statistics 522 */ 523 uint32_t stat_frame_error; 524 uint32_t stat_cksum_error; 525 uint32_t stat_exceed_pkt; 526 uint32_t stat_pkt_cnt; 527 #endif 528 529 struct igb *igb; /* Pointer to igb struct */ 530 mac_ring_handle_t ring_handle; /* call back ring handle */ 531 uint32_t group_index; /* group index */ 532 uint64_t ring_gen_num; 533 } igb_rx_ring_t; 534 535 /* 536 * Software Receive Ring Group 537 */ 538 typedef struct igb_rx_group { 539 uint32_t index; /* Group index */ 540 mac_group_handle_t group_handle; /* call back group handle */ 541 struct igb *igb; /* Pointer to igb struct */ 542 } igb_rx_group_t; 543 544 typedef struct igb { 545 int instance; 546 mac_handle_t mac_hdl; 547 dev_info_t *dip; 548 struct e1000_hw hw; 549 struct igb_osdep osdep; 550 551 adapter_info_t *capab; /* adapter capabilities */ 552 553 uint32_t igb_state; 554 link_state_t link_state; 555 uint32_t link_speed; 556 uint32_t link_duplex; 557 uint32_t link_down_timeout; 558 boolean_t link_complete; 559 timeout_id_t link_tid; 560 561 uint32_t reset_count; 562 uint32_t attach_progress; 563 uint32_t loopback_mode; 564 uint32_t default_mtu; 565 uint32_t max_frame_size; 566 uint32_t dout_sync; 567 568 uint32_t rcb_pending; 569 570 uint32_t mr_enable; /* Enable multiple rings */ 571 uint32_t vmdq_mode; /* Mode of VMDq */ 572 573 /* 574 * Receive Rings and Groups 575 */ 576 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 577 uint32_t num_rx_rings; /* Number of rx rings in use */ 578 uint32_t rx_ring_size; /* Rx descriptor ring size */ 579 uint32_t rx_buf_size; /* Rx buffer size */ 580 igb_rx_group_t *rx_groups; /* Array of rx groups */ 581 uint32_t num_rx_groups; /* Number of rx groups in use */ 582 583 /* 584 * Transmit Rings 585 */ 586 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 587 uint32_t num_tx_rings; /* Number of tx rings in use */ 588 uint32_t tx_ring_size; /* Tx descriptor ring size */ 589 uint32_t tx_buf_size; /* Tx buffer size */ 590 591 boolean_t tx_ring_init; 592 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 593 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 594 boolean_t lso_enable; /* Large Segment Offload */ 595 uint32_t tx_copy_thresh; /* Tx copy threshold */ 596 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 597 uint32_t tx_overload_thresh; /* Tx overload threshold */ 598 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 599 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 600 uint32_t rx_copy_thresh; /* Rx copy threshold */ 601 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 602 603 uint32_t intr_throttling[MAX_NUM_EITR]; 604 uint32_t intr_force; 605 606 int intr_type; 607 int intr_cnt; 608 int intr_cap; 609 size_t intr_size; 610 uint_t intr_pri; 611 ddi_intr_handle_t *htable; 612 uint32_t eims_mask; 613 uint32_t ims_mask; 614 615 kmutex_t gen_lock; /* General lock for device access */ 616 kmutex_t watchdog_lock; 617 kmutex_t link_lock; 618 kmutex_t rx_pending_lock; 619 620 boolean_t watchdog_enable; 621 boolean_t watchdog_start; 622 timeout_id_t watchdog_tid; 623 624 boolean_t unicst_init; 625 uint32_t unicst_avail; 626 uint32_t unicst_total; 627 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 628 uint32_t mcast_count; 629 uint32_t mcast_alloc_count; 630 uint32_t mcast_max_num; 631 struct ether_addr *mcast_table; 632 633 /* 634 * Kstat definitions 635 */ 636 kstat_t *igb_ks; 637 638 uint32_t param_en_1000fdx_cap:1, 639 param_en_1000hdx_cap:1, 640 param_en_100t4_cap:1, 641 param_en_100fdx_cap:1, 642 param_en_100hdx_cap:1, 643 param_en_10fdx_cap:1, 644 param_en_10hdx_cap:1, 645 param_1000fdx_cap:1, 646 param_1000hdx_cap:1, 647 param_100t4_cap:1, 648 param_100fdx_cap:1, 649 param_100hdx_cap:1, 650 param_10fdx_cap:1, 651 param_10hdx_cap:1, 652 param_autoneg_cap:1, 653 param_pause_cap:1, 654 param_asym_pause_cap:1, 655 param_rem_fault:1, 656 param_adv_1000fdx_cap:1, 657 param_adv_1000hdx_cap:1, 658 param_adv_100t4_cap:1, 659 param_adv_100fdx_cap:1, 660 param_adv_100hdx_cap:1, 661 param_adv_10fdx_cap:1, 662 param_adv_10hdx_cap:1, 663 param_adv_autoneg_cap:1, 664 param_adv_pause_cap:1, 665 param_adv_asym_pause_cap:1, 666 param_adv_rem_fault:1, 667 param_lp_1000fdx_cap:1, 668 param_lp_1000hdx_cap:1, 669 param_lp_100t4_cap:1; 670 671 uint32_t param_lp_100fdx_cap:1, 672 param_lp_100hdx_cap:1, 673 param_lp_10fdx_cap:1, 674 param_lp_10hdx_cap:1, 675 param_lp_autoneg_cap:1, 676 param_lp_pause_cap:1, 677 param_lp_asym_pause_cap:1, 678 param_lp_rem_fault:1, 679 param_pad_to_32:24; 680 681 /* 682 * FMA capabilities 683 */ 684 int fm_capabilities; 685 686 ulong_t page_size; 687 } igb_t; 688 689 typedef struct igb_stat { 690 691 kstat_named_t link_speed; /* Link Speed */ 692 kstat_named_t reset_count; /* Reset Count */ 693 kstat_named_t dout_sync; /* DMA out of sync */ 694 #ifdef IGB_DEBUG 695 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 696 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 697 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 698 699 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 700 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 701 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 702 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 703 kstat_named_t tx_reschedule; /* Tx Reschedule */ 704 705 kstat_named_t gprc; /* Good Packets Received Count */ 706 kstat_named_t gptc; /* Good Packets Xmitted Count */ 707 kstat_named_t gor; /* Good Octets Received Count */ 708 kstat_named_t got; /* Good Octets Xmitd Count */ 709 kstat_named_t prc64; /* Packets Received - 64b */ 710 kstat_named_t prc127; /* Packets Received - 65-127b */ 711 kstat_named_t prc255; /* Packets Received - 127-255b */ 712 kstat_named_t prc511; /* Packets Received - 256-511b */ 713 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 714 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 715 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 716 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 717 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 718 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 719 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 720 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 721 #endif 722 kstat_named_t crcerrs; /* CRC Error Count */ 723 kstat_named_t symerrs; /* Symbol Error Count */ 724 kstat_named_t mpc; /* Missed Packet Count */ 725 kstat_named_t scc; /* Single Collision Count */ 726 kstat_named_t ecol; /* Excessive Collision Count */ 727 kstat_named_t mcc; /* Multiple Collision Count */ 728 kstat_named_t latecol; /* Late Collision Count */ 729 kstat_named_t colc; /* Collision Count */ 730 kstat_named_t dc; /* Defer Count */ 731 kstat_named_t sec; /* Sequence Error Count */ 732 kstat_named_t rlec; /* Receive Length Error Count */ 733 kstat_named_t xonrxc; /* XON Received Count */ 734 kstat_named_t xontxc; /* XON Xmitted Count */ 735 kstat_named_t xoffrxc; /* XOFF Received Count */ 736 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 737 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 738 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 739 kstat_named_t mprc; /* Multicast Pkts Received Count */ 740 kstat_named_t rnbc; /* Receive No Buffers Count */ 741 kstat_named_t ruc; /* Receive Undersize Count */ 742 kstat_named_t rfc; /* Receive Frag Count */ 743 kstat_named_t roc; /* Receive Oversize Count */ 744 kstat_named_t rjc; /* Receive Jabber Count */ 745 kstat_named_t tor; /* Total Octets Recvd Count */ 746 kstat_named_t tot; /* Total Octets Xmted Count */ 747 kstat_named_t tpr; /* Total Packets Received */ 748 kstat_named_t tpt; /* Total Packets Xmitted */ 749 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 750 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 751 kstat_named_t algnerrc; /* Alignment Error count */ 752 kstat_named_t rxerrc; /* Rx Error Count */ 753 kstat_named_t tncrs; /* Transmit with no CRS */ 754 kstat_named_t cexterr; /* Carrier Extension Error count */ 755 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 756 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 757 } igb_stat_t; 758 759 /* 760 * Function prototypes in e1000_osdep.c 761 */ 762 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 763 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 764 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 765 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 766 void e1000_rar_clear(struct e1000_hw *, uint32_t); 767 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 768 uint32_t, uint8_t); 769 770 /* 771 * Function prototypes in igb_buf.c 772 */ 773 int igb_alloc_dma(igb_t *); 774 void igb_free_dma(igb_t *); 775 void igb_free_dma_buffer(dma_buffer_t *); 776 int igb_alloc_rx_ring_data(igb_rx_ring_t *rx_ring); 777 void igb_free_rx_ring_data(igb_rx_data_t *rx_data); 778 779 /* 780 * Function prototypes in igb_main.c 781 */ 782 int igb_start(igb_t *, boolean_t); 783 void igb_stop(igb_t *, boolean_t); 784 int igb_setup_link(igb_t *, boolean_t); 785 int igb_unicst_find(igb_t *, const uint8_t *); 786 int igb_unicst_set(igb_t *, const uint8_t *, int); 787 int igb_multicst_add(igb_t *, const uint8_t *); 788 int igb_multicst_remove(igb_t *, const uint8_t *); 789 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 790 void igb_enable_watchdog_timer(igb_t *); 791 void igb_disable_watchdog_timer(igb_t *); 792 int igb_atomic_reserve(uint32_t *, uint32_t); 793 int igb_check_acc_handle(ddi_acc_handle_t); 794 int igb_check_dma_handle(ddi_dma_handle_t); 795 void igb_fm_ereport(igb_t *, char *); 796 void igb_set_fma_flags(int); 797 798 /* 799 * Function prototypes in igb_gld.c 800 */ 801 int igb_m_start(void *); 802 void igb_m_stop(void *); 803 int igb_m_promisc(void *, boolean_t); 804 int igb_m_multicst(void *, boolean_t, const uint8_t *); 805 int igb_m_unicst(void *, const uint8_t *); 806 int igb_m_stat(void *, uint_t, uint64_t *); 807 void igb_m_resources(void *); 808 void igb_m_ioctl(void *, queue_t *, mblk_t *); 809 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 810 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 811 mac_ring_info_t *, mac_ring_handle_t); 812 int igb_m_setprop(void *, const char *, mac_prop_id_t, uint_t, const void *); 813 int igb_m_getprop(void *, const char *, mac_prop_id_t, 814 uint_t, uint_t, void *, uint_t *); 815 int igb_set_priv_prop(igb_t *, const char *, uint_t, const void *); 816 int igb_get_priv_prop(igb_t *, const char *, 817 uint_t, uint_t, void *, uint_t *); 818 boolean_t igb_param_locked(mac_prop_id_t); 819 void igb_fill_group(void *arg, mac_ring_type_t, const int, 820 mac_group_info_t *, mac_group_handle_t); 821 int igb_rx_ring_intr_enable(mac_intr_handle_t); 822 int igb_rx_ring_intr_disable(mac_intr_handle_t); 823 int igb_get_def_val(igb_t *, mac_prop_id_t, uint_t, void *); 824 825 /* 826 * Function prototypes in igb_rx.c 827 */ 828 mblk_t *igb_rx(igb_rx_ring_t *, int); 829 void igb_rx_recycle(caddr_t arg); 830 831 /* 832 * Function prototypes in igb_tx.c 833 */ 834 void igb_free_tcb(tx_control_block_t *); 835 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 836 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 837 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 838 839 /* 840 * Function prototypes in igb_log.c 841 */ 842 void igb_notice(void *, const char *, ...); 843 void igb_log(void *, const char *, ...); 844 void igb_error(void *, const char *, ...); 845 846 /* 847 * Function prototypes in igb_stat.c 848 */ 849 int igb_init_stats(igb_t *); 850 851 mblk_t *igb_rx_ring_poll(void *, int); 852 mblk_t *igb_tx_ring_send(void *, mblk_t *); 853 854 #ifdef __cplusplus 855 } 856 #endif 857 858 #endif /* _IGB_SW_H */ 859