1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2009 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _IGB_SW_H 30 #define _IGB_SW_H 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/types.h> 37 #include <sys/conf.h> 38 #include <sys/debug.h> 39 #include <sys/stropts.h> 40 #include <sys/stream.h> 41 #include <sys/strsun.h> 42 #include <sys/strlog.h> 43 #include <sys/kmem.h> 44 #include <sys/stat.h> 45 #include <sys/kstat.h> 46 #include <sys/modctl.h> 47 #include <sys/errno.h> 48 #include <sys/dlpi.h> 49 #include <sys/mac_provider.h> 50 #include <sys/mac_ether.h> 51 #include <sys/vlan.h> 52 #include <sys/ddi.h> 53 #include <sys/sunddi.h> 54 #include <sys/pci.h> 55 #include <sys/pcie.h> 56 #include <sys/sdt.h> 57 #include <sys/ethernet.h> 58 #include <sys/pattr.h> 59 #include <sys/strsubr.h> 60 #include <sys/netlb.h> 61 #include <sys/random.h> 62 #include <inet/common.h> 63 #include <inet/tcp.h> 64 #include <inet/ip.h> 65 #include <inet/mi.h> 66 #include <inet/nd.h> 67 #include <sys/ddifm.h> 68 #include <sys/fm/protocol.h> 69 #include <sys/fm/util.h> 70 #include <sys/fm/io/ddi.h> 71 #include "igb_api.h" 72 #include "igb_82575.h" 73 74 75 #define MODULE_NAME "igb" /* module name */ 76 77 #define IGB_SUCCESS DDI_SUCCESS 78 #define IGB_FAILURE DDI_FAILURE 79 80 #define IGB_UNKNOWN 0x00 81 #define IGB_INITIALIZED 0x01 82 #define IGB_STARTED 0x02 83 #define IGB_SUSPENDED 0x04 84 #define IGB_STALL 0x08 85 86 #define IGB_INTR_NONE 0 87 #define IGB_INTR_MSIX 1 88 #define IGB_INTR_MSI 2 89 #define IGB_INTR_LEGACY 3 90 91 #define IGB_ADAPTER_REGSET 1 /* mapping adapter registers */ 92 #define IGB_ADAPTER_MSIXTAB 4 /* mapping msi-x table */ 93 94 #define IGB_NO_POLL -1 95 #define IGB_NO_FREE_SLOT -1 96 97 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 98 #define MCAST_ALLOC_COUNT 256 99 #define MAX_COOKIE 18 100 #define MIN_NUM_TX_DESC 2 101 102 /* 103 * Number of settings for interrupt throttle rate (ITR). There is one of 104 * these per msi-x vector and it needs to be the maximum of all silicon 105 * types supported by this driver. 106 */ 107 #define MAX_NUM_EITR 25 108 109 /* 110 * Maximum values for user configurable parameters 111 */ 112 #define MAX_TX_RING_SIZE 4096 113 #define MAX_RX_RING_SIZE 4096 114 #define MAX_RX_GROUP_NUM 4 115 116 #define MAX_MTU 9000 117 #define MAX_RX_LIMIT_PER_INTR 4096 118 119 #define MAX_RX_COPY_THRESHOLD 9216 120 #define MAX_TX_COPY_THRESHOLD 9216 121 #define MAX_TX_RECYCLE_THRESHOLD DEFAULT_TX_RING_SIZE 122 #define MAX_TX_OVERLOAD_THRESHOLD DEFAULT_TX_RING_SIZE 123 #define MAX_TX_RESCHED_THRESHOLD DEFAULT_TX_RING_SIZE 124 #define MAX_MCAST_NUM 8192 125 126 /* 127 * Minimum values for user configurable parameters 128 */ 129 #define MIN_TX_RING_SIZE 64 130 #define MIN_RX_RING_SIZE 64 131 #define MIN_RX_GROUP_NUM 1 132 133 #define MIN_MTU ETHERMIN 134 #define MIN_RX_LIMIT_PER_INTR 16 135 136 #define MIN_RX_COPY_THRESHOLD 0 137 #define MIN_TX_COPY_THRESHOLD 0 138 #define MIN_TX_RECYCLE_THRESHOLD MIN_NUM_TX_DESC 139 #define MIN_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 140 #define MIN_TX_RESCHED_THRESHOLD MIN_NUM_TX_DESC 141 #define MIN_MCAST_NUM 8 142 143 /* 144 * Default values for user configurable parameters 145 */ 146 #define DEFAULT_TX_RING_SIZE 512 147 #define DEFAULT_RX_RING_SIZE 512 148 #define DEFAULT_RX_GROUP_NUM 1 149 150 #define DEFAULT_MTU ETHERMTU 151 #define DEFAULT_RX_LIMIT_PER_INTR 256 152 153 #define DEFAULT_RX_COPY_THRESHOLD 128 154 #define DEFAULT_TX_COPY_THRESHOLD 512 155 #define DEFAULT_TX_RECYCLE_THRESHOLD (MAX_COOKIE + 1) 156 #define DEFAULT_TX_OVERLOAD_THRESHOLD MIN_NUM_TX_DESC 157 #define DEFAULT_TX_RESCHED_THRESHOLD 128 158 #define DEFAULT_MCAST_NUM 4096 159 160 #define IGB_LSO_MAXLEN 65535 161 162 #define TX_DRAIN_TIME 200 163 #define RX_DRAIN_TIME 200 164 165 #define STALL_WATCHDOG_TIMEOUT 8 /* 8 seconds */ 166 #define MAX_LINK_DOWN_TIMEOUT 8 /* 8 seconds */ 167 168 /* 169 * Defined for IP header alignment. 170 */ 171 #define IPHDR_ALIGN_ROOM 2 172 173 /* 174 * Bit flags for attach_progress 175 */ 176 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 177 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 178 #define ATTACH_PROGRESS_PROPS 0x0004 /* Properties initialized */ 179 #define ATTACH_PROGRESS_ALLOC_INTR 0x0008 /* Interrupts allocated */ 180 #define ATTACH_PROGRESS_ALLOC_RINGS 0x0010 /* Rings allocated */ 181 #define ATTACH_PROGRESS_ADD_INTR 0x0020 /* Intr handlers added */ 182 #define ATTACH_PROGRESS_LOCKS 0x0040 /* Locks initialized */ 183 #define ATTACH_PROGRESS_INIT_ADAPTER 0x0080 /* Adapter initialized */ 184 #define ATTACH_PROGRESS_ALLOC_DMA 0x0100 /* DMA resources allocated */ 185 #define ATTACH_PROGRESS_STATS 0x0200 /* Kstats created */ 186 #define ATTACH_PROGRESS_NDD 0x0400 /* NDD initialized */ 187 #define ATTACH_PROGRESS_MAC 0x0800 /* MAC registered */ 188 #define ATTACH_PROGRESS_ENABLE_INTR 0x1000 /* DDI interrupts enabled */ 189 #define ATTACH_PROGRESS_FMINIT 0x2000 /* FMA initialized */ 190 191 #define PROP_ADV_AUTONEG_CAP "adv_autoneg_cap" 192 #define PROP_ADV_1000FDX_CAP "adv_1000fdx_cap" 193 #define PROP_ADV_1000HDX_CAP "adv_1000hdx_cap" 194 #define PROP_ADV_100FDX_CAP "adv_100fdx_cap" 195 #define PROP_ADV_100HDX_CAP "adv_100hdx_cap" 196 #define PROP_ADV_10FDX_CAP "adv_10fdx_cap" 197 #define PROP_ADV_10HDX_CAP "adv_10hdx_cap" 198 #define PROP_DEFAULT_MTU "default_mtu" 199 #define PROP_FLOW_CONTROL "flow_control" 200 #define PROP_TX_RING_SIZE "tx_ring_size" 201 #define PROP_RX_RING_SIZE "rx_ring_size" 202 #define PROP_MR_ENABLE "mr_enable" 203 #define PROP_RX_GROUP_NUM "rx_group_number" 204 205 #define PROP_INTR_FORCE "intr_force" 206 #define PROP_TX_HCKSUM_ENABLE "tx_hcksum_enable" 207 #define PROP_RX_HCKSUM_ENABLE "rx_hcksum_enable" 208 #define PROP_LSO_ENABLE "lso_enable" 209 #define PROP_TX_HEAD_WB_ENABLE "tx_head_wb_enable" 210 #define PROP_TX_COPY_THRESHOLD "tx_copy_threshold" 211 #define PROP_TX_RECYCLE_THRESHOLD "tx_recycle_threshold" 212 #define PROP_TX_OVERLOAD_THRESHOLD "tx_overload_threshold" 213 #define PROP_TX_RESCHED_THRESHOLD "tx_resched_threshold" 214 #define PROP_RX_COPY_THRESHOLD "rx_copy_threshold" 215 #define PROP_RX_LIMIT_PER_INTR "rx_limit_per_intr" 216 #define PROP_INTR_THROTTLING "intr_throttling" 217 #define PROP_MCAST_MAX_NUM "mcast_max_num" 218 219 #define IGB_LB_NONE 0 220 #define IGB_LB_EXTERNAL 1 221 #define IGB_LB_INTERNAL_MAC 2 222 #define IGB_LB_INTERNAL_PHY 3 223 #define IGB_LB_INTERNAL_SERDES 4 224 225 /* 226 * Shorthand for the NDD parameters 227 */ 228 #define param_autoneg_cap nd_params[PARAM_AUTONEG_CAP].val 229 #define param_pause_cap nd_params[PARAM_PAUSE_CAP].val 230 #define param_asym_pause_cap nd_params[PARAM_ASYM_PAUSE_CAP].val 231 #define param_1000fdx_cap nd_params[PARAM_1000FDX_CAP].val 232 #define param_1000hdx_cap nd_params[PARAM_1000HDX_CAP].val 233 #define param_100t4_cap nd_params[PARAM_100T4_CAP].val 234 #define param_100fdx_cap nd_params[PARAM_100FDX_CAP].val 235 #define param_100hdx_cap nd_params[PARAM_100HDX_CAP].val 236 #define param_10fdx_cap nd_params[PARAM_10FDX_CAP].val 237 #define param_10hdx_cap nd_params[PARAM_10HDX_CAP].val 238 #define param_rem_fault nd_params[PARAM_REM_FAULT].val 239 240 #define param_adv_autoneg_cap nd_params[PARAM_ADV_AUTONEG_CAP].val 241 #define param_adv_pause_cap nd_params[PARAM_ADV_PAUSE_CAP].val 242 #define param_adv_asym_pause_cap nd_params[PARAM_ADV_ASYM_PAUSE_CAP].val 243 #define param_adv_1000fdx_cap nd_params[PARAM_ADV_1000FDX_CAP].val 244 #define param_adv_1000hdx_cap nd_params[PARAM_ADV_1000HDX_CAP].val 245 #define param_adv_100t4_cap nd_params[PARAM_ADV_100T4_CAP].val 246 #define param_adv_100fdx_cap nd_params[PARAM_ADV_100FDX_CAP].val 247 #define param_adv_100hdx_cap nd_params[PARAM_ADV_100HDX_CAP].val 248 #define param_adv_10fdx_cap nd_params[PARAM_ADV_10FDX_CAP].val 249 #define param_adv_10hdx_cap nd_params[PARAM_ADV_10HDX_CAP].val 250 #define param_adv_rem_fault nd_params[PARAM_ADV_REM_FAULT].val 251 252 #define param_lp_autoneg_cap nd_params[PARAM_LP_AUTONEG_CAP].val 253 #define param_lp_pause_cap nd_params[PARAM_LP_PAUSE_CAP].val 254 #define param_lp_asym_pause_cap nd_params[PARAM_LP_ASYM_PAUSE_CAP].val 255 #define param_lp_1000fdx_cap nd_params[PARAM_LP_1000FDX_CAP].val 256 #define param_lp_1000hdx_cap nd_params[PARAM_LP_1000HDX_CAP].val 257 #define param_lp_100t4_cap nd_params[PARAM_LP_100T4_CAP].val 258 #define param_lp_100fdx_cap nd_params[PARAM_LP_100FDX_CAP].val 259 #define param_lp_100hdx_cap nd_params[PARAM_LP_100HDX_CAP].val 260 #define param_lp_10fdx_cap nd_params[PARAM_LP_10FDX_CAP].val 261 #define param_lp_10hdx_cap nd_params[PARAM_LP_10HDX_CAP].val 262 #define param_lp_rem_fault nd_params[PARAM_LP_REM_FAULT].val 263 264 enum ioc_reply { 265 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 266 IOC_DONE, /* OK, reply sent */ 267 IOC_ACK, /* OK, just send ACK */ 268 IOC_REPLY /* OK, just send reply */ 269 }; 270 271 /* 272 * For s/w context extraction from a tx frame 273 */ 274 #define TX_CXT_SUCCESS 0 275 #define TX_CXT_E_LSO_CSUM (-1) 276 #define TX_CXT_E_ETHER_TYPE (-2) 277 278 #define DMA_SYNC(area, flag) ((void) ddi_dma_sync((area)->dma_handle, \ 279 0, 0, (flag))) 280 281 /* 282 * Defined for ring index operations 283 * ASSERT(index < limit) 284 * ASSERT(step < limit) 285 * ASSERT(index1 < limit) 286 * ASSERT(index2 < limit) 287 */ 288 #define NEXT_INDEX(index, step, limit) (((index) + (step)) < (limit) ? \ 289 (index) + (step) : (index) + (step) - (limit)) 290 #define PREV_INDEX(index, step, limit) ((index) >= (step) ? \ 291 (index) - (step) : (index) + (limit) - (step)) 292 #define OFFSET(index1, index2, limit) ((index1) <= (index2) ? \ 293 (index2) - (index1) : (index2) + (limit) - (index1)) 294 295 #define LINK_LIST_INIT(_LH) \ 296 (_LH)->head = (_LH)->tail = NULL 297 298 #define LIST_GET_HEAD(_LH) ((single_link_t *)((_LH)->head)) 299 300 #define LIST_POP_HEAD(_LH) \ 301 (single_link_t *)(_LH)->head; \ 302 { \ 303 if ((_LH)->head != NULL) { \ 304 (_LH)->head = (_LH)->head->link; \ 305 if ((_LH)->head == NULL) \ 306 (_LH)->tail = NULL; \ 307 } \ 308 } 309 310 #define LIST_GET_TAIL(_LH) ((single_link_t *)((_LH)->tail)) 311 312 #define LIST_PUSH_TAIL(_LH, _E) \ 313 if ((_LH)->tail != NULL) { \ 314 (_LH)->tail->link = (single_link_t *)(_E); \ 315 (_LH)->tail = (single_link_t *)(_E); \ 316 } else { \ 317 (_LH)->head = (_LH)->tail = (single_link_t *)(_E); \ 318 } \ 319 (_E)->link = NULL; 320 321 #define LIST_GET_NEXT(_LH, _E) \ 322 (((_LH)->tail == (single_link_t *)(_E)) ? \ 323 NULL : ((single_link_t *)(_E))->link) 324 325 326 typedef struct single_link { 327 struct single_link *link; 328 } single_link_t; 329 330 typedef struct link_list { 331 single_link_t *head; 332 single_link_t *tail; 333 } link_list_t; 334 335 /* 336 * Property lookups 337 */ 338 #define IGB_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 339 DDI_PROP_DONTPASS, (n)) 340 #define IGB_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 341 DDI_PROP_DONTPASS, (n), -1) 342 343 344 /* capability/feature flags */ 345 #define IGB_FLAG_HAS_DCA (1 << 0) /* has Direct Cache Access */ 346 #define IGB_FLAG_VMDQ_POOL (1 << 1) /* has vmdq capability */ 347 #define IGB_FLAG_NEED_CTX_IDX (1 << 2) /* context descriptor needs index */ 348 349 /* function pointer for nic-specific functions */ 350 typedef void (*igb_nic_func_t)(struct igb *); 351 352 /* adapter-specific info for each supported device type */ 353 typedef struct adapter_info { 354 /* limits */ 355 uint32_t max_rx_que_num; /* maximum number of rx queues */ 356 uint32_t min_rx_que_num; /* minimum number of rx queues */ 357 uint32_t def_rx_que_num; /* default number of rx queues */ 358 uint32_t max_tx_que_num; /* maximum number of tx queues */ 359 uint32_t min_tx_que_num; /* minimum number of tx queues */ 360 uint32_t def_tx_que_num; /* default number of tx queues */ 361 uint32_t max_intr_throttle; /* maximum interrupt throttle */ 362 uint32_t min_intr_throttle; /* minimum interrupt throttle */ 363 uint32_t def_intr_throttle; /* default interrupt throttle */ 364 /* function pointers */ 365 igb_nic_func_t enable_intr; /* enable adapter interrupts */ 366 igb_nic_func_t setup_msix; /* set up msi-x vectors */ 367 /* capabilities */ 368 uint32_t flags; /* capability flags */ 369 uint32_t rxdctl_mask; /* mask for RXDCTL register */ 370 } adapter_info_t; 371 372 /* 373 * Named Data (ND) Parameter Management Structure 374 */ 375 typedef struct { 376 struct igb *private; 377 uint32_t info; 378 uint32_t min; 379 uint32_t max; 380 uint32_t val; 381 char *name; 382 } nd_param_t; 383 384 /* 385 * NDD parameter indexes, divided into: 386 * 387 * read-only parameters describing the hardware's capabilities 388 * read-write parameters controlling the advertised capabilities 389 * read-only parameters describing the partner's capabilities 390 * read-write parameters controlling the force speed and duplex 391 * read-only parameters describing the link state 392 * read-only parameters describing the driver properties 393 * read-write parameters controlling the driver properties 394 */ 395 enum { 396 PARAM_AUTONEG_CAP, 397 PARAM_PAUSE_CAP, 398 PARAM_ASYM_PAUSE_CAP, 399 PARAM_1000FDX_CAP, 400 PARAM_1000HDX_CAP, 401 PARAM_100T4_CAP, 402 PARAM_100FDX_CAP, 403 PARAM_100HDX_CAP, 404 PARAM_10FDX_CAP, 405 PARAM_10HDX_CAP, 406 PARAM_REM_FAULT, 407 408 PARAM_ADV_AUTONEG_CAP, 409 PARAM_ADV_PAUSE_CAP, 410 PARAM_ADV_ASYM_PAUSE_CAP, 411 PARAM_ADV_1000FDX_CAP, 412 PARAM_ADV_1000HDX_CAP, 413 PARAM_ADV_100T4_CAP, 414 PARAM_ADV_100FDX_CAP, 415 PARAM_ADV_100HDX_CAP, 416 PARAM_ADV_10FDX_CAP, 417 PARAM_ADV_10HDX_CAP, 418 PARAM_ADV_REM_FAULT, 419 420 PARAM_LP_AUTONEG_CAP, 421 PARAM_LP_PAUSE_CAP, 422 PARAM_LP_ASYM_PAUSE_CAP, 423 PARAM_LP_1000FDX_CAP, 424 PARAM_LP_1000HDX_CAP, 425 PARAM_LP_100T4_CAP, 426 PARAM_LP_100FDX_CAP, 427 PARAM_LP_100HDX_CAP, 428 PARAM_LP_10FDX_CAP, 429 PARAM_LP_10HDX_CAP, 430 PARAM_LP_REM_FAULT, 431 432 PARAM_LINK_STATUS, 433 PARAM_LINK_SPEED, 434 PARAM_LINK_DUPLEX, 435 436 PARAM_COUNT 437 }; 438 439 typedef union igb_ether_addr { 440 struct { 441 uint32_t high; 442 uint32_t low; 443 } reg; 444 struct { 445 uint8_t set; 446 uint8_t group_index; 447 uint8_t addr[ETHERADDRL]; 448 } mac; 449 } igb_ether_addr_t; 450 451 typedef enum { 452 USE_NONE, 453 USE_COPY, 454 USE_DMA 455 } tx_type_t; 456 457 typedef enum { 458 RCB_FREE, 459 RCB_SENDUP 460 } rcb_state_t; 461 462 typedef struct tx_context { 463 uint32_t hcksum_flags; 464 uint32_t ip_hdr_len; 465 uint32_t mac_hdr_len; 466 uint32_t l4_proto; 467 uint32_t mss; 468 uint32_t l4_hdr_len; 469 boolean_t lso_flag; 470 } tx_context_t; 471 472 /* Hold address/length of each DMA segment */ 473 typedef struct sw_desc { 474 uint64_t address; 475 size_t length; 476 } sw_desc_t; 477 478 /* Handles and addresses of DMA buffer */ 479 typedef struct dma_buffer { 480 caddr_t address; /* Virtual address */ 481 uint64_t dma_address; /* DMA (Hardware) address */ 482 ddi_acc_handle_t acc_handle; /* Data access handle */ 483 ddi_dma_handle_t dma_handle; /* DMA handle */ 484 size_t size; /* Buffer size */ 485 size_t len; /* Data length in the buffer */ 486 } dma_buffer_t; 487 488 /* 489 * Tx Control Block 490 */ 491 typedef struct tx_control_block { 492 single_link_t link; 493 uint32_t frag_num; 494 uint32_t desc_num; 495 mblk_t *mp; 496 tx_type_t tx_type; 497 ddi_dma_handle_t tx_dma_handle; 498 dma_buffer_t tx_buf; 499 sw_desc_t desc[MAX_COOKIE]; 500 } tx_control_block_t; 501 502 /* 503 * RX Control Block 504 */ 505 typedef struct rx_control_block { 506 mblk_t *mp; 507 rcb_state_t state; 508 dma_buffer_t rx_buf; 509 frtn_t free_rtn; 510 struct igb_rx_ring *rx_ring; 511 } rx_control_block_t; 512 513 /* 514 * Software Data Structure for Tx Ring 515 */ 516 typedef struct igb_tx_ring { 517 uint32_t index; /* Ring index */ 518 uint32_t intr_vector; /* Interrupt vector index */ 519 520 /* 521 * Mutexes 522 */ 523 kmutex_t tx_lock; 524 kmutex_t recycle_lock; 525 kmutex_t tcb_head_lock; 526 kmutex_t tcb_tail_lock; 527 528 /* 529 * Tx descriptor ring definitions 530 */ 531 dma_buffer_t tbd_area; 532 union e1000_adv_tx_desc *tbd_ring; 533 uint32_t tbd_head; /* Index of next tbd to recycle */ 534 uint32_t tbd_tail; /* Index of next tbd to transmit */ 535 uint32_t tbd_free; /* Number of free tbd */ 536 537 /* 538 * Tx control block list definitions 539 */ 540 tx_control_block_t *tcb_area; 541 tx_control_block_t **work_list; 542 tx_control_block_t **free_list; 543 uint32_t tcb_head; /* Head index of free list */ 544 uint32_t tcb_tail; /* Tail index of free list */ 545 uint32_t tcb_free; /* Number of free tcb in free list */ 546 547 uint32_t *tbd_head_wb; /* Head write-back */ 548 uint32_t (*tx_recycle)(struct igb_tx_ring *); 549 550 /* 551 * s/w context structure for TCP/UDP checksum offload and LSO. 552 */ 553 tx_context_t tx_context; 554 555 /* 556 * Tx ring settings and status 557 */ 558 uint32_t ring_size; /* Tx descriptor ring size */ 559 uint32_t free_list_size; /* Tx free list size */ 560 uint32_t copy_thresh; 561 uint32_t recycle_thresh; 562 uint32_t overload_thresh; 563 uint32_t resched_thresh; 564 565 boolean_t reschedule; 566 uint32_t recycle_fail; 567 uint32_t stall_watchdog; 568 569 #ifdef IGB_DEBUG 570 /* 571 * Debug statistics 572 */ 573 uint32_t stat_overload; 574 uint32_t stat_fail_no_tbd; 575 uint32_t stat_fail_no_tcb; 576 uint32_t stat_fail_dma_bind; 577 uint32_t stat_reschedule; 578 uint32_t stat_pkt_cnt; 579 #endif 580 581 /* 582 * Pointer to the igb struct 583 */ 584 struct igb *igb; 585 mac_ring_handle_t ring_handle; /* call back ring handle */ 586 } igb_tx_ring_t; 587 588 /* 589 * Software Receive Ring 590 */ 591 typedef struct igb_rx_ring { 592 uint32_t index; /* Ring index */ 593 uint32_t intr_vector; /* Interrupt vector index */ 594 595 /* 596 * Mutexes 597 */ 598 kmutex_t rx_lock; /* Rx access lock */ 599 kmutex_t recycle_lock; /* Recycle lock, for rcb_tail */ 600 601 /* 602 * Rx descriptor ring definitions 603 */ 604 dma_buffer_t rbd_area; /* DMA buffer of rx desc ring */ 605 union e1000_adv_rx_desc *rbd_ring; /* Rx desc ring */ 606 uint32_t rbd_next; /* Index of next rx desc */ 607 608 /* 609 * Rx control block list definitions 610 */ 611 rx_control_block_t *rcb_area; 612 rx_control_block_t **work_list; /* Work list of rcbs */ 613 rx_control_block_t **free_list; /* Free list of rcbs */ 614 uint32_t rcb_head; /* Index of next free rcb */ 615 uint32_t rcb_tail; /* Index to put recycled rcb */ 616 uint32_t rcb_free; /* Number of free rcbs */ 617 618 /* 619 * Rx ring settings and status 620 */ 621 uint32_t ring_size; /* Rx descriptor ring size */ 622 uint32_t free_list_size; /* Rx free list size */ 623 uint32_t limit_per_intr; /* Max packets per interrupt */ 624 uint32_t copy_thresh; 625 626 #ifdef IGB_DEBUG 627 /* 628 * Debug statistics 629 */ 630 uint32_t stat_frame_error; 631 uint32_t stat_cksum_error; 632 uint32_t stat_exceed_pkt; 633 uint32_t stat_pkt_cnt; 634 #endif 635 636 struct igb *igb; /* Pointer to igb struct */ 637 mac_ring_handle_t ring_handle; /* call back ring handle */ 638 uint32_t group_index; /* group index */ 639 uint64_t ring_gen_num; 640 } igb_rx_ring_t; 641 642 /* 643 * Software Receive Ring Group 644 */ 645 typedef struct igb_rx_group { 646 uint32_t index; /* Group index */ 647 mac_group_handle_t group_handle; /* call back group handle */ 648 struct igb *igb; /* Pointer to igb struct */ 649 } igb_rx_group_t; 650 651 typedef struct igb { 652 int instance; 653 mac_handle_t mac_hdl; 654 dev_info_t *dip; 655 struct e1000_hw hw; 656 struct igb_osdep osdep; 657 658 adapter_info_t *capab; /* adapter capabilities */ 659 660 uint32_t igb_state; 661 link_state_t link_state; 662 uint32_t link_speed; 663 uint32_t link_duplex; 664 uint32_t link_down_timeout; 665 666 uint32_t reset_count; 667 uint32_t attach_progress; 668 uint32_t loopback_mode; 669 uint32_t max_frame_size; 670 uint32_t dout_sync; 671 672 uint32_t mr_enable; /* Enable multiple rings */ 673 uint32_t vmdq_mode; /* Mode of VMDq */ 674 675 /* 676 * Receive Rings and Groups 677 */ 678 igb_rx_ring_t *rx_rings; /* Array of rx rings */ 679 uint32_t num_rx_rings; /* Number of rx rings in use */ 680 uint32_t rx_ring_size; /* Rx descriptor ring size */ 681 uint32_t rx_buf_size; /* Rx buffer size */ 682 igb_rx_group_t *rx_groups; /* Array of rx groups */ 683 uint32_t num_rx_groups; /* Number of rx groups in use */ 684 685 /* 686 * Transmit Rings 687 */ 688 igb_tx_ring_t *tx_rings; /* Array of tx rings */ 689 uint32_t num_tx_rings; /* Number of tx rings in use */ 690 uint32_t tx_ring_size; /* Tx descriptor ring size */ 691 uint32_t tx_buf_size; /* Tx buffer size */ 692 693 boolean_t tx_head_wb_enable; /* Tx head wrtie-back */ 694 boolean_t tx_hcksum_enable; /* Tx h/w cksum offload */ 695 boolean_t lso_enable; /* Large Segment Offload */ 696 uint32_t tx_copy_thresh; /* Tx copy threshold */ 697 uint32_t tx_recycle_thresh; /* Tx recycle threshold */ 698 uint32_t tx_overload_thresh; /* Tx overload threshold */ 699 uint32_t tx_resched_thresh; /* Tx reschedule threshold */ 700 boolean_t rx_hcksum_enable; /* Rx h/w cksum offload */ 701 uint32_t rx_copy_thresh; /* Rx copy threshold */ 702 uint32_t rx_limit_per_intr; /* Rx pkts per interrupt */ 703 704 uint32_t intr_throttling[MAX_NUM_EITR]; 705 uint32_t intr_force; 706 707 int intr_type; 708 int intr_cnt; 709 int intr_cap; 710 size_t intr_size; 711 uint_t intr_pri; 712 ddi_intr_handle_t *htable; 713 uint32_t eims_mask; 714 uint32_t ims_mask; 715 716 kmutex_t gen_lock; /* General lock for device access */ 717 kmutex_t watchdog_lock; 718 719 boolean_t watchdog_enable; 720 boolean_t watchdog_start; 721 timeout_id_t watchdog_tid; 722 723 boolean_t unicst_init; 724 uint32_t unicst_avail; 725 uint32_t unicst_total; 726 igb_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 727 uint32_t mcast_count; 728 uint32_t mcast_alloc_count; 729 uint32_t mcast_max_num; 730 struct ether_addr *mcast_table; 731 732 /* 733 * Kstat definitions 734 */ 735 kstat_t *igb_ks; 736 737 /* 738 * NDD definitions 739 */ 740 caddr_t nd_data; 741 nd_param_t nd_params[PARAM_COUNT]; 742 743 /* 744 * FMA capabilities 745 */ 746 int fm_capabilities; 747 748 ulong_t page_size; 749 } igb_t; 750 751 typedef struct igb_stat { 752 753 kstat_named_t link_speed; /* Link Speed */ 754 kstat_named_t reset_count; /* Reset Count */ 755 kstat_named_t dout_sync; /* DMA out of sync */ 756 #ifdef IGB_DEBUG 757 kstat_named_t rx_frame_error; /* Rx Error in Packet */ 758 kstat_named_t rx_cksum_error; /* Rx Checksum Error */ 759 kstat_named_t rx_exceed_pkt; /* Rx Exceed Max Pkt Count */ 760 761 kstat_named_t tx_overload; /* Tx Desc Ring Overload */ 762 kstat_named_t tx_fail_no_tcb; /* Tx Fail Freelist Empty */ 763 kstat_named_t tx_fail_no_tbd; /* Tx Fail Desc Ring Empty */ 764 kstat_named_t tx_fail_dma_bind; /* Tx Fail DMA bind */ 765 kstat_named_t tx_reschedule; /* Tx Reschedule */ 766 767 kstat_named_t gprc; /* Good Packets Received Count */ 768 kstat_named_t gptc; /* Good Packets Xmitted Count */ 769 kstat_named_t gor; /* Good Octets Received Count */ 770 kstat_named_t got; /* Good Octets Xmitd Count */ 771 kstat_named_t prc64; /* Packets Received - 64b */ 772 kstat_named_t prc127; /* Packets Received - 65-127b */ 773 kstat_named_t prc255; /* Packets Received - 127-255b */ 774 kstat_named_t prc511; /* Packets Received - 256-511b */ 775 kstat_named_t prc1023; /* Packets Received - 511-1023b */ 776 kstat_named_t prc1522; /* Packets Received - 1024-1522b */ 777 kstat_named_t ptc64; /* Packets Xmitted (64b) */ 778 kstat_named_t ptc127; /* Packets Xmitted (64-127b) */ 779 kstat_named_t ptc255; /* Packets Xmitted (128-255b) */ 780 kstat_named_t ptc511; /* Packets Xmitted (255-511b) */ 781 kstat_named_t ptc1023; /* Packets Xmitted (512-1023b) */ 782 kstat_named_t ptc1522; /* Packets Xmitted (1024-1522b */ 783 #endif 784 kstat_named_t crcerrs; /* CRC Error Count */ 785 kstat_named_t symerrs; /* Symbol Error Count */ 786 kstat_named_t mpc; /* Missed Packet Count */ 787 kstat_named_t scc; /* Single Collision Count */ 788 kstat_named_t ecol; /* Excessive Collision Count */ 789 kstat_named_t mcc; /* Multiple Collision Count */ 790 kstat_named_t latecol; /* Late Collision Count */ 791 kstat_named_t colc; /* Collision Count */ 792 kstat_named_t dc; /* Defer Count */ 793 kstat_named_t sec; /* Sequence Error Count */ 794 kstat_named_t rlec; /* Receive Length Error Count */ 795 kstat_named_t xonrxc; /* XON Received Count */ 796 kstat_named_t xontxc; /* XON Xmitted Count */ 797 kstat_named_t xoffrxc; /* XOFF Received Count */ 798 kstat_named_t xofftxc; /* Xoff Xmitted Count */ 799 kstat_named_t fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 800 kstat_named_t bprc; /* Broadcasts Pkts Received Count */ 801 kstat_named_t mprc; /* Multicast Pkts Received Count */ 802 kstat_named_t rnbc; /* Receive No Buffers Count */ 803 kstat_named_t ruc; /* Receive Undersize Count */ 804 kstat_named_t rfc; /* Receive Frag Count */ 805 kstat_named_t roc; /* Receive Oversize Count */ 806 kstat_named_t rjc; /* Receive Jabber Count */ 807 kstat_named_t tor; /* Total Octets Recvd Count */ 808 kstat_named_t tot; /* Total Octets Xmted Count */ 809 kstat_named_t tpr; /* Total Packets Received */ 810 kstat_named_t tpt; /* Total Packets Xmitted */ 811 kstat_named_t mptc; /* Multicast Packets Xmited Count */ 812 kstat_named_t bptc; /* Broadcast Packets Xmited Count */ 813 kstat_named_t algnerrc; /* Alignment Error count */ 814 kstat_named_t rxerrc; /* Rx Error Count */ 815 kstat_named_t tncrs; /* Transmit with no CRS */ 816 kstat_named_t cexterr; /* Carrier Extension Error count */ 817 kstat_named_t tsctc; /* TCP seg contexts xmit count */ 818 kstat_named_t tsctfc; /* TCP seg contexts xmit fail count */ 819 } igb_stat_t; 820 821 /* 822 * Function prototypes in e1000_osdep.c 823 */ 824 void e1000_write_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 825 void e1000_read_pci_cfg(struct e1000_hw *, uint32_t, uint16_t *); 826 int32_t e1000_read_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 827 int32_t e1000_write_pcie_cap_reg(struct e1000_hw *, uint32_t, uint16_t *); 828 void e1000_rar_clear(struct e1000_hw *, uint32_t); 829 void e1000_rar_set_vmdq(struct e1000_hw *, const uint8_t *, uint32_t, 830 uint32_t, uint8_t); 831 832 /* 833 * Function prototypes in igb_buf.c 834 */ 835 int igb_alloc_dma(igb_t *); 836 void igb_free_dma(igb_t *); 837 838 /* 839 * Function prototypes in igb_main.c 840 */ 841 int igb_start(igb_t *); 842 void igb_stop(igb_t *); 843 int igb_setup_link(igb_t *, boolean_t); 844 int igb_unicst_find(igb_t *, const uint8_t *); 845 int igb_unicst_set(igb_t *, const uint8_t *, int); 846 int igb_multicst_add(igb_t *, const uint8_t *); 847 int igb_multicst_remove(igb_t *, const uint8_t *); 848 enum ioc_reply igb_loopback_ioctl(igb_t *, struct iocblk *, mblk_t *); 849 void igb_enable_watchdog_timer(igb_t *); 850 void igb_disable_watchdog_timer(igb_t *); 851 int igb_atomic_reserve(uint32_t *, uint32_t); 852 int igb_check_acc_handle(ddi_acc_handle_t); 853 int igb_check_dma_handle(ddi_dma_handle_t); 854 void igb_fm_ereport(igb_t *, char *); 855 void igb_set_fma_flags(int, int); 856 857 /* 858 * Function prototypes in igb_gld.c 859 */ 860 int igb_m_start(void *); 861 void igb_m_stop(void *); 862 int igb_m_promisc(void *, boolean_t); 863 int igb_m_multicst(void *, boolean_t, const uint8_t *); 864 int igb_m_unicst(void *, const uint8_t *); 865 int igb_m_stat(void *, uint_t, uint64_t *); 866 void igb_m_resources(void *); 867 void igb_m_ioctl(void *, queue_t *, mblk_t *); 868 boolean_t igb_m_getcapab(void *, mac_capab_t, void *); 869 void igb_fill_ring(void *, mac_ring_type_t, const int, const int, 870 mac_ring_info_t *, mac_ring_handle_t); 871 void igb_fill_group(void *arg, mac_ring_type_t, const int, 872 mac_group_info_t *, mac_group_handle_t); 873 int igb_rx_ring_intr_enable(mac_intr_handle_t); 874 int igb_rx_ring_intr_disable(mac_intr_handle_t); 875 876 /* 877 * Function prototypes in igb_rx.c 878 */ 879 mblk_t *igb_rx(igb_rx_ring_t *, int); 880 void igb_rx_recycle(caddr_t arg); 881 882 /* 883 * Function prototypes in igb_tx.c 884 */ 885 void igb_free_tcb(tx_control_block_t *); 886 void igb_put_free_list(igb_tx_ring_t *, link_list_t *); 887 uint32_t igb_tx_recycle_legacy(igb_tx_ring_t *); 888 uint32_t igb_tx_recycle_head_wb(igb_tx_ring_t *); 889 890 /* 891 * Function prototypes in igb_log.c 892 */ 893 void igb_notice(void *, const char *, ...); 894 void igb_log(void *, const char *, ...); 895 void igb_error(void *, const char *, ...); 896 897 /* 898 * Function prototypes in igb_ndd.c 899 */ 900 int igb_nd_init(igb_t *); 901 void igb_nd_cleanup(igb_t *); 902 enum ioc_reply igb_nd_ioctl(igb_t *, queue_t *, mblk_t *, struct iocblk *); 903 904 /* 905 * Function prototypes in igb_stat.c 906 */ 907 int igb_init_stats(igb_t *); 908 909 mblk_t *igb_rx_ring_poll(void *, int); 910 mblk_t *igb_tx_ring_send(void *, mblk_t *); 911 912 #ifdef __cplusplus 913 } 914 #endif 915 916 #endif /* _IGB_SW_H */ 917