1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 * Copyright 2013, Nexenta Systems, Inc. All rights reserved. 29 */ 30 31 #include "igb_sw.h" 32 33 static char ident[] = "Intel 1Gb Ethernet"; 34 static char igb_version[] = "igb 2.3.8-ish"; 35 36 /* 37 * Local function protoypes 38 */ 39 static int igb_register_mac(igb_t *); 40 static int igb_identify_hardware(igb_t *); 41 static int igb_regs_map(igb_t *); 42 static void igb_init_properties(igb_t *); 43 static int igb_init_driver_settings(igb_t *); 44 static void igb_init_locks(igb_t *); 45 static void igb_destroy_locks(igb_t *); 46 static int igb_init_mac_address(igb_t *); 47 static int igb_init(igb_t *); 48 static int igb_init_adapter(igb_t *); 49 static void igb_stop_adapter(igb_t *); 50 static int igb_reset(igb_t *); 51 static void igb_tx_clean(igb_t *); 52 static boolean_t igb_tx_drain(igb_t *); 53 static boolean_t igb_rx_drain(igb_t *); 54 static int igb_alloc_rings(igb_t *); 55 static int igb_alloc_rx_data(igb_t *); 56 static void igb_free_rx_data(igb_t *); 57 static void igb_free_rings(igb_t *); 58 static void igb_setup_rings(igb_t *); 59 static void igb_setup_rx(igb_t *); 60 static void igb_setup_tx(igb_t *); 61 static void igb_setup_rx_ring(igb_rx_ring_t *); 62 static void igb_setup_tx_ring(igb_tx_ring_t *); 63 static void igb_setup_rss(igb_t *); 64 static void igb_setup_mac_rss_classify(igb_t *); 65 static void igb_setup_mac_classify(igb_t *); 66 static void igb_init_unicst(igb_t *); 67 static void igb_setup_multicst(igb_t *); 68 static void igb_get_phy_state(igb_t *); 69 static void igb_param_sync(igb_t *); 70 static void igb_get_conf(igb_t *); 71 static int igb_get_prop(igb_t *, char *, int, int, int); 72 static boolean_t igb_is_link_up(igb_t *); 73 static boolean_t igb_link_check(igb_t *); 74 static void igb_local_timer(void *); 75 static void igb_link_timer(void *); 76 static void igb_arm_watchdog_timer(igb_t *); 77 static void igb_start_watchdog_timer(igb_t *); 78 static void igb_restart_watchdog_timer(igb_t *); 79 static void igb_stop_watchdog_timer(igb_t *); 80 static void igb_start_link_timer(igb_t *); 81 static void igb_stop_link_timer(igb_t *); 82 static void igb_disable_adapter_interrupts(igb_t *); 83 static void igb_enable_adapter_interrupts_82575(igb_t *); 84 static void igb_enable_adapter_interrupts_82576(igb_t *); 85 static void igb_enable_adapter_interrupts_82580(igb_t *); 86 static boolean_t is_valid_mac_addr(uint8_t *); 87 static boolean_t igb_stall_check(igb_t *); 88 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 89 static void igb_set_external_loopback(igb_t *); 90 static void igb_set_internal_phy_loopback(igb_t *); 91 static void igb_set_internal_serdes_loopback(igb_t *); 92 static boolean_t igb_find_mac_address(igb_t *); 93 static int igb_alloc_intrs(igb_t *); 94 static int igb_alloc_intr_handles(igb_t *, int); 95 static int igb_add_intr_handlers(igb_t *); 96 static void igb_rem_intr_handlers(igb_t *); 97 static void igb_rem_intrs(igb_t *); 98 static int igb_enable_intrs(igb_t *); 99 static int igb_disable_intrs(igb_t *); 100 static void igb_setup_msix_82575(igb_t *); 101 static void igb_setup_msix_82576(igb_t *); 102 static void igb_setup_msix_82580(igb_t *); 103 static uint_t igb_intr_legacy(void *, void *); 104 static uint_t igb_intr_msi(void *, void *); 105 static uint_t igb_intr_rx(void *, void *); 106 static uint_t igb_intr_tx(void *, void *); 107 static uint_t igb_intr_tx_other(void *, void *); 108 static void igb_intr_rx_work(igb_rx_ring_t *); 109 static void igb_intr_tx_work(igb_tx_ring_t *); 110 static void igb_intr_link_work(igb_t *); 111 static void igb_get_driver_control(struct e1000_hw *); 112 static void igb_release_driver_control(struct e1000_hw *); 113 114 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 115 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 116 static int igb_resume(dev_info_t *); 117 static int igb_suspend(dev_info_t *); 118 static int igb_quiesce(dev_info_t *); 119 static void igb_unconfigure(dev_info_t *, igb_t *); 120 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 121 const void *); 122 static void igb_fm_init(igb_t *); 123 static void igb_fm_fini(igb_t *); 124 static void igb_release_multicast(igb_t *); 125 126 char *igb_priv_props[] = { 127 "_eee_support", 128 "_tx_copy_thresh", 129 "_tx_recycle_thresh", 130 "_tx_overload_thresh", 131 "_tx_resched_thresh", 132 "_rx_copy_thresh", 133 "_rx_limit_per_intr", 134 "_intr_throttling", 135 "_adv_pause_cap", 136 "_adv_asym_pause_cap", 137 NULL 138 }; 139 140 static struct cb_ops igb_cb_ops = { 141 nulldev, /* cb_open */ 142 nulldev, /* cb_close */ 143 nodev, /* cb_strategy */ 144 nodev, /* cb_print */ 145 nodev, /* cb_dump */ 146 nodev, /* cb_read */ 147 nodev, /* cb_write */ 148 nodev, /* cb_ioctl */ 149 nodev, /* cb_devmap */ 150 nodev, /* cb_mmap */ 151 nodev, /* cb_segmap */ 152 nochpoll, /* cb_chpoll */ 153 ddi_prop_op, /* cb_prop_op */ 154 NULL, /* cb_stream */ 155 D_MP | D_HOTPLUG, /* cb_flag */ 156 CB_REV, /* cb_rev */ 157 nodev, /* cb_aread */ 158 nodev /* cb_awrite */ 159 }; 160 161 static struct dev_ops igb_dev_ops = { 162 DEVO_REV, /* devo_rev */ 163 0, /* devo_refcnt */ 164 NULL, /* devo_getinfo */ 165 nulldev, /* devo_identify */ 166 nulldev, /* devo_probe */ 167 igb_attach, /* devo_attach */ 168 igb_detach, /* devo_detach */ 169 nodev, /* devo_reset */ 170 &igb_cb_ops, /* devo_cb_ops */ 171 NULL, /* devo_bus_ops */ 172 ddi_power, /* devo_power */ 173 igb_quiesce, /* devo_quiesce */ 174 }; 175 176 static struct modldrv igb_modldrv = { 177 &mod_driverops, /* Type of module. This one is a driver */ 178 ident, /* Discription string */ 179 &igb_dev_ops, /* driver ops */ 180 }; 181 182 static struct modlinkage igb_modlinkage = { 183 MODREV_1, &igb_modldrv, NULL 184 }; 185 186 /* Access attributes for register mapping */ 187 ddi_device_acc_attr_t igb_regs_acc_attr = { 188 DDI_DEVICE_ATTR_V1, 189 DDI_STRUCTURE_LE_ACC, 190 DDI_STRICTORDER_ACC, 191 DDI_FLAGERR_ACC 192 }; 193 194 #define IGB_M_CALLBACK_FLAGS \ 195 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 196 197 static mac_callbacks_t igb_m_callbacks = { 198 IGB_M_CALLBACK_FLAGS, 199 igb_m_stat, 200 igb_m_start, 201 igb_m_stop, 202 igb_m_promisc, 203 igb_m_multicst, 204 NULL, 205 NULL, 206 NULL, 207 igb_m_ioctl, 208 igb_m_getcapab, 209 NULL, 210 NULL, 211 igb_m_setprop, 212 igb_m_getprop, 213 igb_m_propinfo 214 }; 215 216 /* 217 * Initialize capabilities of each supported adapter type 218 */ 219 static adapter_info_t igb_82575_cap = { 220 /* limits */ 221 4, /* maximum number of rx queues */ 222 1, /* minimum number of rx queues */ 223 4, /* default number of rx queues */ 224 4, /* maximum number of tx queues */ 225 1, /* minimum number of tx queues */ 226 4, /* default number of tx queues */ 227 65535, /* maximum interrupt throttle rate */ 228 0, /* minimum interrupt throttle rate */ 229 200, /* default interrupt throttle rate */ 230 231 /* function pointers */ 232 igb_enable_adapter_interrupts_82575, 233 igb_setup_msix_82575, 234 235 /* capabilities */ 236 (IGB_FLAG_HAS_DCA | /* capability flags */ 237 IGB_FLAG_VMDQ_POOL), 238 239 0xffc00000 /* mask for RXDCTL register */ 240 }; 241 242 static adapter_info_t igb_82576_cap = { 243 /* limits */ 244 16, /* maximum number of rx queues */ 245 1, /* minimum number of rx queues */ 246 4, /* default number of rx queues */ 247 16, /* maximum number of tx queues */ 248 1, /* minimum number of tx queues */ 249 4, /* default number of tx queues */ 250 65535, /* maximum interrupt throttle rate */ 251 0, /* minimum interrupt throttle rate */ 252 200, /* default interrupt throttle rate */ 253 254 /* function pointers */ 255 igb_enable_adapter_interrupts_82576, 256 igb_setup_msix_82576, 257 258 /* capabilities */ 259 (IGB_FLAG_HAS_DCA | /* capability flags */ 260 IGB_FLAG_VMDQ_POOL | 261 IGB_FLAG_NEED_CTX_IDX), 262 263 0xffe00000 /* mask for RXDCTL register */ 264 }; 265 266 static adapter_info_t igb_82580_cap = { 267 /* limits */ 268 8, /* maximum number of rx queues */ 269 1, /* minimum number of rx queues */ 270 4, /* default number of rx queues */ 271 8, /* maximum number of tx queues */ 272 1, /* minimum number of tx queues */ 273 4, /* default number of tx queues */ 274 65535, /* maximum interrupt throttle rate */ 275 0, /* minimum interrupt throttle rate */ 276 200, /* default interrupt throttle rate */ 277 278 /* function pointers */ 279 igb_enable_adapter_interrupts_82580, 280 igb_setup_msix_82580, 281 282 /* capabilities */ 283 (IGB_FLAG_HAS_DCA | /* capability flags */ 284 IGB_FLAG_VMDQ_POOL | 285 IGB_FLAG_NEED_CTX_IDX), 286 287 0xffe00000 /* mask for RXDCTL register */ 288 }; 289 290 static adapter_info_t igb_i350_cap = { 291 /* limits */ 292 8, /* maximum number of rx queues */ 293 1, /* minimum number of rx queues */ 294 4, /* default number of rx queues */ 295 8, /* maximum number of tx queues */ 296 1, /* minimum number of tx queues */ 297 4, /* default number of tx queues */ 298 65535, /* maximum interrupt throttle rate */ 299 0, /* minimum interrupt throttle rate */ 300 200, /* default interrupt throttle rate */ 301 302 /* function pointers */ 303 igb_enable_adapter_interrupts_82580, 304 igb_setup_msix_82580, 305 306 /* capabilities */ 307 (IGB_FLAG_HAS_DCA | /* capability flags */ 308 IGB_FLAG_VMDQ_POOL | 309 IGB_FLAG_NEED_CTX_IDX), 310 311 0xffe00000 /* mask for RXDCTL register */ 312 }; 313 314 static adapter_info_t igb_i210_cap = { 315 /* limits */ 316 4, /* maximum number of rx queues */ 317 1, /* minimum number of rx queues */ 318 4, /* default number of rx queues */ 319 4, /* maximum number of tx queues */ 320 1, /* minimum number of tx queues */ 321 4, /* default number of tx queues */ 322 65535, /* maximum interrupt throttle rate */ 323 0, /* minimum interrupt throttle rate */ 324 200, /* default interrupt throttle rate */ 325 326 /* function pointers */ 327 igb_enable_adapter_interrupts_82580, 328 igb_setup_msix_82580, 329 330 /* capabilities */ 331 (IGB_FLAG_HAS_DCA | /* capability flags */ 332 IGB_FLAG_VMDQ_POOL | 333 IGB_FLAG_NEED_CTX_IDX), 334 335 0xfff00000 /* mask for RXDCTL register */ 336 }; 337 338 static adapter_info_t igb_i354_cap = { 339 /* limits */ 340 8, /* maximum number of rx queues */ 341 1, /* minimum number of rx queues */ 342 4, /* default number of rx queues */ 343 8, /* maximum number of tx queues */ 344 1, /* minimum number of tx queues */ 345 4, /* default number of tx queues */ 346 65535, /* maximum interrupt throttle rate */ 347 0, /* minimum interrupt throttle rate */ 348 200, /* default interrupt throttle rate */ 349 350 /* function pointers */ 351 igb_enable_adapter_interrupts_82580, 352 igb_setup_msix_82580, 353 354 /* capabilities */ 355 (IGB_FLAG_HAS_DCA | /* capability flags */ 356 IGB_FLAG_VMDQ_POOL | 357 IGB_FLAG_NEED_CTX_IDX), 358 359 0xfff00000 /* mask for RXDCTL register */ 360 }; 361 362 /* 363 * Module Initialization Functions 364 */ 365 366 int 367 _init(void) 368 { 369 int status; 370 371 mac_init_ops(&igb_dev_ops, MODULE_NAME); 372 373 status = mod_install(&igb_modlinkage); 374 375 if (status != DDI_SUCCESS) { 376 mac_fini_ops(&igb_dev_ops); 377 } 378 379 return (status); 380 } 381 382 int 383 _fini(void) 384 { 385 int status; 386 387 status = mod_remove(&igb_modlinkage); 388 389 if (status == DDI_SUCCESS) { 390 mac_fini_ops(&igb_dev_ops); 391 } 392 393 return (status); 394 395 } 396 397 int 398 _info(struct modinfo *modinfop) 399 { 400 int status; 401 402 status = mod_info(&igb_modlinkage, modinfop); 403 404 return (status); 405 } 406 407 /* 408 * igb_attach - driver attach 409 * 410 * This function is the device specific initialization entry 411 * point. This entry point is required and must be written. 412 * The DDI_ATTACH command must be provided in the attach entry 413 * point. When attach() is called with cmd set to DDI_ATTACH, 414 * all normal kernel services (such as kmem_alloc(9F)) are 415 * available for use by the driver. 416 * 417 * The attach() function will be called once for each instance 418 * of the device on the system with cmd set to DDI_ATTACH. 419 * Until attach() succeeds, the only driver entry points which 420 * may be called are open(9E) and getinfo(9E). 421 */ 422 static int 423 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 424 { 425 igb_t *igb; 426 struct igb_osdep *osdep; 427 struct e1000_hw *hw; 428 int instance; 429 430 /* 431 * Check the command and perform corresponding operations 432 */ 433 switch (cmd) { 434 default: 435 return (DDI_FAILURE); 436 437 case DDI_RESUME: 438 return (igb_resume(devinfo)); 439 440 case DDI_ATTACH: 441 break; 442 } 443 444 /* Get the device instance */ 445 instance = ddi_get_instance(devinfo); 446 447 /* Allocate memory for the instance data structure */ 448 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 449 450 igb->dip = devinfo; 451 igb->instance = instance; 452 453 hw = &igb->hw; 454 osdep = &igb->osdep; 455 hw->back = osdep; 456 osdep->igb = igb; 457 458 /* Attach the instance pointer to the dev_info data structure */ 459 ddi_set_driver_private(devinfo, igb); 460 461 462 /* Initialize for fma support */ 463 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 464 0, 0x0f, 465 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 466 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 467 igb_fm_init(igb); 468 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 469 470 /* 471 * Map PCI config space registers 472 */ 473 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 474 igb_error(igb, "Failed to map PCI configurations"); 475 goto attach_fail; 476 } 477 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 478 479 /* 480 * Identify the chipset family 481 */ 482 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 483 igb_error(igb, "Failed to identify hardware"); 484 goto attach_fail; 485 } 486 487 /* 488 * Map device registers 489 */ 490 if (igb_regs_map(igb) != IGB_SUCCESS) { 491 igb_error(igb, "Failed to map device registers"); 492 goto attach_fail; 493 } 494 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 495 496 /* 497 * Initialize driver parameters 498 */ 499 igb_init_properties(igb); 500 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 501 502 /* 503 * Allocate interrupts 504 */ 505 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 506 igb_error(igb, "Failed to allocate interrupts"); 507 goto attach_fail; 508 } 509 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 510 511 /* 512 * Allocate rx/tx rings based on the ring numbers. 513 * The actual numbers of rx/tx rings are decided by the number of 514 * allocated interrupt vectors, so we should allocate the rings after 515 * interrupts are allocated. 516 */ 517 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 518 igb_error(igb, "Failed to allocate rx/tx rings or groups"); 519 goto attach_fail; 520 } 521 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 522 523 /* 524 * Add interrupt handlers 525 */ 526 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 527 igb_error(igb, "Failed to add interrupt handlers"); 528 goto attach_fail; 529 } 530 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 531 532 /* 533 * Initialize driver parameters 534 */ 535 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 536 igb_error(igb, "Failed to initialize driver settings"); 537 goto attach_fail; 538 } 539 540 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 541 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 542 goto attach_fail; 543 } 544 545 /* 546 * Initialize mutexes for this device. 547 * Do this before enabling the interrupt handler and 548 * register the softint to avoid the condition where 549 * interrupt handler can try using uninitialized mutex 550 */ 551 igb_init_locks(igb); 552 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 553 554 /* 555 * Initialize the adapter 556 */ 557 if (igb_init(igb) != IGB_SUCCESS) { 558 igb_error(igb, "Failed to initialize adapter"); 559 goto attach_fail; 560 } 561 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 562 563 /* 564 * Initialize statistics 565 */ 566 if (igb_init_stats(igb) != IGB_SUCCESS) { 567 igb_error(igb, "Failed to initialize statistics"); 568 goto attach_fail; 569 } 570 igb->attach_progress |= ATTACH_PROGRESS_STATS; 571 572 /* 573 * Register the driver to the MAC 574 */ 575 if (igb_register_mac(igb) != IGB_SUCCESS) { 576 igb_error(igb, "Failed to register MAC"); 577 goto attach_fail; 578 } 579 igb->attach_progress |= ATTACH_PROGRESS_MAC; 580 581 /* 582 * Now that mutex locks are initialized, and the chip is also 583 * initialized, enable interrupts. 584 */ 585 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 586 igb_error(igb, "Failed to enable DDI interrupts"); 587 goto attach_fail; 588 } 589 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 590 591 igb_log(igb, "%s", igb_version); 592 atomic_or_32(&igb->igb_state, IGB_INITIALIZED); 593 594 /* 595 * Newer models have Energy Efficient Ethernet, let's disable this by 596 * default. 597 */ 598 if (igb->hw.mac.type == e1000_i350) 599 (void) e1000_set_eee_i350(&igb->hw); 600 else if (igb->hw.mac.type == e1000_i354) 601 (void) e1000_set_eee_i354(&igb->hw); 602 603 return (DDI_SUCCESS); 604 605 attach_fail: 606 igb_unconfigure(devinfo, igb); 607 return (DDI_FAILURE); 608 } 609 610 /* 611 * igb_detach - driver detach 612 * 613 * The detach() function is the complement of the attach routine. 614 * If cmd is set to DDI_DETACH, detach() is used to remove the 615 * state associated with a given instance of a device node 616 * prior to the removal of that instance from the system. 617 * 618 * The detach() function will be called once for each instance 619 * of the device for which there has been a successful attach() 620 * once there are no longer any opens on the device. 621 * 622 * Interrupts routine are disabled, All memory allocated by this 623 * driver are freed. 624 */ 625 static int 626 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 627 { 628 igb_t *igb; 629 630 /* 631 * Check detach command 632 */ 633 switch (cmd) { 634 default: 635 return (DDI_FAILURE); 636 637 case DDI_SUSPEND: 638 return (igb_suspend(devinfo)); 639 640 case DDI_DETACH: 641 break; 642 } 643 644 645 /* 646 * Get the pointer to the driver private data structure 647 */ 648 igb = (igb_t *)ddi_get_driver_private(devinfo); 649 if (igb == NULL) 650 return (DDI_FAILURE); 651 652 /* 653 * Unregister MAC. If failed, we have to fail the detach 654 */ 655 if (mac_unregister(igb->mac_hdl) != 0) { 656 igb_error(igb, "Failed to unregister MAC"); 657 return (DDI_FAILURE); 658 } 659 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 660 661 /* 662 * If the device is still running, it needs to be stopped first. 663 * This check is necessary because under some specific circumstances, 664 * the detach routine can be called without stopping the interface 665 * first. 666 */ 667 mutex_enter(&igb->gen_lock); 668 if (igb->igb_state & IGB_STARTED) { 669 atomic_and_32(&igb->igb_state, ~IGB_STARTED); 670 igb_stop(igb, B_TRUE); 671 mutex_exit(&igb->gen_lock); 672 /* Disable and stop the watchdog timer */ 673 igb_disable_watchdog_timer(igb); 674 } else 675 mutex_exit(&igb->gen_lock); 676 677 /* 678 * Check if there are still rx buffers held by the upper layer. 679 * If so, fail the detach. 680 */ 681 if (!igb_rx_drain(igb)) 682 return (DDI_FAILURE); 683 684 /* 685 * Do the remaining unconfigure routines 686 */ 687 igb_unconfigure(devinfo, igb); 688 689 return (DDI_SUCCESS); 690 } 691 692 /* 693 * quiesce(9E) entry point. 694 * 695 * This function is called when the system is single-threaded at high 696 * PIL with preemption disabled. Therefore, this function must not be 697 * blocked. 698 * 699 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 700 * DDI_FAILURE indicates an error condition and should almost never happen. 701 */ 702 static int 703 igb_quiesce(dev_info_t *devinfo) 704 { 705 igb_t *igb; 706 struct e1000_hw *hw; 707 708 igb = (igb_t *)ddi_get_driver_private(devinfo); 709 710 if (igb == NULL) 711 return (DDI_FAILURE); 712 713 hw = &igb->hw; 714 715 /* 716 * Disable the adapter interrupts 717 */ 718 igb_disable_adapter_interrupts(igb); 719 720 /* Tell firmware driver is no longer in control */ 721 igb_release_driver_control(hw); 722 723 /* 724 * Reset the chipset 725 */ 726 (void) e1000_reset_hw(hw); 727 728 /* 729 * Reset PHY if possible 730 */ 731 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 732 (void) e1000_phy_hw_reset(hw); 733 734 return (DDI_SUCCESS); 735 } 736 737 /* 738 * igb_unconfigure - release all resources held by this instance 739 */ 740 static void 741 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 742 { 743 /* 744 * Disable interrupt 745 */ 746 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 747 (void) igb_disable_intrs(igb); 748 } 749 750 /* 751 * Unregister MAC 752 */ 753 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 754 (void) mac_unregister(igb->mac_hdl); 755 } 756 757 /* 758 * Free statistics 759 */ 760 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 761 kstat_delete((kstat_t *)igb->igb_ks); 762 } 763 764 /* 765 * Remove interrupt handlers 766 */ 767 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 768 igb_rem_intr_handlers(igb); 769 } 770 771 /* 772 * Remove interrupts 773 */ 774 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 775 igb_rem_intrs(igb); 776 } 777 778 /* 779 * Remove driver properties 780 */ 781 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 782 (void) ddi_prop_remove_all(devinfo); 783 } 784 785 /* 786 * Stop the adapter 787 */ 788 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) { 789 mutex_enter(&igb->gen_lock); 790 igb_stop_adapter(igb); 791 mutex_exit(&igb->gen_lock); 792 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 793 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 794 } 795 796 /* 797 * Free multicast table 798 */ 799 igb_release_multicast(igb); 800 801 /* 802 * Free register handle 803 */ 804 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 805 if (igb->osdep.reg_handle != NULL) 806 ddi_regs_map_free(&igb->osdep.reg_handle); 807 } 808 809 /* 810 * Free PCI config handle 811 */ 812 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 813 if (igb->osdep.cfg_handle != NULL) 814 pci_config_teardown(&igb->osdep.cfg_handle); 815 } 816 817 /* 818 * Free locks 819 */ 820 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 821 igb_destroy_locks(igb); 822 } 823 824 /* 825 * Free the rx/tx rings 826 */ 827 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 828 igb_free_rings(igb); 829 } 830 831 /* 832 * Remove FMA 833 */ 834 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 835 igb_fm_fini(igb); 836 } 837 838 /* 839 * Free the driver data structure 840 */ 841 kmem_free(igb, sizeof (igb_t)); 842 843 ddi_set_driver_private(devinfo, NULL); 844 } 845 846 /* 847 * igb_register_mac - Register the driver and its function pointers with 848 * the GLD interface 849 */ 850 static int 851 igb_register_mac(igb_t *igb) 852 { 853 struct e1000_hw *hw = &igb->hw; 854 mac_register_t *mac; 855 int status; 856 857 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 858 return (IGB_FAILURE); 859 860 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 861 mac->m_driver = igb; 862 mac->m_dip = igb->dip; 863 mac->m_src_addr = hw->mac.addr; 864 mac->m_callbacks = &igb_m_callbacks; 865 mac->m_min_sdu = 0; 866 mac->m_max_sdu = igb->max_frame_size - 867 sizeof (struct ether_vlan_header) - ETHERFCSL; 868 mac->m_margin = VLAN_TAGSZ; 869 mac->m_priv_props = igb_priv_props; 870 mac->m_v12n = MAC_VIRT_LEVEL1; 871 872 status = mac_register(mac, &igb->mac_hdl); 873 874 mac_free(mac); 875 876 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 877 } 878 879 /* 880 * igb_identify_hardware - Identify the type of the chipset 881 */ 882 static int 883 igb_identify_hardware(igb_t *igb) 884 { 885 struct e1000_hw *hw = &igb->hw; 886 struct igb_osdep *osdep = &igb->osdep; 887 888 /* 889 * Get the device id 890 */ 891 hw->vendor_id = 892 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 893 hw->device_id = 894 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 895 hw->revision_id = 896 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 897 hw->subsystem_device_id = 898 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 899 hw->subsystem_vendor_id = 900 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 901 902 /* 903 * Set the mac type of the adapter based on the device id 904 */ 905 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 906 return (IGB_FAILURE); 907 } 908 909 /* 910 * Install adapter capabilities based on mac type 911 */ 912 switch (hw->mac.type) { 913 case e1000_82575: 914 igb->capab = &igb_82575_cap; 915 break; 916 case e1000_82576: 917 igb->capab = &igb_82576_cap; 918 break; 919 case e1000_82580: 920 igb->capab = &igb_82580_cap; 921 break; 922 case e1000_i350: 923 igb->capab = &igb_i350_cap; 924 break; 925 case e1000_i210: 926 case e1000_i211: 927 igb->capab = &igb_i210_cap; 928 break; 929 case e1000_i354: 930 igb->capab = &igb_i354_cap; 931 break; 932 default: 933 return (IGB_FAILURE); 934 } 935 936 return (IGB_SUCCESS); 937 } 938 939 /* 940 * igb_regs_map - Map the device registers 941 */ 942 static int 943 igb_regs_map(igb_t *igb) 944 { 945 dev_info_t *devinfo = igb->dip; 946 struct e1000_hw *hw = &igb->hw; 947 struct igb_osdep *osdep = &igb->osdep; 948 off_t mem_size; 949 950 /* 951 * First get the size of device registers to be mapped. 952 */ 953 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) != 954 DDI_SUCCESS) { 955 return (IGB_FAILURE); 956 } 957 958 /* 959 * Call ddi_regs_map_setup() to map registers 960 */ 961 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET, 962 (caddr_t *)&hw->hw_addr, 0, 963 mem_size, &igb_regs_acc_attr, 964 &osdep->reg_handle)) != DDI_SUCCESS) { 965 return (IGB_FAILURE); 966 } 967 968 return (IGB_SUCCESS); 969 } 970 971 /* 972 * igb_init_properties - Initialize driver properties 973 */ 974 static void 975 igb_init_properties(igb_t *igb) 976 { 977 /* 978 * Get conf file properties, including link settings 979 * jumbo frames, ring number, descriptor number, etc. 980 */ 981 igb_get_conf(igb); 982 } 983 984 /* 985 * igb_init_driver_settings - Initialize driver settings 986 * 987 * The settings include hardware function pointers, bus information, 988 * rx/tx rings settings, link state, and any other parameters that 989 * need to be setup during driver initialization. 990 */ 991 static int 992 igb_init_driver_settings(igb_t *igb) 993 { 994 struct e1000_hw *hw = &igb->hw; 995 igb_rx_ring_t *rx_ring; 996 igb_tx_ring_t *tx_ring; 997 uint32_t rx_size; 998 uint32_t tx_size; 999 int i; 1000 1001 /* 1002 * Initialize chipset specific hardware function pointers 1003 */ 1004 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 1005 return (IGB_FAILURE); 1006 } 1007 1008 /* 1009 * Get bus information 1010 */ 1011 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 1012 return (IGB_FAILURE); 1013 } 1014 1015 /* 1016 * Get the system page size 1017 */ 1018 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1); 1019 1020 /* 1021 * Set rx buffer size 1022 * The IP header alignment room is counted in the calculation. 1023 * The rx buffer size is in unit of 1K that is required by the 1024 * chipset hardware. 1025 */ 1026 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 1027 igb->rx_buf_size = ((rx_size >> 10) + 1028 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 1029 1030 /* 1031 * Set tx buffer size 1032 */ 1033 tx_size = igb->max_frame_size; 1034 igb->tx_buf_size = ((tx_size >> 10) + 1035 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 1036 1037 /* 1038 * Initialize rx/tx rings parameters 1039 */ 1040 for (i = 0; i < igb->num_rx_rings; i++) { 1041 rx_ring = &igb->rx_rings[i]; 1042 rx_ring->index = i; 1043 rx_ring->igb = igb; 1044 } 1045 1046 for (i = 0; i < igb->num_tx_rings; i++) { 1047 tx_ring = &igb->tx_rings[i]; 1048 tx_ring->index = i; 1049 tx_ring->igb = igb; 1050 if (igb->tx_head_wb_enable) 1051 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 1052 else 1053 tx_ring->tx_recycle = igb_tx_recycle_legacy; 1054 1055 tx_ring->ring_size = igb->tx_ring_size; 1056 tx_ring->free_list_size = igb->tx_ring_size + 1057 (igb->tx_ring_size >> 1); 1058 } 1059 1060 /* 1061 * Initialize values of interrupt throttling rates 1062 */ 1063 for (i = 1; i < MAX_NUM_EITR; i++) 1064 igb->intr_throttling[i] = igb->intr_throttling[0]; 1065 1066 /* 1067 * The initial link state should be "unknown" 1068 */ 1069 igb->link_state = LINK_STATE_UNKNOWN; 1070 1071 return (IGB_SUCCESS); 1072 } 1073 1074 /* 1075 * igb_init_locks - Initialize locks 1076 */ 1077 static void 1078 igb_init_locks(igb_t *igb) 1079 { 1080 igb_rx_ring_t *rx_ring; 1081 igb_tx_ring_t *tx_ring; 1082 int i; 1083 1084 for (i = 0; i < igb->num_rx_rings; i++) { 1085 rx_ring = &igb->rx_rings[i]; 1086 mutex_init(&rx_ring->rx_lock, NULL, 1087 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1088 } 1089 1090 for (i = 0; i < igb->num_tx_rings; i++) { 1091 tx_ring = &igb->tx_rings[i]; 1092 mutex_init(&tx_ring->tx_lock, NULL, 1093 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1094 mutex_init(&tx_ring->recycle_lock, NULL, 1095 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1096 mutex_init(&tx_ring->tcb_head_lock, NULL, 1097 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1098 mutex_init(&tx_ring->tcb_tail_lock, NULL, 1099 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1100 } 1101 1102 mutex_init(&igb->gen_lock, NULL, 1103 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1104 1105 mutex_init(&igb->watchdog_lock, NULL, 1106 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1107 1108 mutex_init(&igb->link_lock, NULL, 1109 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1110 } 1111 1112 /* 1113 * igb_destroy_locks - Destroy locks 1114 */ 1115 static void 1116 igb_destroy_locks(igb_t *igb) 1117 { 1118 igb_rx_ring_t *rx_ring; 1119 igb_tx_ring_t *tx_ring; 1120 int i; 1121 1122 for (i = 0; i < igb->num_rx_rings; i++) { 1123 rx_ring = &igb->rx_rings[i]; 1124 mutex_destroy(&rx_ring->rx_lock); 1125 } 1126 1127 for (i = 0; i < igb->num_tx_rings; i++) { 1128 tx_ring = &igb->tx_rings[i]; 1129 mutex_destroy(&tx_ring->tx_lock); 1130 mutex_destroy(&tx_ring->recycle_lock); 1131 mutex_destroy(&tx_ring->tcb_head_lock); 1132 mutex_destroy(&tx_ring->tcb_tail_lock); 1133 } 1134 1135 mutex_destroy(&igb->gen_lock); 1136 mutex_destroy(&igb->watchdog_lock); 1137 mutex_destroy(&igb->link_lock); 1138 } 1139 1140 static int 1141 igb_resume(dev_info_t *devinfo) 1142 { 1143 igb_t *igb; 1144 1145 igb = (igb_t *)ddi_get_driver_private(devinfo); 1146 if (igb == NULL) 1147 return (DDI_FAILURE); 1148 1149 mutex_enter(&igb->gen_lock); 1150 1151 /* 1152 * Enable interrupts 1153 */ 1154 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1155 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 1156 igb_error(igb, "Failed to enable DDI interrupts"); 1157 mutex_exit(&igb->gen_lock); 1158 return (DDI_FAILURE); 1159 } 1160 } 1161 1162 if (igb->igb_state & IGB_STARTED) { 1163 if (igb_start(igb, B_FALSE) != IGB_SUCCESS) { 1164 mutex_exit(&igb->gen_lock); 1165 return (DDI_FAILURE); 1166 } 1167 1168 /* 1169 * Enable and start the watchdog timer 1170 */ 1171 igb_enable_watchdog_timer(igb); 1172 } 1173 1174 atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED); 1175 1176 mutex_exit(&igb->gen_lock); 1177 1178 return (DDI_SUCCESS); 1179 } 1180 1181 static int 1182 igb_suspend(dev_info_t *devinfo) 1183 { 1184 igb_t *igb; 1185 1186 igb = (igb_t *)ddi_get_driver_private(devinfo); 1187 if (igb == NULL) 1188 return (DDI_FAILURE); 1189 1190 mutex_enter(&igb->gen_lock); 1191 1192 atomic_or_32(&igb->igb_state, IGB_SUSPENDED); 1193 1194 /* 1195 * Disable interrupts 1196 */ 1197 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1198 (void) igb_disable_intrs(igb); 1199 } 1200 1201 if (!(igb->igb_state & IGB_STARTED)) { 1202 mutex_exit(&igb->gen_lock); 1203 return (DDI_SUCCESS); 1204 } 1205 1206 igb_stop(igb, B_FALSE); 1207 1208 mutex_exit(&igb->gen_lock); 1209 1210 /* 1211 * Disable and stop the watchdog timer 1212 */ 1213 igb_disable_watchdog_timer(igb); 1214 1215 return (DDI_SUCCESS); 1216 } 1217 1218 static int 1219 igb_init(igb_t *igb) 1220 { 1221 mutex_enter(&igb->gen_lock); 1222 1223 /* 1224 * Initilize the adapter 1225 */ 1226 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1227 mutex_exit(&igb->gen_lock); 1228 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1229 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1230 return (IGB_FAILURE); 1231 } 1232 1233 mutex_exit(&igb->gen_lock); 1234 1235 return (IGB_SUCCESS); 1236 } 1237 1238 /* 1239 * igb_init_mac_address - Initialize the default MAC address 1240 * 1241 * On success, the MAC address is entered in the igb->hw.mac.addr 1242 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive 1243 * address register. 1244 * 1245 * Important side effects: 1246 * 1. adapter is reset - this is required to put it in a known state. 1247 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where 1248 * MAC address and all default settings are stored, so a valid checksum 1249 * is required. 1250 */ 1251 static int 1252 igb_init_mac_address(igb_t *igb) 1253 { 1254 struct e1000_hw *hw = &igb->hw; 1255 1256 ASSERT(mutex_owned(&igb->gen_lock)); 1257 1258 /* 1259 * Reset chipset to put the hardware in a known state 1260 * before we try to get MAC address from NVM. 1261 */ 1262 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1263 igb_error(igb, "Adapter reset failed."); 1264 goto init_mac_fail; 1265 } 1266 1267 /* 1268 * NVM validation 1269 */ 1270 if (((igb->hw.mac.type != e1000_i210) && 1271 (igb->hw.mac.type != e1000_i211)) && 1272 (e1000_validate_nvm_checksum(hw) < 0)) { 1273 /* 1274 * Some PCI-E parts fail the first check due to 1275 * the link being in sleep state. Call it again, 1276 * if it fails a second time its a real issue. 1277 */ 1278 if (e1000_validate_nvm_checksum(hw) < 0) { 1279 igb_error(igb, 1280 "Invalid NVM checksum. Please contact " 1281 "the vendor to update the NVM."); 1282 goto init_mac_fail; 1283 } 1284 } 1285 1286 /* 1287 * Get the mac address 1288 * This function should handle SPARC case correctly. 1289 */ 1290 if (!igb_find_mac_address(igb)) { 1291 igb_error(igb, "Failed to get the mac address"); 1292 goto init_mac_fail; 1293 } 1294 1295 /* Validate mac address */ 1296 if (!is_valid_mac_addr(hw->mac.addr)) { 1297 igb_error(igb, "Invalid mac address"); 1298 goto init_mac_fail; 1299 } 1300 1301 return (IGB_SUCCESS); 1302 1303 init_mac_fail: 1304 return (IGB_FAILURE); 1305 } 1306 1307 /* 1308 * igb_init_adapter - Initialize the adapter 1309 */ 1310 static int 1311 igb_init_adapter(igb_t *igb) 1312 { 1313 struct e1000_hw *hw = &igb->hw; 1314 uint32_t pba; 1315 int oemid[2]; 1316 uint16_t nvmword; 1317 uint32_t hwm; 1318 uint32_t default_mtu; 1319 u8 pbanum[E1000_PBANUM_LENGTH]; 1320 char eepromver[5]; /* f.ff */ 1321 int i; 1322 1323 ASSERT(mutex_owned(&igb->gen_lock)); 1324 1325 /* 1326 * In order to obtain the default MAC address, this will reset the 1327 * adapter and validate the NVM that the address and many other 1328 * default settings come from. 1329 */ 1330 if (igb_init_mac_address(igb) != IGB_SUCCESS) { 1331 igb_error(igb, "Failed to initialize MAC address"); 1332 goto init_adapter_fail; 1333 } 1334 1335 /* 1336 * Packet Buffer Allocation (PBA) 1337 * Writing PBA sets the receive portion of the buffer 1338 * the remainder is used for the transmit buffer. 1339 */ 1340 switch (hw->mac.type) { 1341 case e1000_82575: 1342 pba = E1000_PBA_32K; 1343 break; 1344 case e1000_82576: 1345 pba = E1000_READ_REG(hw, E1000_RXPBS); 1346 pba &= E1000_RXPBS_SIZE_MASK_82576; 1347 break; 1348 case e1000_82580: 1349 case e1000_i350: 1350 case e1000_i354: 1351 pba = E1000_READ_REG(hw, E1000_RXPBS); 1352 pba = e1000_rxpbs_adjust_82580(pba); 1353 break; 1354 case e1000_i210: 1355 case e1000_i211: 1356 pba = E1000_PBA_34K; 1357 default: 1358 break; 1359 } 1360 1361 /* Special needs in case of Jumbo frames */ 1362 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 1363 MIN_MTU, MAX_MTU, DEFAULT_MTU); 1364 if ((hw->mac.type == e1000_82575) && (default_mtu > ETHERMTU)) { 1365 u32 tx_space, min_tx, min_rx; 1366 pba = E1000_READ_REG(hw, E1000_PBA); 1367 tx_space = pba >> 16; 1368 pba &= 0xffff; 1369 min_tx = (igb->max_frame_size + 1370 sizeof (struct e1000_tx_desc) - ETHERNET_FCS_SIZE) * 2; 1371 min_tx = roundup(min_tx, 1024); 1372 min_tx >>= 10; 1373 min_rx = igb->max_frame_size; 1374 min_rx = roundup(min_rx, 1024); 1375 min_rx >>= 10; 1376 if (tx_space < min_tx && 1377 ((min_tx - tx_space) < pba)) { 1378 pba = pba - (min_tx - tx_space); 1379 /* 1380 * if short on rx space, rx wins 1381 * and must trump tx adjustment 1382 */ 1383 if (pba < min_rx) 1384 pba = min_rx; 1385 } 1386 E1000_WRITE_REG(hw, E1000_PBA, pba); 1387 } 1388 1389 DEBUGOUT1("igb_init: pba=%dK", pba); 1390 1391 /* 1392 * These parameters control the automatic generation (Tx) and 1393 * response (Rx) to Ethernet PAUSE frames. 1394 * - High water mark should allow for at least two frames to be 1395 * received after sending an XOFF. 1396 * - Low water mark works best when it is very near the high water mark. 1397 * This allows the receiver to restart by sending XON when it has 1398 * drained a bit. 1399 */ 1400 hwm = min(((pba << 10) * 9 / 10), 1401 ((pba << 10) - 2 * igb->max_frame_size)); 1402 1403 if (hw->mac.type < e1000_82576) { 1404 hw->fc.high_water = hwm & 0xFFF8; /* 8-byte granularity */ 1405 hw->fc.low_water = hw->fc.high_water - 8; 1406 } else { 1407 hw->fc.high_water = hwm & 0xFFF0; /* 16-byte granularity */ 1408 hw->fc.low_water = hw->fc.high_water - 16; 1409 } 1410 1411 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1412 hw->fc.send_xon = B_TRUE; 1413 1414 (void) e1000_validate_mdi_setting(hw); 1415 1416 /* 1417 * Reset the chipset hardware the second time to put PBA settings 1418 * into effect. 1419 */ 1420 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1421 igb_error(igb, "Second reset failed"); 1422 goto init_adapter_fail; 1423 } 1424 1425 /* 1426 * Don't wait for auto-negotiation to complete 1427 */ 1428 hw->phy.autoneg_wait_to_complete = B_FALSE; 1429 1430 /* 1431 * Copper options 1432 */ 1433 if (hw->phy.media_type == e1000_media_type_copper) { 1434 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1435 hw->phy.disable_polarity_correction = B_FALSE; 1436 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1437 } 1438 1439 /* 1440 * Initialize link settings 1441 */ 1442 (void) igb_setup_link(igb, B_FALSE); 1443 1444 /* 1445 * Configure/Initialize hardware 1446 */ 1447 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1448 igb_error(igb, "Failed to initialize hardware"); 1449 goto init_adapter_fail; 1450 } 1451 1452 /* 1453 * Start the link setup timer 1454 */ 1455 igb_start_link_timer(igb); 1456 1457 /* 1458 * Disable wakeup control by default 1459 */ 1460 E1000_WRITE_REG(hw, E1000_WUC, 0); 1461 1462 /* 1463 * Record phy info in hw struct 1464 */ 1465 (void) e1000_get_phy_info(hw); 1466 1467 /* 1468 * Make sure driver has control 1469 */ 1470 igb_get_driver_control(hw); 1471 1472 /* 1473 * Restore LED settings to the default from EEPROM 1474 * to meet the standard for Sun platforms. 1475 */ 1476 (void) e1000_cleanup_led(hw); 1477 1478 /* 1479 * Setup MSI-X interrupts 1480 */ 1481 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1482 igb->capab->setup_msix(igb); 1483 1484 /* 1485 * Initialize unicast addresses. 1486 */ 1487 igb_init_unicst(igb); 1488 1489 /* 1490 * Setup and initialize the mctable structures. 1491 */ 1492 igb_setup_multicst(igb); 1493 1494 /* 1495 * Set interrupt throttling rate 1496 */ 1497 for (i = 0; i < igb->intr_cnt; i++) 1498 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1499 1500 /* 1501 * Read identifying information and place in devinfo. 1502 */ 1503 nvmword = 0xffff; 1504 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_0, 1, &nvmword); 1505 oemid[0] = (int)nvmword; 1506 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_1, 1, &nvmword); 1507 oemid[1] = (int)nvmword; 1508 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, igb->dip, 1509 "oem-identifier", oemid, 2); 1510 1511 pbanum[0] = '\0'; 1512 (void) e1000_read_pba_string(&igb->hw, pbanum, sizeof (pbanum)); 1513 if (*pbanum != '\0') { 1514 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip, 1515 "printed-board-assembly", (char *)pbanum); 1516 } 1517 1518 nvmword = 0xffff; 1519 (void) e1000_read_nvm(&igb->hw, NVM_VERSION, 1, &nvmword); 1520 if ((nvmword & 0xf00) == 0) { 1521 (void) snprintf(eepromver, sizeof (eepromver), "%x.%x", 1522 (nvmword & 0xf000) >> 12, (nvmword & 0xff)); 1523 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip, 1524 "nvm-version", eepromver); 1525 } 1526 1527 /* 1528 * Save the state of the phy 1529 */ 1530 igb_get_phy_state(igb); 1531 1532 igb_param_sync(igb); 1533 1534 return (IGB_SUCCESS); 1535 1536 init_adapter_fail: 1537 /* 1538 * Reset PHY if possible 1539 */ 1540 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1541 (void) e1000_phy_hw_reset(hw); 1542 1543 return (IGB_FAILURE); 1544 } 1545 1546 /* 1547 * igb_stop_adapter - Stop the adapter 1548 */ 1549 static void 1550 igb_stop_adapter(igb_t *igb) 1551 { 1552 struct e1000_hw *hw = &igb->hw; 1553 1554 ASSERT(mutex_owned(&igb->gen_lock)); 1555 1556 /* Stop the link setup timer */ 1557 igb_stop_link_timer(igb); 1558 1559 /* Tell firmware driver is no longer in control */ 1560 igb_release_driver_control(hw); 1561 1562 /* 1563 * Reset the chipset 1564 */ 1565 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1566 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1567 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1568 } 1569 1570 /* 1571 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient 1572 */ 1573 } 1574 1575 /* 1576 * igb_reset - Reset the chipset and restart the driver. 1577 * 1578 * It involves stopping and re-starting the chipset, 1579 * and re-configuring the rx/tx rings. 1580 */ 1581 static int 1582 igb_reset(igb_t *igb) 1583 { 1584 int i; 1585 1586 mutex_enter(&igb->gen_lock); 1587 1588 ASSERT(igb->igb_state & IGB_STARTED); 1589 atomic_and_32(&igb->igb_state, ~IGB_STARTED); 1590 1591 /* 1592 * Disable the adapter interrupts to stop any rx/tx activities 1593 * before draining pending data and resetting hardware. 1594 */ 1595 igb_disable_adapter_interrupts(igb); 1596 1597 /* 1598 * Drain the pending transmit packets 1599 */ 1600 (void) igb_tx_drain(igb); 1601 1602 for (i = 0; i < igb->num_rx_rings; i++) 1603 mutex_enter(&igb->rx_rings[i].rx_lock); 1604 for (i = 0; i < igb->num_tx_rings; i++) 1605 mutex_enter(&igb->tx_rings[i].tx_lock); 1606 1607 /* 1608 * Stop the adapter 1609 */ 1610 igb_stop_adapter(igb); 1611 1612 /* 1613 * Clean the pending tx data/resources 1614 */ 1615 igb_tx_clean(igb); 1616 1617 /* 1618 * Start the adapter 1619 */ 1620 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1621 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1622 goto reset_failure; 1623 } 1624 1625 /* 1626 * Setup the rx/tx rings 1627 */ 1628 igb->tx_ring_init = B_FALSE; 1629 igb_setup_rings(igb); 1630 1631 atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL)); 1632 1633 /* 1634 * Enable adapter interrupts 1635 * The interrupts must be enabled after the driver state is START 1636 */ 1637 igb->capab->enable_intr(igb); 1638 1639 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1640 goto reset_failure; 1641 1642 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1643 goto reset_failure; 1644 1645 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1646 mutex_exit(&igb->tx_rings[i].tx_lock); 1647 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1648 mutex_exit(&igb->rx_rings[i].rx_lock); 1649 1650 atomic_or_32(&igb->igb_state, IGB_STARTED); 1651 1652 mutex_exit(&igb->gen_lock); 1653 1654 return (IGB_SUCCESS); 1655 1656 reset_failure: 1657 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1658 mutex_exit(&igb->tx_rings[i].tx_lock); 1659 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1660 mutex_exit(&igb->rx_rings[i].rx_lock); 1661 1662 mutex_exit(&igb->gen_lock); 1663 1664 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1665 1666 return (IGB_FAILURE); 1667 } 1668 1669 /* 1670 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1671 */ 1672 static void 1673 igb_tx_clean(igb_t *igb) 1674 { 1675 igb_tx_ring_t *tx_ring; 1676 tx_control_block_t *tcb; 1677 link_list_t pending_list; 1678 uint32_t desc_num; 1679 int i, j; 1680 1681 LINK_LIST_INIT(&pending_list); 1682 1683 for (i = 0; i < igb->num_tx_rings; i++) { 1684 tx_ring = &igb->tx_rings[i]; 1685 1686 mutex_enter(&tx_ring->recycle_lock); 1687 1688 /* 1689 * Clean the pending tx data - the pending packets in the 1690 * work_list that have no chances to be transmitted again. 1691 * 1692 * We must ensure the chipset is stopped or the link is down 1693 * before cleaning the transmit packets. 1694 */ 1695 desc_num = 0; 1696 for (j = 0; j < tx_ring->ring_size; j++) { 1697 tcb = tx_ring->work_list[j]; 1698 if (tcb != NULL) { 1699 desc_num += tcb->desc_num; 1700 1701 tx_ring->work_list[j] = NULL; 1702 1703 igb_free_tcb(tcb); 1704 1705 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1706 } 1707 } 1708 1709 if (desc_num > 0) { 1710 atomic_add_32(&tx_ring->tbd_free, desc_num); 1711 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1712 1713 /* 1714 * Reset the head and tail pointers of the tbd ring; 1715 * Reset the head write-back if it is enabled. 1716 */ 1717 tx_ring->tbd_head = 0; 1718 tx_ring->tbd_tail = 0; 1719 if (igb->tx_head_wb_enable) 1720 *tx_ring->tbd_head_wb = 0; 1721 1722 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1723 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1724 } 1725 1726 mutex_exit(&tx_ring->recycle_lock); 1727 1728 /* 1729 * Add the tx control blocks in the pending list to 1730 * the free list. 1731 */ 1732 igb_put_free_list(tx_ring, &pending_list); 1733 } 1734 } 1735 1736 /* 1737 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1738 */ 1739 static boolean_t 1740 igb_tx_drain(igb_t *igb) 1741 { 1742 igb_tx_ring_t *tx_ring; 1743 boolean_t done; 1744 int i, j; 1745 1746 /* 1747 * Wait for a specific time to allow pending tx packets 1748 * to be transmitted. 1749 * 1750 * Check the counter tbd_free to see if transmission is done. 1751 * No lock protection is needed here. 1752 * 1753 * Return B_TRUE if all pending packets have been transmitted; 1754 * Otherwise return B_FALSE; 1755 */ 1756 for (i = 0; i < TX_DRAIN_TIME; i++) { 1757 1758 done = B_TRUE; 1759 for (j = 0; j < igb->num_tx_rings; j++) { 1760 tx_ring = &igb->tx_rings[j]; 1761 done = done && 1762 (tx_ring->tbd_free == tx_ring->ring_size); 1763 } 1764 1765 if (done) 1766 break; 1767 1768 msec_delay(1); 1769 } 1770 1771 return (done); 1772 } 1773 1774 /* 1775 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1776 */ 1777 static boolean_t 1778 igb_rx_drain(igb_t *igb) 1779 { 1780 boolean_t done; 1781 int i; 1782 1783 /* 1784 * Polling the rx free list to check if those rx buffers held by 1785 * the upper layer are released. 1786 * 1787 * Check the counter rcb_free to see if all pending buffers are 1788 * released. No lock protection is needed here. 1789 * 1790 * Return B_TRUE if all pending buffers have been released; 1791 * Otherwise return B_FALSE; 1792 */ 1793 for (i = 0; i < RX_DRAIN_TIME; i++) { 1794 done = (igb->rcb_pending == 0); 1795 1796 if (done) 1797 break; 1798 1799 msec_delay(1); 1800 } 1801 1802 return (done); 1803 } 1804 1805 /* 1806 * igb_start - Start the driver/chipset 1807 */ 1808 int 1809 igb_start(igb_t *igb, boolean_t alloc_buffer) 1810 { 1811 int i; 1812 1813 ASSERT(mutex_owned(&igb->gen_lock)); 1814 1815 if (alloc_buffer) { 1816 if (igb_alloc_rx_data(igb) != IGB_SUCCESS) { 1817 igb_error(igb, 1818 "Failed to allocate software receive rings"); 1819 return (IGB_FAILURE); 1820 } 1821 1822 /* Allocate buffers for all the rx/tx rings */ 1823 if (igb_alloc_dma(igb) != IGB_SUCCESS) { 1824 igb_error(igb, "Failed to allocate DMA resource"); 1825 return (IGB_FAILURE); 1826 } 1827 1828 igb->tx_ring_init = B_TRUE; 1829 } else { 1830 igb->tx_ring_init = B_FALSE; 1831 } 1832 1833 for (i = 0; i < igb->num_rx_rings; i++) 1834 mutex_enter(&igb->rx_rings[i].rx_lock); 1835 for (i = 0; i < igb->num_tx_rings; i++) 1836 mutex_enter(&igb->tx_rings[i].tx_lock); 1837 1838 /* 1839 * Start the adapter 1840 */ 1841 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) { 1842 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1843 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1844 goto start_failure; 1845 } 1846 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 1847 } 1848 1849 /* 1850 * Setup the rx/tx rings 1851 */ 1852 igb_setup_rings(igb); 1853 1854 /* 1855 * Enable adapter interrupts 1856 * The interrupts must be enabled after the driver state is START 1857 */ 1858 igb->capab->enable_intr(igb); 1859 1860 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1861 goto start_failure; 1862 1863 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1864 goto start_failure; 1865 1866 if (igb->hw.mac.type == e1000_i350) 1867 (void) e1000_set_eee_i350(&igb->hw); 1868 else if (igb->hw.mac.type == e1000_i354) 1869 (void) e1000_set_eee_i354(&igb->hw); 1870 1871 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1872 mutex_exit(&igb->tx_rings[i].tx_lock); 1873 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1874 mutex_exit(&igb->rx_rings[i].rx_lock); 1875 1876 return (IGB_SUCCESS); 1877 1878 start_failure: 1879 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1880 mutex_exit(&igb->tx_rings[i].tx_lock); 1881 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1882 mutex_exit(&igb->rx_rings[i].rx_lock); 1883 1884 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1885 1886 return (IGB_FAILURE); 1887 } 1888 1889 /* 1890 * igb_stop - Stop the driver/chipset 1891 */ 1892 void 1893 igb_stop(igb_t *igb, boolean_t free_buffer) 1894 { 1895 int i; 1896 1897 ASSERT(mutex_owned(&igb->gen_lock)); 1898 1899 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER; 1900 1901 /* 1902 * Disable the adapter interrupts 1903 */ 1904 igb_disable_adapter_interrupts(igb); 1905 1906 /* 1907 * Drain the pending tx packets 1908 */ 1909 (void) igb_tx_drain(igb); 1910 1911 for (i = 0; i < igb->num_rx_rings; i++) 1912 mutex_enter(&igb->rx_rings[i].rx_lock); 1913 for (i = 0; i < igb->num_tx_rings; i++) 1914 mutex_enter(&igb->tx_rings[i].tx_lock); 1915 1916 /* 1917 * Stop the adapter 1918 */ 1919 igb_stop_adapter(igb); 1920 1921 /* 1922 * Clean the pending tx data/resources 1923 */ 1924 igb_tx_clean(igb); 1925 1926 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1927 mutex_exit(&igb->tx_rings[i].tx_lock); 1928 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1929 mutex_exit(&igb->rx_rings[i].rx_lock); 1930 1931 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1932 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1933 1934 if (igb->link_state == LINK_STATE_UP) { 1935 igb->link_state = LINK_STATE_UNKNOWN; 1936 mac_link_update(igb->mac_hdl, igb->link_state); 1937 } 1938 1939 if (free_buffer) { 1940 /* 1941 * Release the DMA/memory resources of rx/tx rings 1942 */ 1943 igb_free_dma(igb); 1944 igb_free_rx_data(igb); 1945 } 1946 } 1947 1948 /* 1949 * igb_alloc_rings - Allocate memory space for rx/tx rings 1950 */ 1951 static int 1952 igb_alloc_rings(igb_t *igb) 1953 { 1954 /* 1955 * Allocate memory space for rx rings 1956 */ 1957 igb->rx_rings = kmem_zalloc( 1958 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1959 KM_NOSLEEP); 1960 1961 if (igb->rx_rings == NULL) { 1962 return (IGB_FAILURE); 1963 } 1964 1965 /* 1966 * Allocate memory space for tx rings 1967 */ 1968 igb->tx_rings = kmem_zalloc( 1969 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1970 KM_NOSLEEP); 1971 1972 if (igb->tx_rings == NULL) { 1973 kmem_free(igb->rx_rings, 1974 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1975 igb->rx_rings = NULL; 1976 return (IGB_FAILURE); 1977 } 1978 1979 /* 1980 * Allocate memory space for rx ring groups 1981 */ 1982 igb->rx_groups = kmem_zalloc( 1983 sizeof (igb_rx_group_t) * igb->num_rx_groups, 1984 KM_NOSLEEP); 1985 1986 if (igb->rx_groups == NULL) { 1987 kmem_free(igb->rx_rings, 1988 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1989 kmem_free(igb->tx_rings, 1990 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1991 igb->rx_rings = NULL; 1992 igb->tx_rings = NULL; 1993 return (IGB_FAILURE); 1994 } 1995 1996 return (IGB_SUCCESS); 1997 } 1998 1999 /* 2000 * igb_free_rings - Free the memory space of rx/tx rings. 2001 */ 2002 static void 2003 igb_free_rings(igb_t *igb) 2004 { 2005 if (igb->rx_rings != NULL) { 2006 kmem_free(igb->rx_rings, 2007 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 2008 igb->rx_rings = NULL; 2009 } 2010 2011 if (igb->tx_rings != NULL) { 2012 kmem_free(igb->tx_rings, 2013 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 2014 igb->tx_rings = NULL; 2015 } 2016 2017 if (igb->rx_groups != NULL) { 2018 kmem_free(igb->rx_groups, 2019 sizeof (igb_rx_group_t) * igb->num_rx_groups); 2020 igb->rx_groups = NULL; 2021 } 2022 } 2023 2024 static int 2025 igb_alloc_rx_data(igb_t *igb) 2026 { 2027 igb_rx_ring_t *rx_ring; 2028 int i; 2029 2030 for (i = 0; i < igb->num_rx_rings; i++) { 2031 rx_ring = &igb->rx_rings[i]; 2032 if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS) 2033 goto alloc_rx_rings_failure; 2034 } 2035 return (IGB_SUCCESS); 2036 2037 alloc_rx_rings_failure: 2038 igb_free_rx_data(igb); 2039 return (IGB_FAILURE); 2040 } 2041 2042 static void 2043 igb_free_rx_data(igb_t *igb) 2044 { 2045 igb_rx_ring_t *rx_ring; 2046 igb_rx_data_t *rx_data; 2047 int i; 2048 2049 for (i = 0; i < igb->num_rx_rings; i++) { 2050 rx_ring = &igb->rx_rings[i]; 2051 2052 mutex_enter(&igb->rx_pending_lock); 2053 rx_data = rx_ring->rx_data; 2054 2055 if (rx_data != NULL) { 2056 rx_data->flag |= IGB_RX_STOPPED; 2057 2058 if (rx_data->rcb_pending == 0) { 2059 igb_free_rx_ring_data(rx_data); 2060 rx_ring->rx_data = NULL; 2061 } 2062 } 2063 2064 mutex_exit(&igb->rx_pending_lock); 2065 } 2066 } 2067 2068 /* 2069 * igb_setup_rings - Setup rx/tx rings 2070 */ 2071 static void 2072 igb_setup_rings(igb_t *igb) 2073 { 2074 /* 2075 * Setup the rx/tx rings, including the following: 2076 * 2077 * 1. Setup the descriptor ring and the control block buffers; 2078 * 2. Initialize necessary registers for receive/transmit; 2079 * 3. Initialize software pointers/parameters for receive/transmit; 2080 */ 2081 igb_setup_rx(igb); 2082 2083 igb_setup_tx(igb); 2084 } 2085 2086 static void 2087 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 2088 { 2089 igb_t *igb = rx_ring->igb; 2090 igb_rx_data_t *rx_data = rx_ring->rx_data; 2091 struct e1000_hw *hw = &igb->hw; 2092 rx_control_block_t *rcb; 2093 union e1000_adv_rx_desc *rbd; 2094 uint32_t size; 2095 uint32_t buf_low; 2096 uint32_t buf_high; 2097 uint32_t rxdctl; 2098 int i; 2099 2100 ASSERT(mutex_owned(&rx_ring->rx_lock)); 2101 ASSERT(mutex_owned(&igb->gen_lock)); 2102 2103 /* 2104 * Initialize descriptor ring with buffer addresses 2105 */ 2106 for (i = 0; i < igb->rx_ring_size; i++) { 2107 rcb = rx_data->work_list[i]; 2108 rbd = &rx_data->rbd_ring[i]; 2109 2110 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 2111 rbd->read.hdr_addr = NULL; 2112 } 2113 2114 /* 2115 * Initialize the base address registers 2116 */ 2117 buf_low = (uint32_t)rx_data->rbd_area.dma_address; 2118 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32); 2119 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 2120 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 2121 2122 /* 2123 * Initialize the length register 2124 */ 2125 size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc); 2126 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 2127 2128 /* 2129 * Initialize buffer size & descriptor type 2130 */ 2131 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), 2132 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 2133 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF)); 2134 2135 /* 2136 * Setup the Receive Descriptor Control Register (RXDCTL) 2137 */ 2138 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 2139 rxdctl &= igb->capab->rxdctl_mask; 2140 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 2141 rxdctl |= 16; /* pthresh */ 2142 rxdctl |= 8 << 8; /* hthresh */ 2143 rxdctl |= 1 << 16; /* wthresh */ 2144 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl); 2145 2146 rx_data->rbd_next = 0; 2147 } 2148 2149 static void 2150 igb_setup_rx(igb_t *igb) 2151 { 2152 igb_rx_ring_t *rx_ring; 2153 igb_rx_data_t *rx_data; 2154 igb_rx_group_t *rx_group; 2155 struct e1000_hw *hw = &igb->hw; 2156 uint32_t rctl, rxcsum; 2157 uint32_t ring_per_group; 2158 int i; 2159 2160 /* 2161 * Setup the Receive Control Register (RCTL), and enable the 2162 * receiver. The initial configuration is to: enable the receiver, 2163 * accept broadcasts, discard bad packets, accept long packets, 2164 * disable VLAN filter checking, and set receive buffer size to 2165 * 2k. For 82575, also set the receive descriptor minimum 2166 * threshold size to 1/2 the ring. 2167 */ 2168 rctl = E1000_READ_REG(hw, E1000_RCTL); 2169 2170 /* 2171 * Clear the field used for wakeup control. This driver doesn't do 2172 * wakeup but leave this here for completeness. 2173 */ 2174 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2175 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 2176 2177 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 2178 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 2179 E1000_RCTL_LPE | /* Large Packet Enable */ 2180 /* Multicast filter offset */ 2181 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 2182 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */ 2183 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 2184 2185 for (i = 0; i < igb->num_rx_groups; i++) { 2186 rx_group = &igb->rx_groups[i]; 2187 rx_group->index = i; 2188 rx_group->igb = igb; 2189 } 2190 2191 /* 2192 * Set up all rx descriptor rings - must be called before receive unit 2193 * enabled. 2194 */ 2195 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2196 for (i = 0; i < igb->num_rx_rings; i++) { 2197 rx_ring = &igb->rx_rings[i]; 2198 igb_setup_rx_ring(rx_ring); 2199 2200 /* 2201 * Map a ring to a group by assigning a group index 2202 */ 2203 rx_ring->group_index = i / ring_per_group; 2204 } 2205 2206 /* 2207 * Setup the Rx Long Packet Max Length register 2208 */ 2209 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 2210 2211 /* 2212 * Hardware checksum settings 2213 */ 2214 if (igb->rx_hcksum_enable) { 2215 rxcsum = 2216 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 2217 E1000_RXCSUM_IPOFL; /* IP checksum */ 2218 2219 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2220 } 2221 2222 /* 2223 * Setup classify and RSS for multiple receive queues 2224 */ 2225 switch (igb->vmdq_mode) { 2226 case E1000_VMDQ_OFF: 2227 /* 2228 * One ring group, only RSS is needed when more than 2229 * one ring enabled. 2230 */ 2231 if (igb->num_rx_rings > 1) 2232 igb_setup_rss(igb); 2233 break; 2234 case E1000_VMDQ_MAC: 2235 /* 2236 * Multiple groups, each group has one ring, 2237 * only the MAC classification is needed. 2238 */ 2239 igb_setup_mac_classify(igb); 2240 break; 2241 case E1000_VMDQ_MAC_RSS: 2242 /* 2243 * Multiple groups and multiple rings, both 2244 * MAC classification and RSS are needed. 2245 */ 2246 igb_setup_mac_rss_classify(igb); 2247 break; 2248 } 2249 2250 /* 2251 * Enable the receive unit - must be done after all 2252 * the rx setup above. 2253 */ 2254 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2255 2256 /* 2257 * Initialize all adapter ring head & tail pointers - must 2258 * be done after receive unit is enabled 2259 */ 2260 for (i = 0; i < igb->num_rx_rings; i++) { 2261 rx_ring = &igb->rx_rings[i]; 2262 rx_data = rx_ring->rx_data; 2263 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 2264 E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1); 2265 } 2266 2267 /* 2268 * 82575 with manageability enabled needs a special flush to make 2269 * sure the fifos start clean. 2270 */ 2271 if ((hw->mac.type == e1000_82575) && 2272 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) { 2273 e1000_rx_fifo_flush_82575(hw); 2274 } 2275 } 2276 2277 static void 2278 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 2279 { 2280 igb_t *igb = tx_ring->igb; 2281 struct e1000_hw *hw = &igb->hw; 2282 uint32_t size; 2283 uint32_t buf_low; 2284 uint32_t buf_high; 2285 uint32_t reg_val; 2286 2287 ASSERT(mutex_owned(&tx_ring->tx_lock)); 2288 ASSERT(mutex_owned(&igb->gen_lock)); 2289 2290 2291 /* 2292 * Initialize the length register 2293 */ 2294 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 2295 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 2296 2297 /* 2298 * Initialize the base address registers 2299 */ 2300 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 2301 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 2302 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 2303 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 2304 2305 /* 2306 * Setup head & tail pointers 2307 */ 2308 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 2309 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 2310 2311 /* 2312 * Setup head write-back 2313 */ 2314 if (igb->tx_head_wb_enable) { 2315 /* 2316 * The memory of the head write-back is allocated using 2317 * the extra tbd beyond the tail of the tbd ring. 2318 */ 2319 tx_ring->tbd_head_wb = (uint32_t *) 2320 ((uintptr_t)tx_ring->tbd_area.address + size); 2321 *tx_ring->tbd_head_wb = 0; 2322 2323 buf_low = (uint32_t) 2324 (tx_ring->tbd_area.dma_address + size); 2325 buf_high = (uint32_t) 2326 ((tx_ring->tbd_area.dma_address + size) >> 32); 2327 2328 /* Set the head write-back enable bit */ 2329 buf_low |= E1000_TX_HEAD_WB_ENABLE; 2330 2331 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 2332 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 2333 2334 /* 2335 * Turn off relaxed ordering for head write back or it will 2336 * cause problems with the tx recycling 2337 */ 2338 reg_val = E1000_READ_REG(hw, 2339 E1000_DCA_TXCTRL(tx_ring->index)); 2340 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 2341 E1000_WRITE_REG(hw, 2342 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 2343 } else { 2344 tx_ring->tbd_head_wb = NULL; 2345 } 2346 2347 tx_ring->tbd_head = 0; 2348 tx_ring->tbd_tail = 0; 2349 tx_ring->tbd_free = tx_ring->ring_size; 2350 2351 if (igb->tx_ring_init == B_TRUE) { 2352 tx_ring->tcb_head = 0; 2353 tx_ring->tcb_tail = 0; 2354 tx_ring->tcb_free = tx_ring->free_list_size; 2355 } 2356 2357 /* 2358 * Enable TXDCTL per queue 2359 */ 2360 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); 2361 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; 2362 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); 2363 2364 /* 2365 * Initialize hardware checksum offload settings 2366 */ 2367 bzero(&tx_ring->tx_context, sizeof (tx_context_t)); 2368 } 2369 2370 static void 2371 igb_setup_tx(igb_t *igb) 2372 { 2373 igb_tx_ring_t *tx_ring; 2374 struct e1000_hw *hw = &igb->hw; 2375 uint32_t reg_val; 2376 int i; 2377 2378 for (i = 0; i < igb->num_tx_rings; i++) { 2379 tx_ring = &igb->tx_rings[i]; 2380 igb_setup_tx_ring(tx_ring); 2381 } 2382 2383 /* 2384 * Setup the Transmit Control Register (TCTL) 2385 */ 2386 reg_val = E1000_READ_REG(hw, E1000_TCTL); 2387 reg_val &= ~E1000_TCTL_CT; 2388 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2389 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2390 2391 /* Enable transmits */ 2392 reg_val |= E1000_TCTL_EN; 2393 2394 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 2395 } 2396 2397 /* 2398 * igb_setup_rss - Setup receive-side scaling feature 2399 */ 2400 static void 2401 igb_setup_rss(igb_t *igb) 2402 { 2403 struct e1000_hw *hw = &igb->hw; 2404 uint32_t i, mrqc, rxcsum; 2405 int shift = 0; 2406 uint32_t random; 2407 union e1000_reta { 2408 uint32_t dword; 2409 uint8_t bytes[4]; 2410 } reta; 2411 2412 /* Setup the Redirection Table */ 2413 if (hw->mac.type == e1000_82576) { 2414 shift = 3; 2415 } else if (hw->mac.type == e1000_82575) { 2416 shift = 6; 2417 } 2418 for (i = 0; i < (32 * 4); i++) { 2419 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 2420 if ((i & 3) == 3) { 2421 E1000_WRITE_REG(hw, 2422 (E1000_RETA(0) + (i & ~3)), reta.dword); 2423 } 2424 } 2425 2426 /* Fill out hash function seeds */ 2427 for (i = 0; i < 10; i++) { 2428 (void) random_get_pseudo_bytes((uint8_t *)&random, 2429 sizeof (uint32_t)); 2430 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2431 } 2432 2433 /* Setup the Multiple Receive Queue Control register */ 2434 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2435 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2436 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2437 E1000_MRQC_RSS_FIELD_IPV6 | 2438 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2439 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2440 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2441 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2442 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2443 2444 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2445 2446 /* 2447 * Disable Packet Checksum to enable RSS for multiple receive queues. 2448 * 2449 * The Packet Checksum is not ethernet CRC. It is another kind of 2450 * checksum offloading provided by the 82575 chipset besides the IP 2451 * header checksum offloading and the TCP/UDP checksum offloading. 2452 * The Packet Checksum is by default computed over the entire packet 2453 * from the first byte of the DA through the last byte of the CRC, 2454 * including the Ethernet and IP headers. 2455 * 2456 * It is a hardware limitation that Packet Checksum is mutually 2457 * exclusive with RSS. 2458 */ 2459 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2460 rxcsum |= E1000_RXCSUM_PCSD; 2461 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2462 } 2463 2464 /* 2465 * igb_setup_mac_rss_classify - Setup MAC classification and rss 2466 */ 2467 static void 2468 igb_setup_mac_rss_classify(igb_t *igb) 2469 { 2470 struct e1000_hw *hw = &igb->hw; 2471 uint32_t i, mrqc, vmdctl, rxcsum; 2472 uint32_t ring_per_group; 2473 int shift_group0, shift_group1; 2474 uint32_t random; 2475 union e1000_reta { 2476 uint32_t dword; 2477 uint8_t bytes[4]; 2478 } reta; 2479 2480 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2481 2482 /* Setup the Redirection Table, it is shared between two groups */ 2483 shift_group0 = 2; 2484 shift_group1 = 6; 2485 for (i = 0; i < (32 * 4); i++) { 2486 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) | 2487 ((ring_per_group + (i % ring_per_group)) << shift_group1); 2488 if ((i & 3) == 3) { 2489 E1000_WRITE_REG(hw, 2490 (E1000_RETA(0) + (i & ~3)), reta.dword); 2491 } 2492 } 2493 2494 /* Fill out hash function seeds */ 2495 for (i = 0; i < 10; i++) { 2496 (void) random_get_pseudo_bytes((uint8_t *)&random, 2497 sizeof (uint32_t)); 2498 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2499 } 2500 2501 /* 2502 * Setup the Multiple Receive Queue Control register, 2503 * enable VMDq based on packet destination MAC address and RSS. 2504 */ 2505 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP; 2506 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2507 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2508 E1000_MRQC_RSS_FIELD_IPV6 | 2509 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2510 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2511 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2512 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2513 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2514 2515 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2516 2517 2518 /* Define the default group and default queues */ 2519 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE; 2520 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl); 2521 2522 /* 2523 * Disable Packet Checksum to enable RSS for multiple receive queues. 2524 * 2525 * The Packet Checksum is not ethernet CRC. It is another kind of 2526 * checksum offloading provided by the 82575 chipset besides the IP 2527 * header checksum offloading and the TCP/UDP checksum offloading. 2528 * The Packet Checksum is by default computed over the entire packet 2529 * from the first byte of the DA through the last byte of the CRC, 2530 * including the Ethernet and IP headers. 2531 * 2532 * It is a hardware limitation that Packet Checksum is mutually 2533 * exclusive with RSS. 2534 */ 2535 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2536 rxcsum |= E1000_RXCSUM_PCSD; 2537 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2538 } 2539 2540 /* 2541 * igb_setup_mac_classify - Setup MAC classification feature 2542 */ 2543 static void 2544 igb_setup_mac_classify(igb_t *igb) 2545 { 2546 struct e1000_hw *hw = &igb->hw; 2547 uint32_t mrqc, rxcsum; 2548 2549 /* 2550 * Setup the Multiple Receive Queue Control register, 2551 * enable VMDq based on packet destination MAC address. 2552 */ 2553 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP; 2554 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2555 2556 /* 2557 * Disable Packet Checksum to enable RSS for multiple receive queues. 2558 * 2559 * The Packet Checksum is not ethernet CRC. It is another kind of 2560 * checksum offloading provided by the 82575 chipset besides the IP 2561 * header checksum offloading and the TCP/UDP checksum offloading. 2562 * The Packet Checksum is by default computed over the entire packet 2563 * from the first byte of the DA through the last byte of the CRC, 2564 * including the Ethernet and IP headers. 2565 * 2566 * It is a hardware limitation that Packet Checksum is mutually 2567 * exclusive with RSS. 2568 */ 2569 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2570 rxcsum |= E1000_RXCSUM_PCSD; 2571 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2572 2573 } 2574 2575 /* 2576 * igb_init_unicst - Initialize the unicast addresses 2577 */ 2578 static void 2579 igb_init_unicst(igb_t *igb) 2580 { 2581 struct e1000_hw *hw = &igb->hw; 2582 int slot; 2583 2584 /* 2585 * Here we should consider two situations: 2586 * 2587 * 1. Chipset is initialized the first time 2588 * Initialize the multiple unicast addresses, and 2589 * save the default MAC address. 2590 * 2591 * 2. Chipset is reset 2592 * Recover the multiple unicast addresses from the 2593 * software data structure to the RAR registers. 2594 */ 2595 2596 /* 2597 * Clear the default MAC address in the RAR0 rgister, 2598 * which is loaded from EEPROM when system boot or chipreset, 2599 * this will cause the conficts with add_mac/rem_mac entry 2600 * points when VMDq is enabled. For this reason, the RAR0 2601 * must be cleared for both cases mentioned above. 2602 */ 2603 e1000_rar_clear(hw, 0); 2604 2605 if (!igb->unicst_init) { 2606 2607 /* Initialize the multiple unicast addresses */ 2608 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2609 igb->unicst_avail = igb->unicst_total; 2610 2611 for (slot = 0; slot < igb->unicst_total; slot++) 2612 igb->unicst_addr[slot].mac.set = 0; 2613 2614 igb->unicst_init = B_TRUE; 2615 } else { 2616 /* Re-configure the RAR registers */ 2617 for (slot = 0; slot < igb->unicst_total; slot++) { 2618 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr, 2619 slot, igb->vmdq_mode, 2620 igb->unicst_addr[slot].mac.group_index); 2621 } 2622 } 2623 } 2624 2625 /* 2626 * igb_unicst_find - Find the slot for the specified unicast address 2627 */ 2628 int 2629 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr) 2630 { 2631 int slot; 2632 2633 ASSERT(mutex_owned(&igb->gen_lock)); 2634 2635 for (slot = 0; slot < igb->unicst_total; slot++) { 2636 if (bcmp(igb->unicst_addr[slot].mac.addr, 2637 mac_addr, ETHERADDRL) == 0) 2638 return (slot); 2639 } 2640 2641 return (-1); 2642 } 2643 2644 /* 2645 * igb_unicst_set - Set the unicast address to the specified slot 2646 */ 2647 int 2648 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2649 int slot) 2650 { 2651 struct e1000_hw *hw = &igb->hw; 2652 2653 ASSERT(mutex_owned(&igb->gen_lock)); 2654 2655 /* 2656 * Save the unicast address in the software data structure 2657 */ 2658 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2659 2660 /* 2661 * Set the unicast address to the RAR register 2662 */ 2663 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2664 2665 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2666 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2667 return (EIO); 2668 } 2669 2670 return (0); 2671 } 2672 2673 /* 2674 * igb_multicst_add - Add a multicst address 2675 */ 2676 int 2677 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2678 { 2679 struct ether_addr *new_table; 2680 size_t new_len; 2681 size_t old_len; 2682 2683 ASSERT(mutex_owned(&igb->gen_lock)); 2684 2685 if ((multiaddr[0] & 01) == 0) { 2686 igb_error(igb, "Illegal multicast address"); 2687 return (EINVAL); 2688 } 2689 2690 if (igb->mcast_count >= igb->mcast_max_num) { 2691 igb_error(igb, "Adapter requested more than %d mcast addresses", 2692 igb->mcast_max_num); 2693 return (ENOENT); 2694 } 2695 2696 if (igb->mcast_count == igb->mcast_alloc_count) { 2697 old_len = igb->mcast_alloc_count * 2698 sizeof (struct ether_addr); 2699 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) * 2700 sizeof (struct ether_addr); 2701 2702 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2703 if (new_table == NULL) { 2704 igb_error(igb, 2705 "Not enough memory to alloc mcast table"); 2706 return (ENOMEM); 2707 } 2708 2709 if (igb->mcast_table != NULL) { 2710 bcopy(igb->mcast_table, new_table, old_len); 2711 kmem_free(igb->mcast_table, old_len); 2712 } 2713 igb->mcast_alloc_count += MCAST_ALLOC_COUNT; 2714 igb->mcast_table = new_table; 2715 } 2716 2717 bcopy(multiaddr, 2718 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2719 igb->mcast_count++; 2720 2721 /* 2722 * Update the multicast table in the hardware 2723 */ 2724 igb_setup_multicst(igb); 2725 2726 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2727 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2728 return (EIO); 2729 } 2730 2731 return (0); 2732 } 2733 2734 /* 2735 * igb_multicst_remove - Remove a multicst address 2736 */ 2737 int 2738 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2739 { 2740 struct ether_addr *new_table; 2741 size_t new_len; 2742 size_t old_len; 2743 int i; 2744 2745 ASSERT(mutex_owned(&igb->gen_lock)); 2746 2747 for (i = 0; i < igb->mcast_count; i++) { 2748 if (bcmp(multiaddr, &igb->mcast_table[i], 2749 ETHERADDRL) == 0) { 2750 for (i++; i < igb->mcast_count; i++) { 2751 igb->mcast_table[i - 1] = 2752 igb->mcast_table[i]; 2753 } 2754 igb->mcast_count--; 2755 break; 2756 } 2757 } 2758 2759 if ((igb->mcast_alloc_count - igb->mcast_count) > 2760 MCAST_ALLOC_COUNT) { 2761 old_len = igb->mcast_alloc_count * 2762 sizeof (struct ether_addr); 2763 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) * 2764 sizeof (struct ether_addr); 2765 2766 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2767 if (new_table != NULL) { 2768 bcopy(igb->mcast_table, new_table, new_len); 2769 kmem_free(igb->mcast_table, old_len); 2770 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT; 2771 igb->mcast_table = new_table; 2772 } 2773 } 2774 2775 /* 2776 * Update the multicast table in the hardware 2777 */ 2778 igb_setup_multicst(igb); 2779 2780 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2781 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2782 return (EIO); 2783 } 2784 2785 return (0); 2786 } 2787 2788 static void 2789 igb_release_multicast(igb_t *igb) 2790 { 2791 if (igb->mcast_table != NULL) { 2792 kmem_free(igb->mcast_table, 2793 igb->mcast_alloc_count * sizeof (struct ether_addr)); 2794 igb->mcast_table = NULL; 2795 } 2796 } 2797 2798 /* 2799 * igb_setup_multicast - setup multicast data structures 2800 * 2801 * This routine initializes all of the multicast related structures 2802 * and save them in the hardware registers. 2803 */ 2804 static void 2805 igb_setup_multicst(igb_t *igb) 2806 { 2807 uint8_t *mc_addr_list; 2808 uint32_t mc_addr_count; 2809 struct e1000_hw *hw = &igb->hw; 2810 2811 ASSERT(mutex_owned(&igb->gen_lock)); 2812 ASSERT(igb->mcast_count <= igb->mcast_max_num); 2813 2814 mc_addr_list = (uint8_t *)igb->mcast_table; 2815 mc_addr_count = igb->mcast_count; 2816 2817 /* 2818 * Update the multicase addresses to the MTA registers 2819 */ 2820 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count); 2821 } 2822 2823 /* 2824 * igb_get_conf - Get driver configurations set in driver.conf 2825 * 2826 * This routine gets user-configured values out of the configuration 2827 * file igb.conf. 2828 * 2829 * For each configurable value, there is a minimum, a maximum, and a 2830 * default. 2831 * If user does not configure a value, use the default. 2832 * If user configures below the minimum, use the minumum. 2833 * If user configures above the maximum, use the maxumum. 2834 */ 2835 static void 2836 igb_get_conf(igb_t *igb) 2837 { 2838 struct e1000_hw *hw = &igb->hw; 2839 uint32_t default_mtu; 2840 uint32_t flow_control; 2841 uint32_t ring_per_group; 2842 int i; 2843 2844 /* 2845 * igb driver supports the following user configurations: 2846 * 2847 * Link configurations: 2848 * adv_autoneg_cap 2849 * adv_1000fdx_cap 2850 * adv_100fdx_cap 2851 * adv_100hdx_cap 2852 * adv_10fdx_cap 2853 * adv_10hdx_cap 2854 * Note: 1000hdx is not supported. 2855 * 2856 * Jumbo frame configuration: 2857 * default_mtu 2858 * 2859 * Ethernet flow control configuration: 2860 * flow_control 2861 * 2862 * Multiple rings configurations: 2863 * tx_queue_number 2864 * tx_ring_size 2865 * rx_queue_number 2866 * rx_ring_size 2867 * 2868 * Call igb_get_prop() to get the value for a specific 2869 * configuration parameter. 2870 */ 2871 2872 /* 2873 * Link configurations 2874 */ 2875 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2876 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2877 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2878 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2879 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2880 PROP_ADV_100FDX_CAP, 0, 1, 1); 2881 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2882 PROP_ADV_100HDX_CAP, 0, 1, 1); 2883 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2884 PROP_ADV_10FDX_CAP, 0, 1, 1); 2885 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2886 PROP_ADV_10HDX_CAP, 0, 1, 1); 2887 2888 /* 2889 * Jumbo frame configurations 2890 */ 2891 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2892 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2893 2894 igb->max_frame_size = default_mtu + 2895 sizeof (struct ether_vlan_header) + ETHERFCSL; 2896 2897 /* 2898 * Ethernet flow control configuration 2899 */ 2900 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2901 e1000_fc_none, 4, e1000_fc_full); 2902 if (flow_control == 4) 2903 flow_control = e1000_fc_default; 2904 2905 hw->fc.requested_mode = flow_control; 2906 2907 /* 2908 * Multiple rings configurations 2909 */ 2910 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2911 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2912 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2913 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2914 2915 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0); 2916 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM, 2917 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2918 /* 2919 * Currently we do not support VMDq for 82576 and 82580. 2920 * If it is e1000_82576, set num_rx_groups to 1. 2921 */ 2922 if (hw->mac.type >= e1000_82576) 2923 igb->num_rx_groups = 1; 2924 2925 if (igb->mr_enable) { 2926 igb->num_tx_rings = igb->capab->def_tx_que_num; 2927 igb->num_rx_rings = igb->capab->def_rx_que_num; 2928 } else { 2929 igb->num_tx_rings = 1; 2930 igb->num_rx_rings = 1; 2931 2932 if (igb->num_rx_groups > 1) { 2933 igb_error(igb, 2934 "Invalid rx groups number. Please enable multiple " 2935 "rings first"); 2936 igb->num_rx_groups = 1; 2937 } 2938 } 2939 2940 /* 2941 * Check the divisibility between rx rings and rx groups. 2942 */ 2943 for (i = igb->num_rx_groups; i > 0; i--) { 2944 if ((igb->num_rx_rings % i) == 0) 2945 break; 2946 } 2947 if (i != igb->num_rx_groups) { 2948 igb_error(igb, 2949 "Invalid rx groups number. Downgrade the rx group " 2950 "number to %d.", i); 2951 igb->num_rx_groups = i; 2952 } 2953 2954 /* 2955 * Get the ring number per group. 2956 */ 2957 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2958 2959 if (igb->num_rx_groups == 1) { 2960 /* 2961 * One rx ring group, the rx ring number is num_rx_rings. 2962 */ 2963 igb->vmdq_mode = E1000_VMDQ_OFF; 2964 } else if (ring_per_group == 1) { 2965 /* 2966 * Multiple rx groups, each group has one rx ring. 2967 */ 2968 igb->vmdq_mode = E1000_VMDQ_MAC; 2969 } else { 2970 /* 2971 * Multiple groups and multiple rings. 2972 */ 2973 igb->vmdq_mode = E1000_VMDQ_MAC_RSS; 2974 } 2975 2976 /* 2977 * Tunable used to force an interrupt type. The only use is 2978 * for testing of the lesser interrupt types. 2979 * 0 = don't force interrupt type 2980 * 1 = force interrupt type MSIX 2981 * 2 = force interrupt type MSI 2982 * 3 = force interrupt type Legacy 2983 */ 2984 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2985 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2986 2987 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2988 0, 1, 1); 2989 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2990 0, 1, 1); 2991 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2992 0, 1, 1); 2993 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2994 0, 1, 1); 2995 2996 /* 2997 * igb LSO needs the tx h/w checksum support. 2998 * Here LSO will be disabled if tx h/w checksum has been disabled. 2999 */ 3000 if (igb->tx_hcksum_enable == B_FALSE) 3001 igb->lso_enable = B_FALSE; 3002 3003 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 3004 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 3005 DEFAULT_TX_COPY_THRESHOLD); 3006 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 3007 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3008 DEFAULT_TX_RECYCLE_THRESHOLD); 3009 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 3010 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 3011 DEFAULT_TX_OVERLOAD_THRESHOLD); 3012 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 3013 MIN_TX_RESCHED_THRESHOLD, 3014 MIN(igb->tx_ring_size, MAX_TX_RESCHED_THRESHOLD), 3015 igb->tx_ring_size > DEFAULT_TX_RESCHED_THRESHOLD ? 3016 DEFAULT_TX_RESCHED_THRESHOLD : DEFAULT_TX_RESCHED_THRESHOLD_LOW); 3017 3018 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 3019 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 3020 DEFAULT_RX_COPY_THRESHOLD); 3021 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 3022 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 3023 DEFAULT_RX_LIMIT_PER_INTR); 3024 3025 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 3026 igb->capab->min_intr_throttle, 3027 igb->capab->max_intr_throttle, 3028 igb->capab->def_intr_throttle); 3029 3030 /* 3031 * Max number of multicast addresses 3032 */ 3033 igb->mcast_max_num = 3034 igb_get_prop(igb, PROP_MCAST_MAX_NUM, 3035 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM); 3036 } 3037 3038 /* 3039 * igb_get_prop - Get a property value out of the configuration file igb.conf 3040 * 3041 * Caller provides the name of the property, a default value, a minimum 3042 * value, and a maximum value. 3043 * 3044 * Return configured value of the property, with default, minimum and 3045 * maximum properly applied. 3046 */ 3047 static int 3048 igb_get_prop(igb_t *igb, 3049 char *propname, /* name of the property */ 3050 int minval, /* minimum acceptable value */ 3051 int maxval, /* maximim acceptable value */ 3052 int defval) /* default value */ 3053 { 3054 int value; 3055 3056 /* 3057 * Call ddi_prop_get_int() to read the conf settings 3058 */ 3059 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 3060 DDI_PROP_DONTPASS, propname, defval); 3061 3062 if (value > maxval) 3063 value = maxval; 3064 3065 if (value < minval) 3066 value = minval; 3067 3068 return (value); 3069 } 3070 3071 /* 3072 * igb_setup_link - Using the link properties to setup the link 3073 */ 3074 int 3075 igb_setup_link(igb_t *igb, boolean_t setup_hw) 3076 { 3077 struct e1000_mac_info *mac; 3078 struct e1000_phy_info *phy; 3079 boolean_t invalid; 3080 3081 mac = &igb->hw.mac; 3082 phy = &igb->hw.phy; 3083 invalid = B_FALSE; 3084 3085 if (igb->param_adv_autoneg_cap == 1) { 3086 mac->autoneg = B_TRUE; 3087 phy->autoneg_advertised = 0; 3088 3089 /* 3090 * 1000hdx is not supported for autonegotiation 3091 */ 3092 if (igb->param_adv_1000fdx_cap == 1) 3093 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3094 3095 if (igb->param_adv_100fdx_cap == 1) 3096 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3097 3098 if (igb->param_adv_100hdx_cap == 1) 3099 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3100 3101 if (igb->param_adv_10fdx_cap == 1) 3102 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3103 3104 if (igb->param_adv_10hdx_cap == 1) 3105 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3106 3107 if (phy->autoneg_advertised == 0) 3108 invalid = B_TRUE; 3109 } else { 3110 mac->autoneg = B_FALSE; 3111 3112 /* 3113 * 1000fdx and 1000hdx are not supported for forced link 3114 */ 3115 if (igb->param_adv_100fdx_cap == 1) 3116 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3117 else if (igb->param_adv_100hdx_cap == 1) 3118 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3119 else if (igb->param_adv_10fdx_cap == 1) 3120 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3121 else if (igb->param_adv_10hdx_cap == 1) 3122 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3123 else 3124 invalid = B_TRUE; 3125 } 3126 3127 if (invalid) { 3128 igb_notice(igb, "Invalid link settings. Setup link to " 3129 "autonegotiation with full link capabilities."); 3130 mac->autoneg = B_TRUE; 3131 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3132 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3133 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3134 } 3135 3136 if (setup_hw) { 3137 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 3138 return (IGB_FAILURE); 3139 } 3140 3141 return (IGB_SUCCESS); 3142 } 3143 3144 3145 /* 3146 * igb_is_link_up - Check if the link is up 3147 */ 3148 static boolean_t 3149 igb_is_link_up(igb_t *igb) 3150 { 3151 struct e1000_hw *hw = &igb->hw; 3152 boolean_t link_up = B_FALSE; 3153 3154 ASSERT(mutex_owned(&igb->gen_lock)); 3155 3156 /* 3157 * get_link_status is set in the interrupt handler on link-status-change 3158 * or rx sequence error interrupt. get_link_status will stay 3159 * false until the e1000_check_for_link establishes link only 3160 * for copper adapters. 3161 */ 3162 switch (hw->phy.media_type) { 3163 case e1000_media_type_copper: 3164 if (hw->mac.get_link_status) { 3165 (void) e1000_check_for_link(hw); 3166 link_up = !hw->mac.get_link_status; 3167 } else { 3168 link_up = B_TRUE; 3169 } 3170 break; 3171 case e1000_media_type_fiber: 3172 (void) e1000_check_for_link(hw); 3173 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 3174 break; 3175 case e1000_media_type_internal_serdes: 3176 (void) e1000_check_for_link(hw); 3177 link_up = hw->mac.serdes_has_link; 3178 break; 3179 } 3180 3181 return (link_up); 3182 } 3183 3184 /* 3185 * igb_link_check - Link status processing 3186 */ 3187 static boolean_t 3188 igb_link_check(igb_t *igb) 3189 { 3190 struct e1000_hw *hw = &igb->hw; 3191 uint16_t speed = 0, duplex = 0; 3192 boolean_t link_changed = B_FALSE; 3193 3194 ASSERT(mutex_owned(&igb->gen_lock)); 3195 3196 if (igb_is_link_up(igb)) { 3197 /* 3198 * The Link is up, check whether it was marked as down earlier 3199 */ 3200 if (igb->link_state != LINK_STATE_UP) { 3201 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3202 igb->link_speed = speed; 3203 igb->link_duplex = duplex; 3204 igb->link_state = LINK_STATE_UP; 3205 link_changed = B_TRUE; 3206 if (!igb->link_complete) 3207 igb_stop_link_timer(igb); 3208 } 3209 } else if (igb->link_complete) { 3210 if (igb->link_state != LINK_STATE_DOWN) { 3211 igb->link_speed = 0; 3212 igb->link_duplex = 0; 3213 igb->link_state = LINK_STATE_DOWN; 3214 link_changed = B_TRUE; 3215 } 3216 } 3217 3218 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3219 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3220 return (B_FALSE); 3221 } 3222 3223 return (link_changed); 3224 } 3225 3226 /* 3227 * igb_local_timer - driver watchdog function 3228 * 3229 * This function will handle the hardware stall check, link status 3230 * check and other routines. 3231 */ 3232 static void 3233 igb_local_timer(void *arg) 3234 { 3235 igb_t *igb = (igb_t *)arg; 3236 boolean_t link_changed = B_FALSE; 3237 3238 if (igb->igb_state & IGB_ERROR) { 3239 igb->reset_count++; 3240 if (igb_reset(igb) == IGB_SUCCESS) 3241 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED); 3242 3243 igb_restart_watchdog_timer(igb); 3244 return; 3245 } 3246 3247 if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) { 3248 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 3249 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 3250 igb->reset_count++; 3251 if (igb_reset(igb) == IGB_SUCCESS) 3252 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED); 3253 3254 igb_restart_watchdog_timer(igb); 3255 return; 3256 } 3257 3258 mutex_enter(&igb->gen_lock); 3259 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED)) 3260 link_changed = igb_link_check(igb); 3261 mutex_exit(&igb->gen_lock); 3262 3263 if (link_changed) 3264 mac_link_update(igb->mac_hdl, igb->link_state); 3265 3266 igb_restart_watchdog_timer(igb); 3267 } 3268 3269 /* 3270 * igb_link_timer - link setup timer function 3271 * 3272 * It is called when the timer for link setup is expired, which indicates 3273 * the completion of the link setup. The link state will not be updated 3274 * until the link setup is completed. And the link state will not be sent 3275 * to the upper layer through mac_link_update() in this function. It will 3276 * be updated in the local timer routine or the interrupts service routine 3277 * after the interface is started (plumbed). 3278 */ 3279 static void 3280 igb_link_timer(void *arg) 3281 { 3282 igb_t *igb = (igb_t *)arg; 3283 3284 mutex_enter(&igb->link_lock); 3285 igb->link_complete = B_TRUE; 3286 igb->link_tid = 0; 3287 mutex_exit(&igb->link_lock); 3288 } 3289 /* 3290 * igb_stall_check - check for transmit stall 3291 * 3292 * This function checks if the adapter is stalled (in transmit). 3293 * 3294 * It is called each time the watchdog timeout is invoked. 3295 * If the transmit descriptor reclaim continuously fails, 3296 * the watchdog value will increment by 1. If the watchdog 3297 * value exceeds the threshold, the igb is assumed to 3298 * have stalled and need to be reset. 3299 */ 3300 static boolean_t 3301 igb_stall_check(igb_t *igb) 3302 { 3303 igb_tx_ring_t *tx_ring; 3304 struct e1000_hw *hw = &igb->hw; 3305 boolean_t result; 3306 int i; 3307 3308 if (igb->link_state != LINK_STATE_UP) 3309 return (B_FALSE); 3310 3311 /* 3312 * If any tx ring is stalled, we'll reset the chipset 3313 */ 3314 result = B_FALSE; 3315 for (i = 0; i < igb->num_tx_rings; i++) { 3316 tx_ring = &igb->tx_rings[i]; 3317 3318 if (tx_ring->recycle_fail > 0) 3319 tx_ring->stall_watchdog++; 3320 else 3321 tx_ring->stall_watchdog = 0; 3322 3323 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 3324 result = B_TRUE; 3325 if (hw->mac.type == e1000_82580) { 3326 hw->dev_spec._82575.global_device_reset 3327 = B_TRUE; 3328 } 3329 break; 3330 } 3331 } 3332 3333 if (result) { 3334 tx_ring->stall_watchdog = 0; 3335 tx_ring->recycle_fail = 0; 3336 } 3337 3338 return (result); 3339 } 3340 3341 3342 /* 3343 * is_valid_mac_addr - Check if the mac address is valid 3344 */ 3345 static boolean_t 3346 is_valid_mac_addr(uint8_t *mac_addr) 3347 { 3348 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3349 const uint8_t addr_test2[6] = 3350 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3351 3352 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3353 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3354 return (B_FALSE); 3355 3356 return (B_TRUE); 3357 } 3358 3359 static boolean_t 3360 igb_find_mac_address(igb_t *igb) 3361 { 3362 struct e1000_hw *hw = &igb->hw; 3363 #ifdef __sparc 3364 uchar_t *bytes; 3365 struct ether_addr sysaddr; 3366 uint_t nelts; 3367 int err; 3368 boolean_t found = B_FALSE; 3369 3370 /* 3371 * The "vendor's factory-set address" may already have 3372 * been extracted from the chip, but if the property 3373 * "local-mac-address" is set we use that instead. 3374 * 3375 * We check whether it looks like an array of 6 3376 * bytes (which it should, if OBP set it). If we can't 3377 * make sense of it this way, we'll ignore it. 3378 */ 3379 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3380 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3381 if (err == DDI_PROP_SUCCESS) { 3382 if (nelts == ETHERADDRL) { 3383 while (nelts--) 3384 hw->mac.addr[nelts] = bytes[nelts]; 3385 found = B_TRUE; 3386 } 3387 ddi_prop_free(bytes); 3388 } 3389 3390 /* 3391 * Look up the OBP property "local-mac-address?". If the user has set 3392 * 'local-mac-address? = false', use "the system address" instead. 3393 */ 3394 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 3395 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3396 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3397 if (localetheraddr(NULL, &sysaddr) != 0) { 3398 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 3399 found = B_TRUE; 3400 } 3401 } 3402 ddi_prop_free(bytes); 3403 } 3404 3405 /* 3406 * Finally(!), if there's a valid "mac-address" property (created 3407 * if we netbooted from this interface), we must use this instead 3408 * of any of the above to ensure that the NFS/install server doesn't 3409 * get confused by the address changing as Solaris takes over! 3410 */ 3411 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3412 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3413 if (err == DDI_PROP_SUCCESS) { 3414 if (nelts == ETHERADDRL) { 3415 while (nelts--) 3416 hw->mac.addr[nelts] = bytes[nelts]; 3417 found = B_TRUE; 3418 } 3419 ddi_prop_free(bytes); 3420 } 3421 3422 if (found) { 3423 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 3424 return (B_TRUE); 3425 } 3426 #endif 3427 3428 /* 3429 * Read the device MAC address from the EEPROM 3430 */ 3431 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 3432 return (B_FALSE); 3433 3434 return (B_TRUE); 3435 } 3436 3437 #pragma inline(igb_arm_watchdog_timer) 3438 3439 static void 3440 igb_arm_watchdog_timer(igb_t *igb) 3441 { 3442 /* 3443 * Fire a watchdog timer 3444 */ 3445 igb->watchdog_tid = 3446 timeout(igb_local_timer, 3447 (void *)igb, 1 * drv_usectohz(1000000)); 3448 3449 } 3450 3451 /* 3452 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 3453 */ 3454 void 3455 igb_enable_watchdog_timer(igb_t *igb) 3456 { 3457 mutex_enter(&igb->watchdog_lock); 3458 3459 if (!igb->watchdog_enable) { 3460 igb->watchdog_enable = B_TRUE; 3461 igb->watchdog_start = B_TRUE; 3462 igb_arm_watchdog_timer(igb); 3463 } 3464 3465 mutex_exit(&igb->watchdog_lock); 3466 3467 } 3468 3469 /* 3470 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 3471 */ 3472 void 3473 igb_disable_watchdog_timer(igb_t *igb) 3474 { 3475 timeout_id_t tid; 3476 3477 mutex_enter(&igb->watchdog_lock); 3478 3479 igb->watchdog_enable = B_FALSE; 3480 igb->watchdog_start = B_FALSE; 3481 tid = igb->watchdog_tid; 3482 igb->watchdog_tid = 0; 3483 3484 mutex_exit(&igb->watchdog_lock); 3485 3486 if (tid != 0) 3487 (void) untimeout(tid); 3488 3489 } 3490 3491 /* 3492 * igb_start_watchdog_timer - Start the driver watchdog timer 3493 */ 3494 static void 3495 igb_start_watchdog_timer(igb_t *igb) 3496 { 3497 mutex_enter(&igb->watchdog_lock); 3498 3499 if (igb->watchdog_enable) { 3500 if (!igb->watchdog_start) { 3501 igb->watchdog_start = B_TRUE; 3502 igb_arm_watchdog_timer(igb); 3503 } 3504 } 3505 3506 mutex_exit(&igb->watchdog_lock); 3507 } 3508 3509 /* 3510 * igb_restart_watchdog_timer - Restart the driver watchdog timer 3511 */ 3512 static void 3513 igb_restart_watchdog_timer(igb_t *igb) 3514 { 3515 mutex_enter(&igb->watchdog_lock); 3516 3517 if (igb->watchdog_start) 3518 igb_arm_watchdog_timer(igb); 3519 3520 mutex_exit(&igb->watchdog_lock); 3521 } 3522 3523 /* 3524 * igb_stop_watchdog_timer - Stop the driver watchdog timer 3525 */ 3526 static void 3527 igb_stop_watchdog_timer(igb_t *igb) 3528 { 3529 timeout_id_t tid; 3530 3531 mutex_enter(&igb->watchdog_lock); 3532 3533 igb->watchdog_start = B_FALSE; 3534 tid = igb->watchdog_tid; 3535 igb->watchdog_tid = 0; 3536 3537 mutex_exit(&igb->watchdog_lock); 3538 3539 if (tid != 0) 3540 (void) untimeout(tid); 3541 } 3542 3543 /* 3544 * igb_start_link_timer - Start the link setup timer 3545 */ 3546 static void 3547 igb_start_link_timer(struct igb *igb) 3548 { 3549 struct e1000_hw *hw = &igb->hw; 3550 clock_t link_timeout; 3551 3552 if (hw->mac.autoneg) 3553 link_timeout = PHY_AUTO_NEG_LIMIT * 3554 drv_usectohz(100000); 3555 else 3556 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 3557 3558 mutex_enter(&igb->link_lock); 3559 if (hw->phy.autoneg_wait_to_complete) { 3560 igb->link_complete = B_TRUE; 3561 } else { 3562 igb->link_complete = B_FALSE; 3563 igb->link_tid = timeout(igb_link_timer, (void *)igb, 3564 link_timeout); 3565 } 3566 mutex_exit(&igb->link_lock); 3567 } 3568 3569 /* 3570 * igb_stop_link_timer - Stop the link setup timer 3571 */ 3572 static void 3573 igb_stop_link_timer(struct igb *igb) 3574 { 3575 timeout_id_t tid; 3576 3577 mutex_enter(&igb->link_lock); 3578 igb->link_complete = B_TRUE; 3579 tid = igb->link_tid; 3580 igb->link_tid = 0; 3581 mutex_exit(&igb->link_lock); 3582 3583 if (tid != 0) 3584 (void) untimeout(tid); 3585 } 3586 3587 /* 3588 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 3589 */ 3590 static void 3591 igb_disable_adapter_interrupts(igb_t *igb) 3592 { 3593 struct e1000_hw *hw = &igb->hw; 3594 3595 /* 3596 * Set the IMC register to mask all the interrupts, 3597 * including the tx interrupts. 3598 */ 3599 E1000_WRITE_REG(hw, E1000_IMC, ~0); 3600 E1000_WRITE_REG(hw, E1000_IAM, 0); 3601 3602 /* 3603 * Additional disabling for MSI-X 3604 */ 3605 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3606 E1000_WRITE_REG(hw, E1000_EIMC, ~0); 3607 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3608 E1000_WRITE_REG(hw, E1000_EIAM, 0); 3609 } 3610 3611 E1000_WRITE_FLUSH(hw); 3612 } 3613 3614 /* 3615 * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580 3616 */ 3617 static void 3618 igb_enable_adapter_interrupts_82580(igb_t *igb) 3619 { 3620 struct e1000_hw *hw = &igb->hw; 3621 3622 /* Clear any pending interrupts */ 3623 (void) E1000_READ_REG(hw, E1000_ICR); 3624 igb->ims_mask |= E1000_IMS_DRSTA; 3625 3626 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3627 3628 /* Interrupt enabling for MSI-X */ 3629 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3630 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3631 igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA); 3632 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask); 3633 } else { /* Interrupt enabling for MSI and legacy */ 3634 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3635 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3636 igb->ims_mask |= E1000_IMS_DRSTA; 3637 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask); 3638 } 3639 3640 /* Disable auto-mask for ICR interrupt bits */ 3641 E1000_WRITE_REG(hw, E1000_IAM, 0); 3642 3643 E1000_WRITE_FLUSH(hw); 3644 } 3645 3646 /* 3647 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576 3648 */ 3649 static void 3650 igb_enable_adapter_interrupts_82576(igb_t *igb) 3651 { 3652 struct e1000_hw *hw = &igb->hw; 3653 3654 /* Clear any pending interrupts */ 3655 (void) E1000_READ_REG(hw, E1000_ICR); 3656 3657 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3658 3659 /* Interrupt enabling for MSI-X */ 3660 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3661 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3662 igb->ims_mask = E1000_IMS_LSC; 3663 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3664 } else { 3665 /* Interrupt enabling for MSI and legacy */ 3666 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3667 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3668 E1000_WRITE_REG(hw, E1000_IMS, 3669 (IMS_ENABLE_MASK | E1000_IMS_TXQE)); 3670 } 3671 3672 /* Disable auto-mask for ICR interrupt bits */ 3673 E1000_WRITE_REG(hw, E1000_IAM, 0); 3674 3675 E1000_WRITE_FLUSH(hw); 3676 } 3677 3678 /* 3679 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575 3680 */ 3681 static void 3682 igb_enable_adapter_interrupts_82575(igb_t *igb) 3683 { 3684 struct e1000_hw *hw = &igb->hw; 3685 uint32_t reg; 3686 3687 /* Clear any pending interrupts */ 3688 (void) E1000_READ_REG(hw, E1000_ICR); 3689 3690 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3691 /* Interrupt enabling for MSI-X */ 3692 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3693 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3694 igb->ims_mask = E1000_IMS_LSC; 3695 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3696 3697 /* Enable MSI-X PBA support */ 3698 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3699 reg |= E1000_CTRL_EXT_PBA_CLR; 3700 3701 /* Non-selective interrupt clear-on-read */ 3702 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 3703 3704 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3705 } else { 3706 /* Interrupt enabling for MSI and legacy */ 3707 igb->ims_mask = IMS_ENABLE_MASK; 3708 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3709 } 3710 3711 E1000_WRITE_FLUSH(hw); 3712 } 3713 3714 /* 3715 * Loopback Support 3716 */ 3717 static lb_property_t lb_normal = 3718 { normal, "normal", IGB_LB_NONE }; 3719 static lb_property_t lb_external = 3720 { external, "External", IGB_LB_EXTERNAL }; 3721 static lb_property_t lb_phy = 3722 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 3723 static lb_property_t lb_serdes = 3724 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 3725 3726 enum ioc_reply 3727 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 3728 { 3729 lb_info_sz_t *lbsp; 3730 lb_property_t *lbpp; 3731 struct e1000_hw *hw; 3732 uint32_t *lbmp; 3733 uint32_t size; 3734 uint32_t value; 3735 3736 hw = &igb->hw; 3737 3738 if (mp->b_cont == NULL) 3739 return (IOC_INVAL); 3740 3741 switch (iocp->ioc_cmd) { 3742 default: 3743 return (IOC_INVAL); 3744 3745 case LB_GET_INFO_SIZE: 3746 size = sizeof (lb_info_sz_t); 3747 if (iocp->ioc_count != size) 3748 return (IOC_INVAL); 3749 3750 value = sizeof (lb_normal); 3751 if (hw->phy.media_type == e1000_media_type_copper) 3752 value += sizeof (lb_phy); 3753 else 3754 value += sizeof (lb_serdes); 3755 value += sizeof (lb_external); 3756 3757 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 3758 *lbsp = value; 3759 break; 3760 3761 case LB_GET_INFO: 3762 value = sizeof (lb_normal); 3763 if (hw->phy.media_type == e1000_media_type_copper) 3764 value += sizeof (lb_phy); 3765 else 3766 value += sizeof (lb_serdes); 3767 value += sizeof (lb_external); 3768 3769 size = value; 3770 if (iocp->ioc_count != size) 3771 return (IOC_INVAL); 3772 3773 value = 0; 3774 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 3775 3776 lbpp[value++] = lb_normal; 3777 if (hw->phy.media_type == e1000_media_type_copper) 3778 lbpp[value++] = lb_phy; 3779 else 3780 lbpp[value++] = lb_serdes; 3781 lbpp[value++] = lb_external; 3782 break; 3783 3784 case LB_GET_MODE: 3785 size = sizeof (uint32_t); 3786 if (iocp->ioc_count != size) 3787 return (IOC_INVAL); 3788 3789 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3790 *lbmp = igb->loopback_mode; 3791 break; 3792 3793 case LB_SET_MODE: 3794 size = 0; 3795 if (iocp->ioc_count != sizeof (uint32_t)) 3796 return (IOC_INVAL); 3797 3798 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3799 if (!igb_set_loopback_mode(igb, *lbmp)) 3800 return (IOC_INVAL); 3801 break; 3802 } 3803 3804 iocp->ioc_count = size; 3805 iocp->ioc_error = 0; 3806 3807 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3808 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3809 return (IOC_INVAL); 3810 } 3811 3812 return (IOC_REPLY); 3813 } 3814 3815 /* 3816 * igb_set_loopback_mode - Setup loopback based on the loopback mode 3817 */ 3818 static boolean_t 3819 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 3820 { 3821 struct e1000_hw *hw; 3822 int i; 3823 3824 if (mode == igb->loopback_mode) 3825 return (B_TRUE); 3826 3827 hw = &igb->hw; 3828 3829 igb->loopback_mode = mode; 3830 3831 if (mode == IGB_LB_NONE) { 3832 /* Reset the chip */ 3833 hw->phy.autoneg_wait_to_complete = B_TRUE; 3834 (void) igb_reset(igb); 3835 hw->phy.autoneg_wait_to_complete = B_FALSE; 3836 return (B_TRUE); 3837 } 3838 3839 mutex_enter(&igb->gen_lock); 3840 3841 switch (mode) { 3842 default: 3843 mutex_exit(&igb->gen_lock); 3844 return (B_FALSE); 3845 3846 case IGB_LB_EXTERNAL: 3847 igb_set_external_loopback(igb); 3848 break; 3849 3850 case IGB_LB_INTERNAL_PHY: 3851 igb_set_internal_phy_loopback(igb); 3852 break; 3853 3854 case IGB_LB_INTERNAL_SERDES: 3855 igb_set_internal_serdes_loopback(igb); 3856 break; 3857 } 3858 3859 mutex_exit(&igb->gen_lock); 3860 3861 /* 3862 * When external loopback is set, wait up to 1000ms to get the link up. 3863 * According to test, 1000ms can work and it's an experimental value. 3864 */ 3865 if (mode == IGB_LB_EXTERNAL) { 3866 for (i = 0; i <= 10; i++) { 3867 mutex_enter(&igb->gen_lock); 3868 (void) igb_link_check(igb); 3869 mutex_exit(&igb->gen_lock); 3870 3871 if (igb->link_state == LINK_STATE_UP) 3872 break; 3873 3874 msec_delay(100); 3875 } 3876 3877 if (igb->link_state != LINK_STATE_UP) { 3878 /* 3879 * Does not support external loopback. 3880 * Reset driver to loopback none. 3881 */ 3882 igb->loopback_mode = IGB_LB_NONE; 3883 3884 /* Reset the chip */ 3885 hw->phy.autoneg_wait_to_complete = B_TRUE; 3886 (void) igb_reset(igb); 3887 hw->phy.autoneg_wait_to_complete = B_FALSE; 3888 3889 IGB_DEBUGLOG_0(igb, "Set external loopback failed, " 3890 "reset to loopback none."); 3891 3892 return (B_FALSE); 3893 } 3894 } 3895 3896 return (B_TRUE); 3897 } 3898 3899 /* 3900 * igb_set_external_loopback - Set the external loopback mode 3901 */ 3902 static void 3903 igb_set_external_loopback(igb_t *igb) 3904 { 3905 struct e1000_hw *hw; 3906 uint32_t ctrl_ext; 3907 3908 hw = &igb->hw; 3909 3910 /* Set link mode to PHY (00b) in the Extended Control register */ 3911 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3912 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3913 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3914 3915 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3916 (void) e1000_write_phy_reg(hw, 0x9, 0x1a00); 3917 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3918 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3919 } 3920 3921 /* 3922 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3923 */ 3924 static void 3925 igb_set_internal_phy_loopback(igb_t *igb) 3926 { 3927 struct e1000_hw *hw; 3928 uint32_t ctrl_ext; 3929 uint16_t phy_ctrl; 3930 uint16_t phy_pconf; 3931 3932 hw = &igb->hw; 3933 3934 /* Set link mode to PHY (00b) in the Extended Control register */ 3935 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3936 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3937 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3938 3939 /* 3940 * Set PHY control register (0x4140): 3941 * Set full duplex mode 3942 * Set loopback bit 3943 * Clear auto-neg enable bit 3944 * Set PHY speed 3945 */ 3946 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3947 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3948 3949 /* Set the link disable bit in the Port Configuration register */ 3950 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3951 phy_pconf |= (uint16_t)1 << 14; 3952 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3953 } 3954 3955 /* 3956 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3957 */ 3958 static void 3959 igb_set_internal_serdes_loopback(igb_t *igb) 3960 { 3961 struct e1000_hw *hw; 3962 uint32_t ctrl_ext; 3963 uint32_t ctrl; 3964 uint32_t pcs_lctl; 3965 uint32_t connsw; 3966 3967 hw = &igb->hw; 3968 3969 /* Set link mode to SerDes (11b) in the Extended Control register */ 3970 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3971 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3972 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3973 3974 /* Configure the SerDes to loopback */ 3975 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3976 3977 /* Set Device Control register */ 3978 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3979 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3980 E1000_CTRL_SLU); /* Force link up */ 3981 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3982 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3983 E1000_CTRL_LRST); /* Clear link reset */ 3984 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3985 3986 /* Set PCS Link Control register */ 3987 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3988 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3989 E1000_PCS_LCTL_FSD | 3990 E1000_PCS_LCTL_FDV_FULL | 3991 E1000_PCS_LCTL_FLV_LINK_UP); 3992 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3993 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3994 3995 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3996 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3997 connsw &= ~E1000_CONNSW_ENRGSRC; 3998 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3999 } 4000 4001 #pragma inline(igb_intr_rx_work) 4002 /* 4003 * igb_intr_rx_work - rx processing of ISR 4004 */ 4005 static void 4006 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 4007 { 4008 mblk_t *mp; 4009 4010 mutex_enter(&rx_ring->rx_lock); 4011 mp = igb_rx(rx_ring, IGB_NO_POLL); 4012 mutex_exit(&rx_ring->rx_lock); 4013 4014 if (mp != NULL) 4015 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp, 4016 rx_ring->ring_gen_num); 4017 } 4018 4019 #pragma inline(igb_intr_tx_work) 4020 /* 4021 * igb_intr_tx_work - tx processing of ISR 4022 */ 4023 static void 4024 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 4025 { 4026 igb_t *igb = tx_ring->igb; 4027 4028 /* Recycle the tx descriptors */ 4029 tx_ring->tx_recycle(tx_ring); 4030 4031 /* Schedule the re-transmit */ 4032 if (tx_ring->reschedule && 4033 (tx_ring->tbd_free >= igb->tx_resched_thresh)) { 4034 tx_ring->reschedule = B_FALSE; 4035 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle); 4036 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 4037 } 4038 } 4039 4040 #pragma inline(igb_intr_link_work) 4041 /* 4042 * igb_intr_link_work - link-status-change processing of ISR 4043 */ 4044 static void 4045 igb_intr_link_work(igb_t *igb) 4046 { 4047 boolean_t link_changed; 4048 4049 igb_stop_watchdog_timer(igb); 4050 4051 mutex_enter(&igb->gen_lock); 4052 4053 /* 4054 * Because we got a link-status-change interrupt, force 4055 * e1000_check_for_link() to look at phy 4056 */ 4057 igb->hw.mac.get_link_status = B_TRUE; 4058 4059 /* igb_link_check takes care of link status change */ 4060 link_changed = igb_link_check(igb); 4061 4062 /* Get new phy state */ 4063 igb_get_phy_state(igb); 4064 4065 mutex_exit(&igb->gen_lock); 4066 4067 if (link_changed) 4068 mac_link_update(igb->mac_hdl, igb->link_state); 4069 4070 igb_start_watchdog_timer(igb); 4071 } 4072 4073 /* 4074 * igb_intr_legacy - Interrupt handler for legacy interrupts 4075 */ 4076 static uint_t 4077 igb_intr_legacy(void *arg1, void *arg2) 4078 { 4079 igb_t *igb = (igb_t *)arg1; 4080 igb_tx_ring_t *tx_ring; 4081 uint32_t icr; 4082 mblk_t *mp; 4083 boolean_t tx_reschedule; 4084 boolean_t link_changed; 4085 uint_t result; 4086 4087 _NOTE(ARGUNUSED(arg2)); 4088 4089 mutex_enter(&igb->gen_lock); 4090 4091 if (igb->igb_state & IGB_SUSPENDED) { 4092 mutex_exit(&igb->gen_lock); 4093 return (DDI_INTR_UNCLAIMED); 4094 } 4095 4096 mp = NULL; 4097 tx_reschedule = B_FALSE; 4098 link_changed = B_FALSE; 4099 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4100 4101 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4102 mutex_exit(&igb->gen_lock); 4103 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4104 atomic_or_32(&igb->igb_state, IGB_ERROR); 4105 return (DDI_INTR_UNCLAIMED); 4106 } 4107 4108 if (icr & E1000_ICR_INT_ASSERTED) { 4109 /* 4110 * E1000_ICR_INT_ASSERTED bit was set: 4111 * Read(Clear) the ICR, claim this interrupt, 4112 * look for work to do. 4113 */ 4114 ASSERT(igb->num_rx_rings == 1); 4115 ASSERT(igb->num_tx_rings == 1); 4116 4117 /* Make sure all interrupt causes cleared */ 4118 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 4119 4120 if (icr & E1000_ICR_RXT0) { 4121 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL); 4122 } 4123 4124 if (icr & E1000_ICR_TXDW) { 4125 tx_ring = &igb->tx_rings[0]; 4126 4127 /* Recycle the tx descriptors */ 4128 tx_ring->tx_recycle(tx_ring); 4129 4130 /* Schedule the re-transmit */ 4131 tx_reschedule = (tx_ring->reschedule && 4132 (tx_ring->tbd_free >= igb->tx_resched_thresh)); 4133 } 4134 4135 if (icr & E1000_ICR_LSC) { 4136 /* 4137 * Because we got a link-status-change interrupt, force 4138 * e1000_check_for_link() to look at phy 4139 */ 4140 igb->hw.mac.get_link_status = B_TRUE; 4141 4142 /* igb_link_check takes care of link status change */ 4143 link_changed = igb_link_check(igb); 4144 4145 /* Get new phy state */ 4146 igb_get_phy_state(igb); 4147 } 4148 4149 if (icr & E1000_ICR_DRSTA) { 4150 /* 82580 Full Device Reset needed */ 4151 atomic_or_32(&igb->igb_state, IGB_STALL); 4152 } 4153 4154 result = DDI_INTR_CLAIMED; 4155 } else { 4156 /* 4157 * E1000_ICR_INT_ASSERTED bit was not set: 4158 * Don't claim this interrupt. 4159 */ 4160 result = DDI_INTR_UNCLAIMED; 4161 } 4162 4163 mutex_exit(&igb->gen_lock); 4164 4165 /* 4166 * Do the following work outside of the gen_lock 4167 */ 4168 if (mp != NULL) 4169 mac_rx(igb->mac_hdl, NULL, mp); 4170 4171 if (tx_reschedule) { 4172 tx_ring->reschedule = B_FALSE; 4173 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle); 4174 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 4175 } 4176 4177 if (link_changed) 4178 mac_link_update(igb->mac_hdl, igb->link_state); 4179 4180 return (result); 4181 } 4182 4183 /* 4184 * igb_intr_msi - Interrupt handler for MSI 4185 */ 4186 static uint_t 4187 igb_intr_msi(void *arg1, void *arg2) 4188 { 4189 igb_t *igb = (igb_t *)arg1; 4190 uint32_t icr; 4191 4192 _NOTE(ARGUNUSED(arg2)); 4193 4194 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4195 4196 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4197 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4198 atomic_or_32(&igb->igb_state, IGB_ERROR); 4199 return (DDI_INTR_CLAIMED); 4200 } 4201 4202 /* Make sure all interrupt causes cleared */ 4203 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 4204 4205 /* 4206 * For MSI interrupt, we have only one vector, 4207 * so we have only one rx ring and one tx ring enabled. 4208 */ 4209 ASSERT(igb->num_rx_rings == 1); 4210 ASSERT(igb->num_tx_rings == 1); 4211 4212 if (icr & E1000_ICR_RXT0) { 4213 igb_intr_rx_work(&igb->rx_rings[0]); 4214 } 4215 4216 if (icr & E1000_ICR_TXDW) { 4217 igb_intr_tx_work(&igb->tx_rings[0]); 4218 } 4219 4220 if (icr & E1000_ICR_LSC) { 4221 igb_intr_link_work(igb); 4222 } 4223 4224 if (icr & E1000_ICR_DRSTA) { 4225 /* 82580 Full Device Reset needed */ 4226 atomic_or_32(&igb->igb_state, IGB_STALL); 4227 } 4228 4229 return (DDI_INTR_CLAIMED); 4230 } 4231 4232 /* 4233 * igb_intr_rx - Interrupt handler for rx 4234 */ 4235 static uint_t 4236 igb_intr_rx(void *arg1, void *arg2) 4237 { 4238 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 4239 4240 _NOTE(ARGUNUSED(arg2)); 4241 4242 /* 4243 * Only used via MSI-X vector so don't check cause bits 4244 * and only clean the given ring. 4245 */ 4246 igb_intr_rx_work(rx_ring); 4247 4248 return (DDI_INTR_CLAIMED); 4249 } 4250 4251 /* 4252 * igb_intr_tx - Interrupt handler for tx 4253 */ 4254 static uint_t 4255 igb_intr_tx(void *arg1, void *arg2) 4256 { 4257 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1; 4258 4259 _NOTE(ARGUNUSED(arg2)); 4260 4261 /* 4262 * Only used via MSI-X vector so don't check cause bits 4263 * and only clean the given ring. 4264 */ 4265 igb_intr_tx_work(tx_ring); 4266 4267 return (DDI_INTR_CLAIMED); 4268 } 4269 4270 /* 4271 * igb_intr_tx_other - Interrupt handler for both tx and other 4272 * 4273 */ 4274 static uint_t 4275 igb_intr_tx_other(void *arg1, void *arg2) 4276 { 4277 igb_t *igb = (igb_t *)arg1; 4278 uint32_t icr; 4279 4280 _NOTE(ARGUNUSED(arg2)); 4281 4282 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4283 4284 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4285 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4286 atomic_or_32(&igb->igb_state, IGB_ERROR); 4287 return (DDI_INTR_CLAIMED); 4288 } 4289 4290 /* 4291 * Look for tx reclaiming work first. Remember, in the 4292 * case of only interrupt sharing, only one tx ring is 4293 * used 4294 */ 4295 igb_intr_tx_work(&igb->tx_rings[0]); 4296 4297 /* 4298 * Check for "other" causes. 4299 */ 4300 if (icr & E1000_ICR_LSC) { 4301 igb_intr_link_work(igb); 4302 } 4303 4304 /* 4305 * The DOUTSYNC bit indicates a tx packet dropped because 4306 * DMA engine gets "out of sync". There isn't a real fix 4307 * for this. The Intel recommendation is to count the number 4308 * of occurrences so user can detect when it is happening. 4309 * The issue is non-fatal and there's no recovery action 4310 * available. 4311 */ 4312 if (icr & E1000_ICR_DOUTSYNC) { 4313 IGB_STAT(igb->dout_sync); 4314 } 4315 4316 if (icr & E1000_ICR_DRSTA) { 4317 /* 82580 Full Device Reset needed */ 4318 atomic_or_32(&igb->igb_state, IGB_STALL); 4319 } 4320 4321 return (DDI_INTR_CLAIMED); 4322 } 4323 4324 /* 4325 * igb_alloc_intrs - Allocate interrupts for the driver 4326 * 4327 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 4328 * if not successful, try Legacy. 4329 * igb->intr_force can be used to force sequence to start with 4330 * any of the 3 types. 4331 * If MSI-X is not used, number of tx/rx rings is forced to 1. 4332 */ 4333 static int 4334 igb_alloc_intrs(igb_t *igb) 4335 { 4336 dev_info_t *devinfo; 4337 int intr_types; 4338 int rc; 4339 4340 devinfo = igb->dip; 4341 4342 /* Get supported interrupt types */ 4343 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4344 4345 if (rc != DDI_SUCCESS) { 4346 igb_log(igb, 4347 "Get supported interrupt types failed: %d", rc); 4348 return (IGB_FAILURE); 4349 } 4350 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 4351 4352 igb->intr_type = 0; 4353 4354 /* Install MSI-X interrupts */ 4355 if ((intr_types & DDI_INTR_TYPE_MSIX) && 4356 (igb->intr_force <= IGB_INTR_MSIX)) { 4357 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 4358 4359 if (rc == IGB_SUCCESS) 4360 return (IGB_SUCCESS); 4361 4362 igb_log(igb, 4363 "Allocate MSI-X failed, trying MSI interrupts..."); 4364 } 4365 4366 /* MSI-X not used, force rings to 1 */ 4367 igb->num_rx_rings = 1; 4368 igb->num_tx_rings = 1; 4369 igb_log(igb, 4370 "MSI-X not used, force rx and tx queue number to 1"); 4371 4372 /* Install MSI interrupts */ 4373 if ((intr_types & DDI_INTR_TYPE_MSI) && 4374 (igb->intr_force <= IGB_INTR_MSI)) { 4375 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 4376 4377 if (rc == IGB_SUCCESS) 4378 return (IGB_SUCCESS); 4379 4380 igb_log(igb, 4381 "Allocate MSI failed, trying Legacy interrupts..."); 4382 } 4383 4384 /* Install legacy interrupts */ 4385 if (intr_types & DDI_INTR_TYPE_FIXED) { 4386 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 4387 4388 if (rc == IGB_SUCCESS) 4389 return (IGB_SUCCESS); 4390 4391 igb_log(igb, 4392 "Allocate Legacy interrupts failed"); 4393 } 4394 4395 /* If none of the 3 types succeeded, return failure */ 4396 return (IGB_FAILURE); 4397 } 4398 4399 /* 4400 * igb_alloc_intr_handles - Allocate interrupt handles. 4401 * 4402 * For legacy and MSI, only 1 handle is needed. For MSI-X, 4403 * if fewer than 2 handles are available, return failure. 4404 * Upon success, this sets the number of Rx rings to a number that 4405 * matches the handles available for Rx interrupts. 4406 */ 4407 static int 4408 igb_alloc_intr_handles(igb_t *igb, int intr_type) 4409 { 4410 dev_info_t *devinfo; 4411 int orig, request, count, avail, actual; 4412 int diff, minimum; 4413 int rc; 4414 4415 devinfo = igb->dip; 4416 4417 switch (intr_type) { 4418 case DDI_INTR_TYPE_FIXED: 4419 request = 1; /* Request 1 legacy interrupt handle */ 4420 minimum = 1; 4421 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 4422 break; 4423 4424 case DDI_INTR_TYPE_MSI: 4425 request = 1; /* Request 1 MSI interrupt handle */ 4426 minimum = 1; 4427 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 4428 break; 4429 4430 case DDI_INTR_TYPE_MSIX: 4431 /* 4432 * Number of vectors for the adapter is 4433 * # rx rings + # tx rings 4434 * One of tx vectors is for tx & other 4435 */ 4436 request = igb->num_rx_rings + igb->num_tx_rings; 4437 orig = request; 4438 minimum = 2; 4439 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 4440 break; 4441 4442 default: 4443 igb_log(igb, 4444 "invalid call to igb_alloc_intr_handles(): %d\n", 4445 intr_type); 4446 return (IGB_FAILURE); 4447 } 4448 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 4449 request, minimum); 4450 4451 /* 4452 * Get number of supported interrupts 4453 */ 4454 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4455 if ((rc != DDI_SUCCESS) || (count < minimum)) { 4456 igb_log(igb, 4457 "Get supported interrupt number failed. " 4458 "Return: %d, count: %d", rc, count); 4459 return (IGB_FAILURE); 4460 } 4461 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 4462 4463 /* 4464 * Get number of available interrupts 4465 */ 4466 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4467 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 4468 igb_log(igb, 4469 "Get available interrupt number failed. " 4470 "Return: %d, available: %d", rc, avail); 4471 return (IGB_FAILURE); 4472 } 4473 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 4474 4475 if (avail < request) { 4476 igb_log(igb, "Request %d handles, %d available", 4477 request, avail); 4478 request = avail; 4479 } 4480 4481 actual = 0; 4482 igb->intr_cnt = 0; 4483 4484 /* 4485 * Allocate an array of interrupt handles 4486 */ 4487 igb->intr_size = request * sizeof (ddi_intr_handle_t); 4488 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 4489 4490 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 4491 request, &actual, DDI_INTR_ALLOC_NORMAL); 4492 if (rc != DDI_SUCCESS) { 4493 igb_log(igb, "Allocate interrupts failed. " 4494 "return: %d, request: %d, actual: %d", 4495 rc, request, actual); 4496 goto alloc_handle_fail; 4497 } 4498 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 4499 4500 igb->intr_cnt = actual; 4501 4502 if (actual < minimum) { 4503 igb_log(igb, "Insufficient interrupt handles allocated: %d", 4504 actual); 4505 goto alloc_handle_fail; 4506 } 4507 4508 /* 4509 * For MSI-X, actual might force us to reduce number of tx & rx rings 4510 */ 4511 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) { 4512 diff = orig - actual; 4513 if (diff < igb->num_tx_rings) { 4514 igb_log(igb, 4515 "MSI-X vectors force Tx queue number to %d", 4516 igb->num_tx_rings - diff); 4517 igb->num_tx_rings -= diff; 4518 } else { 4519 igb_log(igb, 4520 "MSI-X vectors force Tx queue number to 1"); 4521 igb->num_tx_rings = 1; 4522 4523 igb_log(igb, 4524 "MSI-X vectors force Rx queue number to %d", 4525 actual - 1); 4526 igb->num_rx_rings = actual - 1; 4527 } 4528 } 4529 4530 /* 4531 * Get priority for first vector, assume remaining are all the same 4532 */ 4533 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 4534 if (rc != DDI_SUCCESS) { 4535 igb_log(igb, 4536 "Get interrupt priority failed: %d", rc); 4537 goto alloc_handle_fail; 4538 } 4539 4540 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 4541 if (rc != DDI_SUCCESS) { 4542 igb_log(igb, 4543 "Get interrupt cap failed: %d", rc); 4544 goto alloc_handle_fail; 4545 } 4546 4547 igb->intr_type = intr_type; 4548 4549 return (IGB_SUCCESS); 4550 4551 alloc_handle_fail: 4552 igb_rem_intrs(igb); 4553 4554 return (IGB_FAILURE); 4555 } 4556 4557 /* 4558 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 4559 * 4560 * Before adding the interrupt handlers, the interrupt vectors have 4561 * been allocated, and the rx/tx rings have also been allocated. 4562 */ 4563 static int 4564 igb_add_intr_handlers(igb_t *igb) 4565 { 4566 igb_rx_ring_t *rx_ring; 4567 igb_tx_ring_t *tx_ring; 4568 int vector; 4569 int rc; 4570 int i; 4571 4572 vector = 0; 4573 4574 switch (igb->intr_type) { 4575 case DDI_INTR_TYPE_MSIX: 4576 /* Add interrupt handler for tx + other */ 4577 tx_ring = &igb->tx_rings[0]; 4578 rc = ddi_intr_add_handler(igb->htable[vector], 4579 (ddi_intr_handler_t *)igb_intr_tx_other, 4580 (void *)igb, NULL); 4581 4582 if (rc != DDI_SUCCESS) { 4583 igb_log(igb, 4584 "Add tx/other interrupt handler failed: %d", rc); 4585 return (IGB_FAILURE); 4586 } 4587 tx_ring->intr_vector = vector; 4588 vector++; 4589 4590 /* Add interrupt handler for each rx ring */ 4591 for (i = 0; i < igb->num_rx_rings; i++) { 4592 rx_ring = &igb->rx_rings[i]; 4593 4594 rc = ddi_intr_add_handler(igb->htable[vector], 4595 (ddi_intr_handler_t *)igb_intr_rx, 4596 (void *)rx_ring, NULL); 4597 4598 if (rc != DDI_SUCCESS) { 4599 igb_log(igb, 4600 "Add rx interrupt handler failed. " 4601 "return: %d, rx ring: %d", rc, i); 4602 for (vector--; vector >= 0; vector--) { 4603 (void) ddi_intr_remove_handler( 4604 igb->htable[vector]); 4605 } 4606 return (IGB_FAILURE); 4607 } 4608 4609 rx_ring->intr_vector = vector; 4610 4611 vector++; 4612 } 4613 4614 /* Add interrupt handler for each tx ring from 2nd ring */ 4615 for (i = 1; i < igb->num_tx_rings; i++) { 4616 tx_ring = &igb->tx_rings[i]; 4617 4618 rc = ddi_intr_add_handler(igb->htable[vector], 4619 (ddi_intr_handler_t *)igb_intr_tx, 4620 (void *)tx_ring, NULL); 4621 4622 if (rc != DDI_SUCCESS) { 4623 igb_log(igb, 4624 "Add tx interrupt handler failed. " 4625 "return: %d, tx ring: %d", rc, i); 4626 for (vector--; vector >= 0; vector--) { 4627 (void) ddi_intr_remove_handler( 4628 igb->htable[vector]); 4629 } 4630 return (IGB_FAILURE); 4631 } 4632 4633 tx_ring->intr_vector = vector; 4634 4635 vector++; 4636 } 4637 4638 break; 4639 4640 case DDI_INTR_TYPE_MSI: 4641 /* Add interrupt handlers for the only vector */ 4642 rc = ddi_intr_add_handler(igb->htable[vector], 4643 (ddi_intr_handler_t *)igb_intr_msi, 4644 (void *)igb, NULL); 4645 4646 if (rc != DDI_SUCCESS) { 4647 igb_log(igb, 4648 "Add MSI interrupt handler failed: %d", rc); 4649 return (IGB_FAILURE); 4650 } 4651 4652 rx_ring = &igb->rx_rings[0]; 4653 rx_ring->intr_vector = vector; 4654 4655 vector++; 4656 break; 4657 4658 case DDI_INTR_TYPE_FIXED: 4659 /* Add interrupt handlers for the only vector */ 4660 rc = ddi_intr_add_handler(igb->htable[vector], 4661 (ddi_intr_handler_t *)igb_intr_legacy, 4662 (void *)igb, NULL); 4663 4664 if (rc != DDI_SUCCESS) { 4665 igb_log(igb, 4666 "Add legacy interrupt handler failed: %d", rc); 4667 return (IGB_FAILURE); 4668 } 4669 4670 rx_ring = &igb->rx_rings[0]; 4671 rx_ring->intr_vector = vector; 4672 4673 vector++; 4674 break; 4675 4676 default: 4677 return (IGB_FAILURE); 4678 } 4679 4680 ASSERT(vector == igb->intr_cnt); 4681 4682 return (IGB_SUCCESS); 4683 } 4684 4685 /* 4686 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts 4687 * 4688 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 4689 */ 4690 static void 4691 igb_setup_msix_82575(igb_t *igb) 4692 { 4693 uint32_t eims = 0; 4694 int i, vector; 4695 struct e1000_hw *hw = &igb->hw; 4696 4697 /* 4698 * Set vector for tx ring 0 and other causes. 4699 * NOTE assumption that it is vector 0. 4700 */ 4701 vector = 0; 4702 4703 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 4704 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 4705 vector++; 4706 4707 for (i = 0; i < igb->num_rx_rings; i++) { 4708 /* 4709 * Set vector for each rx ring 4710 */ 4711 eims = (E1000_EICR_RX_QUEUE0 << i); 4712 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4713 4714 /* 4715 * Accumulate bits to enable in 4716 * igb_enable_adapter_interrupts_82575() 4717 */ 4718 igb->eims_mask |= eims; 4719 4720 vector++; 4721 } 4722 4723 for (i = 1; i < igb->num_tx_rings; i++) { 4724 /* 4725 * Set vector for each tx ring from 2nd tx ring 4726 */ 4727 eims = (E1000_EICR_TX_QUEUE0 << i); 4728 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4729 4730 /* 4731 * Accumulate bits to enable in 4732 * igb_enable_adapter_interrupts_82575() 4733 */ 4734 igb->eims_mask |= eims; 4735 4736 vector++; 4737 } 4738 4739 ASSERT(vector == igb->intr_cnt); 4740 4741 /* 4742 * Disable IAM for ICR interrupt bits 4743 */ 4744 E1000_WRITE_REG(hw, E1000_IAM, 0); 4745 E1000_WRITE_FLUSH(hw); 4746 } 4747 4748 /* 4749 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts 4750 * 4751 * 82576 uses a table based method for assigning vectors. Each queue has a 4752 * single entry in the table to which we write a vector number along with a 4753 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors 4754 * take a different position in the 4-byte register depending on whether 4755 * they are numbered above or below 8. 4756 */ 4757 static void 4758 igb_setup_msix_82576(igb_t *igb) 4759 { 4760 struct e1000_hw *hw = &igb->hw; 4761 uint32_t ivar, index, vector; 4762 int i; 4763 4764 /* must enable msi-x capability before IVAR settings */ 4765 E1000_WRITE_REG(hw, E1000_GPIE, 4766 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR)); 4767 4768 /* 4769 * Set vector for tx ring 0 and other causes. 4770 * NOTE assumption that it is vector 0. 4771 * This is also interdependent with installation of interrupt service 4772 * routines in igb_add_intr_handlers(). 4773 */ 4774 4775 /* assign "other" causes to vector 0 */ 4776 vector = 0; 4777 ivar = ((vector | E1000_IVAR_VALID) << 8); 4778 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4779 4780 /* assign tx ring 0 to vector 0 */ 4781 ivar = ((vector | E1000_IVAR_VALID) << 8); 4782 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4783 4784 /* prepare to enable tx & other interrupt causes */ 4785 igb->eims_mask = (1 << vector); 4786 4787 vector ++; 4788 for (i = 0; i < igb->num_rx_rings; i++) { 4789 /* 4790 * Set vector for each rx ring 4791 */ 4792 index = (i & 0x7); 4793 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4794 4795 if (i < 8) { 4796 /* vector goes into low byte of register */ 4797 ivar = ivar & 0xFFFFFF00; 4798 ivar |= (vector | E1000_IVAR_VALID); 4799 } else { 4800 /* vector goes into third byte of register */ 4801 ivar = ivar & 0xFF00FFFF; 4802 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4803 } 4804 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4805 4806 /* Accumulate interrupt-cause bits to enable */ 4807 igb->eims_mask |= (1 << vector); 4808 4809 vector ++; 4810 } 4811 4812 for (i = 1; i < igb->num_tx_rings; i++) { 4813 /* 4814 * Set vector for each tx ring from 2nd tx ring. 4815 * Note assumption that tx vectors numericall follow rx vectors. 4816 */ 4817 index = (i & 0x7); 4818 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4819 4820 if (i < 8) { 4821 /* vector goes into second byte of register */ 4822 ivar = ivar & 0xFFFF00FF; 4823 ivar |= ((vector | E1000_IVAR_VALID) << 8); 4824 } else { 4825 /* vector goes into fourth byte of register */ 4826 ivar = ivar & 0x00FFFFFF; 4827 ivar |= (vector | E1000_IVAR_VALID) << 24; 4828 } 4829 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4830 4831 /* Accumulate interrupt-cause bits to enable */ 4832 igb->eims_mask |= (1 << vector); 4833 4834 vector ++; 4835 } 4836 4837 ASSERT(vector == igb->intr_cnt); 4838 } 4839 4840 /* 4841 * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts 4842 * 4843 * 82580 uses same table approach at 82576 but has fewer entries. Each 4844 * queue has a single entry in the table to which we write a vector number 4845 * along with a "valid" bit. Vectors take a different position in the 4846 * register depending on * whether * they are numbered above or below 4. 4847 */ 4848 static void 4849 igb_setup_msix_82580(igb_t *igb) 4850 { 4851 struct e1000_hw *hw = &igb->hw; 4852 uint32_t ivar, index, vector; 4853 int i; 4854 4855 /* must enable msi-x capability before IVAR settings */ 4856 E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE | 4857 E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME)); 4858 /* 4859 * Set vector for tx ring 0 and other causes. 4860 * NOTE assumption that it is vector 0. 4861 * This is also interdependent with installation of interrupt service 4862 * routines in igb_add_intr_handlers(). 4863 */ 4864 4865 /* assign "other" causes to vector 0 */ 4866 vector = 0; 4867 ivar = ((vector | E1000_IVAR_VALID) << 8); 4868 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4869 4870 /* assign tx ring 0 to vector 0 */ 4871 ivar = ((vector | E1000_IVAR_VALID) << 8); 4872 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4873 4874 /* prepare to enable tx & other interrupt causes */ 4875 igb->eims_mask = (1 << vector); 4876 4877 vector ++; 4878 4879 for (i = 0; i < igb->num_rx_rings; i++) { 4880 /* 4881 * Set vector for each rx ring 4882 */ 4883 index = (i >> 1); 4884 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4885 4886 if (i & 1) { 4887 /* vector goes into third byte of register */ 4888 ivar = ivar & 0xFF00FFFF; 4889 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4890 } else { 4891 /* vector goes into low byte of register */ 4892 ivar = ivar & 0xFFFFFF00; 4893 ivar |= (vector | E1000_IVAR_VALID); 4894 } 4895 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4896 4897 /* Accumulate interrupt-cause bits to enable */ 4898 igb->eims_mask |= (1 << vector); 4899 4900 vector ++; 4901 } 4902 4903 for (i = 1; i < igb->num_tx_rings; i++) { 4904 /* 4905 * Set vector for each tx ring from 2nd tx ring. 4906 * Note assumption that tx vectors numericall follow rx vectors. 4907 */ 4908 index = (i >> 1); 4909 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4910 4911 if (i & 1) { 4912 /* vector goes into high byte of register */ 4913 ivar = ivar & 0x00FFFFFF; 4914 ivar |= ((vector | E1000_IVAR_VALID) << 24); 4915 } else { 4916 /* vector goes into second byte of register */ 4917 ivar = ivar & 0xFFFF00FF; 4918 ivar |= (vector | E1000_IVAR_VALID) << 8; 4919 } 4920 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4921 4922 /* Accumulate interrupt-cause bits to enable */ 4923 igb->eims_mask |= (1 << vector); 4924 4925 vector ++; 4926 } 4927 ASSERT(vector == igb->intr_cnt); 4928 } 4929 4930 /* 4931 * igb_rem_intr_handlers - remove the interrupt handlers 4932 */ 4933 static void 4934 igb_rem_intr_handlers(igb_t *igb) 4935 { 4936 int i; 4937 int rc; 4938 4939 for (i = 0; i < igb->intr_cnt; i++) { 4940 rc = ddi_intr_remove_handler(igb->htable[i]); 4941 if (rc != DDI_SUCCESS) { 4942 IGB_DEBUGLOG_1(igb, 4943 "Remove intr handler failed: %d", rc); 4944 } 4945 } 4946 } 4947 4948 /* 4949 * igb_rem_intrs - remove the allocated interrupts 4950 */ 4951 static void 4952 igb_rem_intrs(igb_t *igb) 4953 { 4954 int i; 4955 int rc; 4956 4957 for (i = 0; i < igb->intr_cnt; i++) { 4958 rc = ddi_intr_free(igb->htable[i]); 4959 if (rc != DDI_SUCCESS) { 4960 IGB_DEBUGLOG_1(igb, 4961 "Free intr failed: %d", rc); 4962 } 4963 } 4964 4965 kmem_free(igb->htable, igb->intr_size); 4966 igb->htable = NULL; 4967 } 4968 4969 /* 4970 * igb_enable_intrs - enable all the ddi interrupts 4971 */ 4972 static int 4973 igb_enable_intrs(igb_t *igb) 4974 { 4975 int i; 4976 int rc; 4977 4978 /* Enable interrupts */ 4979 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4980 /* Call ddi_intr_block_enable() for MSI */ 4981 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 4982 if (rc != DDI_SUCCESS) { 4983 igb_log(igb, 4984 "Enable block intr failed: %d", rc); 4985 return (IGB_FAILURE); 4986 } 4987 } else { 4988 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4989 for (i = 0; i < igb->intr_cnt; i++) { 4990 rc = ddi_intr_enable(igb->htable[i]); 4991 if (rc != DDI_SUCCESS) { 4992 igb_log(igb, 4993 "Enable intr failed: %d", rc); 4994 return (IGB_FAILURE); 4995 } 4996 } 4997 } 4998 4999 return (IGB_SUCCESS); 5000 } 5001 5002 /* 5003 * igb_disable_intrs - disable all the ddi interrupts 5004 */ 5005 static int 5006 igb_disable_intrs(igb_t *igb) 5007 { 5008 int i; 5009 int rc; 5010 5011 /* Disable all interrupts */ 5012 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 5013 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 5014 if (rc != DDI_SUCCESS) { 5015 igb_log(igb, 5016 "Disable block intr failed: %d", rc); 5017 return (IGB_FAILURE); 5018 } 5019 } else { 5020 for (i = 0; i < igb->intr_cnt; i++) { 5021 rc = ddi_intr_disable(igb->htable[i]); 5022 if (rc != DDI_SUCCESS) { 5023 igb_log(igb, 5024 "Disable intr failed: %d", rc); 5025 return (IGB_FAILURE); 5026 } 5027 } 5028 } 5029 5030 return (IGB_SUCCESS); 5031 } 5032 5033 /* 5034 * igb_get_phy_state - Get and save the parameters read from PHY registers 5035 */ 5036 static void 5037 igb_get_phy_state(igb_t *igb) 5038 { 5039 struct e1000_hw *hw = &igb->hw; 5040 uint16_t phy_ctrl; 5041 uint16_t phy_status; 5042 uint16_t phy_an_adv; 5043 uint16_t phy_an_exp; 5044 uint16_t phy_ext_status; 5045 uint16_t phy_1000t_ctrl; 5046 uint16_t phy_1000t_status; 5047 uint16_t phy_lp_able; 5048 5049 ASSERT(mutex_owned(&igb->gen_lock)); 5050 5051 if (hw->phy.media_type == e1000_media_type_copper) { 5052 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5053 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 5054 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 5055 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 5056 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 5057 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 5058 (void) e1000_read_phy_reg(hw, 5059 PHY_1000T_STATUS, &phy_1000t_status); 5060 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 5061 5062 igb->param_autoneg_cap = 5063 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5064 igb->param_pause_cap = 5065 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5066 igb->param_asym_pause_cap = 5067 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5068 igb->param_1000fdx_cap = 5069 ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5070 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5071 igb->param_1000hdx_cap = 5072 ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5073 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5074 igb->param_100t4_cap = 5075 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5076 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 5077 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5078 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 5079 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5080 igb->param_10fdx_cap = 5081 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5082 igb->param_10hdx_cap = 5083 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5084 igb->param_rem_fault = 5085 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 5086 5087 igb->param_adv_autoneg_cap = hw->mac.autoneg; 5088 igb->param_adv_pause_cap = 5089 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5090 igb->param_adv_asym_pause_cap = 5091 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5092 igb->param_adv_1000hdx_cap = 5093 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5094 igb->param_adv_100t4_cap = 5095 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5096 igb->param_adv_rem_fault = 5097 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 5098 if (igb->param_adv_autoneg_cap == 1) { 5099 igb->param_adv_1000fdx_cap = 5100 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5101 igb->param_adv_100fdx_cap = 5102 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5103 igb->param_adv_100hdx_cap = 5104 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5105 igb->param_adv_10fdx_cap = 5106 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5107 igb->param_adv_10hdx_cap = 5108 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5109 } 5110 5111 igb->param_lp_autoneg_cap = 5112 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5113 igb->param_lp_pause_cap = 5114 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5115 igb->param_lp_asym_pause_cap = 5116 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5117 igb->param_lp_1000fdx_cap = 5118 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5119 igb->param_lp_1000hdx_cap = 5120 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5121 igb->param_lp_100t4_cap = 5122 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5123 igb->param_lp_100fdx_cap = 5124 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5125 igb->param_lp_100hdx_cap = 5126 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5127 igb->param_lp_10fdx_cap = 5128 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5129 igb->param_lp_10hdx_cap = 5130 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5131 igb->param_lp_rem_fault = 5132 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 5133 } else { 5134 /* 5135 * 1Gig Fiber adapter only offers 1Gig Full Duplex. 5136 */ 5137 igb->param_autoneg_cap = 0; 5138 igb->param_pause_cap = 1; 5139 igb->param_asym_pause_cap = 1; 5140 igb->param_1000fdx_cap = 1; 5141 igb->param_1000hdx_cap = 0; 5142 igb->param_100t4_cap = 0; 5143 igb->param_100fdx_cap = 0; 5144 igb->param_100hdx_cap = 0; 5145 igb->param_10fdx_cap = 0; 5146 igb->param_10hdx_cap = 0; 5147 5148 igb->param_adv_autoneg_cap = 0; 5149 igb->param_adv_pause_cap = 1; 5150 igb->param_adv_asym_pause_cap = 1; 5151 igb->param_adv_1000fdx_cap = 1; 5152 igb->param_adv_1000hdx_cap = 0; 5153 igb->param_adv_100t4_cap = 0; 5154 igb->param_adv_100fdx_cap = 0; 5155 igb->param_adv_100hdx_cap = 0; 5156 igb->param_adv_10fdx_cap = 0; 5157 igb->param_adv_10hdx_cap = 0; 5158 5159 igb->param_lp_autoneg_cap = 0; 5160 igb->param_lp_pause_cap = 0; 5161 igb->param_lp_asym_pause_cap = 0; 5162 igb->param_lp_1000fdx_cap = 0; 5163 igb->param_lp_1000hdx_cap = 0; 5164 igb->param_lp_100t4_cap = 0; 5165 igb->param_lp_100fdx_cap = 0; 5166 igb->param_lp_100hdx_cap = 0; 5167 igb->param_lp_10fdx_cap = 0; 5168 igb->param_lp_10hdx_cap = 0; 5169 igb->param_lp_rem_fault = 0; 5170 } 5171 } 5172 5173 /* 5174 * synchronize the adv* and en* parameters. 5175 * 5176 * See comments in <sys/dld.h> for details of the *_en_* 5177 * parameters. The usage of ndd for setting adv parameters will 5178 * synchronize all the en parameters with the e1000g parameters, 5179 * implicitly disabling any settings made via dladm. 5180 */ 5181 static void 5182 igb_param_sync(igb_t *igb) 5183 { 5184 igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap; 5185 igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap; 5186 igb->param_en_100t4_cap = igb->param_adv_100t4_cap; 5187 igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap; 5188 igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap; 5189 igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap; 5190 igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap; 5191 } 5192 5193 /* 5194 * igb_get_driver_control 5195 */ 5196 static void 5197 igb_get_driver_control(struct e1000_hw *hw) 5198 { 5199 uint32_t ctrl_ext; 5200 5201 /* Notify firmware that driver is in control of device */ 5202 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5203 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 5204 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5205 } 5206 5207 /* 5208 * igb_release_driver_control 5209 */ 5210 static void 5211 igb_release_driver_control(struct e1000_hw *hw) 5212 { 5213 uint32_t ctrl_ext; 5214 5215 /* Notify firmware that driver is no longer in control of device */ 5216 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5217 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 5218 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5219 } 5220 5221 /* 5222 * igb_atomic_reserve - Atomic decrease operation 5223 */ 5224 int 5225 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 5226 { 5227 uint32_t oldval; 5228 uint32_t newval; 5229 5230 /* ATOMICALLY */ 5231 do { 5232 oldval = *count_p; 5233 if (oldval < n) 5234 return (-1); 5235 newval = oldval - n; 5236 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 5237 5238 return (newval); 5239 } 5240 5241 /* 5242 * FMA support 5243 */ 5244 5245 int 5246 igb_check_acc_handle(ddi_acc_handle_t handle) 5247 { 5248 ddi_fm_error_t de; 5249 5250 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5251 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5252 return (de.fme_status); 5253 } 5254 5255 int 5256 igb_check_dma_handle(ddi_dma_handle_t handle) 5257 { 5258 ddi_fm_error_t de; 5259 5260 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5261 return (de.fme_status); 5262 } 5263 5264 /* 5265 * The IO fault service error handling callback function 5266 */ 5267 /*ARGSUSED*/ 5268 static int 5269 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5270 { 5271 /* 5272 * as the driver can always deal with an error in any dma or 5273 * access handle, we can just return the fme_status value. 5274 */ 5275 pci_ereport_post(dip, err, NULL); 5276 return (err->fme_status); 5277 } 5278 5279 static void 5280 igb_fm_init(igb_t *igb) 5281 { 5282 ddi_iblock_cookie_t iblk; 5283 int fma_dma_flag; 5284 5285 /* Only register with IO Fault Services if we have some capability */ 5286 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5287 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5288 } else { 5289 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5290 } 5291 5292 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5293 fma_dma_flag = 1; 5294 } else { 5295 fma_dma_flag = 0; 5296 } 5297 5298 (void) igb_set_fma_flags(fma_dma_flag); 5299 5300 if (igb->fm_capabilities) { 5301 5302 /* Register capabilities with IO Fault Services */ 5303 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 5304 5305 /* 5306 * Initialize pci ereport capabilities if ereport capable 5307 */ 5308 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 5309 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5310 pci_ereport_setup(igb->dip); 5311 5312 /* 5313 * Register error callback if error callback capable 5314 */ 5315 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5316 ddi_fm_handler_register(igb->dip, 5317 igb_fm_error_cb, (void*) igb); 5318 } 5319 } 5320 5321 static void 5322 igb_fm_fini(igb_t *igb) 5323 { 5324 /* Only unregister FMA capabilities if we registered some */ 5325 if (igb->fm_capabilities) { 5326 5327 /* 5328 * Release any resources allocated by pci_ereport_setup() 5329 */ 5330 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 5331 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5332 pci_ereport_teardown(igb->dip); 5333 5334 /* 5335 * Un-register error callback if error callback capable 5336 */ 5337 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5338 ddi_fm_handler_unregister(igb->dip); 5339 5340 /* Unregister from IO Fault Services */ 5341 ddi_fm_fini(igb->dip); 5342 } 5343 } 5344 5345 void 5346 igb_fm_ereport(igb_t *igb, char *detail) 5347 { 5348 uint64_t ena; 5349 char buf[FM_MAX_CLASS]; 5350 5351 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5352 ena = fm_ena_generate(0, FM_ENA_FMT1); 5353 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 5354 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 5355 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5356 } 5357 } 5358