1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2007-2012 Intel Corporation. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 * Copyright 2013, Nexenta Systems, Inc. All rights reserved. 29 */ 30 31 #include "igb_sw.h" 32 33 static char ident[] = "Intel 1Gb Ethernet"; 34 static char igb_version[] = "igb 1.1.18"; 35 36 /* 37 * Local function protoypes 38 */ 39 static int igb_register_mac(igb_t *); 40 static int igb_identify_hardware(igb_t *); 41 static int igb_regs_map(igb_t *); 42 static void igb_init_properties(igb_t *); 43 static int igb_init_driver_settings(igb_t *); 44 static void igb_init_locks(igb_t *); 45 static void igb_destroy_locks(igb_t *); 46 static int igb_init_mac_address(igb_t *); 47 static int igb_init(igb_t *); 48 static int igb_init_adapter(igb_t *); 49 static void igb_stop_adapter(igb_t *); 50 static int igb_reset(igb_t *); 51 static void igb_tx_clean(igb_t *); 52 static boolean_t igb_tx_drain(igb_t *); 53 static boolean_t igb_rx_drain(igb_t *); 54 static int igb_alloc_rings(igb_t *); 55 static int igb_alloc_rx_data(igb_t *); 56 static void igb_free_rx_data(igb_t *); 57 static void igb_free_rings(igb_t *); 58 static void igb_setup_rings(igb_t *); 59 static void igb_setup_rx(igb_t *); 60 static void igb_setup_tx(igb_t *); 61 static void igb_setup_rx_ring(igb_rx_ring_t *); 62 static void igb_setup_tx_ring(igb_tx_ring_t *); 63 static void igb_setup_rss(igb_t *); 64 static void igb_setup_mac_rss_classify(igb_t *); 65 static void igb_setup_mac_classify(igb_t *); 66 static void igb_init_unicst(igb_t *); 67 static void igb_setup_multicst(igb_t *); 68 static void igb_get_phy_state(igb_t *); 69 static void igb_param_sync(igb_t *); 70 static void igb_get_conf(igb_t *); 71 static int igb_get_prop(igb_t *, char *, int, int, int); 72 static boolean_t igb_is_link_up(igb_t *); 73 static boolean_t igb_link_check(igb_t *); 74 static void igb_local_timer(void *); 75 static void igb_link_timer(void *); 76 static void igb_arm_watchdog_timer(igb_t *); 77 static void igb_start_watchdog_timer(igb_t *); 78 static void igb_restart_watchdog_timer(igb_t *); 79 static void igb_stop_watchdog_timer(igb_t *); 80 static void igb_start_link_timer(igb_t *); 81 static void igb_stop_link_timer(igb_t *); 82 static void igb_disable_adapter_interrupts(igb_t *); 83 static void igb_enable_adapter_interrupts_82575(igb_t *); 84 static void igb_enable_adapter_interrupts_82576(igb_t *); 85 static void igb_enable_adapter_interrupts_82580(igb_t *); 86 static boolean_t is_valid_mac_addr(uint8_t *); 87 static boolean_t igb_stall_check(igb_t *); 88 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 89 static void igb_set_external_loopback(igb_t *); 90 static void igb_set_internal_phy_loopback(igb_t *); 91 static void igb_set_internal_serdes_loopback(igb_t *); 92 static boolean_t igb_find_mac_address(igb_t *); 93 static int igb_alloc_intrs(igb_t *); 94 static int igb_alloc_intr_handles(igb_t *, int); 95 static int igb_add_intr_handlers(igb_t *); 96 static void igb_rem_intr_handlers(igb_t *); 97 static void igb_rem_intrs(igb_t *); 98 static int igb_enable_intrs(igb_t *); 99 static int igb_disable_intrs(igb_t *); 100 static void igb_setup_msix_82575(igb_t *); 101 static void igb_setup_msix_82576(igb_t *); 102 static void igb_setup_msix_82580(igb_t *); 103 static uint_t igb_intr_legacy(void *, void *); 104 static uint_t igb_intr_msi(void *, void *); 105 static uint_t igb_intr_rx(void *, void *); 106 static uint_t igb_intr_tx(void *, void *); 107 static uint_t igb_intr_tx_other(void *, void *); 108 static void igb_intr_rx_work(igb_rx_ring_t *); 109 static void igb_intr_tx_work(igb_tx_ring_t *); 110 static void igb_intr_link_work(igb_t *); 111 static void igb_get_driver_control(struct e1000_hw *); 112 static void igb_release_driver_control(struct e1000_hw *); 113 114 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 115 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 116 static int igb_resume(dev_info_t *); 117 static int igb_suspend(dev_info_t *); 118 static int igb_quiesce(dev_info_t *); 119 static void igb_unconfigure(dev_info_t *, igb_t *); 120 static int igb_fm_error_cb(dev_info_t *, ddi_fm_error_t *, 121 const void *); 122 static void igb_fm_init(igb_t *); 123 static void igb_fm_fini(igb_t *); 124 static void igb_release_multicast(igb_t *); 125 126 char *igb_priv_props[] = { 127 "_eee_support", 128 "_tx_copy_thresh", 129 "_tx_recycle_thresh", 130 "_tx_overload_thresh", 131 "_tx_resched_thresh", 132 "_rx_copy_thresh", 133 "_rx_limit_per_intr", 134 "_intr_throttling", 135 "_adv_pause_cap", 136 "_adv_asym_pause_cap", 137 NULL 138 }; 139 140 static struct cb_ops igb_cb_ops = { 141 nulldev, /* cb_open */ 142 nulldev, /* cb_close */ 143 nodev, /* cb_strategy */ 144 nodev, /* cb_print */ 145 nodev, /* cb_dump */ 146 nodev, /* cb_read */ 147 nodev, /* cb_write */ 148 nodev, /* cb_ioctl */ 149 nodev, /* cb_devmap */ 150 nodev, /* cb_mmap */ 151 nodev, /* cb_segmap */ 152 nochpoll, /* cb_chpoll */ 153 ddi_prop_op, /* cb_prop_op */ 154 NULL, /* cb_stream */ 155 D_MP | D_HOTPLUG, /* cb_flag */ 156 CB_REV, /* cb_rev */ 157 nodev, /* cb_aread */ 158 nodev /* cb_awrite */ 159 }; 160 161 static struct dev_ops igb_dev_ops = { 162 DEVO_REV, /* devo_rev */ 163 0, /* devo_refcnt */ 164 NULL, /* devo_getinfo */ 165 nulldev, /* devo_identify */ 166 nulldev, /* devo_probe */ 167 igb_attach, /* devo_attach */ 168 igb_detach, /* devo_detach */ 169 nodev, /* devo_reset */ 170 &igb_cb_ops, /* devo_cb_ops */ 171 NULL, /* devo_bus_ops */ 172 ddi_power, /* devo_power */ 173 igb_quiesce, /* devo_quiesce */ 174 }; 175 176 static struct modldrv igb_modldrv = { 177 &mod_driverops, /* Type of module. This one is a driver */ 178 ident, /* Discription string */ 179 &igb_dev_ops, /* driver ops */ 180 }; 181 182 static struct modlinkage igb_modlinkage = { 183 MODREV_1, &igb_modldrv, NULL 184 }; 185 186 /* Access attributes for register mapping */ 187 ddi_device_acc_attr_t igb_regs_acc_attr = { 188 DDI_DEVICE_ATTR_V1, 189 DDI_STRUCTURE_LE_ACC, 190 DDI_STRICTORDER_ACC, 191 DDI_FLAGERR_ACC 192 }; 193 194 #define IGB_M_CALLBACK_FLAGS \ 195 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP | MC_PROPINFO) 196 197 static mac_callbacks_t igb_m_callbacks = { 198 IGB_M_CALLBACK_FLAGS, 199 igb_m_stat, 200 igb_m_start, 201 igb_m_stop, 202 igb_m_promisc, 203 igb_m_multicst, 204 NULL, 205 NULL, 206 NULL, 207 igb_m_ioctl, 208 igb_m_getcapab, 209 NULL, 210 NULL, 211 igb_m_setprop, 212 igb_m_getprop, 213 igb_m_propinfo 214 }; 215 216 /* 217 * Initialize capabilities of each supported adapter type 218 */ 219 static adapter_info_t igb_82575_cap = { 220 /* limits */ 221 4, /* maximum number of rx queues */ 222 1, /* minimum number of rx queues */ 223 4, /* default number of rx queues */ 224 4, /* maximum number of tx queues */ 225 1, /* minimum number of tx queues */ 226 4, /* default number of tx queues */ 227 65535, /* maximum interrupt throttle rate */ 228 0, /* minimum interrupt throttle rate */ 229 200, /* default interrupt throttle rate */ 230 231 /* function pointers */ 232 igb_enable_adapter_interrupts_82575, 233 igb_setup_msix_82575, 234 235 /* capabilities */ 236 (IGB_FLAG_HAS_DCA | /* capability flags */ 237 IGB_FLAG_VMDQ_POOL), 238 239 0xffc00000 /* mask for RXDCTL register */ 240 }; 241 242 static adapter_info_t igb_82576_cap = { 243 /* limits */ 244 16, /* maximum number of rx queues */ 245 1, /* minimum number of rx queues */ 246 4, /* default number of rx queues */ 247 16, /* maximum number of tx queues */ 248 1, /* minimum number of tx queues */ 249 4, /* default number of tx queues */ 250 65535, /* maximum interrupt throttle rate */ 251 0, /* minimum interrupt throttle rate */ 252 200, /* default interrupt throttle rate */ 253 254 /* function pointers */ 255 igb_enable_adapter_interrupts_82576, 256 igb_setup_msix_82576, 257 258 /* capabilities */ 259 (IGB_FLAG_HAS_DCA | /* capability flags */ 260 IGB_FLAG_VMDQ_POOL | 261 IGB_FLAG_NEED_CTX_IDX), 262 263 0xffe00000 /* mask for RXDCTL register */ 264 }; 265 266 static adapter_info_t igb_82580_cap = { 267 /* limits */ 268 8, /* maximum number of rx queues */ 269 1, /* minimum number of rx queues */ 270 4, /* default number of rx queues */ 271 8, /* maximum number of tx queues */ 272 1, /* minimum number of tx queues */ 273 4, /* default number of tx queues */ 274 65535, /* maximum interrupt throttle rate */ 275 0, /* minimum interrupt throttle rate */ 276 200, /* default interrupt throttle rate */ 277 278 /* function pointers */ 279 igb_enable_adapter_interrupts_82580, 280 igb_setup_msix_82580, 281 282 /* capabilities */ 283 (IGB_FLAG_HAS_DCA | /* capability flags */ 284 IGB_FLAG_VMDQ_POOL | 285 IGB_FLAG_NEED_CTX_IDX), 286 287 0xffe00000 /* mask for RXDCTL register */ 288 }; 289 290 static adapter_info_t igb_i350_cap = { 291 /* limits */ 292 8, /* maximum number of rx queues */ 293 1, /* minimum number of rx queues */ 294 4, /* default number of rx queues */ 295 8, /* maximum number of tx queues */ 296 1, /* minimum number of tx queues */ 297 4, /* default number of tx queues */ 298 65535, /* maximum interrupt throttle rate */ 299 0, /* minimum interrupt throttle rate */ 300 200, /* default interrupt throttle rate */ 301 302 /* function pointers */ 303 igb_enable_adapter_interrupts_82580, 304 igb_setup_msix_82580, 305 306 /* capabilities */ 307 (IGB_FLAG_HAS_DCA | /* capability flags */ 308 IGB_FLAG_VMDQ_POOL | 309 IGB_FLAG_NEED_CTX_IDX), 310 311 0xffe00000 /* mask for RXDCTL register */ 312 }; 313 314 /* 315 * Module Initialization Functions 316 */ 317 318 int 319 _init(void) 320 { 321 int status; 322 323 mac_init_ops(&igb_dev_ops, MODULE_NAME); 324 325 status = mod_install(&igb_modlinkage); 326 327 if (status != DDI_SUCCESS) { 328 mac_fini_ops(&igb_dev_ops); 329 } 330 331 return (status); 332 } 333 334 int 335 _fini(void) 336 { 337 int status; 338 339 status = mod_remove(&igb_modlinkage); 340 341 if (status == DDI_SUCCESS) { 342 mac_fini_ops(&igb_dev_ops); 343 } 344 345 return (status); 346 347 } 348 349 int 350 _info(struct modinfo *modinfop) 351 { 352 int status; 353 354 status = mod_info(&igb_modlinkage, modinfop); 355 356 return (status); 357 } 358 359 /* 360 * igb_attach - driver attach 361 * 362 * This function is the device specific initialization entry 363 * point. This entry point is required and must be written. 364 * The DDI_ATTACH command must be provided in the attach entry 365 * point. When attach() is called with cmd set to DDI_ATTACH, 366 * all normal kernel services (such as kmem_alloc(9F)) are 367 * available for use by the driver. 368 * 369 * The attach() function will be called once for each instance 370 * of the device on the system with cmd set to DDI_ATTACH. 371 * Until attach() succeeds, the only driver entry points which 372 * may be called are open(9E) and getinfo(9E). 373 */ 374 static int 375 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 376 { 377 igb_t *igb; 378 struct igb_osdep *osdep; 379 struct e1000_hw *hw; 380 int instance; 381 382 /* 383 * Check the command and perform corresponding operations 384 */ 385 switch (cmd) { 386 default: 387 return (DDI_FAILURE); 388 389 case DDI_RESUME: 390 return (igb_resume(devinfo)); 391 392 case DDI_ATTACH: 393 break; 394 } 395 396 /* Get the device instance */ 397 instance = ddi_get_instance(devinfo); 398 399 /* Allocate memory for the instance data structure */ 400 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 401 402 igb->dip = devinfo; 403 igb->instance = instance; 404 405 hw = &igb->hw; 406 osdep = &igb->osdep; 407 hw->back = osdep; 408 osdep->igb = igb; 409 410 /* Attach the instance pointer to the dev_info data structure */ 411 ddi_set_driver_private(devinfo, igb); 412 413 414 /* Initialize for fma support */ 415 igb->fm_capabilities = igb_get_prop(igb, "fm-capable", 416 0, 0x0f, 417 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 418 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 419 igb_fm_init(igb); 420 igb->attach_progress |= ATTACH_PROGRESS_FMINIT; 421 422 /* 423 * Map PCI config space registers 424 */ 425 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 426 igb_error(igb, "Failed to map PCI configurations"); 427 goto attach_fail; 428 } 429 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 430 431 /* 432 * Identify the chipset family 433 */ 434 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 435 igb_error(igb, "Failed to identify hardware"); 436 goto attach_fail; 437 } 438 439 /* 440 * Map device registers 441 */ 442 if (igb_regs_map(igb) != IGB_SUCCESS) { 443 igb_error(igb, "Failed to map device registers"); 444 goto attach_fail; 445 } 446 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 447 448 /* 449 * Initialize driver parameters 450 */ 451 igb_init_properties(igb); 452 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 453 454 /* 455 * Allocate interrupts 456 */ 457 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 458 igb_error(igb, "Failed to allocate interrupts"); 459 goto attach_fail; 460 } 461 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 462 463 /* 464 * Allocate rx/tx rings based on the ring numbers. 465 * The actual numbers of rx/tx rings are decided by the number of 466 * allocated interrupt vectors, so we should allocate the rings after 467 * interrupts are allocated. 468 */ 469 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 470 igb_error(igb, "Failed to allocate rx/tx rings or groups"); 471 goto attach_fail; 472 } 473 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 474 475 /* 476 * Add interrupt handlers 477 */ 478 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 479 igb_error(igb, "Failed to add interrupt handlers"); 480 goto attach_fail; 481 } 482 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 483 484 /* 485 * Initialize driver parameters 486 */ 487 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 488 igb_error(igb, "Failed to initialize driver settings"); 489 goto attach_fail; 490 } 491 492 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) { 493 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 494 goto attach_fail; 495 } 496 497 /* 498 * Initialize mutexes for this device. 499 * Do this before enabling the interrupt handler and 500 * register the softint to avoid the condition where 501 * interrupt handler can try using uninitialized mutex 502 */ 503 igb_init_locks(igb); 504 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 505 506 /* 507 * Initialize the adapter 508 */ 509 if (igb_init(igb) != IGB_SUCCESS) { 510 igb_error(igb, "Failed to initialize adapter"); 511 goto attach_fail; 512 } 513 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 514 515 /* 516 * Initialize statistics 517 */ 518 if (igb_init_stats(igb) != IGB_SUCCESS) { 519 igb_error(igb, "Failed to initialize statistics"); 520 goto attach_fail; 521 } 522 igb->attach_progress |= ATTACH_PROGRESS_STATS; 523 524 /* 525 * Register the driver to the MAC 526 */ 527 if (igb_register_mac(igb) != IGB_SUCCESS) { 528 igb_error(igb, "Failed to register MAC"); 529 goto attach_fail; 530 } 531 igb->attach_progress |= ATTACH_PROGRESS_MAC; 532 533 /* 534 * Now that mutex locks are initialized, and the chip is also 535 * initialized, enable interrupts. 536 */ 537 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 538 igb_error(igb, "Failed to enable DDI interrupts"); 539 goto attach_fail; 540 } 541 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 542 543 igb_log(igb, "%s", igb_version); 544 atomic_or_32(&igb->igb_state, IGB_INITIALIZED); 545 546 /* 547 * Newer models have Energy Efficient Ethernet, let's disable this by 548 * default. 549 */ 550 if (igb->hw.mac.type == e1000_i350) 551 (void) e1000_set_eee_i350(&igb->hw); 552 553 return (DDI_SUCCESS); 554 555 attach_fail: 556 igb_unconfigure(devinfo, igb); 557 return (DDI_FAILURE); 558 } 559 560 /* 561 * igb_detach - driver detach 562 * 563 * The detach() function is the complement of the attach routine. 564 * If cmd is set to DDI_DETACH, detach() is used to remove the 565 * state associated with a given instance of a device node 566 * prior to the removal of that instance from the system. 567 * 568 * The detach() function will be called once for each instance 569 * of the device for which there has been a successful attach() 570 * once there are no longer any opens on the device. 571 * 572 * Interrupts routine are disabled, All memory allocated by this 573 * driver are freed. 574 */ 575 static int 576 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 577 { 578 igb_t *igb; 579 580 /* 581 * Check detach command 582 */ 583 switch (cmd) { 584 default: 585 return (DDI_FAILURE); 586 587 case DDI_SUSPEND: 588 return (igb_suspend(devinfo)); 589 590 case DDI_DETACH: 591 break; 592 } 593 594 595 /* 596 * Get the pointer to the driver private data structure 597 */ 598 igb = (igb_t *)ddi_get_driver_private(devinfo); 599 if (igb == NULL) 600 return (DDI_FAILURE); 601 602 /* 603 * Unregister MAC. If failed, we have to fail the detach 604 */ 605 if (mac_unregister(igb->mac_hdl) != 0) { 606 igb_error(igb, "Failed to unregister MAC"); 607 return (DDI_FAILURE); 608 } 609 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 610 611 /* 612 * If the device is still running, it needs to be stopped first. 613 * This check is necessary because under some specific circumstances, 614 * the detach routine can be called without stopping the interface 615 * first. 616 */ 617 mutex_enter(&igb->gen_lock); 618 if (igb->igb_state & IGB_STARTED) { 619 atomic_and_32(&igb->igb_state, ~IGB_STARTED); 620 igb_stop(igb, B_TRUE); 621 mutex_exit(&igb->gen_lock); 622 /* Disable and stop the watchdog timer */ 623 igb_disable_watchdog_timer(igb); 624 } else 625 mutex_exit(&igb->gen_lock); 626 627 /* 628 * Check if there are still rx buffers held by the upper layer. 629 * If so, fail the detach. 630 */ 631 if (!igb_rx_drain(igb)) 632 return (DDI_FAILURE); 633 634 /* 635 * Do the remaining unconfigure routines 636 */ 637 igb_unconfigure(devinfo, igb); 638 639 return (DDI_SUCCESS); 640 } 641 642 /* 643 * quiesce(9E) entry point. 644 * 645 * This function is called when the system is single-threaded at high 646 * PIL with preemption disabled. Therefore, this function must not be 647 * blocked. 648 * 649 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 650 * DDI_FAILURE indicates an error condition and should almost never happen. 651 */ 652 static int 653 igb_quiesce(dev_info_t *devinfo) 654 { 655 igb_t *igb; 656 struct e1000_hw *hw; 657 658 igb = (igb_t *)ddi_get_driver_private(devinfo); 659 660 if (igb == NULL) 661 return (DDI_FAILURE); 662 663 hw = &igb->hw; 664 665 /* 666 * Disable the adapter interrupts 667 */ 668 igb_disable_adapter_interrupts(igb); 669 670 /* Tell firmware driver is no longer in control */ 671 igb_release_driver_control(hw); 672 673 /* 674 * Reset the chipset 675 */ 676 (void) e1000_reset_hw(hw); 677 678 /* 679 * Reset PHY if possible 680 */ 681 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 682 (void) e1000_phy_hw_reset(hw); 683 684 return (DDI_SUCCESS); 685 } 686 687 /* 688 * igb_unconfigure - release all resources held by this instance 689 */ 690 static void 691 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 692 { 693 /* 694 * Disable interrupt 695 */ 696 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 697 (void) igb_disable_intrs(igb); 698 } 699 700 /* 701 * Unregister MAC 702 */ 703 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 704 (void) mac_unregister(igb->mac_hdl); 705 } 706 707 /* 708 * Free statistics 709 */ 710 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 711 kstat_delete((kstat_t *)igb->igb_ks); 712 } 713 714 /* 715 * Remove interrupt handlers 716 */ 717 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 718 igb_rem_intr_handlers(igb); 719 } 720 721 /* 722 * Remove interrupts 723 */ 724 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 725 igb_rem_intrs(igb); 726 } 727 728 /* 729 * Remove driver properties 730 */ 731 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 732 (void) ddi_prop_remove_all(devinfo); 733 } 734 735 /* 736 * Stop the adapter 737 */ 738 if (igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) { 739 mutex_enter(&igb->gen_lock); 740 igb_stop_adapter(igb); 741 mutex_exit(&igb->gen_lock); 742 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 743 ddi_fm_service_impact(igb->dip, DDI_SERVICE_UNAFFECTED); 744 } 745 746 /* 747 * Free multicast table 748 */ 749 igb_release_multicast(igb); 750 751 /* 752 * Free register handle 753 */ 754 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 755 if (igb->osdep.reg_handle != NULL) 756 ddi_regs_map_free(&igb->osdep.reg_handle); 757 } 758 759 /* 760 * Free PCI config handle 761 */ 762 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 763 if (igb->osdep.cfg_handle != NULL) 764 pci_config_teardown(&igb->osdep.cfg_handle); 765 } 766 767 /* 768 * Free locks 769 */ 770 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 771 igb_destroy_locks(igb); 772 } 773 774 /* 775 * Free the rx/tx rings 776 */ 777 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 778 igb_free_rings(igb); 779 } 780 781 /* 782 * Remove FMA 783 */ 784 if (igb->attach_progress & ATTACH_PROGRESS_FMINIT) { 785 igb_fm_fini(igb); 786 } 787 788 /* 789 * Free the driver data structure 790 */ 791 kmem_free(igb, sizeof (igb_t)); 792 793 ddi_set_driver_private(devinfo, NULL); 794 } 795 796 /* 797 * igb_register_mac - Register the driver and its function pointers with 798 * the GLD interface 799 */ 800 static int 801 igb_register_mac(igb_t *igb) 802 { 803 struct e1000_hw *hw = &igb->hw; 804 mac_register_t *mac; 805 int status; 806 807 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 808 return (IGB_FAILURE); 809 810 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 811 mac->m_driver = igb; 812 mac->m_dip = igb->dip; 813 mac->m_src_addr = hw->mac.addr; 814 mac->m_callbacks = &igb_m_callbacks; 815 mac->m_min_sdu = 0; 816 mac->m_max_sdu = igb->max_frame_size - 817 sizeof (struct ether_vlan_header) - ETHERFCSL; 818 mac->m_margin = VLAN_TAGSZ; 819 mac->m_priv_props = igb_priv_props; 820 mac->m_v12n = MAC_VIRT_LEVEL1; 821 822 status = mac_register(mac, &igb->mac_hdl); 823 824 mac_free(mac); 825 826 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 827 } 828 829 /* 830 * igb_identify_hardware - Identify the type of the chipset 831 */ 832 static int 833 igb_identify_hardware(igb_t *igb) 834 { 835 struct e1000_hw *hw = &igb->hw; 836 struct igb_osdep *osdep = &igb->osdep; 837 838 /* 839 * Get the device id 840 */ 841 hw->vendor_id = 842 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 843 hw->device_id = 844 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 845 hw->revision_id = 846 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 847 hw->subsystem_device_id = 848 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 849 hw->subsystem_vendor_id = 850 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 851 852 /* 853 * Set the mac type of the adapter based on the device id 854 */ 855 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 856 return (IGB_FAILURE); 857 } 858 859 /* 860 * Install adapter capabilities based on mac type 861 */ 862 switch (hw->mac.type) { 863 case e1000_82575: 864 igb->capab = &igb_82575_cap; 865 break; 866 case e1000_82576: 867 igb->capab = &igb_82576_cap; 868 break; 869 case e1000_82580: 870 igb->capab = &igb_82580_cap; 871 break; 872 case e1000_i350: 873 igb->capab = &igb_i350_cap; 874 break; 875 default: 876 return (IGB_FAILURE); 877 } 878 879 return (IGB_SUCCESS); 880 } 881 882 /* 883 * igb_regs_map - Map the device registers 884 */ 885 static int 886 igb_regs_map(igb_t *igb) 887 { 888 dev_info_t *devinfo = igb->dip; 889 struct e1000_hw *hw = &igb->hw; 890 struct igb_osdep *osdep = &igb->osdep; 891 off_t mem_size; 892 893 /* 894 * First get the size of device registers to be mapped. 895 */ 896 if (ddi_dev_regsize(devinfo, IGB_ADAPTER_REGSET, &mem_size) != 897 DDI_SUCCESS) { 898 return (IGB_FAILURE); 899 } 900 901 /* 902 * Call ddi_regs_map_setup() to map registers 903 */ 904 if ((ddi_regs_map_setup(devinfo, IGB_ADAPTER_REGSET, 905 (caddr_t *)&hw->hw_addr, 0, 906 mem_size, &igb_regs_acc_attr, 907 &osdep->reg_handle)) != DDI_SUCCESS) { 908 return (IGB_FAILURE); 909 } 910 911 return (IGB_SUCCESS); 912 } 913 914 /* 915 * igb_init_properties - Initialize driver properties 916 */ 917 static void 918 igb_init_properties(igb_t *igb) 919 { 920 /* 921 * Get conf file properties, including link settings 922 * jumbo frames, ring number, descriptor number, etc. 923 */ 924 igb_get_conf(igb); 925 } 926 927 /* 928 * igb_init_driver_settings - Initialize driver settings 929 * 930 * The settings include hardware function pointers, bus information, 931 * rx/tx rings settings, link state, and any other parameters that 932 * need to be setup during driver initialization. 933 */ 934 static int 935 igb_init_driver_settings(igb_t *igb) 936 { 937 struct e1000_hw *hw = &igb->hw; 938 igb_rx_ring_t *rx_ring; 939 igb_tx_ring_t *tx_ring; 940 uint32_t rx_size; 941 uint32_t tx_size; 942 int i; 943 944 /* 945 * Initialize chipset specific hardware function pointers 946 */ 947 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 948 return (IGB_FAILURE); 949 } 950 951 /* 952 * Get bus information 953 */ 954 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 955 return (IGB_FAILURE); 956 } 957 958 /* 959 * Get the system page size 960 */ 961 igb->page_size = ddi_ptob(igb->dip, (ulong_t)1); 962 963 /* 964 * Set rx buffer size 965 * The IP header alignment room is counted in the calculation. 966 * The rx buffer size is in unit of 1K that is required by the 967 * chipset hardware. 968 */ 969 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 970 igb->rx_buf_size = ((rx_size >> 10) + 971 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 972 973 /* 974 * Set tx buffer size 975 */ 976 tx_size = igb->max_frame_size; 977 igb->tx_buf_size = ((tx_size >> 10) + 978 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 979 980 /* 981 * Initialize rx/tx rings parameters 982 */ 983 for (i = 0; i < igb->num_rx_rings; i++) { 984 rx_ring = &igb->rx_rings[i]; 985 rx_ring->index = i; 986 rx_ring->igb = igb; 987 } 988 989 for (i = 0; i < igb->num_tx_rings; i++) { 990 tx_ring = &igb->tx_rings[i]; 991 tx_ring->index = i; 992 tx_ring->igb = igb; 993 if (igb->tx_head_wb_enable) 994 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 995 else 996 tx_ring->tx_recycle = igb_tx_recycle_legacy; 997 998 tx_ring->ring_size = igb->tx_ring_size; 999 tx_ring->free_list_size = igb->tx_ring_size + 1000 (igb->tx_ring_size >> 1); 1001 } 1002 1003 /* 1004 * Initialize values of interrupt throttling rates 1005 */ 1006 for (i = 1; i < MAX_NUM_EITR; i++) 1007 igb->intr_throttling[i] = igb->intr_throttling[0]; 1008 1009 /* 1010 * The initial link state should be "unknown" 1011 */ 1012 igb->link_state = LINK_STATE_UNKNOWN; 1013 1014 return (IGB_SUCCESS); 1015 } 1016 1017 /* 1018 * igb_init_locks - Initialize locks 1019 */ 1020 static void 1021 igb_init_locks(igb_t *igb) 1022 { 1023 igb_rx_ring_t *rx_ring; 1024 igb_tx_ring_t *tx_ring; 1025 int i; 1026 1027 for (i = 0; i < igb->num_rx_rings; i++) { 1028 rx_ring = &igb->rx_rings[i]; 1029 mutex_init(&rx_ring->rx_lock, NULL, 1030 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1031 } 1032 1033 for (i = 0; i < igb->num_tx_rings; i++) { 1034 tx_ring = &igb->tx_rings[i]; 1035 mutex_init(&tx_ring->tx_lock, NULL, 1036 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1037 mutex_init(&tx_ring->recycle_lock, NULL, 1038 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1039 mutex_init(&tx_ring->tcb_head_lock, NULL, 1040 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1041 mutex_init(&tx_ring->tcb_tail_lock, NULL, 1042 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1043 } 1044 1045 mutex_init(&igb->gen_lock, NULL, 1046 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1047 1048 mutex_init(&igb->watchdog_lock, NULL, 1049 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1050 1051 mutex_init(&igb->link_lock, NULL, 1052 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 1053 } 1054 1055 /* 1056 * igb_destroy_locks - Destroy locks 1057 */ 1058 static void 1059 igb_destroy_locks(igb_t *igb) 1060 { 1061 igb_rx_ring_t *rx_ring; 1062 igb_tx_ring_t *tx_ring; 1063 int i; 1064 1065 for (i = 0; i < igb->num_rx_rings; i++) { 1066 rx_ring = &igb->rx_rings[i]; 1067 mutex_destroy(&rx_ring->rx_lock); 1068 } 1069 1070 for (i = 0; i < igb->num_tx_rings; i++) { 1071 tx_ring = &igb->tx_rings[i]; 1072 mutex_destroy(&tx_ring->tx_lock); 1073 mutex_destroy(&tx_ring->recycle_lock); 1074 mutex_destroy(&tx_ring->tcb_head_lock); 1075 mutex_destroy(&tx_ring->tcb_tail_lock); 1076 } 1077 1078 mutex_destroy(&igb->gen_lock); 1079 mutex_destroy(&igb->watchdog_lock); 1080 mutex_destroy(&igb->link_lock); 1081 } 1082 1083 static int 1084 igb_resume(dev_info_t *devinfo) 1085 { 1086 igb_t *igb; 1087 1088 igb = (igb_t *)ddi_get_driver_private(devinfo); 1089 if (igb == NULL) 1090 return (DDI_FAILURE); 1091 1092 mutex_enter(&igb->gen_lock); 1093 1094 /* 1095 * Enable interrupts 1096 */ 1097 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1098 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 1099 igb_error(igb, "Failed to enable DDI interrupts"); 1100 mutex_exit(&igb->gen_lock); 1101 return (DDI_FAILURE); 1102 } 1103 } 1104 1105 if (igb->igb_state & IGB_STARTED) { 1106 if (igb_start(igb, B_FALSE) != IGB_SUCCESS) { 1107 mutex_exit(&igb->gen_lock); 1108 return (DDI_FAILURE); 1109 } 1110 1111 /* 1112 * Enable and start the watchdog timer 1113 */ 1114 igb_enable_watchdog_timer(igb); 1115 } 1116 1117 atomic_and_32(&igb->igb_state, ~IGB_SUSPENDED); 1118 1119 mutex_exit(&igb->gen_lock); 1120 1121 return (DDI_SUCCESS); 1122 } 1123 1124 static int 1125 igb_suspend(dev_info_t *devinfo) 1126 { 1127 igb_t *igb; 1128 1129 igb = (igb_t *)ddi_get_driver_private(devinfo); 1130 if (igb == NULL) 1131 return (DDI_FAILURE); 1132 1133 mutex_enter(&igb->gen_lock); 1134 1135 atomic_or_32(&igb->igb_state, IGB_SUSPENDED); 1136 1137 /* 1138 * Disable interrupts 1139 */ 1140 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1141 (void) igb_disable_intrs(igb); 1142 } 1143 1144 if (!(igb->igb_state & IGB_STARTED)) { 1145 mutex_exit(&igb->gen_lock); 1146 return (DDI_SUCCESS); 1147 } 1148 1149 igb_stop(igb, B_FALSE); 1150 1151 mutex_exit(&igb->gen_lock); 1152 1153 /* 1154 * Disable and stop the watchdog timer 1155 */ 1156 igb_disable_watchdog_timer(igb); 1157 1158 return (DDI_SUCCESS); 1159 } 1160 1161 static int 1162 igb_init(igb_t *igb) 1163 { 1164 mutex_enter(&igb->gen_lock); 1165 1166 /* 1167 * Initilize the adapter 1168 */ 1169 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1170 mutex_exit(&igb->gen_lock); 1171 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1172 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1173 return (IGB_FAILURE); 1174 } 1175 1176 mutex_exit(&igb->gen_lock); 1177 1178 return (IGB_SUCCESS); 1179 } 1180 1181 /* 1182 * igb_init_mac_address - Initialize the default MAC address 1183 * 1184 * On success, the MAC address is entered in the igb->hw.mac.addr 1185 * and hw->mac.perm_addr fields and the adapter's RAR(0) receive 1186 * address register. 1187 * 1188 * Important side effects: 1189 * 1. adapter is reset - this is required to put it in a known state. 1190 * 2. all of non-volatile memory (NVM) is read & checksummed - NVM is where 1191 * MAC address and all default settings are stored, so a valid checksum 1192 * is required. 1193 */ 1194 static int 1195 igb_init_mac_address(igb_t *igb) 1196 { 1197 struct e1000_hw *hw = &igb->hw; 1198 1199 ASSERT(mutex_owned(&igb->gen_lock)); 1200 1201 /* 1202 * Reset chipset to put the hardware in a known state 1203 * before we try to get MAC address from NVM. 1204 */ 1205 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1206 igb_error(igb, "Adapter reset failed."); 1207 goto init_mac_fail; 1208 } 1209 1210 /* 1211 * NVM validation 1212 */ 1213 if (e1000_validate_nvm_checksum(hw) < 0) { 1214 /* 1215 * Some PCI-E parts fail the first check due to 1216 * the link being in sleep state. Call it again, 1217 * if it fails a second time its a real issue. 1218 */ 1219 if (e1000_validate_nvm_checksum(hw) < 0) { 1220 igb_error(igb, 1221 "Invalid NVM checksum. Please contact " 1222 "the vendor to update the NVM."); 1223 goto init_mac_fail; 1224 } 1225 } 1226 1227 /* 1228 * Get the mac address 1229 * This function should handle SPARC case correctly. 1230 */ 1231 if (!igb_find_mac_address(igb)) { 1232 igb_error(igb, "Failed to get the mac address"); 1233 goto init_mac_fail; 1234 } 1235 1236 /* Validate mac address */ 1237 if (!is_valid_mac_addr(hw->mac.addr)) { 1238 igb_error(igb, "Invalid mac address"); 1239 goto init_mac_fail; 1240 } 1241 1242 return (IGB_SUCCESS); 1243 1244 init_mac_fail: 1245 return (IGB_FAILURE); 1246 } 1247 1248 /* 1249 * igb_init_adapter - Initialize the adapter 1250 */ 1251 static int 1252 igb_init_adapter(igb_t *igb) 1253 { 1254 struct e1000_hw *hw = &igb->hw; 1255 uint32_t pba; 1256 uint32_t high_water; 1257 int oemid[2]; 1258 uint16_t nvmword; 1259 u8 pbanum[E1000_PBANUM_LENGTH]; 1260 char eepromver[5]; /* f.ff */ 1261 int i; 1262 1263 ASSERT(mutex_owned(&igb->gen_lock)); 1264 1265 /* 1266 * In order to obtain the default MAC address, this will reset the 1267 * adapter and validate the NVM that the address and many other 1268 * default settings come from. 1269 */ 1270 if (igb_init_mac_address(igb) != IGB_SUCCESS) { 1271 igb_error(igb, "Failed to initialize MAC address"); 1272 goto init_adapter_fail; 1273 } 1274 1275 /* 1276 * Setup flow control 1277 * 1278 * These parameters set thresholds for the adapter's generation(Tx) 1279 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1280 * settings. Flow control is enabled or disabled in the configuration 1281 * file. 1282 * High-water mark is set down from the top of the rx fifo (not 1283 * sensitive to max_frame_size) and low-water is set just below 1284 * high-water mark. 1285 * The high water mark must be low enough to fit one full frame above 1286 * it in the rx FIFO. Should be the lower of: 1287 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 1288 * frame. 1289 */ 1290 /* 1291 * The default setting of PBA is correct for 82575 and other supported 1292 * adapters do not have the E1000_PBA register, so PBA value is only 1293 * used for calculation here and is never written to the adapter. 1294 */ 1295 if (hw->mac.type == e1000_82575) { 1296 pba = E1000_PBA_34K; 1297 } else { 1298 pba = E1000_PBA_64K; 1299 } 1300 1301 high_water = min(((pba << 10) * 9 / 10), 1302 ((pba << 10) - igb->max_frame_size)); 1303 1304 if (hw->mac.type == e1000_82575) { 1305 /* 8-byte granularity */ 1306 hw->fc.high_water = high_water & 0xFFF8; 1307 hw->fc.low_water = hw->fc.high_water - 8; 1308 } else { 1309 /* 16-byte granularity */ 1310 hw->fc.high_water = high_water & 0xFFF0; 1311 hw->fc.low_water = hw->fc.high_water - 16; 1312 } 1313 1314 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1315 hw->fc.send_xon = B_TRUE; 1316 1317 (void) e1000_validate_mdi_setting(hw); 1318 1319 /* 1320 * Reset the chipset hardware the second time to put PBA settings 1321 * into effect. 1322 */ 1323 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1324 igb_error(igb, "Second reset failed"); 1325 goto init_adapter_fail; 1326 } 1327 1328 /* 1329 * Don't wait for auto-negotiation to complete 1330 */ 1331 hw->phy.autoneg_wait_to_complete = B_FALSE; 1332 1333 /* 1334 * Copper options 1335 */ 1336 if (hw->phy.media_type == e1000_media_type_copper) { 1337 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1338 hw->phy.disable_polarity_correction = B_FALSE; 1339 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1340 } 1341 1342 /* 1343 * Initialize link settings 1344 */ 1345 (void) igb_setup_link(igb, B_FALSE); 1346 1347 /* 1348 * Configure/Initialize hardware 1349 */ 1350 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1351 igb_error(igb, "Failed to initialize hardware"); 1352 goto init_adapter_fail; 1353 } 1354 1355 /* 1356 * Start the link setup timer 1357 */ 1358 igb_start_link_timer(igb); 1359 1360 /* 1361 * Disable wakeup control by default 1362 */ 1363 E1000_WRITE_REG(hw, E1000_WUC, 0); 1364 1365 /* 1366 * Record phy info in hw struct 1367 */ 1368 (void) e1000_get_phy_info(hw); 1369 1370 /* 1371 * Make sure driver has control 1372 */ 1373 igb_get_driver_control(hw); 1374 1375 /* 1376 * Restore LED settings to the default from EEPROM 1377 * to meet the standard for Sun platforms. 1378 */ 1379 (void) e1000_cleanup_led(hw); 1380 1381 /* 1382 * Setup MSI-X interrupts 1383 */ 1384 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1385 igb->capab->setup_msix(igb); 1386 1387 /* 1388 * Initialize unicast addresses. 1389 */ 1390 igb_init_unicst(igb); 1391 1392 /* 1393 * Setup and initialize the mctable structures. 1394 */ 1395 igb_setup_multicst(igb); 1396 1397 /* 1398 * Set interrupt throttling rate 1399 */ 1400 for (i = 0; i < igb->intr_cnt; i++) 1401 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1402 1403 /* 1404 * Read identifying information and place in devinfo. 1405 */ 1406 nvmword = 0xffff; 1407 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_0, 1, &nvmword); 1408 oemid[0] = (int)nvmword; 1409 (void) e1000_read_nvm(&igb->hw, NVM_OEM_OFFSET_1, 1, &nvmword); 1410 oemid[1] = (int)nvmword; 1411 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, igb->dip, 1412 "oem-identifier", oemid, 2); 1413 1414 pbanum[0] = '\0'; 1415 (void) e1000_read_pba_string(&igb->hw, pbanum, sizeof (pbanum)); 1416 if (*pbanum != '\0') { 1417 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip, 1418 "printed-board-assembly", (char *)pbanum); 1419 } 1420 1421 nvmword = 0xffff; 1422 (void) e1000_read_nvm(&igb->hw, NVM_VERSION, 1, &nvmword); 1423 if ((nvmword & 0xf00) == 0) { 1424 (void) snprintf(eepromver, sizeof (eepromver), "%x.%x", 1425 (nvmword & 0xf000) >> 12, (nvmword & 0xff)); 1426 (void) ddi_prop_update_string(DDI_DEV_T_NONE, igb->dip, 1427 "nvm-version", eepromver); 1428 } 1429 1430 /* 1431 * Save the state of the phy 1432 */ 1433 igb_get_phy_state(igb); 1434 1435 igb_param_sync(igb); 1436 1437 return (IGB_SUCCESS); 1438 1439 init_adapter_fail: 1440 /* 1441 * Reset PHY if possible 1442 */ 1443 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1444 (void) e1000_phy_hw_reset(hw); 1445 1446 return (IGB_FAILURE); 1447 } 1448 1449 /* 1450 * igb_stop_adapter - Stop the adapter 1451 */ 1452 static void 1453 igb_stop_adapter(igb_t *igb) 1454 { 1455 struct e1000_hw *hw = &igb->hw; 1456 1457 ASSERT(mutex_owned(&igb->gen_lock)); 1458 1459 /* Stop the link setup timer */ 1460 igb_stop_link_timer(igb); 1461 1462 /* Tell firmware driver is no longer in control */ 1463 igb_release_driver_control(hw); 1464 1465 /* 1466 * Reset the chipset 1467 */ 1468 if (e1000_reset_hw(hw) != E1000_SUCCESS) { 1469 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1470 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1471 } 1472 1473 /* 1474 * e1000_phy_hw_reset is not needed here, MAC reset above is sufficient 1475 */ 1476 } 1477 1478 /* 1479 * igb_reset - Reset the chipset and restart the driver. 1480 * 1481 * It involves stopping and re-starting the chipset, 1482 * and re-configuring the rx/tx rings. 1483 */ 1484 static int 1485 igb_reset(igb_t *igb) 1486 { 1487 int i; 1488 1489 mutex_enter(&igb->gen_lock); 1490 1491 ASSERT(igb->igb_state & IGB_STARTED); 1492 atomic_and_32(&igb->igb_state, ~IGB_STARTED); 1493 1494 /* 1495 * Disable the adapter interrupts to stop any rx/tx activities 1496 * before draining pending data and resetting hardware. 1497 */ 1498 igb_disable_adapter_interrupts(igb); 1499 1500 /* 1501 * Drain the pending transmit packets 1502 */ 1503 (void) igb_tx_drain(igb); 1504 1505 for (i = 0; i < igb->num_rx_rings; i++) 1506 mutex_enter(&igb->rx_rings[i].rx_lock); 1507 for (i = 0; i < igb->num_tx_rings; i++) 1508 mutex_enter(&igb->tx_rings[i].tx_lock); 1509 1510 /* 1511 * Stop the adapter 1512 */ 1513 igb_stop_adapter(igb); 1514 1515 /* 1516 * Clean the pending tx data/resources 1517 */ 1518 igb_tx_clean(igb); 1519 1520 /* 1521 * Start the adapter 1522 */ 1523 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1524 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1525 goto reset_failure; 1526 } 1527 1528 /* 1529 * Setup the rx/tx rings 1530 */ 1531 igb->tx_ring_init = B_FALSE; 1532 igb_setup_rings(igb); 1533 1534 atomic_and_32(&igb->igb_state, ~(IGB_ERROR | IGB_STALL)); 1535 1536 /* 1537 * Enable adapter interrupts 1538 * The interrupts must be enabled after the driver state is START 1539 */ 1540 igb->capab->enable_intr(igb); 1541 1542 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1543 goto reset_failure; 1544 1545 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1546 goto reset_failure; 1547 1548 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1549 mutex_exit(&igb->tx_rings[i].tx_lock); 1550 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1551 mutex_exit(&igb->rx_rings[i].rx_lock); 1552 1553 atomic_or_32(&igb->igb_state, IGB_STARTED); 1554 1555 mutex_exit(&igb->gen_lock); 1556 1557 return (IGB_SUCCESS); 1558 1559 reset_failure: 1560 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1561 mutex_exit(&igb->tx_rings[i].tx_lock); 1562 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1563 mutex_exit(&igb->rx_rings[i].rx_lock); 1564 1565 mutex_exit(&igb->gen_lock); 1566 1567 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1568 1569 return (IGB_FAILURE); 1570 } 1571 1572 /* 1573 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1574 */ 1575 static void 1576 igb_tx_clean(igb_t *igb) 1577 { 1578 igb_tx_ring_t *tx_ring; 1579 tx_control_block_t *tcb; 1580 link_list_t pending_list; 1581 uint32_t desc_num; 1582 int i, j; 1583 1584 LINK_LIST_INIT(&pending_list); 1585 1586 for (i = 0; i < igb->num_tx_rings; i++) { 1587 tx_ring = &igb->tx_rings[i]; 1588 1589 mutex_enter(&tx_ring->recycle_lock); 1590 1591 /* 1592 * Clean the pending tx data - the pending packets in the 1593 * work_list that have no chances to be transmitted again. 1594 * 1595 * We must ensure the chipset is stopped or the link is down 1596 * before cleaning the transmit packets. 1597 */ 1598 desc_num = 0; 1599 for (j = 0; j < tx_ring->ring_size; j++) { 1600 tcb = tx_ring->work_list[j]; 1601 if (tcb != NULL) { 1602 desc_num += tcb->desc_num; 1603 1604 tx_ring->work_list[j] = NULL; 1605 1606 igb_free_tcb(tcb); 1607 1608 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1609 } 1610 } 1611 1612 if (desc_num > 0) { 1613 atomic_add_32(&tx_ring->tbd_free, desc_num); 1614 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1615 1616 /* 1617 * Reset the head and tail pointers of the tbd ring; 1618 * Reset the head write-back if it is enabled. 1619 */ 1620 tx_ring->tbd_head = 0; 1621 tx_ring->tbd_tail = 0; 1622 if (igb->tx_head_wb_enable) 1623 *tx_ring->tbd_head_wb = 0; 1624 1625 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1626 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1627 } 1628 1629 mutex_exit(&tx_ring->recycle_lock); 1630 1631 /* 1632 * Add the tx control blocks in the pending list to 1633 * the free list. 1634 */ 1635 igb_put_free_list(tx_ring, &pending_list); 1636 } 1637 } 1638 1639 /* 1640 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1641 */ 1642 static boolean_t 1643 igb_tx_drain(igb_t *igb) 1644 { 1645 igb_tx_ring_t *tx_ring; 1646 boolean_t done; 1647 int i, j; 1648 1649 /* 1650 * Wait for a specific time to allow pending tx packets 1651 * to be transmitted. 1652 * 1653 * Check the counter tbd_free to see if transmission is done. 1654 * No lock protection is needed here. 1655 * 1656 * Return B_TRUE if all pending packets have been transmitted; 1657 * Otherwise return B_FALSE; 1658 */ 1659 for (i = 0; i < TX_DRAIN_TIME; i++) { 1660 1661 done = B_TRUE; 1662 for (j = 0; j < igb->num_tx_rings; j++) { 1663 tx_ring = &igb->tx_rings[j]; 1664 done = done && 1665 (tx_ring->tbd_free == tx_ring->ring_size); 1666 } 1667 1668 if (done) 1669 break; 1670 1671 msec_delay(1); 1672 } 1673 1674 return (done); 1675 } 1676 1677 /* 1678 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1679 */ 1680 static boolean_t 1681 igb_rx_drain(igb_t *igb) 1682 { 1683 boolean_t done; 1684 int i; 1685 1686 /* 1687 * Polling the rx free list to check if those rx buffers held by 1688 * the upper layer are released. 1689 * 1690 * Check the counter rcb_free to see if all pending buffers are 1691 * released. No lock protection is needed here. 1692 * 1693 * Return B_TRUE if all pending buffers have been released; 1694 * Otherwise return B_FALSE; 1695 */ 1696 for (i = 0; i < RX_DRAIN_TIME; i++) { 1697 done = (igb->rcb_pending == 0); 1698 1699 if (done) 1700 break; 1701 1702 msec_delay(1); 1703 } 1704 1705 return (done); 1706 } 1707 1708 /* 1709 * igb_start - Start the driver/chipset 1710 */ 1711 int 1712 igb_start(igb_t *igb, boolean_t alloc_buffer) 1713 { 1714 int i; 1715 1716 ASSERT(mutex_owned(&igb->gen_lock)); 1717 1718 if (alloc_buffer) { 1719 if (igb_alloc_rx_data(igb) != IGB_SUCCESS) { 1720 igb_error(igb, 1721 "Failed to allocate software receive rings"); 1722 return (IGB_FAILURE); 1723 } 1724 1725 /* Allocate buffers for all the rx/tx rings */ 1726 if (igb_alloc_dma(igb) != IGB_SUCCESS) { 1727 igb_error(igb, "Failed to allocate DMA resource"); 1728 return (IGB_FAILURE); 1729 } 1730 1731 igb->tx_ring_init = B_TRUE; 1732 } else { 1733 igb->tx_ring_init = B_FALSE; 1734 } 1735 1736 for (i = 0; i < igb->num_rx_rings; i++) 1737 mutex_enter(&igb->rx_rings[i].rx_lock); 1738 for (i = 0; i < igb->num_tx_rings; i++) 1739 mutex_enter(&igb->tx_rings[i].tx_lock); 1740 1741 /* 1742 * Start the adapter 1743 */ 1744 if ((igb->attach_progress & ATTACH_PROGRESS_INIT_ADAPTER) == 0) { 1745 if (igb_init_adapter(igb) != IGB_SUCCESS) { 1746 igb_fm_ereport(igb, DDI_FM_DEVICE_INVAL_STATE); 1747 goto start_failure; 1748 } 1749 igb->attach_progress |= ATTACH_PROGRESS_INIT_ADAPTER; 1750 } 1751 1752 /* 1753 * Setup the rx/tx rings 1754 */ 1755 igb_setup_rings(igb); 1756 1757 /* 1758 * Enable adapter interrupts 1759 * The interrupts must be enabled after the driver state is START 1760 */ 1761 igb->capab->enable_intr(igb); 1762 1763 if (igb_check_acc_handle(igb->osdep.cfg_handle) != DDI_FM_OK) 1764 goto start_failure; 1765 1766 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1767 goto start_failure; 1768 1769 if (igb->hw.mac.type == e1000_i350) 1770 (void) e1000_set_eee_i350(&igb->hw); 1771 1772 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1773 mutex_exit(&igb->tx_rings[i].tx_lock); 1774 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1775 mutex_exit(&igb->rx_rings[i].rx_lock); 1776 1777 return (IGB_SUCCESS); 1778 1779 start_failure: 1780 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1781 mutex_exit(&igb->tx_rings[i].tx_lock); 1782 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1783 mutex_exit(&igb->rx_rings[i].rx_lock); 1784 1785 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1786 1787 return (IGB_FAILURE); 1788 } 1789 1790 /* 1791 * igb_stop - Stop the driver/chipset 1792 */ 1793 void 1794 igb_stop(igb_t *igb, boolean_t free_buffer) 1795 { 1796 int i; 1797 1798 ASSERT(mutex_owned(&igb->gen_lock)); 1799 1800 igb->attach_progress &= ~ATTACH_PROGRESS_INIT_ADAPTER; 1801 1802 /* 1803 * Disable the adapter interrupts 1804 */ 1805 igb_disable_adapter_interrupts(igb); 1806 1807 /* 1808 * Drain the pending tx packets 1809 */ 1810 (void) igb_tx_drain(igb); 1811 1812 for (i = 0; i < igb->num_rx_rings; i++) 1813 mutex_enter(&igb->rx_rings[i].rx_lock); 1814 for (i = 0; i < igb->num_tx_rings; i++) 1815 mutex_enter(&igb->tx_rings[i].tx_lock); 1816 1817 /* 1818 * Stop the adapter 1819 */ 1820 igb_stop_adapter(igb); 1821 1822 /* 1823 * Clean the pending tx data/resources 1824 */ 1825 igb_tx_clean(igb); 1826 1827 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1828 mutex_exit(&igb->tx_rings[i].tx_lock); 1829 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1830 mutex_exit(&igb->rx_rings[i].rx_lock); 1831 1832 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) 1833 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 1834 1835 if (igb->link_state == LINK_STATE_UP) { 1836 igb->link_state = LINK_STATE_UNKNOWN; 1837 mac_link_update(igb->mac_hdl, igb->link_state); 1838 } 1839 1840 if (free_buffer) { 1841 /* 1842 * Release the DMA/memory resources of rx/tx rings 1843 */ 1844 igb_free_dma(igb); 1845 igb_free_rx_data(igb); 1846 } 1847 } 1848 1849 /* 1850 * igb_alloc_rings - Allocate memory space for rx/tx rings 1851 */ 1852 static int 1853 igb_alloc_rings(igb_t *igb) 1854 { 1855 /* 1856 * Allocate memory space for rx rings 1857 */ 1858 igb->rx_rings = kmem_zalloc( 1859 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1860 KM_NOSLEEP); 1861 1862 if (igb->rx_rings == NULL) { 1863 return (IGB_FAILURE); 1864 } 1865 1866 /* 1867 * Allocate memory space for tx rings 1868 */ 1869 igb->tx_rings = kmem_zalloc( 1870 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1871 KM_NOSLEEP); 1872 1873 if (igb->tx_rings == NULL) { 1874 kmem_free(igb->rx_rings, 1875 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1876 igb->rx_rings = NULL; 1877 return (IGB_FAILURE); 1878 } 1879 1880 /* 1881 * Allocate memory space for rx ring groups 1882 */ 1883 igb->rx_groups = kmem_zalloc( 1884 sizeof (igb_rx_group_t) * igb->num_rx_groups, 1885 KM_NOSLEEP); 1886 1887 if (igb->rx_groups == NULL) { 1888 kmem_free(igb->rx_rings, 1889 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1890 kmem_free(igb->tx_rings, 1891 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1892 igb->rx_rings = NULL; 1893 igb->tx_rings = NULL; 1894 return (IGB_FAILURE); 1895 } 1896 1897 return (IGB_SUCCESS); 1898 } 1899 1900 /* 1901 * igb_free_rings - Free the memory space of rx/tx rings. 1902 */ 1903 static void 1904 igb_free_rings(igb_t *igb) 1905 { 1906 if (igb->rx_rings != NULL) { 1907 kmem_free(igb->rx_rings, 1908 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1909 igb->rx_rings = NULL; 1910 } 1911 1912 if (igb->tx_rings != NULL) { 1913 kmem_free(igb->tx_rings, 1914 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1915 igb->tx_rings = NULL; 1916 } 1917 1918 if (igb->rx_groups != NULL) { 1919 kmem_free(igb->rx_groups, 1920 sizeof (igb_rx_group_t) * igb->num_rx_groups); 1921 igb->rx_groups = NULL; 1922 } 1923 } 1924 1925 static int 1926 igb_alloc_rx_data(igb_t *igb) 1927 { 1928 igb_rx_ring_t *rx_ring; 1929 int i; 1930 1931 for (i = 0; i < igb->num_rx_rings; i++) { 1932 rx_ring = &igb->rx_rings[i]; 1933 if (igb_alloc_rx_ring_data(rx_ring) != IGB_SUCCESS) 1934 goto alloc_rx_rings_failure; 1935 } 1936 return (IGB_SUCCESS); 1937 1938 alloc_rx_rings_failure: 1939 igb_free_rx_data(igb); 1940 return (IGB_FAILURE); 1941 } 1942 1943 static void 1944 igb_free_rx_data(igb_t *igb) 1945 { 1946 igb_rx_ring_t *rx_ring; 1947 igb_rx_data_t *rx_data; 1948 int i; 1949 1950 for (i = 0; i < igb->num_rx_rings; i++) { 1951 rx_ring = &igb->rx_rings[i]; 1952 1953 mutex_enter(&igb->rx_pending_lock); 1954 rx_data = rx_ring->rx_data; 1955 1956 if (rx_data != NULL) { 1957 rx_data->flag |= IGB_RX_STOPPED; 1958 1959 if (rx_data->rcb_pending == 0) { 1960 igb_free_rx_ring_data(rx_data); 1961 rx_ring->rx_data = NULL; 1962 } 1963 } 1964 1965 mutex_exit(&igb->rx_pending_lock); 1966 } 1967 } 1968 1969 /* 1970 * igb_setup_rings - Setup rx/tx rings 1971 */ 1972 static void 1973 igb_setup_rings(igb_t *igb) 1974 { 1975 /* 1976 * Setup the rx/tx rings, including the following: 1977 * 1978 * 1. Setup the descriptor ring and the control block buffers; 1979 * 2. Initialize necessary registers for receive/transmit; 1980 * 3. Initialize software pointers/parameters for receive/transmit; 1981 */ 1982 igb_setup_rx(igb); 1983 1984 igb_setup_tx(igb); 1985 } 1986 1987 static void 1988 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1989 { 1990 igb_t *igb = rx_ring->igb; 1991 igb_rx_data_t *rx_data = rx_ring->rx_data; 1992 struct e1000_hw *hw = &igb->hw; 1993 rx_control_block_t *rcb; 1994 union e1000_adv_rx_desc *rbd; 1995 uint32_t size; 1996 uint32_t buf_low; 1997 uint32_t buf_high; 1998 uint32_t rxdctl; 1999 int i; 2000 2001 ASSERT(mutex_owned(&rx_ring->rx_lock)); 2002 ASSERT(mutex_owned(&igb->gen_lock)); 2003 2004 /* 2005 * Initialize descriptor ring with buffer addresses 2006 */ 2007 for (i = 0; i < igb->rx_ring_size; i++) { 2008 rcb = rx_data->work_list[i]; 2009 rbd = &rx_data->rbd_ring[i]; 2010 2011 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 2012 rbd->read.hdr_addr = NULL; 2013 } 2014 2015 /* 2016 * Initialize the base address registers 2017 */ 2018 buf_low = (uint32_t)rx_data->rbd_area.dma_address; 2019 buf_high = (uint32_t)(rx_data->rbd_area.dma_address >> 32); 2020 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 2021 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 2022 2023 /* 2024 * Initialize the length register 2025 */ 2026 size = rx_data->ring_size * sizeof (union e1000_adv_rx_desc); 2027 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 2028 2029 /* 2030 * Initialize buffer size & descriptor type 2031 */ 2032 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), 2033 ((igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 2034 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF)); 2035 2036 /* 2037 * Setup the Receive Descriptor Control Register (RXDCTL) 2038 */ 2039 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 2040 rxdctl &= igb->capab->rxdctl_mask; 2041 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 2042 rxdctl |= 16; /* pthresh */ 2043 rxdctl |= 8 << 8; /* hthresh */ 2044 rxdctl |= 1 << 16; /* wthresh */ 2045 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), rxdctl); 2046 2047 rx_data->rbd_next = 0; 2048 } 2049 2050 static void 2051 igb_setup_rx(igb_t *igb) 2052 { 2053 igb_rx_ring_t *rx_ring; 2054 igb_rx_data_t *rx_data; 2055 igb_rx_group_t *rx_group; 2056 struct e1000_hw *hw = &igb->hw; 2057 uint32_t rctl, rxcsum; 2058 uint32_t ring_per_group; 2059 int i; 2060 2061 /* 2062 * Setup the Receive Control Register (RCTL), and enable the 2063 * receiver. The initial configuration is to: enable the receiver, 2064 * accept broadcasts, discard bad packets, accept long packets, 2065 * disable VLAN filter checking, and set receive buffer size to 2066 * 2k. For 82575, also set the receive descriptor minimum 2067 * threshold size to 1/2 the ring. 2068 */ 2069 rctl = E1000_READ_REG(hw, E1000_RCTL); 2070 2071 /* 2072 * Clear the field used for wakeup control. This driver doesn't do 2073 * wakeup but leave this here for completeness. 2074 */ 2075 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2076 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 2077 2078 rctl |= (E1000_RCTL_EN | /* Enable Receive Unit */ 2079 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 2080 E1000_RCTL_LPE | /* Large Packet Enable */ 2081 /* Multicast filter offset */ 2082 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 2083 E1000_RCTL_RDMTS_HALF | /* rx descriptor threshold */ 2084 E1000_RCTL_SECRC); /* Strip Ethernet CRC */ 2085 2086 for (i = 0; i < igb->num_rx_groups; i++) { 2087 rx_group = &igb->rx_groups[i]; 2088 rx_group->index = i; 2089 rx_group->igb = igb; 2090 } 2091 2092 /* 2093 * Set up all rx descriptor rings - must be called before receive unit 2094 * enabled. 2095 */ 2096 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2097 for (i = 0; i < igb->num_rx_rings; i++) { 2098 rx_ring = &igb->rx_rings[i]; 2099 igb_setup_rx_ring(rx_ring); 2100 2101 /* 2102 * Map a ring to a group by assigning a group index 2103 */ 2104 rx_ring->group_index = i / ring_per_group; 2105 } 2106 2107 /* 2108 * Setup the Rx Long Packet Max Length register 2109 */ 2110 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 2111 2112 /* 2113 * Hardware checksum settings 2114 */ 2115 if (igb->rx_hcksum_enable) { 2116 rxcsum = 2117 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 2118 E1000_RXCSUM_IPOFL; /* IP checksum */ 2119 2120 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2121 } 2122 2123 /* 2124 * Setup classify and RSS for multiple receive queues 2125 */ 2126 switch (igb->vmdq_mode) { 2127 case E1000_VMDQ_OFF: 2128 /* 2129 * One ring group, only RSS is needed when more than 2130 * one ring enabled. 2131 */ 2132 if (igb->num_rx_rings > 1) 2133 igb_setup_rss(igb); 2134 break; 2135 case E1000_VMDQ_MAC: 2136 /* 2137 * Multiple groups, each group has one ring, 2138 * only the MAC classification is needed. 2139 */ 2140 igb_setup_mac_classify(igb); 2141 break; 2142 case E1000_VMDQ_MAC_RSS: 2143 /* 2144 * Multiple groups and multiple rings, both 2145 * MAC classification and RSS are needed. 2146 */ 2147 igb_setup_mac_rss_classify(igb); 2148 break; 2149 } 2150 2151 /* 2152 * Enable the receive unit - must be done after all 2153 * the rx setup above. 2154 */ 2155 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2156 2157 /* 2158 * Initialize all adapter ring head & tail pointers - must 2159 * be done after receive unit is enabled 2160 */ 2161 for (i = 0; i < igb->num_rx_rings; i++) { 2162 rx_ring = &igb->rx_rings[i]; 2163 rx_data = rx_ring->rx_data; 2164 E1000_WRITE_REG(hw, E1000_RDH(i), 0); 2165 E1000_WRITE_REG(hw, E1000_RDT(i), rx_data->ring_size - 1); 2166 } 2167 2168 /* 2169 * 82575 with manageability enabled needs a special flush to make 2170 * sure the fifos start clean. 2171 */ 2172 if ((hw->mac.type == e1000_82575) && 2173 (E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) { 2174 e1000_rx_fifo_flush_82575(hw); 2175 } 2176 } 2177 2178 static void 2179 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 2180 { 2181 igb_t *igb = tx_ring->igb; 2182 struct e1000_hw *hw = &igb->hw; 2183 uint32_t size; 2184 uint32_t buf_low; 2185 uint32_t buf_high; 2186 uint32_t reg_val; 2187 2188 ASSERT(mutex_owned(&tx_ring->tx_lock)); 2189 ASSERT(mutex_owned(&igb->gen_lock)); 2190 2191 2192 /* 2193 * Initialize the length register 2194 */ 2195 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 2196 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 2197 2198 /* 2199 * Initialize the base address registers 2200 */ 2201 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 2202 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 2203 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 2204 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 2205 2206 /* 2207 * Setup head & tail pointers 2208 */ 2209 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 2210 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 2211 2212 /* 2213 * Setup head write-back 2214 */ 2215 if (igb->tx_head_wb_enable) { 2216 /* 2217 * The memory of the head write-back is allocated using 2218 * the extra tbd beyond the tail of the tbd ring. 2219 */ 2220 tx_ring->tbd_head_wb = (uint32_t *) 2221 ((uintptr_t)tx_ring->tbd_area.address + size); 2222 *tx_ring->tbd_head_wb = 0; 2223 2224 buf_low = (uint32_t) 2225 (tx_ring->tbd_area.dma_address + size); 2226 buf_high = (uint32_t) 2227 ((tx_ring->tbd_area.dma_address + size) >> 32); 2228 2229 /* Set the head write-back enable bit */ 2230 buf_low |= E1000_TX_HEAD_WB_ENABLE; 2231 2232 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 2233 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 2234 2235 /* 2236 * Turn off relaxed ordering for head write back or it will 2237 * cause problems with the tx recycling 2238 */ 2239 reg_val = E1000_READ_REG(hw, 2240 E1000_DCA_TXCTRL(tx_ring->index)); 2241 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 2242 E1000_WRITE_REG(hw, 2243 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 2244 } else { 2245 tx_ring->tbd_head_wb = NULL; 2246 } 2247 2248 tx_ring->tbd_head = 0; 2249 tx_ring->tbd_tail = 0; 2250 tx_ring->tbd_free = tx_ring->ring_size; 2251 2252 if (igb->tx_ring_init == B_TRUE) { 2253 tx_ring->tcb_head = 0; 2254 tx_ring->tcb_tail = 0; 2255 tx_ring->tcb_free = tx_ring->free_list_size; 2256 } 2257 2258 /* 2259 * Enable TXDCTL per queue 2260 */ 2261 reg_val = E1000_READ_REG(hw, E1000_TXDCTL(tx_ring->index)); 2262 reg_val |= E1000_TXDCTL_QUEUE_ENABLE; 2263 E1000_WRITE_REG(hw, E1000_TXDCTL(tx_ring->index), reg_val); 2264 2265 /* 2266 * Initialize hardware checksum offload settings 2267 */ 2268 bzero(&tx_ring->tx_context, sizeof (tx_context_t)); 2269 } 2270 2271 static void 2272 igb_setup_tx(igb_t *igb) 2273 { 2274 igb_tx_ring_t *tx_ring; 2275 struct e1000_hw *hw = &igb->hw; 2276 uint32_t reg_val; 2277 int i; 2278 2279 for (i = 0; i < igb->num_tx_rings; i++) { 2280 tx_ring = &igb->tx_rings[i]; 2281 igb_setup_tx_ring(tx_ring); 2282 } 2283 2284 /* 2285 * Setup the Transmit Control Register (TCTL) 2286 */ 2287 reg_val = E1000_READ_REG(hw, E1000_TCTL); 2288 reg_val &= ~E1000_TCTL_CT; 2289 reg_val |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2290 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2291 2292 /* Enable transmits */ 2293 reg_val |= E1000_TCTL_EN; 2294 2295 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 2296 } 2297 2298 /* 2299 * igb_setup_rss - Setup receive-side scaling feature 2300 */ 2301 static void 2302 igb_setup_rss(igb_t *igb) 2303 { 2304 struct e1000_hw *hw = &igb->hw; 2305 uint32_t i, mrqc, rxcsum; 2306 int shift = 0; 2307 uint32_t random; 2308 union e1000_reta { 2309 uint32_t dword; 2310 uint8_t bytes[4]; 2311 } reta; 2312 2313 /* Setup the Redirection Table */ 2314 if (hw->mac.type == e1000_82576) { 2315 shift = 3; 2316 } else if (hw->mac.type == e1000_82575) { 2317 shift = 6; 2318 } 2319 for (i = 0; i < (32 * 4); i++) { 2320 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 2321 if ((i & 3) == 3) { 2322 E1000_WRITE_REG(hw, 2323 (E1000_RETA(0) + (i & ~3)), reta.dword); 2324 } 2325 } 2326 2327 /* Fill out hash function seeds */ 2328 for (i = 0; i < 10; i++) { 2329 (void) random_get_pseudo_bytes((uint8_t *)&random, 2330 sizeof (uint32_t)); 2331 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2332 } 2333 2334 /* Setup the Multiple Receive Queue Control register */ 2335 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 2336 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2337 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2338 E1000_MRQC_RSS_FIELD_IPV6 | 2339 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2340 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2341 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2342 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2343 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2344 2345 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2346 2347 /* 2348 * Disable Packet Checksum to enable RSS for multiple receive queues. 2349 * 2350 * The Packet Checksum is not ethernet CRC. It is another kind of 2351 * checksum offloading provided by the 82575 chipset besides the IP 2352 * header checksum offloading and the TCP/UDP checksum offloading. 2353 * The Packet Checksum is by default computed over the entire packet 2354 * from the first byte of the DA through the last byte of the CRC, 2355 * including the Ethernet and IP headers. 2356 * 2357 * It is a hardware limitation that Packet Checksum is mutually 2358 * exclusive with RSS. 2359 */ 2360 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2361 rxcsum |= E1000_RXCSUM_PCSD; 2362 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2363 } 2364 2365 /* 2366 * igb_setup_mac_rss_classify - Setup MAC classification and rss 2367 */ 2368 static void 2369 igb_setup_mac_rss_classify(igb_t *igb) 2370 { 2371 struct e1000_hw *hw = &igb->hw; 2372 uint32_t i, mrqc, vmdctl, rxcsum; 2373 uint32_t ring_per_group; 2374 int shift_group0, shift_group1; 2375 uint32_t random; 2376 union e1000_reta { 2377 uint32_t dword; 2378 uint8_t bytes[4]; 2379 } reta; 2380 2381 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2382 2383 /* Setup the Redirection Table, it is shared between two groups */ 2384 shift_group0 = 2; 2385 shift_group1 = 6; 2386 for (i = 0; i < (32 * 4); i++) { 2387 reta.bytes[i & 3] = ((i % ring_per_group) << shift_group0) | 2388 ((ring_per_group + (i % ring_per_group)) << shift_group1); 2389 if ((i & 3) == 3) { 2390 E1000_WRITE_REG(hw, 2391 (E1000_RETA(0) + (i & ~3)), reta.dword); 2392 } 2393 } 2394 2395 /* Fill out hash function seeds */ 2396 for (i = 0; i < 10; i++) { 2397 (void) random_get_pseudo_bytes((uint8_t *)&random, 2398 sizeof (uint32_t)); 2399 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 2400 } 2401 2402 /* 2403 * Setup the Multiple Receive Queue Control register, 2404 * enable VMDq based on packet destination MAC address and RSS. 2405 */ 2406 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_RSS_GROUP; 2407 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 2408 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2409 E1000_MRQC_RSS_FIELD_IPV6 | 2410 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2411 E1000_MRQC_RSS_FIELD_IPV4_UDP | 2412 E1000_MRQC_RSS_FIELD_IPV6_UDP | 2413 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 2414 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 2415 2416 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2417 2418 2419 /* Define the default group and default queues */ 2420 vmdctl = E1000_VMDQ_MAC_GROUP_DEFAULT_QUEUE; 2421 E1000_WRITE_REG(hw, E1000_VT_CTL, vmdctl); 2422 2423 /* 2424 * Disable Packet Checksum to enable RSS for multiple receive queues. 2425 * 2426 * The Packet Checksum is not ethernet CRC. It is another kind of 2427 * checksum offloading provided by the 82575 chipset besides the IP 2428 * header checksum offloading and the TCP/UDP checksum offloading. 2429 * The Packet Checksum is by default computed over the entire packet 2430 * from the first byte of the DA through the last byte of the CRC, 2431 * including the Ethernet and IP headers. 2432 * 2433 * It is a hardware limitation that Packet Checksum is mutually 2434 * exclusive with RSS. 2435 */ 2436 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2437 rxcsum |= E1000_RXCSUM_PCSD; 2438 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2439 } 2440 2441 /* 2442 * igb_setup_mac_classify - Setup MAC classification feature 2443 */ 2444 static void 2445 igb_setup_mac_classify(igb_t *igb) 2446 { 2447 struct e1000_hw *hw = &igb->hw; 2448 uint32_t mrqc, rxcsum; 2449 2450 /* 2451 * Setup the Multiple Receive Queue Control register, 2452 * enable VMDq based on packet destination MAC address. 2453 */ 2454 mrqc = E1000_MRQC_ENABLE_VMDQ_MAC_GROUP; 2455 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 2456 2457 /* 2458 * Disable Packet Checksum to enable RSS for multiple receive queues. 2459 * 2460 * The Packet Checksum is not ethernet CRC. It is another kind of 2461 * checksum offloading provided by the 82575 chipset besides the IP 2462 * header checksum offloading and the TCP/UDP checksum offloading. 2463 * The Packet Checksum is by default computed over the entire packet 2464 * from the first byte of the DA through the last byte of the CRC, 2465 * including the Ethernet and IP headers. 2466 * 2467 * It is a hardware limitation that Packet Checksum is mutually 2468 * exclusive with RSS. 2469 */ 2470 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 2471 rxcsum |= E1000_RXCSUM_PCSD; 2472 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 2473 2474 } 2475 2476 /* 2477 * igb_init_unicst - Initialize the unicast addresses 2478 */ 2479 static void 2480 igb_init_unicst(igb_t *igb) 2481 { 2482 struct e1000_hw *hw = &igb->hw; 2483 int slot; 2484 2485 /* 2486 * Here we should consider two situations: 2487 * 2488 * 1. Chipset is initialized the first time 2489 * Initialize the multiple unicast addresses, and 2490 * save the default MAC address. 2491 * 2492 * 2. Chipset is reset 2493 * Recover the multiple unicast addresses from the 2494 * software data structure to the RAR registers. 2495 */ 2496 2497 /* 2498 * Clear the default MAC address in the RAR0 rgister, 2499 * which is loaded from EEPROM when system boot or chipreset, 2500 * this will cause the conficts with add_mac/rem_mac entry 2501 * points when VMDq is enabled. For this reason, the RAR0 2502 * must be cleared for both cases mentioned above. 2503 */ 2504 e1000_rar_clear(hw, 0); 2505 2506 if (!igb->unicst_init) { 2507 2508 /* Initialize the multiple unicast addresses */ 2509 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2510 igb->unicst_avail = igb->unicst_total; 2511 2512 for (slot = 0; slot < igb->unicst_total; slot++) 2513 igb->unicst_addr[slot].mac.set = 0; 2514 2515 igb->unicst_init = B_TRUE; 2516 } else { 2517 /* Re-configure the RAR registers */ 2518 for (slot = 0; slot < igb->unicst_total; slot++) { 2519 e1000_rar_set_vmdq(hw, igb->unicst_addr[slot].mac.addr, 2520 slot, igb->vmdq_mode, 2521 igb->unicst_addr[slot].mac.group_index); 2522 } 2523 } 2524 } 2525 2526 /* 2527 * igb_unicst_find - Find the slot for the specified unicast address 2528 */ 2529 int 2530 igb_unicst_find(igb_t *igb, const uint8_t *mac_addr) 2531 { 2532 int slot; 2533 2534 ASSERT(mutex_owned(&igb->gen_lock)); 2535 2536 for (slot = 0; slot < igb->unicst_total; slot++) { 2537 if (bcmp(igb->unicst_addr[slot].mac.addr, 2538 mac_addr, ETHERADDRL) == 0) 2539 return (slot); 2540 } 2541 2542 return (-1); 2543 } 2544 2545 /* 2546 * igb_unicst_set - Set the unicast address to the specified slot 2547 */ 2548 int 2549 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 2550 int slot) 2551 { 2552 struct e1000_hw *hw = &igb->hw; 2553 2554 ASSERT(mutex_owned(&igb->gen_lock)); 2555 2556 /* 2557 * Save the unicast address in the software data structure 2558 */ 2559 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 2560 2561 /* 2562 * Set the unicast address to the RAR register 2563 */ 2564 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2565 2566 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2567 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2568 return (EIO); 2569 } 2570 2571 return (0); 2572 } 2573 2574 /* 2575 * igb_multicst_add - Add a multicst address 2576 */ 2577 int 2578 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 2579 { 2580 struct ether_addr *new_table; 2581 size_t new_len; 2582 size_t old_len; 2583 2584 ASSERT(mutex_owned(&igb->gen_lock)); 2585 2586 if ((multiaddr[0] & 01) == 0) { 2587 igb_error(igb, "Illegal multicast address"); 2588 return (EINVAL); 2589 } 2590 2591 if (igb->mcast_count >= igb->mcast_max_num) { 2592 igb_error(igb, "Adapter requested more than %d mcast addresses", 2593 igb->mcast_max_num); 2594 return (ENOENT); 2595 } 2596 2597 if (igb->mcast_count == igb->mcast_alloc_count) { 2598 old_len = igb->mcast_alloc_count * 2599 sizeof (struct ether_addr); 2600 new_len = (igb->mcast_alloc_count + MCAST_ALLOC_COUNT) * 2601 sizeof (struct ether_addr); 2602 2603 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2604 if (new_table == NULL) { 2605 igb_error(igb, 2606 "Not enough memory to alloc mcast table"); 2607 return (ENOMEM); 2608 } 2609 2610 if (igb->mcast_table != NULL) { 2611 bcopy(igb->mcast_table, new_table, old_len); 2612 kmem_free(igb->mcast_table, old_len); 2613 } 2614 igb->mcast_alloc_count += MCAST_ALLOC_COUNT; 2615 igb->mcast_table = new_table; 2616 } 2617 2618 bcopy(multiaddr, 2619 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2620 igb->mcast_count++; 2621 2622 /* 2623 * Update the multicast table in the hardware 2624 */ 2625 igb_setup_multicst(igb); 2626 2627 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2628 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2629 return (EIO); 2630 } 2631 2632 return (0); 2633 } 2634 2635 /* 2636 * igb_multicst_remove - Remove a multicst address 2637 */ 2638 int 2639 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2640 { 2641 struct ether_addr *new_table; 2642 size_t new_len; 2643 size_t old_len; 2644 int i; 2645 2646 ASSERT(mutex_owned(&igb->gen_lock)); 2647 2648 for (i = 0; i < igb->mcast_count; i++) { 2649 if (bcmp(multiaddr, &igb->mcast_table[i], 2650 ETHERADDRL) == 0) { 2651 for (i++; i < igb->mcast_count; i++) { 2652 igb->mcast_table[i - 1] = 2653 igb->mcast_table[i]; 2654 } 2655 igb->mcast_count--; 2656 break; 2657 } 2658 } 2659 2660 if ((igb->mcast_alloc_count - igb->mcast_count) > 2661 MCAST_ALLOC_COUNT) { 2662 old_len = igb->mcast_alloc_count * 2663 sizeof (struct ether_addr); 2664 new_len = (igb->mcast_alloc_count - MCAST_ALLOC_COUNT) * 2665 sizeof (struct ether_addr); 2666 2667 new_table = kmem_alloc(new_len, KM_NOSLEEP); 2668 if (new_table != NULL) { 2669 bcopy(igb->mcast_table, new_table, new_len); 2670 kmem_free(igb->mcast_table, old_len); 2671 igb->mcast_alloc_count -= MCAST_ALLOC_COUNT; 2672 igb->mcast_table = new_table; 2673 } 2674 } 2675 2676 /* 2677 * Update the multicast table in the hardware 2678 */ 2679 igb_setup_multicst(igb); 2680 2681 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 2682 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 2683 return (EIO); 2684 } 2685 2686 return (0); 2687 } 2688 2689 static void 2690 igb_release_multicast(igb_t *igb) 2691 { 2692 if (igb->mcast_table != NULL) { 2693 kmem_free(igb->mcast_table, 2694 igb->mcast_alloc_count * sizeof (struct ether_addr)); 2695 igb->mcast_table = NULL; 2696 } 2697 } 2698 2699 /* 2700 * igb_setup_multicast - setup multicast data structures 2701 * 2702 * This routine initializes all of the multicast related structures 2703 * and save them in the hardware registers. 2704 */ 2705 static void 2706 igb_setup_multicst(igb_t *igb) 2707 { 2708 uint8_t *mc_addr_list; 2709 uint32_t mc_addr_count; 2710 struct e1000_hw *hw = &igb->hw; 2711 2712 ASSERT(mutex_owned(&igb->gen_lock)); 2713 ASSERT(igb->mcast_count <= igb->mcast_max_num); 2714 2715 mc_addr_list = (uint8_t *)igb->mcast_table; 2716 mc_addr_count = igb->mcast_count; 2717 2718 /* 2719 * Update the multicase addresses to the MTA registers 2720 */ 2721 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count); 2722 } 2723 2724 /* 2725 * igb_get_conf - Get driver configurations set in driver.conf 2726 * 2727 * This routine gets user-configured values out of the configuration 2728 * file igb.conf. 2729 * 2730 * For each configurable value, there is a minimum, a maximum, and a 2731 * default. 2732 * If user does not configure a value, use the default. 2733 * If user configures below the minimum, use the minumum. 2734 * If user configures above the maximum, use the maxumum. 2735 */ 2736 static void 2737 igb_get_conf(igb_t *igb) 2738 { 2739 struct e1000_hw *hw = &igb->hw; 2740 uint32_t default_mtu; 2741 uint32_t flow_control; 2742 uint32_t ring_per_group; 2743 int i; 2744 2745 /* 2746 * igb driver supports the following user configurations: 2747 * 2748 * Link configurations: 2749 * adv_autoneg_cap 2750 * adv_1000fdx_cap 2751 * adv_100fdx_cap 2752 * adv_100hdx_cap 2753 * adv_10fdx_cap 2754 * adv_10hdx_cap 2755 * Note: 1000hdx is not supported. 2756 * 2757 * Jumbo frame configuration: 2758 * default_mtu 2759 * 2760 * Ethernet flow control configuration: 2761 * flow_control 2762 * 2763 * Multiple rings configurations: 2764 * tx_queue_number 2765 * tx_ring_size 2766 * rx_queue_number 2767 * rx_ring_size 2768 * 2769 * Call igb_get_prop() to get the value for a specific 2770 * configuration parameter. 2771 */ 2772 2773 /* 2774 * Link configurations 2775 */ 2776 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2777 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2778 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2779 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2780 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2781 PROP_ADV_100FDX_CAP, 0, 1, 1); 2782 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2783 PROP_ADV_100HDX_CAP, 0, 1, 1); 2784 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2785 PROP_ADV_10FDX_CAP, 0, 1, 1); 2786 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2787 PROP_ADV_10HDX_CAP, 0, 1, 1); 2788 2789 /* 2790 * Jumbo frame configurations 2791 */ 2792 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2793 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2794 2795 igb->max_frame_size = default_mtu + 2796 sizeof (struct ether_vlan_header) + ETHERFCSL; 2797 2798 /* 2799 * Ethernet flow control configuration 2800 */ 2801 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2802 e1000_fc_none, 4, e1000_fc_full); 2803 if (flow_control == 4) 2804 flow_control = e1000_fc_default; 2805 2806 hw->fc.requested_mode = flow_control; 2807 2808 /* 2809 * Multiple rings configurations 2810 */ 2811 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2812 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2813 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2814 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2815 2816 igb->mr_enable = igb_get_prop(igb, PROP_MR_ENABLE, 0, 1, 0); 2817 igb->num_rx_groups = igb_get_prop(igb, PROP_RX_GROUP_NUM, 2818 MIN_RX_GROUP_NUM, MAX_RX_GROUP_NUM, DEFAULT_RX_GROUP_NUM); 2819 /* 2820 * Currently we do not support VMDq for 82576 and 82580. 2821 * If it is e1000_82576, set num_rx_groups to 1. 2822 */ 2823 if (hw->mac.type >= e1000_82576) 2824 igb->num_rx_groups = 1; 2825 2826 if (igb->mr_enable) { 2827 igb->num_tx_rings = igb->capab->def_tx_que_num; 2828 igb->num_rx_rings = igb->capab->def_rx_que_num; 2829 } else { 2830 igb->num_tx_rings = 1; 2831 igb->num_rx_rings = 1; 2832 2833 if (igb->num_rx_groups > 1) { 2834 igb_error(igb, 2835 "Invalid rx groups number. Please enable multiple " 2836 "rings first"); 2837 igb->num_rx_groups = 1; 2838 } 2839 } 2840 2841 /* 2842 * Check the divisibility between rx rings and rx groups. 2843 */ 2844 for (i = igb->num_rx_groups; i > 0; i--) { 2845 if ((igb->num_rx_rings % i) == 0) 2846 break; 2847 } 2848 if (i != igb->num_rx_groups) { 2849 igb_error(igb, 2850 "Invalid rx groups number. Downgrade the rx group " 2851 "number to %d.", i); 2852 igb->num_rx_groups = i; 2853 } 2854 2855 /* 2856 * Get the ring number per group. 2857 */ 2858 ring_per_group = igb->num_rx_rings / igb->num_rx_groups; 2859 2860 if (igb->num_rx_groups == 1) { 2861 /* 2862 * One rx ring group, the rx ring number is num_rx_rings. 2863 */ 2864 igb->vmdq_mode = E1000_VMDQ_OFF; 2865 } else if (ring_per_group == 1) { 2866 /* 2867 * Multiple rx groups, each group has one rx ring. 2868 */ 2869 igb->vmdq_mode = E1000_VMDQ_MAC; 2870 } else { 2871 /* 2872 * Multiple groups and multiple rings. 2873 */ 2874 igb->vmdq_mode = E1000_VMDQ_MAC_RSS; 2875 } 2876 2877 /* 2878 * Tunable used to force an interrupt type. The only use is 2879 * for testing of the lesser interrupt types. 2880 * 0 = don't force interrupt type 2881 * 1 = force interrupt type MSIX 2882 * 2 = force interrupt type MSI 2883 * 3 = force interrupt type Legacy 2884 */ 2885 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2886 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2887 2888 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2889 0, 1, 1); 2890 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2891 0, 1, 1); 2892 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2893 0, 1, 1); 2894 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2895 0, 1, 1); 2896 2897 /* 2898 * igb LSO needs the tx h/w checksum support. 2899 * Here LSO will be disabled if tx h/w checksum has been disabled. 2900 */ 2901 if (igb->tx_hcksum_enable == B_FALSE) 2902 igb->lso_enable = B_FALSE; 2903 2904 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2905 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2906 DEFAULT_TX_COPY_THRESHOLD); 2907 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2908 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2909 DEFAULT_TX_RECYCLE_THRESHOLD); 2910 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2911 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2912 DEFAULT_TX_OVERLOAD_THRESHOLD); 2913 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2914 MIN_TX_RESCHED_THRESHOLD, 2915 MIN(igb->tx_ring_size, MAX_TX_RESCHED_THRESHOLD), 2916 igb->tx_ring_size > DEFAULT_TX_RESCHED_THRESHOLD ? 2917 DEFAULT_TX_RESCHED_THRESHOLD : DEFAULT_TX_RESCHED_THRESHOLD_LOW); 2918 2919 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2920 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2921 DEFAULT_RX_COPY_THRESHOLD); 2922 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2923 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2924 DEFAULT_RX_LIMIT_PER_INTR); 2925 2926 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2927 igb->capab->min_intr_throttle, 2928 igb->capab->max_intr_throttle, 2929 igb->capab->def_intr_throttle); 2930 2931 /* 2932 * Max number of multicast addresses 2933 */ 2934 igb->mcast_max_num = 2935 igb_get_prop(igb, PROP_MCAST_MAX_NUM, 2936 MIN_MCAST_NUM, MAX_MCAST_NUM, DEFAULT_MCAST_NUM); 2937 } 2938 2939 /* 2940 * igb_get_prop - Get a property value out of the configuration file igb.conf 2941 * 2942 * Caller provides the name of the property, a default value, a minimum 2943 * value, and a maximum value. 2944 * 2945 * Return configured value of the property, with default, minimum and 2946 * maximum properly applied. 2947 */ 2948 static int 2949 igb_get_prop(igb_t *igb, 2950 char *propname, /* name of the property */ 2951 int minval, /* minimum acceptable value */ 2952 int maxval, /* maximim acceptable value */ 2953 int defval) /* default value */ 2954 { 2955 int value; 2956 2957 /* 2958 * Call ddi_prop_get_int() to read the conf settings 2959 */ 2960 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2961 DDI_PROP_DONTPASS, propname, defval); 2962 2963 if (value > maxval) 2964 value = maxval; 2965 2966 if (value < minval) 2967 value = minval; 2968 2969 return (value); 2970 } 2971 2972 /* 2973 * igb_setup_link - Using the link properties to setup the link 2974 */ 2975 int 2976 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2977 { 2978 struct e1000_mac_info *mac; 2979 struct e1000_phy_info *phy; 2980 boolean_t invalid; 2981 2982 mac = &igb->hw.mac; 2983 phy = &igb->hw.phy; 2984 invalid = B_FALSE; 2985 2986 if (igb->param_adv_autoneg_cap == 1) { 2987 mac->autoneg = B_TRUE; 2988 phy->autoneg_advertised = 0; 2989 2990 /* 2991 * 1000hdx is not supported for autonegotiation 2992 */ 2993 if (igb->param_adv_1000fdx_cap == 1) 2994 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2995 2996 if (igb->param_adv_100fdx_cap == 1) 2997 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2998 2999 if (igb->param_adv_100hdx_cap == 1) 3000 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3001 3002 if (igb->param_adv_10fdx_cap == 1) 3003 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3004 3005 if (igb->param_adv_10hdx_cap == 1) 3006 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3007 3008 if (phy->autoneg_advertised == 0) 3009 invalid = B_TRUE; 3010 } else { 3011 mac->autoneg = B_FALSE; 3012 3013 /* 3014 * 1000fdx and 1000hdx are not supported for forced link 3015 */ 3016 if (igb->param_adv_100fdx_cap == 1) 3017 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3018 else if (igb->param_adv_100hdx_cap == 1) 3019 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3020 else if (igb->param_adv_10fdx_cap == 1) 3021 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3022 else if (igb->param_adv_10hdx_cap == 1) 3023 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3024 else 3025 invalid = B_TRUE; 3026 } 3027 3028 if (invalid) { 3029 igb_notice(igb, "Invalid link settings. Setup link to " 3030 "autonegotiation with full link capabilities."); 3031 mac->autoneg = B_TRUE; 3032 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3033 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3034 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3035 } 3036 3037 if (setup_hw) { 3038 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 3039 return (IGB_FAILURE); 3040 } 3041 3042 return (IGB_SUCCESS); 3043 } 3044 3045 3046 /* 3047 * igb_is_link_up - Check if the link is up 3048 */ 3049 static boolean_t 3050 igb_is_link_up(igb_t *igb) 3051 { 3052 struct e1000_hw *hw = &igb->hw; 3053 boolean_t link_up = B_FALSE; 3054 3055 ASSERT(mutex_owned(&igb->gen_lock)); 3056 3057 /* 3058 * get_link_status is set in the interrupt handler on link-status-change 3059 * or rx sequence error interrupt. get_link_status will stay 3060 * false until the e1000_check_for_link establishes link only 3061 * for copper adapters. 3062 */ 3063 switch (hw->phy.media_type) { 3064 case e1000_media_type_copper: 3065 if (hw->mac.get_link_status) { 3066 (void) e1000_check_for_link(hw); 3067 link_up = !hw->mac.get_link_status; 3068 } else { 3069 link_up = B_TRUE; 3070 } 3071 break; 3072 case e1000_media_type_fiber: 3073 (void) e1000_check_for_link(hw); 3074 link_up = (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU); 3075 break; 3076 case e1000_media_type_internal_serdes: 3077 (void) e1000_check_for_link(hw); 3078 link_up = hw->mac.serdes_has_link; 3079 break; 3080 } 3081 3082 return (link_up); 3083 } 3084 3085 /* 3086 * igb_link_check - Link status processing 3087 */ 3088 static boolean_t 3089 igb_link_check(igb_t *igb) 3090 { 3091 struct e1000_hw *hw = &igb->hw; 3092 uint16_t speed = 0, duplex = 0; 3093 boolean_t link_changed = B_FALSE; 3094 3095 ASSERT(mutex_owned(&igb->gen_lock)); 3096 3097 if (igb_is_link_up(igb)) { 3098 /* 3099 * The Link is up, check whether it was marked as down earlier 3100 */ 3101 if (igb->link_state != LINK_STATE_UP) { 3102 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3103 igb->link_speed = speed; 3104 igb->link_duplex = duplex; 3105 igb->link_state = LINK_STATE_UP; 3106 link_changed = B_TRUE; 3107 if (!igb->link_complete) 3108 igb_stop_link_timer(igb); 3109 } 3110 } else if (igb->link_complete) { 3111 if (igb->link_state != LINK_STATE_DOWN) { 3112 igb->link_speed = 0; 3113 igb->link_duplex = 0; 3114 igb->link_state = LINK_STATE_DOWN; 3115 link_changed = B_TRUE; 3116 } 3117 } 3118 3119 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3120 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3121 return (B_FALSE); 3122 } 3123 3124 return (link_changed); 3125 } 3126 3127 /* 3128 * igb_local_timer - driver watchdog function 3129 * 3130 * This function will handle the hardware stall check, link status 3131 * check and other routines. 3132 */ 3133 static void 3134 igb_local_timer(void *arg) 3135 { 3136 igb_t *igb = (igb_t *)arg; 3137 boolean_t link_changed = B_FALSE; 3138 3139 if (igb->igb_state & IGB_ERROR) { 3140 igb->reset_count++; 3141 if (igb_reset(igb) == IGB_SUCCESS) 3142 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED); 3143 3144 igb_restart_watchdog_timer(igb); 3145 return; 3146 } 3147 3148 if (igb_stall_check(igb) || (igb->igb_state & IGB_STALL)) { 3149 igb_fm_ereport(igb, DDI_FM_DEVICE_STALL); 3150 ddi_fm_service_impact(igb->dip, DDI_SERVICE_LOST); 3151 igb->reset_count++; 3152 if (igb_reset(igb) == IGB_SUCCESS) 3153 ddi_fm_service_impact(igb->dip, DDI_SERVICE_RESTORED); 3154 3155 igb_restart_watchdog_timer(igb); 3156 return; 3157 } 3158 3159 mutex_enter(&igb->gen_lock); 3160 if (!(igb->igb_state & IGB_SUSPENDED) && (igb->igb_state & IGB_STARTED)) 3161 link_changed = igb_link_check(igb); 3162 mutex_exit(&igb->gen_lock); 3163 3164 if (link_changed) 3165 mac_link_update(igb->mac_hdl, igb->link_state); 3166 3167 igb_restart_watchdog_timer(igb); 3168 } 3169 3170 /* 3171 * igb_link_timer - link setup timer function 3172 * 3173 * It is called when the timer for link setup is expired, which indicates 3174 * the completion of the link setup. The link state will not be updated 3175 * until the link setup is completed. And the link state will not be sent 3176 * to the upper layer through mac_link_update() in this function. It will 3177 * be updated in the local timer routine or the interrupts service routine 3178 * after the interface is started (plumbed). 3179 */ 3180 static void 3181 igb_link_timer(void *arg) 3182 { 3183 igb_t *igb = (igb_t *)arg; 3184 3185 mutex_enter(&igb->link_lock); 3186 igb->link_complete = B_TRUE; 3187 igb->link_tid = 0; 3188 mutex_exit(&igb->link_lock); 3189 } 3190 /* 3191 * igb_stall_check - check for transmit stall 3192 * 3193 * This function checks if the adapter is stalled (in transmit). 3194 * 3195 * It is called each time the watchdog timeout is invoked. 3196 * If the transmit descriptor reclaim continuously fails, 3197 * the watchdog value will increment by 1. If the watchdog 3198 * value exceeds the threshold, the igb is assumed to 3199 * have stalled and need to be reset. 3200 */ 3201 static boolean_t 3202 igb_stall_check(igb_t *igb) 3203 { 3204 igb_tx_ring_t *tx_ring; 3205 struct e1000_hw *hw = &igb->hw; 3206 boolean_t result; 3207 int i; 3208 3209 if (igb->link_state != LINK_STATE_UP) 3210 return (B_FALSE); 3211 3212 /* 3213 * If any tx ring is stalled, we'll reset the chipset 3214 */ 3215 result = B_FALSE; 3216 for (i = 0; i < igb->num_tx_rings; i++) { 3217 tx_ring = &igb->tx_rings[i]; 3218 3219 if (tx_ring->recycle_fail > 0) 3220 tx_ring->stall_watchdog++; 3221 else 3222 tx_ring->stall_watchdog = 0; 3223 3224 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 3225 result = B_TRUE; 3226 if (hw->mac.type == e1000_82580) { 3227 hw->dev_spec._82575.global_device_reset 3228 = B_TRUE; 3229 } 3230 break; 3231 } 3232 } 3233 3234 if (result) { 3235 tx_ring->stall_watchdog = 0; 3236 tx_ring->recycle_fail = 0; 3237 } 3238 3239 return (result); 3240 } 3241 3242 3243 /* 3244 * is_valid_mac_addr - Check if the mac address is valid 3245 */ 3246 static boolean_t 3247 is_valid_mac_addr(uint8_t *mac_addr) 3248 { 3249 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 3250 const uint8_t addr_test2[6] = 3251 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3252 3253 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3254 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3255 return (B_FALSE); 3256 3257 return (B_TRUE); 3258 } 3259 3260 static boolean_t 3261 igb_find_mac_address(igb_t *igb) 3262 { 3263 struct e1000_hw *hw = &igb->hw; 3264 #ifdef __sparc 3265 uchar_t *bytes; 3266 struct ether_addr sysaddr; 3267 uint_t nelts; 3268 int err; 3269 boolean_t found = B_FALSE; 3270 3271 /* 3272 * The "vendor's factory-set address" may already have 3273 * been extracted from the chip, but if the property 3274 * "local-mac-address" is set we use that instead. 3275 * 3276 * We check whether it looks like an array of 6 3277 * bytes (which it should, if OBP set it). If we can't 3278 * make sense of it this way, we'll ignore it. 3279 */ 3280 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3281 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3282 if (err == DDI_PROP_SUCCESS) { 3283 if (nelts == ETHERADDRL) { 3284 while (nelts--) 3285 hw->mac.addr[nelts] = bytes[nelts]; 3286 found = B_TRUE; 3287 } 3288 ddi_prop_free(bytes); 3289 } 3290 3291 /* 3292 * Look up the OBP property "local-mac-address?". If the user has set 3293 * 'local-mac-address? = false', use "the system address" instead. 3294 */ 3295 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 3296 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3297 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3298 if (localetheraddr(NULL, &sysaddr) != 0) { 3299 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 3300 found = B_TRUE; 3301 } 3302 } 3303 ddi_prop_free(bytes); 3304 } 3305 3306 /* 3307 * Finally(!), if there's a valid "mac-address" property (created 3308 * if we netbooted from this interface), we must use this instead 3309 * of any of the above to ensure that the NFS/install server doesn't 3310 * get confused by the address changing as Solaris takes over! 3311 */ 3312 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 3313 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3314 if (err == DDI_PROP_SUCCESS) { 3315 if (nelts == ETHERADDRL) { 3316 while (nelts--) 3317 hw->mac.addr[nelts] = bytes[nelts]; 3318 found = B_TRUE; 3319 } 3320 ddi_prop_free(bytes); 3321 } 3322 3323 if (found) { 3324 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 3325 return (B_TRUE); 3326 } 3327 #endif 3328 3329 /* 3330 * Read the device MAC address from the EEPROM 3331 */ 3332 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 3333 return (B_FALSE); 3334 3335 return (B_TRUE); 3336 } 3337 3338 #pragma inline(igb_arm_watchdog_timer) 3339 3340 static void 3341 igb_arm_watchdog_timer(igb_t *igb) 3342 { 3343 /* 3344 * Fire a watchdog timer 3345 */ 3346 igb->watchdog_tid = 3347 timeout(igb_local_timer, 3348 (void *)igb, 1 * drv_usectohz(1000000)); 3349 3350 } 3351 3352 /* 3353 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 3354 */ 3355 void 3356 igb_enable_watchdog_timer(igb_t *igb) 3357 { 3358 mutex_enter(&igb->watchdog_lock); 3359 3360 if (!igb->watchdog_enable) { 3361 igb->watchdog_enable = B_TRUE; 3362 igb->watchdog_start = B_TRUE; 3363 igb_arm_watchdog_timer(igb); 3364 } 3365 3366 mutex_exit(&igb->watchdog_lock); 3367 3368 } 3369 3370 /* 3371 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 3372 */ 3373 void 3374 igb_disable_watchdog_timer(igb_t *igb) 3375 { 3376 timeout_id_t tid; 3377 3378 mutex_enter(&igb->watchdog_lock); 3379 3380 igb->watchdog_enable = B_FALSE; 3381 igb->watchdog_start = B_FALSE; 3382 tid = igb->watchdog_tid; 3383 igb->watchdog_tid = 0; 3384 3385 mutex_exit(&igb->watchdog_lock); 3386 3387 if (tid != 0) 3388 (void) untimeout(tid); 3389 3390 } 3391 3392 /* 3393 * igb_start_watchdog_timer - Start the driver watchdog timer 3394 */ 3395 static void 3396 igb_start_watchdog_timer(igb_t *igb) 3397 { 3398 mutex_enter(&igb->watchdog_lock); 3399 3400 if (igb->watchdog_enable) { 3401 if (!igb->watchdog_start) { 3402 igb->watchdog_start = B_TRUE; 3403 igb_arm_watchdog_timer(igb); 3404 } 3405 } 3406 3407 mutex_exit(&igb->watchdog_lock); 3408 } 3409 3410 /* 3411 * igb_restart_watchdog_timer - Restart the driver watchdog timer 3412 */ 3413 static void 3414 igb_restart_watchdog_timer(igb_t *igb) 3415 { 3416 mutex_enter(&igb->watchdog_lock); 3417 3418 if (igb->watchdog_start) 3419 igb_arm_watchdog_timer(igb); 3420 3421 mutex_exit(&igb->watchdog_lock); 3422 } 3423 3424 /* 3425 * igb_stop_watchdog_timer - Stop the driver watchdog timer 3426 */ 3427 static void 3428 igb_stop_watchdog_timer(igb_t *igb) 3429 { 3430 timeout_id_t tid; 3431 3432 mutex_enter(&igb->watchdog_lock); 3433 3434 igb->watchdog_start = B_FALSE; 3435 tid = igb->watchdog_tid; 3436 igb->watchdog_tid = 0; 3437 3438 mutex_exit(&igb->watchdog_lock); 3439 3440 if (tid != 0) 3441 (void) untimeout(tid); 3442 } 3443 3444 /* 3445 * igb_start_link_timer - Start the link setup timer 3446 */ 3447 static void 3448 igb_start_link_timer(struct igb *igb) 3449 { 3450 struct e1000_hw *hw = &igb->hw; 3451 clock_t link_timeout; 3452 3453 if (hw->mac.autoneg) 3454 link_timeout = PHY_AUTO_NEG_LIMIT * 3455 drv_usectohz(100000); 3456 else 3457 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 3458 3459 mutex_enter(&igb->link_lock); 3460 if (hw->phy.autoneg_wait_to_complete) { 3461 igb->link_complete = B_TRUE; 3462 } else { 3463 igb->link_complete = B_FALSE; 3464 igb->link_tid = timeout(igb_link_timer, (void *)igb, 3465 link_timeout); 3466 } 3467 mutex_exit(&igb->link_lock); 3468 } 3469 3470 /* 3471 * igb_stop_link_timer - Stop the link setup timer 3472 */ 3473 static void 3474 igb_stop_link_timer(struct igb *igb) 3475 { 3476 timeout_id_t tid; 3477 3478 mutex_enter(&igb->link_lock); 3479 igb->link_complete = B_TRUE; 3480 tid = igb->link_tid; 3481 igb->link_tid = 0; 3482 mutex_exit(&igb->link_lock); 3483 3484 if (tid != 0) 3485 (void) untimeout(tid); 3486 } 3487 3488 /* 3489 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 3490 */ 3491 static void 3492 igb_disable_adapter_interrupts(igb_t *igb) 3493 { 3494 struct e1000_hw *hw = &igb->hw; 3495 3496 /* 3497 * Set the IMC register to mask all the interrupts, 3498 * including the tx interrupts. 3499 */ 3500 E1000_WRITE_REG(hw, E1000_IMC, ~0); 3501 E1000_WRITE_REG(hw, E1000_IAM, 0); 3502 3503 /* 3504 * Additional disabling for MSI-X 3505 */ 3506 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3507 E1000_WRITE_REG(hw, E1000_EIMC, ~0); 3508 E1000_WRITE_REG(hw, E1000_EIAC, 0); 3509 E1000_WRITE_REG(hw, E1000_EIAM, 0); 3510 } 3511 3512 E1000_WRITE_FLUSH(hw); 3513 } 3514 3515 /* 3516 * igb_enable_adapter_interrupts_82580 - Enable NIC interrupts for 82580 3517 */ 3518 static void 3519 igb_enable_adapter_interrupts_82580(igb_t *igb) 3520 { 3521 struct e1000_hw *hw = &igb->hw; 3522 3523 /* Clear any pending interrupts */ 3524 (void) E1000_READ_REG(hw, E1000_ICR); 3525 igb->ims_mask |= E1000_IMS_DRSTA; 3526 3527 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3528 3529 /* Interrupt enabling for MSI-X */ 3530 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3531 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3532 igb->ims_mask = (E1000_IMS_LSC | E1000_IMS_DRSTA); 3533 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask); 3534 } else { /* Interrupt enabling for MSI and legacy */ 3535 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3536 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3537 igb->ims_mask |= E1000_IMS_DRSTA; 3538 E1000_WRITE_REG(hw, E1000_IMS, igb->ims_mask); 3539 } 3540 3541 /* Disable auto-mask for ICR interrupt bits */ 3542 E1000_WRITE_REG(hw, E1000_IAM, 0); 3543 3544 E1000_WRITE_FLUSH(hw); 3545 } 3546 3547 /* 3548 * igb_enable_adapter_interrupts_82576 - Enable NIC interrupts for 82576 3549 */ 3550 static void 3551 igb_enable_adapter_interrupts_82576(igb_t *igb) 3552 { 3553 struct e1000_hw *hw = &igb->hw; 3554 3555 /* Clear any pending interrupts */ 3556 (void) E1000_READ_REG(hw, E1000_ICR); 3557 3558 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3559 3560 /* Interrupt enabling for MSI-X */ 3561 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3562 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3563 igb->ims_mask = E1000_IMS_LSC; 3564 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3565 } else { 3566 /* Interrupt enabling for MSI and legacy */ 3567 E1000_WRITE_REG(hw, E1000_IVAR0, E1000_IVAR_VALID); 3568 igb->ims_mask = IMS_ENABLE_MASK | E1000_IMS_TXQE; 3569 E1000_WRITE_REG(hw, E1000_IMS, 3570 (IMS_ENABLE_MASK | E1000_IMS_TXQE)); 3571 } 3572 3573 /* Disable auto-mask for ICR interrupt bits */ 3574 E1000_WRITE_REG(hw, E1000_IAM, 0); 3575 3576 E1000_WRITE_FLUSH(hw); 3577 } 3578 3579 /* 3580 * igb_enable_adapter_interrupts_82575 - Enable NIC interrupts for 82575 3581 */ 3582 static void 3583 igb_enable_adapter_interrupts_82575(igb_t *igb) 3584 { 3585 struct e1000_hw *hw = &igb->hw; 3586 uint32_t reg; 3587 3588 /* Clear any pending interrupts */ 3589 (void) E1000_READ_REG(hw, E1000_ICR); 3590 3591 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 3592 /* Interrupt enabling for MSI-X */ 3593 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 3594 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 3595 igb->ims_mask = E1000_IMS_LSC; 3596 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 3597 3598 /* Enable MSI-X PBA support */ 3599 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 3600 reg |= E1000_CTRL_EXT_PBA_CLR; 3601 3602 /* Non-selective interrupt clear-on-read */ 3603 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 3604 3605 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 3606 } else { 3607 /* Interrupt enabling for MSI and legacy */ 3608 igb->ims_mask = IMS_ENABLE_MASK; 3609 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 3610 } 3611 3612 E1000_WRITE_FLUSH(hw); 3613 } 3614 3615 /* 3616 * Loopback Support 3617 */ 3618 static lb_property_t lb_normal = 3619 { normal, "normal", IGB_LB_NONE }; 3620 static lb_property_t lb_external = 3621 { external, "External", IGB_LB_EXTERNAL }; 3622 static lb_property_t lb_phy = 3623 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 3624 static lb_property_t lb_serdes = 3625 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 3626 3627 enum ioc_reply 3628 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 3629 { 3630 lb_info_sz_t *lbsp; 3631 lb_property_t *lbpp; 3632 struct e1000_hw *hw; 3633 uint32_t *lbmp; 3634 uint32_t size; 3635 uint32_t value; 3636 3637 hw = &igb->hw; 3638 3639 if (mp->b_cont == NULL) 3640 return (IOC_INVAL); 3641 3642 switch (iocp->ioc_cmd) { 3643 default: 3644 return (IOC_INVAL); 3645 3646 case LB_GET_INFO_SIZE: 3647 size = sizeof (lb_info_sz_t); 3648 if (iocp->ioc_count != size) 3649 return (IOC_INVAL); 3650 3651 value = sizeof (lb_normal); 3652 if (hw->phy.media_type == e1000_media_type_copper) 3653 value += sizeof (lb_phy); 3654 else 3655 value += sizeof (lb_serdes); 3656 value += sizeof (lb_external); 3657 3658 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 3659 *lbsp = value; 3660 break; 3661 3662 case LB_GET_INFO: 3663 value = sizeof (lb_normal); 3664 if (hw->phy.media_type == e1000_media_type_copper) 3665 value += sizeof (lb_phy); 3666 else 3667 value += sizeof (lb_serdes); 3668 value += sizeof (lb_external); 3669 3670 size = value; 3671 if (iocp->ioc_count != size) 3672 return (IOC_INVAL); 3673 3674 value = 0; 3675 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 3676 3677 lbpp[value++] = lb_normal; 3678 if (hw->phy.media_type == e1000_media_type_copper) 3679 lbpp[value++] = lb_phy; 3680 else 3681 lbpp[value++] = lb_serdes; 3682 lbpp[value++] = lb_external; 3683 break; 3684 3685 case LB_GET_MODE: 3686 size = sizeof (uint32_t); 3687 if (iocp->ioc_count != size) 3688 return (IOC_INVAL); 3689 3690 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3691 *lbmp = igb->loopback_mode; 3692 break; 3693 3694 case LB_SET_MODE: 3695 size = 0; 3696 if (iocp->ioc_count != sizeof (uint32_t)) 3697 return (IOC_INVAL); 3698 3699 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 3700 if (!igb_set_loopback_mode(igb, *lbmp)) 3701 return (IOC_INVAL); 3702 break; 3703 } 3704 3705 iocp->ioc_count = size; 3706 iocp->ioc_error = 0; 3707 3708 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 3709 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 3710 return (IOC_INVAL); 3711 } 3712 3713 return (IOC_REPLY); 3714 } 3715 3716 /* 3717 * igb_set_loopback_mode - Setup loopback based on the loopback mode 3718 */ 3719 static boolean_t 3720 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 3721 { 3722 struct e1000_hw *hw; 3723 int i; 3724 3725 if (mode == igb->loopback_mode) 3726 return (B_TRUE); 3727 3728 hw = &igb->hw; 3729 3730 igb->loopback_mode = mode; 3731 3732 if (mode == IGB_LB_NONE) { 3733 /* Reset the chip */ 3734 hw->phy.autoneg_wait_to_complete = B_TRUE; 3735 (void) igb_reset(igb); 3736 hw->phy.autoneg_wait_to_complete = B_FALSE; 3737 return (B_TRUE); 3738 } 3739 3740 mutex_enter(&igb->gen_lock); 3741 3742 switch (mode) { 3743 default: 3744 mutex_exit(&igb->gen_lock); 3745 return (B_FALSE); 3746 3747 case IGB_LB_EXTERNAL: 3748 igb_set_external_loopback(igb); 3749 break; 3750 3751 case IGB_LB_INTERNAL_PHY: 3752 igb_set_internal_phy_loopback(igb); 3753 break; 3754 3755 case IGB_LB_INTERNAL_SERDES: 3756 igb_set_internal_serdes_loopback(igb); 3757 break; 3758 } 3759 3760 mutex_exit(&igb->gen_lock); 3761 3762 /* 3763 * When external loopback is set, wait up to 1000ms to get the link up. 3764 * According to test, 1000ms can work and it's an experimental value. 3765 */ 3766 if (mode == IGB_LB_EXTERNAL) { 3767 for (i = 0; i <= 10; i++) { 3768 mutex_enter(&igb->gen_lock); 3769 (void) igb_link_check(igb); 3770 mutex_exit(&igb->gen_lock); 3771 3772 if (igb->link_state == LINK_STATE_UP) 3773 break; 3774 3775 msec_delay(100); 3776 } 3777 3778 if (igb->link_state != LINK_STATE_UP) { 3779 /* 3780 * Does not support external loopback. 3781 * Reset driver to loopback none. 3782 */ 3783 igb->loopback_mode = IGB_LB_NONE; 3784 3785 /* Reset the chip */ 3786 hw->phy.autoneg_wait_to_complete = B_TRUE; 3787 (void) igb_reset(igb); 3788 hw->phy.autoneg_wait_to_complete = B_FALSE; 3789 3790 IGB_DEBUGLOG_0(igb, "Set external loopback failed, " 3791 "reset to loopback none."); 3792 3793 return (B_FALSE); 3794 } 3795 } 3796 3797 return (B_TRUE); 3798 } 3799 3800 /* 3801 * igb_set_external_loopback - Set the external loopback mode 3802 */ 3803 static void 3804 igb_set_external_loopback(igb_t *igb) 3805 { 3806 struct e1000_hw *hw; 3807 uint32_t ctrl_ext; 3808 3809 hw = &igb->hw; 3810 3811 /* Set link mode to PHY (00b) in the Extended Control register */ 3812 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3813 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3814 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3815 3816 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 3817 (void) e1000_write_phy_reg(hw, 0x9, 0x1a00); 3818 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 3819 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 3820 } 3821 3822 /* 3823 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 3824 */ 3825 static void 3826 igb_set_internal_phy_loopback(igb_t *igb) 3827 { 3828 struct e1000_hw *hw; 3829 uint32_t ctrl_ext; 3830 uint16_t phy_ctrl; 3831 uint16_t phy_pconf; 3832 3833 hw = &igb->hw; 3834 3835 /* Set link mode to PHY (00b) in the Extended Control register */ 3836 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3837 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 3838 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3839 3840 /* 3841 * Set PHY control register (0x4140): 3842 * Set full duplex mode 3843 * Set loopback bit 3844 * Clear auto-neg enable bit 3845 * Set PHY speed 3846 */ 3847 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 3848 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 3849 3850 /* Set the link disable bit in the Port Configuration register */ 3851 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 3852 phy_pconf |= (uint16_t)1 << 14; 3853 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 3854 } 3855 3856 /* 3857 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 3858 */ 3859 static void 3860 igb_set_internal_serdes_loopback(igb_t *igb) 3861 { 3862 struct e1000_hw *hw; 3863 uint32_t ctrl_ext; 3864 uint32_t ctrl; 3865 uint32_t pcs_lctl; 3866 uint32_t connsw; 3867 3868 hw = &igb->hw; 3869 3870 /* Set link mode to SerDes (11b) in the Extended Control register */ 3871 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3872 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 3873 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3874 3875 /* Configure the SerDes to loopback */ 3876 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 3877 3878 /* Set Device Control register */ 3879 ctrl = E1000_READ_REG(hw, E1000_CTRL); 3880 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 3881 E1000_CTRL_SLU); /* Force link up */ 3882 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 3883 E1000_CTRL_TFCE | /* Disable transmit flow control */ 3884 E1000_CTRL_LRST); /* Clear link reset */ 3885 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 3886 3887 /* Set PCS Link Control register */ 3888 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 3889 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 3890 E1000_PCS_LCTL_FSD | 3891 E1000_PCS_LCTL_FDV_FULL | 3892 E1000_PCS_LCTL_FLV_LINK_UP); 3893 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3894 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3895 3896 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3897 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3898 connsw &= ~E1000_CONNSW_ENRGSRC; 3899 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3900 } 3901 3902 #pragma inline(igb_intr_rx_work) 3903 /* 3904 * igb_intr_rx_work - rx processing of ISR 3905 */ 3906 static void 3907 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3908 { 3909 mblk_t *mp; 3910 3911 mutex_enter(&rx_ring->rx_lock); 3912 mp = igb_rx(rx_ring, IGB_NO_POLL); 3913 mutex_exit(&rx_ring->rx_lock); 3914 3915 if (mp != NULL) 3916 mac_rx_ring(rx_ring->igb->mac_hdl, rx_ring->ring_handle, mp, 3917 rx_ring->ring_gen_num); 3918 } 3919 3920 #pragma inline(igb_intr_tx_work) 3921 /* 3922 * igb_intr_tx_work - tx processing of ISR 3923 */ 3924 static void 3925 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3926 { 3927 igb_t *igb = tx_ring->igb; 3928 3929 /* Recycle the tx descriptors */ 3930 tx_ring->tx_recycle(tx_ring); 3931 3932 /* Schedule the re-transmit */ 3933 if (tx_ring->reschedule && 3934 (tx_ring->tbd_free >= igb->tx_resched_thresh)) { 3935 tx_ring->reschedule = B_FALSE; 3936 mac_tx_ring_update(tx_ring->igb->mac_hdl, tx_ring->ring_handle); 3937 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3938 } 3939 } 3940 3941 #pragma inline(igb_intr_link_work) 3942 /* 3943 * igb_intr_link_work - link-status-change processing of ISR 3944 */ 3945 static void 3946 igb_intr_link_work(igb_t *igb) 3947 { 3948 boolean_t link_changed; 3949 3950 igb_stop_watchdog_timer(igb); 3951 3952 mutex_enter(&igb->gen_lock); 3953 3954 /* 3955 * Because we got a link-status-change interrupt, force 3956 * e1000_check_for_link() to look at phy 3957 */ 3958 igb->hw.mac.get_link_status = B_TRUE; 3959 3960 /* igb_link_check takes care of link status change */ 3961 link_changed = igb_link_check(igb); 3962 3963 /* Get new phy state */ 3964 igb_get_phy_state(igb); 3965 3966 mutex_exit(&igb->gen_lock); 3967 3968 if (link_changed) 3969 mac_link_update(igb->mac_hdl, igb->link_state); 3970 3971 igb_start_watchdog_timer(igb); 3972 } 3973 3974 /* 3975 * igb_intr_legacy - Interrupt handler for legacy interrupts 3976 */ 3977 static uint_t 3978 igb_intr_legacy(void *arg1, void *arg2) 3979 { 3980 igb_t *igb = (igb_t *)arg1; 3981 igb_tx_ring_t *tx_ring; 3982 uint32_t icr; 3983 mblk_t *mp; 3984 boolean_t tx_reschedule; 3985 boolean_t link_changed; 3986 uint_t result; 3987 3988 _NOTE(ARGUNUSED(arg2)); 3989 3990 mutex_enter(&igb->gen_lock); 3991 3992 if (igb->igb_state & IGB_SUSPENDED) { 3993 mutex_exit(&igb->gen_lock); 3994 return (DDI_INTR_UNCLAIMED); 3995 } 3996 3997 mp = NULL; 3998 tx_reschedule = B_FALSE; 3999 link_changed = B_FALSE; 4000 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4001 4002 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4003 mutex_exit(&igb->gen_lock); 4004 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4005 atomic_or_32(&igb->igb_state, IGB_ERROR); 4006 return (DDI_INTR_UNCLAIMED); 4007 } 4008 4009 if (icr & E1000_ICR_INT_ASSERTED) { 4010 /* 4011 * E1000_ICR_INT_ASSERTED bit was set: 4012 * Read(Clear) the ICR, claim this interrupt, 4013 * look for work to do. 4014 */ 4015 ASSERT(igb->num_rx_rings == 1); 4016 ASSERT(igb->num_tx_rings == 1); 4017 4018 /* Make sure all interrupt causes cleared */ 4019 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 4020 4021 if (icr & E1000_ICR_RXT0) { 4022 mp = igb_rx(&igb->rx_rings[0], IGB_NO_POLL); 4023 } 4024 4025 if (icr & E1000_ICR_TXDW) { 4026 tx_ring = &igb->tx_rings[0]; 4027 4028 /* Recycle the tx descriptors */ 4029 tx_ring->tx_recycle(tx_ring); 4030 4031 /* Schedule the re-transmit */ 4032 tx_reschedule = (tx_ring->reschedule && 4033 (tx_ring->tbd_free >= igb->tx_resched_thresh)); 4034 } 4035 4036 if (icr & E1000_ICR_LSC) { 4037 /* 4038 * Because we got a link-status-change interrupt, force 4039 * e1000_check_for_link() to look at phy 4040 */ 4041 igb->hw.mac.get_link_status = B_TRUE; 4042 4043 /* igb_link_check takes care of link status change */ 4044 link_changed = igb_link_check(igb); 4045 4046 /* Get new phy state */ 4047 igb_get_phy_state(igb); 4048 } 4049 4050 if (icr & E1000_ICR_DRSTA) { 4051 /* 82580 Full Device Reset needed */ 4052 atomic_or_32(&igb->igb_state, IGB_STALL); 4053 } 4054 4055 result = DDI_INTR_CLAIMED; 4056 } else { 4057 /* 4058 * E1000_ICR_INT_ASSERTED bit was not set: 4059 * Don't claim this interrupt. 4060 */ 4061 result = DDI_INTR_UNCLAIMED; 4062 } 4063 4064 mutex_exit(&igb->gen_lock); 4065 4066 /* 4067 * Do the following work outside of the gen_lock 4068 */ 4069 if (mp != NULL) 4070 mac_rx(igb->mac_hdl, NULL, mp); 4071 4072 if (tx_reschedule) { 4073 tx_ring->reschedule = B_FALSE; 4074 mac_tx_ring_update(igb->mac_hdl, tx_ring->ring_handle); 4075 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 4076 } 4077 4078 if (link_changed) 4079 mac_link_update(igb->mac_hdl, igb->link_state); 4080 4081 return (result); 4082 } 4083 4084 /* 4085 * igb_intr_msi - Interrupt handler for MSI 4086 */ 4087 static uint_t 4088 igb_intr_msi(void *arg1, void *arg2) 4089 { 4090 igb_t *igb = (igb_t *)arg1; 4091 uint32_t icr; 4092 4093 _NOTE(ARGUNUSED(arg2)); 4094 4095 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4096 4097 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4098 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4099 atomic_or_32(&igb->igb_state, IGB_ERROR); 4100 return (DDI_INTR_CLAIMED); 4101 } 4102 4103 /* Make sure all interrupt causes cleared */ 4104 (void) E1000_READ_REG(&igb->hw, E1000_EICR); 4105 4106 /* 4107 * For MSI interrupt, we have only one vector, 4108 * so we have only one rx ring and one tx ring enabled. 4109 */ 4110 ASSERT(igb->num_rx_rings == 1); 4111 ASSERT(igb->num_tx_rings == 1); 4112 4113 if (icr & E1000_ICR_RXT0) { 4114 igb_intr_rx_work(&igb->rx_rings[0]); 4115 } 4116 4117 if (icr & E1000_ICR_TXDW) { 4118 igb_intr_tx_work(&igb->tx_rings[0]); 4119 } 4120 4121 if (icr & E1000_ICR_LSC) { 4122 igb_intr_link_work(igb); 4123 } 4124 4125 if (icr & E1000_ICR_DRSTA) { 4126 /* 82580 Full Device Reset needed */ 4127 atomic_or_32(&igb->igb_state, IGB_STALL); 4128 } 4129 4130 return (DDI_INTR_CLAIMED); 4131 } 4132 4133 /* 4134 * igb_intr_rx - Interrupt handler for rx 4135 */ 4136 static uint_t 4137 igb_intr_rx(void *arg1, void *arg2) 4138 { 4139 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 4140 4141 _NOTE(ARGUNUSED(arg2)); 4142 4143 /* 4144 * Only used via MSI-X vector so don't check cause bits 4145 * and only clean the given ring. 4146 */ 4147 igb_intr_rx_work(rx_ring); 4148 4149 return (DDI_INTR_CLAIMED); 4150 } 4151 4152 /* 4153 * igb_intr_tx - Interrupt handler for tx 4154 */ 4155 static uint_t 4156 igb_intr_tx(void *arg1, void *arg2) 4157 { 4158 igb_tx_ring_t *tx_ring = (igb_tx_ring_t *)arg1; 4159 4160 _NOTE(ARGUNUSED(arg2)); 4161 4162 /* 4163 * Only used via MSI-X vector so don't check cause bits 4164 * and only clean the given ring. 4165 */ 4166 igb_intr_tx_work(tx_ring); 4167 4168 return (DDI_INTR_CLAIMED); 4169 } 4170 4171 /* 4172 * igb_intr_tx_other - Interrupt handler for both tx and other 4173 * 4174 */ 4175 static uint_t 4176 igb_intr_tx_other(void *arg1, void *arg2) 4177 { 4178 igb_t *igb = (igb_t *)arg1; 4179 uint32_t icr; 4180 4181 _NOTE(ARGUNUSED(arg2)); 4182 4183 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 4184 4185 if (igb_check_acc_handle(igb->osdep.reg_handle) != DDI_FM_OK) { 4186 ddi_fm_service_impact(igb->dip, DDI_SERVICE_DEGRADED); 4187 atomic_or_32(&igb->igb_state, IGB_ERROR); 4188 return (DDI_INTR_CLAIMED); 4189 } 4190 4191 /* 4192 * Look for tx reclaiming work first. Remember, in the 4193 * case of only interrupt sharing, only one tx ring is 4194 * used 4195 */ 4196 igb_intr_tx_work(&igb->tx_rings[0]); 4197 4198 /* 4199 * Check for "other" causes. 4200 */ 4201 if (icr & E1000_ICR_LSC) { 4202 igb_intr_link_work(igb); 4203 } 4204 4205 /* 4206 * The DOUTSYNC bit indicates a tx packet dropped because 4207 * DMA engine gets "out of sync". There isn't a real fix 4208 * for this. The Intel recommendation is to count the number 4209 * of occurrences so user can detect when it is happening. 4210 * The issue is non-fatal and there's no recovery action 4211 * available. 4212 */ 4213 if (icr & E1000_ICR_DOUTSYNC) { 4214 IGB_STAT(igb->dout_sync); 4215 } 4216 4217 if (icr & E1000_ICR_DRSTA) { 4218 /* 82580 Full Device Reset needed */ 4219 atomic_or_32(&igb->igb_state, IGB_STALL); 4220 } 4221 4222 return (DDI_INTR_CLAIMED); 4223 } 4224 4225 /* 4226 * igb_alloc_intrs - Allocate interrupts for the driver 4227 * 4228 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 4229 * if not successful, try Legacy. 4230 * igb->intr_force can be used to force sequence to start with 4231 * any of the 3 types. 4232 * If MSI-X is not used, number of tx/rx rings is forced to 1. 4233 */ 4234 static int 4235 igb_alloc_intrs(igb_t *igb) 4236 { 4237 dev_info_t *devinfo; 4238 int intr_types; 4239 int rc; 4240 4241 devinfo = igb->dip; 4242 4243 /* Get supported interrupt types */ 4244 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4245 4246 if (rc != DDI_SUCCESS) { 4247 igb_log(igb, 4248 "Get supported interrupt types failed: %d", rc); 4249 return (IGB_FAILURE); 4250 } 4251 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 4252 4253 igb->intr_type = 0; 4254 4255 /* Install MSI-X interrupts */ 4256 if ((intr_types & DDI_INTR_TYPE_MSIX) && 4257 (igb->intr_force <= IGB_INTR_MSIX)) { 4258 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSIX); 4259 4260 if (rc == IGB_SUCCESS) 4261 return (IGB_SUCCESS); 4262 4263 igb_log(igb, 4264 "Allocate MSI-X failed, trying MSI interrupts..."); 4265 } 4266 4267 /* MSI-X not used, force rings to 1 */ 4268 igb->num_rx_rings = 1; 4269 igb->num_tx_rings = 1; 4270 igb_log(igb, 4271 "MSI-X not used, force rx and tx queue number to 1"); 4272 4273 /* Install MSI interrupts */ 4274 if ((intr_types & DDI_INTR_TYPE_MSI) && 4275 (igb->intr_force <= IGB_INTR_MSI)) { 4276 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_MSI); 4277 4278 if (rc == IGB_SUCCESS) 4279 return (IGB_SUCCESS); 4280 4281 igb_log(igb, 4282 "Allocate MSI failed, trying Legacy interrupts..."); 4283 } 4284 4285 /* Install legacy interrupts */ 4286 if (intr_types & DDI_INTR_TYPE_FIXED) { 4287 rc = igb_alloc_intr_handles(igb, DDI_INTR_TYPE_FIXED); 4288 4289 if (rc == IGB_SUCCESS) 4290 return (IGB_SUCCESS); 4291 4292 igb_log(igb, 4293 "Allocate Legacy interrupts failed"); 4294 } 4295 4296 /* If none of the 3 types succeeded, return failure */ 4297 return (IGB_FAILURE); 4298 } 4299 4300 /* 4301 * igb_alloc_intr_handles - Allocate interrupt handles. 4302 * 4303 * For legacy and MSI, only 1 handle is needed. For MSI-X, 4304 * if fewer than 2 handles are available, return failure. 4305 * Upon success, this sets the number of Rx rings to a number that 4306 * matches the handles available for Rx interrupts. 4307 */ 4308 static int 4309 igb_alloc_intr_handles(igb_t *igb, int intr_type) 4310 { 4311 dev_info_t *devinfo; 4312 int orig, request, count, avail, actual; 4313 int diff, minimum; 4314 int rc; 4315 4316 devinfo = igb->dip; 4317 4318 switch (intr_type) { 4319 case DDI_INTR_TYPE_FIXED: 4320 request = 1; /* Request 1 legacy interrupt handle */ 4321 minimum = 1; 4322 IGB_DEBUGLOG_0(igb, "interrupt type: legacy"); 4323 break; 4324 4325 case DDI_INTR_TYPE_MSI: 4326 request = 1; /* Request 1 MSI interrupt handle */ 4327 minimum = 1; 4328 IGB_DEBUGLOG_0(igb, "interrupt type: MSI"); 4329 break; 4330 4331 case DDI_INTR_TYPE_MSIX: 4332 /* 4333 * Number of vectors for the adapter is 4334 * # rx rings + # tx rings 4335 * One of tx vectors is for tx & other 4336 */ 4337 request = igb->num_rx_rings + igb->num_tx_rings; 4338 orig = request; 4339 minimum = 2; 4340 IGB_DEBUGLOG_0(igb, "interrupt type: MSI-X"); 4341 break; 4342 4343 default: 4344 igb_log(igb, 4345 "invalid call to igb_alloc_intr_handles(): %d\n", 4346 intr_type); 4347 return (IGB_FAILURE); 4348 } 4349 IGB_DEBUGLOG_2(igb, "interrupt handles requested: %d minimum: %d", 4350 request, minimum); 4351 4352 /* 4353 * Get number of supported interrupts 4354 */ 4355 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4356 if ((rc != DDI_SUCCESS) || (count < minimum)) { 4357 igb_log(igb, 4358 "Get supported interrupt number failed. " 4359 "Return: %d, count: %d", rc, count); 4360 return (IGB_FAILURE); 4361 } 4362 IGB_DEBUGLOG_1(igb, "interrupts supported: %d", count); 4363 4364 /* 4365 * Get number of available interrupts 4366 */ 4367 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4368 if ((rc != DDI_SUCCESS) || (avail < minimum)) { 4369 igb_log(igb, 4370 "Get available interrupt number failed. " 4371 "Return: %d, available: %d", rc, avail); 4372 return (IGB_FAILURE); 4373 } 4374 IGB_DEBUGLOG_1(igb, "interrupts available: %d", avail); 4375 4376 if (avail < request) { 4377 igb_log(igb, "Request %d handles, %d available", 4378 request, avail); 4379 request = avail; 4380 } 4381 4382 actual = 0; 4383 igb->intr_cnt = 0; 4384 4385 /* 4386 * Allocate an array of interrupt handles 4387 */ 4388 igb->intr_size = request * sizeof (ddi_intr_handle_t); 4389 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 4390 4391 rc = ddi_intr_alloc(devinfo, igb->htable, intr_type, 0, 4392 request, &actual, DDI_INTR_ALLOC_NORMAL); 4393 if (rc != DDI_SUCCESS) { 4394 igb_log(igb, "Allocate interrupts failed. " 4395 "return: %d, request: %d, actual: %d", 4396 rc, request, actual); 4397 goto alloc_handle_fail; 4398 } 4399 IGB_DEBUGLOG_1(igb, "interrupts actually allocated: %d", actual); 4400 4401 igb->intr_cnt = actual; 4402 4403 if (actual < minimum) { 4404 igb_log(igb, "Insufficient interrupt handles allocated: %d", 4405 actual); 4406 goto alloc_handle_fail; 4407 } 4408 4409 /* 4410 * For MSI-X, actual might force us to reduce number of tx & rx rings 4411 */ 4412 if ((intr_type == DDI_INTR_TYPE_MSIX) && (orig > actual)) { 4413 diff = orig - actual; 4414 if (diff < igb->num_tx_rings) { 4415 igb_log(igb, 4416 "MSI-X vectors force Tx queue number to %d", 4417 igb->num_tx_rings - diff); 4418 igb->num_tx_rings -= diff; 4419 } else { 4420 igb_log(igb, 4421 "MSI-X vectors force Tx queue number to 1"); 4422 igb->num_tx_rings = 1; 4423 4424 igb_log(igb, 4425 "MSI-X vectors force Rx queue number to %d", 4426 actual - 1); 4427 igb->num_rx_rings = actual - 1; 4428 } 4429 } 4430 4431 /* 4432 * Get priority for first vector, assume remaining are all the same 4433 */ 4434 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 4435 if (rc != DDI_SUCCESS) { 4436 igb_log(igb, 4437 "Get interrupt priority failed: %d", rc); 4438 goto alloc_handle_fail; 4439 } 4440 4441 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 4442 if (rc != DDI_SUCCESS) { 4443 igb_log(igb, 4444 "Get interrupt cap failed: %d", rc); 4445 goto alloc_handle_fail; 4446 } 4447 4448 igb->intr_type = intr_type; 4449 4450 return (IGB_SUCCESS); 4451 4452 alloc_handle_fail: 4453 igb_rem_intrs(igb); 4454 4455 return (IGB_FAILURE); 4456 } 4457 4458 /* 4459 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 4460 * 4461 * Before adding the interrupt handlers, the interrupt vectors have 4462 * been allocated, and the rx/tx rings have also been allocated. 4463 */ 4464 static int 4465 igb_add_intr_handlers(igb_t *igb) 4466 { 4467 igb_rx_ring_t *rx_ring; 4468 igb_tx_ring_t *tx_ring; 4469 int vector; 4470 int rc; 4471 int i; 4472 4473 vector = 0; 4474 4475 switch (igb->intr_type) { 4476 case DDI_INTR_TYPE_MSIX: 4477 /* Add interrupt handler for tx + other */ 4478 tx_ring = &igb->tx_rings[0]; 4479 rc = ddi_intr_add_handler(igb->htable[vector], 4480 (ddi_intr_handler_t *)igb_intr_tx_other, 4481 (void *)igb, NULL); 4482 4483 if (rc != DDI_SUCCESS) { 4484 igb_log(igb, 4485 "Add tx/other interrupt handler failed: %d", rc); 4486 return (IGB_FAILURE); 4487 } 4488 tx_ring->intr_vector = vector; 4489 vector++; 4490 4491 /* Add interrupt handler for each rx ring */ 4492 for (i = 0; i < igb->num_rx_rings; i++) { 4493 rx_ring = &igb->rx_rings[i]; 4494 4495 rc = ddi_intr_add_handler(igb->htable[vector], 4496 (ddi_intr_handler_t *)igb_intr_rx, 4497 (void *)rx_ring, NULL); 4498 4499 if (rc != DDI_SUCCESS) { 4500 igb_log(igb, 4501 "Add rx interrupt handler failed. " 4502 "return: %d, rx ring: %d", rc, i); 4503 for (vector--; vector >= 0; vector--) { 4504 (void) ddi_intr_remove_handler( 4505 igb->htable[vector]); 4506 } 4507 return (IGB_FAILURE); 4508 } 4509 4510 rx_ring->intr_vector = vector; 4511 4512 vector++; 4513 } 4514 4515 /* Add interrupt handler for each tx ring from 2nd ring */ 4516 for (i = 1; i < igb->num_tx_rings; i++) { 4517 tx_ring = &igb->tx_rings[i]; 4518 4519 rc = ddi_intr_add_handler(igb->htable[vector], 4520 (ddi_intr_handler_t *)igb_intr_tx, 4521 (void *)tx_ring, NULL); 4522 4523 if (rc != DDI_SUCCESS) { 4524 igb_log(igb, 4525 "Add tx interrupt handler failed. " 4526 "return: %d, tx ring: %d", rc, i); 4527 for (vector--; vector >= 0; vector--) { 4528 (void) ddi_intr_remove_handler( 4529 igb->htable[vector]); 4530 } 4531 return (IGB_FAILURE); 4532 } 4533 4534 tx_ring->intr_vector = vector; 4535 4536 vector++; 4537 } 4538 4539 break; 4540 4541 case DDI_INTR_TYPE_MSI: 4542 /* Add interrupt handlers for the only vector */ 4543 rc = ddi_intr_add_handler(igb->htable[vector], 4544 (ddi_intr_handler_t *)igb_intr_msi, 4545 (void *)igb, NULL); 4546 4547 if (rc != DDI_SUCCESS) { 4548 igb_log(igb, 4549 "Add MSI interrupt handler failed: %d", rc); 4550 return (IGB_FAILURE); 4551 } 4552 4553 rx_ring = &igb->rx_rings[0]; 4554 rx_ring->intr_vector = vector; 4555 4556 vector++; 4557 break; 4558 4559 case DDI_INTR_TYPE_FIXED: 4560 /* Add interrupt handlers for the only vector */ 4561 rc = ddi_intr_add_handler(igb->htable[vector], 4562 (ddi_intr_handler_t *)igb_intr_legacy, 4563 (void *)igb, NULL); 4564 4565 if (rc != DDI_SUCCESS) { 4566 igb_log(igb, 4567 "Add legacy interrupt handler failed: %d", rc); 4568 return (IGB_FAILURE); 4569 } 4570 4571 rx_ring = &igb->rx_rings[0]; 4572 rx_ring->intr_vector = vector; 4573 4574 vector++; 4575 break; 4576 4577 default: 4578 return (IGB_FAILURE); 4579 } 4580 4581 ASSERT(vector == igb->intr_cnt); 4582 4583 return (IGB_SUCCESS); 4584 } 4585 4586 /* 4587 * igb_setup_msix_82575 - setup 82575 adapter to use MSI-X interrupts 4588 * 4589 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 4590 */ 4591 static void 4592 igb_setup_msix_82575(igb_t *igb) 4593 { 4594 uint32_t eims = 0; 4595 int i, vector; 4596 struct e1000_hw *hw = &igb->hw; 4597 4598 /* 4599 * Set vector for tx ring 0 and other causes. 4600 * NOTE assumption that it is vector 0. 4601 */ 4602 vector = 0; 4603 4604 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 4605 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 4606 vector++; 4607 4608 for (i = 0; i < igb->num_rx_rings; i++) { 4609 /* 4610 * Set vector for each rx ring 4611 */ 4612 eims = (E1000_EICR_RX_QUEUE0 << i); 4613 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4614 4615 /* 4616 * Accumulate bits to enable in 4617 * igb_enable_adapter_interrupts_82575() 4618 */ 4619 igb->eims_mask |= eims; 4620 4621 vector++; 4622 } 4623 4624 for (i = 1; i < igb->num_tx_rings; i++) { 4625 /* 4626 * Set vector for each tx ring from 2nd tx ring 4627 */ 4628 eims = (E1000_EICR_TX_QUEUE0 << i); 4629 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 4630 4631 /* 4632 * Accumulate bits to enable in 4633 * igb_enable_adapter_interrupts_82575() 4634 */ 4635 igb->eims_mask |= eims; 4636 4637 vector++; 4638 } 4639 4640 ASSERT(vector == igb->intr_cnt); 4641 4642 /* 4643 * Disable IAM for ICR interrupt bits 4644 */ 4645 E1000_WRITE_REG(hw, E1000_IAM, 0); 4646 E1000_WRITE_FLUSH(hw); 4647 } 4648 4649 /* 4650 * igb_setup_msix_82576 - setup 82576 adapter to use MSI-X interrupts 4651 * 4652 * 82576 uses a table based method for assigning vectors. Each queue has a 4653 * single entry in the table to which we write a vector number along with a 4654 * "valid" bit. The entry is a single byte in a 4-byte register. Vectors 4655 * take a different position in the 4-byte register depending on whether 4656 * they are numbered above or below 8. 4657 */ 4658 static void 4659 igb_setup_msix_82576(igb_t *igb) 4660 { 4661 struct e1000_hw *hw = &igb->hw; 4662 uint32_t ivar, index, vector; 4663 int i; 4664 4665 /* must enable msi-x capability before IVAR settings */ 4666 E1000_WRITE_REG(hw, E1000_GPIE, 4667 (E1000_GPIE_MSIX_MODE | E1000_GPIE_PBA | E1000_GPIE_NSICR)); 4668 4669 /* 4670 * Set vector for tx ring 0 and other causes. 4671 * NOTE assumption that it is vector 0. 4672 * This is also interdependent with installation of interrupt service 4673 * routines in igb_add_intr_handlers(). 4674 */ 4675 4676 /* assign "other" causes to vector 0 */ 4677 vector = 0; 4678 ivar = ((vector | E1000_IVAR_VALID) << 8); 4679 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4680 4681 /* assign tx ring 0 to vector 0 */ 4682 ivar = ((vector | E1000_IVAR_VALID) << 8); 4683 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4684 4685 /* prepare to enable tx & other interrupt causes */ 4686 igb->eims_mask = (1 << vector); 4687 4688 vector ++; 4689 for (i = 0; i < igb->num_rx_rings; i++) { 4690 /* 4691 * Set vector for each rx ring 4692 */ 4693 index = (i & 0x7); 4694 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4695 4696 if (i < 8) { 4697 /* vector goes into low byte of register */ 4698 ivar = ivar & 0xFFFFFF00; 4699 ivar |= (vector | E1000_IVAR_VALID); 4700 } else { 4701 /* vector goes into third byte of register */ 4702 ivar = ivar & 0xFF00FFFF; 4703 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4704 } 4705 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4706 4707 /* Accumulate interrupt-cause bits to enable */ 4708 igb->eims_mask |= (1 << vector); 4709 4710 vector ++; 4711 } 4712 4713 for (i = 1; i < igb->num_tx_rings; i++) { 4714 /* 4715 * Set vector for each tx ring from 2nd tx ring. 4716 * Note assumption that tx vectors numericall follow rx vectors. 4717 */ 4718 index = (i & 0x7); 4719 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4720 4721 if (i < 8) { 4722 /* vector goes into second byte of register */ 4723 ivar = ivar & 0xFFFF00FF; 4724 ivar |= ((vector | E1000_IVAR_VALID) << 8); 4725 } else { 4726 /* vector goes into fourth byte of register */ 4727 ivar = ivar & 0x00FFFFFF; 4728 ivar |= (vector | E1000_IVAR_VALID) << 24; 4729 } 4730 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4731 4732 /* Accumulate interrupt-cause bits to enable */ 4733 igb->eims_mask |= (1 << vector); 4734 4735 vector ++; 4736 } 4737 4738 ASSERT(vector == igb->intr_cnt); 4739 } 4740 4741 /* 4742 * igb_setup_msix_82580 - setup 82580 adapter to use MSI-X interrupts 4743 * 4744 * 82580 uses same table approach at 82576 but has fewer entries. Each 4745 * queue has a single entry in the table to which we write a vector number 4746 * along with a "valid" bit. Vectors take a different position in the 4747 * register depending on * whether * they are numbered above or below 4. 4748 */ 4749 static void 4750 igb_setup_msix_82580(igb_t *igb) 4751 { 4752 struct e1000_hw *hw = &igb->hw; 4753 uint32_t ivar, index, vector; 4754 int i; 4755 4756 /* must enable msi-x capability before IVAR settings */ 4757 E1000_WRITE_REG(hw, E1000_GPIE, (E1000_GPIE_MSIX_MODE | 4758 E1000_GPIE_PBA | E1000_GPIE_NSICR | E1000_GPIE_EIAME)); 4759 /* 4760 * Set vector for tx ring 0 and other causes. 4761 * NOTE assumption that it is vector 0. 4762 * This is also interdependent with installation of interrupt service 4763 * routines in igb_add_intr_handlers(). 4764 */ 4765 4766 /* assign "other" causes to vector 0 */ 4767 vector = 0; 4768 ivar = ((vector | E1000_IVAR_VALID) << 8); 4769 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar); 4770 4771 /* assign tx ring 0 to vector 0 */ 4772 ivar = ((vector | E1000_IVAR_VALID) << 8); 4773 E1000_WRITE_REG(hw, E1000_IVAR0, ivar); 4774 4775 /* prepare to enable tx & other interrupt causes */ 4776 igb->eims_mask = (1 << vector); 4777 4778 vector ++; 4779 4780 for (i = 0; i < igb->num_rx_rings; i++) { 4781 /* 4782 * Set vector for each rx ring 4783 */ 4784 index = (i >> 1); 4785 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4786 4787 if (i & 1) { 4788 /* vector goes into third byte of register */ 4789 ivar = ivar & 0xFF00FFFF; 4790 ivar |= ((vector | E1000_IVAR_VALID) << 16); 4791 } else { 4792 /* vector goes into low byte of register */ 4793 ivar = ivar & 0xFFFFFF00; 4794 ivar |= (vector | E1000_IVAR_VALID); 4795 } 4796 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4797 4798 /* Accumulate interrupt-cause bits to enable */ 4799 igb->eims_mask |= (1 << vector); 4800 4801 vector ++; 4802 } 4803 4804 for (i = 1; i < igb->num_tx_rings; i++) { 4805 /* 4806 * Set vector for each tx ring from 2nd tx ring. 4807 * Note assumption that tx vectors numericall follow rx vectors. 4808 */ 4809 index = (i >> 1); 4810 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index); 4811 4812 if (i & 1) { 4813 /* vector goes into high byte of register */ 4814 ivar = ivar & 0x00FFFFFF; 4815 ivar |= ((vector | E1000_IVAR_VALID) << 24); 4816 } else { 4817 /* vector goes into second byte of register */ 4818 ivar = ivar & 0xFFFF00FF; 4819 ivar |= (vector | E1000_IVAR_VALID) << 8; 4820 } 4821 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar); 4822 4823 /* Accumulate interrupt-cause bits to enable */ 4824 igb->eims_mask |= (1 << vector); 4825 4826 vector ++; 4827 } 4828 ASSERT(vector == igb->intr_cnt); 4829 } 4830 4831 /* 4832 * igb_rem_intr_handlers - remove the interrupt handlers 4833 */ 4834 static void 4835 igb_rem_intr_handlers(igb_t *igb) 4836 { 4837 int i; 4838 int rc; 4839 4840 for (i = 0; i < igb->intr_cnt; i++) { 4841 rc = ddi_intr_remove_handler(igb->htable[i]); 4842 if (rc != DDI_SUCCESS) { 4843 IGB_DEBUGLOG_1(igb, 4844 "Remove intr handler failed: %d", rc); 4845 } 4846 } 4847 } 4848 4849 /* 4850 * igb_rem_intrs - remove the allocated interrupts 4851 */ 4852 static void 4853 igb_rem_intrs(igb_t *igb) 4854 { 4855 int i; 4856 int rc; 4857 4858 for (i = 0; i < igb->intr_cnt; i++) { 4859 rc = ddi_intr_free(igb->htable[i]); 4860 if (rc != DDI_SUCCESS) { 4861 IGB_DEBUGLOG_1(igb, 4862 "Free intr failed: %d", rc); 4863 } 4864 } 4865 4866 kmem_free(igb->htable, igb->intr_size); 4867 igb->htable = NULL; 4868 } 4869 4870 /* 4871 * igb_enable_intrs - enable all the ddi interrupts 4872 */ 4873 static int 4874 igb_enable_intrs(igb_t *igb) 4875 { 4876 int i; 4877 int rc; 4878 4879 /* Enable interrupts */ 4880 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4881 /* Call ddi_intr_block_enable() for MSI */ 4882 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 4883 if (rc != DDI_SUCCESS) { 4884 igb_log(igb, 4885 "Enable block intr failed: %d", rc); 4886 return (IGB_FAILURE); 4887 } 4888 } else { 4889 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4890 for (i = 0; i < igb->intr_cnt; i++) { 4891 rc = ddi_intr_enable(igb->htable[i]); 4892 if (rc != DDI_SUCCESS) { 4893 igb_log(igb, 4894 "Enable intr failed: %d", rc); 4895 return (IGB_FAILURE); 4896 } 4897 } 4898 } 4899 4900 return (IGB_SUCCESS); 4901 } 4902 4903 /* 4904 * igb_disable_intrs - disable all the ddi interrupts 4905 */ 4906 static int 4907 igb_disable_intrs(igb_t *igb) 4908 { 4909 int i; 4910 int rc; 4911 4912 /* Disable all interrupts */ 4913 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 4914 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 4915 if (rc != DDI_SUCCESS) { 4916 igb_log(igb, 4917 "Disable block intr failed: %d", rc); 4918 return (IGB_FAILURE); 4919 } 4920 } else { 4921 for (i = 0; i < igb->intr_cnt; i++) { 4922 rc = ddi_intr_disable(igb->htable[i]); 4923 if (rc != DDI_SUCCESS) { 4924 igb_log(igb, 4925 "Disable intr failed: %d", rc); 4926 return (IGB_FAILURE); 4927 } 4928 } 4929 } 4930 4931 return (IGB_SUCCESS); 4932 } 4933 4934 /* 4935 * igb_get_phy_state - Get and save the parameters read from PHY registers 4936 */ 4937 static void 4938 igb_get_phy_state(igb_t *igb) 4939 { 4940 struct e1000_hw *hw = &igb->hw; 4941 uint16_t phy_ctrl; 4942 uint16_t phy_status; 4943 uint16_t phy_an_adv; 4944 uint16_t phy_an_exp; 4945 uint16_t phy_ext_status; 4946 uint16_t phy_1000t_ctrl; 4947 uint16_t phy_1000t_status; 4948 uint16_t phy_lp_able; 4949 4950 ASSERT(mutex_owned(&igb->gen_lock)); 4951 4952 if (hw->phy.media_type == e1000_media_type_copper) { 4953 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4954 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 4955 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 4956 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 4957 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 4958 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 4959 (void) e1000_read_phy_reg(hw, 4960 PHY_1000T_STATUS, &phy_1000t_status); 4961 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 4962 4963 igb->param_autoneg_cap = 4964 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 4965 igb->param_pause_cap = 4966 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4967 igb->param_asym_pause_cap = 4968 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4969 igb->param_1000fdx_cap = 4970 ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4971 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 4972 igb->param_1000hdx_cap = 4973 ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 4974 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 4975 igb->param_100t4_cap = 4976 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 4977 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 4978 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 4979 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 4980 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 4981 igb->param_10fdx_cap = 4982 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 4983 igb->param_10hdx_cap = 4984 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 4985 igb->param_rem_fault = 4986 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 4987 4988 igb->param_adv_autoneg_cap = hw->mac.autoneg; 4989 igb->param_adv_pause_cap = 4990 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 4991 igb->param_adv_asym_pause_cap = 4992 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 4993 igb->param_adv_1000hdx_cap = 4994 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 4995 igb->param_adv_100t4_cap = 4996 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 4997 igb->param_adv_rem_fault = 4998 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 4999 if (igb->param_adv_autoneg_cap == 1) { 5000 igb->param_adv_1000fdx_cap = 5001 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5002 igb->param_adv_100fdx_cap = 5003 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5004 igb->param_adv_100hdx_cap = 5005 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5006 igb->param_adv_10fdx_cap = 5007 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5008 igb->param_adv_10hdx_cap = 5009 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5010 } 5011 5012 igb->param_lp_autoneg_cap = 5013 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5014 igb->param_lp_pause_cap = 5015 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5016 igb->param_lp_asym_pause_cap = 5017 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5018 igb->param_lp_1000fdx_cap = 5019 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5020 igb->param_lp_1000hdx_cap = 5021 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5022 igb->param_lp_100t4_cap = 5023 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5024 igb->param_lp_100fdx_cap = 5025 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5026 igb->param_lp_100hdx_cap = 5027 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5028 igb->param_lp_10fdx_cap = 5029 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5030 igb->param_lp_10hdx_cap = 5031 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5032 igb->param_lp_rem_fault = 5033 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 5034 } else { 5035 /* 5036 * 1Gig Fiber adapter only offers 1Gig Full Duplex. 5037 */ 5038 igb->param_autoneg_cap = 0; 5039 igb->param_pause_cap = 1; 5040 igb->param_asym_pause_cap = 1; 5041 igb->param_1000fdx_cap = 1; 5042 igb->param_1000hdx_cap = 0; 5043 igb->param_100t4_cap = 0; 5044 igb->param_100fdx_cap = 0; 5045 igb->param_100hdx_cap = 0; 5046 igb->param_10fdx_cap = 0; 5047 igb->param_10hdx_cap = 0; 5048 5049 igb->param_adv_autoneg_cap = 0; 5050 igb->param_adv_pause_cap = 1; 5051 igb->param_adv_asym_pause_cap = 1; 5052 igb->param_adv_1000fdx_cap = 1; 5053 igb->param_adv_1000hdx_cap = 0; 5054 igb->param_adv_100t4_cap = 0; 5055 igb->param_adv_100fdx_cap = 0; 5056 igb->param_adv_100hdx_cap = 0; 5057 igb->param_adv_10fdx_cap = 0; 5058 igb->param_adv_10hdx_cap = 0; 5059 5060 igb->param_lp_autoneg_cap = 0; 5061 igb->param_lp_pause_cap = 0; 5062 igb->param_lp_asym_pause_cap = 0; 5063 igb->param_lp_1000fdx_cap = 0; 5064 igb->param_lp_1000hdx_cap = 0; 5065 igb->param_lp_100t4_cap = 0; 5066 igb->param_lp_100fdx_cap = 0; 5067 igb->param_lp_100hdx_cap = 0; 5068 igb->param_lp_10fdx_cap = 0; 5069 igb->param_lp_10hdx_cap = 0; 5070 igb->param_lp_rem_fault = 0; 5071 } 5072 } 5073 5074 /* 5075 * synchronize the adv* and en* parameters. 5076 * 5077 * See comments in <sys/dld.h> for details of the *_en_* 5078 * parameters. The usage of ndd for setting adv parameters will 5079 * synchronize all the en parameters with the e1000g parameters, 5080 * implicitly disabling any settings made via dladm. 5081 */ 5082 static void 5083 igb_param_sync(igb_t *igb) 5084 { 5085 igb->param_en_1000fdx_cap = igb->param_adv_1000fdx_cap; 5086 igb->param_en_1000hdx_cap = igb->param_adv_1000hdx_cap; 5087 igb->param_en_100t4_cap = igb->param_adv_100t4_cap; 5088 igb->param_en_100fdx_cap = igb->param_adv_100fdx_cap; 5089 igb->param_en_100hdx_cap = igb->param_adv_100hdx_cap; 5090 igb->param_en_10fdx_cap = igb->param_adv_10fdx_cap; 5091 igb->param_en_10hdx_cap = igb->param_adv_10hdx_cap; 5092 } 5093 5094 /* 5095 * igb_get_driver_control 5096 */ 5097 static void 5098 igb_get_driver_control(struct e1000_hw *hw) 5099 { 5100 uint32_t ctrl_ext; 5101 5102 /* Notify firmware that driver is in control of device */ 5103 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5104 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 5105 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5106 } 5107 5108 /* 5109 * igb_release_driver_control 5110 */ 5111 static void 5112 igb_release_driver_control(struct e1000_hw *hw) 5113 { 5114 uint32_t ctrl_ext; 5115 5116 /* Notify firmware that driver is no longer in control of device */ 5117 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5118 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 5119 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5120 } 5121 5122 /* 5123 * igb_atomic_reserve - Atomic decrease operation 5124 */ 5125 int 5126 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 5127 { 5128 uint32_t oldval; 5129 uint32_t newval; 5130 5131 /* ATOMICALLY */ 5132 do { 5133 oldval = *count_p; 5134 if (oldval < n) 5135 return (-1); 5136 newval = oldval - n; 5137 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 5138 5139 return (newval); 5140 } 5141 5142 /* 5143 * FMA support 5144 */ 5145 5146 int 5147 igb_check_acc_handle(ddi_acc_handle_t handle) 5148 { 5149 ddi_fm_error_t de; 5150 5151 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5152 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5153 return (de.fme_status); 5154 } 5155 5156 int 5157 igb_check_dma_handle(ddi_dma_handle_t handle) 5158 { 5159 ddi_fm_error_t de; 5160 5161 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5162 return (de.fme_status); 5163 } 5164 5165 /* 5166 * The IO fault service error handling callback function 5167 */ 5168 /*ARGSUSED*/ 5169 static int 5170 igb_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5171 { 5172 /* 5173 * as the driver can always deal with an error in any dma or 5174 * access handle, we can just return the fme_status value. 5175 */ 5176 pci_ereport_post(dip, err, NULL); 5177 return (err->fme_status); 5178 } 5179 5180 static void 5181 igb_fm_init(igb_t *igb) 5182 { 5183 ddi_iblock_cookie_t iblk; 5184 int fma_dma_flag; 5185 5186 /* Only register with IO Fault Services if we have some capability */ 5187 if (igb->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5188 igb_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5189 } else { 5190 igb_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5191 } 5192 5193 if (igb->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5194 fma_dma_flag = 1; 5195 } else { 5196 fma_dma_flag = 0; 5197 } 5198 5199 (void) igb_set_fma_flags(fma_dma_flag); 5200 5201 if (igb->fm_capabilities) { 5202 5203 /* Register capabilities with IO Fault Services */ 5204 ddi_fm_init(igb->dip, &igb->fm_capabilities, &iblk); 5205 5206 /* 5207 * Initialize pci ereport capabilities if ereport capable 5208 */ 5209 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 5210 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5211 pci_ereport_setup(igb->dip); 5212 5213 /* 5214 * Register error callback if error callback capable 5215 */ 5216 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5217 ddi_fm_handler_register(igb->dip, 5218 igb_fm_error_cb, (void*) igb); 5219 } 5220 } 5221 5222 static void 5223 igb_fm_fini(igb_t *igb) 5224 { 5225 /* Only unregister FMA capabilities if we registered some */ 5226 if (igb->fm_capabilities) { 5227 5228 /* 5229 * Release any resources allocated by pci_ereport_setup() 5230 */ 5231 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities) || 5232 DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5233 pci_ereport_teardown(igb->dip); 5234 5235 /* 5236 * Un-register error callback if error callback capable 5237 */ 5238 if (DDI_FM_ERRCB_CAP(igb->fm_capabilities)) 5239 ddi_fm_handler_unregister(igb->dip); 5240 5241 /* Unregister from IO Fault Services */ 5242 ddi_fm_fini(igb->dip); 5243 } 5244 } 5245 5246 void 5247 igb_fm_ereport(igb_t *igb, char *detail) 5248 { 5249 uint64_t ena; 5250 char buf[FM_MAX_CLASS]; 5251 5252 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5253 ena = fm_ena_generate(0, FM_ENA_FMT1); 5254 if (DDI_FM_EREPORT_CAP(igb->fm_capabilities)) { 5255 ddi_fm_ereport_post(igb->dip, buf, ena, DDI_NOSLEEP, 5256 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5257 } 5258 } 5259