1 /* 2 * CDDL HEADER START 3 * 4 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved. 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at: 10 * http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When using or redistributing this file, you may do so under the 15 * License only. No other modification of this header is permitted. 16 * 17 * If applicable, add the following below this CDDL HEADER, with the 18 * fields enclosed by brackets "[]" replaced with your own identifying 19 * information: Portions Copyright [yyyy] [name of copyright owner] 20 * 21 * CDDL HEADER END 22 */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms of the CDDL. 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include "igb_sw.h" 32 33 static char ident[] = "Intel 1Gb Ethernet 1.1.1"; 34 35 /* 36 * Local function protoypes 37 */ 38 static int igb_register_mac(igb_t *); 39 static int igb_identify_hardware(igb_t *); 40 static int igb_regs_map(igb_t *); 41 static void igb_init_properties(igb_t *); 42 static int igb_init_driver_settings(igb_t *); 43 static void igb_init_locks(igb_t *); 44 static void igb_destroy_locks(igb_t *); 45 static int igb_init(igb_t *); 46 static int igb_chip_start(igb_t *); 47 static void igb_chip_stop(igb_t *); 48 static int igb_reset(igb_t *); 49 static void igb_tx_clean(igb_t *); 50 static boolean_t igb_tx_drain(igb_t *); 51 static boolean_t igb_rx_drain(igb_t *); 52 static int igb_alloc_rings(igb_t *); 53 static int igb_init_rings(igb_t *); 54 static void igb_free_rings(igb_t *); 55 static void igb_fini_rings(igb_t *); 56 static void igb_setup_rings(igb_t *); 57 static void igb_setup_rx(igb_t *); 58 static void igb_setup_tx(igb_t *); 59 static void igb_setup_rx_ring(igb_rx_ring_t *); 60 static void igb_setup_tx_ring(igb_tx_ring_t *); 61 static void igb_setup_rss(igb_t *); 62 static void igb_init_unicst(igb_t *); 63 static void igb_setup_multicst(igb_t *); 64 static void igb_get_phy_state(igb_t *); 65 static void igb_get_conf(igb_t *); 66 static int igb_get_prop(igb_t *, char *, int, int, int); 67 static boolean_t igb_is_link_up(igb_t *); 68 static boolean_t igb_link_check(igb_t *); 69 static void igb_local_timer(void *); 70 static void igb_arm_watchdog_timer(igb_t *); 71 static void igb_start_watchdog_timer(igb_t *); 72 static void igb_restart_watchdog_timer(igb_t *); 73 static void igb_stop_watchdog_timer(igb_t *); 74 static void igb_disable_adapter_interrupts(igb_t *); 75 static void igb_enable_adapter_interrupts(igb_t *); 76 static boolean_t is_valid_mac_addr(uint8_t *); 77 static boolean_t igb_stall_check(igb_t *); 78 static boolean_t igb_set_loopback_mode(igb_t *, uint32_t); 79 static void igb_set_external_loopback(igb_t *); 80 static void igb_set_internal_mac_loopback(igb_t *); 81 static void igb_set_internal_phy_loopback(igb_t *); 82 static void igb_set_internal_serdes_loopback(igb_t *); 83 static boolean_t igb_find_mac_address(igb_t *); 84 static int igb_alloc_intrs(igb_t *); 85 static int igb_alloc_intrs_msix(igb_t *); 86 static int igb_alloc_intrs_msi(igb_t *); 87 static int igb_alloc_intrs_legacy(igb_t *); 88 static int igb_add_intr_handlers(igb_t *); 89 static void igb_rem_intr_handlers(igb_t *); 90 static void igb_rem_intrs(igb_t *); 91 static int igb_enable_intrs(igb_t *); 92 static int igb_disable_intrs(igb_t *); 93 static void igb_setup_adapter_msix(igb_t *); 94 static uint_t igb_intr_legacy(void *, void *); 95 static uint_t igb_intr_msi(void *, void *); 96 static uint_t igb_intr_rx(void *, void *); 97 static uint_t igb_intr_tx_other(void *, void *); 98 static void igb_intr_rx_work(igb_rx_ring_t *); 99 static void igb_intr_tx_work(igb_tx_ring_t *); 100 static void igb_intr_other_work(igb_t *); 101 static void igb_get_driver_control(struct e1000_hw *); 102 static void igb_release_driver_control(struct e1000_hw *); 103 104 static int igb_attach(dev_info_t *, ddi_attach_cmd_t); 105 static int igb_detach(dev_info_t *, ddi_detach_cmd_t); 106 static int igb_resume(dev_info_t *); 107 static int igb_suspend(dev_info_t *); 108 static void igb_unconfigure(dev_info_t *, igb_t *); 109 110 static struct cb_ops igb_cb_ops = { 111 nulldev, /* cb_open */ 112 nulldev, /* cb_close */ 113 nodev, /* cb_strategy */ 114 nodev, /* cb_print */ 115 nodev, /* cb_dump */ 116 nodev, /* cb_read */ 117 nodev, /* cb_write */ 118 nodev, /* cb_ioctl */ 119 nodev, /* cb_devmap */ 120 nodev, /* cb_mmap */ 121 nodev, /* cb_segmap */ 122 nochpoll, /* cb_chpoll */ 123 ddi_prop_op, /* cb_prop_op */ 124 NULL, /* cb_stream */ 125 D_MP | D_HOTPLUG, /* cb_flag */ 126 CB_REV, /* cb_rev */ 127 nodev, /* cb_aread */ 128 nodev /* cb_awrite */ 129 }; 130 131 static struct dev_ops igb_dev_ops = { 132 DEVO_REV, /* devo_rev */ 133 0, /* devo_refcnt */ 134 NULL, /* devo_getinfo */ 135 nulldev, /* devo_identify */ 136 nulldev, /* devo_probe */ 137 igb_attach, /* devo_attach */ 138 igb_detach, /* devo_detach */ 139 nodev, /* devo_reset */ 140 &igb_cb_ops, /* devo_cb_ops */ 141 NULL, /* devo_bus_ops */ 142 ddi_power /* devo_power */ 143 }; 144 145 static struct modldrv igb_modldrv = { 146 &mod_driverops, /* Type of module. This one is a driver */ 147 ident, /* Discription string */ 148 &igb_dev_ops, /* driver ops */ 149 }; 150 151 static struct modlinkage igb_modlinkage = { 152 MODREV_1, &igb_modldrv, NULL 153 }; 154 155 /* Access attributes for register mapping */ 156 ddi_device_acc_attr_t igb_regs_acc_attr = { 157 DDI_DEVICE_ATTR_V0, 158 DDI_STRUCTURE_LE_ACC, 159 DDI_STRICTORDER_ACC, 160 }; 161 162 #define IGB_M_CALLBACK_FLAGS (MC_IOCTL | MC_GETCAPAB) 163 164 static mac_callbacks_t igb_m_callbacks = { 165 IGB_M_CALLBACK_FLAGS, 166 igb_m_stat, 167 igb_m_start, 168 igb_m_stop, 169 igb_m_promisc, 170 igb_m_multicst, 171 igb_m_unicst, 172 igb_m_tx, 173 NULL, 174 igb_m_ioctl, 175 igb_m_getcapab 176 }; 177 178 179 /* 180 * Module Initialization Functions 181 */ 182 183 int 184 _init(void) 185 { 186 int status; 187 188 mac_init_ops(&igb_dev_ops, MODULE_NAME); 189 190 status = mod_install(&igb_modlinkage); 191 192 if (status != DDI_SUCCESS) { 193 mac_fini_ops(&igb_dev_ops); 194 } 195 196 return (status); 197 } 198 199 int 200 _fini(void) 201 { 202 int status; 203 204 status = mod_remove(&igb_modlinkage); 205 206 if (status == DDI_SUCCESS) { 207 mac_fini_ops(&igb_dev_ops); 208 } 209 210 return (status); 211 212 } 213 214 int 215 _info(struct modinfo *modinfop) 216 { 217 int status; 218 219 status = mod_info(&igb_modlinkage, modinfop); 220 221 return (status); 222 } 223 224 /* 225 * igb_attach - driver attach 226 * 227 * This function is the device specific initialization entry 228 * point. This entry point is required and must be written. 229 * The DDI_ATTACH command must be provided in the attach entry 230 * point. When attach() is called with cmd set to DDI_ATTACH, 231 * all normal kernel services (such as kmem_alloc(9F)) are 232 * available for use by the driver. 233 * 234 * The attach() function will be called once for each instance 235 * of the device on the system with cmd set to DDI_ATTACH. 236 * Until attach() succeeds, the only driver entry points which 237 * may be called are open(9E) and getinfo(9E). 238 */ 239 static int 240 igb_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 241 { 242 igb_t *igb; 243 struct igb_osdep *osdep; 244 struct e1000_hw *hw; 245 int instance; 246 247 /* 248 * Check the command and perform corresponding operations 249 */ 250 switch (cmd) { 251 default: 252 return (DDI_FAILURE); 253 254 case DDI_RESUME: 255 return (igb_resume(devinfo)); 256 257 case DDI_ATTACH: 258 break; 259 } 260 261 /* Get the device instance */ 262 instance = ddi_get_instance(devinfo); 263 264 /* Allocate memory for the instance data structure */ 265 igb = kmem_zalloc(sizeof (igb_t), KM_SLEEP); 266 267 igb->dip = devinfo; 268 igb->instance = instance; 269 270 hw = &igb->hw; 271 osdep = &igb->osdep; 272 hw->back = osdep; 273 osdep->igb = igb; 274 275 /* Attach the instance pointer to the dev_info data structure */ 276 ddi_set_driver_private(devinfo, igb); 277 278 /* 279 * Map PCI config space registers 280 */ 281 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 282 igb_error(igb, "Failed to map PCI configurations"); 283 goto attach_fail; 284 } 285 igb->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 286 287 /* 288 * Identify the chipset family 289 */ 290 if (igb_identify_hardware(igb) != IGB_SUCCESS) { 291 igb_error(igb, "Failed to identify hardware"); 292 goto attach_fail; 293 } 294 295 /* 296 * Map device registers 297 */ 298 if (igb_regs_map(igb) != IGB_SUCCESS) { 299 igb_error(igb, "Failed to map device registers"); 300 goto attach_fail; 301 } 302 igb->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 303 304 /* 305 * Initialize driver parameters 306 */ 307 igb_init_properties(igb); 308 igb->attach_progress |= ATTACH_PROGRESS_PROPS; 309 310 /* 311 * Allocate interrupts 312 */ 313 if (igb_alloc_intrs(igb) != IGB_SUCCESS) { 314 igb_error(igb, "Failed to allocate interrupts"); 315 goto attach_fail; 316 } 317 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_INTR; 318 319 /* 320 * Allocate rx/tx rings based on the ring numbers. 321 * The actual numbers of rx/tx rings are decided by the number of 322 * allocated interrupt vectors, so we should allocate the rings after 323 * interrupts are allocated. 324 */ 325 if (igb_alloc_rings(igb) != IGB_SUCCESS) { 326 igb_error(igb, "Failed to allocate rx and tx rings"); 327 goto attach_fail; 328 } 329 igb->attach_progress |= ATTACH_PROGRESS_ALLOC_RINGS; 330 331 /* 332 * Add interrupt handlers 333 */ 334 if (igb_add_intr_handlers(igb) != IGB_SUCCESS) { 335 igb_error(igb, "Failed to add interrupt handlers"); 336 goto attach_fail; 337 } 338 igb->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 339 340 /* 341 * Initialize driver parameters 342 */ 343 if (igb_init_driver_settings(igb) != IGB_SUCCESS) { 344 igb_error(igb, "Failed to initialize driver settings"); 345 goto attach_fail; 346 } 347 348 /* 349 * Initialize mutexes for this device. 350 * Do this before enabling the interrupt handler and 351 * register the softint to avoid the condition where 352 * interrupt handler can try using uninitialized mutex 353 */ 354 igb_init_locks(igb); 355 igb->attach_progress |= ATTACH_PROGRESS_LOCKS; 356 357 /* 358 * Initialize chipset hardware 359 */ 360 if (igb_init(igb) != IGB_SUCCESS) { 361 igb_error(igb, "Failed to initialize adapter"); 362 goto attach_fail; 363 } 364 igb->attach_progress |= ATTACH_PROGRESS_INIT; 365 366 /* 367 * Initialize DMA and hardware settings for rx/tx rings 368 */ 369 if (igb_init_rings(igb) != IGB_SUCCESS) { 370 igb_error(igb, "Failed to initialize rings"); 371 goto attach_fail; 372 } 373 igb->attach_progress |= ATTACH_PROGRESS_INIT_RINGS; 374 375 /* 376 * Initialize statistics 377 */ 378 if (igb_init_stats(igb) != IGB_SUCCESS) { 379 igb_error(igb, "Failed to initialize statistics"); 380 goto attach_fail; 381 } 382 igb->attach_progress |= ATTACH_PROGRESS_STATS; 383 384 /* 385 * Initialize NDD parameters 386 */ 387 if (igb_nd_init(igb) != IGB_SUCCESS) { 388 igb_error(igb, "Failed to initialize ndd"); 389 goto attach_fail; 390 } 391 igb->attach_progress |= ATTACH_PROGRESS_NDD; 392 393 /* 394 * Register the driver to the MAC 395 */ 396 if (igb_register_mac(igb) != IGB_SUCCESS) { 397 igb_error(igb, "Failed to register MAC"); 398 goto attach_fail; 399 } 400 igb->attach_progress |= ATTACH_PROGRESS_MAC; 401 402 /* 403 * Now that mutex locks are initialized, and the chip is also 404 * initialized, enable interrupts. 405 */ 406 if (igb_enable_intrs(igb) != IGB_SUCCESS) { 407 igb_error(igb, "Failed to enable DDI interrupts"); 408 goto attach_fail; 409 } 410 igb->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 411 412 igb->igb_state |= IGB_INITIALIZED; 413 414 return (DDI_SUCCESS); 415 416 attach_fail: 417 igb_unconfigure(devinfo, igb); 418 return (DDI_FAILURE); 419 } 420 421 /* 422 * igb_detach - driver detach 423 * 424 * The detach() function is the complement of the attach routine. 425 * If cmd is set to DDI_DETACH, detach() is used to remove the 426 * state associated with a given instance of a device node 427 * prior to the removal of that instance from the system. 428 * 429 * The detach() function will be called once for each instance 430 * of the device for which there has been a successful attach() 431 * once there are no longer any opens on the device. 432 * 433 * Interrupts routine are disabled, All memory allocated by this 434 * driver are freed. 435 */ 436 static int 437 igb_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 438 { 439 igb_t *igb; 440 441 /* 442 * Check detach command 443 */ 444 switch (cmd) { 445 default: 446 return (DDI_FAILURE); 447 448 case DDI_SUSPEND: 449 return (igb_suspend(devinfo)); 450 451 case DDI_DETACH: 452 break; 453 } 454 455 456 /* 457 * Get the pointer to the driver private data structure 458 */ 459 igb = (igb_t *)ddi_get_driver_private(devinfo); 460 if (igb == NULL) 461 return (DDI_FAILURE); 462 463 /* 464 * Unregister MAC. If failed, we have to fail the detach 465 */ 466 if (mac_unregister(igb->mac_hdl) != 0) { 467 igb_error(igb, "Failed to unregister MAC"); 468 return (DDI_FAILURE); 469 } 470 igb->attach_progress &= ~ATTACH_PROGRESS_MAC; 471 472 /* 473 * If the device is still running, it needs to be stopped first. 474 * This check is necessary because under some specific circumstances, 475 * the detach routine can be called without stopping the interface 476 * first. 477 */ 478 mutex_enter(&igb->gen_lock); 479 if (igb->igb_state & IGB_STARTED) { 480 igb->igb_state &= ~IGB_STARTED; 481 igb_stop(igb); 482 mutex_exit(&igb->gen_lock); 483 /* Disable and stop the watchdog timer */ 484 igb_disable_watchdog_timer(igb); 485 } else 486 mutex_exit(&igb->gen_lock); 487 488 /* 489 * Check if there are still rx buffers held by the upper layer. 490 * If so, fail the detach. 491 */ 492 if (!igb_rx_drain(igb)) 493 return (DDI_FAILURE); 494 495 /* 496 * Do the remaining unconfigure routines 497 */ 498 igb_unconfigure(devinfo, igb); 499 500 return (DDI_SUCCESS); 501 } 502 503 static void 504 igb_unconfigure(dev_info_t *devinfo, igb_t *igb) 505 { 506 /* 507 * Disable interrupt 508 */ 509 if (igb->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 510 (void) igb_disable_intrs(igb); 511 } 512 513 /* 514 * Unregister MAC 515 */ 516 if (igb->attach_progress & ATTACH_PROGRESS_MAC) { 517 (void) mac_unregister(igb->mac_hdl); 518 } 519 520 /* 521 * Free ndd parameters 522 */ 523 if (igb->attach_progress & ATTACH_PROGRESS_NDD) { 524 igb_nd_cleanup(igb); 525 } 526 527 /* 528 * Free statistics 529 */ 530 if (igb->attach_progress & ATTACH_PROGRESS_STATS) { 531 kstat_delete((kstat_t *)igb->igb_ks); 532 } 533 534 /* 535 * Remove interrupt handlers 536 */ 537 if (igb->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 538 igb_rem_intr_handlers(igb); 539 } 540 541 /* 542 * Remove interrupts 543 */ 544 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_INTR) { 545 igb_rem_intrs(igb); 546 } 547 548 /* 549 * Remove driver properties 550 */ 551 if (igb->attach_progress & ATTACH_PROGRESS_PROPS) { 552 (void) ddi_prop_remove_all(devinfo); 553 } 554 555 /* 556 * Release the DMA resources of rx/tx rings 557 */ 558 if (igb->attach_progress & ATTACH_PROGRESS_INIT_RINGS) { 559 igb_fini_rings(igb); 560 } 561 562 /* 563 * Stop the chipset 564 */ 565 if (igb->attach_progress & ATTACH_PROGRESS_INIT) { 566 mutex_enter(&igb->gen_lock); 567 igb_chip_stop(igb); 568 mutex_exit(&igb->gen_lock); 569 } 570 571 /* 572 * Free register handle 573 */ 574 if (igb->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 575 if (igb->osdep.reg_handle != NULL) 576 ddi_regs_map_free(&igb->osdep.reg_handle); 577 } 578 579 /* 580 * Free PCI config handle 581 */ 582 if (igb->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 583 if (igb->osdep.cfg_handle != NULL) 584 pci_config_teardown(&igb->osdep.cfg_handle); 585 } 586 587 /* 588 * Free locks 589 */ 590 if (igb->attach_progress & ATTACH_PROGRESS_LOCKS) { 591 igb_destroy_locks(igb); 592 } 593 594 /* 595 * Free the rx/tx rings 596 */ 597 if (igb->attach_progress & ATTACH_PROGRESS_ALLOC_RINGS) { 598 igb_free_rings(igb); 599 } 600 601 /* 602 * Free device specific structure 603 */ 604 e1000_remove_device(&igb->hw); 605 606 /* 607 * Free the driver data structure 608 */ 609 kmem_free(igb, sizeof (igb_t)); 610 611 ddi_set_driver_private(devinfo, NULL); 612 } 613 614 /* 615 * igb_register_mac - Register the driver and its function pointers with 616 * the GLD interface 617 */ 618 static int 619 igb_register_mac(igb_t *igb) 620 { 621 struct e1000_hw *hw = &igb->hw; 622 mac_register_t *mac; 623 int status; 624 625 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 626 return (IGB_FAILURE); 627 628 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 629 mac->m_driver = igb; 630 mac->m_dip = igb->dip; 631 mac->m_src_addr = hw->mac.addr; 632 mac->m_callbacks = &igb_m_callbacks; 633 mac->m_min_sdu = 0; 634 mac->m_max_sdu = igb->max_frame_size - 635 sizeof (struct ether_vlan_header) - ETHERFCSL; 636 637 status = mac_register(mac, &igb->mac_hdl); 638 639 mac_free(mac); 640 641 return ((status == 0) ? IGB_SUCCESS : IGB_FAILURE); 642 } 643 644 /* 645 * igb_identify_hardware - Identify the type of the chipset 646 */ 647 static int 648 igb_identify_hardware(igb_t *igb) 649 { 650 struct e1000_hw *hw = &igb->hw; 651 struct igb_osdep *osdep = &igb->osdep; 652 653 /* 654 * Get the device id 655 */ 656 hw->vendor_id = 657 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 658 hw->device_id = 659 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 660 hw->revision_id = 661 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 662 hw->subsystem_device_id = 663 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 664 hw->subsystem_vendor_id = 665 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 666 667 /* 668 * Set the mac type of the adapter based on the device id 669 */ 670 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 671 return (IGB_FAILURE); 672 } 673 674 return (IGB_SUCCESS); 675 } 676 677 /* 678 * igb_regs_map - Map the device registers 679 */ 680 static int 681 igb_regs_map(igb_t *igb) 682 { 683 dev_info_t *devinfo = igb->dip; 684 struct e1000_hw *hw = &igb->hw; 685 struct igb_osdep *osdep = &igb->osdep; 686 off_t mem_size; 687 688 /* 689 * First get the size of device registers to be mapped. 690 */ 691 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 692 return (IGB_FAILURE); 693 } 694 695 /* 696 * Call ddi_regs_map_setup() to map registers 697 */ 698 if ((ddi_regs_map_setup(devinfo, 1, 699 (caddr_t *)&hw->hw_addr, 0, 700 mem_size, &igb_regs_acc_attr, 701 &osdep->reg_handle)) != DDI_SUCCESS) { 702 return (IGB_FAILURE); 703 } 704 705 return (IGB_SUCCESS); 706 } 707 708 /* 709 * igb_init_properties - Initialize driver properties 710 */ 711 static void 712 igb_init_properties(igb_t *igb) 713 { 714 /* 715 * Get conf file properties, including link settings 716 * jumbo frames, ring number, descriptor number, etc. 717 */ 718 igb_get_conf(igb); 719 } 720 721 /* 722 * igb_init_driver_settings - Initialize driver settings 723 * 724 * The settings include hardware function pointers, bus information, 725 * rx/tx rings settings, link state, and any other parameters that 726 * need to be setup during driver initialization. 727 */ 728 static int 729 igb_init_driver_settings(igb_t *igb) 730 { 731 struct e1000_hw *hw = &igb->hw; 732 igb_rx_ring_t *rx_ring; 733 igb_tx_ring_t *tx_ring; 734 uint32_t rx_size; 735 uint32_t tx_size; 736 int i; 737 738 /* 739 * Initialize chipset specific hardware function pointers 740 */ 741 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 742 return (IGB_FAILURE); 743 } 744 745 /* 746 * Get bus information 747 */ 748 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 749 return (IGB_FAILURE); 750 } 751 752 /* 753 * Set rx buffer size 754 * The IP header alignment room is counted in the calculation. 755 * The rx buffer size is in unit of 1K that is required by the 756 * chipset hardware. 757 */ 758 rx_size = igb->max_frame_size + IPHDR_ALIGN_ROOM; 759 igb->rx_buf_size = ((rx_size >> 10) + 760 ((rx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 761 762 /* 763 * Set tx buffer size 764 */ 765 tx_size = igb->max_frame_size; 766 igb->tx_buf_size = ((tx_size >> 10) + 767 ((tx_size & (((uint32_t)1 << 10) - 1)) > 0 ? 1 : 0)) << 10; 768 769 /* 770 * Initialize rx/tx rings parameters 771 */ 772 for (i = 0; i < igb->num_rx_rings; i++) { 773 rx_ring = &igb->rx_rings[i]; 774 rx_ring->index = i; 775 rx_ring->igb = igb; 776 777 rx_ring->ring_size = igb->rx_ring_size; 778 rx_ring->free_list_size = igb->rx_ring_size; 779 rx_ring->copy_thresh = igb->rx_copy_thresh; 780 rx_ring->limit_per_intr = igb->rx_limit_per_intr; 781 } 782 783 for (i = 0; i < igb->num_tx_rings; i++) { 784 tx_ring = &igb->tx_rings[i]; 785 tx_ring->index = i; 786 tx_ring->igb = igb; 787 if (igb->tx_head_wb_enable) 788 tx_ring->tx_recycle = igb_tx_recycle_head_wb; 789 else 790 tx_ring->tx_recycle = igb_tx_recycle_legacy; 791 792 tx_ring->ring_size = igb->tx_ring_size; 793 tx_ring->free_list_size = igb->tx_ring_size + 794 (igb->tx_ring_size >> 1); 795 tx_ring->copy_thresh = igb->tx_copy_thresh; 796 tx_ring->recycle_thresh = igb->tx_recycle_thresh; 797 tx_ring->overload_thresh = igb->tx_overload_thresh; 798 tx_ring->resched_thresh = igb->tx_resched_thresh; 799 } 800 801 /* 802 * Initialize values of interrupt throttling rate 803 */ 804 for (i = 1; i < MAX_NUM_EITR; i++) 805 igb->intr_throttling[i] = igb->intr_throttling[0]; 806 807 /* 808 * The initial link state should be "unknown" 809 */ 810 igb->link_state = LINK_STATE_UNKNOWN; 811 812 return (IGB_SUCCESS); 813 } 814 815 /* 816 * igb_init_locks - Initialize locks 817 */ 818 static void 819 igb_init_locks(igb_t *igb) 820 { 821 igb_rx_ring_t *rx_ring; 822 igb_tx_ring_t *tx_ring; 823 int i; 824 825 for (i = 0; i < igb->num_rx_rings; i++) { 826 rx_ring = &igb->rx_rings[i]; 827 mutex_init(&rx_ring->rx_lock, NULL, 828 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 829 mutex_init(&rx_ring->recycle_lock, NULL, 830 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 831 } 832 833 for (i = 0; i < igb->num_tx_rings; i++) { 834 tx_ring = &igb->tx_rings[i]; 835 mutex_init(&tx_ring->tx_lock, NULL, 836 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 837 mutex_init(&tx_ring->recycle_lock, NULL, 838 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 839 mutex_init(&tx_ring->tcb_head_lock, NULL, 840 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 841 mutex_init(&tx_ring->tcb_tail_lock, NULL, 842 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 843 } 844 845 mutex_init(&igb->gen_lock, NULL, 846 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 847 848 mutex_init(&igb->watchdog_lock, NULL, 849 MUTEX_DRIVER, DDI_INTR_PRI(igb->intr_pri)); 850 } 851 852 /* 853 * igb_destroy_locks - Destroy locks 854 */ 855 static void 856 igb_destroy_locks(igb_t *igb) 857 { 858 igb_rx_ring_t *rx_ring; 859 igb_tx_ring_t *tx_ring; 860 int i; 861 862 for (i = 0; i < igb->num_rx_rings; i++) { 863 rx_ring = &igb->rx_rings[i]; 864 mutex_destroy(&rx_ring->rx_lock); 865 mutex_destroy(&rx_ring->recycle_lock); 866 } 867 868 for (i = 0; i < igb->num_tx_rings; i++) { 869 tx_ring = &igb->tx_rings[i]; 870 mutex_destroy(&tx_ring->tx_lock); 871 mutex_destroy(&tx_ring->recycle_lock); 872 mutex_destroy(&tx_ring->tcb_head_lock); 873 mutex_destroy(&tx_ring->tcb_tail_lock); 874 } 875 876 mutex_destroy(&igb->gen_lock); 877 mutex_destroy(&igb->watchdog_lock); 878 } 879 880 static int 881 igb_resume(dev_info_t *devinfo) 882 { 883 igb_t *igb; 884 885 igb = (igb_t *)ddi_get_driver_private(devinfo); 886 if (igb == NULL) 887 return (DDI_FAILURE); 888 889 mutex_enter(&igb->gen_lock); 890 891 if (igb->igb_state & IGB_STARTED) { 892 if (igb_start(igb) != IGB_SUCCESS) { 893 mutex_exit(&igb->gen_lock); 894 return (DDI_FAILURE); 895 } 896 897 /* 898 * Enable and start the watchdog timer 899 */ 900 igb_enable_watchdog_timer(igb); 901 } 902 903 igb->igb_state &= ~IGB_SUSPENDED; 904 905 mutex_exit(&igb->gen_lock); 906 907 return (DDI_SUCCESS); 908 } 909 910 static int 911 igb_suspend(dev_info_t *devinfo) 912 { 913 igb_t *igb; 914 915 igb = (igb_t *)ddi_get_driver_private(devinfo); 916 if (igb == NULL) 917 return (DDI_FAILURE); 918 919 mutex_enter(&igb->gen_lock); 920 921 igb->igb_state |= IGB_SUSPENDED; 922 923 igb_stop(igb); 924 925 mutex_exit(&igb->gen_lock); 926 927 /* 928 * Disable and stop the watchdog timer 929 */ 930 igb_disable_watchdog_timer(igb); 931 932 return (DDI_SUCCESS); 933 } 934 935 /* 936 * igb_init - Initialize the device 937 */ 938 static int 939 igb_init(igb_t *igb) 940 { 941 struct e1000_hw *hw = &igb->hw; 942 uint32_t pba; 943 uint32_t high_water; 944 945 mutex_enter(&igb->gen_lock); 946 947 /* 948 * Reset chipset to put the hardware in a known state 949 * before we try to do anything with the eeprom 950 */ 951 (void) e1000_reset_hw(hw); 952 953 /* 954 * NVM validation 955 */ 956 if (e1000_validate_nvm_checksum(hw) < 0) { 957 /* 958 * Some PCI-E parts fail the first check due to 959 * the link being in sleep state. Call it again, 960 * if it fails a second time its a real issue. 961 */ 962 if (e1000_validate_nvm_checksum(hw) < 0) { 963 igb_error(igb, 964 "Invalid NVM checksum. Please contact " 965 "the vendor to update the NVM."); 966 goto init_fail; 967 } 968 } 969 970 /* 971 * Set the FIFO size 972 */ 973 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */ 974 E1000_WRITE_REG(hw, E1000_PBA, pba); 975 976 /* 977 * Setup flow control 978 * 979 * These parameters set thresholds for the adapter's generation(Tx) 980 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 981 * settings. Flow control is enabled or disabled in the configuration 982 * file. 983 * High-water mark is set down from the top of the rx fifo (not 984 * sensitive to max_frame_size) and low-water is set just below 985 * high-water mark. 986 * The high water mark must be low enough to fit one full frame above 987 * it in the rx FIFO. Should be the lower of: 988 * 90% of the Rx FIFO size, or the full Rx FIFO size minus one full 989 * frame. 990 */ 991 high_water = min(((pba << 10) * 9 / 10), 992 ((pba << 10) - igb->max_frame_size)); 993 994 hw->fc.high_water = high_water & 0xFFF8; 995 hw->fc.low_water = hw->fc.high_water - 8; 996 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 997 hw->fc.send_xon = B_TRUE; 998 999 /* 1000 * Reset the chipset hardware the second time to validate 1001 * the PBA setting. 1002 */ 1003 (void) e1000_reset_hw(hw); 1004 1005 /* 1006 * Don't wait for auto-negotiation to complete 1007 */ 1008 hw->phy.autoneg_wait_to_complete = B_FALSE; 1009 1010 /* 1011 * Copper options 1012 */ 1013 if (hw->phy.media_type == e1000_media_type_copper) { 1014 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 1015 hw->phy.disable_polarity_correction = B_FALSE; 1016 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 1017 } 1018 1019 /* 1020 * Initialize link settings 1021 */ 1022 (void) igb_setup_link(igb, B_FALSE); 1023 1024 /* 1025 * Initialize the chipset hardware 1026 */ 1027 if (igb_chip_start(igb) != IGB_SUCCESS) { 1028 goto init_fail; 1029 } 1030 1031 mutex_exit(&igb->gen_lock); 1032 return (IGB_SUCCESS); 1033 1034 init_fail: 1035 /* 1036 * Reset PHY if possible 1037 */ 1038 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1039 (void) e1000_phy_hw_reset(hw); 1040 1041 mutex_exit(&igb->gen_lock); 1042 return (IGB_FAILURE); 1043 } 1044 1045 /* 1046 * igb_init_rings - Allocate DMA resources for all rx/tx rings and 1047 * initialize relevant hardware settings. 1048 */ 1049 static int 1050 igb_init_rings(igb_t *igb) 1051 { 1052 int i; 1053 1054 /* 1055 * Allocate buffers for all the rx/tx rings 1056 */ 1057 if (igb_alloc_dma(igb) != IGB_SUCCESS) 1058 return (IGB_FAILURE); 1059 1060 /* 1061 * Setup the rx/tx rings 1062 */ 1063 mutex_enter(&igb->gen_lock); 1064 1065 for (i = 0; i < igb->num_rx_rings; i++) 1066 mutex_enter(&igb->rx_rings[i].rx_lock); 1067 for (i = 0; i < igb->num_tx_rings; i++) 1068 mutex_enter(&igb->tx_rings[i].tx_lock); 1069 1070 igb_setup_rings(igb); 1071 1072 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1073 mutex_exit(&igb->tx_rings[i].tx_lock); 1074 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1075 mutex_exit(&igb->rx_rings[i].rx_lock); 1076 1077 mutex_exit(&igb->gen_lock); 1078 1079 return (IGB_SUCCESS); 1080 } 1081 1082 /* 1083 * igb_fini_rings - Release DMA resources of all rx/tx rings 1084 */ 1085 static void 1086 igb_fini_rings(igb_t *igb) 1087 { 1088 /* 1089 * Release the DMA/memory resources of rx/tx rings 1090 */ 1091 igb_free_dma(igb); 1092 } 1093 1094 /* 1095 * igb_chip_start - Initialize and start the chipset hardware 1096 */ 1097 static int 1098 igb_chip_start(igb_t *igb) 1099 { 1100 struct e1000_hw *hw = &igb->hw; 1101 int i; 1102 1103 ASSERT(mutex_owned(&igb->gen_lock)); 1104 1105 /* 1106 * Get the mac address 1107 * This function should handle SPARC case correctly. 1108 */ 1109 if (!igb_find_mac_address(igb)) { 1110 igb_error(igb, "Failed to get the mac address"); 1111 return (IGB_FAILURE); 1112 } 1113 1114 /* Validate mac address */ 1115 if (!is_valid_mac_addr(hw->mac.addr)) { 1116 igb_error(igb, "Invalid mac address"); 1117 return (IGB_FAILURE); 1118 } 1119 1120 /* Disable wakeup control by default */ 1121 E1000_WRITE_REG(hw, E1000_WUC, 0); 1122 1123 /* 1124 * Configure/Initialize hardware 1125 */ 1126 if (e1000_init_hw(hw) != E1000_SUCCESS) { 1127 igb_error(igb, "Failed to initialize hardware"); 1128 return (IGB_FAILURE); 1129 } 1130 1131 /* 1132 * Make sure driver has control 1133 */ 1134 igb_get_driver_control(hw); 1135 1136 /* 1137 * Setup MSI-X interrupts 1138 */ 1139 if (igb->intr_type == DDI_INTR_TYPE_MSIX) 1140 igb_setup_adapter_msix(igb); 1141 1142 /* 1143 * Initialize unicast addresses. 1144 */ 1145 igb_init_unicst(igb); 1146 1147 /* 1148 * Setup and initialize the mctable structures. 1149 */ 1150 igb_setup_multicst(igb); 1151 1152 /* 1153 * Set interrupt throttling rate 1154 */ 1155 for (i = 0; i < igb->intr_cnt; i++) 1156 E1000_WRITE_REG(hw, E1000_EITR(i), igb->intr_throttling[i]); 1157 1158 /* Enable PCI-E master */ 1159 if (hw->bus.type == e1000_bus_type_pci_express) { 1160 e1000_enable_pciex_master(hw); 1161 } 1162 1163 /* 1164 * Save the state of the phy 1165 */ 1166 igb_get_phy_state(igb); 1167 1168 return (IGB_SUCCESS); 1169 } 1170 1171 /* 1172 * igb_chip_stop - Stop the chipset hardware 1173 */ 1174 static void 1175 igb_chip_stop(igb_t *igb) 1176 { 1177 struct e1000_hw *hw = &igb->hw; 1178 1179 ASSERT(mutex_owned(&igb->gen_lock)); 1180 1181 /* Tell firmware driver is no longer in control */ 1182 igb_release_driver_control(hw); 1183 1184 /* 1185 * Reset the chipset 1186 */ 1187 (void) e1000_reset_hw(hw); 1188 1189 /* 1190 * Reset PHY if possible 1191 */ 1192 if (e1000_check_reset_block(hw) == E1000_SUCCESS) 1193 (void) e1000_phy_hw_reset(hw); 1194 } 1195 1196 /* 1197 * igb_reset - Reset the chipset and restart the driver. 1198 * 1199 * It involves stopping and re-starting the chipset, 1200 * and re-configuring the rx/tx rings. 1201 */ 1202 static int 1203 igb_reset(igb_t *igb) 1204 { 1205 int i; 1206 1207 mutex_enter(&igb->gen_lock); 1208 1209 ASSERT(igb->igb_state & IGB_STARTED); 1210 1211 /* 1212 * Disable the adapter interrupts to stop any rx/tx activities 1213 * before draining pending data and resetting hardware. 1214 */ 1215 igb_disable_adapter_interrupts(igb); 1216 1217 /* 1218 * Drain the pending transmit packets 1219 */ 1220 (void) igb_tx_drain(igb); 1221 1222 for (i = 0; i < igb->num_rx_rings; i++) 1223 mutex_enter(&igb->rx_rings[i].rx_lock); 1224 for (i = 0; i < igb->num_tx_rings; i++) 1225 mutex_enter(&igb->tx_rings[i].tx_lock); 1226 1227 /* 1228 * Stop the chipset hardware 1229 */ 1230 igb_chip_stop(igb); 1231 1232 /* 1233 * Clean the pending tx data/resources 1234 */ 1235 igb_tx_clean(igb); 1236 1237 /* 1238 * Start the chipset hardware 1239 */ 1240 if (igb_chip_start(igb) != IGB_SUCCESS) { 1241 goto reset_failure; 1242 } 1243 1244 /* 1245 * Setup the rx/tx rings 1246 */ 1247 igb_setup_rings(igb); 1248 1249 /* 1250 * Enable adapter interrupts 1251 * The interrupts must be enabled after the driver state is START 1252 */ 1253 igb_enable_adapter_interrupts(igb); 1254 1255 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1256 mutex_exit(&igb->tx_rings[i].tx_lock); 1257 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1258 mutex_exit(&igb->rx_rings[i].rx_lock); 1259 1260 mutex_exit(&igb->gen_lock); 1261 1262 return (IGB_SUCCESS); 1263 1264 reset_failure: 1265 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1266 mutex_exit(&igb->tx_rings[i].tx_lock); 1267 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1268 mutex_exit(&igb->rx_rings[i].rx_lock); 1269 1270 mutex_exit(&igb->gen_lock); 1271 1272 return (IGB_FAILURE); 1273 } 1274 1275 /* 1276 * igb_tx_clean - Clean the pending transmit packets and DMA resources 1277 */ 1278 static void 1279 igb_tx_clean(igb_t *igb) 1280 { 1281 igb_tx_ring_t *tx_ring; 1282 tx_control_block_t *tcb; 1283 link_list_t pending_list; 1284 uint32_t desc_num; 1285 int i, j; 1286 1287 LINK_LIST_INIT(&pending_list); 1288 1289 for (i = 0; i < igb->num_tx_rings; i++) { 1290 tx_ring = &igb->tx_rings[i]; 1291 1292 mutex_enter(&tx_ring->recycle_lock); 1293 1294 /* 1295 * Clean the pending tx data - the pending packets in the 1296 * work_list that have no chances to be transmitted again. 1297 * 1298 * We must ensure the chipset is stopped or the link is down 1299 * before cleaning the transmit packets. 1300 */ 1301 desc_num = 0; 1302 for (j = 0; j < tx_ring->ring_size; j++) { 1303 tcb = tx_ring->work_list[j]; 1304 if (tcb != NULL) { 1305 desc_num += tcb->desc_num; 1306 1307 tx_ring->work_list[j] = NULL; 1308 1309 igb_free_tcb(tcb); 1310 1311 LIST_PUSH_TAIL(&pending_list, &tcb->link); 1312 } 1313 } 1314 1315 if (desc_num > 0) { 1316 atomic_add_32(&tx_ring->tbd_free, desc_num); 1317 ASSERT(tx_ring->tbd_free == tx_ring->ring_size); 1318 1319 /* 1320 * Reset the head and tail pointers of the tbd ring 1321 */ 1322 tx_ring->tbd_head = 0; 1323 tx_ring->tbd_tail = 0; 1324 1325 E1000_WRITE_REG(&igb->hw, E1000_TDH(tx_ring->index), 0); 1326 E1000_WRITE_REG(&igb->hw, E1000_TDT(tx_ring->index), 0); 1327 } 1328 1329 mutex_exit(&tx_ring->recycle_lock); 1330 1331 /* 1332 * Add the tx control blocks in the pending list to 1333 * the free list. 1334 */ 1335 igb_put_free_list(tx_ring, &pending_list); 1336 } 1337 } 1338 1339 /* 1340 * igb_tx_drain - Drain the tx rings to allow pending packets to be transmitted 1341 */ 1342 static boolean_t 1343 igb_tx_drain(igb_t *igb) 1344 { 1345 igb_tx_ring_t *tx_ring; 1346 boolean_t done; 1347 int i, j; 1348 1349 /* 1350 * Wait for a specific time to allow pending tx packets 1351 * to be transmitted. 1352 * 1353 * Check the counter tbd_free to see if transmission is done. 1354 * No lock protection is needed here. 1355 * 1356 * Return B_TRUE if all pending packets have been transmitted; 1357 * Otherwise return B_FALSE; 1358 */ 1359 for (i = 0; i < TX_DRAIN_TIME; i++) { 1360 1361 done = B_TRUE; 1362 for (j = 0; j < igb->num_tx_rings; j++) { 1363 tx_ring = &igb->tx_rings[j]; 1364 done = done && 1365 (tx_ring->tbd_free == tx_ring->ring_size); 1366 } 1367 1368 if (done) 1369 break; 1370 1371 msec_delay(1); 1372 } 1373 1374 return (done); 1375 } 1376 1377 /* 1378 * igb_rx_drain - Wait for all rx buffers to be released by upper layer 1379 */ 1380 static boolean_t 1381 igb_rx_drain(igb_t *igb) 1382 { 1383 igb_rx_ring_t *rx_ring; 1384 boolean_t done; 1385 int i, j; 1386 1387 /* 1388 * Polling the rx free list to check if those rx buffers held by 1389 * the upper layer are released. 1390 * 1391 * Check the counter rcb_free to see if all pending buffers are 1392 * released. No lock protection is needed here. 1393 * 1394 * Return B_TRUE if all pending buffers have been released; 1395 * Otherwise return B_FALSE; 1396 */ 1397 for (i = 0; i < RX_DRAIN_TIME; i++) { 1398 1399 done = B_TRUE; 1400 for (j = 0; j < igb->num_rx_rings; j++) { 1401 rx_ring = &igb->rx_rings[j]; 1402 done = done && 1403 (rx_ring->rcb_free == rx_ring->free_list_size); 1404 } 1405 1406 if (done) 1407 break; 1408 1409 msec_delay(1); 1410 } 1411 1412 return (done); 1413 } 1414 1415 /* 1416 * igb_start - Start the driver/chipset 1417 */ 1418 int 1419 igb_start(igb_t *igb) 1420 { 1421 int i; 1422 1423 ASSERT(mutex_owned(&igb->gen_lock)); 1424 1425 for (i = 0; i < igb->num_rx_rings; i++) 1426 mutex_enter(&igb->rx_rings[i].rx_lock); 1427 for (i = 0; i < igb->num_tx_rings; i++) 1428 mutex_enter(&igb->tx_rings[i].tx_lock); 1429 1430 /* 1431 * Start the chipset hardware 1432 */ 1433 if (igb_chip_start(igb) != IGB_SUCCESS) { 1434 goto start_failure; 1435 } 1436 1437 /* 1438 * Setup the rx/tx rings 1439 */ 1440 igb_setup_rings(igb); 1441 1442 /* 1443 * Enable adapter interrupts 1444 * The interrupts must be enabled after the driver state is START 1445 */ 1446 igb_enable_adapter_interrupts(igb); 1447 1448 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1449 mutex_exit(&igb->tx_rings[i].tx_lock); 1450 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1451 mutex_exit(&igb->rx_rings[i].rx_lock); 1452 1453 return (IGB_SUCCESS); 1454 1455 start_failure: 1456 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1457 mutex_exit(&igb->tx_rings[i].tx_lock); 1458 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1459 mutex_exit(&igb->rx_rings[i].rx_lock); 1460 1461 return (IGB_FAILURE); 1462 } 1463 1464 /* 1465 * igb_stop - Stop the driver/chipset 1466 */ 1467 void 1468 igb_stop(igb_t *igb) 1469 { 1470 int i; 1471 1472 ASSERT(mutex_owned(&igb->gen_lock)); 1473 1474 /* 1475 * Disable the adapter interrupts 1476 */ 1477 igb_disable_adapter_interrupts(igb); 1478 1479 /* 1480 * Drain the pending tx packets 1481 */ 1482 (void) igb_tx_drain(igb); 1483 1484 for (i = 0; i < igb->num_rx_rings; i++) 1485 mutex_enter(&igb->rx_rings[i].rx_lock); 1486 for (i = 0; i < igb->num_tx_rings; i++) 1487 mutex_enter(&igb->tx_rings[i].tx_lock); 1488 1489 /* 1490 * Stop the chipset hardware 1491 */ 1492 igb_chip_stop(igb); 1493 1494 /* 1495 * Clean the pending tx data/resources 1496 */ 1497 igb_tx_clean(igb); 1498 1499 for (i = igb->num_tx_rings - 1; i >= 0; i--) 1500 mutex_exit(&igb->tx_rings[i].tx_lock); 1501 for (i = igb->num_rx_rings - 1; i >= 0; i--) 1502 mutex_exit(&igb->rx_rings[i].rx_lock); 1503 } 1504 1505 /* 1506 * igb_alloc_rings - Allocate memory space for rx/tx rings 1507 */ 1508 static int 1509 igb_alloc_rings(igb_t *igb) 1510 { 1511 /* 1512 * Allocate memory space for rx rings 1513 */ 1514 igb->rx_rings = kmem_zalloc( 1515 sizeof (igb_rx_ring_t) * igb->num_rx_rings, 1516 KM_NOSLEEP); 1517 1518 if (igb->rx_rings == NULL) { 1519 return (IGB_FAILURE); 1520 } 1521 1522 /* 1523 * Allocate memory space for tx rings 1524 */ 1525 igb->tx_rings = kmem_zalloc( 1526 sizeof (igb_tx_ring_t) * igb->num_tx_rings, 1527 KM_NOSLEEP); 1528 1529 if (igb->tx_rings == NULL) { 1530 kmem_free(igb->rx_rings, 1531 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1532 igb->rx_rings = NULL; 1533 return (IGB_FAILURE); 1534 } 1535 1536 return (IGB_SUCCESS); 1537 } 1538 1539 /* 1540 * igb_free_rings - Free the memory space of rx/tx rings. 1541 */ 1542 static void 1543 igb_free_rings(igb_t *igb) 1544 { 1545 if (igb->rx_rings != NULL) { 1546 kmem_free(igb->rx_rings, 1547 sizeof (igb_rx_ring_t) * igb->num_rx_rings); 1548 igb->rx_rings = NULL; 1549 } 1550 1551 if (igb->tx_rings != NULL) { 1552 kmem_free(igb->tx_rings, 1553 sizeof (igb_tx_ring_t) * igb->num_tx_rings); 1554 igb->tx_rings = NULL; 1555 } 1556 } 1557 1558 /* 1559 * igb_setup_rings - Setup rx/tx rings 1560 */ 1561 static void 1562 igb_setup_rings(igb_t *igb) 1563 { 1564 /* 1565 * Setup the rx/tx rings, including the following: 1566 * 1567 * 1. Setup the descriptor ring and the control block buffers; 1568 * 2. Initialize necessary registers for receive/transmit; 1569 * 3. Initialize software pointers/parameters for receive/transmit; 1570 */ 1571 igb_setup_rx(igb); 1572 1573 igb_setup_tx(igb); 1574 } 1575 1576 static void 1577 igb_setup_rx_ring(igb_rx_ring_t *rx_ring) 1578 { 1579 igb_t *igb = rx_ring->igb; 1580 struct e1000_hw *hw = &igb->hw; 1581 rx_control_block_t *rcb; 1582 union e1000_adv_rx_desc *rbd; 1583 uint32_t size; 1584 uint32_t buf_low; 1585 uint32_t buf_high; 1586 uint32_t reg_val; 1587 int i; 1588 1589 ASSERT(mutex_owned(&rx_ring->rx_lock)); 1590 ASSERT(mutex_owned(&igb->gen_lock)); 1591 1592 for (i = 0; i < igb->rx_ring_size; i++) { 1593 rcb = rx_ring->work_list[i]; 1594 rbd = &rx_ring->rbd_ring[i]; 1595 1596 rbd->read.pkt_addr = rcb->rx_buf.dma_address; 1597 rbd->read.hdr_addr = NULL; 1598 } 1599 1600 /* 1601 * Initialize the length register 1602 */ 1603 size = rx_ring->ring_size * sizeof (union e1000_adv_rx_desc); 1604 E1000_WRITE_REG(hw, E1000_RDLEN(rx_ring->index), size); 1605 1606 /* 1607 * Initialize the base address registers 1608 */ 1609 buf_low = (uint32_t)rx_ring->rbd_area.dma_address; 1610 buf_high = (uint32_t)(rx_ring->rbd_area.dma_address >> 32); 1611 E1000_WRITE_REG(hw, E1000_RDBAH(rx_ring->index), buf_high); 1612 E1000_WRITE_REG(hw, E1000_RDBAL(rx_ring->index), buf_low); 1613 1614 /* 1615 * Setup head & tail pointers 1616 */ 1617 E1000_WRITE_REG(hw, E1000_RDT(rx_ring->index), rx_ring->ring_size - 1); 1618 E1000_WRITE_REG(hw, E1000_RDH(rx_ring->index), 0); 1619 1620 rx_ring->rbd_next = 0; 1621 1622 /* 1623 * Note: Considering the case that the chipset is being reset 1624 * and there are still some buffers held by the upper layer, 1625 * we should not reset the values of rcb_head, rcb_tail and 1626 * rcb_free; 1627 */ 1628 if (igb->igb_state == IGB_UNKNOWN) { 1629 rx_ring->rcb_head = 0; 1630 rx_ring->rcb_tail = 0; 1631 rx_ring->rcb_free = rx_ring->free_list_size; 1632 } 1633 1634 /* 1635 * Setup the Receive Descriptor Control Register (RXDCTL) 1636 */ 1637 reg_val = E1000_READ_REG(hw, E1000_RXDCTL(rx_ring->index)); 1638 reg_val |= E1000_RXDCTL_QUEUE_ENABLE; 1639 reg_val &= 0xFFF00000; 1640 reg_val |= 16; /* pthresh */ 1641 reg_val |= 8 << 8; /* hthresh */ 1642 reg_val |= 1 << 16; /* wthresh */ 1643 E1000_WRITE_REG(hw, E1000_RXDCTL(rx_ring->index), reg_val); 1644 1645 /* 1646 * Setup the Split and Replication Receive Control Register. 1647 * Set the rx buffer size and the advanced descriptor type. 1648 */ 1649 reg_val = (igb->rx_buf_size >> E1000_SRRCTL_BSIZEPKT_SHIFT) | 1650 E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 1651 1652 E1000_WRITE_REG(hw, E1000_SRRCTL(rx_ring->index), reg_val); 1653 } 1654 1655 static void 1656 igb_setup_rx(igb_t *igb) 1657 { 1658 igb_rx_ring_t *rx_ring; 1659 struct e1000_hw *hw = &igb->hw; 1660 uint32_t reg_val; 1661 int i; 1662 1663 /* 1664 * Setup the Receive Control Register (RCTL), and ENABLE the 1665 * receiver. The initial configuration is to: Enable the receiver, 1666 * accept broadcasts, discard bad packets (and long packets), 1667 * disable VLAN filter checking, set the receive descriptor 1668 * minimum threshold size to 1/2, and the receive buffer size to 1669 * 2k. 1670 */ 1671 reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ 1672 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 1673 E1000_RCTL_LPE | /* Large Packet Enable bit */ 1674 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 1675 E1000_RCTL_RDMTS_HALF | 1676 E1000_RCTL_SECRC | /* Strip Ethernet CRC */ 1677 E1000_RCTL_LBM_NO; /* Loopback Mode = none */ 1678 1679 E1000_WRITE_REG(hw, E1000_RCTL, reg_val); 1680 1681 /* 1682 * igb_setup_rx_ring must be called after configuring RCTL 1683 */ 1684 for (i = 0; i < igb->num_rx_rings; i++) { 1685 rx_ring = &igb->rx_rings[i]; 1686 igb_setup_rx_ring(rx_ring); 1687 } 1688 1689 /* 1690 * Setup the Rx Long Packet Max Length register 1691 */ 1692 E1000_WRITE_REG(hw, E1000_RLPML, igb->max_frame_size); 1693 1694 /* 1695 * Hardware checksum settings 1696 */ 1697 if (igb->rx_hcksum_enable) { 1698 reg_val = 1699 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum */ 1700 E1000_RXCSUM_IPOFL; /* IP checksum */ 1701 1702 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); 1703 } 1704 1705 /* 1706 * Setup RSS for multiple receive queues 1707 */ 1708 if (igb->num_rx_rings > 1) 1709 igb_setup_rss(igb); 1710 } 1711 1712 static void 1713 igb_setup_tx_ring(igb_tx_ring_t *tx_ring) 1714 { 1715 igb_t *igb = tx_ring->igb; 1716 struct e1000_hw *hw = &igb->hw; 1717 uint32_t size; 1718 uint32_t buf_low; 1719 uint32_t buf_high; 1720 uint32_t reg_val; 1721 1722 ASSERT(mutex_owned(&tx_ring->tx_lock)); 1723 ASSERT(mutex_owned(&igb->gen_lock)); 1724 1725 /* 1726 * Initialize the length register 1727 */ 1728 size = tx_ring->ring_size * sizeof (union e1000_adv_tx_desc); 1729 E1000_WRITE_REG(hw, E1000_TDLEN(tx_ring->index), size); 1730 1731 /* 1732 * Initialize the base address registers 1733 */ 1734 buf_low = (uint32_t)tx_ring->tbd_area.dma_address; 1735 buf_high = (uint32_t)(tx_ring->tbd_area.dma_address >> 32); 1736 E1000_WRITE_REG(hw, E1000_TDBAL(tx_ring->index), buf_low); 1737 E1000_WRITE_REG(hw, E1000_TDBAH(tx_ring->index), buf_high); 1738 1739 /* 1740 * Setup head & tail pointers 1741 */ 1742 E1000_WRITE_REG(hw, E1000_TDH(tx_ring->index), 0); 1743 E1000_WRITE_REG(hw, E1000_TDT(tx_ring->index), 0); 1744 1745 /* 1746 * Setup head write-back 1747 */ 1748 if (igb->tx_head_wb_enable) { 1749 /* 1750 * The memory of the head write-back is allocated using 1751 * the extra tbd beyond the tail of the tbd ring. 1752 */ 1753 tx_ring->tbd_head_wb = (uint32_t *) 1754 ((uintptr_t)tx_ring->tbd_area.address + size); 1755 1756 buf_low = (uint32_t) 1757 (tx_ring->tbd_area.dma_address + size); 1758 buf_high = (uint32_t) 1759 ((tx_ring->tbd_area.dma_address + size) >> 32); 1760 1761 /* Set the head write-back enable bit */ 1762 buf_low |= E1000_TX_HEAD_WB_ENABLE; 1763 1764 E1000_WRITE_REG(hw, E1000_TDWBAL(tx_ring->index), buf_low); 1765 E1000_WRITE_REG(hw, E1000_TDWBAH(tx_ring->index), buf_high); 1766 1767 /* 1768 * Turn off relaxed ordering for head write back or it will 1769 * cause problems with the tx recycling 1770 */ 1771 reg_val = E1000_READ_REG(hw, 1772 E1000_DCA_TXCTRL(tx_ring->index)); 1773 reg_val &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN; 1774 E1000_WRITE_REG(hw, 1775 E1000_DCA_TXCTRL(tx_ring->index), reg_val); 1776 } else { 1777 tx_ring->tbd_head_wb = NULL; 1778 } 1779 1780 tx_ring->tbd_head = 0; 1781 tx_ring->tbd_tail = 0; 1782 tx_ring->tbd_free = tx_ring->ring_size; 1783 1784 /* 1785 * Note: Considering the case that the chipset is being reset, 1786 * and there are still some buffers held by the upper layer, 1787 * we should not reset the values of tcb_head, tcb_tail. 1788 */ 1789 if (igb->igb_state == IGB_UNKNOWN) { 1790 tx_ring->tcb_head = 0; 1791 tx_ring->tcb_tail = 0; 1792 tx_ring->tcb_free = tx_ring->free_list_size; 1793 } else { 1794 ASSERT(tx_ring->tcb_free == tx_ring->free_list_size); 1795 } 1796 1797 /* 1798 * Initialize hardware checksum offload settings 1799 */ 1800 tx_ring->hcksum_context.hcksum_flags = 0; 1801 tx_ring->hcksum_context.ip_hdr_len = 0; 1802 tx_ring->hcksum_context.mac_hdr_len = 0; 1803 tx_ring->hcksum_context.l4_proto = 0; 1804 } 1805 1806 static void 1807 igb_setup_tx(igb_t *igb) 1808 { 1809 igb_tx_ring_t *tx_ring; 1810 struct e1000_hw *hw = &igb->hw; 1811 uint32_t reg_val; 1812 int i; 1813 1814 for (i = 0; i < igb->num_tx_rings; i++) { 1815 tx_ring = &igb->tx_rings[i]; 1816 igb_setup_tx_ring(tx_ring); 1817 } 1818 1819 /* 1820 * Setup the Transmit Control Register (TCTL) 1821 */ 1822 reg_val = E1000_TCTL_PSP | E1000_TCTL_EN | 1823 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 1824 (E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT) | 1825 E1000_TCTL_RTLC; 1826 1827 /* Enable the MULR bit */ 1828 if (hw->bus.type == e1000_bus_type_pci_express) 1829 reg_val |= E1000_TCTL_MULR; 1830 1831 E1000_WRITE_REG(hw, E1000_TCTL, reg_val); 1832 1833 /* 1834 * Set the default values for the Tx Inter Packet Gap timer 1835 */ 1836 if (hw->phy.media_type == e1000_media_type_fiber) 1837 reg_val = DEFAULT_82543_TIPG_IPGT_FIBER; 1838 else 1839 reg_val = DEFAULT_82543_TIPG_IPGT_COPPER; 1840 reg_val |= 1841 DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT; 1842 reg_val |= 1843 DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT; 1844 1845 E1000_WRITE_REG(hw, E1000_TIPG, reg_val); 1846 } 1847 1848 /* 1849 * igb_setup_rss - Setup receive-side scaling feature 1850 */ 1851 static void 1852 igb_setup_rss(igb_t *igb) 1853 { 1854 struct e1000_hw *hw = &igb->hw; 1855 uint32_t i, mrqc, rxcsum; 1856 int shift; 1857 uint32_t random; 1858 union e1000_reta { 1859 uint32_t dword; 1860 uint8_t bytes[4]; 1861 } reta; 1862 1863 /* Setup the Redirection Table */ 1864 shift = 6; 1865 for (i = 0; i < (32 * 4); i++) { 1866 reta.bytes[i & 3] = (i % igb->num_rx_rings) << shift; 1867 if ((i & 3) == 3) { 1868 E1000_WRITE_REG(hw, 1869 (E1000_RETA(0) + (i & ~3)), reta.dword); 1870 } 1871 } 1872 1873 /* Fill out hash function seeds */ 1874 for (i = 0; i < 10; i++) { 1875 (void) random_get_pseudo_bytes((uint8_t *)&random, 1876 sizeof (uint32_t)); 1877 E1000_WRITE_REG(hw, E1000_RSSRK(i), random); 1878 } 1879 1880 /* Setup the Multiple Receive Queue Control register */ 1881 mrqc = E1000_MRQC_ENABLE_RSS_4Q; 1882 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 | 1883 E1000_MRQC_RSS_FIELD_IPV4_TCP | 1884 E1000_MRQC_RSS_FIELD_IPV6 | 1885 E1000_MRQC_RSS_FIELD_IPV6_TCP | 1886 E1000_MRQC_RSS_FIELD_IPV4_UDP | 1887 E1000_MRQC_RSS_FIELD_IPV6_UDP | 1888 E1000_MRQC_RSS_FIELD_IPV6_UDP_EX | 1889 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); 1890 1891 E1000_WRITE_REG(hw, E1000_MRQC, mrqc); 1892 1893 /* 1894 * Disable Packet Checksum to enable RSS for multiple receive queues. 1895 * 1896 * The Packet Checksum is not ethernet CRC. It is another kind of 1897 * checksum offloading provided by the 82575 chipset besides the IP 1898 * header checksum offloading and the TCP/UDP checksum offloading. 1899 * The Packet Checksum is by default computed over the entire packet 1900 * from the first byte of the DA through the last byte of the CRC, 1901 * including the Ethernet and IP headers. 1902 * 1903 * It is a hardware limitation that Packet Checksum is mutually 1904 * exclusive with RSS. 1905 */ 1906 rxcsum = E1000_READ_REG(hw, E1000_RXCSUM); 1907 rxcsum |= E1000_RXCSUM_PCSD; 1908 E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum); 1909 } 1910 1911 /* 1912 * igb_init_unicst - Initialize the unicast addresses 1913 */ 1914 static void 1915 igb_init_unicst(igb_t *igb) 1916 { 1917 struct e1000_hw *hw = &igb->hw; 1918 int slot; 1919 1920 /* 1921 * Here we should consider two situations: 1922 * 1923 * 1. Chipset is initialized the first time 1924 * Initialize the multiple unicast addresses, and 1925 * save the default mac address. 1926 * 1927 * 2. Chipset is reset 1928 * Recover the multiple unicast addresses from the 1929 * software data structure to the RAR registers. 1930 */ 1931 if (!igb->unicst_init) { 1932 /* Initialize the multiple unicast addresses */ 1933 igb->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1934 1935 igb->unicst_avail = igb->unicst_total - 1; 1936 1937 /* Store the default mac address */ 1938 e1000_rar_set(hw, hw->mac.addr, 0); 1939 1940 bcopy(hw->mac.addr, igb->unicst_addr[0].mac.addr, 1941 ETHERADDRL); 1942 igb->unicst_addr[0].mac.set = 1; 1943 1944 for (slot = 1; slot < igb->unicst_total; slot++) 1945 igb->unicst_addr[slot].mac.set = 0; 1946 1947 igb->unicst_init = B_TRUE; 1948 } else { 1949 /* Recover the default mac address */ 1950 bcopy(igb->unicst_addr[0].mac.addr, hw->mac.addr, 1951 ETHERADDRL); 1952 1953 /* Store the default mac address */ 1954 e1000_rar_set(hw, hw->mac.addr, 0); 1955 1956 /* Re-configure the RAR registers */ 1957 for (slot = 1; slot < igb->unicst_total; slot++) 1958 e1000_rar_set(hw, 1959 igb->unicst_addr[slot].mac.addr, slot); 1960 } 1961 } 1962 1963 /* 1964 * igb_unicst_set - Set the unicast address to the specified slot 1965 */ 1966 int 1967 igb_unicst_set(igb_t *igb, const uint8_t *mac_addr, 1968 mac_addr_slot_t slot) 1969 { 1970 struct e1000_hw *hw = &igb->hw; 1971 1972 ASSERT(mutex_owned(&igb->gen_lock)); 1973 1974 /* 1975 * Save the unicast address in the software data structure 1976 */ 1977 bcopy(mac_addr, igb->unicst_addr[slot].mac.addr, ETHERADDRL); 1978 1979 /* 1980 * Set the unicast address to the RAR register 1981 */ 1982 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 1983 1984 return (0); 1985 } 1986 1987 /* 1988 * igb_multicst_add - Add a multicst address 1989 */ 1990 int 1991 igb_multicst_add(igb_t *igb, const uint8_t *multiaddr) 1992 { 1993 ASSERT(mutex_owned(&igb->gen_lock)); 1994 1995 if ((multiaddr[0] & 01) == 0) { 1996 return (EINVAL); 1997 } 1998 1999 if (igb->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2000 return (ENOENT); 2001 } 2002 2003 bcopy(multiaddr, 2004 &igb->mcast_table[igb->mcast_count], ETHERADDRL); 2005 igb->mcast_count++; 2006 2007 /* 2008 * Update the multicast table in the hardware 2009 */ 2010 igb_setup_multicst(igb); 2011 2012 return (0); 2013 } 2014 2015 /* 2016 * igb_multicst_remove - Remove a multicst address 2017 */ 2018 int 2019 igb_multicst_remove(igb_t *igb, const uint8_t *multiaddr) 2020 { 2021 int i; 2022 2023 ASSERT(mutex_owned(&igb->gen_lock)); 2024 2025 for (i = 0; i < igb->mcast_count; i++) { 2026 if (bcmp(multiaddr, &igb->mcast_table[i], 2027 ETHERADDRL) == 0) { 2028 for (i++; i < igb->mcast_count; i++) { 2029 igb->mcast_table[i - 1] = 2030 igb->mcast_table[i]; 2031 } 2032 igb->mcast_count--; 2033 break; 2034 } 2035 } 2036 2037 /* 2038 * Update the multicast table in the hardware 2039 */ 2040 igb_setup_multicst(igb); 2041 2042 return (0); 2043 } 2044 2045 /* 2046 * igb_setup_multicast - setup multicast data structures 2047 * 2048 * This routine initializes all of the multicast related structures 2049 * and save them in the hardware registers. 2050 */ 2051 static void 2052 igb_setup_multicst(igb_t *igb) 2053 { 2054 uint8_t *mc_addr_list; 2055 uint32_t mc_addr_count; 2056 struct e1000_hw *hw = &igb->hw; 2057 2058 ASSERT(mutex_owned(&igb->gen_lock)); 2059 2060 ASSERT(igb->mcast_count <= MAX_NUM_MULTICAST_ADDRESSES); 2061 2062 mc_addr_list = (uint8_t *)igb->mcast_table; 2063 mc_addr_count = igb->mcast_count; 2064 2065 /* 2066 * Update the multicase addresses to the MTA registers 2067 */ 2068 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2069 igb->unicst_total, hw->mac.rar_entry_count); 2070 } 2071 2072 /* 2073 * igb_get_conf - Get driver configurations set in driver.conf 2074 * 2075 * This routine gets user-configured values out of the configuration 2076 * file igb.conf. 2077 * 2078 * For each configurable value, there is a minimum, a maximum, and a 2079 * default. 2080 * If user does not configure a value, use the default. 2081 * If user configures below the minimum, use the minumum. 2082 * If user configures above the maximum, use the maxumum. 2083 */ 2084 static void 2085 igb_get_conf(igb_t *igb) 2086 { 2087 struct e1000_hw *hw = &igb->hw; 2088 uint32_t default_mtu; 2089 uint32_t flow_control; 2090 2091 /* 2092 * igb driver supports the following user configurations: 2093 * 2094 * Link configurations: 2095 * adv_autoneg_cap 2096 * adv_1000fdx_cap 2097 * adv_100fdx_cap 2098 * adv_100hdx_cap 2099 * adv_10fdx_cap 2100 * adv_10hdx_cap 2101 * Note: 1000hdx is not supported. 2102 * 2103 * Jumbo frame configuration: 2104 * default_mtu 2105 * 2106 * Ethernet flow control configuration: 2107 * flow_control 2108 * 2109 * Multiple rings configurations: 2110 * tx_queue_number 2111 * tx_ring_size 2112 * rx_queue_number 2113 * rx_ring_size 2114 * 2115 * Call igb_get_prop() to get the value for a specific 2116 * configuration parameter. 2117 */ 2118 2119 /* 2120 * Link configurations 2121 */ 2122 igb->param_adv_autoneg_cap = igb_get_prop(igb, 2123 PROP_ADV_AUTONEG_CAP, 0, 1, 1); 2124 igb->param_adv_1000fdx_cap = igb_get_prop(igb, 2125 PROP_ADV_1000FDX_CAP, 0, 1, 1); 2126 igb->param_adv_100fdx_cap = igb_get_prop(igb, 2127 PROP_ADV_100FDX_CAP, 0, 1, 1); 2128 igb->param_adv_100hdx_cap = igb_get_prop(igb, 2129 PROP_ADV_100HDX_CAP, 0, 1, 1); 2130 igb->param_adv_10fdx_cap = igb_get_prop(igb, 2131 PROP_ADV_10FDX_CAP, 0, 1, 1); 2132 igb->param_adv_10hdx_cap = igb_get_prop(igb, 2133 PROP_ADV_10HDX_CAP, 0, 1, 1); 2134 2135 /* 2136 * Jumbo frame configurations 2137 */ 2138 default_mtu = igb_get_prop(igb, PROP_DEFAULT_MTU, 2139 MIN_MTU, MAX_MTU, DEFAULT_MTU); 2140 2141 igb->max_frame_size = default_mtu + 2142 sizeof (struct ether_vlan_header) + ETHERFCSL; 2143 2144 /* 2145 * Ethernet flow control configuration 2146 */ 2147 flow_control = igb_get_prop(igb, PROP_FLOW_CONTROL, 2148 e1000_fc_none, 4, e1000_fc_full); 2149 if (flow_control == 4) 2150 flow_control = e1000_fc_default; 2151 2152 hw->fc.type = flow_control; 2153 2154 /* 2155 * Multiple rings configurations 2156 */ 2157 igb->num_tx_rings = igb_get_prop(igb, PROP_TX_QUEUE_NUM, 2158 MIN_TX_QUEUE_NUM, MAX_TX_QUEUE_NUM, DEFAULT_TX_QUEUE_NUM); 2159 igb->tx_ring_size = igb_get_prop(igb, PROP_TX_RING_SIZE, 2160 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE, DEFAULT_TX_RING_SIZE); 2161 2162 igb->num_rx_rings = igb_get_prop(igb, PROP_RX_QUEUE_NUM, 2163 MIN_RX_QUEUE_NUM, MAX_RX_QUEUE_NUM, DEFAULT_RX_QUEUE_NUM); 2164 igb->rx_ring_size = igb_get_prop(igb, PROP_RX_RING_SIZE, 2165 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE, DEFAULT_RX_RING_SIZE); 2166 2167 /* 2168 * Tunable used to force an interrupt type. The only use is 2169 * for testing of the lesser interrupt types. 2170 * 0 = don't force interrupt type 2171 * 1 = force interrupt type MSIX 2172 * 2 = force interrupt type MSI 2173 * 3 = force interrupt type Legacy 2174 */ 2175 igb->intr_force = igb_get_prop(igb, PROP_INTR_FORCE, 2176 IGB_INTR_NONE, IGB_INTR_LEGACY, IGB_INTR_NONE); 2177 2178 igb->tx_hcksum_enable = igb_get_prop(igb, PROP_TX_HCKSUM_ENABLE, 2179 0, 1, 1); 2180 igb->rx_hcksum_enable = igb_get_prop(igb, PROP_RX_HCKSUM_ENABLE, 2181 0, 1, 1); 2182 igb->lso_enable = igb_get_prop(igb, PROP_LSO_ENABLE, 2183 0, 1, 0); 2184 igb->tx_head_wb_enable = igb_get_prop(igb, PROP_TX_HEAD_WB_ENABLE, 2185 0, 1, 1); 2186 2187 igb->tx_copy_thresh = igb_get_prop(igb, PROP_TX_COPY_THRESHOLD, 2188 MIN_TX_COPY_THRESHOLD, MAX_TX_COPY_THRESHOLD, 2189 DEFAULT_TX_COPY_THRESHOLD); 2190 igb->tx_recycle_thresh = igb_get_prop(igb, PROP_TX_RECYCLE_THRESHOLD, 2191 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 2192 DEFAULT_TX_RECYCLE_THRESHOLD); 2193 igb->tx_overload_thresh = igb_get_prop(igb, PROP_TX_OVERLOAD_THRESHOLD, 2194 MIN_TX_OVERLOAD_THRESHOLD, MAX_TX_OVERLOAD_THRESHOLD, 2195 DEFAULT_TX_OVERLOAD_THRESHOLD); 2196 igb->tx_resched_thresh = igb_get_prop(igb, PROP_TX_RESCHED_THRESHOLD, 2197 MIN_TX_RESCHED_THRESHOLD, MAX_TX_RESCHED_THRESHOLD, 2198 DEFAULT_TX_RESCHED_THRESHOLD); 2199 2200 igb->rx_copy_thresh = igb_get_prop(igb, PROP_RX_COPY_THRESHOLD, 2201 MIN_RX_COPY_THRESHOLD, MAX_RX_COPY_THRESHOLD, 2202 DEFAULT_RX_COPY_THRESHOLD); 2203 igb->rx_limit_per_intr = igb_get_prop(igb, PROP_RX_LIMIT_PER_INTR, 2204 MIN_RX_LIMIT_PER_INTR, MAX_RX_LIMIT_PER_INTR, 2205 DEFAULT_RX_LIMIT_PER_INTR); 2206 2207 igb->intr_throttling[0] = igb_get_prop(igb, PROP_INTR_THROTTLING, 2208 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 2209 DEFAULT_INTR_THROTTLING); 2210 } 2211 2212 /* 2213 * igb_get_prop - Get a property value out of the configuration file igb.conf 2214 * 2215 * Caller provides the name of the property, a default value, a minimum 2216 * value, and a maximum value. 2217 * 2218 * Return configured value of the property, with default, minimum and 2219 * maximum properly applied. 2220 */ 2221 static int 2222 igb_get_prop(igb_t *igb, 2223 char *propname, /* name of the property */ 2224 int minval, /* minimum acceptable value */ 2225 int maxval, /* maximim acceptable value */ 2226 int defval) /* default value */ 2227 { 2228 int value; 2229 2230 /* 2231 * Call ddi_prop_get_int() to read the conf settings 2232 */ 2233 value = ddi_prop_get_int(DDI_DEV_T_ANY, igb->dip, 2234 DDI_PROP_DONTPASS, propname, defval); 2235 2236 if (value > maxval) 2237 value = maxval; 2238 2239 if (value < minval) 2240 value = minval; 2241 2242 return (value); 2243 } 2244 2245 /* 2246 * igb_setup_link - Using the link properties to setup the link 2247 */ 2248 int 2249 igb_setup_link(igb_t *igb, boolean_t setup_hw) 2250 { 2251 struct e1000_mac_info *mac; 2252 struct e1000_phy_info *phy; 2253 boolean_t invalid; 2254 2255 mac = &igb->hw.mac; 2256 phy = &igb->hw.phy; 2257 invalid = B_FALSE; 2258 2259 if (igb->param_adv_autoneg_cap == 1) { 2260 mac->autoneg = B_TRUE; 2261 phy->autoneg_advertised = 0; 2262 2263 /* 2264 * 1000hdx is not supported for autonegotiation 2265 */ 2266 if (igb->param_adv_1000fdx_cap == 1) 2267 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 2268 2269 if (igb->param_adv_100fdx_cap == 1) 2270 phy->autoneg_advertised |= ADVERTISE_100_FULL; 2271 2272 if (igb->param_adv_100hdx_cap == 1) 2273 phy->autoneg_advertised |= ADVERTISE_100_HALF; 2274 2275 if (igb->param_adv_10fdx_cap == 1) 2276 phy->autoneg_advertised |= ADVERTISE_10_FULL; 2277 2278 if (igb->param_adv_10hdx_cap == 1) 2279 phy->autoneg_advertised |= ADVERTISE_10_HALF; 2280 2281 if (phy->autoneg_advertised == 0) 2282 invalid = B_TRUE; 2283 } else { 2284 mac->autoneg = B_FALSE; 2285 2286 /* 2287 * 1000fdx and 1000hdx are not supported for forced link 2288 */ 2289 if (igb->param_adv_100fdx_cap == 1) 2290 mac->forced_speed_duplex = ADVERTISE_100_FULL; 2291 else if (igb->param_adv_100hdx_cap == 1) 2292 mac->forced_speed_duplex = ADVERTISE_100_HALF; 2293 else if (igb->param_adv_10fdx_cap == 1) 2294 mac->forced_speed_duplex = ADVERTISE_10_FULL; 2295 else if (igb->param_adv_10hdx_cap == 1) 2296 mac->forced_speed_duplex = ADVERTISE_10_HALF; 2297 else 2298 invalid = B_TRUE; 2299 } 2300 2301 if (invalid) { 2302 igb_notice(igb, "Invalid link settings. Setup link to " 2303 "autonegotiation with full link capabilities."); 2304 mac->autoneg = B_TRUE; 2305 phy->autoneg_advertised = ADVERTISE_1000_FULL | 2306 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 2307 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 2308 } 2309 2310 if (setup_hw) { 2311 if (e1000_setup_link(&igb->hw) != E1000_SUCCESS) 2312 return (IGB_FAILURE); 2313 } 2314 2315 return (IGB_SUCCESS); 2316 } 2317 2318 2319 /* 2320 * igb_is_link_up - Check if the link is up 2321 */ 2322 static boolean_t 2323 igb_is_link_up(igb_t *igb) 2324 { 2325 struct e1000_hw *hw = &igb->hw; 2326 boolean_t link_up; 2327 2328 ASSERT(mutex_owned(&igb->gen_lock)); 2329 2330 (void) e1000_check_for_link(hw); 2331 2332 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 2333 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 2334 (hw->mac.serdes_has_link))) { 2335 link_up = B_TRUE; 2336 } else { 2337 link_up = B_FALSE; 2338 } 2339 2340 return (link_up); 2341 } 2342 2343 /* 2344 * igb_link_check - Link status processing 2345 */ 2346 static boolean_t 2347 igb_link_check(igb_t *igb) 2348 { 2349 struct e1000_hw *hw = &igb->hw; 2350 uint16_t speed = 0, duplex = 0; 2351 boolean_t link_changed = B_FALSE; 2352 2353 ASSERT(mutex_owned(&igb->gen_lock)); 2354 2355 if (igb_is_link_up(igb)) { 2356 /* 2357 * The Link is up, check whether it was marked as down earlier 2358 */ 2359 if (igb->link_state != LINK_STATE_UP) { 2360 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 2361 igb->link_speed = speed; 2362 igb->link_duplex = duplex; 2363 igb->link_state = LINK_STATE_UP; 2364 igb->link_down_timeout = 0; 2365 link_changed = B_TRUE; 2366 } 2367 } else { 2368 if (igb->link_state != LINK_STATE_DOWN) { 2369 igb->link_speed = 0; 2370 igb->link_duplex = 0; 2371 igb->link_state = LINK_STATE_DOWN; 2372 link_changed = B_TRUE; 2373 } 2374 2375 if (igb->igb_state & IGB_STARTED) { 2376 if (igb->link_down_timeout < MAX_LINK_DOWN_TIMEOUT) { 2377 igb->link_down_timeout++; 2378 } else if (igb->link_down_timeout == 2379 MAX_LINK_DOWN_TIMEOUT) { 2380 igb_tx_clean(igb); 2381 igb->link_down_timeout++; 2382 } 2383 } 2384 } 2385 2386 return (link_changed); 2387 } 2388 2389 /* 2390 * igb_local_timer - driver watchdog function 2391 * 2392 * This function will handle the transmit stall check, link status check and 2393 * other routines. 2394 */ 2395 static void 2396 igb_local_timer(void *arg) 2397 { 2398 igb_t *igb = (igb_t *)arg; 2399 struct e1000_hw *hw = &igb->hw; 2400 boolean_t link_changed; 2401 2402 if (igb_stall_check(igb)) { 2403 igb->reset_count++; 2404 (void) igb_reset(igb); 2405 } 2406 2407 mutex_enter(&igb->gen_lock); 2408 link_changed = igb_link_check(igb); 2409 mutex_exit(&igb->gen_lock); 2410 2411 if (link_changed) 2412 mac_link_update(igb->mac_hdl, igb->link_state); 2413 2414 /* 2415 * Set Timer Interrupts 2416 */ 2417 if (igb->intr_type != DDI_INTR_TYPE_MSIX) 2418 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2419 2420 igb_restart_watchdog_timer(igb); 2421 } 2422 2423 /* 2424 * igb_stall_check - check for transmit stall 2425 * 2426 * This function checks if the adapter is stalled (in transmit). 2427 * 2428 * It is called each time the watchdog timeout is invoked. 2429 * If the transmit descriptor reclaim continuously fails, 2430 * the watchdog value will increment by 1. If the watchdog 2431 * value exceeds the threshold, the igb is assumed to 2432 * have stalled and need to be reset. 2433 */ 2434 static boolean_t 2435 igb_stall_check(igb_t *igb) 2436 { 2437 igb_tx_ring_t *tx_ring; 2438 boolean_t result; 2439 int i; 2440 2441 if (igb->link_state != LINK_STATE_UP) 2442 return (B_FALSE); 2443 2444 /* 2445 * If any tx ring is stalled, we'll reset the chipset 2446 */ 2447 result = B_FALSE; 2448 for (i = 0; i < igb->num_tx_rings; i++) { 2449 tx_ring = &igb->tx_rings[i]; 2450 2451 if (tx_ring->recycle_fail > 0) 2452 tx_ring->stall_watchdog++; 2453 else 2454 tx_ring->stall_watchdog = 0; 2455 2456 if (tx_ring->stall_watchdog >= STALL_WATCHDOG_TIMEOUT) { 2457 result = B_TRUE; 2458 break; 2459 } 2460 } 2461 2462 if (result) { 2463 tx_ring->stall_watchdog = 0; 2464 tx_ring->recycle_fail = 0; 2465 } 2466 2467 return (result); 2468 } 2469 2470 2471 /* 2472 * is_valid_mac_addr - Check if the mac address is valid 2473 */ 2474 static boolean_t 2475 is_valid_mac_addr(uint8_t *mac_addr) 2476 { 2477 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 2478 const uint8_t addr_test2[6] = 2479 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 2480 2481 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 2482 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 2483 return (B_FALSE); 2484 2485 return (B_TRUE); 2486 } 2487 2488 static boolean_t 2489 igb_find_mac_address(igb_t *igb) 2490 { 2491 struct e1000_hw *hw = &igb->hw; 2492 #ifdef __sparc 2493 uchar_t *bytes; 2494 struct ether_addr sysaddr; 2495 uint_t nelts; 2496 int err; 2497 boolean_t found = B_FALSE; 2498 2499 /* 2500 * The "vendor's factory-set address" may already have 2501 * been extracted from the chip, but if the property 2502 * "local-mac-address" is set we use that instead. 2503 * 2504 * We check whether it looks like an array of 6 2505 * bytes (which it should, if OBP set it). If we can't 2506 * make sense of it this way, we'll ignore it. 2507 */ 2508 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2509 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 2510 if (err == DDI_PROP_SUCCESS) { 2511 if (nelts == ETHERADDRL) { 2512 while (nelts--) 2513 hw->mac.addr[nelts] = bytes[nelts]; 2514 found = B_TRUE; 2515 } 2516 ddi_prop_free(bytes); 2517 } 2518 2519 /* 2520 * Look up the OBP property "local-mac-address?". If the user has set 2521 * 'local-mac-address? = false', use "the system address" instead. 2522 */ 2523 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 0, 2524 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 2525 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 2526 if (localetheraddr(NULL, &sysaddr) != 0) { 2527 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 2528 found = B_TRUE; 2529 } 2530 } 2531 ddi_prop_free(bytes); 2532 } 2533 2534 /* 2535 * Finally(!), if there's a valid "mac-address" property (created 2536 * if we netbooted from this interface), we must use this instead 2537 * of any of the above to ensure that the NFS/install server doesn't 2538 * get confused by the address changing as Solaris takes over! 2539 */ 2540 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, igb->dip, 2541 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 2542 if (err == DDI_PROP_SUCCESS) { 2543 if (nelts == ETHERADDRL) { 2544 while (nelts--) 2545 hw->mac.addr[nelts] = bytes[nelts]; 2546 found = B_TRUE; 2547 } 2548 ddi_prop_free(bytes); 2549 } 2550 2551 if (found) { 2552 bcopy(hw->mac.addr, hw->mac.perm_addr, ETHERADDRL); 2553 return (B_TRUE); 2554 } 2555 #endif 2556 2557 /* 2558 * Read the device MAC address from the EEPROM 2559 */ 2560 if (e1000_read_mac_addr(hw) != E1000_SUCCESS) 2561 return (B_FALSE); 2562 2563 return (B_TRUE); 2564 } 2565 2566 #pragma inline(igb_arm_watchdog_timer) 2567 2568 static void 2569 igb_arm_watchdog_timer(igb_t *igb) 2570 { 2571 /* 2572 * Fire a watchdog timer 2573 */ 2574 igb->watchdog_tid = 2575 timeout(igb_local_timer, 2576 (void *)igb, 1 * drv_usectohz(1000000)); 2577 2578 } 2579 2580 /* 2581 * igb_enable_watchdog_timer - Enable and start the driver watchdog timer 2582 */ 2583 void 2584 igb_enable_watchdog_timer(igb_t *igb) 2585 { 2586 mutex_enter(&igb->watchdog_lock); 2587 2588 if (!igb->watchdog_enable) { 2589 igb->watchdog_enable = B_TRUE; 2590 igb->watchdog_start = B_TRUE; 2591 igb_arm_watchdog_timer(igb); 2592 } 2593 2594 mutex_exit(&igb->watchdog_lock); 2595 2596 } 2597 2598 /* 2599 * igb_disable_watchdog_timer - Disable and stop the driver watchdog timer 2600 */ 2601 void 2602 igb_disable_watchdog_timer(igb_t *igb) 2603 { 2604 timeout_id_t tid; 2605 2606 mutex_enter(&igb->watchdog_lock); 2607 2608 igb->watchdog_enable = B_FALSE; 2609 igb->watchdog_start = B_FALSE; 2610 tid = igb->watchdog_tid; 2611 igb->watchdog_tid = 0; 2612 2613 mutex_exit(&igb->watchdog_lock); 2614 2615 if (tid != 0) 2616 (void) untimeout(tid); 2617 2618 } 2619 2620 /* 2621 * igb_start_watchdog_timer - Start the driver watchdog timer 2622 */ 2623 static void 2624 igb_start_watchdog_timer(igb_t *igb) 2625 { 2626 mutex_enter(&igb->watchdog_lock); 2627 2628 if (igb->watchdog_enable) { 2629 if (!igb->watchdog_start) { 2630 igb->watchdog_start = B_TRUE; 2631 igb_arm_watchdog_timer(igb); 2632 } 2633 } 2634 2635 mutex_exit(&igb->watchdog_lock); 2636 } 2637 2638 /* 2639 * igb_restart_watchdog_timer - Restart the driver watchdog timer 2640 */ 2641 static void 2642 igb_restart_watchdog_timer(igb_t *igb) 2643 { 2644 mutex_enter(&igb->watchdog_lock); 2645 2646 if (igb->watchdog_start) 2647 igb_arm_watchdog_timer(igb); 2648 2649 mutex_exit(&igb->watchdog_lock); 2650 } 2651 2652 /* 2653 * igb_stop_watchdog_timer - Stop the driver watchdog timer 2654 */ 2655 static void 2656 igb_stop_watchdog_timer(igb_t *igb) 2657 { 2658 timeout_id_t tid; 2659 2660 mutex_enter(&igb->watchdog_lock); 2661 2662 igb->watchdog_start = B_FALSE; 2663 tid = igb->watchdog_tid; 2664 igb->watchdog_tid = 0; 2665 2666 mutex_exit(&igb->watchdog_lock); 2667 2668 if (tid != 0) 2669 (void) untimeout(tid); 2670 } 2671 2672 /* 2673 * igb_disable_adapter_interrupts - Clear/disable all hardware interrupts 2674 */ 2675 static void 2676 igb_disable_adapter_interrupts(igb_t *igb) 2677 { 2678 struct e1000_hw *hw = &igb->hw; 2679 2680 /* 2681 * Set the IMC register to mask all the interrupts, 2682 * including the tx interrupts. 2683 */ 2684 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 2685 2686 /* 2687 * Additional disabling for MSI-X 2688 */ 2689 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2690 E1000_WRITE_REG(hw, E1000_EIMC, 0xffffffff); 2691 E1000_WRITE_REG(hw, E1000_EIAC, 0x0); 2692 } 2693 2694 E1000_WRITE_FLUSH(hw); 2695 } 2696 2697 /* 2698 * igb_enable_adapter_interrupts - Mask/enable all hardware interrupts 2699 */ 2700 static void 2701 igb_enable_adapter_interrupts(igb_t *igb) 2702 { 2703 struct e1000_hw *hw = &igb->hw; 2704 uint32_t reg; 2705 2706 if (igb->intr_type == DDI_INTR_TYPE_MSIX) { 2707 /* Interrupt enabling for MSI-X */ 2708 E1000_WRITE_REG(hw, E1000_EIMS, igb->eims_mask); 2709 E1000_WRITE_REG(hw, E1000_EIAC, igb->eims_mask); 2710 E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC); 2711 2712 /* Enable MSI-X PBA support */ 2713 reg = E1000_READ_REG(hw, E1000_CTRL_EXT); 2714 reg |= E1000_CTRL_EXT_PBA_CLR; 2715 2716 /* Non-selective interrupt clear-on-read */ 2717 reg |= E1000_CTRL_EXT_IRCA; /* Called NSICR in the EAS */ 2718 2719 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg); 2720 } else { 2721 /* Interrupt enabling for MSI and legacy */ 2722 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK); 2723 } 2724 2725 E1000_WRITE_FLUSH(hw); 2726 } 2727 2728 /* 2729 * Loopback Support 2730 */ 2731 static lb_property_t lb_normal = 2732 { normal, "normal", IGB_LB_NONE }; 2733 static lb_property_t lb_external = 2734 { external, "External", IGB_LB_EXTERNAL }; 2735 static lb_property_t lb_mac = 2736 { internal, "MAC", IGB_LB_INTERNAL_MAC }; 2737 static lb_property_t lb_phy = 2738 { internal, "PHY", IGB_LB_INTERNAL_PHY }; 2739 static lb_property_t lb_serdes = 2740 { internal, "SerDes", IGB_LB_INTERNAL_SERDES }; 2741 2742 enum ioc_reply 2743 igb_loopback_ioctl(igb_t *igb, struct iocblk *iocp, mblk_t *mp) 2744 { 2745 lb_info_sz_t *lbsp; 2746 lb_property_t *lbpp; 2747 struct e1000_hw *hw; 2748 uint32_t *lbmp; 2749 uint32_t size; 2750 uint32_t value; 2751 2752 hw = &igb->hw; 2753 2754 if (mp->b_cont == NULL) 2755 return (IOC_INVAL); 2756 2757 switch (iocp->ioc_cmd) { 2758 default: 2759 return (IOC_INVAL); 2760 2761 case LB_GET_INFO_SIZE: 2762 size = sizeof (lb_info_sz_t); 2763 if (iocp->ioc_count != size) 2764 return (IOC_INVAL); 2765 2766 value = sizeof (lb_normal); 2767 value += sizeof (lb_mac); 2768 if (hw->phy.media_type == e1000_media_type_copper) 2769 value += sizeof (lb_phy); 2770 else 2771 value += sizeof (lb_serdes); 2772 value += sizeof (lb_external); 2773 2774 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 2775 *lbsp = value; 2776 break; 2777 2778 case LB_GET_INFO: 2779 value = sizeof (lb_normal); 2780 value += sizeof (lb_mac); 2781 if (hw->phy.media_type == e1000_media_type_copper) 2782 value += sizeof (lb_phy); 2783 else 2784 value += sizeof (lb_serdes); 2785 value += sizeof (lb_external); 2786 2787 size = value; 2788 if (iocp->ioc_count != size) 2789 return (IOC_INVAL); 2790 2791 value = 0; 2792 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 2793 2794 lbpp[value++] = lb_normal; 2795 lbpp[value++] = lb_mac; 2796 if (hw->phy.media_type == e1000_media_type_copper) 2797 lbpp[value++] = lb_phy; 2798 else 2799 lbpp[value++] = lb_serdes; 2800 lbpp[value++] = lb_external; 2801 break; 2802 2803 case LB_GET_MODE: 2804 size = sizeof (uint32_t); 2805 if (iocp->ioc_count != size) 2806 return (IOC_INVAL); 2807 2808 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2809 *lbmp = igb->loopback_mode; 2810 break; 2811 2812 case LB_SET_MODE: 2813 size = 0; 2814 if (iocp->ioc_count != sizeof (uint32_t)) 2815 return (IOC_INVAL); 2816 2817 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 2818 if (!igb_set_loopback_mode(igb, *lbmp)) 2819 return (IOC_INVAL); 2820 break; 2821 } 2822 2823 iocp->ioc_count = size; 2824 iocp->ioc_error = 0; 2825 2826 return (IOC_REPLY); 2827 } 2828 2829 /* 2830 * igb_set_loopback_mode - Setup loopback based on the loopback mode 2831 */ 2832 static boolean_t 2833 igb_set_loopback_mode(igb_t *igb, uint32_t mode) 2834 { 2835 struct e1000_hw *hw; 2836 2837 if (mode == igb->loopback_mode) 2838 return (B_TRUE); 2839 2840 hw = &igb->hw; 2841 2842 igb->loopback_mode = mode; 2843 2844 if (mode == IGB_LB_NONE) { 2845 /* Reset the chip */ 2846 hw->phy.autoneg_wait_to_complete = B_TRUE; 2847 (void) igb_reset(igb); 2848 hw->phy.autoneg_wait_to_complete = B_FALSE; 2849 return (B_TRUE); 2850 } 2851 2852 mutex_enter(&igb->gen_lock); 2853 2854 switch (mode) { 2855 default: 2856 mutex_exit(&igb->gen_lock); 2857 return (B_FALSE); 2858 2859 case IGB_LB_EXTERNAL: 2860 igb_set_external_loopback(igb); 2861 break; 2862 2863 case IGB_LB_INTERNAL_MAC: 2864 igb_set_internal_mac_loopback(igb); 2865 break; 2866 2867 case IGB_LB_INTERNAL_PHY: 2868 igb_set_internal_phy_loopback(igb); 2869 break; 2870 2871 case IGB_LB_INTERNAL_SERDES: 2872 igb_set_internal_serdes_loopback(igb); 2873 break; 2874 } 2875 2876 mutex_exit(&igb->gen_lock); 2877 2878 return (B_TRUE); 2879 } 2880 2881 /* 2882 * igb_set_external_loopback - Set the external loopback mode 2883 */ 2884 static void 2885 igb_set_external_loopback(igb_t *igb) 2886 { 2887 struct e1000_hw *hw; 2888 2889 hw = &igb->hw; 2890 2891 /* Set phy to known state */ 2892 (void) e1000_phy_hw_reset(hw); 2893 2894 (void) e1000_write_phy_reg(hw, 0x0, 0x0140); 2895 (void) e1000_write_phy_reg(hw, 0x9, 0x1b00); 2896 (void) e1000_write_phy_reg(hw, 0x12, 0x1610); 2897 (void) e1000_write_phy_reg(hw, 0x1f37, 0x3f1c); 2898 } 2899 2900 /* 2901 * igb_set_internal_mac_loopback - Set the internal MAC loopback mode 2902 */ 2903 static void 2904 igb_set_internal_mac_loopback(igb_t *igb) 2905 { 2906 struct e1000_hw *hw; 2907 uint32_t ctrl; 2908 uint32_t rctl; 2909 2910 hw = &igb->hw; 2911 2912 /* Set the Receive Control register */ 2913 rctl = E1000_READ_REG(hw, E1000_RCTL); 2914 rctl &= ~E1000_RCTL_LBM_TCVR; 2915 rctl |= E1000_RCTL_LBM_MAC; 2916 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2917 2918 /* Set the Device Control register */ 2919 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2920 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 2921 ctrl |= (E1000_CTRL_SLU | /* Force link up */ 2922 E1000_CTRL_FRCSPD | /* Force speed */ 2923 E1000_CTRL_FRCDPX | /* Force duplex */ 2924 E1000_CTRL_SPD_1000 | /* Force speed to 1000 */ 2925 E1000_CTRL_FD); /* Force full duplex */ 2926 ctrl &= ~E1000_CTRL_ILOS; /* Clear ILOS when there's a link */ 2927 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2928 } 2929 2930 /* 2931 * igb_set_internal_phy_loopback - Set the internal PHY loopback mode 2932 */ 2933 static void 2934 igb_set_internal_phy_loopback(igb_t *igb) 2935 { 2936 struct e1000_hw *hw; 2937 uint32_t ctrl_ext; 2938 uint16_t phy_ctrl; 2939 uint16_t phy_pconf; 2940 2941 hw = &igb->hw; 2942 2943 /* Set link mode to PHY (00b) in the Extended Control register */ 2944 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2945 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK; 2946 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2947 2948 /* 2949 * Set PHY control register (0x4140): 2950 * Set full duplex mode 2951 * Set loopback bit 2952 * Clear auto-neg enable bit 2953 * Set PHY speed 2954 */ 2955 phy_ctrl = MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000 | MII_CR_LOOPBACK; 2956 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 2957 2958 /* Set the link disable bit in the Port Configuration register */ 2959 (void) e1000_read_phy_reg(hw, 0x10, &phy_pconf); 2960 phy_pconf |= (uint16_t)1 << 14; 2961 (void) e1000_write_phy_reg(hw, 0x10, phy_pconf); 2962 } 2963 2964 /* 2965 * igb_set_internal_serdes_loopback - Set the internal SerDes loopback mode 2966 */ 2967 static void 2968 igb_set_internal_serdes_loopback(igb_t *igb) 2969 { 2970 struct e1000_hw *hw; 2971 uint32_t ctrl_ext; 2972 uint32_t ctrl; 2973 uint32_t pcs_lctl; 2974 uint32_t connsw; 2975 2976 hw = &igb->hw; 2977 2978 /* Set link mode to SerDes (11b) in the Extended Control register */ 2979 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 2980 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 2981 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 2982 2983 /* Configure the SerDes to loopback */ 2984 E1000_WRITE_REG(hw, E1000_SCTL, 0x410); 2985 2986 /* Set Device Control register */ 2987 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2988 ctrl |= (E1000_CTRL_FD | /* Force full duplex */ 2989 E1000_CTRL_SLU); /* Force link up */ 2990 ctrl &= ~(E1000_CTRL_RFCE | /* Disable receive flow control */ 2991 E1000_CTRL_TFCE | /* Disable transmit flow control */ 2992 E1000_CTRL_LRST); /* Clear link reset */ 2993 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2994 2995 /* Set PCS Link Control register */ 2996 pcs_lctl = E1000_READ_REG(hw, E1000_PCS_LCTL); 2997 pcs_lctl |= (E1000_PCS_LCTL_FORCE_LINK | 2998 E1000_PCS_LCTL_FSD | 2999 E1000_PCS_LCTL_FDV_FULL | 3000 E1000_PCS_LCTL_FLV_LINK_UP); 3001 pcs_lctl &= ~E1000_PCS_LCTL_AN_ENABLE; 3002 E1000_WRITE_REG(hw, E1000_PCS_LCTL, pcs_lctl); 3003 3004 /* Set the Copper/Fiber Switch Control - CONNSW register */ 3005 connsw = E1000_READ_REG(hw, E1000_CONNSW); 3006 connsw &= ~E1000_CONNSW_ENRGSRC; 3007 E1000_WRITE_REG(hw, E1000_CONNSW, connsw); 3008 } 3009 3010 #pragma inline(igb_intr_rx_work) 3011 /* 3012 * igb_intr_rx_work - rx processing of ISR 3013 */ 3014 static void 3015 igb_intr_rx_work(igb_rx_ring_t *rx_ring) 3016 { 3017 mblk_t *mp; 3018 3019 mutex_enter(&rx_ring->rx_lock); 3020 mp = igb_rx(rx_ring); 3021 mutex_exit(&rx_ring->rx_lock); 3022 3023 if (mp != NULL) 3024 mac_rx(rx_ring->igb->mac_hdl, NULL, mp); 3025 } 3026 3027 #pragma inline(igb_intr_tx_work) 3028 /* 3029 * igb_intr_tx_work - tx processing of ISR 3030 */ 3031 static void 3032 igb_intr_tx_work(igb_tx_ring_t *tx_ring) 3033 { 3034 /* Recycle the tx descriptors */ 3035 tx_ring->tx_recycle(tx_ring); 3036 3037 /* Schedule the re-transmit */ 3038 if (tx_ring->reschedule && 3039 (tx_ring->tbd_free >= tx_ring->resched_thresh)) { 3040 tx_ring->reschedule = B_FALSE; 3041 mac_tx_update(tx_ring->igb->mac_hdl); 3042 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3043 } 3044 } 3045 3046 #pragma inline(igb_intr_other_work) 3047 /* 3048 * igb_intr_other_work - other processing of ISR 3049 */ 3050 static void 3051 igb_intr_other_work(igb_t *igb) 3052 { 3053 boolean_t link_changed; 3054 3055 igb_stop_watchdog_timer(igb); 3056 3057 mutex_enter(&igb->gen_lock); 3058 3059 /* 3060 * Because we got a link-status-change interrupt, force 3061 * e1000_check_for_link() to look at phy 3062 */ 3063 igb->hw.mac.get_link_status = B_TRUE; 3064 3065 /* igb_link_check takes care of link status change */ 3066 link_changed = igb_link_check(igb); 3067 3068 /* Get new phy state */ 3069 igb_get_phy_state(igb); 3070 3071 mutex_exit(&igb->gen_lock); 3072 3073 if (link_changed) 3074 mac_link_update(igb->mac_hdl, igb->link_state); 3075 3076 igb_start_watchdog_timer(igb); 3077 } 3078 3079 /* 3080 * igb_intr_legacy - Interrupt handler for legacy interrupts 3081 */ 3082 static uint_t 3083 igb_intr_legacy(void *arg1, void *arg2) 3084 { 3085 igb_t *igb = (igb_t *)arg1; 3086 igb_tx_ring_t *tx_ring; 3087 uint32_t icr; 3088 mblk_t *mp; 3089 boolean_t tx_reschedule; 3090 boolean_t link_changed; 3091 uint_t result; 3092 3093 _NOTE(ARGUNUSED(arg2)); 3094 3095 mutex_enter(&igb->gen_lock); 3096 3097 if (igb->igb_state & IGB_SUSPENDED) { 3098 mutex_exit(&igb->gen_lock); 3099 return (DDI_INTR_UNCLAIMED); 3100 } 3101 3102 mp = NULL; 3103 tx_reschedule = B_FALSE; 3104 link_changed = B_FALSE; 3105 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3106 3107 if (icr & E1000_ICR_INT_ASSERTED) { 3108 /* 3109 * E1000_ICR_INT_ASSERTED bit was set: 3110 * Read(Clear) the ICR, claim this interrupt, 3111 * look for work to do. 3112 */ 3113 ASSERT(igb->num_rx_rings == 1); 3114 ASSERT(igb->num_tx_rings == 1); 3115 3116 if (icr & E1000_ICR_RXT0) { 3117 mp = igb_rx(&igb->rx_rings[0]); 3118 } 3119 3120 if (icr & E1000_ICR_TXDW) { 3121 tx_ring = &igb->tx_rings[0]; 3122 3123 /* Recycle the tx descriptors */ 3124 tx_ring->tx_recycle(tx_ring); 3125 3126 /* Schedule the re-transmit */ 3127 tx_reschedule = (tx_ring->reschedule && 3128 (tx_ring->tbd_free >= tx_ring->resched_thresh)); 3129 } 3130 3131 if (icr & E1000_ICR_LSC) { 3132 /* 3133 * Because we got a link-status-change interrupt, force 3134 * e1000_check_for_link() to look at phy 3135 */ 3136 igb->hw.mac.get_link_status = B_TRUE; 3137 3138 /* igb_link_check takes care of link status change */ 3139 link_changed = igb_link_check(igb); 3140 3141 /* Get new phy state */ 3142 igb_get_phy_state(igb); 3143 } 3144 3145 result = DDI_INTR_CLAIMED; 3146 } else { 3147 /* 3148 * E1000_ICR_INT_ASSERTED bit was not set: 3149 * Don't claim this interrupt. 3150 */ 3151 result = DDI_INTR_UNCLAIMED; 3152 } 3153 3154 mutex_exit(&igb->gen_lock); 3155 3156 /* 3157 * Do the following work outside of the gen_lock 3158 */ 3159 if (mp != NULL) 3160 mac_rx(igb->mac_hdl, NULL, mp); 3161 3162 if (tx_reschedule) { 3163 tx_ring->reschedule = B_FALSE; 3164 mac_tx_update(igb->mac_hdl); 3165 IGB_DEBUG_STAT(tx_ring->stat_reschedule); 3166 } 3167 3168 if (link_changed) 3169 mac_link_update(igb->mac_hdl, igb->link_state); 3170 3171 return (result); 3172 } 3173 3174 /* 3175 * igb_intr_msi - Interrupt handler for MSI 3176 */ 3177 static uint_t 3178 igb_intr_msi(void *arg1, void *arg2) 3179 { 3180 igb_t *igb = (igb_t *)arg1; 3181 uint32_t icr; 3182 3183 _NOTE(ARGUNUSED(arg2)); 3184 3185 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3186 3187 /* 3188 * For MSI interrupt, we have only one vector, 3189 * so we have only one rx ring and one tx ring enabled. 3190 */ 3191 ASSERT(igb->num_rx_rings == 1); 3192 ASSERT(igb->num_tx_rings == 1); 3193 3194 if (icr & E1000_ICR_RXT0) { 3195 igb_intr_rx_work(&igb->rx_rings[0]); 3196 } 3197 3198 if (icr & E1000_ICR_TXDW) { 3199 igb_intr_tx_work(&igb->tx_rings[0]); 3200 } 3201 3202 if (icr & E1000_ICR_LSC) { 3203 igb_intr_other_work(igb); 3204 } 3205 3206 return (DDI_INTR_CLAIMED); 3207 } 3208 3209 /* 3210 * igb_intr_rx - Interrupt handler for rx 3211 */ 3212 static uint_t 3213 igb_intr_rx(void *arg1, void *arg2) 3214 { 3215 igb_rx_ring_t *rx_ring = (igb_rx_ring_t *)arg1; 3216 3217 _NOTE(ARGUNUSED(arg2)); 3218 3219 /* 3220 * Only used via MSI-X vector so don't check cause bits 3221 * and only clean the given ring. 3222 */ 3223 igb_intr_rx_work(rx_ring); 3224 3225 return (DDI_INTR_CLAIMED); 3226 } 3227 3228 /* 3229 * igb_intr_tx_other - Interrupt handler for both tx and other 3230 * 3231 * Always look for Tx cleanup work. Only look for other work if the right 3232 * bits are set in the Interrupt Cause Register. 3233 */ 3234 static uint_t 3235 igb_intr_tx_other(void *arg1, void *arg2) 3236 { 3237 igb_t *igb = (igb_t *)arg1; 3238 uint32_t icr; 3239 3240 _NOTE(ARGUNUSED(arg2)); 3241 3242 icr = E1000_READ_REG(&igb->hw, E1000_ICR); 3243 3244 /* 3245 * Always look for Tx cleanup work. We don't have separate 3246 * transmit vectors, so we have only one tx ring enabled. 3247 */ 3248 ASSERT(igb->num_tx_rings == 1); 3249 igb_intr_tx_work(&igb->tx_rings[0]); 3250 3251 /* 3252 * Check for "other" causes. 3253 */ 3254 if (icr & E1000_ICR_LSC) { 3255 igb_intr_other_work(igb); 3256 } 3257 3258 return (DDI_INTR_CLAIMED); 3259 } 3260 3261 /* 3262 * igb_alloc_intrs - Allocate interrupts for the driver 3263 * 3264 * Normal sequence is to try MSI-X; if not sucessful, try MSI; 3265 * if not successful, try Legacy. 3266 * igb->intr_force can be used to force sequence to start with 3267 * any of the 3 types. 3268 * If MSI-X is not used, number of tx/rx rings is forced to 1. 3269 */ 3270 static int 3271 igb_alloc_intrs(igb_t *igb) 3272 { 3273 dev_info_t *devinfo; 3274 int intr_types; 3275 int rc; 3276 3277 devinfo = igb->dip; 3278 3279 /* Get supported interrupt types */ 3280 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3281 3282 if (rc != DDI_SUCCESS) { 3283 igb_log(igb, 3284 "Get supported interrupt types failed: %d", rc); 3285 return (IGB_FAILURE); 3286 } 3287 IGB_DEBUGLOG_1(igb, "Supported interrupt types: %x", intr_types); 3288 3289 igb->intr_type = 0; 3290 3291 /* Install MSI-X interrupts */ 3292 if ((intr_types & DDI_INTR_TYPE_MSIX) && 3293 (igb->intr_force <= IGB_INTR_MSIX)) { 3294 rc = igb_alloc_intrs_msix(igb); 3295 3296 if (rc == IGB_SUCCESS) 3297 return (IGB_SUCCESS); 3298 3299 igb_log(igb, 3300 "Allocate MSI-X failed, trying MSI interrupts..."); 3301 } 3302 3303 /* MSI-X not used, force rings to 1 */ 3304 igb->num_rx_rings = 1; 3305 igb->num_tx_rings = 1; 3306 igb_log(igb, 3307 "MSI-X not used, force rx and tx queue number to 1"); 3308 3309 /* Install MSI interrupts */ 3310 if ((intr_types & DDI_INTR_TYPE_MSI) && 3311 (igb->intr_force <= IGB_INTR_MSI)) { 3312 rc = igb_alloc_intrs_msi(igb); 3313 3314 if (rc == IGB_SUCCESS) 3315 return (IGB_SUCCESS); 3316 3317 igb_log(igb, 3318 "Allocate MSI failed, trying Legacy interrupts..."); 3319 } 3320 3321 /* Install legacy interrupts */ 3322 if (intr_types & DDI_INTR_TYPE_FIXED) { 3323 rc = igb_alloc_intrs_legacy(igb); 3324 3325 if (rc == IGB_SUCCESS) 3326 return (IGB_SUCCESS); 3327 3328 igb_log(igb, 3329 "Allocate Legacy interrupts failed"); 3330 } 3331 3332 /* If none of the 3 types succeeded, return failure */ 3333 return (IGB_FAILURE); 3334 } 3335 3336 /* 3337 * igb_alloc_intrs_msix - Allocate the MSIX interrupts 3338 * 3339 * If fewer than 2 vectors are available, return failure. 3340 * Upon success, this sets the number of Rx rings to a number that 3341 * matches the vectors available for Rx interrupts. 3342 */ 3343 static int 3344 igb_alloc_intrs_msix(igb_t *igb) 3345 { 3346 dev_info_t *devinfo; 3347 int request, count, avail, actual; 3348 int rx_rings; 3349 int rc; 3350 3351 devinfo = igb->dip; 3352 3353 /* 3354 * Currently only 1 tx ring is supported. More tx rings 3355 * will be supported with future enhancement. 3356 */ 3357 if (igb->num_tx_rings > 1) { 3358 igb->num_tx_rings = 1; 3359 igb_log(igb, 3360 "Use only 1 MSI-X vector for tx, " 3361 "force tx queue number to 1"); 3362 } 3363 3364 /* 3365 * Best number of vectors for the adapter is 3366 * # rx rings + # tx rings + 1 for other 3367 * But currently we only support number of vectors of 3368 * # rx rings + 1 for tx & other 3369 */ 3370 request = igb->num_rx_rings + 1; 3371 IGB_DEBUGLOG_1(igb, "MSI-X interrupts requested: %d", request); 3372 3373 /* Get number of supported interrupts */ 3374 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSIX, &count); 3375 if ((rc != DDI_SUCCESS) || (count == 0)) { 3376 igb_log(igb, 3377 "Get interrupt number failed. Return: %d, count: %d", 3378 rc, count); 3379 return (IGB_FAILURE); 3380 } 3381 IGB_DEBUGLOG_1(igb, "MSI-X interrupts supported: %d", count); 3382 3383 /* Get number of available interrupts */ 3384 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSIX, &avail); 3385 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3386 igb_log(igb, 3387 "Get interrupt available number failed. " 3388 "Return: %d, available: %d", rc, avail); 3389 return (IGB_FAILURE); 3390 } 3391 IGB_DEBUGLOG_1(igb, "MSI-X interrupts available: %d", avail); 3392 3393 if (avail < request) { 3394 igb_log(igb, 3395 "Request %d MSI-X vectors, %d available", 3396 request, avail); 3397 request = avail; 3398 } 3399 3400 actual = 0; 3401 igb->intr_cnt = 0; 3402 3403 /* Allocate an array of interrupt handles */ 3404 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3405 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3406 3407 /* Call ddi_intr_alloc() */ 3408 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_MSIX, 0, 3409 request, &actual, DDI_INTR_ALLOC_NORMAL); 3410 if (rc != DDI_SUCCESS) { 3411 igb_log(igb, "Allocate MSI-X interrupts failed. " 3412 "return: %d, request: %d, actual: %d", 3413 rc, request, actual); 3414 goto alloc_msix_fail; 3415 } 3416 IGB_DEBUGLOG_1(igb, "MSI-X interrupts actually allocated: %d", actual); 3417 3418 igb->intr_cnt = actual; 3419 3420 /* 3421 * Now we know the actual number of vectors. Here we assume that 3422 * tx and other will share 1 vector and all remaining (must be at 3423 * least 1 remaining) will be used for rx. 3424 */ 3425 if (actual < 2) { 3426 igb_log(igb, "Insufficient MSI-X interrupts available: %d", 3427 actual); 3428 goto alloc_msix_fail; 3429 } 3430 3431 rx_rings = actual - 1; 3432 if (rx_rings < igb->num_rx_rings) { 3433 igb_log(igb, "MSI-X vectors force Rx queue number to %d", 3434 rx_rings); 3435 igb->num_rx_rings = rx_rings; 3436 } 3437 3438 /* Get priority for first vector, assume remaining are all the same */ 3439 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3440 if (rc != DDI_SUCCESS) { 3441 igb_log(igb, 3442 "Get interrupt priority failed: %d", rc); 3443 goto alloc_msix_fail; 3444 } 3445 3446 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3447 if (rc != DDI_SUCCESS) { 3448 igb_log(igb, 3449 "Get interrupt cap failed: %d", rc); 3450 goto alloc_msix_fail; 3451 } 3452 3453 igb->intr_type = DDI_INTR_TYPE_MSIX; 3454 3455 return (IGB_SUCCESS); 3456 3457 alloc_msix_fail: 3458 igb_rem_intrs(igb); 3459 3460 return (IGB_FAILURE); 3461 } 3462 3463 /* 3464 * igb_alloc_intrs_msi - Allocate the MSI interrupts 3465 */ 3466 static int 3467 igb_alloc_intrs_msi(igb_t *igb) 3468 { 3469 dev_info_t *devinfo; 3470 int request, count, avail, actual; 3471 int rc; 3472 3473 devinfo = igb->dip; 3474 3475 /* Request 1 MSI interrupt vector */ 3476 request = 1; 3477 IGB_DEBUGLOG_1(igb, "MSI interrupts requested: %d", request); 3478 3479 /* Get number of supported interrupts */ 3480 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSI, &count); 3481 if ((rc != DDI_SUCCESS) || (count == 0)) { 3482 igb_log(igb, 3483 "Get MSI supported number failed. Return: %d, count: %d", 3484 rc, count); 3485 return (IGB_FAILURE); 3486 } 3487 IGB_DEBUGLOG_1(igb, "MSI interrupts supported: %d", count); 3488 3489 /* Get number of available interrupts */ 3490 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSI, &avail); 3491 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3492 igb_log(igb, 3493 "Get MSI available number failed. " 3494 "Return: %d, available: %d", rc, avail); 3495 return (IGB_FAILURE); 3496 } 3497 IGB_DEBUGLOG_1(igb, "MSI interrupts available: %d", avail); 3498 3499 actual = 0; 3500 igb->intr_cnt = 0; 3501 3502 /* Allocate an array of interrupt handles */ 3503 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3504 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3505 3506 /* Call ddi_intr_alloc() */ 3507 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_MSI, 0, 3508 request, &actual, DDI_INTR_ALLOC_NORMAL); 3509 if ((rc != DDI_SUCCESS) || (actual == 0)) { 3510 igb_log(igb, 3511 "Allocate MSI interrupts failed: %d", rc); 3512 goto alloc_msi_fail; 3513 } 3514 3515 ASSERT(actual == 1); 3516 igb->intr_cnt = actual; 3517 3518 /* Get priority for first msi, assume remaining are all the same */ 3519 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3520 if (rc != DDI_SUCCESS) { 3521 igb_log(igb, 3522 "Get interrupt priority failed: %d", rc); 3523 goto alloc_msi_fail; 3524 } 3525 3526 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3527 if (rc != DDI_SUCCESS) { 3528 igb_log(igb, 3529 "Get interrupt cap failed: %d\n", rc); 3530 goto alloc_msi_fail; 3531 3532 } 3533 3534 igb->intr_type = DDI_INTR_TYPE_MSI; 3535 3536 return (IGB_SUCCESS); 3537 3538 alloc_msi_fail: 3539 igb_rem_intrs(igb); 3540 3541 return (IGB_FAILURE); 3542 } 3543 3544 /* 3545 * igb_alloc_intrs_legacy - Allocate the Legacy interrupts 3546 */ 3547 static int 3548 igb_alloc_intrs_legacy(igb_t *igb) 3549 { 3550 dev_info_t *devinfo; 3551 int request, count, avail, actual; 3552 int rc; 3553 3554 devinfo = igb->dip; 3555 3556 /* Request 1 Legacy interrupt vector */ 3557 request = 1; 3558 IGB_DEBUGLOG_1(igb, "Legacy interrupts requested: %d", request); 3559 3560 /* Get number of supported interrupts */ 3561 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &count); 3562 if ((rc != DDI_SUCCESS) || (count == 0)) { 3563 igb_log(igb, 3564 "Get Legacy supported number failed. Return: %d, count: %d", 3565 rc, count); 3566 return (IGB_FAILURE); 3567 } 3568 IGB_DEBUGLOG_1(igb, "Legacy interrupts supported: %d", count); 3569 3570 /* Get number of available interrupts */ 3571 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_FIXED, &avail); 3572 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3573 igb_log(igb, 3574 "Get Legacy available number failed. " 3575 "Return: %d, available: %d", rc, avail); 3576 return (IGB_FAILURE); 3577 } 3578 IGB_DEBUGLOG_1(igb, "Legacy interrupts available: %d", avail); 3579 3580 actual = 0; 3581 igb->intr_cnt = 0; 3582 3583 /* Allocate an array of interrupt handles */ 3584 igb->intr_size = request * sizeof (ddi_intr_handle_t); 3585 igb->htable = kmem_alloc(igb->intr_size, KM_SLEEP); 3586 3587 /* Call ddi_intr_alloc() */ 3588 rc = ddi_intr_alloc(devinfo, igb->htable, DDI_INTR_TYPE_FIXED, 0, 3589 request, &actual, DDI_INTR_ALLOC_NORMAL); 3590 if ((rc != DDI_SUCCESS) || (actual == 0)) { 3591 igb_log(igb, 3592 "Allocate Legacy interrupts failed: %d", rc); 3593 goto alloc_legacy_fail; 3594 } 3595 3596 ASSERT(actual == 1); 3597 igb->intr_cnt = actual; 3598 3599 /* Get priority for first msi, assume remaining are all the same */ 3600 rc = ddi_intr_get_pri(igb->htable[0], &igb->intr_pri); 3601 if (rc != DDI_SUCCESS) { 3602 igb_log(igb, 3603 "Get interrupt priority failed: %d", rc); 3604 goto alloc_legacy_fail; 3605 } 3606 3607 rc = ddi_intr_get_cap(igb->htable[0], &igb->intr_cap); 3608 if (rc != DDI_SUCCESS) { 3609 igb_log(igb, 3610 "Get interrupt cap failed: %d\n", rc); 3611 goto alloc_legacy_fail; 3612 } 3613 3614 igb->intr_type = DDI_INTR_TYPE_FIXED; 3615 3616 return (IGB_SUCCESS); 3617 3618 alloc_legacy_fail: 3619 igb_rem_intrs(igb); 3620 3621 return (IGB_FAILURE); 3622 } 3623 3624 /* 3625 * igb_add_intr_handlers - Add interrupt handlers based on the interrupt type 3626 * 3627 * Before adding the interrupt handlers, the interrupt vectors have 3628 * been allocated, and the rx/tx rings have also been allocated. 3629 */ 3630 static int 3631 igb_add_intr_handlers(igb_t *igb) 3632 { 3633 igb_rx_ring_t *rx_ring; 3634 int vector; 3635 int rc; 3636 int i; 3637 3638 vector = 0; 3639 3640 switch (igb->intr_type) { 3641 case DDI_INTR_TYPE_MSIX: 3642 /* Add interrupt handler for tx + other */ 3643 rc = ddi_intr_add_handler(igb->htable[vector], 3644 (ddi_intr_handler_t *)igb_intr_tx_other, 3645 (void *)igb, NULL); 3646 if (rc != DDI_SUCCESS) { 3647 igb_log(igb, 3648 "Add tx/other interrupt handler failed: %d", rc); 3649 return (IGB_FAILURE); 3650 } 3651 vector++; 3652 3653 /* Add interrupt handler for each rx ring */ 3654 for (i = 0; i < igb->num_rx_rings; i++) { 3655 rx_ring = &igb->rx_rings[i]; 3656 3657 rc = ddi_intr_add_handler(igb->htable[vector], 3658 (ddi_intr_handler_t *)igb_intr_rx, 3659 (void *)rx_ring, NULL); 3660 3661 if (rc != DDI_SUCCESS) { 3662 igb_log(igb, 3663 "Add rx interrupt handler failed. " 3664 "return: %d, rx ring: %d", rc, i); 3665 for (vector--; vector >= 0; vector--) { 3666 (void) ddi_intr_remove_handler( 3667 igb->htable[vector]); 3668 } 3669 return (IGB_FAILURE); 3670 } 3671 3672 rx_ring->intr_vector = vector; 3673 3674 vector++; 3675 } 3676 break; 3677 3678 case DDI_INTR_TYPE_MSI: 3679 /* Add interrupt handlers for the only vector */ 3680 rc = ddi_intr_add_handler(igb->htable[vector], 3681 (ddi_intr_handler_t *)igb_intr_msi, 3682 (void *)igb, NULL); 3683 3684 if (rc != DDI_SUCCESS) { 3685 igb_log(igb, 3686 "Add MSI interrupt handler failed: %d", rc); 3687 return (IGB_FAILURE); 3688 } 3689 3690 rx_ring = &igb->rx_rings[0]; 3691 rx_ring->intr_vector = vector; 3692 3693 vector++; 3694 break; 3695 3696 case DDI_INTR_TYPE_FIXED: 3697 /* Add interrupt handlers for the only vector */ 3698 rc = ddi_intr_add_handler(igb->htable[vector], 3699 (ddi_intr_handler_t *)igb_intr_legacy, 3700 (void *)igb, NULL); 3701 3702 if (rc != DDI_SUCCESS) { 3703 igb_log(igb, 3704 "Add legacy interrupt handler failed: %d", rc); 3705 return (IGB_FAILURE); 3706 } 3707 3708 rx_ring = &igb->rx_rings[0]; 3709 rx_ring->intr_vector = vector; 3710 3711 vector++; 3712 break; 3713 3714 default: 3715 return (IGB_FAILURE); 3716 } 3717 3718 ASSERT(vector == igb->intr_cnt); 3719 3720 return (IGB_SUCCESS); 3721 } 3722 3723 /* 3724 * igb_setup_adapter_msix - setup the adapter to use MSI-X interrupts 3725 * 3726 * For each vector enabled on the adapter, Set the MSIXBM register accordingly 3727 */ 3728 static void 3729 igb_setup_adapter_msix(igb_t *igb) 3730 { 3731 uint32_t eims = 0; 3732 int i, vector; 3733 struct e1000_hw *hw = &igb->hw; 3734 3735 /* 3736 * Set vector for Tx + Other causes 3737 * NOTE assumption that there is only one of these and it is vector 0 3738 */ 3739 vector = 0; 3740 igb->eims_mask = E1000_EICR_TX_QUEUE0 | E1000_EICR_OTHER; 3741 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), igb->eims_mask); 3742 3743 vector++; 3744 for (i = 0; i < igb->num_rx_rings; i++) { 3745 /* 3746 * Set vector for each rx ring 3747 */ 3748 eims = (E1000_EICR_RX_QUEUE0 << i); 3749 E1000_WRITE_REG(hw, E1000_MSIXBM(vector), eims); 3750 3751 /* 3752 * Accumulate bits to enable in igb_enable_adapter_interrupts() 3753 */ 3754 igb->eims_mask |= eims; 3755 3756 vector++; 3757 } 3758 3759 ASSERT(vector == igb->intr_cnt); 3760 3761 /* 3762 * Disable IAM for ICR interrupt bits 3763 */ 3764 E1000_WRITE_REG(hw, E1000_IAM, 0); 3765 E1000_WRITE_FLUSH(hw); 3766 } 3767 3768 /* 3769 * igb_rem_intr_handlers - remove the interrupt handlers 3770 */ 3771 static void 3772 igb_rem_intr_handlers(igb_t *igb) 3773 { 3774 int i; 3775 int rc; 3776 3777 for (i = 0; i < igb->intr_cnt; i++) { 3778 rc = ddi_intr_remove_handler(igb->htable[i]); 3779 if (rc != DDI_SUCCESS) { 3780 IGB_DEBUGLOG_1(igb, 3781 "Remove intr handler failed: %d", rc); 3782 } 3783 } 3784 } 3785 3786 /* 3787 * igb_rem_intrs - remove the allocated interrupts 3788 */ 3789 static void 3790 igb_rem_intrs(igb_t *igb) 3791 { 3792 int i; 3793 int rc; 3794 3795 for (i = 0; i < igb->intr_cnt; i++) { 3796 rc = ddi_intr_free(igb->htable[i]); 3797 if (rc != DDI_SUCCESS) { 3798 IGB_DEBUGLOG_1(igb, 3799 "Free intr failed: %d", rc); 3800 } 3801 } 3802 3803 kmem_free(igb->htable, igb->intr_size); 3804 igb->htable = NULL; 3805 } 3806 3807 /* 3808 * igb_enable_intrs - enable all the ddi interrupts 3809 */ 3810 static int 3811 igb_enable_intrs(igb_t *igb) 3812 { 3813 int i; 3814 int rc; 3815 3816 /* Enable interrupts */ 3817 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3818 /* Call ddi_intr_block_enable() for MSI */ 3819 rc = ddi_intr_block_enable(igb->htable, igb->intr_cnt); 3820 if (rc != DDI_SUCCESS) { 3821 igb_log(igb, 3822 "Enable block intr failed: %d", rc); 3823 return (IGB_FAILURE); 3824 } 3825 } else { 3826 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 3827 for (i = 0; i < igb->intr_cnt; i++) { 3828 rc = ddi_intr_enable(igb->htable[i]); 3829 if (rc != DDI_SUCCESS) { 3830 igb_log(igb, 3831 "Enable intr failed: %d", rc); 3832 return (IGB_FAILURE); 3833 } 3834 } 3835 } 3836 3837 return (IGB_SUCCESS); 3838 } 3839 3840 /* 3841 * igb_disable_intrs - disable all the ddi interrupts 3842 */ 3843 static int 3844 igb_disable_intrs(igb_t *igb) 3845 { 3846 int i; 3847 int rc; 3848 3849 /* Disable all interrupts */ 3850 if (igb->intr_cap & DDI_INTR_FLAG_BLOCK) { 3851 rc = ddi_intr_block_disable(igb->htable, igb->intr_cnt); 3852 if (rc != DDI_SUCCESS) { 3853 igb_log(igb, 3854 "Disable block intr failed: %d", rc); 3855 return (IGB_FAILURE); 3856 } 3857 } else { 3858 for (i = 0; i < igb->intr_cnt; i++) { 3859 rc = ddi_intr_disable(igb->htable[i]); 3860 if (rc != DDI_SUCCESS) { 3861 igb_log(igb, 3862 "Disable intr failed: %d", rc); 3863 return (IGB_FAILURE); 3864 } 3865 } 3866 } 3867 3868 return (IGB_SUCCESS); 3869 } 3870 3871 /* 3872 * igb_get_phy_state - Get and save the parameters read from PHY registers 3873 */ 3874 static void 3875 igb_get_phy_state(igb_t *igb) 3876 { 3877 struct e1000_hw *hw = &igb->hw; 3878 uint16_t phy_ctrl; 3879 uint16_t phy_status; 3880 uint16_t phy_an_adv; 3881 uint16_t phy_an_exp; 3882 uint16_t phy_ext_status; 3883 uint16_t phy_1000t_ctrl; 3884 uint16_t phy_1000t_status; 3885 uint16_t phy_lp_able; 3886 3887 ASSERT(mutex_owned(&igb->gen_lock)); 3888 3889 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 3890 (void) e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3891 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &phy_an_adv); 3892 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_an_exp); 3893 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3894 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_1000t_ctrl); 3895 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_1000t_status); 3896 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_lp_able); 3897 3898 igb->param_autoneg_cap = 3899 (phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 3900 igb->param_pause_cap = 3901 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 3902 igb->param_asym_pause_cap = 3903 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 3904 igb->param_1000fdx_cap = ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3905 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 3906 igb->param_1000hdx_cap = ((phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 3907 (phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 3908 igb->param_100t4_cap = 3909 (phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 3910 igb->param_100fdx_cap = ((phy_status & MII_SR_100X_FD_CAPS) || 3911 (phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 3912 igb->param_100hdx_cap = ((phy_status & MII_SR_100X_HD_CAPS) || 3913 (phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 3914 igb->param_10fdx_cap = 3915 (phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 3916 igb->param_10hdx_cap = 3917 (phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 3918 igb->param_rem_fault = 3919 (phy_status & MII_SR_REMOTE_FAULT) ? 1 : 0; 3920 3921 igb->param_adv_autoneg_cap = hw->mac.autoneg; 3922 igb->param_adv_pause_cap = 3923 (phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 3924 igb->param_adv_asym_pause_cap = 3925 (phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 3926 igb->param_adv_1000hdx_cap = 3927 (phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 3928 igb->param_adv_100t4_cap = 3929 (phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 3930 igb->param_adv_rem_fault = 3931 (phy_an_adv & NWAY_AR_REMOTE_FAULT) ? 1 : 0; 3932 if (igb->param_adv_autoneg_cap == 1) { 3933 igb->param_adv_1000fdx_cap = 3934 (phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 3935 igb->param_adv_100fdx_cap = 3936 (phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 3937 igb->param_adv_100hdx_cap = 3938 (phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 3939 igb->param_adv_10fdx_cap = 3940 (phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 3941 igb->param_adv_10hdx_cap = 3942 (phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 3943 } 3944 3945 igb->param_lp_autoneg_cap = 3946 (phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 3947 igb->param_lp_pause_cap = 3948 (phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 3949 igb->param_lp_asym_pause_cap = 3950 (phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 3951 igb->param_lp_1000fdx_cap = 3952 (phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 3953 igb->param_lp_1000hdx_cap = 3954 (phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 3955 igb->param_lp_100t4_cap = 3956 (phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 3957 igb->param_lp_100fdx_cap = 3958 (phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 3959 igb->param_lp_100hdx_cap = 3960 (phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 3961 igb->param_lp_10fdx_cap = 3962 (phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 3963 igb->param_lp_10hdx_cap = 3964 (phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 3965 igb->param_lp_rem_fault = 3966 (phy_lp_able & NWAY_LPAR_REMOTE_FAULT) ? 1 : 0; 3967 } 3968 3969 /* 3970 * igb_get_driver_control 3971 */ 3972 static void 3973 igb_get_driver_control(struct e1000_hw *hw) 3974 { 3975 uint32_t ctrl_ext; 3976 3977 /* Notify firmware that driver is in control of device */ 3978 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3979 ctrl_ext |= E1000_CTRL_EXT_DRV_LOAD; 3980 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3981 } 3982 3983 /* 3984 * igb_release_driver_control 3985 */ 3986 static void 3987 igb_release_driver_control(struct e1000_hw *hw) 3988 { 3989 uint32_t ctrl_ext; 3990 3991 /* Notify firmware that driver is no longer in control of device */ 3992 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 3993 ctrl_ext &= ~E1000_CTRL_EXT_DRV_LOAD; 3994 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 3995 } 3996 3997 /* 3998 * igb_atomic_reserve - Atomic decrease operation 3999 */ 4000 int 4001 igb_atomic_reserve(uint32_t *count_p, uint32_t n) 4002 { 4003 uint32_t oldval; 4004 uint32_t newval; 4005 4006 /* ATOMICALLY */ 4007 do { 4008 oldval = *count_p; 4009 if (oldval < n) 4010 return (-1); 4011 newval = oldval - n; 4012 } while (atomic_cas_32(count_p, oldval, newval) != oldval); 4013 4014 return (newval); 4015 } 4016