1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <hxge_impl.h> 27 #include <hxge_rxdma.h> 28 29 /* 30 * Globals: tunable parameters (/etc/system or adb) 31 * 32 */ 33 extern uint32_t hxge_rbr_size; 34 extern uint32_t hxge_rcr_size; 35 extern uint32_t hxge_rbr_spare_size; 36 extern uint32_t hxge_mblks_pending; 37 38 /* 39 * Tunable to reduce the amount of time spent in the 40 * ISR doing Rx Processing. 41 */ 42 extern uint32_t hxge_max_rx_pkts; 43 44 /* 45 * Tunables to manage the receive buffer blocks. 46 * 47 * hxge_rx_threshold_hi: copy all buffers. 48 * hxge_rx_bcopy_size_type: receive buffer block size type. 49 * hxge_rx_threshold_lo: copy only up to tunable block size type. 50 */ 51 extern hxge_rxbuf_threshold_t hxge_rx_threshold_hi; 52 extern hxge_rxbuf_type_t hxge_rx_buf_size_type; 53 extern hxge_rxbuf_threshold_t hxge_rx_threshold_lo; 54 55 static hxge_status_t hxge_map_rxdma(p_hxge_t hxgep); 56 static void hxge_unmap_rxdma(p_hxge_t hxgep); 57 static hxge_status_t hxge_rxdma_hw_start_common(p_hxge_t hxgep); 58 static hxge_status_t hxge_rxdma_hw_start(p_hxge_t hxgep); 59 static void hxge_rxdma_hw_stop(p_hxge_t hxgep); 60 static hxge_status_t hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 61 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 62 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 63 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 64 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 65 static void hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 66 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 67 static hxge_status_t hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, 68 uint16_t dma_channel, p_hxge_dma_common_t *dma_rbr_cntl_p, 69 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 70 p_rx_rbr_ring_t *rbr_p, p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p); 71 static void hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 72 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p); 73 static hxge_status_t hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, 74 uint16_t channel, p_hxge_dma_common_t *dma_buf_p, 75 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks); 76 static void hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 77 p_rx_rbr_ring_t rbr_p); 78 static hxge_status_t hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 79 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p); 80 static hxge_status_t hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel); 81 static mblk_t *hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 82 p_rx_rcr_ring_t *rcr_p, rdc_stat_t cs); 83 static void hxge_receive_packet(p_hxge_t hxgep, p_rx_rcr_ring_t rcr_p, 84 p_rcr_entry_t rcr_desc_rd_head_p, boolean_t *multi_p, 85 mblk_t ** mp, mblk_t ** mp_cont, uint32_t *invalid_rcr_entry); 86 static hxge_status_t hxge_disable_rxdma_channel(p_hxge_t hxgep, 87 uint16_t channel); 88 static p_rx_msg_t hxge_allocb(size_t, uint32_t, p_hxge_dma_common_t); 89 static void hxge_freeb(p_rx_msg_t); 90 static void hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, 91 p_hxge_ldv_t ldvp, rdc_stat_t cs); 92 static hxge_status_t hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, 93 p_hxge_ldv_t ldvp, rdc_stat_t cs); 94 static hxge_status_t hxge_rxbuf_index_info_init(p_hxge_t hxgep, 95 p_rx_rbr_ring_t rx_dmap); 96 static hxge_status_t hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, 97 uint16_t channel); 98 static hxge_status_t hxge_rx_port_fatal_err_recover(p_hxge_t hxgep); 99 100 hxge_status_t 101 hxge_init_rxdma_channels(p_hxge_t hxgep) 102 { 103 hxge_status_t status = HXGE_OK; 104 block_reset_t reset_reg; 105 106 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_init_rxdma_channels")); 107 108 /* Reset RDC block from PEU to clear any previous state */ 109 reset_reg.value = 0; 110 reset_reg.bits.rdc_rst = 1; 111 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 112 HXGE_DELAY(1000); 113 114 status = hxge_map_rxdma(hxgep); 115 if (status != HXGE_OK) { 116 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 117 "<== hxge_init_rxdma: status 0x%x", status)); 118 return (status); 119 } 120 121 status = hxge_rxdma_hw_start_common(hxgep); 122 if (status != HXGE_OK) { 123 hxge_unmap_rxdma(hxgep); 124 } 125 126 status = hxge_rxdma_hw_start(hxgep); 127 if (status != HXGE_OK) { 128 hxge_unmap_rxdma(hxgep); 129 } 130 131 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 132 "<== hxge_init_rxdma_channels: status 0x%x", status)); 133 return (status); 134 } 135 136 void 137 hxge_uninit_rxdma_channels(p_hxge_t hxgep) 138 { 139 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_uninit_rxdma_channels")); 140 141 hxge_rxdma_hw_stop(hxgep); 142 hxge_unmap_rxdma(hxgep); 143 144 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_uinit_rxdma_channels")); 145 } 146 147 hxge_status_t 148 hxge_init_rxdma_channel_cntl_stat(p_hxge_t hxgep, uint16_t channel, 149 rdc_stat_t *cs_p) 150 { 151 hpi_handle_t handle; 152 hpi_status_t rs = HPI_SUCCESS; 153 hxge_status_t status = HXGE_OK; 154 155 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 156 "<== hxge_init_rxdma_channel_cntl_stat")); 157 158 handle = HXGE_DEV_HPI_HANDLE(hxgep); 159 rs = hpi_rxdma_control_status(handle, OP_SET, channel, cs_p); 160 161 if (rs != HPI_SUCCESS) { 162 status = HXGE_ERROR | rs; 163 } 164 return (status); 165 } 166 167 168 hxge_status_t 169 hxge_enable_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 170 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 171 { 172 hpi_handle_t handle; 173 rdc_desc_cfg_t rdc_desc; 174 rdc_rcr_cfg_b_t *cfgb_p; 175 hpi_status_t rs = HPI_SUCCESS; 176 177 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel")); 178 handle = HXGE_DEV_HPI_HANDLE(hxgep); 179 180 /* 181 * Use configuration data composed at init time. Write to hardware the 182 * receive ring configurations. 183 */ 184 rdc_desc.mbox_enable = 1; 185 rdc_desc.mbox_addr = mbox_p->mbox_addr; 186 HXGE_DEBUG_MSG((hxgep, RX_CTL, 187 "==> hxge_enable_rxdma_channel: mboxp $%p($%p)", 188 mbox_p->mbox_addr, rdc_desc.mbox_addr)); 189 190 rdc_desc.rbr_len = rbr_p->rbb_max; 191 rdc_desc.rbr_addr = rbr_p->rbr_addr; 192 193 switch (hxgep->rx_bksize_code) { 194 case RBR_BKSIZE_4K: 195 rdc_desc.page_size = SIZE_4KB; 196 break; 197 case RBR_BKSIZE_8K: 198 rdc_desc.page_size = SIZE_8KB; 199 break; 200 } 201 202 rdc_desc.size0 = rbr_p->hpi_pkt_buf_size0; 203 rdc_desc.valid0 = 1; 204 205 rdc_desc.size1 = rbr_p->hpi_pkt_buf_size1; 206 rdc_desc.valid1 = 1; 207 208 rdc_desc.size2 = rbr_p->hpi_pkt_buf_size2; 209 rdc_desc.valid2 = 1; 210 211 rdc_desc.full_hdr = rcr_p->full_hdr_flag; 212 rdc_desc.offset = rcr_p->sw_priv_hdr_len; 213 214 rdc_desc.rcr_len = rcr_p->comp_size; 215 rdc_desc.rcr_addr = rcr_p->rcr_addr; 216 217 cfgb_p = &(rcr_p->rcr_cfgb); 218 rdc_desc.rcr_threshold = cfgb_p->bits.pthres; 219 rdc_desc.rcr_timeout = cfgb_p->bits.timeout; 220 rdc_desc.rcr_timeout_enable = cfgb_p->bits.entout; 221 222 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 223 "rbr_len qlen %d pagesize code %d rcr_len %d", 224 rdc_desc.rbr_len, rdc_desc.page_size, rdc_desc.rcr_len)); 225 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_enable_rxdma_channel: " 226 "size 0 %d size 1 %d size 2 %d", 227 rbr_p->hpi_pkt_buf_size0, rbr_p->hpi_pkt_buf_size1, 228 rbr_p->hpi_pkt_buf_size2)); 229 230 rs = hpi_rxdma_cfg_rdc_ring(handle, rbr_p->rdc, &rdc_desc); 231 if (rs != HPI_SUCCESS) { 232 return (HXGE_ERROR | rs); 233 } 234 235 /* 236 * Enable the timeout and threshold. 237 */ 238 rs = hpi_rxdma_cfg_rdc_rcr_threshold(handle, channel, 239 rdc_desc.rcr_threshold); 240 if (rs != HPI_SUCCESS) { 241 return (HXGE_ERROR | rs); 242 } 243 244 rs = hpi_rxdma_cfg_rdc_rcr_timeout(handle, channel, 245 rdc_desc.rcr_timeout); 246 if (rs != HPI_SUCCESS) { 247 return (HXGE_ERROR | rs); 248 } 249 250 /* Enable the DMA */ 251 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 252 if (rs != HPI_SUCCESS) { 253 return (HXGE_ERROR | rs); 254 } 255 256 /* Kick the DMA engine */ 257 hpi_rxdma_rdc_rbr_kick(handle, channel, rbr_p->rbb_max); 258 259 /* Clear the rbr empty bit */ 260 (void) hpi_rxdma_channel_rbr_empty_clear(handle, channel); 261 262 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_enable_rxdma_channel")); 263 264 return (HXGE_OK); 265 } 266 267 static hxge_status_t 268 hxge_disable_rxdma_channel(p_hxge_t hxgep, uint16_t channel) 269 { 270 hpi_handle_t handle; 271 hpi_status_t rs = HPI_SUCCESS; 272 273 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_disable_rxdma_channel")); 274 275 handle = HXGE_DEV_HPI_HANDLE(hxgep); 276 277 /* disable the DMA */ 278 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 279 if (rs != HPI_SUCCESS) { 280 HXGE_DEBUG_MSG((hxgep, RX_CTL, 281 "<== hxge_disable_rxdma_channel:failed (0x%x)", rs)); 282 return (HXGE_ERROR | rs); 283 } 284 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_disable_rxdma_channel")); 285 return (HXGE_OK); 286 } 287 288 hxge_status_t 289 hxge_rxdma_channel_rcrflush(p_hxge_t hxgep, uint8_t channel) 290 { 291 hpi_handle_t handle; 292 hxge_status_t status = HXGE_OK; 293 294 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 295 "==> hxge_rxdma_channel_rcrflush")); 296 297 handle = HXGE_DEV_HPI_HANDLE(hxgep); 298 hpi_rxdma_rdc_rcr_flush(handle, channel); 299 300 HXGE_DEBUG_MSG((hxgep, DMA_CTL, 301 "<== hxge_rxdma_channel_rcrflush")); 302 return (status); 303 304 } 305 306 #define MID_INDEX(l, r) ((r + l + 1) >> 1) 307 308 #define TO_LEFT -1 309 #define TO_RIGHT 1 310 #define BOTH_RIGHT (TO_RIGHT + TO_RIGHT) 311 #define BOTH_LEFT (TO_LEFT + TO_LEFT) 312 #define IN_MIDDLE (TO_RIGHT + TO_LEFT) 313 #define NO_HINT 0xffffffff 314 315 /*ARGSUSED*/ 316 hxge_status_t 317 hxge_rxbuf_pp_to_vp(p_hxge_t hxgep, p_rx_rbr_ring_t rbr_p, 318 uint8_t pktbufsz_type, uint64_t *pkt_buf_addr_pp, 319 uint64_t **pkt_buf_addr_p, uint32_t *bufoffset, uint32_t *msg_index) 320 { 321 int bufsize; 322 uint64_t pktbuf_pp; 323 uint64_t dvma_addr; 324 rxring_info_t *ring_info; 325 int base_side, end_side; 326 int r_index, l_index, anchor_index; 327 int found, search_done; 328 uint32_t offset, chunk_size, block_size, page_size_mask; 329 uint32_t chunk_index, block_index, total_index; 330 int max_iterations, iteration; 331 rxbuf_index_info_t *bufinfo; 332 333 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_rxbuf_pp_to_vp")); 334 335 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 336 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d", 337 pkt_buf_addr_pp, pktbufsz_type)); 338 339 #if defined(__i386) 340 pktbuf_pp = (uint64_t)(uint32_t)pkt_buf_addr_pp; 341 #else 342 pktbuf_pp = (uint64_t)pkt_buf_addr_pp; 343 #endif 344 345 switch (pktbufsz_type) { 346 case 0: 347 bufsize = rbr_p->pkt_buf_size0; 348 break; 349 case 1: 350 bufsize = rbr_p->pkt_buf_size1; 351 break; 352 case 2: 353 bufsize = rbr_p->pkt_buf_size2; 354 break; 355 case RCR_SINGLE_BLOCK: 356 bufsize = 0; 357 anchor_index = 0; 358 break; 359 default: 360 return (HXGE_ERROR); 361 } 362 363 if (rbr_p->num_blocks == 1) { 364 anchor_index = 0; 365 ring_info = rbr_p->ring_info; 366 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 367 368 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 369 "==> hxge_rxbuf_pp_to_vp: (found, 1 block) " 370 "buf_pp $%p btype %d anchor_index %d bufinfo $%p", 371 pkt_buf_addr_pp, pktbufsz_type, anchor_index, bufinfo)); 372 373 goto found_index; 374 } 375 376 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 377 "==> hxge_rxbuf_pp_to_vp: buf_pp $%p btype %d anchor_index %d", 378 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 379 380 ring_info = rbr_p->ring_info; 381 found = B_FALSE; 382 bufinfo = (rxbuf_index_info_t *)ring_info->buffer; 383 iteration = 0; 384 max_iterations = ring_info->max_iterations; 385 386 /* 387 * First check if this block have been seen recently. This is indicated 388 * by a hint which is initialized when the first buffer of the block is 389 * seen. The hint is reset when the last buffer of the block has been 390 * processed. As three block sizes are supported, three hints are kept. 391 * The idea behind the hints is that once the hardware uses a block 392 * for a buffer of that size, it will use it exclusively for that size 393 * and will use it until it is exhausted. It is assumed that there 394 * would a single block being used for the same buffer sizes at any 395 * given time. 396 */ 397 if (ring_info->hint[pktbufsz_type] != NO_HINT) { 398 anchor_index = ring_info->hint[pktbufsz_type]; 399 dvma_addr = bufinfo[anchor_index].dvma_addr; 400 chunk_size = bufinfo[anchor_index].buf_size; 401 if ((pktbuf_pp >= dvma_addr) && 402 (pktbuf_pp < (dvma_addr + chunk_size))) { 403 found = B_TRUE; 404 /* 405 * check if this is the last buffer in the block If so, 406 * then reset the hint for the size; 407 */ 408 409 if ((pktbuf_pp + bufsize) >= (dvma_addr + chunk_size)) 410 ring_info->hint[pktbufsz_type] = NO_HINT; 411 } 412 } 413 414 if (found == B_FALSE) { 415 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 416 "==> hxge_rxbuf_pp_to_vp: (!found)" 417 "buf_pp $%p btype %d anchor_index %d", 418 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 419 420 /* 421 * This is the first buffer of the block of this size. Need to 422 * search the whole information array. the search algorithm 423 * uses a binary tree search algorithm. It assumes that the 424 * information is already sorted with increasing order info[0] 425 * < info[1] < info[2] .... < info[n-1] where n is the size of 426 * the information array 427 */ 428 r_index = rbr_p->num_blocks - 1; 429 l_index = 0; 430 search_done = B_FALSE; 431 anchor_index = MID_INDEX(r_index, l_index); 432 while (search_done == B_FALSE) { 433 if ((r_index == l_index) || 434 (iteration >= max_iterations)) 435 search_done = B_TRUE; 436 437 end_side = TO_RIGHT; /* to the right */ 438 base_side = TO_LEFT; /* to the left */ 439 /* read the DVMA address information and sort it */ 440 dvma_addr = bufinfo[anchor_index].dvma_addr; 441 chunk_size = bufinfo[anchor_index].buf_size; 442 443 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 444 "==> hxge_rxbuf_pp_to_vp: (searching)" 445 "buf_pp $%p btype %d " 446 "anchor_index %d chunk_size %d dvmaaddr $%p", 447 pkt_buf_addr_pp, pktbufsz_type, anchor_index, 448 chunk_size, dvma_addr)); 449 450 if (pktbuf_pp >= dvma_addr) 451 base_side = TO_RIGHT; /* to the right */ 452 if (pktbuf_pp < (dvma_addr + chunk_size)) 453 end_side = TO_LEFT; /* to the left */ 454 455 switch (base_side + end_side) { 456 case IN_MIDDLE: 457 /* found */ 458 found = B_TRUE; 459 search_done = B_TRUE; 460 if ((pktbuf_pp + bufsize) < 461 (dvma_addr + chunk_size)) 462 ring_info->hint[pktbufsz_type] = 463 bufinfo[anchor_index].buf_index; 464 break; 465 case BOTH_RIGHT: 466 /* not found: go to the right */ 467 l_index = anchor_index + 1; 468 anchor_index = MID_INDEX(r_index, l_index); 469 break; 470 471 case BOTH_LEFT: 472 /* not found: go to the left */ 473 r_index = anchor_index - 1; 474 anchor_index = MID_INDEX(r_index, l_index); 475 break; 476 default: /* should not come here */ 477 return (HXGE_ERROR); 478 } 479 iteration++; 480 } 481 482 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 483 "==> hxge_rxbuf_pp_to_vp: (search done)" 484 "buf_pp $%p btype %d anchor_index %d", 485 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 486 } 487 488 if (found == B_FALSE) { 489 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 490 "==> hxge_rxbuf_pp_to_vp: (search failed)" 491 "buf_pp $%p btype %d anchor_index %d", 492 pkt_buf_addr_pp, pktbufsz_type, anchor_index)); 493 return (HXGE_ERROR); 494 } 495 496 found_index: 497 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 498 "==> hxge_rxbuf_pp_to_vp: (FOUND1)" 499 "buf_pp $%p btype %d bufsize %d anchor_index %d", 500 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index)); 501 502 /* index of the first block in this chunk */ 503 chunk_index = bufinfo[anchor_index].start_index; 504 dvma_addr = bufinfo[anchor_index].dvma_addr; 505 page_size_mask = ring_info->block_size_mask; 506 507 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 508 "==> hxge_rxbuf_pp_to_vp: (FOUND3), get chunk)" 509 "buf_pp $%p btype %d bufsize %d " 510 "anchor_index %d chunk_index %d dvma $%p", 511 pkt_buf_addr_pp, pktbufsz_type, bufsize, 512 anchor_index, chunk_index, dvma_addr)); 513 514 offset = pktbuf_pp - dvma_addr; /* offset within the chunk */ 515 block_size = rbr_p->block_size; /* System block(page) size */ 516 517 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 518 "==> hxge_rxbuf_pp_to_vp: (FOUND4), get chunk)" 519 "buf_pp $%p btype %d bufsize %d " 520 "anchor_index %d chunk_index %d dvma $%p " 521 "offset %d block_size %d", 522 pkt_buf_addr_pp, pktbufsz_type, bufsize, anchor_index, 523 chunk_index, dvma_addr, offset, block_size)); 524 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> getting total index")); 525 526 block_index = (offset / block_size); /* index within chunk */ 527 total_index = chunk_index + block_index; 528 529 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 530 "==> hxge_rxbuf_pp_to_vp: " 531 "total_index %d dvma_addr $%p " 532 "offset %d block_size %d " 533 "block_index %d ", 534 total_index, dvma_addr, offset, block_size, block_index)); 535 536 #if defined(__i386) 537 *pkt_buf_addr_p = (uint64_t *)((uint32_t)bufinfo[anchor_index].kaddr + 538 (uint32_t)offset); 539 #else 540 *pkt_buf_addr_p = (uint64_t *)((uint64_t)bufinfo[anchor_index].kaddr + 541 offset); 542 #endif 543 544 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 545 "==> hxge_rxbuf_pp_to_vp: " 546 "total_index %d dvma_addr $%p " 547 "offset %d block_size %d " 548 "block_index %d " 549 "*pkt_buf_addr_p $%p", 550 total_index, dvma_addr, offset, block_size, 551 block_index, *pkt_buf_addr_p)); 552 553 *msg_index = total_index; 554 *bufoffset = (offset & page_size_mask); 555 556 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 557 "==> hxge_rxbuf_pp_to_vp: get msg index: " 558 "msg_index %d bufoffset_index %d", 559 *msg_index, *bufoffset)); 560 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "<== hxge_rxbuf_pp_to_vp")); 561 562 return (HXGE_OK); 563 } 564 565 566 /* 567 * used by quick sort (qsort) function 568 * to perform comparison 569 */ 570 static int 571 hxge_sort_compare(const void *p1, const void *p2) 572 { 573 574 rxbuf_index_info_t *a, *b; 575 576 a = (rxbuf_index_info_t *)p1; 577 b = (rxbuf_index_info_t *)p2; 578 579 if (a->dvma_addr > b->dvma_addr) 580 return (1); 581 if (a->dvma_addr < b->dvma_addr) 582 return (-1); 583 return (0); 584 } 585 586 /* 587 * Grabbed this sort implementation from common/syscall/avl.c 588 * 589 * Generic shellsort, from K&R (1st ed, p 58.), somewhat modified. 590 * v = Ptr to array/vector of objs 591 * n = # objs in the array 592 * s = size of each obj (must be multiples of a word size) 593 * f = ptr to function to compare two objs 594 * returns (-1 = less than, 0 = equal, 1 = greater than 595 */ 596 void 597 hxge_ksort(caddr_t v, int n, int s, int (*f) ()) 598 { 599 int g, i, j, ii; 600 unsigned int *p1, *p2; 601 unsigned int tmp; 602 603 /* No work to do */ 604 if (v == NULL || n <= 1) 605 return; 606 /* Sanity check on arguments */ 607 ASSERT(((uintptr_t)v & 0x3) == 0 && (s & 0x3) == 0); 608 ASSERT(s > 0); 609 610 for (g = n / 2; g > 0; g /= 2) { 611 for (i = g; i < n; i++) { 612 for (j = i - g; j >= 0 && 613 (*f) (v + j * s, v + (j + g) * s) == 1; j -= g) { 614 p1 = (unsigned *)(v + j * s); 615 p2 = (unsigned *)(v + (j + g) * s); 616 for (ii = 0; ii < s / 4; ii++) { 617 tmp = *p1; 618 *p1++ = *p2; 619 *p2++ = tmp; 620 } 621 } 622 } 623 } 624 } 625 626 /* 627 * Initialize data structures required for rxdma 628 * buffer dvma->vmem address lookup 629 */ 630 /*ARGSUSED*/ 631 static hxge_status_t 632 hxge_rxbuf_index_info_init(p_hxge_t hxgep, p_rx_rbr_ring_t rbrp) 633 { 634 int index; 635 rxring_info_t *ring_info; 636 int max_iteration = 0, max_index = 0; 637 638 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "==> hxge_rxbuf_index_info_init")); 639 640 ring_info = rbrp->ring_info; 641 ring_info->hint[0] = NO_HINT; 642 ring_info->hint[1] = NO_HINT; 643 ring_info->hint[2] = NO_HINT; 644 max_index = rbrp->num_blocks; 645 646 /* read the DVMA address information and sort it */ 647 /* do init of the information array */ 648 649 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 650 " hxge_rxbuf_index_info_init Sort ptrs")); 651 652 /* sort the array */ 653 hxge_ksort((void *) ring_info->buffer, max_index, 654 sizeof (rxbuf_index_info_t), hxge_sort_compare); 655 656 for (index = 0; index < max_index; index++) { 657 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 658 " hxge_rxbuf_index_info_init: sorted chunk %d " 659 " ioaddr $%p kaddr $%p size %x", 660 index, ring_info->buffer[index].dvma_addr, 661 ring_info->buffer[index].kaddr, 662 ring_info->buffer[index].buf_size)); 663 } 664 665 max_iteration = 0; 666 while (max_index >= (1ULL << max_iteration)) 667 max_iteration++; 668 ring_info->max_iterations = max_iteration + 1; 669 670 HXGE_DEBUG_MSG((hxgep, DMA2_CTL, 671 " hxge_rxbuf_index_info_init Find max iter %d", 672 ring_info->max_iterations)); 673 HXGE_DEBUG_MSG((hxgep, DMA_CTL, "<== hxge_rxbuf_index_info_init")); 674 675 return (HXGE_OK); 676 } 677 678 /*ARGSUSED*/ 679 void 680 hxge_dump_rcr_entry(p_hxge_t hxgep, p_rcr_entry_t entry_p) 681 { 682 #ifdef HXGE_DEBUG 683 684 uint32_t bptr; 685 uint64_t pp; 686 687 bptr = entry_p->bits.pkt_buf_addr; 688 689 HXGE_DEBUG_MSG((hxgep, RX_CTL, 690 "\trcr entry $%p " 691 "\trcr entry 0x%0llx " 692 "\trcr entry 0x%08x " 693 "\trcr entry 0x%08x " 694 "\tvalue 0x%0llx\n" 695 "\tmulti = %d\n" 696 "\tpkt_type = 0x%x\n" 697 "\terror = 0x%04x\n" 698 "\tl2_len = %d\n" 699 "\tpktbufsize = %d\n" 700 "\tpkt_buf_addr = $%p\n" 701 "\tpkt_buf_addr (<< 6) = $%p\n", 702 entry_p, 703 *(int64_t *)entry_p, 704 *(int32_t *)entry_p, 705 *(int32_t *)((char *)entry_p + 32), 706 entry_p->value, 707 entry_p->bits.multi, 708 entry_p->bits.pkt_type, 709 entry_p->bits.error, 710 entry_p->bits.l2_len, 711 entry_p->bits.pktbufsz, 712 bptr, 713 entry_p->bits.pkt_buf_addr_l)); 714 715 pp = (entry_p->value & RCR_PKT_BUF_ADDR_MASK) << 716 RCR_PKT_BUF_ADDR_SHIFT; 717 718 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rcr pp 0x%llx l2 len %d", 719 pp, (*(int64_t *)entry_p >> 40) & 0x3fff)); 720 #endif 721 } 722 723 /*ARGSUSED*/ 724 void 725 hxge_rxdma_stop(p_hxge_t hxgep) 726 { 727 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop")); 728 729 (void) hxge_rx_vmac_disable(hxgep); 730 (void) hxge_rxdma_hw_mode(hxgep, HXGE_DMA_STOP); 731 732 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop")); 733 } 734 735 void 736 hxge_rxdma_stop_reinit(p_hxge_t hxgep) 737 { 738 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_reinit")); 739 740 (void) hxge_rxdma_stop(hxgep); 741 (void) hxge_uninit_rxdma_channels(hxgep); 742 (void) hxge_init_rxdma_channels(hxgep); 743 744 (void) hxge_rx_vmac_enable(hxgep); 745 746 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_reinit")); 747 } 748 749 hxge_status_t 750 hxge_rxdma_hw_mode(p_hxge_t hxgep, boolean_t enable) 751 { 752 int i, ndmas; 753 uint16_t channel; 754 p_rx_rbr_rings_t rx_rbr_rings; 755 p_rx_rbr_ring_t *rbr_rings; 756 hpi_handle_t handle; 757 hpi_status_t rs = HPI_SUCCESS; 758 hxge_status_t status = HXGE_OK; 759 760 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 761 "==> hxge_rxdma_hw_mode: mode %d", enable)); 762 763 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 764 HXGE_DEBUG_MSG((hxgep, RX_CTL, 765 "<== hxge_rxdma_mode: not initialized")); 766 return (HXGE_ERROR); 767 } 768 769 rx_rbr_rings = hxgep->rx_rbr_rings; 770 if (rx_rbr_rings == NULL) { 771 HXGE_DEBUG_MSG((hxgep, RX_CTL, 772 "<== hxge_rxdma_mode: NULL ring pointer")); 773 return (HXGE_ERROR); 774 } 775 776 if (rx_rbr_rings->rbr_rings == NULL) { 777 HXGE_DEBUG_MSG((hxgep, RX_CTL, 778 "<== hxge_rxdma_mode: NULL rbr rings pointer")); 779 return (HXGE_ERROR); 780 } 781 782 ndmas = rx_rbr_rings->ndmas; 783 if (!ndmas) { 784 HXGE_DEBUG_MSG((hxgep, RX_CTL, 785 "<== hxge_rxdma_mode: no channel")); 786 return (HXGE_ERROR); 787 } 788 789 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 790 "==> hxge_rxdma_mode (ndmas %d)", ndmas)); 791 792 rbr_rings = rx_rbr_rings->rbr_rings; 793 794 handle = HXGE_DEV_HPI_HANDLE(hxgep); 795 796 for (i = 0; i < ndmas; i++) { 797 if (rbr_rings == NULL || rbr_rings[i] == NULL) { 798 continue; 799 } 800 channel = rbr_rings[i]->rdc; 801 if (enable) { 802 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 803 "==> hxge_rxdma_hw_mode: channel %d (enable)", 804 channel)); 805 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 806 } else { 807 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 808 "==> hxge_rxdma_hw_mode: channel %d (disable)", 809 channel)); 810 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 811 } 812 } 813 814 status = ((rs == HPI_SUCCESS) ? HXGE_OK : HXGE_ERROR | rs); 815 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 816 "<== hxge_rxdma_hw_mode: status 0x%x", status)); 817 818 return (status); 819 } 820 821 int 822 hxge_rxdma_get_ring_index(p_hxge_t hxgep, uint16_t channel) 823 { 824 int i, ndmas; 825 uint16_t rdc; 826 p_rx_rbr_rings_t rx_rbr_rings; 827 p_rx_rbr_ring_t *rbr_rings; 828 829 HXGE_DEBUG_MSG((hxgep, RX_CTL, 830 "==> hxge_rxdma_get_ring_index: channel %d", channel)); 831 832 rx_rbr_rings = hxgep->rx_rbr_rings; 833 if (rx_rbr_rings == NULL) { 834 HXGE_DEBUG_MSG((hxgep, RX_CTL, 835 "<== hxge_rxdma_get_ring_index: NULL ring pointer")); 836 return (-1); 837 } 838 839 ndmas = rx_rbr_rings->ndmas; 840 if (!ndmas) { 841 HXGE_DEBUG_MSG((hxgep, RX_CTL, 842 "<== hxge_rxdma_get_ring_index: no channel")); 843 return (-1); 844 } 845 846 HXGE_DEBUG_MSG((hxgep, RX_CTL, 847 "==> hxge_rxdma_get_ring_index (ndmas %d)", ndmas)); 848 849 rbr_rings = rx_rbr_rings->rbr_rings; 850 for (i = 0; i < ndmas; i++) { 851 rdc = rbr_rings[i]->rdc; 852 if (channel == rdc) { 853 HXGE_DEBUG_MSG((hxgep, RX_CTL, 854 "==> hxge_rxdma_get_rbr_ring: " 855 "channel %d (index %d) " 856 "ring %d", channel, i, rbr_rings[i])); 857 858 return (i); 859 } 860 } 861 862 HXGE_DEBUG_MSG((hxgep, RX_CTL, 863 "<== hxge_rxdma_get_rbr_ring_index: not found")); 864 865 return (-1); 866 } 867 868 /* 869 * Static functions start here. 870 */ 871 static p_rx_msg_t 872 hxge_allocb(size_t size, uint32_t pri, p_hxge_dma_common_t dmabuf_p) 873 { 874 p_rx_msg_t hxge_mp = NULL; 875 p_hxge_dma_common_t dmamsg_p; 876 uchar_t *buffer; 877 878 hxge_mp = KMEM_ZALLOC(sizeof (rx_msg_t), KM_NOSLEEP); 879 if (hxge_mp == NULL) { 880 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 881 "Allocation of a rx msg failed.")); 882 goto hxge_allocb_exit; 883 } 884 885 hxge_mp->use_buf_pool = B_FALSE; 886 if (dmabuf_p) { 887 hxge_mp->use_buf_pool = B_TRUE; 888 889 dmamsg_p = (p_hxge_dma_common_t)&hxge_mp->buf_dma; 890 *dmamsg_p = *dmabuf_p; 891 dmamsg_p->nblocks = 1; 892 dmamsg_p->block_size = size; 893 dmamsg_p->alength = size; 894 buffer = (uchar_t *)dmabuf_p->kaddrp; 895 896 dmabuf_p->kaddrp = (void *)((char *)dmabuf_p->kaddrp + size); 897 dmabuf_p->ioaddr_pp = (void *) 898 ((char *)dmabuf_p->ioaddr_pp + size); 899 900 dmabuf_p->alength -= size; 901 dmabuf_p->offset += size; 902 dmabuf_p->dma_cookie.dmac_laddress += size; 903 dmabuf_p->dma_cookie.dmac_size -= size; 904 } else { 905 buffer = KMEM_ALLOC(size, KM_NOSLEEP); 906 if (buffer == NULL) { 907 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, 908 "Allocation of a receive page failed.")); 909 goto hxge_allocb_fail1; 910 } 911 } 912 913 hxge_mp->rx_mblk_p = desballoc(buffer, size, pri, &hxge_mp->freeb); 914 if (hxge_mp->rx_mblk_p == NULL) { 915 HXGE_ERROR_MSG((NULL, HXGE_ERR_CTL, "desballoc failed.")); 916 goto hxge_allocb_fail2; 917 } 918 hxge_mp->buffer = buffer; 919 hxge_mp->block_size = size; 920 hxge_mp->freeb.free_func = (void (*) ()) hxge_freeb; 921 hxge_mp->freeb.free_arg = (caddr_t)hxge_mp; 922 hxge_mp->ref_cnt = 1; 923 hxge_mp->free = B_TRUE; 924 hxge_mp->rx_use_bcopy = B_FALSE; 925 926 atomic_inc_32(&hxge_mblks_pending); 927 928 goto hxge_allocb_exit; 929 930 hxge_allocb_fail2: 931 if (!hxge_mp->use_buf_pool) { 932 KMEM_FREE(buffer, size); 933 } 934 hxge_allocb_fail1: 935 KMEM_FREE(hxge_mp, sizeof (rx_msg_t)); 936 hxge_mp = NULL; 937 938 hxge_allocb_exit: 939 return (hxge_mp); 940 } 941 942 p_mblk_t 943 hxge_dupb(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 944 { 945 p_mblk_t mp; 946 947 HXGE_DEBUG_MSG((NULL, MEM_CTL, "==> hxge_dupb")); 948 HXGE_DEBUG_MSG((NULL, MEM_CTL, "hxge_mp = $%p " 949 "offset = 0x%08X " "size = 0x%08X", hxge_mp, offset, size)); 950 951 mp = desballoc(&hxge_mp->buffer[offset], size, 0, &hxge_mp->freeb); 952 if (mp == NULL) { 953 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 954 goto hxge_dupb_exit; 955 } 956 957 atomic_inc_32(&hxge_mp->ref_cnt); 958 959 hxge_dupb_exit: 960 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 961 return (mp); 962 } 963 964 p_mblk_t 965 hxge_dupb_bcopy(p_rx_msg_t hxge_mp, uint_t offset, size_t size) 966 { 967 p_mblk_t mp; 968 uchar_t *dp; 969 970 mp = allocb(size + HXGE_RXBUF_EXTRA, 0); 971 if (mp == NULL) { 972 HXGE_DEBUG_MSG((NULL, RX_CTL, "desballoc failed")); 973 goto hxge_dupb_bcopy_exit; 974 } 975 dp = mp->b_rptr = mp->b_rptr + HXGE_RXBUF_EXTRA; 976 bcopy((void *) &hxge_mp->buffer[offset], dp, size); 977 mp->b_wptr = dp + size; 978 979 hxge_dupb_bcopy_exit: 980 981 HXGE_DEBUG_MSG((NULL, MEM_CTL, "<== hxge_dupb mp = $%p", hxge_mp)); 982 983 return (mp); 984 } 985 986 void hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, 987 p_rx_msg_t rx_msg_p); 988 989 void 990 hxge_post_page(p_hxge_t hxgep, p_rx_rbr_ring_t rx_rbr_p, p_rx_msg_t rx_msg_p) 991 { 992 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_post_page")); 993 994 /* Reuse this buffer */ 995 rx_msg_p->free = B_FALSE; 996 rx_msg_p->cur_usage_cnt = 0; 997 rx_msg_p->max_usage_cnt = 0; 998 rx_msg_p->pkt_buf_size = 0; 999 1000 if (rx_rbr_p->rbr_use_bcopy) { 1001 rx_msg_p->rx_use_bcopy = B_FALSE; 1002 atomic_dec_32(&rx_rbr_p->rbr_consumed); 1003 } 1004 1005 /* 1006 * Get the rbr header pointer and its offset index. 1007 */ 1008 MUTEX_ENTER(&rx_rbr_p->post_lock); 1009 rx_rbr_p->rbr_wr_index = ((rx_rbr_p->rbr_wr_index + 1) & 1010 rx_rbr_p->rbr_wrap_mask); 1011 rx_rbr_p->rbr_desc_vp[rx_rbr_p->rbr_wr_index] = rx_msg_p->shifted_addr; 1012 MUTEX_EXIT(&rx_rbr_p->post_lock); 1013 1014 hpi_rxdma_rdc_rbr_kick(HXGE_DEV_HPI_HANDLE(hxgep), rx_rbr_p->rdc, 1); 1015 1016 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1017 "<== hxge_post_page (channel %d post_next_index %d)", 1018 rx_rbr_p->rdc, rx_rbr_p->rbr_wr_index)); 1019 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_post_page")); 1020 } 1021 1022 void 1023 hxge_freeb(p_rx_msg_t rx_msg_p) 1024 { 1025 size_t size; 1026 uchar_t *buffer = NULL; 1027 int ref_cnt; 1028 boolean_t free_state = B_FALSE; 1029 rx_rbr_ring_t *ring = rx_msg_p->rx_rbr_p; 1030 1031 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "==> hxge_freeb")); 1032 HXGE_DEBUG_MSG((NULL, MEM2_CTL, 1033 "hxge_freeb:rx_msg_p = $%p (block pending %d)", 1034 rx_msg_p, hxge_mblks_pending)); 1035 1036 /* 1037 * First we need to get the free state, then 1038 * atomic decrement the reference count to prevent 1039 * the race condition with the interrupt thread that 1040 * is processing a loaned up buffer block. 1041 */ 1042 free_state = rx_msg_p->free; 1043 ref_cnt = atomic_add_32_nv(&rx_msg_p->ref_cnt, -1); 1044 if (!ref_cnt) { 1045 atomic_dec_32(&hxge_mblks_pending); 1046 1047 buffer = rx_msg_p->buffer; 1048 size = rx_msg_p->block_size; 1049 1050 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "hxge_freeb: " 1051 "will free: rx_msg_p = $%p (block pending %d)", 1052 rx_msg_p, hxge_mblks_pending)); 1053 1054 if (!rx_msg_p->use_buf_pool) { 1055 KMEM_FREE(buffer, size); 1056 } 1057 1058 KMEM_FREE(rx_msg_p, sizeof (rx_msg_t)); 1059 if (ring) { 1060 /* 1061 * Decrement the receive buffer ring's reference 1062 * count, too. 1063 */ 1064 atomic_dec_32(&ring->rbr_ref_cnt); 1065 1066 /* 1067 * Free the receive buffer ring, iff 1068 * 1. all the receive buffers have been freed 1069 * 2. and we are in the proper state (that is, 1070 * we are not UNMAPPING). 1071 */ 1072 if (ring->rbr_ref_cnt == 0 && 1073 ring->rbr_state == RBR_UNMAPPED) { 1074 KMEM_FREE(ring, sizeof (*ring)); 1075 } 1076 } 1077 goto hxge_freeb_exit; 1078 } 1079 1080 /* 1081 * Repost buffer. 1082 */ 1083 if ((ring != NULL) && free_state && (ref_cnt == 1)) { 1084 HXGE_DEBUG_MSG((NULL, RX_CTL, 1085 "hxge_freeb: post page $%p:", rx_msg_p)); 1086 if (ring->rbr_state == RBR_POSTING) 1087 hxge_post_page(rx_msg_p->hxgep, ring, rx_msg_p); 1088 } 1089 1090 hxge_freeb_exit: 1091 HXGE_DEBUG_MSG((NULL, MEM2_CTL, "<== hxge_freeb")); 1092 } 1093 1094 uint_t 1095 hxge_rx_intr(caddr_t arg1, caddr_t arg2) 1096 { 1097 p_hxge_ldv_t ldvp = (p_hxge_ldv_t)arg1; 1098 p_hxge_t hxgep = (p_hxge_t)arg2; 1099 p_hxge_ldg_t ldgp; 1100 uint8_t channel; 1101 hpi_handle_t handle; 1102 rdc_stat_t cs; 1103 uint_t serviced = DDI_INTR_UNCLAIMED; 1104 1105 if (ldvp == NULL) { 1106 HXGE_DEBUG_MSG((NULL, RX_INT_CTL, 1107 "<== hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1108 return (DDI_INTR_UNCLAIMED); 1109 } 1110 1111 if (arg2 == NULL || (void *) ldvp->hxgep != arg2) { 1112 hxgep = ldvp->hxgep; 1113 } 1114 1115 /* 1116 * If the interface is not started, just swallow the interrupt 1117 * for the logical device and don't rearm it. 1118 */ 1119 if (hxgep->hxge_mac_state != HXGE_MAC_STARTED) 1120 return (DDI_INTR_CLAIMED); 1121 1122 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1123 "==> hxge_rx_intr: arg2 $%p arg1 $%p", hxgep, ldvp)); 1124 1125 /* 1126 * This interrupt handler is for a specific receive dma channel. 1127 */ 1128 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1129 1130 /* 1131 * Get the control and status for this channel. 1132 */ 1133 channel = ldvp->channel; 1134 ldgp = ldvp->ldgp; 1135 RXDMA_REG_READ64(handle, RDC_STAT, channel, &cs.value); 1136 1137 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_intr:channel %d " 1138 "cs 0x%016llx rcrto 0x%x rcrthres %x", 1139 channel, cs.value, cs.bits.rcr_to, cs.bits.rcr_thres)); 1140 1141 hxge_rx_pkts_vring(hxgep, ldvp->vdma_index, ldvp, cs); 1142 serviced = DDI_INTR_CLAIMED; 1143 1144 /* error events. */ 1145 if (cs.value & RDC_STAT_ERROR) { 1146 (void) hxge_rx_err_evnts(hxgep, ldvp->vdma_index, ldvp, cs); 1147 } 1148 1149 hxge_intr_exit: 1150 /* 1151 * Enable the mailbox update interrupt if we want to use mailbox. We 1152 * probably don't need to use mailbox as it only saves us one pio read. 1153 * Also write 1 to rcrthres and rcrto to clear these two edge triggered 1154 * bits. 1155 */ 1156 cs.value &= RDC_STAT_WR1C; 1157 cs.bits.mex = 1; 1158 cs.bits.ptrread = 0; 1159 cs.bits.pktread = 0; 1160 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1161 1162 /* 1163 * Rearm this logical group if this is a single device group. 1164 */ 1165 if (ldgp->nldvs == 1) { 1166 ld_intr_mgmt_t mgm; 1167 1168 mgm.value = 0; 1169 mgm.bits.arm = 1; 1170 mgm.bits.timer = ldgp->ldg_timer; 1171 HXGE_REG_WR32(handle, 1172 LD_INTR_MGMT + LDSV_OFFSET(ldgp->ldg), mgm.value); 1173 } 1174 1175 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1176 "<== hxge_rx_intr: serviced %d", serviced)); 1177 1178 return (serviced); 1179 } 1180 1181 static void 1182 hxge_rx_pkts_vring(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1183 rdc_stat_t cs) 1184 { 1185 p_mblk_t mp; 1186 p_rx_rcr_ring_t rcrp; 1187 1188 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts_vring")); 1189 if ((mp = hxge_rx_pkts(hxgep, vindex, ldvp, &rcrp, cs)) == NULL) { 1190 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1191 "<== hxge_rx_pkts_vring: no mp")); 1192 return; 1193 } 1194 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts_vring: $%p", mp)); 1195 1196 #ifdef HXGE_DEBUG 1197 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1198 "==> hxge_rx_pkts_vring:calling mac_rx (NEMO) " 1199 "LEN %d mp $%p mp->b_next $%p rcrp $%p " 1200 "mac_handle $%p", 1201 (mp->b_wptr - mp->b_rptr), mp, mp->b_next, 1202 rcrp, rcrp->rcr_mac_handle)); 1203 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1204 "==> hxge_rx_pkts_vring: dump packets " 1205 "(mp $%p b_rptr $%p b_wptr $%p):\n %s", 1206 mp, mp->b_rptr, mp->b_wptr, 1207 hxge_dump_packet((char *)mp->b_rptr, 64))); 1208 1209 if (mp->b_cont) { 1210 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1211 "==> hxge_rx_pkts_vring: dump b_cont packets " 1212 "(mp->b_cont $%p b_rptr $%p b_wptr $%p):\n %s", 1213 mp->b_cont, mp->b_cont->b_rptr, mp->b_cont->b_wptr, 1214 hxge_dump_packet((char *)mp->b_cont->b_rptr, 1215 mp->b_cont->b_wptr - mp->b_cont->b_rptr))); 1216 } 1217 if (mp->b_next) { 1218 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1219 "==> hxge_rx_pkts_vring: dump next packets " 1220 "(b_rptr $%p): %s", 1221 mp->b_next->b_rptr, 1222 hxge_dump_packet((char *)mp->b_next->b_rptr, 64))); 1223 } 1224 #endif 1225 1226 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1227 "==> hxge_rx_pkts_vring: send packet to stack")); 1228 mac_rx(hxgep->mach, rcrp->rcr_mac_handle, mp); 1229 1230 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_pkts_vring")); 1231 } 1232 1233 /*ARGSUSED*/ 1234 mblk_t * 1235 hxge_rx_pkts(p_hxge_t hxgep, uint_t vindex, p_hxge_ldv_t ldvp, 1236 p_rx_rcr_ring_t *rcrp, rdc_stat_t cs) 1237 { 1238 hpi_handle_t handle; 1239 uint8_t channel; 1240 p_rx_rcr_rings_t rx_rcr_rings; 1241 p_rx_rcr_ring_t rcr_p; 1242 uint32_t comp_rd_index; 1243 p_rcr_entry_t rcr_desc_rd_head_p; 1244 p_rcr_entry_t rcr_desc_rd_head_pp; 1245 p_mblk_t nmp, mp_cont, head_mp, *tail_mp; 1246 uint16_t qlen, nrcr_read, npkt_read; 1247 uint32_t qlen_hw, qlen_sw; 1248 uint32_t invalid_rcr_entry; 1249 boolean_t multi; 1250 rdc_rcr_cfg_b_t rcr_cfg_b; 1251 p_rx_mbox_t rx_mboxp; 1252 p_rxdma_mailbox_t mboxp; 1253 uint64_t rcr_head_index, rcr_tail_index; 1254 uint64_t rcr_tail; 1255 uint64_t value; 1256 rdc_rcr_tail_t rcr_tail_reg; 1257 p_hxge_rx_ring_stats_t rdc_stats; 1258 1259 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:vindex %d " 1260 "channel %d", vindex, ldvp->channel)); 1261 1262 if (!(hxgep->drv_state & STATE_HW_INITIALIZED)) { 1263 return (NULL); 1264 } 1265 1266 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1267 rx_rcr_rings = hxgep->rx_rcr_rings; 1268 rcr_p = rx_rcr_rings->rcr_rings[vindex]; 1269 channel = rcr_p->rdc; 1270 if (channel != ldvp->channel) { 1271 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "==> hxge_rx_pkts:index %d " 1272 "channel %d, and rcr channel %d not matched.", 1273 vindex, ldvp->channel, channel)); 1274 return (NULL); 1275 } 1276 1277 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1278 "==> hxge_rx_pkts: START: rcr channel %d " 1279 "head_p $%p head_pp $%p index %d ", 1280 channel, rcr_p->rcr_desc_rd_head_p, 1281 rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1282 1283 rx_mboxp = hxgep->rx_mbox_areas_p->rxmbox_areas[channel]; 1284 mboxp = (p_rxdma_mailbox_t)rx_mboxp->rx_mbox.kaddrp; 1285 1286 (void) hpi_rxdma_rdc_rcr_qlen_get(handle, channel, &qlen); 1287 RXDMA_REG_READ64(handle, RDC_RCR_TAIL, channel, &rcr_tail_reg.value); 1288 rcr_tail = rcr_tail_reg.bits.tail; 1289 1290 if (!qlen) { 1291 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1292 "<== hxge_rx_pkts:rcr channel %d qlen %d (no pkts)", 1293 channel, qlen)); 1294 return (NULL); 1295 } 1296 1297 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_pkts:rcr channel %d " 1298 "qlen %d", channel, qlen)); 1299 1300 comp_rd_index = rcr_p->comp_rd_index; 1301 1302 rcr_desc_rd_head_p = rcr_p->rcr_desc_rd_head_p; 1303 rcr_desc_rd_head_pp = rcr_p->rcr_desc_rd_head_pp; 1304 nrcr_read = npkt_read = 0; 1305 1306 /* 1307 * Number of packets queued (The jumbo or multi packet will be counted 1308 * as only one paccket and it may take up more than one completion 1309 * entry). 1310 */ 1311 qlen_hw = (qlen < hxge_max_rx_pkts) ? qlen : hxge_max_rx_pkts; 1312 head_mp = NULL; 1313 tail_mp = &head_mp; 1314 nmp = mp_cont = NULL; 1315 multi = B_FALSE; 1316 1317 rcr_head_index = rcr_p->rcr_desc_rd_head_p - rcr_p->rcr_desc_first_p; 1318 rcr_tail_index = rcr_tail - rcr_p->rcr_tail_begin; 1319 1320 if (rcr_tail_index >= rcr_head_index) { 1321 qlen_sw = rcr_tail_index - rcr_head_index; 1322 } else { 1323 /* rcr_tail has wrapped around */ 1324 qlen_sw = (rcr_p->comp_size - rcr_head_index) + rcr_tail_index; 1325 } 1326 1327 if (qlen_hw > qlen_sw) { 1328 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1329 "Channel %d, rcr_qlen from reg %d and from rcr_tail %d\n", 1330 channel, qlen_hw, qlen_sw)); 1331 qlen_hw = qlen_sw; 1332 } 1333 1334 while (qlen_hw) { 1335 #ifdef HXGE_DEBUG 1336 hxge_dump_rcr_entry(hxgep, rcr_desc_rd_head_p); 1337 #endif 1338 /* 1339 * Process one completion ring entry. 1340 */ 1341 invalid_rcr_entry = 0; 1342 hxge_receive_packet(hxgep, 1343 rcr_p, rcr_desc_rd_head_p, &multi, &nmp, &mp_cont, 1344 &invalid_rcr_entry); 1345 if (invalid_rcr_entry != 0) { 1346 rdc_stats = rcr_p->rdc_stats; 1347 rdc_stats->rcr_invalids++; 1348 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1349 "Channel %d could only read 0x%x packets, " 1350 "but 0x%x pending\n", channel, npkt_read, qlen_hw)); 1351 break; 1352 } 1353 1354 /* 1355 * message chaining modes (nemo msg chaining) 1356 */ 1357 if (nmp) { 1358 nmp->b_next = NULL; 1359 if (!multi && !mp_cont) { /* frame fits a partition */ 1360 *tail_mp = nmp; 1361 tail_mp = &nmp->b_next; 1362 nmp = NULL; 1363 } else if (multi && !mp_cont) { /* first segment */ 1364 *tail_mp = nmp; 1365 tail_mp = &nmp->b_cont; 1366 } else if (multi && mp_cont) { /* mid of multi segs */ 1367 *tail_mp = mp_cont; 1368 tail_mp = &mp_cont->b_cont; 1369 } else if (!multi && mp_cont) { /* last segment */ 1370 *tail_mp = mp_cont; 1371 tail_mp = &nmp->b_next; 1372 nmp = NULL; 1373 } 1374 } 1375 1376 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1377 "==> hxge_rx_pkts: loop: rcr channel %d " 1378 "before updating: multi %d " 1379 "nrcr_read %d " 1380 "npk read %d " 1381 "head_pp $%p index %d ", 1382 channel, multi, 1383 nrcr_read, npkt_read, rcr_desc_rd_head_pp, comp_rd_index)); 1384 1385 if (!multi) { 1386 qlen_hw--; 1387 npkt_read++; 1388 } 1389 1390 /* 1391 * Update the next read entry. 1392 */ 1393 comp_rd_index = NEXT_ENTRY(comp_rd_index, 1394 rcr_p->comp_wrap_mask); 1395 1396 rcr_desc_rd_head_p = NEXT_ENTRY_PTR(rcr_desc_rd_head_p, 1397 rcr_p->rcr_desc_first_p, rcr_p->rcr_desc_last_p); 1398 1399 nrcr_read++; 1400 1401 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1402 "<== hxge_rx_pkts: (SAM, process one packet) " 1403 "nrcr_read %d", nrcr_read)); 1404 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1405 "==> hxge_rx_pkts: loop: rcr channel %d " 1406 "multi %d nrcr_read %d npk read %d head_pp $%p index %d ", 1407 channel, multi, nrcr_read, npkt_read, rcr_desc_rd_head_pp, 1408 comp_rd_index)); 1409 } 1410 1411 rcr_p->rcr_desc_rd_head_pp = rcr_desc_rd_head_pp; 1412 rcr_p->comp_rd_index = comp_rd_index; 1413 rcr_p->rcr_desc_rd_head_p = rcr_desc_rd_head_p; 1414 1415 /* Adjust the mailbox queue length for a hardware bug workaround */ 1416 mboxp->rcrstat_a.bits.qlen -= npkt_read; 1417 1418 if ((hxgep->intr_timeout != rcr_p->intr_timeout) || 1419 (hxgep->intr_threshold != rcr_p->intr_threshold)) { 1420 rcr_p->intr_timeout = hxgep->intr_timeout; 1421 rcr_p->intr_threshold = hxgep->intr_threshold; 1422 rcr_cfg_b.value = 0x0ULL; 1423 if (rcr_p->intr_timeout) 1424 rcr_cfg_b.bits.entout = 1; 1425 rcr_cfg_b.bits.timeout = rcr_p->intr_timeout; 1426 rcr_cfg_b.bits.pthres = rcr_p->intr_threshold; 1427 RXDMA_REG_WRITE64(handle, RDC_RCR_CFG_B, 1428 channel, rcr_cfg_b.value); 1429 } 1430 1431 cs.bits.pktread = npkt_read; 1432 cs.bits.ptrread = nrcr_read; 1433 value = cs.value; 1434 cs.value &= 0xffffffffULL; 1435 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1436 1437 cs.value = value & ~0xffffffffULL; 1438 cs.bits.pktread = 0; 1439 cs.bits.ptrread = 0; 1440 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs.value); 1441 1442 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, 1443 "==> hxge_rx_pkts: EXIT: rcr channel %d " 1444 "head_pp $%p index %016llx ", 1445 channel, rcr_p->rcr_desc_rd_head_pp, rcr_p->comp_rd_index)); 1446 1447 /* 1448 * Update RCR buffer pointer read and number of packets read. 1449 */ 1450 1451 *rcrp = rcr_p; 1452 1453 HXGE_DEBUG_MSG((hxgep, RX_INT_CTL, "<== hxge_rx_pkts")); 1454 1455 return (head_mp); 1456 } 1457 1458 #define RCR_ENTRY_PATTERN 0x5a5a6b6b7c7c8d8dULL 1459 1460 /*ARGSUSED*/ 1461 void 1462 hxge_receive_packet(p_hxge_t hxgep, 1463 p_rx_rcr_ring_t rcr_p, p_rcr_entry_t rcr_desc_rd_head_p, 1464 boolean_t *multi_p, mblk_t **mp, mblk_t **mp_cont, 1465 uint32_t *invalid_rcr_entry) 1466 { 1467 p_mblk_t nmp = NULL; 1468 uint64_t multi; 1469 uint8_t channel; 1470 1471 boolean_t first_entry = B_TRUE; 1472 boolean_t is_tcp_udp = B_FALSE; 1473 boolean_t buffer_free = B_FALSE; 1474 boolean_t error_send_up = B_FALSE; 1475 uint8_t error_type; 1476 uint16_t l2_len; 1477 uint16_t skip_len; 1478 uint8_t pktbufsz_type; 1479 uint64_t rcr_entry; 1480 uint64_t *pkt_buf_addr_pp; 1481 uint64_t *pkt_buf_addr_p; 1482 uint32_t buf_offset; 1483 uint32_t bsize; 1484 uint32_t msg_index; 1485 p_rx_rbr_ring_t rx_rbr_p; 1486 p_rx_msg_t *rx_msg_ring_p; 1487 p_rx_msg_t rx_msg_p; 1488 1489 uint16_t sw_offset_bytes = 0, hdr_size = 0; 1490 hxge_status_t status = HXGE_OK; 1491 boolean_t is_valid = B_FALSE; 1492 p_hxge_rx_ring_stats_t rdc_stats; 1493 uint32_t bytes_read; 1494 1495 uint64_t pkt_type; 1496 1497 channel = rcr_p->rdc; 1498 1499 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "==> hxge_receive_packet")); 1500 1501 first_entry = (*mp == NULL) ? B_TRUE : B_FALSE; 1502 rcr_entry = *((uint64_t *)rcr_desc_rd_head_p); 1503 1504 /* Verify the content of the rcr_entry for a hardware bug workaround */ 1505 if ((rcr_entry == 0x0) || (rcr_entry == RCR_ENTRY_PATTERN)) { 1506 *invalid_rcr_entry = 1; 1507 HXGE_DEBUG_MSG((hxgep, RX2_CTL, "hxge_receive_packet " 1508 "Channel %d invalid RCR entry 0x%llx found, returning\n", 1509 channel, (long long) rcr_entry)); 1510 return; 1511 } 1512 *((uint64_t *)rcr_desc_rd_head_p) = RCR_ENTRY_PATTERN; 1513 1514 multi = (rcr_entry & RCR_MULTI_MASK); 1515 pkt_type = (rcr_entry & RCR_PKT_TYPE_MASK); 1516 1517 error_type = ((rcr_entry & RCR_ERROR_MASK) >> RCR_ERROR_SHIFT); 1518 l2_len = ((rcr_entry & RCR_L2_LEN_MASK) >> RCR_L2_LEN_SHIFT); 1519 1520 /* 1521 * Hardware does not strip the CRC due bug ID 11451 where 1522 * the hardware mis handles minimum size packets. 1523 */ 1524 l2_len -= ETHERFCSL; 1525 1526 pktbufsz_type = ((rcr_entry & RCR_PKTBUFSZ_MASK) >> 1527 RCR_PKTBUFSZ_SHIFT); 1528 #if defined(__i386) 1529 pkt_buf_addr_pp = (uint64_t *)(uint32_t)((rcr_entry & 1530 RCR_PKT_BUF_ADDR_MASK) << RCR_PKT_BUF_ADDR_SHIFT); 1531 #else 1532 pkt_buf_addr_pp = (uint64_t *)((rcr_entry & RCR_PKT_BUF_ADDR_MASK) << 1533 RCR_PKT_BUF_ADDR_SHIFT); 1534 #endif 1535 1536 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1537 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1538 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1539 "error_type 0x%x pkt_type 0x%x " 1540 "pktbufsz_type %d ", 1541 rcr_desc_rd_head_p, rcr_entry, pkt_buf_addr_pp, l2_len, 1542 multi, error_type, pkt_type, pktbufsz_type)); 1543 1544 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1545 "==> hxge_receive_packet: entryp $%p entry 0x%0llx " 1546 "pkt_buf_addr_pp $%p l2_len %d multi %d " 1547 "error_type 0x%x pkt_type 0x%x ", rcr_desc_rd_head_p, 1548 rcr_entry, pkt_buf_addr_pp, l2_len, multi, error_type, pkt_type)); 1549 1550 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1551 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1552 "full pkt_buf_addr_pp $%p l2_len %d", 1553 rcr_entry, pkt_buf_addr_pp, l2_len)); 1554 1555 /* get the stats ptr */ 1556 rdc_stats = rcr_p->rdc_stats; 1557 1558 if (!l2_len) { 1559 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1560 "<== hxge_receive_packet: failed: l2 length is 0.")); 1561 return; 1562 } 1563 1564 /* shift 6 bits to get the full io address */ 1565 #if defined(__i386) 1566 pkt_buf_addr_pp = (uint64_t *)((uint32_t)pkt_buf_addr_pp << 1567 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1568 #else 1569 pkt_buf_addr_pp = (uint64_t *)((uint64_t)pkt_buf_addr_pp << 1570 RCR_PKT_BUF_ADDR_SHIFT_FULL); 1571 #endif 1572 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1573 "==> (rbr) hxge_receive_packet: entry 0x%0llx " 1574 "full pkt_buf_addr_pp $%p l2_len %d", 1575 rcr_entry, pkt_buf_addr_pp, l2_len)); 1576 1577 rx_rbr_p = rcr_p->rx_rbr_p; 1578 rx_msg_ring_p = rx_rbr_p->rx_msg_ring; 1579 1580 if (first_entry) { 1581 hdr_size = (rcr_p->full_hdr_flag ? RXDMA_HDR_SIZE_FULL : 1582 RXDMA_HDR_SIZE_DEFAULT); 1583 1584 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1585 "==> hxge_receive_packet: first entry 0x%016llx " 1586 "pkt_buf_addr_pp $%p l2_len %d hdr %d", 1587 rcr_entry, pkt_buf_addr_pp, l2_len, hdr_size)); 1588 } 1589 1590 MUTEX_ENTER(&rcr_p->lock); 1591 MUTEX_ENTER(&rx_rbr_p->lock); 1592 1593 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1594 "==> (rbr 1) hxge_receive_packet: entry 0x%0llx " 1595 "full pkt_buf_addr_pp $%p l2_len %d", 1596 rcr_entry, pkt_buf_addr_pp, l2_len)); 1597 1598 /* 1599 * Packet buffer address in the completion entry points to the starting 1600 * buffer address (offset 0). Use the starting buffer address to locate 1601 * the corresponding kernel address. 1602 */ 1603 status = hxge_rxbuf_pp_to_vp(hxgep, rx_rbr_p, 1604 pktbufsz_type, pkt_buf_addr_pp, &pkt_buf_addr_p, 1605 &buf_offset, &msg_index); 1606 1607 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1608 "==> (rbr 2) hxge_receive_packet: entry 0x%0llx " 1609 "full pkt_buf_addr_pp $%p l2_len %d", 1610 rcr_entry, pkt_buf_addr_pp, l2_len)); 1611 1612 if (status != HXGE_OK) { 1613 MUTEX_EXIT(&rx_rbr_p->lock); 1614 MUTEX_EXIT(&rcr_p->lock); 1615 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1616 "<== hxge_receive_packet: found vaddr failed %d", status)); 1617 return; 1618 } 1619 1620 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1621 "==> (rbr 3) hxge_receive_packet: entry 0x%0llx " 1622 "full pkt_buf_addr_pp $%p l2_len %d", 1623 rcr_entry, pkt_buf_addr_pp, l2_len)); 1624 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1625 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1626 "full pkt_buf_addr_pp $%p l2_len %d", 1627 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1628 1629 if (msg_index >= rx_rbr_p->tnblocks) { 1630 MUTEX_EXIT(&rx_rbr_p->lock); 1631 MUTEX_EXIT(&rcr_p->lock); 1632 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1633 "==> hxge_receive_packet: FATAL msg_index (%d) " 1634 "should be smaller than tnblocks (%d)\n", 1635 msg_index, rx_rbr_p->tnblocks)); 1636 return; 1637 } 1638 1639 rx_msg_p = rx_msg_ring_p[msg_index]; 1640 1641 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1642 "==> (rbr 4 msgindex %d) hxge_receive_packet: entry 0x%0llx " 1643 "full pkt_buf_addr_pp $%p l2_len %d", 1644 msg_index, rcr_entry, pkt_buf_addr_pp, l2_len)); 1645 1646 switch (pktbufsz_type) { 1647 case RCR_PKTBUFSZ_0: 1648 bsize = rx_rbr_p->pkt_buf_size0_bytes; 1649 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1650 "==> hxge_receive_packet: 0 buf %d", bsize)); 1651 break; 1652 case RCR_PKTBUFSZ_1: 1653 bsize = rx_rbr_p->pkt_buf_size1_bytes; 1654 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1655 "==> hxge_receive_packet: 1 buf %d", bsize)); 1656 break; 1657 case RCR_PKTBUFSZ_2: 1658 bsize = rx_rbr_p->pkt_buf_size2_bytes; 1659 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1660 "==> hxge_receive_packet: 2 buf %d", bsize)); 1661 break; 1662 case RCR_SINGLE_BLOCK: 1663 bsize = rx_msg_p->block_size; 1664 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1665 "==> hxge_receive_packet: single %d", bsize)); 1666 1667 break; 1668 default: 1669 MUTEX_EXIT(&rx_rbr_p->lock); 1670 MUTEX_EXIT(&rcr_p->lock); 1671 return; 1672 } 1673 1674 DMA_COMMON_SYNC_OFFSET(rx_msg_p->buf_dma, 1675 (buf_offset + sw_offset_bytes), (hdr_size + l2_len), 1676 DDI_DMA_SYNC_FORCPU); 1677 1678 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1679 "==> hxge_receive_packet: after first dump:usage count")); 1680 1681 if (rx_msg_p->cur_usage_cnt == 0) { 1682 if (rx_rbr_p->rbr_use_bcopy) { 1683 atomic_inc_32(&rx_rbr_p->rbr_consumed); 1684 if (rx_rbr_p->rbr_consumed < 1685 rx_rbr_p->rbr_threshold_hi) { 1686 if (rx_rbr_p->rbr_threshold_lo == 0 || 1687 ((rx_rbr_p->rbr_consumed >= 1688 rx_rbr_p->rbr_threshold_lo) && 1689 (rx_rbr_p->rbr_bufsize_type >= 1690 pktbufsz_type))) { 1691 rx_msg_p->rx_use_bcopy = B_TRUE; 1692 } 1693 } else { 1694 rx_msg_p->rx_use_bcopy = B_TRUE; 1695 } 1696 } 1697 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1698 "==> hxge_receive_packet: buf %d (new block) ", bsize)); 1699 1700 rx_msg_p->pkt_buf_size_code = pktbufsz_type; 1701 rx_msg_p->pkt_buf_size = bsize; 1702 rx_msg_p->cur_usage_cnt = 1; 1703 if (pktbufsz_type == RCR_SINGLE_BLOCK) { 1704 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1705 "==> hxge_receive_packet: buf %d (single block) ", 1706 bsize)); 1707 /* 1708 * Buffer can be reused once the free function is 1709 * called. 1710 */ 1711 rx_msg_p->max_usage_cnt = 1; 1712 buffer_free = B_TRUE; 1713 } else { 1714 rx_msg_p->max_usage_cnt = rx_msg_p->block_size / bsize; 1715 if (rx_msg_p->max_usage_cnt == 1) { 1716 buffer_free = B_TRUE; 1717 } 1718 } 1719 } else { 1720 rx_msg_p->cur_usage_cnt++; 1721 if (rx_msg_p->cur_usage_cnt == rx_msg_p->max_usage_cnt) { 1722 buffer_free = B_TRUE; 1723 } 1724 } 1725 1726 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1727 "msgbuf index = %d l2len %d bytes usage %d max_usage %d ", 1728 msg_index, l2_len, 1729 rx_msg_p->cur_usage_cnt, rx_msg_p->max_usage_cnt)); 1730 1731 if (error_type) { 1732 rdc_stats->ierrors++; 1733 /* Update error stats */ 1734 rdc_stats->errlog.compl_err_type = error_type; 1735 HXGE_FM_REPORT_ERROR(hxgep, NULL, HXGE_FM_EREPORT_RDMC_RCR_ERR); 1736 1737 if (error_type & RCR_CTRL_FIFO_DED) { 1738 rdc_stats->ctrl_fifo_ecc_err++; 1739 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1740 " hxge_receive_packet: " 1741 " channel %d RCR ctrl_fifo_ded error", channel)); 1742 } else if (error_type & RCR_DATA_FIFO_DED) { 1743 rdc_stats->data_fifo_ecc_err++; 1744 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1745 " hxge_receive_packet: channel %d" 1746 " RCR data_fifo_ded error", channel)); 1747 } 1748 1749 /* 1750 * Update and repost buffer block if max usage count is 1751 * reached. 1752 */ 1753 if (error_send_up == B_FALSE) { 1754 atomic_inc_32(&rx_msg_p->ref_cnt); 1755 if (buffer_free == B_TRUE) { 1756 rx_msg_p->free = B_TRUE; 1757 } 1758 1759 MUTEX_EXIT(&rx_rbr_p->lock); 1760 MUTEX_EXIT(&rcr_p->lock); 1761 hxge_freeb(rx_msg_p); 1762 return; 1763 } 1764 } 1765 1766 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1767 "==> hxge_receive_packet: DMA sync second ")); 1768 1769 bytes_read = rcr_p->rcvd_pkt_bytes; 1770 skip_len = sw_offset_bytes + hdr_size; 1771 if (!rx_msg_p->rx_use_bcopy) { 1772 /* 1773 * For loaned up buffers, the driver reference count 1774 * will be incremented first and then the free state. 1775 */ 1776 if ((nmp = hxge_dupb(rx_msg_p, buf_offset, bsize)) != NULL) { 1777 if (first_entry) { 1778 nmp->b_rptr = &nmp->b_rptr[skip_len]; 1779 if (l2_len < bsize - skip_len) { 1780 nmp->b_wptr = &nmp->b_rptr[l2_len]; 1781 } else { 1782 nmp->b_wptr = &nmp->b_rptr[bsize 1783 - skip_len]; 1784 } 1785 } else { 1786 if (l2_len - bytes_read < bsize) { 1787 nmp->b_wptr = 1788 &nmp->b_rptr[l2_len - bytes_read]; 1789 } else { 1790 nmp->b_wptr = &nmp->b_rptr[bsize]; 1791 } 1792 } 1793 } 1794 } else { 1795 if (first_entry) { 1796 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset + skip_len, 1797 l2_len < bsize - skip_len ? 1798 l2_len : bsize - skip_len); 1799 } else { 1800 nmp = hxge_dupb_bcopy(rx_msg_p, buf_offset, 1801 l2_len - bytes_read < bsize ? 1802 l2_len - bytes_read : bsize); 1803 } 1804 } 1805 1806 if (nmp != NULL) { 1807 if (first_entry) 1808 bytes_read = nmp->b_wptr - nmp->b_rptr; 1809 else 1810 bytes_read += nmp->b_wptr - nmp->b_rptr; 1811 1812 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1813 "==> hxge_receive_packet after dupb: " 1814 "rbr consumed %d " 1815 "pktbufsz_type %d " 1816 "nmp $%p rptr $%p wptr $%p " 1817 "buf_offset %d bzise %d l2_len %d skip_len %d", 1818 rx_rbr_p->rbr_consumed, 1819 pktbufsz_type, 1820 nmp, nmp->b_rptr, nmp->b_wptr, 1821 buf_offset, bsize, l2_len, skip_len)); 1822 } else { 1823 cmn_err(CE_WARN, "!hxge_receive_packet: update stats (error)"); 1824 1825 atomic_inc_32(&rx_msg_p->ref_cnt); 1826 if (buffer_free == B_TRUE) { 1827 rx_msg_p->free = B_TRUE; 1828 } 1829 1830 MUTEX_EXIT(&rx_rbr_p->lock); 1831 MUTEX_EXIT(&rcr_p->lock); 1832 hxge_freeb(rx_msg_p); 1833 return; 1834 } 1835 1836 if (buffer_free == B_TRUE) { 1837 rx_msg_p->free = B_TRUE; 1838 } 1839 1840 /* 1841 * ERROR, FRAG and PKT_TYPE are only reported in the first entry. If a 1842 * packet is not fragmented and no error bit is set, then L4 checksum 1843 * is OK. 1844 */ 1845 is_valid = (nmp != NULL); 1846 if (first_entry) { 1847 rdc_stats->ipackets++; /* count only 1st seg for jumbo */ 1848 if (l2_len > (STD_FRAME_SIZE - ETHERFCSL)) 1849 rdc_stats->jumbo_pkts++; 1850 rdc_stats->ibytes += skip_len + l2_len < bsize ? 1851 l2_len : bsize; 1852 } else { 1853 /* 1854 * Add the current portion of the packet to the kstats. 1855 * The current portion of the packet is calculated by using 1856 * length of the packet and the previously received portion. 1857 */ 1858 rdc_stats->ibytes += l2_len - rcr_p->rcvd_pkt_bytes < bsize ? 1859 l2_len - rcr_p->rcvd_pkt_bytes : bsize; 1860 } 1861 1862 rcr_p->rcvd_pkt_bytes = bytes_read; 1863 1864 if (rx_msg_p->free && rx_msg_p->rx_use_bcopy) { 1865 atomic_inc_32(&rx_msg_p->ref_cnt); 1866 MUTEX_EXIT(&rx_rbr_p->lock); 1867 MUTEX_EXIT(&rcr_p->lock); 1868 hxge_freeb(rx_msg_p); 1869 } else { 1870 MUTEX_EXIT(&rx_rbr_p->lock); 1871 MUTEX_EXIT(&rcr_p->lock); 1872 } 1873 1874 if (is_valid) { 1875 nmp->b_cont = NULL; 1876 if (first_entry) { 1877 *mp = nmp; 1878 *mp_cont = NULL; 1879 } else { 1880 *mp_cont = nmp; 1881 } 1882 } 1883 1884 /* 1885 * Update stats and hardware checksuming. 1886 */ 1887 if (is_valid && !multi) { 1888 is_tcp_udp = ((pkt_type == RCR_PKT_IS_TCP || 1889 pkt_type == RCR_PKT_IS_UDP) ? B_TRUE : B_FALSE); 1890 1891 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_receive_packet: " 1892 "is_valid 0x%x multi %d pkt %d d error %d", 1893 is_valid, multi, is_tcp_udp, error_type)); 1894 1895 if (is_tcp_udp && !error_type) { 1896 (void) hcksum_assoc(nmp, NULL, NULL, 0, 0, 0, 0, 1897 HCK_FULLCKSUM_OK | HCK_FULLCKSUM, 0); 1898 1899 HXGE_DEBUG_MSG((hxgep, RX_CTL, 1900 "==> hxge_receive_packet: Full tcp/udp cksum " 1901 "is_valid 0x%x multi %d pkt %d " 1902 "error %d", 1903 is_valid, multi, is_tcp_udp, error_type)); 1904 } 1905 } 1906 1907 HXGE_DEBUG_MSG((hxgep, RX2_CTL, 1908 "==> hxge_receive_packet: *mp 0x%016llx", *mp)); 1909 1910 *multi_p = (multi == RCR_MULTI_MASK); 1911 1912 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_receive_packet: " 1913 "multi %d nmp 0x%016llx *mp 0x%016llx *mp_cont 0x%016llx", 1914 *multi_p, nmp, *mp, *mp_cont)); 1915 } 1916 1917 /*ARGSUSED*/ 1918 static hxge_status_t 1919 hxge_rx_err_evnts(p_hxge_t hxgep, uint_t index, p_hxge_ldv_t ldvp, 1920 rdc_stat_t cs) 1921 { 1922 p_hxge_rx_ring_stats_t rdc_stats; 1923 hpi_handle_t handle; 1924 boolean_t rxchan_fatal = B_FALSE; 1925 uint8_t channel; 1926 hxge_status_t status = HXGE_OK; 1927 uint64_t cs_val; 1928 1929 HXGE_DEBUG_MSG((hxgep, INT_CTL, "==> hxge_rx_err_evnts")); 1930 1931 handle = HXGE_DEV_HPI_HANDLE(hxgep); 1932 channel = ldvp->channel; 1933 1934 /* Clear the interrupts */ 1935 cs.bits.pktread = 0; 1936 cs.bits.ptrread = 0; 1937 cs_val = cs.value & RDC_STAT_WR1C; 1938 RXDMA_REG_WRITE64(handle, RDC_STAT, channel, cs_val); 1939 1940 rdc_stats = &hxgep->statsp->rdc_stats[ldvp->vdma_index]; 1941 1942 if (cs.bits.rbr_cpl_to) { 1943 rdc_stats->rbr_tmout++; 1944 HXGE_FM_REPORT_ERROR(hxgep, channel, 1945 HXGE_FM_EREPORT_RDMC_RBR_CPL_TO); 1946 rxchan_fatal = B_TRUE; 1947 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1948 "==> hxge_rx_err_evnts(channel %d): " 1949 "fatal error: rx_rbr_timeout", channel)); 1950 } 1951 1952 if ((cs.bits.rcr_shadow_par_err) || (cs.bits.rbr_prefetch_par_err)) { 1953 (void) hpi_rxdma_ring_perr_stat_get(handle, 1954 &rdc_stats->errlog.pre_par, &rdc_stats->errlog.sha_par); 1955 } 1956 1957 if (cs.bits.rcr_shadow_par_err) { 1958 rdc_stats->rcr_sha_par++; 1959 HXGE_FM_REPORT_ERROR(hxgep, channel, 1960 HXGE_FM_EREPORT_RDMC_RCR_SHA_PAR); 1961 rxchan_fatal = B_TRUE; 1962 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1963 "==> hxge_rx_err_evnts(channel %d): " 1964 "fatal error: rcr_shadow_par_err", channel)); 1965 } 1966 1967 if (cs.bits.rbr_prefetch_par_err) { 1968 rdc_stats->rbr_pre_par++; 1969 HXGE_FM_REPORT_ERROR(hxgep, channel, 1970 HXGE_FM_EREPORT_RDMC_RBR_PRE_PAR); 1971 rxchan_fatal = B_TRUE; 1972 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1973 "==> hxge_rx_err_evnts(channel %d): " 1974 "fatal error: rbr_prefetch_par_err", channel)); 1975 } 1976 1977 if (cs.bits.rbr_pre_empty) { 1978 rdc_stats->rbr_pre_empty++; 1979 HXGE_FM_REPORT_ERROR(hxgep, channel, 1980 HXGE_FM_EREPORT_RDMC_RBR_PRE_EMPTY); 1981 rxchan_fatal = B_TRUE; 1982 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1983 "==> hxge_rx_err_evnts(channel %d): " 1984 "fatal error: rbr_pre_empty", channel)); 1985 } 1986 1987 if (cs.bits.peu_resp_err) { 1988 rdc_stats->peu_resp_err++; 1989 HXGE_FM_REPORT_ERROR(hxgep, channel, 1990 HXGE_FM_EREPORT_RDMC_PEU_RESP_ERR); 1991 rxchan_fatal = B_TRUE; 1992 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 1993 "==> hxge_rx_err_evnts(channel %d): " 1994 "fatal error: peu_resp_err", channel)); 1995 } 1996 1997 if (cs.bits.rcr_thres) { 1998 rdc_stats->rcr_thres++; 1999 } 2000 2001 if (cs.bits.rcr_to) { 2002 rdc_stats->rcr_to++; 2003 } 2004 2005 if (cs.bits.rcr_shadow_full) { 2006 rdc_stats->rcr_shadow_full++; 2007 HXGE_FM_REPORT_ERROR(hxgep, channel, 2008 HXGE_FM_EREPORT_RDMC_RCR_SHA_FULL); 2009 rxchan_fatal = B_TRUE; 2010 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2011 "==> hxge_rx_err_evnts(channel %d): " 2012 "fatal error: rcr_shadow_full", channel)); 2013 } 2014 2015 if (cs.bits.rcr_full) { 2016 rdc_stats->rcrfull++; 2017 HXGE_FM_REPORT_ERROR(hxgep, channel, 2018 HXGE_FM_EREPORT_RDMC_RCRFULL); 2019 rxchan_fatal = B_TRUE; 2020 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2021 "==> hxge_rx_err_evnts(channel %d): " 2022 "fatal error: rcrfull error", channel)); 2023 } 2024 2025 if (cs.bits.rbr_empty) { 2026 rdc_stats->rbr_empty++; 2027 if (rdc_stats->rbr_empty == 1) 2028 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2029 "==> hxge_rx_err_evnts(channel %d): " 2030 "rbr empty error", channel)); 2031 /* 2032 * DMA channel is disabled due to rbr_empty bit is set 2033 * although it is not fatal. Enable the DMA channel here 2034 * to work-around the hardware bug. 2035 */ 2036 (void) hpi_rxdma_cfg_rdc_enable(handle, channel); 2037 } 2038 2039 if (cs.bits.rbr_full) { 2040 rdc_stats->rbrfull++; 2041 HXGE_FM_REPORT_ERROR(hxgep, channel, 2042 HXGE_FM_EREPORT_RDMC_RBRFULL); 2043 rxchan_fatal = B_TRUE; 2044 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2045 "==> hxge_rx_err_evnts(channel %d): " 2046 "fatal error: rbr_full error", channel)); 2047 } 2048 2049 if (rxchan_fatal) { 2050 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2051 " hxge_rx_err_evnts: fatal error on Channel #%d\n", 2052 channel)); 2053 status = hxge_rxdma_fatal_err_recover(hxgep, channel); 2054 if (status == HXGE_OK) { 2055 FM_SERVICE_RESTORED(hxgep); 2056 } 2057 } 2058 HXGE_DEBUG_MSG((hxgep, INT_CTL, "<== hxge_rx_err_evnts")); 2059 2060 return (status); 2061 } 2062 2063 static hxge_status_t 2064 hxge_map_rxdma(p_hxge_t hxgep) 2065 { 2066 int i, ndmas; 2067 uint16_t channel; 2068 p_rx_rbr_rings_t rx_rbr_rings; 2069 p_rx_rbr_ring_t *rbr_rings; 2070 p_rx_rcr_rings_t rx_rcr_rings; 2071 p_rx_rcr_ring_t *rcr_rings; 2072 p_rx_mbox_areas_t rx_mbox_areas_p; 2073 p_rx_mbox_t *rx_mbox_p; 2074 p_hxge_dma_pool_t dma_buf_poolp; 2075 p_hxge_dma_common_t *dma_buf_p; 2076 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2077 p_hxge_dma_common_t *dma_rbr_cntl_p; 2078 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2079 p_hxge_dma_common_t *dma_rcr_cntl_p; 2080 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2081 p_hxge_dma_common_t *dma_mbox_cntl_p; 2082 uint32_t *num_chunks; 2083 hxge_status_t status = HXGE_OK; 2084 2085 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_map_rxdma")); 2086 2087 dma_buf_poolp = hxgep->rx_buf_pool_p; 2088 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2089 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2090 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2091 2092 if (!dma_buf_poolp->buf_allocated || 2093 !dma_rbr_cntl_poolp->buf_allocated || 2094 !dma_rcr_cntl_poolp->buf_allocated || 2095 !dma_mbox_cntl_poolp->buf_allocated) { 2096 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2097 "<== hxge_map_rxdma: buf not allocated")); 2098 return (HXGE_ERROR); 2099 } 2100 2101 ndmas = dma_buf_poolp->ndmas; 2102 if (!ndmas) { 2103 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2104 "<== hxge_map_rxdma: no dma allocated")); 2105 return (HXGE_ERROR); 2106 } 2107 2108 num_chunks = dma_buf_poolp->num_chunks; 2109 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2110 dma_rbr_cntl_p = dma_rbr_cntl_poolp->dma_buf_pool_p; 2111 dma_rcr_cntl_p = dma_rcr_cntl_poolp->dma_buf_pool_p; 2112 dma_mbox_cntl_p = dma_mbox_cntl_poolp->dma_buf_pool_p; 2113 2114 rx_rbr_rings = (p_rx_rbr_rings_t) 2115 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2116 rbr_rings = (p_rx_rbr_ring_t *)KMEM_ZALLOC( 2117 sizeof (p_rx_rbr_ring_t) * ndmas, KM_SLEEP); 2118 2119 rx_rcr_rings = (p_rx_rcr_rings_t) 2120 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2121 rcr_rings = (p_rx_rcr_ring_t *)KMEM_ZALLOC( 2122 sizeof (p_rx_rcr_ring_t) * ndmas, KM_SLEEP); 2123 2124 rx_mbox_areas_p = (p_rx_mbox_areas_t) 2125 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2126 rx_mbox_p = (p_rx_mbox_t *)KMEM_ZALLOC( 2127 sizeof (p_rx_mbox_t) * ndmas, KM_SLEEP); 2128 2129 /* 2130 * Timeout should be set based on the system clock divider. 2131 * The following timeout value of 1 assumes that the 2132 * granularity (1000) is 3 microseconds running at 300MHz. 2133 */ 2134 2135 hxgep->intr_threshold = RXDMA_RCR_PTHRES_DEFAULT; 2136 hxgep->intr_timeout = RXDMA_RCR_TO_DEFAULT; 2137 2138 /* 2139 * Map descriptors from the buffer polls for each dam channel. 2140 */ 2141 for (i = 0; i < ndmas; i++) { 2142 /* 2143 * Set up and prepare buffer blocks, descriptors and mailbox. 2144 */ 2145 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2146 status = hxge_map_rxdma_channel(hxgep, channel, 2147 (p_hxge_dma_common_t *)&dma_buf_p[i], 2148 (p_rx_rbr_ring_t *)&rbr_rings[i], 2149 num_chunks[i], 2150 (p_hxge_dma_common_t *)&dma_rbr_cntl_p[i], 2151 (p_hxge_dma_common_t *)&dma_rcr_cntl_p[i], 2152 (p_hxge_dma_common_t *)&dma_mbox_cntl_p[i], 2153 (p_rx_rcr_ring_t *)&rcr_rings[i], 2154 (p_rx_mbox_t *)&rx_mbox_p[i]); 2155 if (status != HXGE_OK) { 2156 goto hxge_map_rxdma_fail1; 2157 } 2158 rbr_rings[i]->index = (uint16_t)i; 2159 rcr_rings[i]->index = (uint16_t)i; 2160 rcr_rings[i]->rdc_stats = &hxgep->statsp->rdc_stats[i]; 2161 } 2162 2163 rx_rbr_rings->ndmas = rx_rcr_rings->ndmas = ndmas; 2164 rx_rbr_rings->rbr_rings = rbr_rings; 2165 hxgep->rx_rbr_rings = rx_rbr_rings; 2166 rx_rcr_rings->rcr_rings = rcr_rings; 2167 hxgep->rx_rcr_rings = rx_rcr_rings; 2168 2169 rx_mbox_areas_p->rxmbox_areas = rx_mbox_p; 2170 hxgep->rx_mbox_areas_p = rx_mbox_areas_p; 2171 2172 goto hxge_map_rxdma_exit; 2173 2174 hxge_map_rxdma_fail1: 2175 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2176 "==> hxge_map_rxdma: unmap rbr,rcr (status 0x%x channel %d i %d)", 2177 status, channel, i)); 2178 i--; 2179 for (; i >= 0; i--) { 2180 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2181 hxge_unmap_rxdma_channel(hxgep, channel, 2182 rbr_rings[i], rcr_rings[i], rx_mbox_p[i]); 2183 } 2184 2185 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2186 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2187 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2188 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2189 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2190 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2191 2192 hxge_map_rxdma_exit: 2193 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2194 "<== hxge_map_rxdma: (status 0x%x channel %d)", status, channel)); 2195 2196 return (status); 2197 } 2198 2199 static void 2200 hxge_unmap_rxdma(p_hxge_t hxgep) 2201 { 2202 int i, ndmas; 2203 uint16_t channel; 2204 p_rx_rbr_rings_t rx_rbr_rings; 2205 p_rx_rbr_ring_t *rbr_rings; 2206 p_rx_rcr_rings_t rx_rcr_rings; 2207 p_rx_rcr_ring_t *rcr_rings; 2208 p_rx_mbox_areas_t rx_mbox_areas_p; 2209 p_rx_mbox_t *rx_mbox_p; 2210 p_hxge_dma_pool_t dma_buf_poolp; 2211 p_hxge_dma_pool_t dma_rbr_cntl_poolp; 2212 p_hxge_dma_pool_t dma_rcr_cntl_poolp; 2213 p_hxge_dma_pool_t dma_mbox_cntl_poolp; 2214 p_hxge_dma_common_t *dma_buf_p; 2215 2216 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_unmap_rxdma")); 2217 2218 dma_buf_poolp = hxgep->rx_buf_pool_p; 2219 dma_rbr_cntl_poolp = hxgep->rx_rbr_cntl_pool_p; 2220 dma_rcr_cntl_poolp = hxgep->rx_rcr_cntl_pool_p; 2221 dma_mbox_cntl_poolp = hxgep->rx_mbox_cntl_pool_p; 2222 2223 if (!dma_buf_poolp->buf_allocated || 2224 !dma_rbr_cntl_poolp->buf_allocated || 2225 !dma_rcr_cntl_poolp->buf_allocated || 2226 !dma_mbox_cntl_poolp->buf_allocated) { 2227 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2228 "<== hxge_unmap_rxdma: NULL buf pointers")); 2229 return; 2230 } 2231 2232 rx_rbr_rings = hxgep->rx_rbr_rings; 2233 rx_rcr_rings = hxgep->rx_rcr_rings; 2234 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2235 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2236 "<== hxge_unmap_rxdma: NULL pointers")); 2237 return; 2238 } 2239 2240 ndmas = rx_rbr_rings->ndmas; 2241 if (!ndmas) { 2242 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2243 "<== hxge_unmap_rxdma: no channel")); 2244 return; 2245 } 2246 2247 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2248 "==> hxge_unmap_rxdma (ndmas %d)", ndmas)); 2249 2250 rbr_rings = rx_rbr_rings->rbr_rings; 2251 rcr_rings = rx_rcr_rings->rcr_rings; 2252 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 2253 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 2254 dma_buf_p = dma_buf_poolp->dma_buf_pool_p; 2255 2256 for (i = 0; i < ndmas; i++) { 2257 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 2258 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2259 "==> hxge_unmap_rxdma (ndmas %d) channel %d", 2260 ndmas, channel)); 2261 (void) hxge_unmap_rxdma_channel(hxgep, channel, 2262 (p_rx_rbr_ring_t)rbr_rings[i], 2263 (p_rx_rcr_ring_t)rcr_rings[i], 2264 (p_rx_mbox_t)rx_mbox_p[i]); 2265 } 2266 2267 KMEM_FREE(rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2268 KMEM_FREE(rbr_rings, sizeof (p_rx_rbr_ring_t) * ndmas); 2269 KMEM_FREE(rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2270 KMEM_FREE(rcr_rings, sizeof (p_rx_rcr_ring_t) * ndmas); 2271 KMEM_FREE(rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2272 KMEM_FREE(rx_mbox_p, sizeof (p_rx_mbox_t) * ndmas); 2273 2274 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma")); 2275 } 2276 2277 hxge_status_t 2278 hxge_map_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2279 p_hxge_dma_common_t *dma_buf_p, p_rx_rbr_ring_t *rbr_p, 2280 uint32_t num_chunks, p_hxge_dma_common_t *dma_rbr_cntl_p, 2281 p_hxge_dma_common_t *dma_rcr_cntl_p, p_hxge_dma_common_t *dma_mbox_cntl_p, 2282 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2283 { 2284 int status = HXGE_OK; 2285 2286 /* 2287 * Set up and prepare buffer blocks, descriptors and mailbox. 2288 */ 2289 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2290 "==> hxge_map_rxdma_channel (channel %d)", channel)); 2291 2292 /* 2293 * Receive buffer blocks 2294 */ 2295 status = hxge_map_rxdma_channel_buf_ring(hxgep, channel, 2296 dma_buf_p, rbr_p, num_chunks); 2297 if (status != HXGE_OK) { 2298 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2299 "==> hxge_map_rxdma_channel (channel %d): " 2300 "map buffer failed 0x%x", channel, status)); 2301 goto hxge_map_rxdma_channel_exit; 2302 } 2303 2304 /* 2305 * Receive block ring, completion ring and mailbox. 2306 */ 2307 status = hxge_map_rxdma_channel_cfg_ring(hxgep, channel, 2308 dma_rbr_cntl_p, dma_rcr_cntl_p, dma_mbox_cntl_p, 2309 rbr_p, rcr_p, rx_mbox_p); 2310 if (status != HXGE_OK) { 2311 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2312 "==> hxge_map_rxdma_channel (channel %d): " 2313 "map config failed 0x%x", channel, status)); 2314 goto hxge_map_rxdma_channel_fail2; 2315 } 2316 goto hxge_map_rxdma_channel_exit; 2317 2318 hxge_map_rxdma_channel_fail3: 2319 /* Free rbr, rcr */ 2320 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2321 "==> hxge_map_rxdma_channel: free rbr/rcr (status 0x%x channel %d)", 2322 status, channel)); 2323 hxge_unmap_rxdma_channel_cfg_ring(hxgep, *rcr_p, *rx_mbox_p); 2324 2325 hxge_map_rxdma_channel_fail2: 2326 /* Free buffer blocks */ 2327 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2328 "==> hxge_map_rxdma_channel: free rx buffers" 2329 "(hxgep 0x%x status 0x%x channel %d)", 2330 hxgep, status, channel)); 2331 hxge_unmap_rxdma_channel_buf_ring(hxgep, *rbr_p); 2332 2333 status = HXGE_ERROR; 2334 2335 hxge_map_rxdma_channel_exit: 2336 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2337 "<== hxge_map_rxdma_channel: (hxgep 0x%x status 0x%x channel %d)", 2338 hxgep, status, channel)); 2339 2340 return (status); 2341 } 2342 2343 /*ARGSUSED*/ 2344 static void 2345 hxge_unmap_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 2346 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2347 { 2348 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2349 "==> hxge_unmap_rxdma_channel (channel %d)", channel)); 2350 2351 /* 2352 * unmap receive block ring, completion ring and mailbox. 2353 */ 2354 (void) hxge_unmap_rxdma_channel_cfg_ring(hxgep, rcr_p, rx_mbox_p); 2355 2356 /* unmap buffer blocks */ 2357 (void) hxge_unmap_rxdma_channel_buf_ring(hxgep, rbr_p); 2358 2359 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_unmap_rxdma_channel")); 2360 } 2361 2362 /*ARGSUSED*/ 2363 static hxge_status_t 2364 hxge_map_rxdma_channel_cfg_ring(p_hxge_t hxgep, uint16_t dma_channel, 2365 p_hxge_dma_common_t *dma_rbr_cntl_p, p_hxge_dma_common_t *dma_rcr_cntl_p, 2366 p_hxge_dma_common_t *dma_mbox_cntl_p, p_rx_rbr_ring_t *rbr_p, 2367 p_rx_rcr_ring_t *rcr_p, p_rx_mbox_t *rx_mbox_p) 2368 { 2369 p_rx_rbr_ring_t rbrp; 2370 p_rx_rcr_ring_t rcrp; 2371 p_rx_mbox_t mboxp; 2372 p_hxge_dma_common_t cntl_dmap; 2373 p_hxge_dma_common_t dmap; 2374 p_rx_msg_t *rx_msg_ring; 2375 p_rx_msg_t rx_msg_p; 2376 rdc_rbr_cfg_a_t *rcfga_p; 2377 rdc_rbr_cfg_b_t *rcfgb_p; 2378 rdc_rcr_cfg_a_t *cfga_p; 2379 rdc_rcr_cfg_b_t *cfgb_p; 2380 rdc_rx_cfg1_t *cfig1_p; 2381 rdc_rx_cfg2_t *cfig2_p; 2382 rdc_rbr_kick_t *kick_p; 2383 uint32_t dmaaddrp; 2384 uint32_t *rbr_vaddrp; 2385 uint32_t bkaddr; 2386 hxge_status_t status = HXGE_OK; 2387 int i; 2388 uint32_t hxge_port_rcr_size; 2389 2390 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2391 "==> hxge_map_rxdma_channel_cfg_ring")); 2392 2393 cntl_dmap = *dma_rbr_cntl_p; 2394 2395 /* 2396 * Map in the receive block ring 2397 */ 2398 rbrp = *rbr_p; 2399 dmap = (p_hxge_dma_common_t)&rbrp->rbr_desc; 2400 hxge_setup_dma_common(dmap, cntl_dmap, rbrp->rbb_max, 4); 2401 2402 /* 2403 * Zero out buffer block ring descriptors. 2404 */ 2405 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2406 2407 rcfga_p = &(rbrp->rbr_cfga); 2408 rcfgb_p = &(rbrp->rbr_cfgb); 2409 kick_p = &(rbrp->rbr_kick); 2410 rcfga_p->value = 0; 2411 rcfgb_p->value = 0; 2412 kick_p->value = 0; 2413 rbrp->rbr_addr = dmap->dma_cookie.dmac_laddress; 2414 rcfga_p->value = (rbrp->rbr_addr & 2415 (RBR_CFIG_A_STDADDR_MASK | RBR_CFIG_A_STDADDR_BASE_MASK)); 2416 rcfga_p->value |= ((uint64_t)rbrp->rbb_max << RBR_CFIG_A_LEN_SHIFT); 2417 2418 /* XXXX: how to choose packet buffer sizes */ 2419 rcfgb_p->bits.bufsz0 = rbrp->pkt_buf_size0; 2420 rcfgb_p->bits.vld0 = 1; 2421 rcfgb_p->bits.bufsz1 = rbrp->pkt_buf_size1; 2422 rcfgb_p->bits.vld1 = 1; 2423 rcfgb_p->bits.bufsz2 = rbrp->pkt_buf_size2; 2424 rcfgb_p->bits.vld2 = 1; 2425 rcfgb_p->bits.bksize = hxgep->rx_bksize_code; 2426 2427 /* 2428 * For each buffer block, enter receive block address to the ring. 2429 */ 2430 rbr_vaddrp = (uint32_t *)dmap->kaddrp; 2431 rbrp->rbr_desc_vp = (uint32_t *)dmap->kaddrp; 2432 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2433 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2434 "rbr_vaddrp $%p", dma_channel, rbr_vaddrp)); 2435 2436 rx_msg_ring = rbrp->rx_msg_ring; 2437 for (i = 0; i < rbrp->tnblocks; i++) { 2438 rx_msg_p = rx_msg_ring[i]; 2439 rx_msg_p->hxgep = hxgep; 2440 rx_msg_p->rx_rbr_p = rbrp; 2441 bkaddr = (uint32_t) 2442 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2443 RBR_BKADDR_SHIFT)); 2444 rx_msg_p->free = B_FALSE; 2445 rx_msg_p->max_usage_cnt = 0xbaddcafe; 2446 2447 *rbr_vaddrp++ = bkaddr; 2448 } 2449 2450 kick_p->bits.bkadd = rbrp->rbb_max; 2451 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 2452 2453 rbrp->rbr_rd_index = 0; 2454 2455 rbrp->rbr_consumed = 0; 2456 rbrp->rbr_use_bcopy = B_TRUE; 2457 rbrp->rbr_bufsize_type = RCR_PKTBUFSZ_0; 2458 2459 /* 2460 * Do bcopy on packets greater than bcopy size once the lo threshold is 2461 * reached. This lo threshold should be less than the hi threshold. 2462 * 2463 * Do bcopy on every packet once the hi threshold is reached. 2464 */ 2465 if (hxge_rx_threshold_lo >= hxge_rx_threshold_hi) { 2466 /* default it to use hi */ 2467 hxge_rx_threshold_lo = hxge_rx_threshold_hi; 2468 } 2469 if (hxge_rx_buf_size_type > HXGE_RBR_TYPE2) { 2470 hxge_rx_buf_size_type = HXGE_RBR_TYPE2; 2471 } 2472 rbrp->rbr_bufsize_type = hxge_rx_buf_size_type; 2473 2474 switch (hxge_rx_threshold_hi) { 2475 default: 2476 case HXGE_RX_COPY_NONE: 2477 /* Do not do bcopy at all */ 2478 rbrp->rbr_use_bcopy = B_FALSE; 2479 rbrp->rbr_threshold_hi = rbrp->rbb_max; 2480 break; 2481 2482 case HXGE_RX_COPY_1: 2483 case HXGE_RX_COPY_2: 2484 case HXGE_RX_COPY_3: 2485 case HXGE_RX_COPY_4: 2486 case HXGE_RX_COPY_5: 2487 case HXGE_RX_COPY_6: 2488 case HXGE_RX_COPY_7: 2489 rbrp->rbr_threshold_hi = 2490 rbrp->rbb_max * (hxge_rx_threshold_hi) / 2491 HXGE_RX_BCOPY_SCALE; 2492 break; 2493 2494 case HXGE_RX_COPY_ALL: 2495 rbrp->rbr_threshold_hi = 0; 2496 break; 2497 } 2498 2499 switch (hxge_rx_threshold_lo) { 2500 default: 2501 case HXGE_RX_COPY_NONE: 2502 /* Do not do bcopy at all */ 2503 if (rbrp->rbr_use_bcopy) { 2504 rbrp->rbr_use_bcopy = B_FALSE; 2505 } 2506 rbrp->rbr_threshold_lo = rbrp->rbb_max; 2507 break; 2508 2509 case HXGE_RX_COPY_1: 2510 case HXGE_RX_COPY_2: 2511 case HXGE_RX_COPY_3: 2512 case HXGE_RX_COPY_4: 2513 case HXGE_RX_COPY_5: 2514 case HXGE_RX_COPY_6: 2515 case HXGE_RX_COPY_7: 2516 rbrp->rbr_threshold_lo = 2517 rbrp->rbb_max * (hxge_rx_threshold_lo) / 2518 HXGE_RX_BCOPY_SCALE; 2519 break; 2520 2521 case HXGE_RX_COPY_ALL: 2522 rbrp->rbr_threshold_lo = 0; 2523 break; 2524 } 2525 2526 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2527 "hxge_map_rxdma_channel_cfg_ring: channel %d rbb_max %d " 2528 "rbrp->rbr_bufsize_type %d rbb_threshold_hi %d " 2529 "rbb_threshold_lo %d", 2530 dma_channel, rbrp->rbb_max, rbrp->rbr_bufsize_type, 2531 rbrp->rbr_threshold_hi, rbrp->rbr_threshold_lo)); 2532 2533 /* Map in the receive completion ring */ 2534 rcrp = (p_rx_rcr_ring_t)KMEM_ZALLOC(sizeof (rx_rcr_ring_t), KM_SLEEP); 2535 rcrp->rdc = dma_channel; 2536 2537 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 2538 rcrp->comp_size = hxge_port_rcr_size; 2539 rcrp->comp_wrap_mask = hxge_port_rcr_size - 1; 2540 2541 rcrp->max_receive_pkts = hxge_max_rx_pkts; 2542 2543 cntl_dmap = *dma_rcr_cntl_p; 2544 2545 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 2546 hxge_setup_dma_common(dmap, cntl_dmap, rcrp->comp_size, 2547 sizeof (rcr_entry_t)); 2548 rcrp->comp_rd_index = 0; 2549 rcrp->comp_wt_index = 0; 2550 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 2551 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 2552 #if defined(__i386) 2553 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2554 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2555 #else 2556 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 2557 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 2558 #endif 2559 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 2560 (hxge_port_rcr_size - 1); 2561 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 2562 (hxge_port_rcr_size - 1); 2563 2564 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 2565 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 2566 2567 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2568 "==> hxge_map_rxdma_channel_cfg_ring: channel %d " 2569 "rbr_vaddrp $%p rcr_desc_rd_head_p $%p " 2570 "rcr_desc_rd_head_pp $%p rcr_desc_rd_last_p $%p " 2571 "rcr_desc_rd_last_pp $%p ", 2572 dma_channel, rbr_vaddrp, rcrp->rcr_desc_rd_head_p, 2573 rcrp->rcr_desc_rd_head_pp, rcrp->rcr_desc_last_p, 2574 rcrp->rcr_desc_last_pp)); 2575 2576 /* 2577 * Zero out buffer block ring descriptors. 2578 */ 2579 bzero((caddr_t)dmap->kaddrp, dmap->alength); 2580 rcrp->intr_timeout = hxgep->intr_timeout; 2581 rcrp->intr_threshold = hxgep->intr_threshold; 2582 rcrp->full_hdr_flag = B_FALSE; 2583 rcrp->sw_priv_hdr_len = 0; 2584 2585 cfga_p = &(rcrp->rcr_cfga); 2586 cfgb_p = &(rcrp->rcr_cfgb); 2587 cfga_p->value = 0; 2588 cfgb_p->value = 0; 2589 rcrp->rcr_addr = dmap->dma_cookie.dmac_laddress; 2590 2591 cfga_p->value = (rcrp->rcr_addr & 2592 (RCRCFIG_A_STADDR_MASK | RCRCFIG_A_STADDR_BASE_MASK)); 2593 2594 cfga_p->value |= ((uint64_t)rcrp->comp_size << RCRCFIG_A_LEN_SHIF); 2595 2596 /* 2597 * Timeout should be set based on the system clock divider. The 2598 * following timeout value of 1 assumes that the granularity (1000) is 2599 * 3 microseconds running at 300MHz. 2600 */ 2601 cfgb_p->bits.pthres = rcrp->intr_threshold; 2602 cfgb_p->bits.timeout = rcrp->intr_timeout; 2603 cfgb_p->bits.entout = 1; 2604 2605 /* Map in the mailbox */ 2606 cntl_dmap = *dma_mbox_cntl_p; 2607 mboxp = (p_rx_mbox_t)KMEM_ZALLOC(sizeof (rx_mbox_t), KM_SLEEP); 2608 dmap = (p_hxge_dma_common_t)&mboxp->rx_mbox; 2609 hxge_setup_dma_common(dmap, cntl_dmap, 1, sizeof (rxdma_mailbox_t)); 2610 cfig1_p = (rdc_rx_cfg1_t *)&mboxp->rx_cfg1; 2611 cfig2_p = (rdc_rx_cfg2_t *)&mboxp->rx_cfg2; 2612 cfig1_p->value = cfig2_p->value = 0; 2613 2614 mboxp->mbox_addr = dmap->dma_cookie.dmac_laddress; 2615 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2616 "==> hxge_map_rxdma_channel_cfg_ring: " 2617 "channel %d cfg1 0x%016llx cfig2 0x%016llx cookie 0x%016llx", 2618 dma_channel, cfig1_p->value, cfig2_p->value, 2619 mboxp->mbox_addr)); 2620 2621 dmaaddrp = (uint32_t)((dmap->dma_cookie.dmac_laddress >> 32) & 0xfff); 2622 cfig1_p->bits.mbaddr_h = dmaaddrp; 2623 2624 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 0xffffffff); 2625 dmaaddrp = (uint32_t)(dmap->dma_cookie.dmac_laddress & 2626 RXDMA_CFIG2_MBADDR_L_MASK); 2627 2628 cfig2_p->bits.mbaddr_l = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT); 2629 2630 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2631 "==> hxge_map_rxdma_channel_cfg_ring: channel %d damaddrp $%p " 2632 "cfg1 0x%016llx cfig2 0x%016llx", 2633 dma_channel, dmaaddrp, cfig1_p->value, cfig2_p->value)); 2634 2635 cfig2_p->bits.full_hdr = rcrp->full_hdr_flag; 2636 cfig2_p->bits.offset = rcrp->sw_priv_hdr_len; 2637 2638 rbrp->rx_rcr_p = rcrp; 2639 rcrp->rx_rbr_p = rbrp; 2640 *rcr_p = rcrp; 2641 *rx_mbox_p = mboxp; 2642 2643 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2644 "<== hxge_map_rxdma_channel_cfg_ring status 0x%08x", status)); 2645 return (status); 2646 } 2647 2648 /*ARGSUSED*/ 2649 static void 2650 hxge_unmap_rxdma_channel_cfg_ring(p_hxge_t hxgep, 2651 p_rx_rcr_ring_t rcr_p, p_rx_mbox_t rx_mbox_p) 2652 { 2653 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2654 "==> hxge_unmap_rxdma_channel_cfg_ring: channel %d", rcr_p->rdc)); 2655 2656 KMEM_FREE(rcr_p, sizeof (rx_rcr_ring_t)); 2657 KMEM_FREE(rx_mbox_p, sizeof (rx_mbox_t)); 2658 2659 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2660 "<== hxge_unmap_rxdma_channel_cfg_ring")); 2661 } 2662 2663 static hxge_status_t 2664 hxge_map_rxdma_channel_buf_ring(p_hxge_t hxgep, uint16_t channel, 2665 p_hxge_dma_common_t *dma_buf_p, 2666 p_rx_rbr_ring_t *rbr_p, uint32_t num_chunks) 2667 { 2668 p_rx_rbr_ring_t rbrp; 2669 p_hxge_dma_common_t dma_bufp, tmp_bufp; 2670 p_rx_msg_t *rx_msg_ring; 2671 p_rx_msg_t rx_msg_p; 2672 p_mblk_t mblk_p; 2673 2674 rxring_info_t *ring_info; 2675 hxge_status_t status = HXGE_OK; 2676 int i, j, index; 2677 uint32_t size, bsize, nblocks, nmsgs; 2678 2679 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2680 "==> hxge_map_rxdma_channel_buf_ring: channel %d", channel)); 2681 2682 dma_bufp = tmp_bufp = *dma_buf_p; 2683 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2684 " hxge_map_rxdma_channel_buf_ring: channel %d to map %d " 2685 "chunks bufp 0x%016llx", channel, num_chunks, dma_bufp)); 2686 2687 nmsgs = 0; 2688 for (i = 0; i < num_chunks; i++, tmp_bufp++) { 2689 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2690 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2691 "bufp 0x%016llx nblocks %d nmsgs %d", 2692 channel, tmp_bufp, tmp_bufp->nblocks, nmsgs)); 2693 nmsgs += tmp_bufp->nblocks; 2694 } 2695 if (!nmsgs) { 2696 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2697 "<== hxge_map_rxdma_channel_buf_ring: channel %d " 2698 "no msg blocks", channel)); 2699 status = HXGE_ERROR; 2700 goto hxge_map_rxdma_channel_buf_ring_exit; 2701 } 2702 rbrp = (p_rx_rbr_ring_t)KMEM_ZALLOC(sizeof (rx_rbr_ring_t), KM_SLEEP); 2703 2704 size = nmsgs * sizeof (p_rx_msg_t); 2705 rx_msg_ring = KMEM_ZALLOC(size, KM_SLEEP); 2706 ring_info = (rxring_info_t *)KMEM_ZALLOC(sizeof (rxring_info_t), 2707 KM_SLEEP); 2708 2709 MUTEX_INIT(&rbrp->lock, NULL, MUTEX_DRIVER, 2710 (void *) hxgep->interrupt_cookie); 2711 MUTEX_INIT(&rbrp->post_lock, NULL, MUTEX_DRIVER, 2712 (void *) hxgep->interrupt_cookie); 2713 rbrp->rdc = channel; 2714 rbrp->num_blocks = num_chunks; 2715 rbrp->tnblocks = nmsgs; 2716 rbrp->rbb_max = nmsgs; 2717 rbrp->rbr_max_size = nmsgs; 2718 rbrp->rbr_wrap_mask = (rbrp->rbb_max - 1); 2719 2720 /* 2721 * Buffer sizes suggested by NIU architect. 256, 512 and 2K. 2722 */ 2723 2724 rbrp->pkt_buf_size0 = RBR_BUFSZ0_256B; 2725 rbrp->pkt_buf_size0_bytes = RBR_BUFSZ0_256_BYTES; 2726 rbrp->hpi_pkt_buf_size0 = SIZE_256B; 2727 2728 rbrp->pkt_buf_size1 = RBR_BUFSZ1_1K; 2729 rbrp->pkt_buf_size1_bytes = RBR_BUFSZ1_1K_BYTES; 2730 rbrp->hpi_pkt_buf_size1 = SIZE_1KB; 2731 2732 rbrp->block_size = hxgep->rx_default_block_size; 2733 2734 if (!hxgep->param_arr[param_accept_jumbo].value) { 2735 rbrp->pkt_buf_size2 = RBR_BUFSZ2_2K; 2736 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_2K_BYTES; 2737 rbrp->hpi_pkt_buf_size2 = SIZE_2KB; 2738 } else { 2739 rbrp->hpi_pkt_buf_size2 = SIZE_4KB; 2740 rbrp->pkt_buf_size2 = RBR_BUFSZ2_4K; 2741 rbrp->pkt_buf_size2_bytes = RBR_BUFSZ2_4K_BYTES; 2742 } 2743 2744 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2745 "==> hxge_map_rxdma_channel_buf_ring: channel %d " 2746 "actual rbr max %d rbb_max %d nmsgs %d " 2747 "rbrp->block_size %d default_block_size %d " 2748 "(config hxge_rbr_size %d hxge_rbr_spare_size %d)", 2749 channel, rbrp->rbr_max_size, rbrp->rbb_max, nmsgs, 2750 rbrp->block_size, hxgep->rx_default_block_size, 2751 hxge_rbr_size, hxge_rbr_spare_size)); 2752 2753 /* 2754 * Map in buffers from the buffer pool. 2755 * Note that num_blocks is the num_chunks. For Sparc, there is likely 2756 * only one chunk. For x86, there will be many chunks. 2757 * Loop over chunks. 2758 */ 2759 index = 0; 2760 for (i = 0; i < rbrp->num_blocks; i++, dma_bufp++) { 2761 bsize = dma_bufp->block_size; 2762 nblocks = dma_bufp->nblocks; 2763 #if defined(__i386) 2764 ring_info->buffer[i].dvma_addr = (uint32_t)dma_bufp->ioaddr_pp; 2765 #else 2766 ring_info->buffer[i].dvma_addr = (uint64_t)dma_bufp->ioaddr_pp; 2767 #endif 2768 ring_info->buffer[i].buf_index = i; 2769 ring_info->buffer[i].buf_size = dma_bufp->alength; 2770 ring_info->buffer[i].start_index = index; 2771 #if defined(__i386) 2772 ring_info->buffer[i].kaddr = (uint32_t)dma_bufp->kaddrp; 2773 #else 2774 ring_info->buffer[i].kaddr = (uint64_t)dma_bufp->kaddrp; 2775 #endif 2776 2777 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2778 " hxge_map_rxdma_channel_buf_ring: map channel %d " 2779 "chunk %d nblocks %d chunk_size %x block_size 0x%x " 2780 "dma_bufp $%p dvma_addr $%p", channel, i, 2781 dma_bufp->nblocks, 2782 ring_info->buffer[i].buf_size, bsize, dma_bufp, 2783 ring_info->buffer[i].dvma_addr)); 2784 2785 /* loop over blocks within a chunk */ 2786 for (j = 0; j < nblocks; j++) { 2787 if ((rx_msg_p = hxge_allocb(bsize, BPRI_LO, 2788 dma_bufp)) == NULL) { 2789 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2790 "allocb failed (index %d i %d j %d)", 2791 index, i, j)); 2792 goto hxge_map_rxdma_channel_buf_ring_fail1; 2793 } 2794 rx_msg_ring[index] = rx_msg_p; 2795 rx_msg_p->block_index = index; 2796 rx_msg_p->shifted_addr = (uint32_t) 2797 ((rx_msg_p->buf_dma.dma_cookie.dmac_laddress >> 2798 RBR_BKADDR_SHIFT)); 2799 /* 2800 * Too much output 2801 * HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2802 * "index %d j %d rx_msg_p $%p mblk %p", 2803 * index, j, rx_msg_p, rx_msg_p->rx_mblk_p)); 2804 */ 2805 mblk_p = rx_msg_p->rx_mblk_p; 2806 mblk_p->b_wptr = mblk_p->b_rptr + bsize; 2807 2808 rbrp->rbr_ref_cnt++; 2809 index++; 2810 rx_msg_p->buf_dma.dma_channel = channel; 2811 } 2812 } 2813 if (i < rbrp->num_blocks) { 2814 goto hxge_map_rxdma_channel_buf_ring_fail1; 2815 } 2816 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2817 "hxge_map_rxdma_channel_buf_ring: done buf init " 2818 "channel %d msg block entries %d", channel, index)); 2819 ring_info->block_size_mask = bsize - 1; 2820 rbrp->rx_msg_ring = rx_msg_ring; 2821 rbrp->dma_bufp = dma_buf_p; 2822 rbrp->ring_info = ring_info; 2823 2824 status = hxge_rxbuf_index_info_init(hxgep, rbrp); 2825 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, " hxge_map_rxdma_channel_buf_ring: " 2826 "channel %d done buf info init", channel)); 2827 2828 /* 2829 * Finally, permit hxge_freeb() to call hxge_post_page(). 2830 */ 2831 rbrp->rbr_state = RBR_POSTING; 2832 2833 *rbr_p = rbrp; 2834 2835 goto hxge_map_rxdma_channel_buf_ring_exit; 2836 2837 hxge_map_rxdma_channel_buf_ring_fail1: 2838 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2839 " hxge_map_rxdma_channel_buf_ring: failed channel (0x%x)", 2840 channel, status)); 2841 2842 index--; 2843 for (; index >= 0; index--) { 2844 rx_msg_p = rx_msg_ring[index]; 2845 if (rx_msg_p != NULL) { 2846 hxge_freeb(rx_msg_p); 2847 rx_msg_ring[index] = NULL; 2848 } 2849 } 2850 2851 hxge_map_rxdma_channel_buf_ring_fail: 2852 MUTEX_DESTROY(&rbrp->post_lock); 2853 MUTEX_DESTROY(&rbrp->lock); 2854 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 2855 KMEM_FREE(rx_msg_ring, size); 2856 KMEM_FREE(rbrp, sizeof (rx_rbr_ring_t)); 2857 2858 status = HXGE_ERROR; 2859 2860 hxge_map_rxdma_channel_buf_ring_exit: 2861 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2862 "<== hxge_map_rxdma_channel_buf_ring status 0x%08x", status)); 2863 2864 return (status); 2865 } 2866 2867 /*ARGSUSED*/ 2868 static void 2869 hxge_unmap_rxdma_channel_buf_ring(p_hxge_t hxgep, 2870 p_rx_rbr_ring_t rbr_p) 2871 { 2872 p_rx_msg_t *rx_msg_ring; 2873 p_rx_msg_t rx_msg_p; 2874 rxring_info_t *ring_info; 2875 int i; 2876 uint32_t size; 2877 2878 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2879 "==> hxge_unmap_rxdma_channel_buf_ring")); 2880 if (rbr_p == NULL) { 2881 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2882 "<== hxge_unmap_rxdma_channel_buf_ring: NULL rbrp")); 2883 return; 2884 } 2885 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2886 "==> hxge_unmap_rxdma_channel_buf_ring: channel %d", rbr_p->rdc)); 2887 2888 rx_msg_ring = rbr_p->rx_msg_ring; 2889 ring_info = rbr_p->ring_info; 2890 2891 if (rx_msg_ring == NULL || ring_info == NULL) { 2892 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2893 "<== hxge_unmap_rxdma_channel_buf_ring: " 2894 "rx_msg_ring $%p ring_info $%p", rx_msg_p, ring_info)); 2895 return; 2896 } 2897 2898 size = rbr_p->tnblocks * sizeof (p_rx_msg_t); 2899 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2900 " hxge_unmap_rxdma_channel_buf_ring: channel %d chunks %d " 2901 "tnblocks %d (max %d) size ptrs %d ", rbr_p->rdc, rbr_p->num_blocks, 2902 rbr_p->tnblocks, rbr_p->rbr_max_size, size)); 2903 2904 for (i = 0; i < rbr_p->tnblocks; i++) { 2905 rx_msg_p = rx_msg_ring[i]; 2906 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2907 " hxge_unmap_rxdma_channel_buf_ring: " 2908 "rx_msg_p $%p", rx_msg_p)); 2909 if (rx_msg_p != NULL) { 2910 hxge_freeb(rx_msg_p); 2911 rx_msg_ring[i] = NULL; 2912 } 2913 } 2914 2915 /* 2916 * We no longer may use the mutex <post_lock>. By setting 2917 * <rbr_state> to anything but POSTING, we prevent 2918 * hxge_post_page() from accessing a dead mutex. 2919 */ 2920 rbr_p->rbr_state = RBR_UNMAPPING; 2921 MUTEX_DESTROY(&rbr_p->post_lock); 2922 2923 MUTEX_DESTROY(&rbr_p->lock); 2924 KMEM_FREE(ring_info, sizeof (rxring_info_t)); 2925 KMEM_FREE(rx_msg_ring, size); 2926 2927 if (rbr_p->rbr_ref_cnt == 0) { 2928 /* This is the normal state of affairs. */ 2929 KMEM_FREE(rbr_p, sizeof (*rbr_p)); 2930 } else { 2931 /* 2932 * Some of our buffers are still being used. 2933 * Therefore, tell hxge_freeb() this ring is 2934 * unmapped, so it may free <rbr_p> for us. 2935 */ 2936 rbr_p->rbr_state = RBR_UNMAPPED; 2937 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 2938 "unmap_rxdma_buf_ring: %d %s outstanding.", 2939 rbr_p->rbr_ref_cnt, 2940 rbr_p->rbr_ref_cnt == 1 ? "msg" : "msgs")); 2941 } 2942 2943 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2944 "<== hxge_unmap_rxdma_channel_buf_ring")); 2945 } 2946 2947 static hxge_status_t 2948 hxge_rxdma_hw_start_common(p_hxge_t hxgep) 2949 { 2950 hxge_status_t status = HXGE_OK; 2951 2952 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 2953 2954 /* 2955 * Load the sharable parameters by writing to the function zero control 2956 * registers. These FZC registers should be initialized only once for 2957 * the entire chip. 2958 */ 2959 (void) hxge_init_fzc_rx_common(hxgep); 2960 2961 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start_common")); 2962 2963 return (status); 2964 } 2965 2966 static hxge_status_t 2967 hxge_rxdma_hw_start(p_hxge_t hxgep) 2968 { 2969 int i, ndmas; 2970 uint16_t channel; 2971 p_rx_rbr_rings_t rx_rbr_rings; 2972 p_rx_rbr_ring_t *rbr_rings; 2973 p_rx_rcr_rings_t rx_rcr_rings; 2974 p_rx_rcr_ring_t *rcr_rings; 2975 p_rx_mbox_areas_t rx_mbox_areas_p; 2976 p_rx_mbox_t *rx_mbox_p; 2977 hxge_status_t status = HXGE_OK; 2978 2979 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start")); 2980 2981 rx_rbr_rings = hxgep->rx_rbr_rings; 2982 rx_rcr_rings = hxgep->rx_rcr_rings; 2983 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 2984 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2985 "<== hxge_rxdma_hw_start: NULL ring pointers")); 2986 return (HXGE_ERROR); 2987 } 2988 2989 ndmas = rx_rbr_rings->ndmas; 2990 if (ndmas == 0) { 2991 HXGE_DEBUG_MSG((hxgep, RX_CTL, 2992 "<== hxge_rxdma_hw_start: no dma channel allocated")); 2993 return (HXGE_ERROR); 2994 } 2995 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 2996 "==> hxge_rxdma_hw_start (ndmas %d)", ndmas)); 2997 2998 /* 2999 * Scrub the RDC Rx DMA Prefetch Buffer Command. 3000 */ 3001 for (i = 0; i < 128; i++) { 3002 HXGE_REG_WR64(hxgep->hpi_handle, RDC_PREF_CMD, i); 3003 } 3004 3005 /* 3006 * Scrub Rx DMA Shadow Tail Command. 3007 */ 3008 for (i = 0; i < 64; i++) { 3009 HXGE_REG_WR64(hxgep->hpi_handle, RDC_SHADOW_CMD, i); 3010 } 3011 3012 /* 3013 * Scrub Rx DMA Control Fifo Command. 3014 */ 3015 for (i = 0; i < 512; i++) { 3016 HXGE_REG_WR64(hxgep->hpi_handle, RDC_CTRL_FIFO_CMD, i); 3017 } 3018 3019 /* 3020 * Scrub Rx DMA Data Fifo Command. 3021 */ 3022 for (i = 0; i < 1536; i++) { 3023 HXGE_REG_WR64(hxgep->hpi_handle, RDC_DATA_FIFO_CMD, i); 3024 } 3025 3026 /* 3027 * Reset the FIFO Error Stat. 3028 */ 3029 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_STAT, 0xFF); 3030 3031 /* Set the error mask to receive interrupts */ 3032 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3033 3034 rbr_rings = rx_rbr_rings->rbr_rings; 3035 rcr_rings = rx_rcr_rings->rcr_rings; 3036 rx_mbox_areas_p = hxgep->rx_mbox_areas_p; 3037 if (rx_mbox_areas_p) { 3038 rx_mbox_p = rx_mbox_areas_p->rxmbox_areas; 3039 } 3040 3041 for (i = 0; i < ndmas; i++) { 3042 channel = rbr_rings[i]->rdc; 3043 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3044 "==> hxge_rxdma_hw_start (ndmas %d) channel %d", 3045 ndmas, channel)); 3046 status = hxge_rxdma_start_channel(hxgep, channel, 3047 (p_rx_rbr_ring_t)rbr_rings[i], 3048 (p_rx_rcr_ring_t)rcr_rings[i], 3049 (p_rx_mbox_t)rx_mbox_p[i]); 3050 if (status != HXGE_OK) { 3051 goto hxge_rxdma_hw_start_fail1; 3052 } 3053 } 3054 3055 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_start: " 3056 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3057 rx_rbr_rings, rx_rcr_rings)); 3058 goto hxge_rxdma_hw_start_exit; 3059 3060 hxge_rxdma_hw_start_fail1: 3061 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3062 "==> hxge_rxdma_hw_start: disable " 3063 "(status 0x%x channel %d i %d)", status, channel, i)); 3064 for (; i >= 0; i--) { 3065 channel = rbr_rings[i]->rdc; 3066 (void) hxge_rxdma_stop_channel(hxgep, channel); 3067 } 3068 3069 hxge_rxdma_hw_start_exit: 3070 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3071 "==> hxge_rxdma_hw_start: (status 0x%x)", status)); 3072 return (status); 3073 } 3074 3075 static void 3076 hxge_rxdma_hw_stop(p_hxge_t hxgep) 3077 { 3078 int i, ndmas; 3079 uint16_t channel; 3080 p_rx_rbr_rings_t rx_rbr_rings; 3081 p_rx_rbr_ring_t *rbr_rings; 3082 p_rx_rcr_rings_t rx_rcr_rings; 3083 3084 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop")); 3085 3086 rx_rbr_rings = hxgep->rx_rbr_rings; 3087 rx_rcr_rings = hxgep->rx_rcr_rings; 3088 3089 if (rx_rbr_rings == NULL || rx_rcr_rings == NULL) { 3090 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3091 "<== hxge_rxdma_hw_stop: NULL ring pointers")); 3092 return; 3093 } 3094 3095 ndmas = rx_rbr_rings->ndmas; 3096 if (!ndmas) { 3097 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3098 "<== hxge_rxdma_hw_stop: no dma channel allocated")); 3099 return; 3100 } 3101 3102 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3103 "==> hxge_rxdma_hw_stop (ndmas %d)", ndmas)); 3104 3105 rbr_rings = rx_rbr_rings->rbr_rings; 3106 for (i = 0; i < ndmas; i++) { 3107 channel = rbr_rings[i]->rdc; 3108 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3109 "==> hxge_rxdma_hw_stop (ndmas %d) channel %d", 3110 ndmas, channel)); 3111 (void) hxge_rxdma_stop_channel(hxgep, channel); 3112 } 3113 3114 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_hw_stop: " 3115 "rx_rbr_rings 0x%016llx rings 0x%016llx", 3116 rx_rbr_rings, rx_rcr_rings)); 3117 3118 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_hw_stop")); 3119 } 3120 3121 static hxge_status_t 3122 hxge_rxdma_start_channel(p_hxge_t hxgep, uint16_t channel, 3123 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p) 3124 { 3125 hpi_handle_t handle; 3126 hpi_status_t rs = HPI_SUCCESS; 3127 rdc_stat_t cs; 3128 rdc_int_mask_t ent_mask; 3129 hxge_status_t status = HXGE_OK; 3130 3131 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel")); 3132 3133 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3134 3135 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "hxge_rxdma_start_channel: " 3136 "hpi handle addr $%p acc $%p", 3137 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3138 3139 /* Reset RXDMA channel */ 3140 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3141 if (rs != HPI_SUCCESS) { 3142 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3143 "==> hxge_rxdma_start_channel: " 3144 "reset rxdma failed (0x%08x channel %d)", 3145 status, channel)); 3146 return (HXGE_ERROR | rs); 3147 } 3148 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3149 "==> hxge_rxdma_start_channel: reset done: channel %d", channel)); 3150 3151 /* 3152 * Initialize the RXDMA channel specific FZC control configurations. 3153 * These FZC registers are pertaining to each RX channel (logical 3154 * pages). 3155 */ 3156 status = hxge_init_fzc_rxdma_channel(hxgep, 3157 channel, rbr_p, rcr_p, mbox_p); 3158 if (status != HXGE_OK) { 3159 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3160 "==> hxge_rxdma_start_channel: " 3161 "init fzc rxdma failed (0x%08x channel %d)", 3162 status, channel)); 3163 return (status); 3164 } 3165 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3166 "==> hxge_rxdma_start_channel: fzc done")); 3167 3168 /* 3169 * Zero out the shadow and prefetch ram. 3170 */ 3171 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3172 "==> hxge_rxdma_start_channel: ram done")); 3173 3174 /* Set up the interrupt event masks. */ 3175 ent_mask.value = 0; 3176 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3177 if (rs != HPI_SUCCESS) { 3178 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3179 "==> hxge_rxdma_start_channel: " 3180 "init rxdma event masks failed (0x%08x channel %d)", 3181 status, channel)); 3182 return (HXGE_ERROR | rs); 3183 } 3184 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3185 "event done: channel %d (mask 0x%016llx)", 3186 channel, ent_mask.value)); 3187 3188 /* 3189 * Load RXDMA descriptors, buffers, mailbox, initialise the receive DMA 3190 * channels and enable each DMA channel. 3191 */ 3192 status = hxge_enable_rxdma_channel(hxgep, 3193 channel, rbr_p, rcr_p, mbox_p); 3194 if (status != HXGE_OK) { 3195 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3196 " hxge_rxdma_start_channel: " 3197 " init enable rxdma failed (0x%08x channel %d)", 3198 status, channel)); 3199 return (status); 3200 } 3201 3202 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3203 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3204 3205 /* 3206 * Initialize the receive DMA control and status register 3207 * Note that rdc_stat HAS to be set after RBR and RCR rings are set 3208 */ 3209 cs.value = 0; 3210 cs.bits.mex = 1; 3211 cs.bits.rcr_thres = 1; 3212 cs.bits.rcr_to = 1; 3213 cs.bits.rbr_empty = 1; 3214 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3215 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3216 "channel %d rx_dma_cntl_stat 0x%0016llx", channel, cs.value)); 3217 if (status != HXGE_OK) { 3218 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3219 "==> hxge_rxdma_start_channel: " 3220 "init rxdma control register failed (0x%08x channel %d", 3221 status, channel)); 3222 return (status); 3223 } 3224 3225 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "==> hxge_rxdma_start_channel: " 3226 "control done - channel %d cs 0x%016llx", channel, cs.value)); 3227 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, 3228 "==> hxge_rxdma_start_channel: enable done")); 3229 HXGE_DEBUG_MSG((hxgep, MEM2_CTL, "<== hxge_rxdma_start_channel")); 3230 3231 return (HXGE_OK); 3232 } 3233 3234 static hxge_status_t 3235 hxge_rxdma_stop_channel(p_hxge_t hxgep, uint16_t channel) 3236 { 3237 hpi_handle_t handle; 3238 hpi_status_t rs = HPI_SUCCESS; 3239 rdc_stat_t cs; 3240 rdc_int_mask_t ent_mask; 3241 hxge_status_t status = HXGE_OK; 3242 3243 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel")); 3244 3245 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3246 3247 HXGE_DEBUG_MSG((hxgep, RX_CTL, "hxge_rxdma_stop_channel: " 3248 "hpi handle addr $%p acc $%p", 3249 hxgep->hpi_handle.regp, hxgep->hpi_handle.regh)); 3250 3251 /* Reset RXDMA channel */ 3252 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3253 if (rs != HPI_SUCCESS) { 3254 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3255 " hxge_rxdma_stop_channel: " 3256 " reset rxdma failed (0x%08x channel %d)", 3257 rs, channel)); 3258 return (HXGE_ERROR | rs); 3259 } 3260 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3261 "==> hxge_rxdma_stop_channel: reset done")); 3262 3263 /* Set up the interrupt event masks. */ 3264 ent_mask.value = RDC_INT_MASK_ALL; 3265 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3266 if (rs != HPI_SUCCESS) { 3267 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3268 "==> hxge_rxdma_stop_channel: " 3269 "set rxdma event masks failed (0x%08x channel %d)", 3270 rs, channel)); 3271 return (HXGE_ERROR | rs); 3272 } 3273 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3274 "==> hxge_rxdma_stop_channel: event done")); 3275 3276 /* Initialize the receive DMA control and status register */ 3277 cs.value = 0; 3278 status = hxge_init_rxdma_channel_cntl_stat(hxgep, channel, &cs); 3279 3280 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_stop_channel: control " 3281 " to default (all 0s) 0x%08x", cs.value)); 3282 3283 if (status != HXGE_OK) { 3284 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3285 " hxge_rxdma_stop_channel: init rxdma" 3286 " control register failed (0x%08x channel %d", 3287 status, channel)); 3288 return (status); 3289 } 3290 3291 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3292 "==> hxge_rxdma_stop_channel: control done")); 3293 3294 /* disable dma channel */ 3295 status = hxge_disable_rxdma_channel(hxgep, channel); 3296 3297 if (status != HXGE_OK) { 3298 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3299 " hxge_rxdma_stop_channel: " 3300 " init enable rxdma failed (0x%08x channel %d)", 3301 status, channel)); 3302 return (status); 3303 } 3304 3305 HXGE_DEBUG_MSG((hxgep, RX_CTL, 3306 "==> hxge_rxdma_stop_channel: disable done")); 3307 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_stop_channel")); 3308 3309 return (HXGE_OK); 3310 } 3311 3312 hxge_status_t 3313 hxge_rxdma_handle_sys_errors(p_hxge_t hxgep) 3314 { 3315 hpi_handle_t handle; 3316 p_hxge_rdc_sys_stats_t statsp; 3317 rdc_fifo_err_stat_t stat; 3318 hxge_status_t status = HXGE_OK; 3319 3320 handle = hxgep->hpi_handle; 3321 statsp = (p_hxge_rdc_sys_stats_t)&hxgep->statsp->rdc_sys_stats; 3322 3323 /* Clear the int_dbg register in case it is an injected err */ 3324 HXGE_REG_WR64(handle, RDC_FIFO_ERR_INT_DBG, 0x0); 3325 3326 /* Get the error status and clear the register */ 3327 HXGE_REG_RD64(handle, RDC_FIFO_ERR_STAT, &stat.value); 3328 HXGE_REG_WR64(handle, RDC_FIFO_ERR_STAT, stat.value); 3329 3330 if (stat.bits.rx_ctrl_fifo_sec) { 3331 statsp->ctrl_fifo_sec++; 3332 if (statsp->ctrl_fifo_sec == 1) 3333 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3334 "==> hxge_rxdma_handle_sys_errors: " 3335 "rx_ctrl_fifo_sec")); 3336 } 3337 3338 if (stat.bits.rx_ctrl_fifo_ded) { 3339 /* Global fatal error encountered */ 3340 statsp->ctrl_fifo_ded++; 3341 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3342 HXGE_FM_EREPORT_RDMC_CTRL_FIFO_DED); 3343 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3344 "==> hxge_rxdma_handle_sys_errors: " 3345 "fatal error: rx_ctrl_fifo_ded error")); 3346 } 3347 3348 if (stat.bits.rx_data_fifo_sec) { 3349 statsp->data_fifo_sec++; 3350 if (statsp->data_fifo_sec == 1) 3351 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3352 "==> hxge_rxdma_handle_sys_errors: " 3353 "rx_data_fifo_sec")); 3354 } 3355 3356 if (stat.bits.rx_data_fifo_ded) { 3357 /* Global fatal error encountered */ 3358 statsp->data_fifo_ded++; 3359 HXGE_FM_REPORT_ERROR(hxgep, NULL, 3360 HXGE_FM_EREPORT_RDMC_DATA_FIFO_DED); 3361 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3362 "==> hxge_rxdma_handle_sys_errors: " 3363 "fatal error: rx_data_fifo_ded error")); 3364 } 3365 3366 if (stat.bits.rx_ctrl_fifo_ded || stat.bits.rx_data_fifo_ded) { 3367 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3368 " hxge_rxdma_handle_sys_errors: fatal error\n")); 3369 status = hxge_rx_port_fatal_err_recover(hxgep); 3370 if (status == HXGE_OK) { 3371 FM_SERVICE_RESTORED(hxgep); 3372 } 3373 } 3374 3375 return (HXGE_OK); 3376 } 3377 3378 static hxge_status_t 3379 hxge_rxdma_fatal_err_recover(p_hxge_t hxgep, uint16_t channel) 3380 { 3381 hpi_handle_t handle; 3382 hpi_status_t rs = HPI_SUCCESS; 3383 hxge_status_t status = HXGE_OK; 3384 p_rx_rbr_ring_t rbrp; 3385 p_rx_rcr_ring_t rcrp; 3386 p_rx_mbox_t mboxp; 3387 rdc_int_mask_t ent_mask; 3388 p_hxge_dma_common_t dmap; 3389 int ring_idx; 3390 p_rx_msg_t rx_msg_p; 3391 int i; 3392 uint32_t hxge_port_rcr_size; 3393 uint64_t tmp; 3394 3395 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rxdma_fatal_err_recover")); 3396 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3397 "Recovering from RxDMAChannel#%d error...", channel)); 3398 3399 /* 3400 * Stop the dma channel waits for the stop done. If the stop done bit 3401 * is not set, then create an error. 3402 */ 3403 3404 handle = HXGE_DEV_HPI_HANDLE(hxgep); 3405 3406 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Rx DMA stop...")); 3407 3408 ring_idx = hxge_rxdma_get_ring_index(hxgep, channel); 3409 rbrp = (p_rx_rbr_ring_t)hxgep->rx_rbr_rings->rbr_rings[ring_idx]; 3410 rcrp = (p_rx_rcr_ring_t)hxgep->rx_rcr_rings->rcr_rings[ring_idx]; 3411 3412 MUTEX_ENTER(&rcrp->lock); 3413 MUTEX_ENTER(&rbrp->lock); 3414 MUTEX_ENTER(&rbrp->post_lock); 3415 3416 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA channel...")); 3417 3418 rs = hpi_rxdma_cfg_rdc_disable(handle, channel); 3419 if (rs != HPI_SUCCESS) { 3420 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3421 "hxge_disable_rxdma_channel:failed")); 3422 goto fail; 3423 } 3424 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxDMA interrupt...")); 3425 3426 /* Disable interrupt */ 3427 ent_mask.value = RDC_INT_MASK_ALL; 3428 rs = hpi_rxdma_event_mask(handle, OP_SET, channel, &ent_mask); 3429 if (rs != HPI_SUCCESS) { 3430 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3431 "Set rxdma event masks failed (channel %d)", channel)); 3432 } 3433 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel reset...")); 3434 3435 /* Reset RXDMA channel */ 3436 rs = hpi_rxdma_cfg_rdc_reset(handle, channel); 3437 if (rs != HPI_SUCCESS) { 3438 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3439 "Reset rxdma failed (channel %d)", channel)); 3440 goto fail; 3441 } 3442 hxge_port_rcr_size = hxgep->hxge_port_rcr_size; 3443 mboxp = (p_rx_mbox_t)hxgep->rx_mbox_areas_p->rxmbox_areas[ring_idx]; 3444 3445 rbrp->rbr_wr_index = (rbrp->rbb_max - 1); 3446 rbrp->rbr_rd_index = 0; 3447 3448 rcrp->comp_rd_index = 0; 3449 rcrp->comp_wt_index = 0; 3450 rcrp->rcr_desc_rd_head_p = rcrp->rcr_desc_first_p = 3451 (p_rcr_entry_t)DMA_COMMON_VPTR(rcrp->rcr_desc); 3452 #if defined(__i386) 3453 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3454 (p_rcr_entry_t)(uint32_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3455 #else 3456 rcrp->rcr_desc_rd_head_pp = rcrp->rcr_desc_first_pp = 3457 (p_rcr_entry_t)DMA_COMMON_IOADDR(rcrp->rcr_desc); 3458 #endif 3459 3460 rcrp->rcr_desc_last_p = rcrp->rcr_desc_rd_head_p + 3461 (hxge_port_rcr_size - 1); 3462 rcrp->rcr_desc_last_pp = rcrp->rcr_desc_rd_head_pp + 3463 (hxge_port_rcr_size - 1); 3464 3465 rcrp->rcr_tail_begin = DMA_COMMON_IOADDR(rcrp->rcr_desc); 3466 rcrp->rcr_tail_begin = (rcrp->rcr_tail_begin & 0x7ffffULL) >> 3; 3467 3468 dmap = (p_hxge_dma_common_t)&rcrp->rcr_desc; 3469 bzero((caddr_t)dmap->kaddrp, dmap->alength); 3470 3471 HXGE_DEBUG_MSG((hxgep, RX_CTL, "rbr entries = %d\n", 3472 rbrp->rbr_max_size)); 3473 3474 for (i = 0; i < rbrp->rbr_max_size; i++) { 3475 /* Reset all the buffers */ 3476 rx_msg_p = rbrp->rx_msg_ring[i]; 3477 rx_msg_p->ref_cnt = 1; 3478 rx_msg_p->free = B_TRUE; 3479 rx_msg_p->cur_usage_cnt = 0; 3480 rx_msg_p->max_usage_cnt = 0; 3481 rx_msg_p->pkt_buf_size = 0; 3482 } 3483 3484 HXGE_DEBUG_MSG((hxgep, RX_CTL, "RxDMA channel re-start...")); 3485 3486 status = hxge_rxdma_start_channel(hxgep, channel, rbrp, rcrp, mboxp); 3487 if (status != HXGE_OK) { 3488 goto fail; 3489 } 3490 3491 /* 3492 * The DMA channel may disable itself automatically. 3493 * The following is a work-around. 3494 */ 3495 HXGE_REG_RD64(handle, RDC_RX_CFG1, &tmp); 3496 rs = hpi_rxdma_cfg_rdc_enable(handle, channel); 3497 if (rs != HPI_SUCCESS) { 3498 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3499 "hpi_rxdma_cfg_rdc_enable (channel %d)", channel)); 3500 } 3501 3502 MUTEX_EXIT(&rbrp->post_lock); 3503 MUTEX_EXIT(&rbrp->lock); 3504 MUTEX_EXIT(&rcrp->lock); 3505 3506 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3507 "Recovery Successful, RxDMAChannel#%d Restored", channel)); 3508 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rxdma_fatal_err_recover")); 3509 3510 return (HXGE_OK); 3511 3512 fail: 3513 MUTEX_EXIT(&rbrp->post_lock); 3514 MUTEX_EXIT(&rbrp->lock); 3515 MUTEX_EXIT(&rcrp->lock); 3516 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3517 3518 return (HXGE_ERROR | rs); 3519 } 3520 3521 static hxge_status_t 3522 hxge_rx_port_fatal_err_recover(p_hxge_t hxgep) 3523 { 3524 hxge_status_t status = HXGE_OK; 3525 p_hxge_dma_common_t *dma_buf_p; 3526 uint16_t channel; 3527 int ndmas; 3528 int i; 3529 block_reset_t reset_reg; 3530 3531 HXGE_DEBUG_MSG((hxgep, RX_CTL, "==> hxge_rx_port_fatal_err_recover")); 3532 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovering from RDC error ...")); 3533 3534 /* Reset RDC block from PEU for this fatal error */ 3535 reset_reg.value = 0; 3536 reset_reg.bits.rdc_rst = 1; 3537 HXGE_REG_WR32(hxgep->hpi_handle, BLOCK_RESET, reset_reg.value); 3538 3539 /* Disable RxMAC */ 3540 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Disable RxMAC...\n")); 3541 if (hxge_rx_vmac_disable(hxgep) != HXGE_OK) 3542 goto fail; 3543 3544 HXGE_DELAY(1000); 3545 3546 /* Restore any common settings after PEU reset */ 3547 if (hxge_rxdma_hw_start_common(hxgep) != HXGE_OK) 3548 goto fail; 3549 3550 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Stop all RxDMA channels...")); 3551 3552 ndmas = hxgep->rx_buf_pool_p->ndmas; 3553 dma_buf_p = hxgep->rx_buf_pool_p->dma_buf_pool_p; 3554 3555 for (i = 0; i < ndmas; i++) { 3556 channel = ((p_hxge_dma_common_t)dma_buf_p[i])->dma_channel; 3557 if (hxge_rxdma_fatal_err_recover(hxgep, channel) != HXGE_OK) { 3558 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3559 "Could not recover channel %d", channel)); 3560 } 3561 } 3562 3563 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Reset RxMAC...")); 3564 3565 /* Reset RxMAC */ 3566 if (hxge_rx_vmac_reset(hxgep) != HXGE_OK) { 3567 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3568 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3569 goto fail; 3570 } 3571 3572 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-initialize RxMAC...")); 3573 3574 /* Re-Initialize RxMAC */ 3575 if ((status = hxge_rx_vmac_init(hxgep)) != HXGE_OK) { 3576 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3577 "hxge_rx_port_fatal_err_recover: Failed to reset RxMAC")); 3578 goto fail; 3579 } 3580 HXGE_DEBUG_MSG((hxgep, RX_CTL, "Re-enable RxMAC...")); 3581 3582 /* Re-enable RxMAC */ 3583 if ((status = hxge_rx_vmac_enable(hxgep)) != HXGE_OK) { 3584 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3585 "hxge_rx_port_fatal_err_recover: Failed to enable RxMAC")); 3586 goto fail; 3587 } 3588 3589 /* Reset the error mask since PEU reset cleared it */ 3590 HXGE_REG_WR64(hxgep->hpi_handle, RDC_FIFO_ERR_INT_MASK, 0x0); 3591 3592 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, 3593 "Recovery Successful, RxPort Restored")); 3594 HXGE_DEBUG_MSG((hxgep, RX_CTL, "<== hxge_rx_port_fatal_err_recover")); 3595 3596 return (HXGE_OK); 3597 fail: 3598 HXGE_ERROR_MSG((hxgep, HXGE_ERR_CTL, "Recovery failed")); 3599 return (status); 3600 } 3601