1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_HXGE_HXGE_IMPL_H 27 #define _SYS_HXGE_HXGE_IMPL_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #ifndef _ASM 34 #include <sys/types.h> 35 #include <sys/byteorder.h> 36 #include <sys/debug.h> 37 #include <sys/stropts.h> 38 #include <sys/stream.h> 39 #include <sys/strlog.h> 40 #include <sys/strsubr.h> 41 #include <sys/cmn_err.h> 42 #include <sys/vtrace.h> 43 #include <sys/kmem.h> 44 #include <sys/ddi.h> 45 #include <sys/sunddi.h> 46 #include <sys/strsun.h> 47 #include <sys/stat.h> 48 #include <sys/cpu.h> 49 #include <sys/kstat.h> 50 #include <inet/common.h> 51 #include <inet/ip.h> 52 #include <inet/ip6.h> 53 #include <sys/dlpi.h> 54 #include <inet/nd.h> 55 #include <netinet/in.h> 56 #include <sys/ethernet.h> 57 #include <sys/vlan.h> 58 #include <sys/pci.h> 59 #include <sys/taskq.h> 60 #include <sys/atomic.h> 61 62 #include <hxge_defs.h> 63 #include <hxge_peu.h> 64 #include <hxge_pfc.h> 65 #include <hxge_pfc_hw.h> 66 #include <hxge_vmac.h> 67 #include <hxge_fm.h> 68 #include <sys/netlb.h> 69 #include <sys/ddi_intr.h> 70 71 #include <sys/mac.h> 72 #include <sys/mac_impl.h> 73 #include <sys/mac_ether.h> 74 75 /* 76 * Handy macros (taken from bge driver) 77 */ 78 #define RBR_SIZE 4 79 #define DMA_COMMON_VPTR(area) ((area.kaddrp)) 80 #define DMA_COMMON_HANDLE(area) ((area.dma_handle)) 81 #define DMA_COMMON_ACC_HANDLE(area) ((area.acc_handle)) 82 #define DMA_COMMON_IOADDR(area) ((area.dma_cookie.dmac_laddress)) 83 #define DMA_COMMON_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_handle,\ 84 (area).offset, (area).alength, \ 85 (flag))) 86 #define DMA_COMMON_SYNC_OFFSET(area, bufoffset, len, flag) \ 87 ((void) ddi_dma_sync((area).dma_handle,\ 88 (area.offset + bufoffset), len, \ 89 (flag))) 90 91 #define NEXT_ENTRY(index, wrap) ((index + 1) & wrap) 92 #define NEXT_ENTRY_PTR(ptr, first, last) \ 93 ((ptr == last) ? first : (ptr + 1)) 94 95 /* 96 * HPI related macros 97 */ 98 #define HXGE_DEV_HPI_HANDLE(hxgep) (hxgep->hpi_handle) 99 100 #define HPI_PCI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_pci_handle.regh = ah) 101 #define HPI_PCI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_pci_handle.regp = ap) 102 103 #define HPI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_handle.regh = ah) 104 #define HPI_ADD_HANDLE_SET(hxgep, ap) \ 105 hxgep->hpi_handle.is_vraddr = B_FALSE; \ 106 hxgep->hpi_handle.function.instance = hxgep->instance; \ 107 hxgep->hpi_handle.function.function = 0; \ 108 hxgep->hpi_handle.hxgep = (void *) hxgep; \ 109 hxgep->hpi_handle.regp = ap; 110 111 #define HPI_REG_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_reg_handle.regh = ah) 112 #define HPI_REG_ADD_HANDLE_SET(hxgep, ap) \ 113 hxgep->hpi_reg_handle.is_vraddr = B_FALSE; \ 114 hxgep->hpi_handle.function.instance = hxgep->instance; \ 115 hxgep->hpi_handle.function.function = 0; \ 116 hxgep->hpi_reg_handle.hxgep = (void *) hxgep; \ 117 hxgep->hpi_reg_handle.regp = ap; 118 119 #define HPI_MSI_ACC_HANDLE_SET(hxgep, ah) (hxgep->hpi_msi_handle.regh = ah) 120 #define HPI_MSI_ADD_HANDLE_SET(hxgep, ap) (hxgep->hpi_msi_handle.regp = ap) 121 122 #define HPI_DMA_ACC_HANDLE_SET(dmap, ah) (dmap->hpi_handle.regh = ah) 123 #define HPI_DMA_ACC_HANDLE_GET(dmap) (dmap->hpi_handle.regh) 124 125 #define LDV_ON(ldv, vector) ((vector >> ldv) & 0x1) 126 127 typedef uint32_t hxge_status_t; 128 129 typedef enum { 130 DVMA, 131 DMA, 132 SDMA 133 } dma_method_t; 134 135 typedef enum { 136 BKSIZE_4K, 137 BKSIZE_8K, 138 BKSIZE_16K, 139 BKSIZE_32K 140 } hxge_rx_block_size_t; 141 142 #ifdef TX_ONE_BUF 143 #define TX_BCOPY_MAX 1514 144 #else 145 #define TX_BCOPY_MAX 2048 146 #define TX_BCOPY_SIZE 2048 147 #endif 148 149 #define TX_STREAM_MIN 512 150 #define TX_FASTDVMA_MIN 1024 151 152 #define HXGE_RDC_RCR_THRESHOLD_MAX 256 153 #define HXGE_RDC_RCR_TIMEOUT_MAX 64 154 #define HXGE_RDC_RCR_THRESHOLD_MIN 1 155 #define HXGE_RDC_RCR_TIMEOUT_MIN 1 156 157 #define HXGE_IS_VLAN_PACKET(ptr) \ 158 ((((struct ether_vlan_header *)ptr)->ether_tpid) == \ 159 htons(VLAN_ETHERTYPE)) 160 161 typedef enum { 162 USE_NONE, 163 USE_BCOPY, 164 USE_DVMA, 165 USE_DMA, 166 USE_SDMA 167 } dma_type_t; 168 169 struct _hxge_block_mv_t { 170 uint32_t msg_type; 171 dma_type_t dma_type; 172 }; 173 174 typedef struct _hxge_block_mv_t hxge_block_mv_t, *p_hxge_block_mv_t; 175 176 typedef struct ether_addr ether_addr_st, *p_ether_addr_t; 177 typedef struct ether_header ether_header_t, *p_ether_header_t; 178 typedef queue_t *p_queue_t; 179 typedef mblk_t *p_mblk_t; 180 181 /* 182 * Common DMA data elements. 183 */ 184 struct _hxge_dma_common_t { 185 uint16_t dma_channel; 186 void *kaddrp; 187 void *ioaddr_pp; 188 ddi_dma_cookie_t dma_cookie; 189 uint32_t ncookies; 190 191 ddi_dma_handle_t dma_handle; 192 hxge_os_acc_handle_t acc_handle; 193 hpi_handle_t hpi_handle; 194 195 size_t block_size; 196 uint32_t nblocks; 197 size_t alength; 198 uint_t offset; 199 uint_t dma_chunk_index; 200 void *orig_ioaddr_pp; 201 uint64_t orig_vatopa; 202 void *orig_kaddrp; 203 size_t orig_alength; 204 boolean_t contig_alloc_type; 205 }; 206 207 typedef struct _hxge_t hxge_t, *p_hxge_t; 208 typedef struct _hxge_dma_common_t hxge_dma_common_t, *p_hxge_dma_common_t; 209 210 typedef struct _hxge_dma_pool_t { 211 p_hxge_dma_common_t *dma_buf_pool_p; 212 uint32_t ndmas; 213 uint32_t *num_chunks; 214 boolean_t buf_allocated; 215 } hxge_dma_pool_t, *p_hxge_dma_pool_t; 216 217 /* 218 * Each logical device (69): 219 * - LDG # 220 * - flag bits 221 * - masks. 222 * - interrupt handler function. 223 * 224 * Generic system interrupt handler with two arguments: 225 * (hxge_sys_intr_t) 226 * Per device instance data structure 227 * Logical group data structure. 228 * 229 * Logical device interrupt handler with two arguments: 230 * (hxge_ldv_intr_t) 231 * Per device instance data structure 232 * Logical device number 233 */ 234 typedef struct _hxge_ldg_t hxge_ldg_t, *p_hxge_ldg_t; 235 typedef struct _hxge_ldv_t hxge_ldv_t, *p_hxge_ldv_t; 236 typedef uint_t (*hxge_sys_intr_t)(caddr_t arg1, caddr_t arg2); 237 typedef uint_t (*hxge_ldv_intr_t)(caddr_t arg1, caddr_t arg2); 238 239 /* 240 * Each logical device Group (64) needs to have the following 241 * configurations: 242 * - timer counter (6 bits) 243 * - timer resolution (20 bits, number of system clocks) 244 * - system data (7 bits) 245 */ 246 struct _hxge_ldg_t { 247 uint8_t ldg; /* logical group number */ 248 uint8_t vldg_index; 249 boolean_t arm; 250 boolean_t interrupted; 251 uint16_t ldg_timer; /* counter */ 252 uint8_t vector; 253 uint8_t nldvs; 254 p_hxge_ldv_t ldvp; 255 hxge_sys_intr_t sys_intr_handler; 256 p_hxge_t hxgep; 257 }; 258 259 struct _hxge_ldv_t { 260 uint8_t ldg_assigned; 261 uint8_t ldv; 262 boolean_t is_rxdma; 263 boolean_t is_txdma; 264 boolean_t is_vmac; 265 boolean_t is_syserr; 266 boolean_t is_pfc; 267 boolean_t use_timer; 268 uint8_t channel; 269 uint8_t vdma_index; 270 p_hxge_ldg_t ldgp; 271 uint8_t ldv_ldf_masks; 272 hxge_ldv_intr_t ldv_intr_handler; 273 p_hxge_t hxgep; 274 }; 275 276 typedef struct _pci_cfg_t { 277 uint16_t vendorid; 278 uint16_t devid; 279 uint16_t command; 280 uint16_t status; 281 uint8_t revid; 282 uint8_t res0; 283 uint16_t junk1; 284 uint8_t cache_line; 285 uint8_t latency; 286 uint8_t header; 287 uint8_t bist; 288 uint32_t base; 289 uint32_t base14; 290 uint32_t base18; 291 uint32_t base1c; 292 uint32_t base20; 293 uint32_t base24; 294 uint32_t base28; 295 uint32_t base2c; 296 uint32_t base30; 297 uint32_t res1[2]; 298 uint8_t int_line; 299 uint8_t int_pin; 300 uint8_t min_gnt; 301 uint8_t max_lat; 302 } pci_cfg_t, *p_pci_cfg_t; 303 304 typedef struct _dev_regs_t { 305 hxge_os_acc_handle_t hxge_pciregh; /* PCI config DDI IO handle */ 306 p_pci_cfg_t hxge_pciregp; /* mapped PCI registers */ 307 308 hxge_os_acc_handle_t hxge_regh; /* device DDI IO (BAR 0) */ 309 void *hxge_regp; /* mapped device registers */ 310 311 hxge_os_acc_handle_t hxge_msix_regh; /* MSI/X DDI handle (BAR 2) */ 312 void *hxge_msix_regp; /* MSI/X register */ 313 314 hxge_os_acc_handle_t hxge_romh; /* fcode rom handle */ 315 unsigned char *hxge_romp; /* fcode pointer */ 316 } dev_regs_t, *p_dev_regs_t; 317 318 typedef struct _nxge_mac_addr_t { 319 ether_addr_t addr; 320 uint_t flags; 321 } hxge_mac_addr_t; 322 323 /* 324 * Driver alternate mac address structure. 325 */ 326 typedef struct _hxge_mmac_t { 327 uint8_t total_factory_macs; 328 uint8_t num_mmac; 329 uint8_t num_factory_mmac; 330 hxge_mac_addr_t mac_pool[16]; 331 ether_addr_t factory_mac_pool[16]; 332 uint8_t naddrfree; /* number of alt mac addr available */ 333 } hxge_mmac_t; 334 335 /* 336 * mmac stats structure 337 */ 338 typedef struct _hxge_mmac_stats_t { 339 uint8_t mmac_max_cnt; 340 uint8_t mmac_avail_cnt; 341 struct ether_addr mmac_avail_pool[16]; 342 } hxge_mmac_stats_t, *p_hxge_mmac_stats_t; 343 344 #include <hxge_common_impl.h> 345 #include <hxge_common.h> 346 #include <hxge_rxdma.h> 347 #include <hxge_txdma.h> 348 #include <hxge_fzc.h> 349 #include <hxge_flow.h> 350 #include <hxge_virtual.h> 351 #include <hxge.h> 352 #include <sys/modctl.h> 353 #include <sys/pattr.h> 354 #include <hpi_vir.h> 355 356 /* 357 * Reconfiguring the network devices requires the net_config privilege 358 * in Solaris 10+. Prior to this, root privilege is required. In order 359 * that the driver binary can run on both S10+ and earlier versions, we 360 * make the decisiion as to which to use at runtime. These declarations 361 * allow for either (or both) to exist ... 362 */ 363 extern int secpolicy_net_config(const cred_t *, boolean_t); 364 extern void hxge_fm_report_error(p_hxge_t hxgep, 365 uint8_t err_chan, hxge_fm_ereport_id_t fm_ereport_id); 366 extern int fm_check_acc_handle(ddi_acc_handle_t); 367 extern int fm_check_dma_handle(ddi_dma_handle_t); 368 369 #pragma weak secpolicy_net_config 370 371 hxge_status_t hxge_classify_init(p_hxge_t hxgep); 372 hxge_status_t hxge_classify_uninit(p_hxge_t hxgep); 373 void hxge_put_tcam(p_hxge_t hxgep, p_mblk_t mp); 374 void hxge_get_tcam(p_hxge_t hxgep, p_mblk_t mp); 375 376 hxge_status_t hxge_classify_init_hw(p_hxge_t hxgep); 377 hxge_status_t hxge_classify_init_sw(p_hxge_t hxgep); 378 hxge_status_t hxge_classify_exit_sw(p_hxge_t hxgep); 379 hxge_status_t hxge_pfc_ip_class_config_all(p_hxge_t hxgep); 380 hxge_status_t hxge_pfc_ip_class_config(p_hxge_t hxgep, tcam_class_t l3_class, 381 uint32_t class_config); 382 hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t hxgep, 383 tcam_class_t l3_class, uint32_t *class_config); 384 385 hxge_status_t hxge_pfc_set_hash(p_hxge_t, uint32_t); 386 hxge_status_t hxge_pfc_config_tcam_enable(p_hxge_t); 387 hxge_status_t hxge_pfc_config_tcam_disable(p_hxge_t); 388 hxge_status_t hxge_pfc_ip_class_config(p_hxge_t, tcam_class_t, uint32_t); 389 hxge_status_t hxge_pfc_ip_class_config_get(p_hxge_t, tcam_class_t, uint32_t *); 390 hxge_status_t hxge_pfc_num_macs_get(p_hxge_t, uint32_t *); 391 hxge_status_t hxge_pfc_mac_addrs_get(p_hxge_t hxgep); 392 393 394 hxge_status_t hxge_pfc_hw_reset(p_hxge_t hxgep); 395 hxge_status_t hxge_pfc_handle_sys_errors(p_hxge_t hxgep); 396 397 /* hxge_kstats.c */ 398 void hxge_init_statsp(p_hxge_t); 399 void hxge_setup_kstats(p_hxge_t); 400 void hxge_destroy_kstats(p_hxge_t); 401 int hxge_port_kstat_update(kstat_t *, int); 402 403 int hxge_m_stat(void *arg, uint_t stat, uint64_t *val); 404 405 /* hxge_hw.c */ 406 void 407 hxge_hw_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 408 void hxge_loopback_ioctl(p_hxge_t, queue_t *, mblk_t *, struct iocblk *); 409 void hxge_global_reset(p_hxge_t); 410 uint_t hxge_intr(caddr_t arg1, caddr_t arg2); 411 void hxge_intr_enable(p_hxge_t hxgep); 412 void hxge_intr_disable(p_hxge_t hxgep); 413 void hxge_hw_id_init(p_hxge_t hxgep); 414 void hxge_hw_init_niu_common(p_hxge_t hxgep); 415 void hxge_intr_hw_enable(p_hxge_t hxgep); 416 void hxge_intr_hw_disable(p_hxge_t hxgep); 417 void hxge_hw_stop(p_hxge_t hxgep); 418 void hxge_global_reset(p_hxge_t hxgep); 419 void hxge_check_hw_state(p_hxge_t hxgep); 420 421 /* hxge_send.c. */ 422 uint_t hxge_reschedule(caddr_t arg); 423 424 /* hxge_ndd.c */ 425 void hxge_get_param_soft_properties(p_hxge_t); 426 void hxge_setup_param(p_hxge_t); 427 void hxge_init_param(p_hxge_t); 428 void hxge_destroy_param(p_hxge_t); 429 boolean_t hxge_check_rxdma_port_member(p_hxge_t, uint8_t); 430 boolean_t hxge_check_txdma_port_member(p_hxge_t, uint8_t); 431 int hxge_param_get_generic(p_hxge_t, queue_t *, mblk_t *, caddr_t); 432 int hxge_param_set_generic(p_hxge_t, queue_t *, mblk_t *, char *, caddr_t); 433 int hxge_get_default(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 434 int hxge_set_default(p_hxge_t, queue_t *, p_mblk_t, char *, caddr_t); 435 int hxge_nd_get_names(p_hxge_t, queue_t *, p_mblk_t, caddr_t); 436 int hxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size); 437 void hxge_param_ioctl(p_hxge_t hxgep, queue_t *, mblk_t *, struct iocblk *); 438 boolean_t hxge_nd_load(caddr_t *, char *, pfi_t, pfi_t, caddr_t); 439 void hxge_nd_free(caddr_t *); 440 int hxge_nd_getset(p_hxge_t, queue_t *, caddr_t, p_mblk_t); 441 boolean_t hxge_set_lb(p_hxge_t, queue_t *wq, p_mblk_t mp); 442 int hxge_param_rx_intr_pkts(p_hxge_t hxgep, queue_t *, mblk_t *, char *, 443 caddr_t); 444 int hxge_param_rx_intr_time(p_hxge_t hxgep, queue_t *, mblk_t *, char *, 445 caddr_t); 446 int hxge_param_set_ip_opt(p_hxge_t hxgep, queue_t *, mblk_t *, char *, caddr_t); 447 int hxge_param_get_ip_opt(p_hxge_t hxgep, queue_t *, mblk_t *, caddr_t); 448 449 /* hxge_virtual.c */ 450 hxge_status_t hxge_get_config_properties(p_hxge_t); 451 hxge_status_t hxge_init_fzc_txdma_channel(p_hxge_t hxgep, uint16_t channel, 452 p_tx_ring_t tx_ring_p, p_tx_mbox_t mbox_p); 453 hxge_status_t hxge_init_fzc_rxdma_channel(p_hxge_t hxgep, uint16_t channel, 454 p_rx_rbr_ring_t rbr_p, p_rx_rcr_ring_t rcr_p, p_rx_mbox_t mbox_p); 455 hxge_status_t hxge_init_fzc_rx_common(p_hxge_t hxgep); 456 hxge_status_t hxge_init_fzc_rxdma_channel_pages(p_hxge_t hxgep, 457 uint16_t channel, p_rx_rbr_ring_t rbr_p); 458 hxge_status_t hxge_init_fzc_txdma_channel_pages(p_hxge_t hxgep, 459 uint16_t channel, p_tx_ring_t tx_ring_p); 460 hxge_status_t hxge_intr_mask_mgmt_set(p_hxge_t hxgep, boolean_t on); 461 462 /* MAC functions */ 463 hxge_status_t hxge_vmac_init(p_hxge_t hxgep); 464 hxge_status_t hxge_link_init(p_hxge_t hxgep); 465 hxge_status_t hxge_tx_vmac_init(p_hxge_t hxgep); 466 hxge_status_t hxge_rx_vmac_init(p_hxge_t hxgep); 467 hxge_status_t hxge_tx_vmac_enable(p_hxge_t hxgep); 468 hxge_status_t hxge_tx_vmac_disable(p_hxge_t hxgep); 469 hxge_status_t hxge_rx_vmac_enable(p_hxge_t hxgep); 470 hxge_status_t hxge_rx_vmac_disable(p_hxge_t hxgep); 471 hxge_status_t hxge_tx_vmac_reset(p_hxge_t hxgep); 472 hxge_status_t hxge_rx_vmac_reset(p_hxge_t hxgep); 473 hxge_status_t hxge_add_mcast_addr(p_hxge_t, struct ether_addr *); 474 hxge_status_t hxge_del_mcast_addr(p_hxge_t, struct ether_addr *); 475 hxge_status_t hxge_set_mac_addr(p_hxge_t hxgep, struct ether_addr *addr); 476 hxge_status_t hxge_set_promisc(p_hxge_t hxgep, boolean_t on); 477 void hxge_save_cntrs(p_hxge_t hxgep); 478 int hxge_vmac_set_framesize(p_hxge_t hxgep); 479 480 void hxge_debug_msg(p_hxge_t, uint64_t, char *, ...); 481 482 #ifdef HXGE_DEBUG 483 char *hxge_dump_packet(char *addr, int size); 484 #endif 485 486 #endif /* !_ASM */ 487 488 #ifdef __cplusplus 489 } 490 #endif 491 492 #endif /* _SYS_HXGE_HXGE_IMPL_H */ 493