1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _HPI_RXDMA_H 27 #define _HPI_RXDMA_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <hpi.h> 36 #include <hxge_defs.h> 37 #include <hxge_pfc.h> 38 #include <hxge_pfc_hw.h> 39 #include <hxge_rdc_hw.h> 40 41 #define RXDMA_CFIG2_MBADDR_L_SHIFT 6 /* bit 31:6 */ 42 #define RXDMA_CFIG2_MBADDR_L_MASK 0x00000000ffffffc0ULL 43 44 #define RBR_CFIG_A_STDADDR_MASK 0x000000000003ffc0ULL 45 #define RBR_CFIG_A_STDADDR_BASE_MASK 0x00000ffffffc0000ULL 46 47 #define RCRCFIG_A_STADDR_SHIFT 6 /* bit 18:6 */ 48 #define RCRCFIG_A_STADDR_MASK 0x000000000007FFC0ULL 49 #define RCRCFIG_A_STADDR_BASE_SHIF 19 /* bit 43:19 */ 50 #define RCRCFIG_A_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 51 #define RCRCFIG_A_LEN_SHIF 48 /* bit 63:48 */ 52 #define RCRCFIG_A_LEN_MASK 0xFFFF000000000000ULL 53 54 #define RCR_FLSH_SHIFT 0 /* RW, bit 0:0 */ 55 #define RCR_FLSH_SET 0x0000000000000001ULL 56 #define RCR_FLSH_MASK 0x0000000000000001ULL 57 58 #define RBR_CFIG_A_LEN_SHIFT 48 /* bits 63:48 */ 59 #define RBR_CFIG_A_LEN_MASK 0xFFFF000000000000ULL 60 61 /* 62 * Buffer block descriptor 63 */ 64 typedef struct _rx_desc_t { 65 uint32_t block_addr; 66 } rx_desc_t, *p_rx_desc_t; 67 68 typedef enum _bsize { 69 SIZE_0B = 0x0, 70 SIZE_64B, 71 SIZE_128B, 72 SIZE_192B, 73 SIZE_256B, 74 SIZE_512B, 75 SIZE_1KB, 76 SIZE_2KB, 77 SIZE_4KB, 78 SIZE_8KB, 79 SIZE_16KB, 80 SIZE_32KB 81 } bsize_t; 82 83 typedef struct _rdc_desc_cfg_t { 84 uint8_t mbox_enable; /* Enable full (18b) header */ 85 uint8_t full_hdr; /* Enable full (18b) header */ 86 uint8_t offset; /* 64 byte offsets */ 87 uint8_t valid2; /* size 2 is valid */ 88 bsize_t size2; /* Size 2 length */ 89 uint8_t valid1; /* size 1 is valid */ 90 bsize_t size1; /* Size 1 length */ 91 uint8_t valid0; /* size 0 is valid */ 92 bsize_t size0; /* Size 1 length */ 93 bsize_t page_size; /* Page or buffer Size */ 94 uint8_t rcr_timeout_enable; 95 uint8_t rcr_timeout; 96 uint16_t rcr_threshold; 97 uint16_t rcr_len; /* RBR Descriptor size (entries) */ 98 uint16_t rbr_len; /* RBR Descriptor size (entries) */ 99 uint64_t mbox_addr; /* Mailbox Address */ 100 uint64_t rcr_addr; /* RCR Address */ 101 uint64_t rbr_addr; /* RBB Address */ 102 } rdc_desc_cfg_t; 103 104 105 /* 106 * Register offset (0x800 bytes for each channel) for receive ring registers. 107 */ 108 #define HXGE_RXDMA_OFFSET(x, v, channel) (x + \ 109 (!v ? DMC_OFFSET(channel) : \ 110 RDMC_PIOVADDR_OFFSET(channel))) 111 112 #define RXDMA_REG_READ64(handle, reg, channel, data_p) {\ 113 HXGE_REG_RD64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ 114 channel)), (data_p))\ 115 } 116 117 #define RXDMA_REG_READ32(handle, reg, channel) \ 118 HXGE_HPI_PIO_READ32(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ 119 channel))) 120 121 #define RXDMA_REG_WRITE64(handle, reg, channel, data) {\ 122 HXGE_REG_WR64(handle, (HXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ 123 channel)), (data))\ 124 } 125 126 /* 127 * RX HPI error codes 128 */ 129 #define RXDMA_ER_ST (RXDMA_BLK_ID << HPI_BLOCK_ID_SHIFT) 130 #define RXDMA_ID_SHIFT(n) (n << HPI_PORT_CHAN_SHIFT) 131 132 #define HPI_RXDMA_ERROR RXDMA_ER_ST 133 134 #define HPI_RXDMA_SW_PARAM_ERROR (HPI_RXDMA_ERROR | 0x40) 135 #define HPI_RXDMA_HW_ERROR (HPI_RXDMA_ERROR | 0x80) 136 137 #define HPI_RXDMA_RDC_INVALID (HPI_RXDMA_ERROR | CHANNEL_INVALID) 138 #define HPI_RXDMA_RESET_ERR (HPI_RXDMA_HW_ERROR | RESET_FAILED) 139 #define HPI_RXDMA_BUFSZIE_INVALID (HPI_RXDMA_SW_PARAM_ERROR | 0x0000b) 140 #define HPI_RXDMA_RBRSZIE_INVALID (HPI_RXDMA_SW_PARAM_ERROR | 0x0000c) 141 #define HPI_RXDMA_RCRSZIE_INVALID (HPI_RXDMA_SW_PARAM_ERROR | 0x0000d) 142 143 #define HPI_RXDMA_CHANNEL_INVALID(n) (RXDMA_ID_SHIFT(n) | \ 144 HPI_RXDMA_ERROR | CHANNEL_INVALID) 145 #define HPI_RXDMA_OPCODE_INVALID(n) (RXDMA_ID_SHIFT(n) | \ 146 HPI_RXDMA_ERROR | OPCODE_INVALID) 147 148 #define HPI_RXDMA_ERROR_ENCODE(err, rdc) \ 149 (RXDMA_ID_SHIFT(rdc) | RXDMA_ER_ST | err) 150 151 #define RXDMA_CHANNEL_VALID(rdc) \ 152 ((rdc < HXGE_MAX_RDCS)) 153 154 #define RXDMA_BUFF_OFFSET_VALID(offset) \ 155 ((offset == SW_OFFSET_NO_OFFSET) || \ 156 (offset == SW_OFFSET_64) || \ 157 (offset == SW_OFFSET_128)) 158 159 #define RXDMA_RCR_TO_VALID(tov) ((tov) && (tov < 64)) 160 #define RXDMA_RCR_THRESH_VALID(thresh) ((thresh) && (thresh < 512)) 161 162 #define hpi_rxdma_rdc_rcr_flush(handle, rdc) \ 163 RXDMA_REG_WRITE64(handle, RDC_RCR_FLUSH, rdc, \ 164 (RCR_FLSH_SET << RCR_FLSH_SHIFT)) 165 #define hpi_rxdma_rdc_rbr_kick(handle, rdc, num_buffers) \ 166 RXDMA_REG_WRITE64(handle, RDC_RBR_KICK, rdc, num_buffers) 167 168 hpi_status_t hpi_rxdma_cfg_rdc_ring(hpi_handle_t handle, uint8_t rdc, 169 rdc_desc_cfg_t *rdc_desc_params); 170 hpi_status_t hpi_rxdma_cfg_clock_div_set(hpi_handle_t handle, uint16_t count); 171 hpi_status_t hpi_rxdma_cfg_logical_page_handle(hpi_handle_t handle, uint8_t rdc, 172 uint64_t pg_handle); 173 174 hpi_status_t hpi_rxdma_rdc_rbr_stat_get(hpi_handle_t handle, uint8_t rdc, 175 rdc_rbr_qlen_t *rbr_stat); 176 hpi_status_t hpi_rxdma_cfg_rdc_reset(hpi_handle_t handle, uint8_t rdc); 177 hpi_status_t hpi_rxdma_cfg_rdc_enable(hpi_handle_t handle, uint8_t rdc); 178 hpi_status_t hpi_rxdma_cfg_rdc_disable(hpi_handle_t handle, uint8_t rdc); 179 hpi_status_t hpi_rxdma_cfg_rdc_rcr_timeout(hpi_handle_t handle, uint8_t rdc, 180 uint8_t rcr_timeout); 181 182 hpi_status_t hpi_rxdma_cfg_rdc_rcr_threshold(hpi_handle_t handle, uint8_t rdc, 183 uint16_t rcr_threshold); 184 hpi_status_t hpi_rxdma_rdc_rcr_qlen_get(hpi_handle_t handle, 185 uint8_t rdc, uint16_t *qlen); 186 187 hpi_status_t hpi_rxdma_ring_perr_stat_get(hpi_handle_t handle, 188 rdc_pref_par_log_t *pre_log, rdc_pref_par_log_t *sha_log); 189 190 hpi_status_t hpi_rxdma_control_status(hpi_handle_t handle, io_op_t op_mode, 191 uint8_t channel, rdc_stat_t *cs_p); 192 hpi_status_t hpi_rxdma_event_mask(hpi_handle_t handle, io_op_t op_mode, 193 uint8_t channel, rdc_int_mask_t *mask_p); 194 hpi_status_t hpi_rxdma_channel_rbr_empty_clear(hpi_handle_t handle, 195 uint8_t channel); 196 197 #ifdef __cplusplus 198 } 199 #endif 200 201 #endif /* _HPI_RXDMA_H */ 202