xref: /titanic_52/usr/src/uts/common/io/hxge/hpi_pfc.h (revision 3dec9fcdd56adf1b4a563137b4915c8f2d83b881)
1*3dec9fcdSqs148142 /*
2*3dec9fcdSqs148142  * CDDL HEADER START
3*3dec9fcdSqs148142  *
4*3dec9fcdSqs148142  * The contents of this file are subject to the terms of the
5*3dec9fcdSqs148142  * Common Development and Distribution License (the "License").
6*3dec9fcdSqs148142  * You may not use this file except in compliance with the License.
7*3dec9fcdSqs148142  *
8*3dec9fcdSqs148142  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*3dec9fcdSqs148142  * or http://www.opensolaris.org/os/licensing.
10*3dec9fcdSqs148142  * See the License for the specific language governing permissions
11*3dec9fcdSqs148142  * and limitations under the License.
12*3dec9fcdSqs148142  *
13*3dec9fcdSqs148142  * When distributing Covered Code, include this CDDL HEADER in each
14*3dec9fcdSqs148142  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*3dec9fcdSqs148142  * If applicable, add the following below this CDDL HEADER, with the
16*3dec9fcdSqs148142  * fields enclosed by brackets "[]" replaced with your own identifying
17*3dec9fcdSqs148142  * information: Portions Copyright [yyyy] [name of copyright owner]
18*3dec9fcdSqs148142  *
19*3dec9fcdSqs148142  * CDDL HEADER END
20*3dec9fcdSqs148142  */
21*3dec9fcdSqs148142 
22*3dec9fcdSqs148142 /*
23*3dec9fcdSqs148142  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
24*3dec9fcdSqs148142  * Use is subject to license terms.
25*3dec9fcdSqs148142  */
26*3dec9fcdSqs148142 
27*3dec9fcdSqs148142 #ifndef _HPI_PFC_H
28*3dec9fcdSqs148142 #define	_HPI_PFC_H
29*3dec9fcdSqs148142 
30*3dec9fcdSqs148142 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31*3dec9fcdSqs148142 
32*3dec9fcdSqs148142 #ifdef __cplusplus
33*3dec9fcdSqs148142 extern "C" {
34*3dec9fcdSqs148142 #endif
35*3dec9fcdSqs148142 
36*3dec9fcdSqs148142 #include <hpi.h>
37*3dec9fcdSqs148142 #include <hxge_common.h>
38*3dec9fcdSqs148142 #include <hxge_pfc_hw.h>
39*3dec9fcdSqs148142 #include <hxge_pfc.h>
40*3dec9fcdSqs148142 
41*3dec9fcdSqs148142 typedef enum _tcam_op {
42*3dec9fcdSqs148142 	TCAM_RWC_STAT	= 0x1,
43*3dec9fcdSqs148142 	TCAM_RWC_MATCH	= 0x2
44*3dec9fcdSqs148142 } tcam_op_t;
45*3dec9fcdSqs148142 
46*3dec9fcdSqs148142 /*
47*3dec9fcdSqs148142  * HPI PFC ERROR Codes
48*3dec9fcdSqs148142  */
49*3dec9fcdSqs148142 #define	HPI_PFC_BLK_CODE	PFC_BLK_ID << 8
50*3dec9fcdSqs148142 #define	HPI_PFC_ERROR		(HPI_FAILURE | HPI_PFC_BLK_CODE)
51*3dec9fcdSqs148142 #define	HPI_TCAM_ERROR		0x10
52*3dec9fcdSqs148142 #define	HPI_FCRAM_ERROR		0x20
53*3dec9fcdSqs148142 #define	HPI_GEN_PFC		0x30
54*3dec9fcdSqs148142 #define	HPI_PFC_SW_PARAM_ERROR	0x40
55*3dec9fcdSqs148142 #define	HPI_PFC_HW_ERROR	0x80
56*3dec9fcdSqs148142 
57*3dec9fcdSqs148142 #define	HPI_PFC_RESET_ERROR	(HPI_PFC_ERROR | HPI_GEN_PFC | RESET_FAILED)
58*3dec9fcdSqs148142 #define	HPI_PFC_TCAM_WR_ERROR		\
59*3dec9fcdSqs148142 	(HPI_PFC_ERROR | HPI_TCAM_ERROR | WRITE_FAILED)
60*3dec9fcdSqs148142 #define	HPI_PFC_ASC_RAM_RD_ERROR	\
61*3dec9fcdSqs148142 	(HPI_PFC_ERROR | HPI_TCAM_ERROR | READ_FAILED)
62*3dec9fcdSqs148142 #define	HPI_PFC_ASC_RAM_WR_ERROR	\
63*3dec9fcdSqs148142 	(HPI_PFC_ERROR | HPI_TCAM_ERROR | WRITE_FAILED)
64*3dec9fcdSqs148142 
65*3dec9fcdSqs148142 #define	TCAM_CLASS_INVALID		\
66*3dec9fcdSqs148142 	(HPI_PFC_SW_PARAM_ERROR | 0xb)
67*3dec9fcdSqs148142 /* have only 0xc, 0xd, 0xe and 0xf left for sw error codes */
68*3dec9fcdSqs148142 #define	HPI_PFC_TCAM_HW_ERROR		\
69*3dec9fcdSqs148142 	(HPI_PFC_ERROR | HPI_PFC_HW_ERROR | HPI_TCAM_ERROR)
70*3dec9fcdSqs148142 
71*3dec9fcdSqs148142 #define	PFC_N_VLAN_MEMBERS		0x20
72*3dec9fcdSqs148142 
73*3dec9fcdSqs148142 #define	PFC_N_MAC_ADDRESSES		16
74*3dec9fcdSqs148142 #define	PFC_MAX_DMA_CHANNELS		4
75*3dec9fcdSqs148142 #define	PFC_MAC_ADDR_STEP		8
76*3dec9fcdSqs148142 
77*3dec9fcdSqs148142 #define	PFC_HASH_STEP			0x08
78*3dec9fcdSqs148142 
79*3dec9fcdSqs148142 #define	PFC_L2_CLASS_CONFIG_STEP	0x08
80*3dec9fcdSqs148142 
81*3dec9fcdSqs148142 #define	PFC_L3_CLASS_CONFIG_STEP	0x08
82*3dec9fcdSqs148142 
83*3dec9fcdSqs148142 #define	PFC_N_TCAM_ENTRIES		42
84*3dec9fcdSqs148142 
85*3dec9fcdSqs148142 #define	PFC_VLAN_REG_OFFSET(vlan_id) \
86*3dec9fcdSqs148142 	((((vlan_id_t)(vlan_id / PFC_N_VLAN_MEMBERS)) * 8) + PFC_VLAN_TABLE)
87*3dec9fcdSqs148142 #define	PFC_VLAN_BIT_OFFSET(vlan_id) \
88*3dec9fcdSqs148142 	(vlan_id % PFC_N_VLAN_MEMBERS)
89*3dec9fcdSqs148142 #define	PFC_MAC_ADDRESS(slot) \
90*3dec9fcdSqs148142 	((slot * PFC_MAC_ADDR_STEP) + PFC_MAC_ADDR)
91*3dec9fcdSqs148142 #define	PFC_MAC_ADDRESS_MASK(slot) \
92*3dec9fcdSqs148142 	((slot * PFC_MAC_ADDR_STEP) + PFC_MAC_ADDR_MASK)
93*3dec9fcdSqs148142 #define	PFC_HASH_ADDR(slot) \
94*3dec9fcdSqs148142 	((slot * PFC_HASH_STEP) + PFC_HASH_TABLE)
95*3dec9fcdSqs148142 
96*3dec9fcdSqs148142 #define	PFC_L2_CONFIG(slot) \
97*3dec9fcdSqs148142 	((slot * PFC_L2_CLASS_CONFIG_STEP) + PFC_L2_CLASS_CONFIG)
98*3dec9fcdSqs148142 #define	PFC_L3_CONFIG(slot) \
99*3dec9fcdSqs148142 	(((slot - TCAM_CLASS_TCP_IPV4) * PFC_L3_CLASS_CONFIG_STEP) + \
100*3dec9fcdSqs148142 	PFC_L3_CLASS_CONFIG)
101*3dec9fcdSqs148142 
102*3dec9fcdSqs148142 typedef uint16_t vlan_id_t;
103*3dec9fcdSqs148142 
104*3dec9fcdSqs148142 /*
105*3dec9fcdSqs148142  * PFC Control Register Functions
106*3dec9fcdSqs148142  */
107*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcam_enable(hpi_handle_t, boolean_t);
108*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_l2_hash(hpi_handle_t, boolean_t);
109*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcp_cksum(hpi_handle_t, boolean_t);
110*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_default_dma(hpi_handle_t, uint32_t);
111*3dec9fcdSqs148142 hpi_status_t hpi_pfc_mac_addr_enable(hpi_handle_t, uint32_t);
112*3dec9fcdSqs148142 hpi_status_t hpi_pfc_mac_addr_disable(hpi_handle_t, uint32_t);
113*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_force_csum(hpi_handle_t, boolean_t);
114*3dec9fcdSqs148142 
115*3dec9fcdSqs148142 /*
116*3dec9fcdSqs148142  * PFC vlan Functions
117*3dec9fcdSqs148142  */
118*3dec9fcdSqs148142 hpi_status_t hpi_pfc_cfg_vlan_table_clear(hpi_handle_t);
119*3dec9fcdSqs148142 hpi_status_t hpi_pfc_cfg_vlan_table_entry_clear(hpi_handle_t, vlan_id_t);
120*3dec9fcdSqs148142 hpi_status_t hpi_pfc_cfg_vlan_table_entry_set(hpi_handle_t, vlan_id_t);
121*3dec9fcdSqs148142 hpi_status_t hpi_pfc_cfg_vlan_control_set(hpi_handle_t, boolean_t,
122*3dec9fcdSqs148142     boolean_t, vlan_id_t);
123*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_vlan_parity_log(hpi_handle_t,
124*3dec9fcdSqs148142     pfc_vlan_par_err_log_t *);
125*3dec9fcdSqs148142 
126*3dec9fcdSqs148142 /*
127*3dec9fcdSqs148142  * PFC Mac Address Functions
128*3dec9fcdSqs148142  */
129*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_mac_address(hpi_handle_t, uint32_t, uint64_t);
130*3dec9fcdSqs148142 hpi_status_t hpi_pfc_clear_mac_address(hpi_handle_t, uint32_t);
131*3dec9fcdSqs148142 hpi_status_t hpi_pfc_clear_multicast_hash_table(hpi_handle_t, uint32_t);
132*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_multicast_hash_table(hpi_handle_t, uint32_t,
133*3dec9fcdSqs148142     uint64_t);
134*3dec9fcdSqs148142 
135*3dec9fcdSqs148142 /*
136*3dec9fcdSqs148142  * PFC L2 and L3 Config Functions.
137*3dec9fcdSqs148142  */
138*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_l2_class_slot(hpi_handle_t, uint16_t, boolean_t, int);
139*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_l3_class_config(hpi_handle_t handle, tcam_class_t slot,
140*3dec9fcdSqs148142     tcam_key_cfg_t *cfg);
141*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_l3_class_config(hpi_handle_t handle, tcam_class_t slot,
142*3dec9fcdSqs148142     tcam_key_cfg_t cfg);
143*3dec9fcdSqs148142 
144*3dec9fcdSqs148142 /*
145*3dec9fcdSqs148142  * PFC TCAM Functions
146*3dec9fcdSqs148142  */
147*3dec9fcdSqs148142 hpi_status_t hpi_pfc_tcam_invalidate_all(hpi_handle_t);
148*3dec9fcdSqs148142 hpi_status_t hpi_pfc_tcam_entry_invalidate(hpi_handle_t, uint32_t);
149*3dec9fcdSqs148142 hpi_status_t hpi_pfc_tcam_entry_write(hpi_handle_t, uint32_t,
150*3dec9fcdSqs148142     hxge_tcam_entry_t *);
151*3dec9fcdSqs148142 hpi_status_t hpi_pfc_tcam_entry_read(hpi_handle_t, uint32_t,
152*3dec9fcdSqs148142     hxge_tcam_entry_t *);
153*3dec9fcdSqs148142 hpi_status_t hpi_pfc_tcam_asc_ram_entry_read(hpi_handle_t handle,
154*3dec9fcdSqs148142     uint32_t location, uint64_t *ram_data);
155*3dec9fcdSqs148142 hpi_status_t hpi_pfc_tcam_asc_ram_entry_write(hpi_handle_t handle,
156*3dec9fcdSqs148142     uint32_t location, uint64_t ram_data);
157*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_tcam_parity_log(hpi_handle_t,
158*3dec9fcdSqs148142     pfc_tcam_par_err_log_t *);
159*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_tcam_auto_init(hpi_handle_t,
160*3dec9fcdSqs148142     pfc_auto_init_t *);
161*3dec9fcdSqs148142 
162*3dec9fcdSqs148142 /*
163*3dec9fcdSqs148142  * PFC TCP Control
164*3dec9fcdSqs148142  */
165*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcp_control_discard(hpi_handle_t, boolean_t);
166*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcp_control_fin(hpi_handle_t, boolean_t);
167*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcp_control_syn(hpi_handle_t, boolean_t);
168*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcp_control_rst(hpi_handle_t, boolean_t);
169*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcp_control_psh(hpi_handle_t, boolean_t);
170*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcp_control_ack(hpi_handle_t, boolean_t);
171*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_tcp_control_urg(hpi_handle_t, boolean_t);
172*3dec9fcdSqs148142 
173*3dec9fcdSqs148142 /*
174*3dec9fcdSqs148142  * PFC Hash Seed Value
175*3dec9fcdSqs148142  */
176*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_hash_seed_value(hpi_handle_t, uint32_t);
177*3dec9fcdSqs148142 
178*3dec9fcdSqs148142 /*
179*3dec9fcdSqs148142  * PFC Interrupt Management Functions
180*3dec9fcdSqs148142  */
181*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_interrupt_status(hpi_handle_t, pfc_int_status_t *);
182*3dec9fcdSqs148142 hpi_status_t hpi_pfc_clear_interrupt_status(hpi_handle_t);
183*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_interrupt_mask(hpi_handle_t, boolean_t,
184*3dec9fcdSqs148142     boolean_t, boolean_t);
185*3dec9fcdSqs148142 
186*3dec9fcdSqs148142 /*
187*3dec9fcdSqs148142  * PFC Packet Logs
188*3dec9fcdSqs148142  */
189*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_drop_log(hpi_handle_t, pfc_drop_log_t *);
190*3dec9fcdSqs148142 hpi_status_t hpi_pfc_set_drop_log_mask(hpi_handle_t, boolean_t,
191*3dec9fcdSqs148142     boolean_t, boolean_t, boolean_t, boolean_t);
192*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_bad_csum_counter(hpi_handle_t, uint64_t *);
193*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_drop_counter(hpi_handle_t, uint64_t *);
194*3dec9fcdSqs148142 
195*3dec9fcdSqs148142 hpi_status_t hpi_pfc_get_number_mac_addrs(hpi_handle_t handle,
196*3dec9fcdSqs148142     uint32_t *n_of_addrs);
197*3dec9fcdSqs148142 hpi_status_t hpi_pfc_mac_addr_get_i(hpi_handle_t handle, uint8_t *data,
198*3dec9fcdSqs148142     int slot);
199*3dec9fcdSqs148142 hpi_status_t hpi_pfc_num_macs_get(hpi_handle_t handle, uint8_t *data);
200*3dec9fcdSqs148142 
201*3dec9fcdSqs148142 #ifdef __cplusplus
202*3dec9fcdSqs148142 }
203*3dec9fcdSqs148142 #endif
204*3dec9fcdSqs148142 
205*3dec9fcdSqs148142 #endif /* !_HPI_PFC_H */
206