1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef HME_PHY_H 27 #define HME_PHY_H 28 29 /* DP83840 - 10/100 Mbps Physical layer from National semiconductor */ 30 31 /* 32 * MII supports a 16-bit register stack of upto 32, addressable through the 33 * MDIO and MDC serial port. 34 */ 35 #define HME_PHY_BMCR 00 /* Basic Mode Control Register */ 36 #define HME_PHY_BMSR 01 /* Basic Mode Status Register */ 37 #define HME_PHY_IDR1 02 /* PHY Identifier Register 1 */ 38 #define HME_PHY_IDR2 03 /* PHY Identifier Register 2 */ 39 #define HME_PHY_ANAR 04 /* Auto-Negotiation Advertisement Register */ 40 #define HME_PHY_ANLPAR 05 /* Auto-Negotiation Link Partner Ability Reg */ 41 #define HME_PHY_ANER 06 /* Auto-Negotiation Expansion Register */ 42 43 /* Registers 7-15 are reserved for future assignments by MII working group */ 44 /* Do not write to these registers */ 45 46 /* Registers 16-17 are reserved for future assignment by Vendor */ 47 /* Do not write to these registers */ 48 49 #define HME_PHY_DIS 18 /* Disconnect Counter */ 50 #define HME_PHY_FCSC 19 /* False Carrier Sense Counter */ 51 #define HME_PHY_NWAYTR 20 /* NWay Test Register */ 52 #define HME_PHY_REC 21 /* RX_ER Counter */ 53 #define HME_PHY_SRR 22 /* Silicon Revision Register */ 54 #define HME_PHY_CSC 23 /* CS Configuration Register */ 55 #define HME_PHY_LBREMR 24 /* Loopback, Bypass, Receiver Error Mask Reg */ 56 #define HME_PHY_AR 25 /* PHY Address Register */ 57 #define HME_PHY_VRES1 26 /* Reserverd for future assignement by vendor */ 58 #define HME_PHY_TPISR 27 /* 10 Mbps TPI Status Register */ 59 #define HME_PHY_NICR 28 /* 10 Mbps Network I/F Configuration Register */ 60 61 /* Registers 29-31 are reserved for future assignment by Vendor */ 62 /* Do not write to these registers */ 63 64 /* 65 * QSI 6612 Physical layer device specific registers. 66 * Addition Interface Technologies Group (NPG) 8/28/1997. 67 */ 68 #define HME_PHY_BTXPC 31 /* BASE-TX Phy control Register */ 69 70 /* ************************************************************************ */ 71 /* Register 00 Basic Mode Control Register */ 72 73 #define PHY_BMCR_RESET (1 << 15) /* Reset */ 74 #define PHY_BMCR_LPBK (1 << 14) /* Loopback of TXD<3:0> */ 75 #define PHY_BMCR_100M (1 << 13) /* Speed selection, 1=100Mbps */ 76 #define PHY_BMCR_ANE (1 << 12) /* Auto Negotiation Enable */ 77 #define PHY_BMCR_PWRDN (1 << 11) /* Power down */ 78 #define PHY_BMCR_ISOLATE (1 << 10) /* Isolate PHY from MII */ 79 #define PHY_BMCR_RAN (1 << 9) /* Restart Auto Negotiation */ 80 #define PHY_BMCR_FDX (1 << 8) /* Full Duplex */ 81 #define PHY_BMCR_COLTST (1 << 7) /* Collision Test */ 82 #define PHY_BMCR_RES1 (0x7f << 0) /* 0-6 Reserved */ 83 84 /* ************************************************************************ */ 85 /* Register 01 Basic Mode Status Register */ 86 87 #define PHY_BMSR_100T4 (1 << 15) /* PHY able to perform 100Base-T4 */ 88 #define PHY_BMSR_100FDX (1 << 14) /* PHY able to perform 100Base-TX FDX */ 89 #define PHY_BMSR_100HDX (1 << 13) /* PHY able to perform 100Base-TX HDX */ 90 #define PHY_BMSR_10FDX (1 << 12) /* PHY able to perform 10Base-T FDX */ 91 #define PHY_BMSR_10HDX (1 << 11) /* PHY able to perform 10Base-T HDX */ 92 #define PHY_BMSR_RES1 (0x1f << 6) /* 6-10 reserved */ 93 #define PHY_BMSR_ANC (1 << 5) /* Auto Negotiation Completed */ 94 #define PHY_BMSR_REMFLT (1 << 4) /* Remote Fault detected */ 95 #define PHY_BMSR_ACFG (1 << 3) /* Able to do Auto Link Negotiation */ 96 #define PHY_BMSR_LNKSTS (1 << 2) /* Link Status */ 97 #define PHY_BMSR_JABDET (1 << 1) /* Jabber Condition Detected */ 98 #define PHY_BMSR_EXTCAP (1 << 0) /* Extended Register Capability */ 99 100 #define PHY_CAPABILITY_MASK (PHY_BMSR_100FDX | PHY_BMSR_100HDX \ 101 | PHY_BMSR_10FDX | PHY_BMSR_10HDX) 102 103 /* ************************************************************************ */ 104 /* 105 * Registers 2 and 3 provide a 32 bit value which is a unique identifier 106 * for a particular type of PHY. A 24-bit Organizationally Unique Identifier 107 * (OUI) is defined with bit 1 as the MSB and bit 24 as the LSB. Bits 3-18 of 108 * the OUI are found in PHY Identifier Register 1 and bits 19-24 are found in 109 * PHY Identifier Register 2. 110 * 111 * The hexadecimal OUI code for NSC is 0x080017 . 112 */ 113 /* Register 02 PHY Identifier Register 1 */ 114 115 /* Register 03 PHY Identifier Register 2 */ 116 117 #define PHY_IDR2_OUILSB (0x3f << 10) /* Bits 19-24 of OUI */ 118 #define PHY_IDR2_VNDMDL (0x3f << 4) /* vendor Model no. */ 119 #define PHY_IDR2_MDLREV (0xf << 0) /* Model revision no. */ 120 121 /* ************************************************************************ */ 122 /* 123 * Register 04 Auto-Negotiation Advertisement Register (nway1Reg) 124 * This register will hold the different modes of operation to be advertised to 125 * the far-end PHY. 126 */ 127 128 #define PHY_ANAR_NP (1 << 15) /* Next Page bit */ 129 #define PHY_ANAR_ACK (1 << 14) /* Acks reception of Link Partner */ 130 /* Capability word */ 131 #define PHY_ANAR_RF (1 << 13) /* Advertise Remote Fault det. cap. */ 132 #define PHY_ANAR_RES1 (0x7 << 10) /* 10-12 reserved */ 133 #define PHY_ANAR_T4 (1 << 9) /* Advertise 100Base-T4 Capability */ 134 #define PHY_ANAR_TXFDX (1 << 8) /* Advertise 100Base-TX FDX Cap. */ 135 #define PHY_ANAR_TX (1 << 7) /* Advertise 100Base-TX Cap. */ 136 #define PHY_ANAR_10FDX (1 << 6) /* Advertise 10Base-T FDX Cap. */ 137 #define PHY_ANAR_10 (1 << 5) /* Advertise 10Base-T Cap. */ 138 #define PHY_ANAR_SELECT (0x1f << 0) /* Binary Encoded selector supported */ 139 /* this node. Currently only CSMA/CD */ 140 /* <00001> is specified */ 141 142 #define PHY_SELECTOR 1 /* Default selector for CSMA/CD */ 143 /* 144 * Priority scheme (from highest to lowest) for Auto Link Negotiation: 145 * 1 - 100Base-TX Full Duplex 146 * 2 - 100Base-T4 147 * 3 - 100Base-TX 148 * 4 - 10Base-T Full Duplex 149 * 5 - 10Base-T 150 */ 151 152 /* ************************************************************************ */ 153 /* 154 * Register 05 Auto-Negotiation Link Partner Ability Reg 155 * This register contains the Link Partners capabilities after NWay 156 * Auto-Negotiation is complete. 157 */ 158 159 #define PHY_ANLPAR_NP (1 << 15) /* Next page Bit */ 160 #define PHY_ANLPAR_ACK (1 << 14) /* Link Partner acks reception of our */ 161 /* capability data word */ 162 #define PHY_ANLPAR_RF (1 << 13) /* LP indicates Remote fault */ 163 #define PHY_ANLPAR_RES1 (0x7 << 10) /* 10-12 reserved */ 164 #define PHY_ANLPAR_T4 (1 << 9) /* 100Base-T4 supported by LP */ 165 #define PHY_ANLPAR_TXFDX (1 << 8) /* 100Base-TX FDX supp. by LP */ 166 #define PHY_ANLPAR_TX (1 << 7) /* 100Base-TX supp. by LP */ 167 #define PHY_ANLPAR_10FDX (1 << 6) /* 10Base-T FDX supp. by LP */ 168 #define PHY_ANLPAR_10 (1 << 5) /* 10Base-T supp. by LP */ 169 #define PHY_ANLPAR_SELECT (0x1f << 0) /* LP's binary encoded node selector */ 170 /* Currently only CSMA/CD is <00001> */ 171 /* is specified */ 172 173 /* ************************************************************************ */ 174 /* 175 * Register 06 Auto-Negotiation Expansion Register 176 * This register contains additional status for NWay Auto-Negotiation 177 */ 178 179 #define PHY_ANER_RES1 (0x7ff << 5) /* 5-15 reserved */ 180 #define PHY_ANER_MLF (1 << 4) /* Multiple Link faults occured */ 181 #define PHY_ANER_LPNP (1 << 3) /* LP supports Next Page negotiation */ 182 #define PHY_ANER_NPABLE (1 << 2) /* This node can send additional */ 183 /* Next Pages. Should be 0 for DP83840 */ 184 #define PHY_ANER_PAGERX (1 << 1) /* new LINK Code Word Page recvd. */ 185 #define PHY_ANER_LPNW (1 << 0) /* LP supports NWay Auto-negotiation */ 186 187 188 /* ************************************************************************ */ 189 190 /* Registers 7-15 are reserved for future assignments by MII working group */ 191 /* Do not write to these registers */ 192 193 /* Registers 16-17 are reserved for future assignment by Vendor */ 194 /* Do not write to these registers */ 195 196 /* ************************************************************************ */ 197 198 /* 199 * Register 18 Disconnect Counter 200 * This 16-bit counter is incremented for every disconnect event. It rolls over 201 * when full. 202 */ 203 204 /* ************************************************************************ */ 205 /* 206 * Register 19 False Carrier Sense Counter 207 * This 16-bit counter is incremented for each false carrier event (i.e. carrier 208 * assertion without JK detect). It freezes when full. 209 */ 210 211 /* ************************************************************************ */ 212 /* 213 * Register 20 NWay Test Register 214 */ 215 #define PHY_NWAYTR_RES1 (0xff << 8) /* 8-15 reserved */ 216 #define PHY_NWAYTR_LPBK (1 << 7) /* Puts NWay into Loopback mode */ 217 #define PHY_NWAYTR_RES2 (0x7f << 0) /* 0-6 reserved */ 218 219 /* ************************************************************************ */ 220 /* 221 * Register 21 RX_ER Counter 222 * This 16-bit counter is incremented once per valid packet (i.e. no collision 223 * occured during packet reception), if there is one or more receive error 224 * condition during the packet reception. The counter is incremented at the end 225 * of the packet reception. 226 */ 227 228 /* ************************************************************************ */ 229 /* 230 * Register 22 Silicon Revision Register 231 * Contains information on silicon revision 232 * This register will be incremented for any change made to the device. 233 */ 234 /* ************************************************************************ */ 235 /* 236 * Register 23 CS Configuration Register 237 */ 238 239 #define PHY_CSCR_NRZIDIS (1 << 15) /* NRZI disabled (for FDDI) */ 240 #define PHY_CSCR_RES1 (1 << 14) /* reserved */ 241 #define PHY_CSCR_TOCDIS (1 << 13) /* disable Timeout counter */ 242 /* in descrambler */ 243 #define PHY_CSCR_REPTR (1 << 12) /* Mode1: Node = 0, repeater = 1 */ 244 #define PHY_CSCR_ENCSEL (1 << 11) /* encoder: 0 = MLT-3, 1 = binary */ 245 #define PHY_CSCR_RES2 (0x7 << 8) /* 8-10 reserved */ 246 #define PHY_CSCR_CLK25M (1 << 7) /* Tristates CLK25M */ 247 #define PHY_CSCR_FLN100 (1 << 6) /* 0 = force good link in 100Mbps */ 248 #define PHY_CSCR_FCONN (1 << 5) /* 1 = bypass disconnect function */ 249 #define PHY_CSCR_TXOFF (1 << 4) /* 1 = Pulls TD from phaser ckt low */ 250 #define PHY_CSCR_RES3 (1 << 3) /* reserved */ 251 #define PHY_CSCR_CSTSEN (1 << 2) /* LED1 pin for connection status */ 252 #define PHY_CSCR_10FDXE (1 << 1) /* LED4 pin for 10Base-T FDX */ 253 #define PHY_CSCR_RES4 (1 << 0) /* reserved */ 254 255 /* ************************************************************************ */ 256 /* 257 * Register 24 Loopback, Bypass, Receiver Error Mask Reg 258 * The high byte of this register configures the DP83840 whilst its low byte 259 * programs the receive error types to be reported in real time as a HEX code 260 * across the MII RXD<3:0> interface. 261 */ 262 263 #define PHY_LBREMR_BPEB (1 << 15) /* Bypass Elasticity buffer */ 264 #define PHY_LBREMR_BP4B5B (1 << 14) /* Bypass 4B5B and 5B4B encoder */ 265 #define PHY_LBREMR_BPSCR (1 << 13) /* Bypass scrambler/descrambler */ 266 #define PHY_LBREMR_BPALIGN (1 << 12) /* Bypass symbol alignment ckt */ 267 #define PHY_LBREMR_EWRAP (1 << 11) /* 10Base-T ENDEC Loopback */ 268 #define PHY_LBREMR_XWRAP (1 << 10) /* 10Base-T Transceiver loopback */ 269 #define PHY_LBREMR_LB (0x3 << 8) /* Twister and remote loopback */ 270 #define PHY_LBREMR_RES1 (0x7 << 5) /* Reserved */ 271 #define PHY_LBREMR_CODE (1 << 4) /* Report det. of Code Error */ 272 #define PHY_LBREMR_PME (1 << 3) /* Report det. of Pre-mature End err */ 273 #define PHY_LBREMR_LINK (1 << 2) /* Report det. of Link Error */ 274 #define PHY_LBREMR_PKT (1 << 1) /* Report det. of Packet error */ 275 #define PHY_LBREMR_EB (1 << 0) /* Report det. of Elasticty buf err */ 276 277 /* ************************************************************************ */ 278 /* 279 * Register 25 PHY Address Register 280 */ 281 282 #define PHY_AR_RES1 (0x1ff << 7) /* reserved */ 283 #define PHY_AR_SPEED10 (1 << 6) /* speed : 1 = 10 Mbps, 0 - 100 Mbps */ 284 #define PHY_AR_CONSTS (1 << 5) /* status of the disconnect function */ 285 #define PHY_AR_ADDR (0x1f << 0) /* PHY Address */ 286 287 /* 288 * The PHYAD<4:0> allow 32 unique PHY addresses. The PHYAD<4:0> share the RX_ER, 289 * PHYAD3, CRS, ENCSEL ald LBEN pins of the PHY. By patching the PHYAD address 290 * pins with a light pull-up or pull-down resistor, the PMD address can be 291 * strobed and stored in these register location during Reset or Power-on reset 292 * time. 293 * 294 * The first PHY address bit transmitted or received is the MSB of the address. 295 * A PHY connected to a station management entity via an interface connector 296 * shall always respond to PHY address < 00000 > . A station management entity 297 * connected to multiple PHY entities must know the appropriate PHY address of 298 * each PHY entity. PHY address should be set to < 00001 > for a single 299 * PHY entity. A PHY address of < 00000 > will cause the Isolate bit 0: < 10 > 300 * to be set to one. 301 */ 302 303 /* ************************************************************************ */ 304 /* 305 * Register 26 Reserverd for future assignement by vendor 306 */ 307 308 /* ************************************************************************ */ 309 /* 310 * Register 27 10 Mbps TPI Status Register 311 */ 312 313 #define PHY_TPISR_RES1 (0x3f << 10) /* reserved */ 314 #define PHY_TPISR_10BTSER (1 << 9) /* 10BASE-T Serial mode */ 315 #define PHY_TPISR_RES2 (0x1ff << 0) /* reserved */ 316 317 /* ************************************************************************ */ 318 /* 319 * Register 28 10 Mbps Network I/F Configuration Register 320 */ 321 322 #define PHY_NICR_RES1 (0x3ff << 6) /* reserved */ 323 #define PHY_NICR_LD (1 << 5) /* Link disable */ 324 #define PHY_NICR_HBE (1 << 4) /* Enable Heart beat function */ 325 #define PHY_NICR_UTP (1 << 3) /* 1 = UTP, 0 = STP */ 326 #define PHY_NICR_LSS (1 << 2) /* Low Squelch select */ 327 #define PHY_NICR_RES2 (1 << 1) /* reserved */ 328 #define PHY_NICR_JBEN (1 << 0) /* Enables Jabber function in FDX */ 329 /* or xwrap mode */ 330 331 /* ************************************************************************ */ 332 333 /* Registers 29-31 are reserved for future assignment by Vendor */ 334 /* Do not write to these registers */ 335 336 /* 337 * QSI 6612 Physical layer device specific register bits. 338 * Addition Interface Technologies Group (NPG) 8/28/1997. 339 */ 340 #define PHY_BTXPC_DSCRAM 0x01 /* Disable data scrambling */ 341 342 /* ************************************************************************ */ 343 344 #endif /* HME_PHY_H */ 345