xref: /titanic_52/usr/src/uts/common/io/e1000g/e1000g_sw.h (revision b6c3f7863936abeae522e48a13887dddeb691a45)
1 /*
2  * This file is provided under a CDDLv1 license.  When using or
3  * redistributing this file, you may do so under this license.
4  * In redistributing this file this license must be included
5  * and no other modification of this header file is permitted.
6  *
7  * CDDL LICENSE SUMMARY
8  *
9  * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved.
10  *
11  * The contents of this file are subject to the terms of Version
12  * 1.0 of the Common Development and Distribution License (the "License").
13  *
14  * You should have received a copy of the License with this software.
15  * You can obtain a copy of the License at
16  *	http://www.opensolaris.org/os/licensing.
17  * See the License for the specific language governing permissions
18  * and limitations under the License.
19  */
20 
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms of the CDDLv1.
24  */
25 
26 #ifndef _E1000G_SW_H
27 #define	_E1000G_SW_H
28 
29 #pragma ident	"%Z%%M%	%I%	%E% SMI"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 /*
36  * **********************************************************************
37  * Module Name:								*
38  *   e1000g_sw.h							*
39  *									*
40  * Abstract:								*
41  *   This header file contains Software-related data structures		*
42  *   definitions.							*
43  *									*
44  * **********************************************************************
45  */
46 
47 #include <sys/types.h>
48 #include <sys/conf.h>
49 #include <sys/debug.h>
50 #include <sys/stropts.h>
51 #include <sys/stream.h>
52 #include <sys/strsun.h>
53 #include <sys/strlog.h>
54 #include <sys/kmem.h>
55 #include <sys/stat.h>
56 #include <sys/kstat.h>
57 #include <sys/modctl.h>
58 #include <sys/errno.h>
59 #include <sys/mac.h>
60 #include <sys/mac_ether.h>
61 #include <sys/vlan.h>
62 #include <sys/ddi.h>
63 #include <sys/sunddi.h>
64 #include <sys/disp.h>
65 #include <sys/pci.h>
66 #include <sys/sdt.h>
67 #include <sys/ethernet.h>
68 #include <sys/pattr.h>
69 #include <sys/strsubr.h>
70 #include <sys/netlb.h>
71 #include <inet/common.h>
72 #include <inet/ip.h>
73 #include <inet/mi.h>
74 #include <inet/nd.h>
75 #include <sys/ddifm.h>
76 #include <sys/fm/protocol.h>
77 #include <sys/fm/util.h>
78 #include <sys/fm/io/ddi.h>
79 #include "e1000_api.h"
80 
81 
82 #define	JUMBO_FRAG_LENGTH		4096
83 
84 #define	LAST_RAR_ENTRY			(E1000_RAR_ENTRIES - 1)
85 #define	MAX_NUM_UNICAST_ADDRESSES	E1000_RAR_ENTRIES
86 #define	MAX_NUM_MULTICAST_ADDRESSES	256
87 
88 #define	MAX_TX_DESC_PER_PACKET		16
89 
90 /*
91  * constants used in setting flow control thresholds
92  */
93 #define	E1000_PBA_MASK		0xffff
94 #define	E1000_PBA_SHIFT		10
95 #define	E1000_FC_HIGH_DIFF	0x1638 /* High: 5688 bytes below Rx FIFO size */
96 #define	E1000_FC_LOW_DIFF	0x1640 /* Low: 5696 bytes below Rx FIFO size */
97 #define	E1000_FC_PAUSE_TIME	0x0680 /* 858 usec */
98 
99 #define	MAX_NUM_TX_DESCRIPTOR		4096
100 #define	MAX_NUM_RX_DESCRIPTOR		4096
101 #define	MAX_NUM_RX_FREELIST		4096
102 #define	MAX_NUM_TX_FREELIST		4096
103 #define	MAX_RX_LIMIT_ON_INTR		4096
104 #define	MAX_RX_INTR_DELAY		65535
105 #define	MAX_RX_INTR_ABS_DELAY		65535
106 #define	MAX_TX_INTR_DELAY		65535
107 #define	MAX_TX_INTR_ABS_DELAY		65535
108 #define	MAX_INTR_THROTTLING		65535
109 #define	MAX_RX_BCOPY_THRESHOLD		E1000_RX_BUFFER_SIZE_2K
110 #define	MAX_TX_BCOPY_THRESHOLD		E1000_TX_BUFFER_SIZE_2K
111 #define	MAX_TX_RECYCLE_THRESHOLD	MAX_NUM_TX_DESCRIPTOR
112 #define	MAX_TX_RECYCLE_NUM		MAX_NUM_TX_DESCRIPTOR
113 
114 #define	MIN_NUM_TX_DESCRIPTOR		80
115 #define	MIN_NUM_RX_DESCRIPTOR		80
116 #define	MIN_NUM_RX_FREELIST		64
117 #define	MIN_NUM_TX_FREELIST		80
118 #define	MIN_RX_LIMIT_ON_INTR		16
119 #define	MIN_RX_INTR_DELAY		0
120 #define	MIN_RX_INTR_ABS_DELAY		0
121 #define	MIN_TX_INTR_DELAY		0
122 #define	MIN_TX_INTR_ABS_DELAY		0
123 #define	MIN_INTR_THROTTLING		0
124 #define	MIN_RX_BCOPY_THRESHOLD		0
125 #define	MIN_TX_BCOPY_THRESHOLD		MINIMUM_ETHERNET_PACKET_SIZE
126 #define	MIN_TX_RECYCLE_THRESHOLD	0
127 #define	MIN_TX_RECYCLE_NUM		MAX_TX_DESC_PER_PACKET
128 
129 #define	DEFAULT_NUM_RX_DESCRIPTOR	2048
130 #define	DEFAULT_NUM_TX_DESCRIPTOR	2048
131 #define	DEFAULT_NUM_RX_FREELIST		4096
132 #define	DEFAULT_NUM_TX_FREELIST		2304
133 #define	DEFAULT_RX_LIMIT_ON_INTR	128
134 
135 #ifdef __sparc
136 #define	MAX_INTR_PER_SEC		7100
137 #define	MIN_INTR_PER_SEC		3000
138 #define	DEFAULT_INTR_PACKET_LOW		5
139 #define	DEFAULT_INTR_PACKET_HIGH	128
140 #define	DEFAULT_TX_RECYCLE_THRESHOLD	512
141 #else
142 #define	MAX_INTR_PER_SEC		15000
143 #define	MIN_INTR_PER_SEC		4000
144 #define	DEFAULT_INTR_PACKET_LOW		10
145 #define	DEFAULT_INTR_PACKET_HIGH	48
146 #define	DEFAULT_TX_RECYCLE_THRESHOLD	DEFAULT_TX_NO_RESOURCE
147 #endif
148 
149 #define	DEFAULT_RX_INTR_DELAY		0
150 #define	DEFAULT_RX_INTR_ABS_DELAY	64
151 #define	DEFAULT_TX_INTR_DELAY		64
152 #define	DEFAULT_TX_INTR_ABS_DELAY	64
153 #define	DEFAULT_INTR_THROTTLING_HIGH    1000000000/(MIN_INTR_PER_SEC*256)
154 #define	DEFAULT_INTR_THROTTLING_LOW	1000000000/(MAX_INTR_PER_SEC*256)
155 #define	DEFAULT_INTR_THROTTLING		DEFAULT_INTR_THROTTLING_LOW
156 
157 #define	DEFAULT_RX_BCOPY_THRESHOLD	128
158 #define	DEFAULT_TX_BCOPY_THRESHOLD	512
159 #define	DEFAULT_TX_RECYCLE_NUM		64
160 #define	DEFAULT_TX_UPDATE_THRESHOLD	256
161 #define	DEFAULT_TX_NO_RESOURCE		6
162 
163 #define	DEFAULT_TX_INTR_ENABLE		1
164 #define	DEFAULT_FLOW_CONTROL		3
165 #define	DEFAULT_MASTER_LATENCY_TIMER	0	/* BIOS should decide */
166 						/* which is normally 0x040 */
167 #define	DEFAULT_TBI_COMPAT_ENABLE	1	/* Enable SBP workaround */
168 #define	DEFAULT_MSI_ENABLE		1	/* MSI Enable */
169 #define	DEFAULT_TX_HCKSUM_ENABLE	1	/* Hardware checksum enable */
170 
171 #define	TX_DRAIN_TIME		(200)	/* # milliseconds xmit drain */
172 
173 /*
174  * The size of the receive/transmite buffers
175  */
176 #define	E1000_RX_BUFFER_SIZE_2K		(2048)
177 #define	E1000_RX_BUFFER_SIZE_4K		(4096)
178 #define	E1000_RX_BUFFER_SIZE_8K		(8192)
179 #define	E1000_RX_BUFFER_SIZE_16K	(16384)
180 
181 #define	E1000_TX_BUFFER_SIZE_2K		(2048)
182 #define	E1000_TX_BUFFER_SIZE_4K		(4096)
183 #define	E1000_TX_BUFFER_SIZE_8K		(8192)
184 #define	E1000_TX_BUFFER_SIZE_16K	(16384)
185 
186 #define	FORCE_BCOPY_EXCEED_FRAGS	0x1
187 #define	FORCE_BCOPY_UNDER_SIZE		0x2
188 
189 #define	E1000G_RX_SW_FREE		0x0
190 #define	E1000G_RX_SW_SENDUP		0x1
191 #define	E1000G_RX_SW_STOP		0x2
192 #define	E1000G_RX_SW_DETACH		0x3
193 
194 /*
195  * definitions for smartspeed workaround
196  */
197 #define	  E1000_SMARTSPEED_MAX		30	/* 30 watchdog iterations */
198 						/* or 30 seconds */
199 #define	  E1000_SMARTSPEED_DOWNSHIFT	6	/* 6 watchdog iterations */
200 						/* or 6 seconds */
201 
202 /*
203  * Definitions for module_info.
204  */
205 #define	 WSNAME			"e1000g"	/* module name */
206 
207 /*
208  * Defined for IP header alignment. We also need to preserve space for
209  * VLAN tag (4 bytes)
210  */
211 #define	E1000G_IPALIGNROOM		6
212 #define	E1000G_IPALIGNPRESERVEROOM	64
213 
214 /*
215  * bit flags for 'attach_progress' which is a member variable in struct e1000g
216  */
217 #define	ATTACH_PROGRESS_PCI_CONFIG	0x0001	/* PCI config setup */
218 #define	ATTACH_PROGRESS_REGS_MAP	0x0002	/* Registers mapped */
219 #define	ATTACH_PROGRESS_SETUP		0x0004	/* Setup driver parameters */
220 #define	ATTACH_PROGRESS_ADD_INTR	0x0008	/* Interrupt added */
221 #define	ATTACH_PROGRESS_LOCKS		0x0010	/* Locks initialized */
222 #define	ATTACH_PROGRESS_SOFT_INTR	0x0020	/* Soft interrupt added */
223 #define	ATTACH_PROGRESS_KSTATS		0x0040	/* Kstats created */
224 #define	ATTACH_PROGRESS_ALLOC		0x0080	/* DMA resources allocated */
225 #define	ATTACH_PROGRESS_INIT		0x0100	/* Driver initialization */
226 #define	ATTACH_PROGRESS_NDD		0x0200	/* NDD initialized */
227 #define	ATTACH_PROGRESS_MAC		0x0400	/* MAC registered */
228 #define	ATTACH_PROGRESS_ENABLE_INTR	0x0800	/* DDI interrupts enabled */
229 #define	ATTACH_PROGRESS_FMINIT		0x1000	/* FMA initiated */
230 
231 /*
232  * Speed and Duplex Settings
233  */
234 #define	GDIAG_10_HALF		1
235 #define	GDIAG_10_FULL		2
236 #define	GDIAG_100_HALF		3
237 #define	GDIAG_100_FULL		4
238 #define	GDIAG_1000_FULL		6
239 #define	GDIAG_ANY		7
240 
241 /*
242  * Coexist Workaround RP: 07/04/03
243  * 82544 Workaround : Co-existence
244  */
245 #define	MAX_TX_BUF_SIZE		(8 * 1024)
246 
247 #define	ROUNDOFF		0x1000
248 
249 /*
250  * Defines for Jumbo Frame
251  */
252 #define	FRAME_SIZE_UPTO_2K	2048
253 #define	FRAME_SIZE_UPTO_4K	4096
254 #define	FRAME_SIZE_UPTO_8K	8192
255 #define	FRAME_SIZE_UPTO_16K	16384
256 #define	FRAME_SIZE_UPTO_9K	9234
257 
258 /* The sizes (in bytes) of a ethernet packet */
259 #define	MAXIMUM_ETHERNET_FRAME_SIZE	1518 /* With FCS */
260 #define	MINIMUM_ETHERNET_FRAME_SIZE	64   /* With FCS */
261 #define	ETHERNET_FCS_SIZE		4
262 #define	MAXIMUM_ETHERNET_PACKET_SIZE	\
263 	(MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
264 #define	MINIMUM_ETHERNET_PACKET_SIZE	\
265 	(MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
266 #define	CRC_LENGTH			ETHERNET_FCS_SIZE
267 
268 /* Defines for Tx stall check */
269 #define	E1000G_STALL_WATCHDOG_COUNT	8
270 
271 #define	MAX_TX_LINK_DOWN_TIMEOUT	8
272 
273 /* Defines for DVMA */
274 #ifdef __sparc
275 #define	E1000G_DEFAULT_DVMA_PAGE_NUM	2
276 #endif
277 
278 /*
279  * Loopback definitions
280  */
281 #define	E1000G_LB_NONE			0
282 #define	E1000G_LB_EXTERNAL_1000		1
283 #define	E1000G_LB_EXTERNAL_100		2
284 #define	E1000G_LB_EXTERNAL_10		3
285 #define	E1000G_LB_INTERNAL_PHY		4
286 
287 /*
288  * Private dip list definitions
289  */
290 #define	E1000G_PRIV_DEVI_ATTACH	0x0
291 #define	E1000G_PRIV_DEVI_DETACH	0x1
292 
293 /*
294  * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL.
295  */
296 #define	QUEUE_INIT_LIST(_LH)	\
297 	(_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0
298 
299 /*
300  * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty.
301  */
302 #define	IS_QUEUE_EMPTY(_LH)	\
303 	((_LH)->Flink == (PSINGLE_LIST_LINK)0)
304 
305 /*
306  * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does
307  * not remove the head from the queue.
308  */
309 #define	QUEUE_GET_HEAD(_LH)	((PSINGLE_LIST_LINK)((_LH)->Flink))
310 
311 /*
312  * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue.
313  */
314 #define	QUEUE_REMOVE_HEAD(_LH)	\
315 { \
316 	PSINGLE_LIST_LINK ListElem; \
317 	if (ListElem = (_LH)->Flink) \
318 	{ \
319 		if (!((_LH)->Flink = ListElem->Flink)) \
320 			(_LH)->Blink = (PSINGLE_LIST_LINK) 0; \
321 	} \
322 }
323 
324 /*
325  * QUEUE_POP_HEAD -- Macro which  will pop the head off of a queue (list),
326  *	and return it (this differs from QUEUE_REMOVE_HEAD only in
327  *	the 1st line).
328  */
329 #define	QUEUE_POP_HEAD(_LH)	\
330 	(PSINGLE_LIST_LINK)(_LH)->Flink; \
331 	{ \
332 		PSINGLE_LIST_LINK ListElem; \
333 		ListElem = (_LH)->Flink; \
334 		if (ListElem) \
335 		{ \
336 			(_LH)->Flink = ListElem->Flink; \
337 			if (!(_LH)->Flink) \
338 				(_LH)->Blink = (PSINGLE_LIST_LINK)0; \
339 		} \
340 	}
341 
342 /*
343  * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not
344  *	remove the tail from the queue.
345  */
346 #define	QUEUE_GET_TAIL(_LH)	((PSINGLE_LIST_LINK)((_LH)->Blink))
347 
348 /*
349  * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue
350  */
351 #define	QUEUE_PUSH_TAIL(_LH, _E)	\
352 	if ((_LH)->Blink) \
353 	{ \
354 		((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \
355 			(PSINGLE_LIST_LINK)(_E); \
356 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
357 	} else { \
358 		(_LH)->Flink = \
359 			(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
360 	} \
361 	(_E)->Flink = (PSINGLE_LIST_LINK)0;
362 
363 /*
364  * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue.
365  */
366 #define	QUEUE_PUSH_HEAD(_LH, _E)	\
367 	if (!((_E)->Flink = (_LH)->Flink)) \
368 	{ \
369 		(_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \
370 	} \
371 	(_LH)->Flink = (PSINGLE_LIST_LINK)(_E);
372 
373 /*
374  * QUEUE_GET_NEXT -- Macro which returns the next element linked to the
375  *	current element.
376  */
377 #define	QUEUE_GET_NEXT(_LH, _E)		\
378 	(PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \
379 	(0) : ((_E)->Flink))
380 
381 /*
382  * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue
383  */
384 #define	QUEUE_APPEND(_LH1, _LH2)	\
385 	if ((_LH2)->Flink) { \
386 		if ((_LH1)->Flink) { \
387 			((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \
388 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
389 		} else { \
390 			(_LH1)->Flink = \
391 				((PSINGLE_LIST_LINK)(_LH2)->Flink); \
392 		} \
393 		(_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \
394 	}
395 
396 /*
397  * Property lookups
398  */
399 #define	E1000G_PROP_EXISTS(d, n)	ddi_prop_exists(DDI_DEV_T_ANY, (d), \
400 						DDI_PROP_DONTPASS, (n))
401 #define	E1000G_PROP_GET_INT(d, n)	ddi_prop_get_int(DDI_DEV_T_ANY, (d), \
402 						DDI_PROP_DONTPASS, (n), -1)
403 
404 /*
405  * Shorthand for the NDD parameters
406  */
407 #define	param_adv_autoneg	nd_params[PARAM_ADV_AUTONEG_CAP].ndp_val
408 #define	param_adv_pause		nd_params[PARAM_ADV_PAUSE_CAP].ndp_val
409 #define	param_adv_asym_pause	nd_params[PARAM_ADV_ASYM_PAUSE_CAP].ndp_val
410 #define	param_adv_1000fdx	nd_params[PARAM_ADV_1000FDX_CAP].ndp_val
411 #define	param_adv_1000hdx	nd_params[PARAM_ADV_1000HDX_CAP].ndp_val
412 #define	param_adv_100fdx	nd_params[PARAM_ADV_100FDX_CAP].ndp_val
413 #define	param_adv_100hdx	nd_params[PARAM_ADV_100HDX_CAP].ndp_val
414 #define	param_adv_10fdx		nd_params[PARAM_ADV_10FDX_CAP].ndp_val
415 #define	param_adv_10hdx		nd_params[PARAM_ADV_10HDX_CAP].ndp_val
416 #define	param_force_speed_duplex nd_params[PARAM_FORCE_SPEED_DUPLEX].ndp_val
417 
418 #ifdef E1000G_DEBUG
419 /*
420  * E1000G-specific ioctls ...
421  */
422 #define	E1000G_IOC		((((((('E' << 4) + '1') << 4) \
423 				+ 'K') << 4) + 'G') << 4)
424 
425 /*
426  * These diagnostic IOCTLS are enabled only in DEBUG drivers
427  */
428 #define	E1000G_IOC_REG_PEEK	(E1000G_IOC | 1)
429 #define	E1000G_IOC_REG_POKE	(E1000G_IOC | 2)
430 #define	E1000G_IOC_CHIP_RESET	(E1000G_IOC | 3)
431 
432 #define	E1000G_PP_SPACE_REG	0	/* PCI memory space	*/
433 #define	E1000G_PP_SPACE_E1000G	1	/* driver's soft state	*/
434 
435 typedef struct {
436 	uint64_t pp_acc_size;	/* It's 1, 2, 4 or 8	*/
437 	uint64_t pp_acc_space;	/* See #defines below	*/
438 	uint64_t pp_acc_offset;	/* See regs definition	*/
439 	uint64_t pp_acc_data;	/* output for peek	*/
440 				/* input for poke	*/
441 } e1000g_peekpoke_t;
442 #endif	/* E1000G_DEBUG */
443 
444 /*
445  * (Internal) return values from ioctl subroutines
446  */
447 enum ioc_reply {
448 	IOC_INVAL = -1,		/* bad, NAK with EINVAL	*/
449 	IOC_DONE,		/* OK, reply sent	*/
450 	IOC_ACK,		/* OK, just send ACK	*/
451 	IOC_REPLY		/* OK, just send reply	*/
452 };
453 
454 /*
455  * Named Data (ND) Parameter Management Structure
456  */
457 typedef struct {
458 	uint32_t ndp_info;
459 	uint32_t ndp_min;
460 	uint32_t ndp_max;
461 	uint32_t ndp_val;
462 	struct e1000g *ndp_instance;
463 	char *ndp_name;
464 } nd_param_t;
465 
466 /*
467  * NDD parameter indexes, divided into:
468  *
469  *	read-only parameters describing the hardware's capabilities
470  *	read-write parameters controlling the advertised capabilities
471  *	read-only parameters describing the partner's capabilities
472  *	read-write parameters controlling the force speed and duplex
473  *	read-only parameters describing the link state
474  *	read-only parameters describing the driver properties
475  *	read-write parameters controlling the driver properties
476  */
477 enum {
478 	PARAM_AUTONEG_CAP,
479 	PARAM_PAUSE_CAP,
480 	PARAM_ASYM_PAUSE_CAP,
481 	PARAM_1000FDX_CAP,
482 	PARAM_1000HDX_CAP,
483 	PARAM_100T4_CAP,
484 	PARAM_100FDX_CAP,
485 	PARAM_100HDX_CAP,
486 	PARAM_10FDX_CAP,
487 	PARAM_10HDX_CAP,
488 
489 	PARAM_ADV_AUTONEG_CAP,
490 	PARAM_ADV_PAUSE_CAP,
491 	PARAM_ADV_ASYM_PAUSE_CAP,
492 	PARAM_ADV_1000FDX_CAP,
493 	PARAM_ADV_1000HDX_CAP,
494 	PARAM_ADV_100T4_CAP,
495 	PARAM_ADV_100FDX_CAP,
496 	PARAM_ADV_100HDX_CAP,
497 	PARAM_ADV_10FDX_CAP,
498 	PARAM_ADV_10HDX_CAP,
499 
500 	PARAM_LP_AUTONEG_CAP,
501 	PARAM_LP_PAUSE_CAP,
502 	PARAM_LP_ASYM_PAUSE_CAP,
503 	PARAM_LP_1000FDX_CAP,
504 	PARAM_LP_1000HDX_CAP,
505 	PARAM_LP_100T4_CAP,
506 	PARAM_LP_100FDX_CAP,
507 	PARAM_LP_100HDX_CAP,
508 	PARAM_LP_10FDX_CAP,
509 	PARAM_LP_10HDX_CAP,
510 
511 	PARAM_FORCE_SPEED_DUPLEX,
512 
513 	PARAM_LINK_STATUS,
514 	PARAM_LINK_SPEED,
515 	PARAM_LINK_DUPLEX,
516 	PARAM_LINK_AUTONEG,
517 
518 	PARAM_MAX_FRAME_SIZE,
519 	PARAM_LOOP_MODE,
520 	PARAM_INTR_TYPE,
521 
522 	PARAM_TX_BCOPY_THRESHOLD,
523 	PARAM_TX_INTR_ENABLE,
524 	PARAM_TX_TIDV,
525 	PARAM_TX_TADV,
526 	PARAM_RX_BCOPY_THRESHOLD,
527 	PARAM_RX_PKT_ON_INTR,
528 	PARAM_RX_RDTR,
529 	PARAM_RX_RADV,
530 
531 	PARAM_COUNT
532 };
533 
534 /*
535  * The entry of the private dip list
536  */
537 typedef struct _private_devi_list {
538 	dev_info_t *priv_dip;
539 	uint16_t flag;
540 	struct _private_devi_list *next;
541 } private_devi_list_t;
542 
543 /*
544  * A structure that points to the next entry in the queue.
545  */
546 typedef struct _SINGLE_LIST_LINK {
547 	struct _SINGLE_LIST_LINK *Flink;
548 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK;
549 
550 /*
551  * A "ListHead" structure that points to the head and tail of a queue
552  */
553 typedef struct _LIST_DESCRIBER {
554 	struct _SINGLE_LIST_LINK *volatile Flink;
555 	struct _SINGLE_LIST_LINK *volatile Blink;
556 } LIST_DESCRIBER, *PLIST_DESCRIBER;
557 
558 /*
559  * Address-Length pair structure that stores descriptor info
560  */
561 typedef struct _sw_desc {
562 	uint64_t address;
563 	uint32_t length;
564 } sw_desc_t, *p_sw_desc_t;
565 
566 typedef struct _desc_array {
567 	sw_desc_t descriptor[4];
568 	uint32_t elements;
569 } desc_array_t, *p_desc_array_t;
570 
571 typedef enum {
572 	USE_NONE,
573 	USE_BCOPY,
574 	USE_DVMA,
575 	USE_DMA
576 } dma_type_t;
577 
578 typedef enum {
579 	E1000G_STOP,
580 	E1000G_START,
581 	E1000G_ERROR
582 } chip_state_t;
583 
584 typedef struct _dma_buffer {
585 	caddr_t address;
586 	uint64_t dma_address;
587 	ddi_acc_handle_t acc_handle;
588 	ddi_dma_handle_t dma_handle;
589 	size_t size;
590 	size_t len;
591 } dma_buffer_t, *p_dma_buffer_t;
592 
593 /*
594  * Transmit Control Block (TCB), Ndis equiv of SWPacket This
595  * structure stores the additional information that is
596  * associated with every packet to be transmitted. It stores the
597  * message block pointer and the TBD addresses associated with
598  * the m_blk and also the link to the next tcb in the chain
599  */
600 typedef struct _tx_sw_packet {
601 	/* Link to the next tx_sw_packet in the list */
602 	SINGLE_LIST_LINK Link;
603 	mblk_t *mp;
604 	uint32_t num_desc;
605 	uint32_t num_mblk_frag;
606 	dma_type_t dma_type;
607 	dma_type_t data_transfer_type;
608 	ddi_dma_handle_t tx_dma_handle;
609 	dma_buffer_t tx_buf[1];
610 	sw_desc_t desc[MAX_TX_DESC_PER_PACKET];
611 } tx_sw_packet_t, *p_tx_sw_packet_t;
612 
613 /*
614  * This structure is similar to the rx_sw_packet structure used
615  * for Ndis. This structure stores information about the 2k
616  * aligned receive buffer into which the FX1000 DMA's frames.
617  * This structure is maintained as a linked list of many
618  * receiver buffer pointers.
619  */
620 typedef struct _rx_sw_packet {
621 	/* Link to the next rx_sw_packet_t in the list */
622 	SINGLE_LIST_LINK Link;
623 	struct _rx_sw_packet *next;
624 	uint16_t flag;
625 	mblk_t *mp;
626 	caddr_t rx_ring;
627 	dma_type_t dma_type;
628 	frtn_t free_rtn;
629 	dma_buffer_t rx_buf[1];
630 } rx_sw_packet_t, *p_rx_sw_packet_t;
631 
632 typedef struct _mblk_list {
633 	mblk_t *head;
634 	mblk_t *tail;
635 } mblk_list_t, *p_mblk_list_t;
636 
637 typedef struct _cksum_data {
638 	uint32_t ether_header_size;
639 	uint32_t cksum_flags;
640 	uint32_t cksum_start;
641 	uint32_t cksum_stuff;
642 } cksum_data_t;
643 
644 typedef union _e1000g_ether_addr {
645 	struct {
646 		uint32_t high;
647 		uint32_t low;
648 	} reg;
649 	struct {
650 		uint8_t set;
651 		uint8_t redundant;
652 		uint8_t addr[ETHERADDRL];
653 	} mac;
654 } e1000g_ether_addr_t;
655 
656 typedef struct _e1000g_stat {
657 
658 	kstat_named_t link_speed;	/* Link Speed */
659 	kstat_named_t reset_count;	/* Reset Count */
660 
661 	kstat_named_t rx_error;		/* Rx Error in Packet */
662 	kstat_named_t rx_esballoc_fail;	/* Rx Desballoc Failure */
663 	kstat_named_t rx_allocb_fail;	/* Rx Allocb Failure */
664 
665 	kstat_named_t tx_no_desc;	/* Tx No Desc */
666 	kstat_named_t tx_no_swpkt;	/* Tx No Pkt Buffer */
667 	kstat_named_t tx_send_fail;	/* Tx SendPkt Failure */
668 	kstat_named_t tx_over_size;	/* Tx Pkt Too Long */
669 	kstat_named_t tx_reschedule;	/* Tx Reschedule */
670 
671 #ifdef E1000G_DEBUG
672 	kstat_named_t rx_none;		/* Rx No Incoming Data */
673 	kstat_named_t rx_multi_desc;	/* Rx Multi Spanned Pkt */
674 	kstat_named_t rx_no_freepkt;	/* Rx No Free Pkt */
675 	kstat_named_t rx_avail_freepkt;	/* Rx Freelist Avail Buffers */
676 
677 	kstat_named_t tx_under_size;	/* Tx Packet Under Size */
678 	kstat_named_t tx_empty_frags;	/* Tx Empty Frags */
679 	kstat_named_t tx_exceed_frags;	/* Tx Exceed Max Frags */
680 	kstat_named_t tx_recycle;	/* Tx Recycle */
681 	kstat_named_t tx_recycle_intr;	/* Tx Recycle in Intr */
682 	kstat_named_t tx_recycle_retry;	/* Tx Recycle Retry */
683 	kstat_named_t tx_recycle_none;	/* Tx No Desc Recycled */
684 	kstat_named_t tx_copy;		/* Tx Send Copy */
685 	kstat_named_t tx_bind;		/* Tx Send Bind */
686 	kstat_named_t tx_multi_copy;	/* Tx Copy Multi Fragments */
687 	kstat_named_t tx_multi_cookie;	/* Tx Pkt Span Multi Cookies */
688 	kstat_named_t tx_lack_desc;	/* Tx Lack of Desc */
689 #endif
690 
691 	kstat_named_t Crcerrs;	/* CRC Error Count */
692 	kstat_named_t Symerrs;	/* Symbol Error Count */
693 	kstat_named_t Mpc;	/* Missed Packet Count */
694 	kstat_named_t Scc;	/* Single Collision Count */
695 	kstat_named_t Ecol;	/* Excessive Collision Count */
696 	kstat_named_t Mcc;	/* Multiple Collision Count */
697 	kstat_named_t Latecol;	/* Late Collision Count */
698 	kstat_named_t Colc;	/* Collision Count */
699 	kstat_named_t Dc;	/* Defer Count */
700 	kstat_named_t Sec;	/* Sequence Error Count */
701 	kstat_named_t Rlec;	/* Receive Length Error Count */
702 	kstat_named_t Xonrxc;	/* XON Received Count */
703 	kstat_named_t Xontxc;	/* XON Xmitted Count */
704 	kstat_named_t Xoffrxc;	/* XOFF Received Count */
705 	kstat_named_t Xofftxc;	/* Xoff Xmitted Count */
706 	kstat_named_t Fcruc;	/* Unknown Flow Conrol Packet Rcvd Count */
707 #ifdef E1000G_DEBUG
708 	kstat_named_t Prc64;	/* Packets Received - 64b */
709 	kstat_named_t Prc127;	/* Packets Received - 65-127b */
710 	kstat_named_t Prc255;	/* Packets Received - 127-255b */
711 	kstat_named_t Prc511;	/* Packets Received - 256-511b */
712 	kstat_named_t Prc1023;	/* Packets Received - 511-1023b */
713 	kstat_named_t Prc1522;	/* Packets Received - 1024-1522b */
714 #endif
715 	kstat_named_t Gprc;	/* Good Packets Received Count */
716 	kstat_named_t Bprc;	/* Broadcasts Pkts Received Count */
717 	kstat_named_t Mprc;	/* Multicast Pkts Received Count */
718 	kstat_named_t Gptc;	/* Good Packets Xmitted Count */
719 	kstat_named_t Gorl;	/* Good Octets Recvd Lo Count */
720 	kstat_named_t Gorh;	/* Good Octets Recvd Hi Count */
721 	kstat_named_t Gotl;	/* Good Octets Xmitd Lo Count */
722 	kstat_named_t Goth;	/* Good Octets Xmitd Hi Count */
723 	kstat_named_t Rnbc;	/* Receive No Buffers Count */
724 	kstat_named_t Ruc;	/* Receive Undersize Count */
725 	kstat_named_t Rfc;	/* Receive Frag Count */
726 	kstat_named_t Roc;	/* Receive Oversize Count */
727 	kstat_named_t Rjc;	/* Receive Jabber Count */
728 	kstat_named_t Torl;	/* Total Octets Recvd Lo Count */
729 	kstat_named_t Torh;	/* Total Octets Recvd Hi Count */
730 	kstat_named_t Totl;	/* Total Octets Xmted Lo Count */
731 	kstat_named_t Toth;	/* Total Octets Xmted Hi Count */
732 	kstat_named_t Tpr;	/* Total Packets Received */
733 	kstat_named_t Tpt;	/* Total Packets Xmitted */
734 #ifdef E1000G_DEBUG
735 	kstat_named_t Ptc64;	/* Packets Xmitted (64b) */
736 	kstat_named_t Ptc127;	/* Packets Xmitted (64-127b) */
737 	kstat_named_t Ptc255;	/* Packets Xmitted (128-255b) */
738 	kstat_named_t Ptc511;	/* Packets Xmitted (255-511b) */
739 	kstat_named_t Ptc1023;	/* Packets Xmitted (512-1023b) */
740 	kstat_named_t Ptc1522;	/* Packets Xmitted (1024-1522b */
741 #endif
742 	kstat_named_t Mptc;	/* Multicast Packets Xmited Count */
743 	kstat_named_t Bptc;	/* Broadcast Packets Xmited Count */
744 	kstat_named_t Algnerrc;	/* Alignment Error count */
745 	kstat_named_t Tuc;	/* Transmit Underrun count */
746 	kstat_named_t Rxerrc;	/* Rx Error Count */
747 	kstat_named_t Tncrs;	/* Transmit with no CRS */
748 	kstat_named_t Cexterr;	/* Carrier Extension Error count */
749 	kstat_named_t Rutec;	/* Receive DMA too Early count */
750 	kstat_named_t Tsctc;	/* TCP seg contexts xmit count */
751 	kstat_named_t Tsctfc;	/* TCP seg contexts xmit fail count */
752 } e1000g_stat_t, *p_e1000g_stat_t;
753 
754 typedef struct _e1000g_tx_ring {
755 	kmutex_t tx_lock;
756 	kmutex_t freelist_lock;
757 	kmutex_t usedlist_lock;
758 	/*
759 	 * Descriptor queue definitions
760 	 */
761 	ddi_dma_handle_t tbd_dma_handle;
762 	ddi_acc_handle_t tbd_acc_handle;
763 	struct e1000_tx_desc *tbd_area;
764 	uint64_t tbd_dma_addr;
765 	struct e1000_tx_desc *tbd_first;
766 	struct e1000_tx_desc *tbd_last;
767 	struct e1000_tx_desc *tbd_oldest;
768 	struct e1000_tx_desc *tbd_next;
769 	uint32_t tbd_avail;
770 	/*
771 	 * Software packet structures definitions
772 	 */
773 	p_tx_sw_packet_t packet_area;
774 	LIST_DESCRIBER used_list;
775 	LIST_DESCRIBER free_list;
776 	/*
777 	 * TCP/UDP checksum offload
778 	 */
779 	cksum_data_t cksum_data;
780 	/*
781 	 * Timer definitions for 82547
782 	 */
783 	timeout_id_t timer_id_82547;
784 	boolean_t timer_enable_82547;
785 	/*
786 	 * reschedule when tx resource is available
787 	 */
788 	boolean_t resched_needed;
789 	uint32_t frags_limit;
790 	uint32_t stall_watchdog;
791 	uint32_t recycle_fail;
792 	mblk_list_t mblks;
793 	/*
794 	 * Statistics
795 	 */
796 	uint32_t stat_no_swpkt;
797 	uint32_t stat_no_desc;
798 	uint32_t stat_send_fail;
799 	uint32_t stat_reschedule;
800 	uint32_t stat_over_size;
801 #ifdef E1000G_DEBUG
802 	uint32_t stat_under_size;
803 	uint32_t stat_exceed_frags;
804 	uint32_t stat_empty_frags;
805 	uint32_t stat_recycle;
806 	uint32_t stat_recycle_intr;
807 	uint32_t stat_recycle_retry;
808 	uint32_t stat_recycle_none;
809 	uint32_t stat_copy;
810 	uint32_t stat_bind;
811 	uint32_t stat_multi_copy;
812 	uint32_t stat_multi_cookie;
813 	uint32_t stat_lack_desc;
814 #endif
815 	/*
816 	 * Pointer to the adapter
817 	 */
818 	struct e1000g *adapter;
819 } e1000g_tx_ring_t, *pe1000g_tx_ring_t;
820 
821 typedef struct _e1000g_rx_ring {
822 	kmutex_t rx_lock;
823 	kmutex_t freelist_lock;
824 	/*
825 	 * Descriptor queue definitions
826 	 */
827 	ddi_dma_handle_t rbd_dma_handle;
828 	ddi_acc_handle_t rbd_acc_handle;
829 	struct e1000_rx_desc *rbd_area;
830 	uint64_t rbd_dma_addr;
831 	struct e1000_rx_desc *rbd_first;
832 	struct e1000_rx_desc *rbd_last;
833 	struct e1000_rx_desc *rbd_next;
834 	/*
835 	 * Software packet structures definitions
836 	 */
837 	p_rx_sw_packet_t packet_area;
838 	LIST_DESCRIBER recv_list;
839 	LIST_DESCRIBER free_list;
840 
841 	p_rx_sw_packet_t pending_list;
842 	uint32_t pending_count;
843 	uint32_t avail_freepkt;
844 	uint32_t rx_mblk_len;
845 	mblk_t *rx_mblk;
846 	mblk_t *rx_mblk_tail;
847 	/*
848 	 * Statistics
849 	 */
850 	uint32_t stat_error;
851 	uint32_t stat_esballoc_fail;
852 	uint32_t stat_allocb_fail;
853 	uint32_t stat_exceed_pkt;
854 #ifdef E1000G_DEBUG
855 	uint32_t stat_none;
856 	uint32_t stat_multi_desc;
857 	uint32_t stat_no_freepkt;
858 #endif
859 	/*
860 	 * Pointer to the adapter
861 	 */
862 	struct e1000g *adapter;
863 } e1000g_rx_ring_t, *pe1000g_rx_ring_t;
864 
865 typedef struct e1000g {
866 	int instance;
867 	dev_info_t *dip;
868 	dev_info_t *priv_dip;
869 	mac_handle_t mh;
870 	mac_resource_handle_t mrh;
871 	struct e1000_hw shared;
872 	struct e1000g_osdep osdep;
873 
874 	chip_state_t chip_state;
875 	boolean_t e1000g_promisc;
876 	boolean_t strip_crc;
877 	boolean_t rx_buffer_setup;
878 	link_state_t link_state;
879 	uint32_t link_speed;
880 	uint32_t link_duplex;
881 	uint32_t master_latency_timer;
882 	uint32_t smartspeed;	/* smartspeed w/a counter */
883 	uint32_t init_count;
884 	uint32_t reset_count;
885 	uint32_t attach_progress;	/* attach tracking */
886 	uint32_t loopback_mode;
887 
888 	uint32_t tx_desc_num;
889 	uint32_t tx_freelist_num;
890 	uint32_t rx_desc_num;
891 	uint32_t rx_freelist_num;
892 	uint32_t tx_buffer_size;
893 	uint32_t rx_buffer_size;
894 
895 	uint32_t tx_link_down_timeout;
896 	uint32_t tx_bcopy_thresh;
897 	uint32_t rx_limit_onintr;
898 	uint32_t rx_bcopy_thresh;
899 #ifndef NO_82542_SUPPORT
900 	uint32_t rx_buf_align;
901 #endif
902 
903 	boolean_t intr_adaptive;
904 	boolean_t tx_intr_enable;
905 	uint32_t tx_recycle_thresh;
906 	uint32_t tx_recycle_num;
907 	uint32_t tx_intr_delay;
908 	uint32_t tx_intr_abs_delay;
909 	uint32_t rx_intr_delay;
910 	uint32_t rx_intr_abs_delay;
911 	uint32_t intr_throttling_rate;
912 
913 	boolean_t watchdog_timer_enabled;
914 	boolean_t watchdog_timer_started;
915 	timeout_id_t watchdog_tid;
916 	boolean_t link_complete;
917 	timeout_id_t link_tid;
918 
919 	e1000g_rx_ring_t rx_ring[1];
920 	e1000g_tx_ring_t tx_ring[1];
921 
922 	/*
923 	 * Rx and Tx packet count for interrupt adaptive setting
924 	 */
925 	uint32_t rx_pkt_cnt;
926 	uint32_t tx_pkt_cnt;
927 
928 	/*
929 	 * The watchdog_lock must be held when updateing the
930 	 * timeout fields in struct e1000g, that is,
931 	 * watchdog_tid, watchdog_timer_started.
932 	 */
933 	kmutex_t watchdog_lock;
934 	/*
935 	 * The link_lock protects the link fields in struct e1000g,
936 	 * such as link_state, link_speed, link_duplex, link_complete, and
937 	 * link_tid.
938 	 */
939 	kmutex_t link_lock;
940 	/*
941 	 * The chip_lock assures that the Rx/Tx process must be
942 	 * stopped while other functions change the hardware
943 	 * configuration of e1000g card, such as e1000g_reset(),
944 	 * e1000g_reset_hw() etc are executed.
945 	 */
946 	krwlock_t chip_lock;
947 
948 	boolean_t unicst_init;
949 	uint32_t unicst_avail;
950 	uint32_t unicst_total;
951 	e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES];
952 
953 	uint32_t mcast_count;
954 	struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES];
955 
956 #ifdef __sparc
957 	ulong_t sys_page_sz;
958 	uint_t dvma_page_num;
959 #endif
960 
961 	boolean_t msi_enabled;
962 	boolean_t tx_hcksum_enabled;
963 	int intr_type;
964 	int intr_cnt;
965 	int intr_cap;
966 	size_t intr_size;
967 	uint_t intr_pri;
968 	ddi_intr_handle_t *htable;
969 
970 	int tx_softint_pri;
971 	ddi_softint_handle_t tx_softint_handle;
972 
973 	kstat_t *e1000g_ksp;
974 
975 	/*
976 	 * NDD parameters
977 	 */
978 	caddr_t nd_data;
979 	nd_param_t nd_params[PARAM_COUNT];
980 
981 	uint16_t phy_ctrl;		/* contents of PHY_CTRL */
982 	uint16_t phy_status;		/* contents of PHY_STATUS */
983 	uint16_t phy_an_adv;		/* contents of PHY_AUTONEG_ADV */
984 	uint16_t phy_an_exp;		/* contents of PHY_AUTONEG_EXP */
985 	uint16_t phy_ext_status;	/* contents of PHY_EXT_STATUS */
986 	uint16_t phy_1000t_ctrl;	/* contents of PHY_1000T_CTRL */
987 	uint16_t phy_1000t_status;	/* contents of PHY_1000T_STATUS */
988 	uint16_t phy_lp_able;		/* contents of PHY_LP_ABILITY */
989 
990 	/*
991 	 * FMA capabilities
992 	 */
993 	int fm_capabilities;
994 } e1000g_t;
995 
996 
997 /*
998  * Function prototypes
999  */
1000 int e1000g_alloc_dma_resources(struct e1000g *Adapter);
1001 void e1000g_release_dma_resources(struct e1000g *Adapter);
1002 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet);
1003 void e1000g_tx_setup(struct e1000g *Adapter);
1004 void e1000g_rx_setup(struct e1000g *Adapter);
1005 void e1000g_setup_multicast(struct e1000g *Adapter);
1006 boolean_t e1000g_reset(struct e1000g *Adapter);
1007 
1008 int e1000g_recycle(e1000g_tx_ring_t *tx_ring);
1009 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet);
1010 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring);
1011 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2);
1012 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp);
1013 mblk_t *e1000g_receive(struct e1000g *Adapter);
1014 void e1000g_rxfree_func(p_rx_sw_packet_t packet);
1015 
1016 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val);
1017 int e1000g_init_stats(struct e1000g *Adapter);
1018 void e1000_tbi_adjust_stats(struct e1000g *Adapter,
1019     uint32_t frame_len, uint8_t *mac_addr);
1020 enum ioc_reply e1000g_nd_ioctl(struct e1000g *Adapter,
1021     queue_t *wq, mblk_t *mp, struct iocblk *iocp);
1022 void e1000g_nd_cleanup(struct e1000g *Adapter);
1023 int e1000g_nd_init(struct e1000g *Adapter);
1024 
1025 void e1000g_clear_interrupt(struct e1000g *Adapter);
1026 void e1000g_mask_interrupt(struct e1000g *Adapter);
1027 void e1000g_clear_all_interrupts(struct e1000g *Adapter);
1028 void e1000g_clear_tx_interrupt(struct e1000g *Adapter);
1029 void e1000g_mask_tx_interrupt(struct e1000g *Adapter);
1030 void phy_spd_state(struct e1000_hw *hw, boolean_t enable);
1031 void e1000_enable_pciex_master(struct e1000_hw *hw);
1032 void e1000g_get_driver_control(struct e1000_hw *hw);
1033 int e1000g_check_acc_handle(ddi_acc_handle_t handle);
1034 int e1000g_check_dma_handle(ddi_dma_handle_t handle);
1035 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail);
1036 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag);
1037 
1038 #pragma inline(e1000_rar_set)
1039 
1040 /*
1041  * Global variables
1042  */
1043 extern boolean_t e1000g_force_detach;
1044 extern uint32_t e1000g_mblks_pending;
1045 extern krwlock_t e1000g_rx_detach_lock;
1046 extern private_devi_list_t *e1000g_private_devi_list;
1047 
1048 #ifdef __cplusplus
1049 }
1050 #endif
1051 
1052 #endif	/* _E1000G_SW_H */
1053