1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac_provider.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 /* Driver states */ 81 #define E1000G_UNKNOWN 0x00 82 #define E1000G_INITIALIZED 0x01 83 #define E1000G_STARTED 0x02 84 #define E1000G_SUSPENDED 0x04 85 #define E1000G_ERROR 0x80 86 87 #define JUMBO_FRAG_LENGTH 4096 88 89 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 90 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 91 #define MAX_NUM_MULTICAST_ADDRESSES 256 92 93 /* 94 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 95 * + one for cross page split 96 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 97 * two for the workaround of the 82546 chip 98 */ 99 #define MAX_COOKIES 18 100 #define MAX_TX_DESC_PER_PACKET 21 101 102 /* 103 * constants used in setting flow control thresholds 104 */ 105 #define E1000_PBA_10K 0x000A 106 #define E1000_PBA_MASK 0xffff 107 #define E1000_PBA_SHIFT 10 108 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 109 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 110 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 111 112 #define MAX_NUM_TX_DESCRIPTOR 4096 113 #define MAX_NUM_RX_DESCRIPTOR 4096 114 #define MAX_NUM_RX_FREELIST 4096 115 #define MAX_NUM_TX_FREELIST 4096 116 #define MAX_RX_LIMIT_ON_INTR 4096 117 #define MAX_RX_INTR_DELAY 65535 118 #define MAX_RX_INTR_ABS_DELAY 65535 119 #define MAX_TX_INTR_DELAY 65535 120 #define MAX_TX_INTR_ABS_DELAY 65535 121 #define MAX_INTR_THROTTLING 65535 122 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 123 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 124 125 #define MIN_NUM_TX_DESCRIPTOR 80 126 #define MIN_NUM_RX_DESCRIPTOR 80 127 #define MIN_NUM_RX_FREELIST 64 128 #define MIN_NUM_TX_FREELIST 80 129 #define MIN_RX_LIMIT_ON_INTR 16 130 #define MIN_RX_INTR_DELAY 0 131 #define MIN_RX_INTR_ABS_DELAY 0 132 #define MIN_TX_INTR_DELAY 0 133 #define MIN_TX_INTR_ABS_DELAY 0 134 #define MIN_INTR_THROTTLING 0 135 #define MIN_RX_BCOPY_THRESHOLD 0 136 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 137 138 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 139 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 140 #define DEFAULT_NUM_RX_FREELIST 4096 141 #define DEFAULT_NUM_TX_FREELIST 2304 142 #define DEFAULT_RX_LIMIT_ON_INTR 128 143 144 #ifdef __sparc 145 #define MAX_INTR_PER_SEC 7100 146 #define MIN_INTR_PER_SEC 3000 147 #define DEFAULT_INTR_PACKET_LOW 5 148 #define DEFAULT_INTR_PACKET_HIGH 128 149 #else 150 #define MAX_INTR_PER_SEC 15000 151 #define MIN_INTR_PER_SEC 4000 152 #define DEFAULT_INTR_PACKET_LOW 10 153 #define DEFAULT_INTR_PACKET_HIGH 48 154 #endif 155 156 #define DEFAULT_RX_INTR_DELAY 0 157 #define DEFAULT_RX_INTR_ABS_DELAY 64 158 #define DEFAULT_TX_INTR_DELAY 64 159 #define DEFAULT_TX_INTR_ABS_DELAY 64 160 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 161 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 162 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 163 164 #define DEFAULT_RX_BCOPY_THRESHOLD 128 165 #define DEFAULT_TX_BCOPY_THRESHOLD 512 166 #define DEFAULT_TX_UPDATE_THRESHOLD 256 167 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 168 169 #define DEFAULT_TX_INTR_ENABLE 1 170 #define DEFAULT_FLOW_CONTROL 3 171 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 172 /* which is normally 0x040 */ 173 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 174 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 175 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 176 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 177 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 178 179 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 180 181 /* 182 * The size of the receive/transmite buffers 183 */ 184 #define E1000_RX_BUFFER_SIZE_2K (2048) 185 #define E1000_RX_BUFFER_SIZE_4K (4096) 186 #define E1000_RX_BUFFER_SIZE_8K (8192) 187 #define E1000_RX_BUFFER_SIZE_16K (16384) 188 189 #define E1000_TX_BUFFER_SIZE_2K (2048) 190 #define E1000_TX_BUFFER_SIZE_4K (4096) 191 #define E1000_TX_BUFFER_SIZE_8K (8192) 192 #define E1000_TX_BUFFER_SIZE_16K (16384) 193 194 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 195 196 #define E1000G_RX_SW_FREE 0x0 197 #define E1000G_RX_SW_SENDUP 0x1 198 #define E1000G_RX_SW_STOP 0x2 199 #define E1000G_RX_SW_DETACH 0x3 200 201 #define E1000G_CHAIN_NO_LIMIT 0 202 203 /* 204 * definitions for smartspeed workaround 205 */ 206 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 207 /* or 30 seconds */ 208 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 209 /* or 6 seconds */ 210 211 /* 212 * Definitions for module_info. 213 */ 214 #define WSNAME "e1000g" /* module name */ 215 216 /* 217 * Defined for IP header alignment. We also need to preserve space for 218 * VLAN tag (4 bytes) 219 */ 220 #define E1000G_IPALIGNROOM 6 221 #define E1000G_IPALIGNPRESERVEROOM 64 222 223 /* 224 * bit flags for 'attach_progress' which is a member variable in struct e1000g 225 */ 226 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 227 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 228 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 229 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 230 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 231 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 232 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 233 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 234 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 235 /* 0200 used to be PROGRESS_NDD. Now unused */ 236 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 237 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 238 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 239 240 /* 241 * Speed and Duplex Settings 242 */ 243 #define GDIAG_10_HALF 1 244 #define GDIAG_10_FULL 2 245 #define GDIAG_100_HALF 3 246 #define GDIAG_100_FULL 4 247 #define GDIAG_1000_FULL 6 248 #define GDIAG_ANY 7 249 250 /* 251 * Coexist Workaround RP: 07/04/03 252 * 82544 Workaround : Co-existence 253 */ 254 #define MAX_TX_BUF_SIZE (8 * 1024) 255 256 /* 257 * Defines for Jumbo Frame 258 */ 259 #define FRAME_SIZE_UPTO_2K 2048 260 #define FRAME_SIZE_UPTO_4K 4096 261 #define FRAME_SIZE_UPTO_8K 8192 262 #define FRAME_SIZE_UPTO_16K 16384 263 #define FRAME_SIZE_UPTO_9K 9234 264 265 #define MAXIMUM_MTU 9000 266 #define DEFAULT_MTU ETHERMTU 267 268 #define DEFAULT_FRAME_SIZE \ 269 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 270 #define MAXIMUM_FRAME_SIZE \ 271 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 272 273 #define E1000_LSO_MAXLEN 65535 274 275 /* Defines for Tx stall check */ 276 #define E1000G_STALL_WATCHDOG_COUNT 8 277 278 #define MAX_TX_LINK_DOWN_TIMEOUT 8 279 280 /* Defines for DVMA */ 281 #ifdef __sparc 282 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 283 #endif 284 285 /* 286 * Loopback definitions 287 */ 288 #define E1000G_LB_NONE 0 289 #define E1000G_LB_EXTERNAL_1000 1 290 #define E1000G_LB_EXTERNAL_100 2 291 #define E1000G_LB_EXTERNAL_10 3 292 #define E1000G_LB_INTERNAL_PHY 4 293 294 /* 295 * Private dip list definitions 296 */ 297 #define E1000G_PRIV_DEVI_ATTACH 0x0 298 #define E1000G_PRIV_DEVI_DETACH 0x1 299 300 /* 301 * Tx descriptor LENGTH field mask 302 */ 303 #define E1000G_TBD_LENGTH_MASK 0x000fffff 304 305 /* 306 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 307 */ 308 #define QUEUE_INIT_LIST(_LH) \ 309 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 310 311 /* 312 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 313 */ 314 #define IS_QUEUE_EMPTY(_LH) \ 315 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 316 317 /* 318 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 319 * not remove the head from the queue. 320 */ 321 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 322 323 /* 324 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 325 */ 326 #define QUEUE_REMOVE_HEAD(_LH) \ 327 { \ 328 PSINGLE_LIST_LINK ListElem; \ 329 if (ListElem = (_LH)->Flink) \ 330 { \ 331 if (!((_LH)->Flink = ListElem->Flink)) \ 332 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 333 } \ 334 } 335 336 /* 337 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 338 * and return it (this differs from QUEUE_REMOVE_HEAD only in 339 * the 1st line). 340 */ 341 #define QUEUE_POP_HEAD(_LH) \ 342 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 343 { \ 344 PSINGLE_LIST_LINK ListElem; \ 345 ListElem = (_LH)->Flink; \ 346 if (ListElem) \ 347 { \ 348 (_LH)->Flink = ListElem->Flink; \ 349 if (!(_LH)->Flink) \ 350 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 351 } \ 352 } 353 354 /* 355 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 356 * remove the tail from the queue. 357 */ 358 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 359 360 /* 361 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 362 */ 363 #define QUEUE_PUSH_TAIL(_LH, _E) \ 364 if ((_LH)->Blink) \ 365 { \ 366 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 367 (PSINGLE_LIST_LINK)(_E); \ 368 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 369 } else { \ 370 (_LH)->Flink = \ 371 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 372 } \ 373 (_E)->Flink = (PSINGLE_LIST_LINK)0; 374 375 /* 376 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 377 */ 378 #define QUEUE_PUSH_HEAD(_LH, _E) \ 379 if (!((_E)->Flink = (_LH)->Flink)) \ 380 { \ 381 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 382 } \ 383 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 384 385 /* 386 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 387 * current element. 388 */ 389 #define QUEUE_GET_NEXT(_LH, _E) \ 390 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 391 (0) : ((_E)->Flink)) 392 393 /* 394 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 395 */ 396 #define QUEUE_APPEND(_LH1, _LH2) \ 397 if ((_LH2)->Flink) { \ 398 if ((_LH1)->Flink) { \ 399 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 400 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 401 } else { \ 402 (_LH1)->Flink = \ 403 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 404 } \ 405 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 406 } 407 408 409 #define QUEUE_SWITCH(_LH1, _LH2) \ 410 if ((_LH2)->Flink) { \ 411 (_LH1)->Flink = (_LH2)->Flink; \ 412 (_LH1)->Blink = (_LH2)->Blink; \ 413 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 414 } 415 416 /* 417 * Property lookups 418 */ 419 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 420 DDI_PROP_DONTPASS, (n)) 421 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 422 DDI_PROP_DONTPASS, (n), -1) 423 424 #ifdef E1000G_DEBUG 425 /* 426 * E1000G-specific ioctls ... 427 */ 428 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 429 + 'K') << 4) + 'G') << 4) 430 431 /* 432 * These diagnostic IOCTLS are enabled only in DEBUG drivers 433 */ 434 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 435 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 436 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 437 438 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 439 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 440 441 typedef struct { 442 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 443 uint64_t pp_acc_space; /* See #defines below */ 444 uint64_t pp_acc_offset; /* See regs definition */ 445 uint64_t pp_acc_data; /* output for peek */ 446 /* input for poke */ 447 } e1000g_peekpoke_t; 448 #endif /* E1000G_DEBUG */ 449 450 /* 451 * (Internal) return values from ioctl subroutines 452 */ 453 enum ioc_reply { 454 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 455 IOC_DONE, /* OK, reply sent */ 456 IOC_ACK, /* OK, just send ACK */ 457 IOC_REPLY /* OK, just send reply */ 458 }; 459 460 /* 461 * Named Data (ND) Parameter Management Structure 462 */ 463 typedef struct { 464 uint32_t ndp_info; 465 uint32_t ndp_min; 466 uint32_t ndp_max; 467 uint32_t ndp_val; 468 struct e1000g *ndp_instance; 469 char *ndp_name; 470 } nd_param_t; 471 472 /* 473 * The entry of the private dip list 474 */ 475 typedef struct _private_devi_list { 476 dev_info_t *priv_dip; 477 uint16_t flag; 478 struct _private_devi_list *next; 479 } private_devi_list_t; 480 481 /* 482 * A structure that points to the next entry in the queue. 483 */ 484 typedef struct _SINGLE_LIST_LINK { 485 struct _SINGLE_LIST_LINK *Flink; 486 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 487 488 /* 489 * A "ListHead" structure that points to the head and tail of a queue 490 */ 491 typedef struct _LIST_DESCRIBER { 492 struct _SINGLE_LIST_LINK *volatile Flink; 493 struct _SINGLE_LIST_LINK *volatile Blink; 494 } LIST_DESCRIBER, *PLIST_DESCRIBER; 495 496 /* 497 * Address-Length pair structure that stores descriptor info 498 */ 499 typedef struct _sw_desc { 500 uint64_t address; 501 uint32_t length; 502 } sw_desc_t, *p_sw_desc_t; 503 504 typedef struct _desc_array { 505 sw_desc_t descriptor[4]; 506 uint32_t elements; 507 } desc_array_t, *p_desc_array_t; 508 509 typedef enum { 510 USE_NONE, 511 USE_BCOPY, 512 USE_DVMA, 513 USE_DMA 514 } dma_type_t; 515 516 typedef struct _dma_buffer { 517 caddr_t address; 518 uint64_t dma_address; 519 ddi_acc_handle_t acc_handle; 520 ddi_dma_handle_t dma_handle; 521 size_t size; 522 size_t len; 523 } dma_buffer_t, *p_dma_buffer_t; 524 525 /* 526 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 527 * structure stores the additional information that is 528 * associated with every packet to be transmitted. It stores the 529 * message block pointer and the TBD addresses associated with 530 * the m_blk and also the link to the next tcb in the chain 531 */ 532 typedef struct _tx_sw_packet { 533 /* Link to the next tx_sw_packet in the list */ 534 SINGLE_LIST_LINK Link; 535 mblk_t *mp; 536 uint32_t num_desc; 537 uint32_t num_mblk_frag; 538 dma_type_t dma_type; 539 dma_type_t data_transfer_type; 540 ddi_dma_handle_t tx_dma_handle; 541 dma_buffer_t tx_buf[1]; 542 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 543 } tx_sw_packet_t, *p_tx_sw_packet_t; 544 545 /* 546 * This structure is similar to the rx_sw_packet structure used 547 * for Ndis. This structure stores information about the 2k 548 * aligned receive buffer into which the FX1000 DMA's frames. 549 * This structure is maintained as a linked list of many 550 * receiver buffer pointers. 551 */ 552 typedef struct _rx_sw_packet { 553 /* Link to the next rx_sw_packet_t in the list */ 554 SINGLE_LIST_LINK Link; 555 struct _rx_sw_packet *next; 556 uint16_t flag; 557 mblk_t *mp; 558 caddr_t rx_ring; 559 dma_type_t dma_type; 560 frtn_t free_rtn; 561 dma_buffer_t rx_buf[1]; 562 } rx_sw_packet_t, *p_rx_sw_packet_t; 563 564 typedef struct _mblk_list { 565 mblk_t *head; 566 mblk_t *tail; 567 } mblk_list_t, *p_mblk_list_t; 568 569 typedef struct _context_data { 570 uint32_t ether_header_size; 571 uint32_t cksum_flags; 572 uint32_t cksum_start; 573 uint32_t cksum_stuff; 574 uint16_t mss; 575 uint8_t hdr_len; 576 uint32_t pay_len; 577 boolean_t lso_flag; 578 } context_data_t; 579 580 typedef union _e1000g_ether_addr { 581 struct { 582 uint32_t high; 583 uint32_t low; 584 } reg; 585 struct { 586 uint8_t set; 587 uint8_t redundant; 588 uint8_t addr[ETHERADDRL]; 589 } mac; 590 } e1000g_ether_addr_t; 591 592 typedef struct _e1000g_stat { 593 594 kstat_named_t link_speed; /* Link Speed */ 595 kstat_named_t reset_count; /* Reset Count */ 596 597 kstat_named_t rx_error; /* Rx Error in Packet */ 598 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 599 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 600 601 kstat_named_t tx_no_desc; /* Tx No Desc */ 602 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 603 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 604 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 605 kstat_named_t tx_reschedule; /* Tx Reschedule */ 606 607 #ifdef E1000G_DEBUG 608 kstat_named_t rx_none; /* Rx No Incoming Data */ 609 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 610 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 611 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 612 613 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 614 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 615 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 616 kstat_named_t tx_recycle; /* Tx Recycle */ 617 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 618 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 619 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 620 kstat_named_t tx_copy; /* Tx Send Copy */ 621 kstat_named_t tx_bind; /* Tx Send Bind */ 622 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 623 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 624 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 625 #endif 626 627 kstat_named_t Crcerrs; /* CRC Error Count */ 628 kstat_named_t Symerrs; /* Symbol Error Count */ 629 kstat_named_t Mpc; /* Missed Packet Count */ 630 kstat_named_t Scc; /* Single Collision Count */ 631 kstat_named_t Ecol; /* Excessive Collision Count */ 632 kstat_named_t Mcc; /* Multiple Collision Count */ 633 kstat_named_t Latecol; /* Late Collision Count */ 634 kstat_named_t Colc; /* Collision Count */ 635 kstat_named_t Dc; /* Defer Count */ 636 kstat_named_t Sec; /* Sequence Error Count */ 637 kstat_named_t Rlec; /* Receive Length Error Count */ 638 kstat_named_t Xonrxc; /* XON Received Count */ 639 kstat_named_t Xontxc; /* XON Xmitted Count */ 640 kstat_named_t Xoffrxc; /* XOFF Received Count */ 641 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 642 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 643 #ifdef E1000G_DEBUG 644 kstat_named_t Prc64; /* Packets Received - 64b */ 645 kstat_named_t Prc127; /* Packets Received - 65-127b */ 646 kstat_named_t Prc255; /* Packets Received - 127-255b */ 647 kstat_named_t Prc511; /* Packets Received - 256-511b */ 648 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 649 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 650 #endif 651 kstat_named_t Gprc; /* Good Packets Received Count */ 652 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 653 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 654 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 655 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 656 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 657 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 658 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 659 kstat_named_t Rnbc; /* Receive No Buffers Count */ 660 kstat_named_t Ruc; /* Receive Undersize Count */ 661 kstat_named_t Rfc; /* Receive Frag Count */ 662 kstat_named_t Roc; /* Receive Oversize Count */ 663 kstat_named_t Rjc; /* Receive Jabber Count */ 664 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 665 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 666 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 667 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 668 kstat_named_t Tpr; /* Total Packets Received */ 669 kstat_named_t Tpt; /* Total Packets Xmitted */ 670 #ifdef E1000G_DEBUG 671 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 672 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 673 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 674 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 675 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 676 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 677 #endif 678 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 679 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 680 kstat_named_t Algnerrc; /* Alignment Error count */ 681 kstat_named_t Tuc; /* Transmit Underrun count */ 682 kstat_named_t Rxerrc; /* Rx Error Count */ 683 kstat_named_t Tncrs; /* Transmit with no CRS */ 684 kstat_named_t Cexterr; /* Carrier Extension Error count */ 685 kstat_named_t Rutec; /* Receive DMA too Early count */ 686 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 687 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 688 } e1000g_stat_t, *p_e1000g_stat_t; 689 690 typedef struct _e1000g_tx_ring { 691 kmutex_t tx_lock; 692 kmutex_t freelist_lock; 693 kmutex_t usedlist_lock; 694 /* 695 * Descriptor queue definitions 696 */ 697 ddi_dma_handle_t tbd_dma_handle; 698 ddi_acc_handle_t tbd_acc_handle; 699 struct e1000_tx_desc *tbd_area; 700 uint64_t tbd_dma_addr; 701 struct e1000_tx_desc *tbd_first; 702 struct e1000_tx_desc *tbd_last; 703 struct e1000_tx_desc *tbd_oldest; 704 struct e1000_tx_desc *tbd_next; 705 uint32_t tbd_avail; 706 /* 707 * Software packet structures definitions 708 */ 709 p_tx_sw_packet_t packet_area; 710 LIST_DESCRIBER used_list; 711 LIST_DESCRIBER free_list; 712 /* 713 * TCP/UDP Context Data Information 714 */ 715 context_data_t pre_context; 716 /* 717 * Timer definitions for 82547 718 */ 719 timeout_id_t timer_id_82547; 720 boolean_t timer_enable_82547; 721 /* 722 * reschedule when tx resource is available 723 */ 724 boolean_t resched_needed; 725 clock_t resched_timestamp; 726 uint32_t stall_watchdog; 727 uint32_t recycle_fail; 728 mblk_list_t mblks; 729 /* 730 * Statistics 731 */ 732 uint32_t stat_no_swpkt; 733 uint32_t stat_no_desc; 734 uint32_t stat_send_fail; 735 uint32_t stat_reschedule; 736 uint32_t stat_timer_reschedule; 737 uint32_t stat_over_size; 738 #ifdef E1000G_DEBUG 739 uint32_t stat_under_size; 740 uint32_t stat_exceed_frags; 741 uint32_t stat_empty_frags; 742 uint32_t stat_recycle; 743 uint32_t stat_recycle_intr; 744 uint32_t stat_recycle_retry; 745 uint32_t stat_recycle_none; 746 uint32_t stat_copy; 747 uint32_t stat_bind; 748 uint32_t stat_multi_copy; 749 uint32_t stat_multi_cookie; 750 uint32_t stat_lack_desc; 751 uint32_t stat_lso_header_fail; 752 #endif 753 /* 754 * Pointer to the adapter 755 */ 756 struct e1000g *adapter; 757 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 758 759 typedef struct _e1000g_rx_ring { 760 kmutex_t rx_lock; 761 kmutex_t freelist_lock; 762 kmutex_t recycle_lock; 763 /* 764 * Descriptor queue definitions 765 */ 766 ddi_dma_handle_t rbd_dma_handle; 767 ddi_acc_handle_t rbd_acc_handle; 768 struct e1000_rx_desc *rbd_area; 769 uint64_t rbd_dma_addr; 770 struct e1000_rx_desc *rbd_first; 771 struct e1000_rx_desc *rbd_last; 772 struct e1000_rx_desc *rbd_next; 773 /* 774 * Software packet structures definitions 775 */ 776 p_rx_sw_packet_t packet_area; 777 LIST_DESCRIBER recv_list; 778 LIST_DESCRIBER free_list; 779 LIST_DESCRIBER recycle_list; 780 781 p_rx_sw_packet_t pending_list; 782 uint32_t pending_count; 783 uint32_t avail_freepkt; 784 uint32_t recycle_freepkt; 785 uint32_t rx_mblk_len; 786 mblk_t *rx_mblk; 787 mblk_t *rx_mblk_tail; 788 mac_ring_handle_t mrh; 789 mac_ring_handle_t mrh_init; 790 uint64_t ring_gen_num; 791 boolean_t poll_flag; 792 793 /* 794 * Statistics 795 */ 796 uint32_t stat_error; 797 uint32_t stat_esballoc_fail; 798 uint32_t stat_allocb_fail; 799 uint32_t stat_exceed_pkt; 800 #ifdef E1000G_DEBUG 801 uint32_t stat_none; 802 uint32_t stat_multi_desc; 803 uint32_t stat_no_freepkt; 804 #endif 805 /* 806 * Pointer to the adapter 807 */ 808 struct e1000g *adapter; 809 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 810 811 typedef struct e1000g { 812 int instance; 813 dev_info_t *dip; 814 dev_info_t *priv_dip; 815 mac_handle_t mh; 816 mac_resource_handle_t mrh; 817 struct e1000_hw shared; 818 struct e1000g_osdep osdep; 819 820 uint32_t e1000g_state; 821 boolean_t e1000g_promisc; 822 boolean_t strip_crc; 823 boolean_t rx_buffer_setup; 824 boolean_t esb2_workaround; 825 link_state_t link_state; 826 uint32_t link_speed; 827 uint32_t link_duplex; 828 uint32_t master_latency_timer; 829 uint32_t smartspeed; /* smartspeed w/a counter */ 830 uint32_t init_count; 831 uint32_t reset_count; 832 uint32_t attach_progress; /* attach tracking */ 833 uint32_t loopback_mode; 834 835 uint32_t tx_desc_num; 836 uint32_t tx_freelist_num; 837 uint32_t rx_desc_num; 838 uint32_t rx_freelist_num; 839 uint32_t tx_buffer_size; 840 uint32_t rx_buffer_size; 841 842 uint32_t tx_link_down_timeout; 843 uint32_t tx_bcopy_thresh; 844 uint32_t rx_limit_onintr; 845 uint32_t rx_bcopy_thresh; 846 uint32_t rx_buf_align; 847 uint32_t desc_align; 848 849 boolean_t intr_adaptive; 850 boolean_t tx_intr_enable; 851 uint32_t tx_intr_delay; 852 uint32_t tx_intr_abs_delay; 853 uint32_t rx_intr_delay; 854 uint32_t rx_intr_abs_delay; 855 uint32_t intr_throttling_rate; 856 857 uint32_t default_mtu; 858 uint32_t max_frame_size; 859 uint32_t min_frame_size; 860 861 boolean_t watchdog_timer_enabled; 862 boolean_t watchdog_timer_started; 863 timeout_id_t watchdog_tid; 864 boolean_t link_complete; 865 timeout_id_t link_tid; 866 867 e1000g_rx_ring_t rx_ring[1]; 868 e1000g_tx_ring_t tx_ring[1]; 869 mac_group_handle_t rx_group; 870 871 /* 872 * Rx and Tx packet count for interrupt adaptive setting 873 */ 874 uint32_t rx_pkt_cnt; 875 uint32_t tx_pkt_cnt; 876 877 /* 878 * The watchdog_lock must be held when updateing the 879 * timeout fields in struct e1000g, that is, 880 * watchdog_tid, watchdog_timer_started. 881 */ 882 kmutex_t watchdog_lock; 883 /* 884 * The link_lock protects the link fields in struct e1000g, 885 * such as link_state, link_speed, link_duplex, link_complete, and 886 * link_tid. 887 */ 888 kmutex_t link_lock; 889 /* 890 * The chip_lock assures that the Rx/Tx process must be 891 * stopped while other functions change the hardware 892 * configuration of e1000g card, such as e1000g_reset(), 893 * e1000g_reset_hw() etc are executed. 894 */ 895 krwlock_t chip_lock; 896 897 boolean_t unicst_init; 898 uint32_t unicst_avail; 899 uint32_t unicst_total; 900 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 901 902 uint32_t mcast_count; 903 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 904 905 ulong_t sys_page_sz; 906 #ifdef __sparc 907 uint_t dvma_page_num; 908 #endif 909 910 boolean_t msi_enable; 911 boolean_t tx_hcksum_enable; 912 boolean_t lso_enable; 913 boolean_t lso_premature_issue; 914 boolean_t mem_workaround_82546; 915 int intr_type; 916 int intr_cnt; 917 int intr_cap; 918 size_t intr_size; 919 uint_t intr_pri; 920 ddi_intr_handle_t *htable; 921 922 int tx_softint_pri; 923 ddi_softint_handle_t tx_softint_handle; 924 925 kstat_t *e1000g_ksp; 926 927 boolean_t poll_mode; 928 929 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 930 uint16_t phy_status; /* contents of PHY_STATUS */ 931 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 932 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 933 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 934 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 935 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 936 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 937 938 /* 939 * FMA capabilities 940 */ 941 int fm_capabilities; 942 943 uint32_t param_en_1000fdx:1, 944 param_en_1000hdx:1, 945 param_en_100fdx:1, 946 param_en_100hdx:1, 947 param_en_10fdx:1, 948 param_en_10hdx:1, 949 param_autoneg_cap:1, 950 param_pause_cap:1, 951 param_asym_pause_cap:1, 952 param_1000fdx_cap:1, 953 param_1000hdx_cap:1, 954 param_100t4_cap:1, 955 param_100fdx_cap:1, 956 param_100hdx_cap:1, 957 param_10fdx_cap:1, 958 param_10hdx_cap:1, 959 param_adv_autoneg:1, 960 param_adv_pause:1, 961 param_adv_asym_pause:1, 962 param_adv_1000fdx:1, 963 param_adv_1000hdx:1, 964 param_adv_100t4:1, 965 param_adv_100fdx:1, 966 param_adv_100hdx:1, 967 param_adv_10fdx:1, 968 param_adv_10hdx:1, 969 param_lp_autoneg:1, 970 param_lp_pause:1, 971 param_lp_asym_pause:1, 972 param_lp_1000fdx:1, 973 param_lp_1000hdx:1, 974 param_lp_100t4:1; 975 976 uint32_t param_lp_100fdx:1, 977 param_lp_100hdx:1, 978 param_lp_10fdx:1, 979 param_lp_10hdx:1, 980 param_pad_to_32:28; 981 982 } e1000g_t; 983 984 985 /* 986 * Function prototypes 987 */ 988 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 989 void e1000g_release_dma_resources(struct e1000g *Adapter); 990 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 991 void e1000g_tx_setup(struct e1000g *Adapter); 992 void e1000g_rx_setup(struct e1000g *Adapter); 993 void e1000g_setup_multicast(struct e1000g *Adapter); 994 995 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 996 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 997 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 998 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 999 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1000 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz); 1001 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1002 1003 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1004 int e1000g_init_stats(struct e1000g *Adapter); 1005 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1006 uint32_t frame_len, uint8_t *mac_addr); 1007 1008 void e1000g_clear_interrupt(struct e1000g *Adapter); 1009 void e1000g_mask_interrupt(struct e1000g *Adapter); 1010 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1011 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1012 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1013 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1014 void e1000_enable_pciex_master(struct e1000_hw *hw); 1015 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1016 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1017 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1018 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1019 int e1000g_reset_link(struct e1000g *Adapter); 1020 1021 /* 1022 * Global variables 1023 */ 1024 extern boolean_t e1000g_force_detach; 1025 extern uint32_t e1000g_mblks_pending; 1026 extern krwlock_t e1000g_rx_detach_lock; 1027 extern private_devi_list_t *e1000g_private_devi_list; 1028 extern int e1000g_poll_mode; 1029 1030 #ifdef __cplusplus 1031 } 1032 #endif 1033 1034 #endif /* _E1000G_SW_H */ 1035