1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac_provider.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 /* Driver states */ 81 #define E1000G_UNKNOWN 0x00 82 #define E1000G_INITIALIZED 0x01 83 #define E1000G_STARTED 0x02 84 #define E1000G_SUSPENDED 0x04 85 #define E1000G_ERROR 0x80 86 87 #define JUMBO_FRAG_LENGTH 4096 88 89 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 90 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 91 #define MCAST_ALLOC_SIZE 256 92 93 /* 94 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 95 * + one for cross page split 96 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 97 * two for the workaround of the 82546 chip 98 */ 99 #define MAX_COOKIES 18 100 #define MAX_TX_DESC_PER_PACKET 21 101 102 /* 103 * constants used in setting flow control thresholds 104 */ 105 #define E1000_PBA_MASK 0xffff 106 #define E1000_PBA_SHIFT 10 107 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 108 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 109 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 110 111 #define MAX_NUM_TX_DESCRIPTOR 4096 112 #define MAX_NUM_RX_DESCRIPTOR 4096 113 #define MAX_NUM_RX_FREELIST 4096 114 #define MAX_NUM_TX_FREELIST 4096 115 #define MAX_RX_LIMIT_ON_INTR 4096 116 #define MAX_RX_INTR_DELAY 65535 117 #define MAX_RX_INTR_ABS_DELAY 65535 118 #define MAX_TX_INTR_DELAY 65535 119 #define MAX_TX_INTR_ABS_DELAY 65535 120 #define MAX_INTR_THROTTLING 65535 121 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 122 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 123 #define MAX_MCAST_NUM 8192 124 125 #define MIN_NUM_TX_DESCRIPTOR 80 126 #define MIN_NUM_RX_DESCRIPTOR 80 127 #define MIN_NUM_RX_FREELIST 64 128 #define MIN_NUM_TX_FREELIST 80 129 #define MIN_RX_LIMIT_ON_INTR 16 130 #define MIN_RX_INTR_DELAY 0 131 #define MIN_RX_INTR_ABS_DELAY 0 132 #define MIN_TX_INTR_DELAY 0 133 #define MIN_TX_INTR_ABS_DELAY 0 134 #define MIN_INTR_THROTTLING 0 135 #define MIN_RX_BCOPY_THRESHOLD 0 136 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 137 #define MIN_MCAST_NUM 8 138 139 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 140 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 141 #define DEFAULT_NUM_RX_FREELIST 4096 142 #define DEFAULT_NUM_TX_FREELIST 2304 143 #define DEFAULT_JUMBO_NUM_RX_DESC 1024 144 #define DEFAULT_JUMBO_NUM_TX_DESC 1024 145 #define DEFAULT_JUMBO_NUM_RX_BUF 2048 146 #define DEFAULT_JUMBO_NUM_TX_BUF 1152 147 #define DEFAULT_RX_LIMIT_ON_INTR 128 148 149 #ifdef __sparc 150 #define MAX_INTR_PER_SEC 7100 151 #define MIN_INTR_PER_SEC 3000 152 #define DEFAULT_INTR_PACKET_LOW 5 153 #define DEFAULT_INTR_PACKET_HIGH 128 154 #else 155 #define MAX_INTR_PER_SEC 15000 156 #define MIN_INTR_PER_SEC 4000 157 #define DEFAULT_INTR_PACKET_LOW 10 158 #define DEFAULT_INTR_PACKET_HIGH 48 159 #endif 160 161 #define DEFAULT_RX_INTR_DELAY 0 162 #define DEFAULT_RX_INTR_ABS_DELAY 64 163 #define DEFAULT_TX_INTR_DELAY 64 164 #define DEFAULT_TX_INTR_ABS_DELAY 64 165 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 166 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 167 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 168 169 #define DEFAULT_RX_BCOPY_THRESHOLD 128 170 #define DEFAULT_TX_BCOPY_THRESHOLD 512 171 #define DEFAULT_TX_UPDATE_THRESHOLD 256 172 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 173 174 #define DEFAULT_TX_INTR_ENABLE 1 175 #define DEFAULT_FLOW_CONTROL 3 176 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 177 /* which is normally 0x040 */ 178 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 179 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 180 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 181 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 182 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 183 184 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 185 #define RX_DRAIN_TIME (200) /* # milliseconds recv drain */ 186 187 #define TX_STALL_TIME_2S (200) /* in unit of tick */ 188 #define TX_STALL_TIME_8S (800) /* in unit of tick */ 189 190 /* 191 * The size of the receive/transmite buffers 192 */ 193 #define E1000_RX_BUFFER_SIZE_2K (2048) 194 #define E1000_RX_BUFFER_SIZE_4K (4096) 195 #define E1000_RX_BUFFER_SIZE_8K (8192) 196 #define E1000_RX_BUFFER_SIZE_16K (16384) 197 198 #define E1000_TX_BUFFER_SIZE_2K (2048) 199 #define E1000_TX_BUFFER_SIZE_4K (4096) 200 #define E1000_TX_BUFFER_SIZE_8K (8192) 201 #define E1000_TX_BUFFER_SIZE_16K (16384) 202 203 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 204 205 #define E1000G_RX_NORMAL 0x0 206 #define E1000G_RX_STOPPED 0x1 207 208 #define E1000G_CHAIN_NO_LIMIT 0 209 210 /* 211 * definitions for smartspeed workaround 212 */ 213 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 214 /* or 30 seconds */ 215 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 216 /* or 6 seconds */ 217 218 /* 219 * Definitions for module_info. 220 */ 221 #define WSNAME "e1000g" /* module name */ 222 223 /* 224 * Defined for IP header alignment. We also need to preserve space for 225 * VLAN tag (4 bytes) 226 */ 227 #define E1000G_IPALIGNROOM 6 228 #define E1000G_IPALIGNPRESERVEROOM 64 229 230 /* 231 * bit flags for 'attach_progress' which is a member variable in struct e1000g 232 */ 233 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 234 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 235 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 236 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 237 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 238 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 239 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 240 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 241 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 242 /* 0200 used to be PROGRESS_NDD. Now unused */ 243 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 244 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 245 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 246 247 /* 248 * Speed and Duplex Settings 249 */ 250 #define GDIAG_10_HALF 1 251 #define GDIAG_10_FULL 2 252 #define GDIAG_100_HALF 3 253 #define GDIAG_100_FULL 4 254 #define GDIAG_1000_FULL 6 255 #define GDIAG_ANY 7 256 257 /* 258 * Coexist Workaround RP: 07/04/03 259 * 82544 Workaround : Co-existence 260 */ 261 #define MAX_TX_BUF_SIZE (8 * 1024) 262 263 /* 264 * Defines for Jumbo Frame 265 */ 266 #define FRAME_SIZE_UPTO_2K 2048 267 #define FRAME_SIZE_UPTO_4K 4096 268 #define FRAME_SIZE_UPTO_8K 8192 269 #define FRAME_SIZE_UPTO_16K 16384 270 #define FRAME_SIZE_UPTO_9K 9234 271 272 #define DEFAULT_MTU ETHERMTU 273 #define MAXIMUM_MTU_4K 4096 274 #define MAXIMUM_MTU_9K 9216 275 276 #define DEFAULT_FRAME_SIZE \ 277 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 278 #define MAXIMUM_FRAME_SIZE \ 279 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 280 281 #define E1000_LSO_MAXLEN 65535 282 283 /* Defines for Tx stall check */ 284 #define E1000G_STALL_WATCHDOG_COUNT 8 285 286 #define MAX_TX_LINK_DOWN_TIMEOUT 8 287 288 /* Defines for DVMA */ 289 #ifdef __sparc 290 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 291 #endif 292 293 /* 294 * Loopback definitions 295 */ 296 #define E1000G_LB_NONE 0 297 #define E1000G_LB_EXTERNAL_1000 1 298 #define E1000G_LB_EXTERNAL_100 2 299 #define E1000G_LB_EXTERNAL_10 3 300 #define E1000G_LB_INTERNAL_PHY 4 301 302 /* 303 * Private dip list definitions 304 */ 305 #define E1000G_PRIV_DEVI_ATTACH 0x0 306 #define E1000G_PRIV_DEVI_DETACH 0x1 307 308 /* 309 * Tx descriptor LENGTH field mask 310 */ 311 #define E1000G_TBD_LENGTH_MASK 0x000fffff 312 313 #define E1000G_IS_VLAN_PACKET(ptr) \ 314 ((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) == \ 315 htons(ETHERTYPE_VLAN)) 316 317 /* 318 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 319 */ 320 #define QUEUE_INIT_LIST(_LH) \ 321 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 322 323 /* 324 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 325 */ 326 #define IS_QUEUE_EMPTY(_LH) \ 327 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 328 329 /* 330 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 331 * not remove the head from the queue. 332 */ 333 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 334 335 /* 336 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 337 */ 338 #define QUEUE_REMOVE_HEAD(_LH) \ 339 { \ 340 PSINGLE_LIST_LINK ListElem; \ 341 if (ListElem = (_LH)->Flink) \ 342 { \ 343 if (!((_LH)->Flink = ListElem->Flink)) \ 344 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 345 } \ 346 } 347 348 /* 349 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 350 * and return it (this differs from QUEUE_REMOVE_HEAD only in 351 * the 1st line). 352 */ 353 #define QUEUE_POP_HEAD(_LH) \ 354 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 355 { \ 356 PSINGLE_LIST_LINK ListElem; \ 357 ListElem = (_LH)->Flink; \ 358 if (ListElem) \ 359 { \ 360 (_LH)->Flink = ListElem->Flink; \ 361 if (!(_LH)->Flink) \ 362 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 363 } \ 364 } 365 366 /* 367 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 368 * remove the tail from the queue. 369 */ 370 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 371 372 /* 373 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 374 */ 375 #define QUEUE_PUSH_TAIL(_LH, _E) \ 376 if ((_LH)->Blink) \ 377 { \ 378 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 379 (PSINGLE_LIST_LINK)(_E); \ 380 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 381 } else { \ 382 (_LH)->Flink = \ 383 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 384 } \ 385 (_E)->Flink = (PSINGLE_LIST_LINK)0; 386 387 /* 388 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 389 */ 390 #define QUEUE_PUSH_HEAD(_LH, _E) \ 391 if (!((_E)->Flink = (_LH)->Flink)) \ 392 { \ 393 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 394 } \ 395 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 396 397 /* 398 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 399 * current element. 400 */ 401 #define QUEUE_GET_NEXT(_LH, _E) \ 402 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 403 (0) : ((_E)->Flink)) 404 405 /* 406 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 407 */ 408 #define QUEUE_APPEND(_LH1, _LH2) \ 409 if ((_LH2)->Flink) { \ 410 if ((_LH1)->Flink) { \ 411 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 412 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 413 } else { \ 414 (_LH1)->Flink = \ 415 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 416 } \ 417 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 418 } 419 420 421 #define QUEUE_SWITCH(_LH1, _LH2) \ 422 if ((_LH2)->Flink) { \ 423 (_LH1)->Flink = (_LH2)->Flink; \ 424 (_LH1)->Blink = (_LH2)->Blink; \ 425 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 426 } 427 428 /* 429 * Property lookups 430 */ 431 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 432 DDI_PROP_DONTPASS, (n)) 433 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 434 DDI_PROP_DONTPASS, (n), -1) 435 436 #ifdef E1000G_DEBUG 437 /* 438 * E1000G-specific ioctls ... 439 */ 440 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 441 + 'K') << 4) + 'G') << 4) 442 443 /* 444 * These diagnostic IOCTLS are enabled only in DEBUG drivers 445 */ 446 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 447 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 448 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 449 450 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 451 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 452 453 typedef struct { 454 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 455 uint64_t pp_acc_space; /* See #defines below */ 456 uint64_t pp_acc_offset; /* See regs definition */ 457 uint64_t pp_acc_data; /* output for peek */ 458 /* input for poke */ 459 } e1000g_peekpoke_t; 460 #endif /* E1000G_DEBUG */ 461 462 /* 463 * (Internal) return values from ioctl subroutines 464 */ 465 enum ioc_reply { 466 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 467 IOC_DONE, /* OK, reply sent */ 468 IOC_ACK, /* OK, just send ACK */ 469 IOC_REPLY /* OK, just send reply */ 470 }; 471 472 /* 473 * Named Data (ND) Parameter Management Structure 474 */ 475 typedef struct { 476 uint32_t ndp_info; 477 uint32_t ndp_min; 478 uint32_t ndp_max; 479 uint32_t ndp_val; 480 struct e1000g *ndp_instance; 481 char *ndp_name; 482 } nd_param_t; 483 484 /* 485 * The entry of the private dip list 486 */ 487 typedef struct _private_devi_list { 488 dev_info_t *priv_dip; 489 uint32_t flag; 490 uint32_t pending_rx_count; 491 struct _private_devi_list *prev; 492 struct _private_devi_list *next; 493 } private_devi_list_t; 494 495 /* 496 * A structure that points to the next entry in the queue. 497 */ 498 typedef struct _SINGLE_LIST_LINK { 499 struct _SINGLE_LIST_LINK *Flink; 500 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 501 502 /* 503 * A "ListHead" structure that points to the head and tail of a queue 504 */ 505 typedef struct _LIST_DESCRIBER { 506 struct _SINGLE_LIST_LINK *volatile Flink; 507 struct _SINGLE_LIST_LINK *volatile Blink; 508 } LIST_DESCRIBER, *PLIST_DESCRIBER; 509 510 enum e1000g_bar_type { 511 E1000G_BAR_CONFIG = 0, 512 E1000G_BAR_IO, 513 E1000G_BAR_MEM32, 514 E1000G_BAR_MEM64 515 }; 516 517 typedef struct { 518 enum e1000g_bar_type type; 519 int rnumber; 520 } bar_info_t; 521 522 /* 523 * Address-Length pair structure that stores descriptor info 524 */ 525 typedef struct _sw_desc { 526 uint64_t address; 527 uint32_t length; 528 } sw_desc_t, *p_sw_desc_t; 529 530 typedef struct _desc_array { 531 sw_desc_t descriptor[4]; 532 uint32_t elements; 533 } desc_array_t, *p_desc_array_t; 534 535 typedef enum { 536 USE_NONE, 537 USE_BCOPY, 538 USE_DVMA, 539 USE_DMA 540 } dma_type_t; 541 542 typedef struct _dma_buffer { 543 caddr_t address; 544 uint64_t dma_address; 545 ddi_acc_handle_t acc_handle; 546 ddi_dma_handle_t dma_handle; 547 size_t size; 548 size_t len; 549 } dma_buffer_t, *p_dma_buffer_t; 550 551 /* 552 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 553 * structure stores the additional information that is 554 * associated with every packet to be transmitted. It stores the 555 * message block pointer and the TBD addresses associated with 556 * the m_blk and also the link to the next tcb in the chain 557 */ 558 typedef struct _tx_sw_packet { 559 /* Link to the next tx_sw_packet in the list */ 560 SINGLE_LIST_LINK Link; 561 mblk_t *mp; 562 uint32_t num_desc; 563 uint32_t num_mblk_frag; 564 dma_type_t dma_type; 565 dma_type_t data_transfer_type; 566 ddi_dma_handle_t tx_dma_handle; 567 dma_buffer_t tx_buf[1]; 568 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 569 int64_t tickstamp; 570 } tx_sw_packet_t, *p_tx_sw_packet_t; 571 572 /* 573 * This structure is similar to the rx_sw_packet structure used 574 * for Ndis. This structure stores information about the 2k 575 * aligned receive buffer into which the FX1000 DMA's frames. 576 * This structure is maintained as a linked list of many 577 * receiver buffer pointers. 578 */ 579 typedef struct _rx_sw_packet { 580 /* Link to the next rx_sw_packet_t in the list */ 581 SINGLE_LIST_LINK Link; 582 struct _rx_sw_packet *next; 583 uint32_t ref_cnt; 584 mblk_t *mp; 585 caddr_t rx_data; 586 dma_type_t dma_type; 587 frtn_t free_rtn; 588 dma_buffer_t rx_buf[1]; 589 } rx_sw_packet_t, *p_rx_sw_packet_t; 590 591 typedef struct _mblk_list { 592 mblk_t *head; 593 mblk_t *tail; 594 } mblk_list_t, *p_mblk_list_t; 595 596 typedef struct _context_data { 597 uint32_t ether_header_size; 598 uint32_t cksum_flags; 599 uint32_t cksum_start; 600 uint32_t cksum_stuff; 601 uint16_t mss; 602 uint8_t hdr_len; 603 uint32_t pay_len; 604 boolean_t lso_flag; 605 } context_data_t; 606 607 typedef union _e1000g_ether_addr { 608 struct { 609 uint32_t high; 610 uint32_t low; 611 } reg; 612 struct { 613 uint8_t set; 614 uint8_t redundant; 615 uint8_t addr[ETHERADDRL]; 616 } mac; 617 } e1000g_ether_addr_t; 618 619 typedef struct _e1000g_stat { 620 621 kstat_named_t link_speed; /* Link Speed */ 622 kstat_named_t reset_count; /* Reset Count */ 623 624 kstat_named_t rx_error; /* Rx Error in Packet */ 625 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 626 kstat_named_t rx_size_error; /* Rx Size Error */ 627 628 kstat_named_t tx_no_desc; /* Tx No Desc */ 629 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 630 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 631 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 632 kstat_named_t tx_reschedule; /* Tx Reschedule */ 633 634 #ifdef E1000G_DEBUG 635 kstat_named_t rx_none; /* Rx No Incoming Data */ 636 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 637 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 638 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 639 640 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 641 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 642 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 643 kstat_named_t tx_recycle; /* Tx Recycle */ 644 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 645 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 646 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 647 kstat_named_t tx_copy; /* Tx Send Copy */ 648 kstat_named_t tx_bind; /* Tx Send Bind */ 649 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 650 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 651 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 652 #endif 653 654 kstat_named_t Crcerrs; /* CRC Error Count */ 655 kstat_named_t Symerrs; /* Symbol Error Count */ 656 kstat_named_t Mpc; /* Missed Packet Count */ 657 kstat_named_t Scc; /* Single Collision Count */ 658 kstat_named_t Ecol; /* Excessive Collision Count */ 659 kstat_named_t Mcc; /* Multiple Collision Count */ 660 kstat_named_t Latecol; /* Late Collision Count */ 661 kstat_named_t Colc; /* Collision Count */ 662 kstat_named_t Dc; /* Defer Count */ 663 kstat_named_t Sec; /* Sequence Error Count */ 664 kstat_named_t Rlec; /* Receive Length Error Count */ 665 kstat_named_t Xonrxc; /* XON Received Count */ 666 kstat_named_t Xontxc; /* XON Xmitted Count */ 667 kstat_named_t Xoffrxc; /* XOFF Received Count */ 668 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 669 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 670 #ifdef E1000G_DEBUG 671 kstat_named_t Prc64; /* Packets Received - 64b */ 672 kstat_named_t Prc127; /* Packets Received - 65-127b */ 673 kstat_named_t Prc255; /* Packets Received - 127-255b */ 674 kstat_named_t Prc511; /* Packets Received - 256-511b */ 675 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 676 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 677 #endif 678 kstat_named_t Gprc; /* Good Packets Received Count */ 679 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 680 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 681 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 682 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 683 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 684 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 685 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 686 kstat_named_t Rnbc; /* Receive No Buffers Count */ 687 kstat_named_t Ruc; /* Receive Undersize Count */ 688 kstat_named_t Rfc; /* Receive Frag Count */ 689 kstat_named_t Roc; /* Receive Oversize Count */ 690 kstat_named_t Rjc; /* Receive Jabber Count */ 691 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 692 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 693 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 694 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 695 kstat_named_t Tpr; /* Total Packets Received */ 696 kstat_named_t Tpt; /* Total Packets Xmitted */ 697 #ifdef E1000G_DEBUG 698 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 699 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 700 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 701 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 702 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 703 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 704 #endif 705 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 706 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 707 kstat_named_t Algnerrc; /* Alignment Error count */ 708 kstat_named_t Tuc; /* Transmit Underrun count */ 709 kstat_named_t Rxerrc; /* Rx Error Count */ 710 kstat_named_t Tncrs; /* Transmit with no CRS */ 711 kstat_named_t Cexterr; /* Carrier Extension Error count */ 712 kstat_named_t Rutec; /* Receive DMA too Early count */ 713 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 714 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 715 } e1000g_stat_t, *p_e1000g_stat_t; 716 717 typedef struct _e1000g_tx_ring { 718 kmutex_t tx_lock; 719 kmutex_t freelist_lock; 720 kmutex_t usedlist_lock; 721 /* 722 * Descriptor queue definitions 723 */ 724 ddi_dma_handle_t tbd_dma_handle; 725 ddi_acc_handle_t tbd_acc_handle; 726 struct e1000_tx_desc *tbd_area; 727 uint64_t tbd_dma_addr; 728 struct e1000_tx_desc *tbd_first; 729 struct e1000_tx_desc *tbd_last; 730 struct e1000_tx_desc *tbd_oldest; 731 struct e1000_tx_desc *tbd_next; 732 uint32_t tbd_avail; 733 /* 734 * Software packet structures definitions 735 */ 736 p_tx_sw_packet_t packet_area; 737 LIST_DESCRIBER used_list; 738 LIST_DESCRIBER free_list; 739 /* 740 * TCP/UDP Context Data Information 741 */ 742 context_data_t pre_context; 743 /* 744 * Timer definitions for 82547 745 */ 746 timeout_id_t timer_id_82547; 747 boolean_t timer_enable_82547; 748 /* 749 * reschedule when tx resource is available 750 */ 751 boolean_t resched_needed; 752 clock_t resched_timestamp; 753 mblk_list_t mblks; 754 /* 755 * Statistics 756 */ 757 uint32_t stat_no_swpkt; 758 uint32_t stat_no_desc; 759 uint32_t stat_send_fail; 760 uint32_t stat_reschedule; 761 uint32_t stat_timer_reschedule; 762 uint32_t stat_over_size; 763 #ifdef E1000G_DEBUG 764 uint32_t stat_under_size; 765 uint32_t stat_exceed_frags; 766 uint32_t stat_empty_frags; 767 uint32_t stat_recycle; 768 uint32_t stat_recycle_intr; 769 uint32_t stat_recycle_retry; 770 uint32_t stat_recycle_none; 771 uint32_t stat_copy; 772 uint32_t stat_bind; 773 uint32_t stat_multi_copy; 774 uint32_t stat_multi_cookie; 775 uint32_t stat_lack_desc; 776 uint32_t stat_lso_header_fail; 777 #endif 778 /* 779 * Pointer to the adapter 780 */ 781 struct e1000g *adapter; 782 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 783 784 typedef struct _e1000g_rx_data { 785 kmutex_t freelist_lock; 786 kmutex_t recycle_lock; 787 /* 788 * Descriptor queue definitions 789 */ 790 ddi_dma_handle_t rbd_dma_handle; 791 ddi_acc_handle_t rbd_acc_handle; 792 struct e1000_rx_desc *rbd_area; 793 uint64_t rbd_dma_addr; 794 struct e1000_rx_desc *rbd_first; 795 struct e1000_rx_desc *rbd_last; 796 struct e1000_rx_desc *rbd_next; 797 /* 798 * Software packet structures definitions 799 */ 800 p_rx_sw_packet_t packet_area; 801 LIST_DESCRIBER recv_list; 802 LIST_DESCRIBER free_list; 803 LIST_DESCRIBER recycle_list; 804 uint32_t flag; 805 806 uint32_t pending_count; 807 uint32_t avail_freepkt; 808 uint32_t recycle_freepkt; 809 uint32_t rx_mblk_len; 810 mblk_t *rx_mblk; 811 mblk_t *rx_mblk_tail; 812 813 private_devi_list_t *priv_devi_node; 814 struct _e1000g_rx_ring *rx_ring; 815 } e1000g_rx_data_t; 816 817 typedef struct _e1000g_rx_ring { 818 e1000g_rx_data_t *rx_data; 819 820 kmutex_t rx_lock; 821 822 mac_ring_handle_t mrh; 823 mac_ring_handle_t mrh_init; 824 uint64_t ring_gen_num; 825 boolean_t poll_flag; 826 827 /* 828 * Statistics 829 */ 830 uint32_t stat_error; 831 uint32_t stat_allocb_fail; 832 uint32_t stat_exceed_pkt; 833 uint32_t stat_size_error; 834 #ifdef E1000G_DEBUG 835 uint32_t stat_none; 836 uint32_t stat_multi_desc; 837 uint32_t stat_no_freepkt; 838 #endif 839 /* 840 * Pointer to the adapter 841 */ 842 struct e1000g *adapter; 843 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 844 845 typedef struct e1000g { 846 int instance; 847 dev_info_t *dip; 848 dev_info_t *priv_dip; 849 private_devi_list_t *priv_devi_node; 850 mac_handle_t mh; 851 mac_resource_handle_t mrh; 852 struct e1000_hw shared; 853 struct e1000g_osdep osdep; 854 855 uint32_t e1000g_state; 856 boolean_t e1000g_promisc; 857 boolean_t strip_crc; 858 boolean_t rx_buffer_setup; 859 boolean_t esb2_workaround; 860 link_state_t link_state; 861 uint32_t link_speed; 862 uint32_t link_duplex; 863 uint32_t master_latency_timer; 864 uint32_t smartspeed; /* smartspeed w/a counter */ 865 uint32_t init_count; 866 uint32_t reset_count; 867 boolean_t reset_flag; 868 uint32_t stall_threshold; 869 boolean_t stall_flag; 870 uint32_t attach_progress; /* attach tracking */ 871 uint32_t loopback_mode; 872 uint32_t pending_rx_count; 873 874 uint32_t tx_desc_num; 875 uint32_t tx_freelist_num; 876 uint32_t rx_desc_num; 877 uint32_t rx_freelist_num; 878 uint32_t tx_buffer_size; 879 uint32_t rx_buffer_size; 880 881 uint32_t tx_link_down_timeout; 882 uint32_t tx_bcopy_thresh; 883 uint32_t rx_limit_onintr; 884 uint32_t rx_bcopy_thresh; 885 uint32_t rx_buf_align; 886 uint32_t desc_align; 887 888 boolean_t intr_adaptive; 889 boolean_t tx_intr_enable; 890 uint32_t tx_intr_delay; 891 uint32_t tx_intr_abs_delay; 892 uint32_t rx_intr_delay; 893 uint32_t rx_intr_abs_delay; 894 uint32_t intr_throttling_rate; 895 896 uint32_t tx_desc_num_flag:1, 897 rx_desc_num_flag:1, 898 tx_buf_num_flag:1, 899 rx_buf_num_flag:1, 900 pad_to_32:28; 901 902 uint32_t default_mtu; 903 uint32_t max_mtu; 904 uint32_t max_frame_size; 905 uint32_t min_frame_size; 906 907 boolean_t watchdog_timer_enabled; 908 boolean_t watchdog_timer_started; 909 timeout_id_t watchdog_tid; 910 boolean_t link_complete; 911 timeout_id_t link_tid; 912 913 e1000g_rx_ring_t rx_ring[1]; 914 e1000g_tx_ring_t tx_ring[1]; 915 mac_group_handle_t rx_group; 916 917 /* 918 * Rx and Tx packet count for interrupt adaptive setting 919 */ 920 uint32_t rx_pkt_cnt; 921 uint32_t tx_pkt_cnt; 922 923 /* 924 * The watchdog_lock must be held when updateing the 925 * timeout fields in struct e1000g, that is, 926 * watchdog_tid, watchdog_timer_started. 927 */ 928 kmutex_t watchdog_lock; 929 /* 930 * The link_lock protects the link fields in struct e1000g, 931 * such as link_state, link_speed, link_duplex, link_complete, and 932 * link_tid. 933 */ 934 kmutex_t link_lock; 935 /* 936 * The chip_lock assures that the Rx/Tx process must be 937 * stopped while other functions change the hardware 938 * configuration of e1000g card, such as e1000g_reset(), 939 * e1000g_reset_hw() etc are executed. 940 */ 941 krwlock_t chip_lock; 942 943 boolean_t unicst_init; 944 uint32_t unicst_avail; 945 uint32_t unicst_total; 946 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 947 948 uint32_t mcast_count; 949 uint32_t mcast_max_num; 950 uint32_t mcast_alloc_count; 951 struct ether_addr *mcast_table; 952 953 ulong_t sys_page_sz; 954 #ifdef __sparc 955 uint_t dvma_page_num; 956 #endif 957 958 boolean_t msi_enable; 959 boolean_t tx_hcksum_enable; 960 boolean_t lso_enable; 961 boolean_t lso_premature_issue; 962 boolean_t mem_workaround_82546; 963 int intr_type; 964 int intr_cnt; 965 int intr_cap; 966 size_t intr_size; 967 uint_t intr_pri; 968 ddi_intr_handle_t *htable; 969 970 int tx_softint_pri; 971 ddi_softint_handle_t tx_softint_handle; 972 973 kstat_t *e1000g_ksp; 974 975 boolean_t poll_mode; 976 977 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 978 uint16_t phy_status; /* contents of PHY_STATUS */ 979 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 980 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 981 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 982 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 983 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 984 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 985 986 /* 987 * FMA capabilities 988 */ 989 int fm_capabilities; 990 991 uint32_t param_en_1000fdx:1, 992 param_en_1000hdx:1, 993 param_en_100fdx:1, 994 param_en_100hdx:1, 995 param_en_10fdx:1, 996 param_en_10hdx:1, 997 param_autoneg_cap:1, 998 param_pause_cap:1, 999 param_asym_pause_cap:1, 1000 param_1000fdx_cap:1, 1001 param_1000hdx_cap:1, 1002 param_100t4_cap:1, 1003 param_100fdx_cap:1, 1004 param_100hdx_cap:1, 1005 param_10fdx_cap:1, 1006 param_10hdx_cap:1, 1007 param_adv_autoneg:1, 1008 param_adv_pause:1, 1009 param_adv_asym_pause:1, 1010 param_adv_1000fdx:1, 1011 param_adv_1000hdx:1, 1012 param_adv_100t4:1, 1013 param_adv_100fdx:1, 1014 param_adv_100hdx:1, 1015 param_adv_10fdx:1, 1016 param_adv_10hdx:1, 1017 param_lp_autoneg:1, 1018 param_lp_pause:1, 1019 param_lp_asym_pause:1, 1020 param_lp_1000fdx:1, 1021 param_lp_1000hdx:1, 1022 param_lp_100t4:1; 1023 1024 uint32_t param_lp_100fdx:1, 1025 param_lp_100hdx:1, 1026 param_lp_10fdx:1, 1027 param_lp_10hdx:1, 1028 param_pad_to_32:28; 1029 1030 } e1000g_t; 1031 1032 1033 /* 1034 * Function prototypes 1035 */ 1036 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node); 1037 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data); 1038 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data); 1039 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 1040 void e1000g_release_dma_resources(struct e1000g *Adapter); 1041 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release); 1042 void e1000g_tx_setup(struct e1000g *Adapter); 1043 void e1000g_rx_setup(struct e1000g *Adapter); 1044 1045 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 1046 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 1047 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 1048 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1049 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1050 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz); 1051 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1052 1053 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1054 int e1000g_init_stats(struct e1000g *Adapter); 1055 int e1000g_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1056 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1057 uint32_t frame_len, uint8_t *mac_addr); 1058 1059 void e1000g_clear_interrupt(struct e1000g *Adapter); 1060 void e1000g_mask_interrupt(struct e1000g *Adapter); 1061 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1062 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1063 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1064 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1065 void e1000_destroy_hw_mutex(struct e1000_hw *hw); 1066 void e1000_enable_pciex_master(struct e1000_hw *hw); 1067 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1068 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1069 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1070 void e1000g_set_fma_flags(int dma_flag); 1071 int e1000g_reset_link(struct e1000g *Adapter); 1072 1073 /* 1074 * Global variables 1075 */ 1076 extern boolean_t e1000g_force_detach; 1077 extern uint32_t e1000g_mblks_pending; 1078 extern kmutex_t e1000g_rx_detach_lock; 1079 extern private_devi_list_t *e1000g_private_devi_list; 1080 extern int e1000g_poll_mode; 1081 1082 #ifdef __cplusplus 1083 } 1084 #endif 1085 1086 #endif /* _E1000G_SW_H */ 1087