1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * ********************************************************************** 35 * Module Name: * 36 * e1000g_sw.h * 37 * * 38 * Abstract: * 39 * This header file contains Software-related data structures * 40 * definitions. * 41 * * 42 * ********************************************************************** 43 */ 44 45 #include <sys/types.h> 46 #include <sys/conf.h> 47 #include <sys/debug.h> 48 #include <sys/stropts.h> 49 #include <sys/stream.h> 50 #include <sys/strsun.h> 51 #include <sys/strlog.h> 52 #include <sys/kmem.h> 53 #include <sys/stat.h> 54 #include <sys/kstat.h> 55 #include <sys/modctl.h> 56 #include <sys/errno.h> 57 #include <sys/mac.h> 58 #include <sys/mac_ether.h> 59 #include <sys/vlan.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/disp.h> 63 #include <sys/pci.h> 64 #include <sys/sdt.h> 65 #include <sys/ethernet.h> 66 #include <sys/pattr.h> 67 #include <sys/strsubr.h> 68 #include <sys/netlb.h> 69 #include <inet/common.h> 70 #include <inet/ip.h> 71 #include <inet/tcp.h> 72 #include <inet/mi.h> 73 #include <inet/nd.h> 74 #include <sys/ddifm.h> 75 #include <sys/fm/protocol.h> 76 #include <sys/fm/util.h> 77 #include <sys/fm/io/ddi.h> 78 #include "e1000_api.h" 79 80 #define JUMBO_FRAG_LENGTH 4096 81 82 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 83 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 84 #define MAX_NUM_MULTICAST_ADDRESSES 256 85 86 /* 87 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 88 * + one for cross page split 89 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 90 * two for the workaround of the 82546 chip 91 */ 92 #define MAX_COOKIES 18 93 #define MAX_TX_DESC_PER_PACKET 21 94 95 /* 96 * constants used in setting flow control thresholds 97 */ 98 #define E1000_PBA_10K 0x000A 99 #define E1000_PBA_MASK 0xffff 100 #define E1000_PBA_SHIFT 10 101 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 102 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 103 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 104 105 #define MAX_NUM_TX_DESCRIPTOR 4096 106 #define MAX_NUM_RX_DESCRIPTOR 4096 107 #define MAX_NUM_RX_FREELIST 4096 108 #define MAX_NUM_TX_FREELIST 4096 109 #define MAX_RX_LIMIT_ON_INTR 4096 110 #define MAX_RX_INTR_DELAY 65535 111 #define MAX_RX_INTR_ABS_DELAY 65535 112 #define MAX_TX_INTR_DELAY 65535 113 #define MAX_TX_INTR_ABS_DELAY 65535 114 #define MAX_INTR_THROTTLING 65535 115 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 116 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 117 #define MAX_TX_RECYCLE_THRESHOLD MAX_NUM_TX_DESCRIPTOR 118 #define MAX_TX_RECYCLE_NUM MAX_NUM_TX_DESCRIPTOR 119 120 #define MIN_NUM_TX_DESCRIPTOR 80 121 #define MIN_NUM_RX_DESCRIPTOR 80 122 #define MIN_NUM_RX_FREELIST 64 123 #define MIN_NUM_TX_FREELIST 80 124 #define MIN_RX_LIMIT_ON_INTR 16 125 #define MIN_RX_INTR_DELAY 0 126 #define MIN_RX_INTR_ABS_DELAY 0 127 #define MIN_TX_INTR_DELAY 0 128 #define MIN_TX_INTR_ABS_DELAY 0 129 #define MIN_INTR_THROTTLING 0 130 #define MIN_RX_BCOPY_THRESHOLD 0 131 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 132 #define MIN_TX_RECYCLE_THRESHOLD 0 133 #define MIN_TX_RECYCLE_NUM MAX_TX_DESC_PER_PACKET 134 135 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 136 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 137 #define DEFAULT_NUM_RX_FREELIST 4096 138 #define DEFAULT_NUM_TX_FREELIST 2304 139 #define DEFAULT_RX_LIMIT_ON_INTR 128 140 141 #ifdef __sparc 142 #define MAX_INTR_PER_SEC 7100 143 #define MIN_INTR_PER_SEC 3000 144 #define DEFAULT_INTR_PACKET_LOW 5 145 #define DEFAULT_INTR_PACKET_HIGH 128 146 #define DEFAULT_TX_RECYCLE_THRESHOLD 512 147 #else 148 #define MAX_INTR_PER_SEC 15000 149 #define MIN_INTR_PER_SEC 4000 150 #define DEFAULT_INTR_PACKET_LOW 10 151 #define DEFAULT_INTR_PACKET_HIGH 48 152 #define DEFAULT_TX_RECYCLE_THRESHOLD DEFAULT_TX_NO_RESOURCE 153 #endif 154 155 #define DEFAULT_RX_INTR_DELAY 0 156 #define DEFAULT_RX_INTR_ABS_DELAY 64 157 #define DEFAULT_TX_INTR_DELAY 64 158 #define DEFAULT_TX_INTR_ABS_DELAY 64 159 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 160 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 161 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 162 163 #define DEFAULT_RX_BCOPY_THRESHOLD 128 164 #define DEFAULT_TX_BCOPY_THRESHOLD 512 165 #define DEFAULT_TX_RECYCLE_NUM 64 166 #define DEFAULT_TX_UPDATE_THRESHOLD 256 167 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 168 169 #define DEFAULT_TX_INTR_ENABLE 1 170 #define DEFAULT_FLOW_CONTROL 3 171 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 172 /* which is normally 0x040 */ 173 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 174 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 175 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 176 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 177 178 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 179 180 /* 181 * The size of the receive/transmite buffers 182 */ 183 #define E1000_RX_BUFFER_SIZE_2K (2048) 184 #define E1000_RX_BUFFER_SIZE_4K (4096) 185 #define E1000_RX_BUFFER_SIZE_8K (8192) 186 #define E1000_RX_BUFFER_SIZE_16K (16384) 187 188 #define E1000_TX_BUFFER_SIZE_2K (2048) 189 #define E1000_TX_BUFFER_SIZE_4K (4096) 190 #define E1000_TX_BUFFER_SIZE_8K (8192) 191 #define E1000_TX_BUFFER_SIZE_16K (16384) 192 193 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 194 195 #define E1000G_RX_SW_FREE 0x0 196 #define E1000G_RX_SW_SENDUP 0x1 197 #define E1000G_RX_SW_STOP 0x2 198 #define E1000G_RX_SW_DETACH 0x3 199 200 /* 201 * definitions for smartspeed workaround 202 */ 203 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 204 /* or 30 seconds */ 205 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 206 /* or 6 seconds */ 207 208 /* 209 * Definitions for module_info. 210 */ 211 #define WSNAME "e1000g" /* module name */ 212 213 /* 214 * Defined for IP header alignment. We also need to preserve space for 215 * VLAN tag (4 bytes) 216 */ 217 #define E1000G_IPALIGNROOM 6 218 #define E1000G_IPALIGNPRESERVEROOM 64 219 220 /* 221 * bit flags for 'attach_progress' which is a member variable in struct e1000g 222 */ 223 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 224 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 225 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 226 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 227 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 228 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 229 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 230 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 231 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 232 /* 0200 used to be PROGRESS_NDD. Now unused */ 233 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 234 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 235 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 236 237 /* 238 * Speed and Duplex Settings 239 */ 240 #define GDIAG_10_HALF 1 241 #define GDIAG_10_FULL 2 242 #define GDIAG_100_HALF 3 243 #define GDIAG_100_FULL 4 244 #define GDIAG_1000_FULL 6 245 #define GDIAG_ANY 7 246 247 /* 248 * Coexist Workaround RP: 07/04/03 249 * 82544 Workaround : Co-existence 250 */ 251 #define MAX_TX_BUF_SIZE (8 * 1024) 252 253 #define ROUNDOFF 0x1000 254 255 /* 256 * Defines for Jumbo Frame 257 */ 258 #define FRAME_SIZE_UPTO_2K 2048 259 #define FRAME_SIZE_UPTO_4K 4096 260 #define FRAME_SIZE_UPTO_8K 8192 261 #define FRAME_SIZE_UPTO_16K 16384 262 #define FRAME_SIZE_UPTO_9K 9234 263 264 #define MAXIMUM_MTU 9000 265 #define DEFAULT_MTU ETHERMTU 266 267 #define DEFAULT_FRAME_SIZE \ 268 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 269 #define MAXIMUM_FRAME_SIZE \ 270 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 271 272 #define E1000_LSO_MAXLEN 65535 273 274 /* Defines for Tx stall check */ 275 #define E1000G_STALL_WATCHDOG_COUNT 8 276 277 #define MAX_TX_LINK_DOWN_TIMEOUT 8 278 279 /* Defines for DVMA */ 280 #ifdef __sparc 281 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 282 #endif 283 284 /* 285 * Loopback definitions 286 */ 287 #define E1000G_LB_NONE 0 288 #define E1000G_LB_EXTERNAL_1000 1 289 #define E1000G_LB_EXTERNAL_100 2 290 #define E1000G_LB_EXTERNAL_10 3 291 #define E1000G_LB_INTERNAL_PHY 4 292 293 /* 294 * Private dip list definitions 295 */ 296 #define E1000G_PRIV_DEVI_ATTACH 0x0 297 #define E1000G_PRIV_DEVI_DETACH 0x1 298 299 /* 300 * Tx descriptor LENGTH field mask 301 */ 302 #define E1000G_TBD_LENGTH_MASK 0x000fffff 303 304 /* 305 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 306 */ 307 #define QUEUE_INIT_LIST(_LH) \ 308 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 309 310 /* 311 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 312 */ 313 #define IS_QUEUE_EMPTY(_LH) \ 314 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 315 316 /* 317 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 318 * not remove the head from the queue. 319 */ 320 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 321 322 /* 323 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 324 */ 325 #define QUEUE_REMOVE_HEAD(_LH) \ 326 { \ 327 PSINGLE_LIST_LINK ListElem; \ 328 if (ListElem = (_LH)->Flink) \ 329 { \ 330 if (!((_LH)->Flink = ListElem->Flink)) \ 331 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 332 } \ 333 } 334 335 /* 336 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 337 * and return it (this differs from QUEUE_REMOVE_HEAD only in 338 * the 1st line). 339 */ 340 #define QUEUE_POP_HEAD(_LH) \ 341 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 342 { \ 343 PSINGLE_LIST_LINK ListElem; \ 344 ListElem = (_LH)->Flink; \ 345 if (ListElem) \ 346 { \ 347 (_LH)->Flink = ListElem->Flink; \ 348 if (!(_LH)->Flink) \ 349 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 350 } \ 351 } 352 353 /* 354 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 355 * remove the tail from the queue. 356 */ 357 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 358 359 /* 360 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 361 */ 362 #define QUEUE_PUSH_TAIL(_LH, _E) \ 363 if ((_LH)->Blink) \ 364 { \ 365 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 366 (PSINGLE_LIST_LINK)(_E); \ 367 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 368 } else { \ 369 (_LH)->Flink = \ 370 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 371 } \ 372 (_E)->Flink = (PSINGLE_LIST_LINK)0; 373 374 /* 375 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 376 */ 377 #define QUEUE_PUSH_HEAD(_LH, _E) \ 378 if (!((_E)->Flink = (_LH)->Flink)) \ 379 { \ 380 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 381 } \ 382 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 383 384 /* 385 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 386 * current element. 387 */ 388 #define QUEUE_GET_NEXT(_LH, _E) \ 389 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 390 (0) : ((_E)->Flink)) 391 392 /* 393 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 394 */ 395 #define QUEUE_APPEND(_LH1, _LH2) \ 396 if ((_LH2)->Flink) { \ 397 if ((_LH1)->Flink) { \ 398 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 399 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 400 } else { \ 401 (_LH1)->Flink = \ 402 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 403 } \ 404 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 405 } 406 407 /* 408 * Property lookups 409 */ 410 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 411 DDI_PROP_DONTPASS, (n)) 412 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 413 DDI_PROP_DONTPASS, (n), -1) 414 415 #ifdef E1000G_DEBUG 416 /* 417 * E1000G-specific ioctls ... 418 */ 419 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 420 + 'K') << 4) + 'G') << 4) 421 422 /* 423 * These diagnostic IOCTLS are enabled only in DEBUG drivers 424 */ 425 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 426 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 427 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 428 429 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 430 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 431 432 typedef struct { 433 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 434 uint64_t pp_acc_space; /* See #defines below */ 435 uint64_t pp_acc_offset; /* See regs definition */ 436 uint64_t pp_acc_data; /* output for peek */ 437 /* input for poke */ 438 } e1000g_peekpoke_t; 439 #endif /* E1000G_DEBUG */ 440 441 /* 442 * (Internal) return values from ioctl subroutines 443 */ 444 enum ioc_reply { 445 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 446 IOC_DONE, /* OK, reply sent */ 447 IOC_ACK, /* OK, just send ACK */ 448 IOC_REPLY /* OK, just send reply */ 449 }; 450 451 /* 452 * Named Data (ND) Parameter Management Structure 453 */ 454 typedef struct { 455 uint32_t ndp_info; 456 uint32_t ndp_min; 457 uint32_t ndp_max; 458 uint32_t ndp_val; 459 struct e1000g *ndp_instance; 460 char *ndp_name; 461 } nd_param_t; 462 463 /* 464 * The entry of the private dip list 465 */ 466 typedef struct _private_devi_list { 467 dev_info_t *priv_dip; 468 uint16_t flag; 469 struct _private_devi_list *next; 470 } private_devi_list_t; 471 472 /* 473 * A structure that points to the next entry in the queue. 474 */ 475 typedef struct _SINGLE_LIST_LINK { 476 struct _SINGLE_LIST_LINK *Flink; 477 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 478 479 /* 480 * A "ListHead" structure that points to the head and tail of a queue 481 */ 482 typedef struct _LIST_DESCRIBER { 483 struct _SINGLE_LIST_LINK *volatile Flink; 484 struct _SINGLE_LIST_LINK *volatile Blink; 485 } LIST_DESCRIBER, *PLIST_DESCRIBER; 486 487 /* 488 * Address-Length pair structure that stores descriptor info 489 */ 490 typedef struct _sw_desc { 491 uint64_t address; 492 uint32_t length; 493 } sw_desc_t, *p_sw_desc_t; 494 495 typedef struct _desc_array { 496 sw_desc_t descriptor[4]; 497 uint32_t elements; 498 } desc_array_t, *p_desc_array_t; 499 500 typedef enum { 501 USE_NONE, 502 USE_BCOPY, 503 USE_DVMA, 504 USE_DMA 505 } dma_type_t; 506 507 typedef enum { 508 E1000G_STOP, 509 E1000G_START, 510 E1000G_ERROR 511 } chip_state_t; 512 513 typedef struct _dma_buffer { 514 caddr_t address; 515 uint64_t dma_address; 516 ddi_acc_handle_t acc_handle; 517 ddi_dma_handle_t dma_handle; 518 size_t size; 519 size_t len; 520 } dma_buffer_t, *p_dma_buffer_t; 521 522 /* 523 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 524 * structure stores the additional information that is 525 * associated with every packet to be transmitted. It stores the 526 * message block pointer and the TBD addresses associated with 527 * the m_blk and also the link to the next tcb in the chain 528 */ 529 typedef struct _tx_sw_packet { 530 /* Link to the next tx_sw_packet in the list */ 531 SINGLE_LIST_LINK Link; 532 mblk_t *mp; 533 uint32_t num_desc; 534 uint32_t num_mblk_frag; 535 dma_type_t dma_type; 536 dma_type_t data_transfer_type; 537 ddi_dma_handle_t tx_dma_handle; 538 dma_buffer_t tx_buf[1]; 539 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 540 } tx_sw_packet_t, *p_tx_sw_packet_t; 541 542 /* 543 * This structure is similar to the rx_sw_packet structure used 544 * for Ndis. This structure stores information about the 2k 545 * aligned receive buffer into which the FX1000 DMA's frames. 546 * This structure is maintained as a linked list of many 547 * receiver buffer pointers. 548 */ 549 typedef struct _rx_sw_packet { 550 /* Link to the next rx_sw_packet_t in the list */ 551 SINGLE_LIST_LINK Link; 552 struct _rx_sw_packet *next; 553 uint16_t flag; 554 mblk_t *mp; 555 caddr_t rx_ring; 556 dma_type_t dma_type; 557 frtn_t free_rtn; 558 dma_buffer_t rx_buf[1]; 559 } rx_sw_packet_t, *p_rx_sw_packet_t; 560 561 typedef struct _mblk_list { 562 mblk_t *head; 563 mblk_t *tail; 564 } mblk_list_t, *p_mblk_list_t; 565 566 typedef struct _context_data { 567 uint32_t ether_header_size; 568 uint32_t cksum_flags; 569 uint32_t cksum_start; 570 uint32_t cksum_stuff; 571 uint16_t mss; 572 uint8_t hdr_len; 573 uint32_t pay_len; 574 boolean_t lso_flag; 575 } context_data_t; 576 577 typedef union _e1000g_ether_addr { 578 struct { 579 uint32_t high; 580 uint32_t low; 581 } reg; 582 struct { 583 uint8_t set; 584 uint8_t redundant; 585 uint8_t addr[ETHERADDRL]; 586 } mac; 587 } e1000g_ether_addr_t; 588 589 typedef struct _e1000g_stat { 590 591 kstat_named_t link_speed; /* Link Speed */ 592 kstat_named_t reset_count; /* Reset Count */ 593 594 kstat_named_t rx_error; /* Rx Error in Packet */ 595 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 596 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 597 598 kstat_named_t tx_no_desc; /* Tx No Desc */ 599 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 600 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 601 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 602 kstat_named_t tx_reschedule; /* Tx Reschedule */ 603 604 #ifdef E1000G_DEBUG 605 kstat_named_t rx_none; /* Rx No Incoming Data */ 606 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 607 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 608 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 609 610 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 611 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 612 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 613 kstat_named_t tx_recycle; /* Tx Recycle */ 614 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 615 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 616 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 617 kstat_named_t tx_copy; /* Tx Send Copy */ 618 kstat_named_t tx_bind; /* Tx Send Bind */ 619 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 620 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 621 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 622 #endif 623 624 kstat_named_t Crcerrs; /* CRC Error Count */ 625 kstat_named_t Symerrs; /* Symbol Error Count */ 626 kstat_named_t Mpc; /* Missed Packet Count */ 627 kstat_named_t Scc; /* Single Collision Count */ 628 kstat_named_t Ecol; /* Excessive Collision Count */ 629 kstat_named_t Mcc; /* Multiple Collision Count */ 630 kstat_named_t Latecol; /* Late Collision Count */ 631 kstat_named_t Colc; /* Collision Count */ 632 kstat_named_t Dc; /* Defer Count */ 633 kstat_named_t Sec; /* Sequence Error Count */ 634 kstat_named_t Rlec; /* Receive Length Error Count */ 635 kstat_named_t Xonrxc; /* XON Received Count */ 636 kstat_named_t Xontxc; /* XON Xmitted Count */ 637 kstat_named_t Xoffrxc; /* XOFF Received Count */ 638 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 639 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 640 #ifdef E1000G_DEBUG 641 kstat_named_t Prc64; /* Packets Received - 64b */ 642 kstat_named_t Prc127; /* Packets Received - 65-127b */ 643 kstat_named_t Prc255; /* Packets Received - 127-255b */ 644 kstat_named_t Prc511; /* Packets Received - 256-511b */ 645 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 646 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 647 #endif 648 kstat_named_t Gprc; /* Good Packets Received Count */ 649 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 650 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 651 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 652 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 653 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 654 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 655 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 656 kstat_named_t Rnbc; /* Receive No Buffers Count */ 657 kstat_named_t Ruc; /* Receive Undersize Count */ 658 kstat_named_t Rfc; /* Receive Frag Count */ 659 kstat_named_t Roc; /* Receive Oversize Count */ 660 kstat_named_t Rjc; /* Receive Jabber Count */ 661 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 662 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 663 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 664 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 665 kstat_named_t Tpr; /* Total Packets Received */ 666 kstat_named_t Tpt; /* Total Packets Xmitted */ 667 #ifdef E1000G_DEBUG 668 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 669 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 670 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 671 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 672 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 673 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 674 #endif 675 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 676 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 677 kstat_named_t Algnerrc; /* Alignment Error count */ 678 kstat_named_t Tuc; /* Transmit Underrun count */ 679 kstat_named_t Rxerrc; /* Rx Error Count */ 680 kstat_named_t Tncrs; /* Transmit with no CRS */ 681 kstat_named_t Cexterr; /* Carrier Extension Error count */ 682 kstat_named_t Rutec; /* Receive DMA too Early count */ 683 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 684 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 685 } e1000g_stat_t, *p_e1000g_stat_t; 686 687 typedef struct _e1000g_tx_ring { 688 kmutex_t tx_lock; 689 kmutex_t freelist_lock; 690 kmutex_t usedlist_lock; 691 /* 692 * Descriptor queue definitions 693 */ 694 ddi_dma_handle_t tbd_dma_handle; 695 ddi_acc_handle_t tbd_acc_handle; 696 struct e1000_tx_desc *tbd_area; 697 uint64_t tbd_dma_addr; 698 struct e1000_tx_desc *tbd_first; 699 struct e1000_tx_desc *tbd_last; 700 struct e1000_tx_desc *tbd_oldest; 701 struct e1000_tx_desc *tbd_next; 702 uint32_t tbd_avail; 703 /* 704 * Software packet structures definitions 705 */ 706 p_tx_sw_packet_t packet_area; 707 LIST_DESCRIBER used_list; 708 LIST_DESCRIBER free_list; 709 /* 710 * TCP/UDP Context Data Information 711 */ 712 context_data_t pre_context; 713 /* 714 * Timer definitions for 82547 715 */ 716 timeout_id_t timer_id_82547; 717 boolean_t timer_enable_82547; 718 /* 719 * reschedule when tx resource is available 720 */ 721 boolean_t resched_needed; 722 uint32_t stall_watchdog; 723 uint32_t recycle_fail; 724 mblk_list_t mblks; 725 /* 726 * Statistics 727 */ 728 uint32_t stat_no_swpkt; 729 uint32_t stat_no_desc; 730 uint32_t stat_send_fail; 731 uint32_t stat_reschedule; 732 uint32_t stat_over_size; 733 #ifdef E1000G_DEBUG 734 uint32_t stat_under_size; 735 uint32_t stat_exceed_frags; 736 uint32_t stat_empty_frags; 737 uint32_t stat_recycle; 738 uint32_t stat_recycle_intr; 739 uint32_t stat_recycle_retry; 740 uint32_t stat_recycle_none; 741 uint32_t stat_copy; 742 uint32_t stat_bind; 743 uint32_t stat_multi_copy; 744 uint32_t stat_multi_cookie; 745 uint32_t stat_lack_desc; 746 uint32_t stat_lso_header_fail; 747 #endif 748 /* 749 * Pointer to the adapter 750 */ 751 struct e1000g *adapter; 752 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 753 754 typedef struct _e1000g_rx_ring { 755 kmutex_t rx_lock; 756 kmutex_t freelist_lock; 757 /* 758 * Descriptor queue definitions 759 */ 760 ddi_dma_handle_t rbd_dma_handle; 761 ddi_acc_handle_t rbd_acc_handle; 762 struct e1000_rx_desc *rbd_area; 763 uint64_t rbd_dma_addr; 764 struct e1000_rx_desc *rbd_first; 765 struct e1000_rx_desc *rbd_last; 766 struct e1000_rx_desc *rbd_next; 767 /* 768 * Software packet structures definitions 769 */ 770 p_rx_sw_packet_t packet_area; 771 LIST_DESCRIBER recv_list; 772 LIST_DESCRIBER free_list; 773 774 p_rx_sw_packet_t pending_list; 775 uint32_t pending_count; 776 uint32_t avail_freepkt; 777 uint32_t rx_mblk_len; 778 mblk_t *rx_mblk; 779 mblk_t *rx_mblk_tail; 780 /* 781 * Statistics 782 */ 783 uint32_t stat_error; 784 uint32_t stat_esballoc_fail; 785 uint32_t stat_allocb_fail; 786 uint32_t stat_exceed_pkt; 787 #ifdef E1000G_DEBUG 788 uint32_t stat_none; 789 uint32_t stat_multi_desc; 790 uint32_t stat_no_freepkt; 791 #endif 792 /* 793 * Pointer to the adapter 794 */ 795 struct e1000g *adapter; 796 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 797 798 typedef struct e1000g { 799 int instance; 800 dev_info_t *dip; 801 dev_info_t *priv_dip; 802 mac_handle_t mh; 803 mac_resource_handle_t mrh; 804 struct e1000_hw shared; 805 struct e1000g_osdep osdep; 806 807 chip_state_t chip_state; 808 boolean_t e1000g_promisc; 809 boolean_t strip_crc; 810 boolean_t rx_buffer_setup; 811 boolean_t esb2_workaround; 812 link_state_t link_state; 813 uint32_t link_speed; 814 uint32_t link_duplex; 815 uint32_t master_latency_timer; 816 uint32_t smartspeed; /* smartspeed w/a counter */ 817 uint32_t init_count; 818 uint32_t reset_count; 819 uint32_t attach_progress; /* attach tracking */ 820 uint32_t loopback_mode; 821 822 uint32_t tx_desc_num; 823 uint32_t tx_freelist_num; 824 uint32_t rx_desc_num; 825 uint32_t rx_freelist_num; 826 uint32_t tx_buffer_size; 827 uint32_t rx_buffer_size; 828 829 uint32_t tx_link_down_timeout; 830 uint32_t tx_bcopy_thresh; 831 uint32_t rx_limit_onintr; 832 uint32_t rx_bcopy_thresh; 833 uint32_t rx_buf_align; 834 835 boolean_t intr_adaptive; 836 boolean_t tx_intr_enable; 837 uint32_t tx_recycle_thresh; 838 uint32_t tx_recycle_num; 839 uint32_t tx_intr_delay; 840 uint32_t tx_intr_abs_delay; 841 uint32_t rx_intr_delay; 842 uint32_t rx_intr_abs_delay; 843 uint32_t intr_throttling_rate; 844 845 uint32_t default_mtu; 846 uint32_t max_frame_size; 847 uint32_t min_frame_size; 848 849 boolean_t watchdog_timer_enabled; 850 boolean_t watchdog_timer_started; 851 timeout_id_t watchdog_tid; 852 boolean_t link_complete; 853 timeout_id_t link_tid; 854 855 e1000g_rx_ring_t rx_ring[1]; 856 e1000g_tx_ring_t tx_ring[1]; 857 858 /* 859 * Rx and Tx packet count for interrupt adaptive setting 860 */ 861 uint32_t rx_pkt_cnt; 862 uint32_t tx_pkt_cnt; 863 864 /* 865 * The watchdog_lock must be held when updateing the 866 * timeout fields in struct e1000g, that is, 867 * watchdog_tid, watchdog_timer_started. 868 */ 869 kmutex_t watchdog_lock; 870 /* 871 * The link_lock protects the link fields in struct e1000g, 872 * such as link_state, link_speed, link_duplex, link_complete, and 873 * link_tid. 874 */ 875 kmutex_t link_lock; 876 /* 877 * The chip_lock assures that the Rx/Tx process must be 878 * stopped while other functions change the hardware 879 * configuration of e1000g card, such as e1000g_reset(), 880 * e1000g_reset_hw() etc are executed. 881 */ 882 krwlock_t chip_lock; 883 884 boolean_t unicst_init; 885 uint32_t unicst_avail; 886 uint32_t unicst_total; 887 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 888 889 uint32_t mcast_count; 890 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 891 892 ulong_t sys_page_sz; 893 #ifdef __sparc 894 uint_t dvma_page_num; 895 #endif 896 897 boolean_t msi_enable; 898 boolean_t tx_hcksum_enable; 899 boolean_t lso_enable; 900 boolean_t lso_premature_issue; 901 int intr_type; 902 int intr_cnt; 903 int intr_cap; 904 size_t intr_size; 905 uint_t intr_pri; 906 ddi_intr_handle_t *htable; 907 908 int tx_softint_pri; 909 ddi_softint_handle_t tx_softint_handle; 910 911 kstat_t *e1000g_ksp; 912 913 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 914 uint16_t phy_status; /* contents of PHY_STATUS */ 915 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 916 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 917 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 918 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 919 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 920 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 921 922 /* 923 * FMA capabilities 924 */ 925 int fm_capabilities; 926 927 uint32_t param_en_1000fdx:1, 928 param_en_1000hdx:1, 929 param_en_100fdx:1, 930 param_en_100hdx:1, 931 param_en_10fdx:1, 932 param_en_10hdx:1, 933 param_autoneg_cap:1, 934 param_pause_cap:1, 935 param_asym_pause_cap:1, 936 param_1000fdx_cap:1, 937 param_1000hdx_cap:1, 938 param_100t4_cap:1, 939 param_100fdx_cap:1, 940 param_100hdx_cap:1, 941 param_10fdx_cap:1, 942 param_10hdx_cap:1, 943 param_adv_autoneg:1, 944 param_adv_pause:1, 945 param_adv_asym_pause:1, 946 param_adv_1000fdx:1, 947 param_adv_1000hdx:1, 948 param_adv_100t4:1, 949 param_adv_100fdx:1, 950 param_adv_100hdx:1, 951 param_adv_10fdx:1, 952 param_adv_10hdx:1, 953 param_lp_autoneg:1, 954 param_lp_pause:1, 955 param_lp_asym_pause:1, 956 param_lp_1000fdx:1, 957 param_lp_1000hdx:1, 958 param_lp_100t4:1; 959 960 uint32_t param_lp_100fdx:1, 961 param_lp_100hdx:1, 962 param_lp_10fdx:1, 963 param_lp_10hdx:1, 964 param_pad_to_32:28; 965 966 } e1000g_t; 967 968 969 /* 970 * Function prototypes 971 */ 972 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 973 void e1000g_release_dma_resources(struct e1000g *Adapter); 974 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 975 void e1000g_tx_setup(struct e1000g *Adapter); 976 void e1000g_rx_setup(struct e1000g *Adapter); 977 void e1000g_setup_multicast(struct e1000g *Adapter); 978 979 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 980 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 981 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 982 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 983 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 984 mblk_t *e1000g_receive(struct e1000g *Adapter); 985 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 986 987 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 988 int e1000g_init_stats(struct e1000g *Adapter); 989 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 990 uint32_t frame_len, uint8_t *mac_addr); 991 992 void e1000g_clear_interrupt(struct e1000g *Adapter); 993 void e1000g_mask_interrupt(struct e1000g *Adapter); 994 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 995 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 996 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 997 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 998 void e1000_enable_pciex_master(struct e1000_hw *hw); 999 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1000 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1001 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1002 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 1003 int e1000g_reset_link(struct e1000g *Adapter); 1004 1005 /* 1006 * Global variables 1007 */ 1008 extern boolean_t e1000g_force_detach; 1009 extern uint32_t e1000g_mblks_pending; 1010 extern krwlock_t e1000g_rx_detach_lock; 1011 extern private_devi_list_t *e1000g_private_devi_list; 1012 1013 #ifdef __cplusplus 1014 } 1015 #endif 1016 1017 #endif /* _E1000G_SW_H */ 1018