1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #ifndef _E1000G_SW_H 27 #define _E1000G_SW_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * ********************************************************************** 37 * Module Name: * 38 * e1000g_sw.h * 39 * * 40 * Abstract: * 41 * This header file contains Software-related data structures * 42 * definitions. * 43 * * 44 * ********************************************************************** 45 */ 46 47 #include <sys/types.h> 48 #include <sys/conf.h> 49 #include <sys/debug.h> 50 #include <sys/stropts.h> 51 #include <sys/stream.h> 52 #include <sys/strsun.h> 53 #include <sys/strlog.h> 54 #include <sys/kmem.h> 55 #include <sys/stat.h> 56 #include <sys/kstat.h> 57 #include <sys/modctl.h> 58 #include <sys/errno.h> 59 #include <sys/mac.h> 60 #include <sys/mac_ether.h> 61 #include <sys/vlan.h> 62 #include <sys/ddi.h> 63 #include <sys/sunddi.h> 64 #include <sys/disp.h> 65 #include <sys/pci.h> 66 #include <sys/sdt.h> 67 #include <sys/ethernet.h> 68 #include <sys/pattr.h> 69 #include <sys/strsubr.h> 70 #include <sys/netlb.h> 71 #include <inet/common.h> 72 #include <inet/ip.h> 73 #include <inet/mi.h> 74 #include <inet/nd.h> 75 #include <sys/ddifm.h> 76 #include <sys/fm/protocol.h> 77 #include <sys/fm/util.h> 78 #include <sys/fm/io/ddi.h> 79 #include "e1000_api.h" 80 81 82 #define JUMBO_FRAG_LENGTH 4096 83 84 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 85 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 86 #define MAX_NUM_MULTICAST_ADDRESSES 256 87 88 #define MAX_TX_DESC_PER_PACKET 16 89 90 /* 91 * constants used in setting flow control thresholds 92 */ 93 #define E1000_PBA_MASK 0xffff 94 #define E1000_PBA_SHIFT 10 95 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 96 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 97 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 98 99 #define MAX_NUM_TX_DESCRIPTOR 4096 100 #define MAX_NUM_RX_DESCRIPTOR 4096 101 #define MAX_NUM_RX_FREELIST 4096 102 #define MAX_NUM_TX_FREELIST 4096 103 #define MAX_RX_LIMIT_ON_INTR 4096 104 #define MAX_RX_INTR_DELAY 65535 105 #define MAX_RX_INTR_ABS_DELAY 65535 106 #define MAX_TX_INTR_DELAY 65535 107 #define MAX_TX_INTR_ABS_DELAY 65535 108 #define MAX_INTR_THROTTLING 65535 109 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 110 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 111 #define MAX_TX_RECYCLE_THRESHOLD MAX_NUM_TX_DESCRIPTOR 112 #define MAX_TX_RECYCLE_NUM MAX_NUM_TX_DESCRIPTOR 113 114 #define MIN_NUM_TX_DESCRIPTOR 80 115 #define MIN_NUM_RX_DESCRIPTOR 80 116 #define MIN_NUM_RX_FREELIST 64 117 #define MIN_NUM_TX_FREELIST 80 118 #define MIN_RX_LIMIT_ON_INTR 16 119 #define MIN_RX_INTR_DELAY 0 120 #define MIN_RX_INTR_ABS_DELAY 0 121 #define MIN_TX_INTR_DELAY 0 122 #define MIN_TX_INTR_ABS_DELAY 0 123 #define MIN_INTR_THROTTLING 0 124 #define MIN_RX_BCOPY_THRESHOLD 0 125 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 126 #define MIN_TX_RECYCLE_THRESHOLD 0 127 #define MIN_TX_RECYCLE_NUM MAX_TX_DESC_PER_PACKET 128 129 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 130 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 131 #define DEFAULT_NUM_RX_FREELIST 4096 132 #define DEFAULT_NUM_TX_FREELIST 2304 133 #define DEFAULT_RX_LIMIT_ON_INTR 128 134 135 #ifdef __sparc 136 #define MAX_INTR_PER_SEC 7100 137 #define MIN_INTR_PER_SEC 3000 138 #define DEFAULT_INTR_PACKET_LOW 5 139 #define DEFAULT_INTR_PACKET_HIGH 128 140 #define DEFAULT_TX_RECYCLE_THRESHOLD 512 141 #else 142 #define MAX_INTR_PER_SEC 15000 143 #define MIN_INTR_PER_SEC 4000 144 #define DEFAULT_INTR_PACKET_LOW 10 145 #define DEFAULT_INTR_PACKET_HIGH 48 146 #define DEFAULT_TX_RECYCLE_THRESHOLD DEFAULT_TX_NO_RESOURCE 147 #endif 148 149 #define DEFAULT_RX_INTR_DELAY 0 150 #define DEFAULT_RX_INTR_ABS_DELAY 64 151 #define DEFAULT_TX_INTR_DELAY 64 152 #define DEFAULT_TX_INTR_ABS_DELAY 64 153 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 154 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 155 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 156 157 #define DEFAULT_RX_BCOPY_THRESHOLD 128 158 #define DEFAULT_TX_BCOPY_THRESHOLD 512 159 #define DEFAULT_TX_RECYCLE_NUM 64 160 #define DEFAULT_TX_UPDATE_THRESHOLD 256 161 #define DEFAULT_TX_NO_RESOURCE 6 162 163 #define DEFAULT_TX_INTR_ENABLE 1 164 #define DEFAULT_FLOW_CONTROL 3 165 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 166 /* which is normally 0x040 */ 167 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 168 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 169 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 170 171 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 172 173 /* 174 * The size of the receive/transmite buffers 175 */ 176 #define E1000_RX_BUFFER_SIZE_2K (2048) 177 #define E1000_RX_BUFFER_SIZE_4K (4096) 178 #define E1000_RX_BUFFER_SIZE_8K (8192) 179 #define E1000_RX_BUFFER_SIZE_16K (16384) 180 181 #define E1000_TX_BUFFER_SIZE_2K (2048) 182 #define E1000_TX_BUFFER_SIZE_4K (4096) 183 #define E1000_TX_BUFFER_SIZE_8K (8192) 184 #define E1000_TX_BUFFER_SIZE_16K (16384) 185 186 #define FORCE_BCOPY_EXCEED_FRAGS 0x1 187 #define FORCE_BCOPY_UNDER_SIZE 0x2 188 189 #define E1000G_RX_SW_FREE 0x0 190 #define E1000G_RX_SW_SENDUP 0x1 191 #define E1000G_RX_SW_STOP 0x2 192 #define E1000G_RX_SW_DETACH 0x3 193 194 /* 195 * definitions for smartspeed workaround 196 */ 197 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 198 /* or 30 seconds */ 199 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 200 /* or 6 seconds */ 201 202 /* 203 * Definitions for module_info. 204 */ 205 #define WSNAME "e1000g" /* module name */ 206 207 /* 208 * Defined for IP header alignment. We also need to preserve space for 209 * VLAN tag (4 bytes) 210 */ 211 #define E1000G_IPALIGNROOM 6 212 #define E1000G_IPALIGNPRESERVEROOM 64 213 214 /* 215 * bit flags for 'attach_progress' which is a member variable in struct e1000g 216 */ 217 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 218 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 219 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 220 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 221 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 222 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 223 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 224 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 225 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 226 /* 0200 used to be PROGRESS_NDD. Now unused */ 227 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 228 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 229 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 230 231 /* 232 * Speed and Duplex Settings 233 */ 234 #define GDIAG_10_HALF 1 235 #define GDIAG_10_FULL 2 236 #define GDIAG_100_HALF 3 237 #define GDIAG_100_FULL 4 238 #define GDIAG_1000_FULL 6 239 #define GDIAG_ANY 7 240 241 /* 242 * Coexist Workaround RP: 07/04/03 243 * 82544 Workaround : Co-existence 244 */ 245 #define MAX_TX_BUF_SIZE (8 * 1024) 246 247 #define ROUNDOFF 0x1000 248 249 /* 250 * Defines for Jumbo Frame 251 */ 252 #define FRAME_SIZE_UPTO_2K 2048 253 #define FRAME_SIZE_UPTO_4K 4096 254 #define FRAME_SIZE_UPTO_8K 8192 255 #define FRAME_SIZE_UPTO_16K 16384 256 #define FRAME_SIZE_UPTO_9K 9234 257 258 #define MAXIMUM_MTU 9000 259 #define DEFAULT_MTU ETHERMTU 260 261 #define DEFAULT_FRAME_SIZE \ 262 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 263 #define MAXIMUM_FRAME_SIZE \ 264 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 265 266 /* Defines for Tx stall check */ 267 #define E1000G_STALL_WATCHDOG_COUNT 8 268 269 #define MAX_TX_LINK_DOWN_TIMEOUT 8 270 271 /* Defines for DVMA */ 272 #ifdef __sparc 273 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 274 #endif 275 276 /* 277 * Loopback definitions 278 */ 279 #define E1000G_LB_NONE 0 280 #define E1000G_LB_EXTERNAL_1000 1 281 #define E1000G_LB_EXTERNAL_100 2 282 #define E1000G_LB_EXTERNAL_10 3 283 #define E1000G_LB_INTERNAL_PHY 4 284 285 /* 286 * Private dip list definitions 287 */ 288 #define E1000G_PRIV_DEVI_ATTACH 0x0 289 #define E1000G_PRIV_DEVI_DETACH 0x1 290 291 /* 292 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 293 */ 294 #define QUEUE_INIT_LIST(_LH) \ 295 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 296 297 /* 298 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 299 */ 300 #define IS_QUEUE_EMPTY(_LH) \ 301 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 302 303 /* 304 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 305 * not remove the head from the queue. 306 */ 307 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 308 309 /* 310 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 311 */ 312 #define QUEUE_REMOVE_HEAD(_LH) \ 313 { \ 314 PSINGLE_LIST_LINK ListElem; \ 315 if (ListElem = (_LH)->Flink) \ 316 { \ 317 if (!((_LH)->Flink = ListElem->Flink)) \ 318 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 319 } \ 320 } 321 322 /* 323 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 324 * and return it (this differs from QUEUE_REMOVE_HEAD only in 325 * the 1st line). 326 */ 327 #define QUEUE_POP_HEAD(_LH) \ 328 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 329 { \ 330 PSINGLE_LIST_LINK ListElem; \ 331 ListElem = (_LH)->Flink; \ 332 if (ListElem) \ 333 { \ 334 (_LH)->Flink = ListElem->Flink; \ 335 if (!(_LH)->Flink) \ 336 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 337 } \ 338 } 339 340 /* 341 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 342 * remove the tail from the queue. 343 */ 344 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 345 346 /* 347 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 348 */ 349 #define QUEUE_PUSH_TAIL(_LH, _E) \ 350 if ((_LH)->Blink) \ 351 { \ 352 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 353 (PSINGLE_LIST_LINK)(_E); \ 354 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 355 } else { \ 356 (_LH)->Flink = \ 357 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 358 } \ 359 (_E)->Flink = (PSINGLE_LIST_LINK)0; 360 361 /* 362 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 363 */ 364 #define QUEUE_PUSH_HEAD(_LH, _E) \ 365 if (!((_E)->Flink = (_LH)->Flink)) \ 366 { \ 367 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 368 } \ 369 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 370 371 /* 372 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 373 * current element. 374 */ 375 #define QUEUE_GET_NEXT(_LH, _E) \ 376 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 377 (0) : ((_E)->Flink)) 378 379 /* 380 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 381 */ 382 #define QUEUE_APPEND(_LH1, _LH2) \ 383 if ((_LH2)->Flink) { \ 384 if ((_LH1)->Flink) { \ 385 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 386 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 387 } else { \ 388 (_LH1)->Flink = \ 389 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 390 } \ 391 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 392 } 393 394 /* 395 * Property lookups 396 */ 397 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 398 DDI_PROP_DONTPASS, (n)) 399 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 400 DDI_PROP_DONTPASS, (n), -1) 401 402 #ifdef E1000G_DEBUG 403 /* 404 * E1000G-specific ioctls ... 405 */ 406 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 407 + 'K') << 4) + 'G') << 4) 408 409 /* 410 * These diagnostic IOCTLS are enabled only in DEBUG drivers 411 */ 412 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 413 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 414 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 415 416 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 417 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 418 419 typedef struct { 420 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 421 uint64_t pp_acc_space; /* See #defines below */ 422 uint64_t pp_acc_offset; /* See regs definition */ 423 uint64_t pp_acc_data; /* output for peek */ 424 /* input for poke */ 425 } e1000g_peekpoke_t; 426 #endif /* E1000G_DEBUG */ 427 428 /* 429 * (Internal) return values from ioctl subroutines 430 */ 431 enum ioc_reply { 432 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 433 IOC_DONE, /* OK, reply sent */ 434 IOC_ACK, /* OK, just send ACK */ 435 IOC_REPLY /* OK, just send reply */ 436 }; 437 438 /* 439 * Named Data (ND) Parameter Management Structure 440 */ 441 typedef struct { 442 uint32_t ndp_info; 443 uint32_t ndp_min; 444 uint32_t ndp_max; 445 uint32_t ndp_val; 446 struct e1000g *ndp_instance; 447 char *ndp_name; 448 } nd_param_t; 449 450 /* 451 * The entry of the private dip list 452 */ 453 typedef struct _private_devi_list { 454 dev_info_t *priv_dip; 455 uint16_t flag; 456 struct _private_devi_list *next; 457 } private_devi_list_t; 458 459 /* 460 * A structure that points to the next entry in the queue. 461 */ 462 typedef struct _SINGLE_LIST_LINK { 463 struct _SINGLE_LIST_LINK *Flink; 464 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 465 466 /* 467 * A "ListHead" structure that points to the head and tail of a queue 468 */ 469 typedef struct _LIST_DESCRIBER { 470 struct _SINGLE_LIST_LINK *volatile Flink; 471 struct _SINGLE_LIST_LINK *volatile Blink; 472 } LIST_DESCRIBER, *PLIST_DESCRIBER; 473 474 /* 475 * Address-Length pair structure that stores descriptor info 476 */ 477 typedef struct _sw_desc { 478 uint64_t address; 479 uint32_t length; 480 } sw_desc_t, *p_sw_desc_t; 481 482 typedef struct _desc_array { 483 sw_desc_t descriptor[4]; 484 uint32_t elements; 485 } desc_array_t, *p_desc_array_t; 486 487 typedef enum { 488 USE_NONE, 489 USE_BCOPY, 490 USE_DVMA, 491 USE_DMA 492 } dma_type_t; 493 494 typedef enum { 495 E1000G_STOP, 496 E1000G_START, 497 E1000G_ERROR 498 } chip_state_t; 499 500 typedef struct _dma_buffer { 501 caddr_t address; 502 uint64_t dma_address; 503 ddi_acc_handle_t acc_handle; 504 ddi_dma_handle_t dma_handle; 505 size_t size; 506 size_t len; 507 } dma_buffer_t, *p_dma_buffer_t; 508 509 /* 510 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 511 * structure stores the additional information that is 512 * associated with every packet to be transmitted. It stores the 513 * message block pointer and the TBD addresses associated with 514 * the m_blk and also the link to the next tcb in the chain 515 */ 516 typedef struct _tx_sw_packet { 517 /* Link to the next tx_sw_packet in the list */ 518 SINGLE_LIST_LINK Link; 519 mblk_t *mp; 520 uint32_t num_desc; 521 uint32_t num_mblk_frag; 522 dma_type_t dma_type; 523 dma_type_t data_transfer_type; 524 ddi_dma_handle_t tx_dma_handle; 525 dma_buffer_t tx_buf[1]; 526 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 527 } tx_sw_packet_t, *p_tx_sw_packet_t; 528 529 /* 530 * This structure is similar to the rx_sw_packet structure used 531 * for Ndis. This structure stores information about the 2k 532 * aligned receive buffer into which the FX1000 DMA's frames. 533 * This structure is maintained as a linked list of many 534 * receiver buffer pointers. 535 */ 536 typedef struct _rx_sw_packet { 537 /* Link to the next rx_sw_packet_t in the list */ 538 SINGLE_LIST_LINK Link; 539 struct _rx_sw_packet *next; 540 uint16_t flag; 541 mblk_t *mp; 542 caddr_t rx_ring; 543 dma_type_t dma_type; 544 frtn_t free_rtn; 545 dma_buffer_t rx_buf[1]; 546 } rx_sw_packet_t, *p_rx_sw_packet_t; 547 548 typedef struct _mblk_list { 549 mblk_t *head; 550 mblk_t *tail; 551 } mblk_list_t, *p_mblk_list_t; 552 553 typedef struct _cksum_data { 554 uint32_t ether_header_size; 555 uint32_t cksum_flags; 556 uint32_t cksum_start; 557 uint32_t cksum_stuff; 558 } cksum_data_t; 559 560 typedef union _e1000g_ether_addr { 561 struct { 562 uint32_t high; 563 uint32_t low; 564 } reg; 565 struct { 566 uint8_t set; 567 uint8_t redundant; 568 uint8_t addr[ETHERADDRL]; 569 } mac; 570 } e1000g_ether_addr_t; 571 572 typedef struct _e1000g_stat { 573 574 kstat_named_t link_speed; /* Link Speed */ 575 kstat_named_t reset_count; /* Reset Count */ 576 577 kstat_named_t rx_error; /* Rx Error in Packet */ 578 kstat_named_t rx_esballoc_fail; /* Rx Desballoc Failure */ 579 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 580 581 kstat_named_t tx_no_desc; /* Tx No Desc */ 582 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 583 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 584 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 585 kstat_named_t tx_reschedule; /* Tx Reschedule */ 586 587 #ifdef E1000G_DEBUG 588 kstat_named_t rx_none; /* Rx No Incoming Data */ 589 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 590 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 591 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 592 593 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 594 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 595 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 596 kstat_named_t tx_recycle; /* Tx Recycle */ 597 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 598 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 599 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 600 kstat_named_t tx_copy; /* Tx Send Copy */ 601 kstat_named_t tx_bind; /* Tx Send Bind */ 602 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 603 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 604 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 605 #endif 606 607 kstat_named_t Crcerrs; /* CRC Error Count */ 608 kstat_named_t Symerrs; /* Symbol Error Count */ 609 kstat_named_t Mpc; /* Missed Packet Count */ 610 kstat_named_t Scc; /* Single Collision Count */ 611 kstat_named_t Ecol; /* Excessive Collision Count */ 612 kstat_named_t Mcc; /* Multiple Collision Count */ 613 kstat_named_t Latecol; /* Late Collision Count */ 614 kstat_named_t Colc; /* Collision Count */ 615 kstat_named_t Dc; /* Defer Count */ 616 kstat_named_t Sec; /* Sequence Error Count */ 617 kstat_named_t Rlec; /* Receive Length Error Count */ 618 kstat_named_t Xonrxc; /* XON Received Count */ 619 kstat_named_t Xontxc; /* XON Xmitted Count */ 620 kstat_named_t Xoffrxc; /* XOFF Received Count */ 621 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 622 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 623 #ifdef E1000G_DEBUG 624 kstat_named_t Prc64; /* Packets Received - 64b */ 625 kstat_named_t Prc127; /* Packets Received - 65-127b */ 626 kstat_named_t Prc255; /* Packets Received - 127-255b */ 627 kstat_named_t Prc511; /* Packets Received - 256-511b */ 628 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 629 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 630 #endif 631 kstat_named_t Gprc; /* Good Packets Received Count */ 632 kstat_named_t Bprc; /* Broadcasts Pkts Received Count */ 633 kstat_named_t Mprc; /* Multicast Pkts Received Count */ 634 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 635 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 636 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 637 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 638 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 639 kstat_named_t Rnbc; /* Receive No Buffers Count */ 640 kstat_named_t Ruc; /* Receive Undersize Count */ 641 kstat_named_t Rfc; /* Receive Frag Count */ 642 kstat_named_t Roc; /* Receive Oversize Count */ 643 kstat_named_t Rjc; /* Receive Jabber Count */ 644 kstat_named_t Torl; /* Total Octets Recvd Lo Count */ 645 kstat_named_t Torh; /* Total Octets Recvd Hi Count */ 646 kstat_named_t Totl; /* Total Octets Xmted Lo Count */ 647 kstat_named_t Toth; /* Total Octets Xmted Hi Count */ 648 kstat_named_t Tpr; /* Total Packets Received */ 649 kstat_named_t Tpt; /* Total Packets Xmitted */ 650 #ifdef E1000G_DEBUG 651 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 652 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 653 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 654 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 655 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 656 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 657 #endif 658 kstat_named_t Mptc; /* Multicast Packets Xmited Count */ 659 kstat_named_t Bptc; /* Broadcast Packets Xmited Count */ 660 kstat_named_t Algnerrc; /* Alignment Error count */ 661 kstat_named_t Tuc; /* Transmit Underrun count */ 662 kstat_named_t Rxerrc; /* Rx Error Count */ 663 kstat_named_t Tncrs; /* Transmit with no CRS */ 664 kstat_named_t Cexterr; /* Carrier Extension Error count */ 665 kstat_named_t Rutec; /* Receive DMA too Early count */ 666 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 667 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 668 } e1000g_stat_t, *p_e1000g_stat_t; 669 670 typedef struct _e1000g_tx_ring { 671 kmutex_t tx_lock; 672 kmutex_t freelist_lock; 673 kmutex_t usedlist_lock; 674 /* 675 * Descriptor queue definitions 676 */ 677 ddi_dma_handle_t tbd_dma_handle; 678 ddi_acc_handle_t tbd_acc_handle; 679 struct e1000_tx_desc *tbd_area; 680 uint64_t tbd_dma_addr; 681 struct e1000_tx_desc *tbd_first; 682 struct e1000_tx_desc *tbd_last; 683 struct e1000_tx_desc *tbd_oldest; 684 struct e1000_tx_desc *tbd_next; 685 uint32_t tbd_avail; 686 /* 687 * Software packet structures definitions 688 */ 689 p_tx_sw_packet_t packet_area; 690 LIST_DESCRIBER used_list; 691 LIST_DESCRIBER free_list; 692 /* 693 * TCP/UDP checksum offload 694 */ 695 cksum_data_t cksum_data; 696 /* 697 * Timer definitions for 82547 698 */ 699 timeout_id_t timer_id_82547; 700 boolean_t timer_enable_82547; 701 /* 702 * reschedule when tx resource is available 703 */ 704 boolean_t resched_needed; 705 uint32_t frags_limit; 706 uint32_t stall_watchdog; 707 uint32_t recycle_fail; 708 mblk_list_t mblks; 709 /* 710 * Statistics 711 */ 712 uint32_t stat_no_swpkt; 713 uint32_t stat_no_desc; 714 uint32_t stat_send_fail; 715 uint32_t stat_reschedule; 716 uint32_t stat_over_size; 717 #ifdef E1000G_DEBUG 718 uint32_t stat_under_size; 719 uint32_t stat_exceed_frags; 720 uint32_t stat_empty_frags; 721 uint32_t stat_recycle; 722 uint32_t stat_recycle_intr; 723 uint32_t stat_recycle_retry; 724 uint32_t stat_recycle_none; 725 uint32_t stat_copy; 726 uint32_t stat_bind; 727 uint32_t stat_multi_copy; 728 uint32_t stat_multi_cookie; 729 uint32_t stat_lack_desc; 730 #endif 731 /* 732 * Pointer to the adapter 733 */ 734 struct e1000g *adapter; 735 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 736 737 typedef struct _e1000g_rx_ring { 738 kmutex_t rx_lock; 739 kmutex_t freelist_lock; 740 /* 741 * Descriptor queue definitions 742 */ 743 ddi_dma_handle_t rbd_dma_handle; 744 ddi_acc_handle_t rbd_acc_handle; 745 struct e1000_rx_desc *rbd_area; 746 uint64_t rbd_dma_addr; 747 struct e1000_rx_desc *rbd_first; 748 struct e1000_rx_desc *rbd_last; 749 struct e1000_rx_desc *rbd_next; 750 /* 751 * Software packet structures definitions 752 */ 753 p_rx_sw_packet_t packet_area; 754 LIST_DESCRIBER recv_list; 755 LIST_DESCRIBER free_list; 756 757 p_rx_sw_packet_t pending_list; 758 uint32_t pending_count; 759 uint32_t avail_freepkt; 760 uint32_t rx_mblk_len; 761 mblk_t *rx_mblk; 762 mblk_t *rx_mblk_tail; 763 /* 764 * Statistics 765 */ 766 uint32_t stat_error; 767 uint32_t stat_esballoc_fail; 768 uint32_t stat_allocb_fail; 769 uint32_t stat_exceed_pkt; 770 #ifdef E1000G_DEBUG 771 uint32_t stat_none; 772 uint32_t stat_multi_desc; 773 uint32_t stat_no_freepkt; 774 #endif 775 /* 776 * Pointer to the adapter 777 */ 778 struct e1000g *adapter; 779 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 780 781 typedef struct e1000g { 782 int instance; 783 dev_info_t *dip; 784 dev_info_t *priv_dip; 785 mac_handle_t mh; 786 mac_resource_handle_t mrh; 787 struct e1000_hw shared; 788 struct e1000g_osdep osdep; 789 790 chip_state_t chip_state; 791 boolean_t e1000g_promisc; 792 boolean_t strip_crc; 793 boolean_t rx_buffer_setup; 794 link_state_t link_state; 795 uint32_t link_speed; 796 uint32_t link_duplex; 797 uint32_t master_latency_timer; 798 uint32_t smartspeed; /* smartspeed w/a counter */ 799 uint32_t init_count; 800 uint32_t reset_count; 801 uint32_t attach_progress; /* attach tracking */ 802 uint32_t loopback_mode; 803 804 uint32_t tx_desc_num; 805 uint32_t tx_freelist_num; 806 uint32_t rx_desc_num; 807 uint32_t rx_freelist_num; 808 uint32_t tx_buffer_size; 809 uint32_t rx_buffer_size; 810 811 uint32_t tx_link_down_timeout; 812 uint32_t tx_bcopy_thresh; 813 uint32_t rx_limit_onintr; 814 uint32_t rx_bcopy_thresh; 815 uint32_t rx_buf_align; 816 817 boolean_t intr_adaptive; 818 boolean_t tx_intr_enable; 819 uint32_t tx_recycle_thresh; 820 uint32_t tx_recycle_num; 821 uint32_t tx_intr_delay; 822 uint32_t tx_intr_abs_delay; 823 uint32_t rx_intr_delay; 824 uint32_t rx_intr_abs_delay; 825 uint32_t intr_throttling_rate; 826 827 uint32_t default_mtu; 828 uint32_t max_frame_size; 829 uint32_t min_frame_size; 830 831 boolean_t watchdog_timer_enabled; 832 boolean_t watchdog_timer_started; 833 timeout_id_t watchdog_tid; 834 boolean_t link_complete; 835 timeout_id_t link_tid; 836 837 e1000g_rx_ring_t rx_ring[1]; 838 e1000g_tx_ring_t tx_ring[1]; 839 840 /* 841 * Rx and Tx packet count for interrupt adaptive setting 842 */ 843 uint32_t rx_pkt_cnt; 844 uint32_t tx_pkt_cnt; 845 846 /* 847 * The watchdog_lock must be held when updateing the 848 * timeout fields in struct e1000g, that is, 849 * watchdog_tid, watchdog_timer_started. 850 */ 851 kmutex_t watchdog_lock; 852 /* 853 * The link_lock protects the link fields in struct e1000g, 854 * such as link_state, link_speed, link_duplex, link_complete, and 855 * link_tid. 856 */ 857 kmutex_t link_lock; 858 /* 859 * The chip_lock assures that the Rx/Tx process must be 860 * stopped while other functions change the hardware 861 * configuration of e1000g card, such as e1000g_reset(), 862 * e1000g_reset_hw() etc are executed. 863 */ 864 krwlock_t chip_lock; 865 866 boolean_t unicst_init; 867 uint32_t unicst_avail; 868 uint32_t unicst_total; 869 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 870 871 uint32_t mcast_count; 872 struct ether_addr mcast_table[MAX_NUM_MULTICAST_ADDRESSES]; 873 874 #ifdef __sparc 875 ulong_t sys_page_sz; 876 uint_t dvma_page_num; 877 #endif 878 879 boolean_t msi_enabled; 880 boolean_t tx_hcksum_enabled; 881 int intr_type; 882 int intr_cnt; 883 int intr_cap; 884 size_t intr_size; 885 uint_t intr_pri; 886 ddi_intr_handle_t *htable; 887 888 int tx_softint_pri; 889 ddi_softint_handle_t tx_softint_handle; 890 891 kstat_t *e1000g_ksp; 892 893 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 894 uint16_t phy_status; /* contents of PHY_STATUS */ 895 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 896 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 897 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 898 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 899 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 900 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 901 902 /* 903 * FMA capabilities 904 */ 905 int fm_capabilities; 906 907 uint32_t param_en_1000fdx:1, 908 param_en_1000hdx:1, 909 param_en_100fdx:1, 910 param_en_100hdx:1, 911 param_en_10fdx:1, 912 param_en_10hdx:1, 913 param_autoneg_cap:1, 914 param_pause_cap:1, 915 param_asym_pause_cap:1, 916 param_1000fdx_cap:1, 917 param_1000hdx_cap:1, 918 param_100t4_cap:1, 919 param_100fdx_cap:1, 920 param_100hdx_cap:1, 921 param_10fdx_cap:1, 922 param_10hdx_cap:1, 923 param_adv_autoneg:1, 924 param_adv_pause:1, 925 param_adv_asym_pause:1, 926 param_adv_1000fdx:1, 927 param_adv_1000hdx:1, 928 param_adv_100t4:1, 929 param_adv_100fdx:1, 930 param_adv_100hdx:1, 931 param_adv_10fdx:1, 932 param_adv_10hdx:1, 933 param_lp_autoneg:1, 934 param_lp_pause:1, 935 param_lp_asym_pause:1, 936 param_lp_1000fdx:1, 937 param_lp_1000hdx:1, 938 param_lp_100t4:1; 939 940 uint32_t param_lp_100fdx:1, 941 param_lp_100hdx:1, 942 param_lp_10fdx:1, 943 param_lp_10hdx:1, 944 param_pad_to_32:28; 945 946 } e1000g_t; 947 948 949 /* 950 * Function prototypes 951 */ 952 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 953 void e1000g_release_dma_resources(struct e1000g *Adapter); 954 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet); 955 void e1000g_tx_setup(struct e1000g *Adapter); 956 void e1000g_rx_setup(struct e1000g *Adapter); 957 void e1000g_setup_multicast(struct e1000g *Adapter); 958 boolean_t e1000g_reset(struct e1000g *Adapter); 959 960 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 961 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 962 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 963 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 964 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 965 mblk_t *e1000g_receive(struct e1000g *Adapter); 966 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 967 968 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 969 int e1000g_init_stats(struct e1000g *Adapter); 970 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 971 uint32_t frame_len, uint8_t *mac_addr); 972 973 void e1000g_clear_interrupt(struct e1000g *Adapter); 974 void e1000g_mask_interrupt(struct e1000g *Adapter); 975 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 976 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 977 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 978 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 979 void e1000_enable_pciex_master(struct e1000_hw *hw); 980 void e1000g_get_driver_control(struct e1000_hw *hw); 981 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 982 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 983 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 984 void e1000g_set_fma_flags(struct e1000g *Adapter, int acc_flag, int dma_flag); 985 986 int e1000g_reset_link(struct e1000g *Adapter); 987 988 #pragma inline(e1000_rar_set) 989 990 /* 991 * Global variables 992 */ 993 extern boolean_t e1000g_force_detach; 994 extern uint32_t e1000g_mblks_pending; 995 extern krwlock_t e1000g_rx_detach_lock; 996 extern private_devi_list_t *e1000g_private_devi_list; 997 998 #ifdef __cplusplus 999 } 1000 #endif 1001 1002 #endif /* _E1000G_SW_H */ 1003