1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright (c) 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright 2012 David Höppner. All rights reserved. 24 * Copyright (c) 2017, Joyent, Inc. 25 */ 26 27 #ifndef _E1000G_SW_H 28 #define _E1000G_SW_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 /* 35 * ********************************************************************** 36 * Module Name: * 37 * e1000g_sw.h * 38 * * 39 * Abstract: * 40 * This header file contains Software-related data structures * 41 * definitions. * 42 * * 43 * ********************************************************************** 44 */ 45 46 #include <sys/types.h> 47 #include <sys/conf.h> 48 #include <sys/debug.h> 49 #include <sys/stropts.h> 50 #include <sys/stream.h> 51 #include <sys/strsun.h> 52 #include <sys/strlog.h> 53 #include <sys/kmem.h> 54 #include <sys/stat.h> 55 #include <sys/kstat.h> 56 #include <sys/modctl.h> 57 #include <sys/errno.h> 58 #include <sys/mac_provider.h> 59 #include <sys/mac_ether.h> 60 #include <sys/vlan.h> 61 #include <sys/ddi.h> 62 #include <sys/sunddi.h> 63 #include <sys/disp.h> 64 #include <sys/pci.h> 65 #include <sys/sdt.h> 66 #include <sys/ethernet.h> 67 #include <sys/pattr.h> 68 #include <sys/strsubr.h> 69 #include <sys/netlb.h> 70 #include <inet/common.h> 71 #include <inet/ip.h> 72 #include <inet/tcp.h> 73 #include <inet/mi.h> 74 #include <inet/nd.h> 75 #include <sys/ddifm.h> 76 #include <sys/fm/protocol.h> 77 #include <sys/fm/util.h> 78 #include <sys/fm/io/ddi.h> 79 #include "e1000_api.h" 80 81 /* Driver states */ 82 #define E1000G_UNKNOWN 0x00 83 #define E1000G_INITIALIZED 0x01 84 #define E1000G_STARTED 0x02 85 #define E1000G_SUSPENDED 0x04 86 #define E1000G_ERROR 0x80 87 88 #define JUMBO_FRAG_LENGTH 4096 89 90 #define LAST_RAR_ENTRY (E1000_RAR_ENTRIES - 1) 91 #define MAX_NUM_UNICAST_ADDRESSES E1000_RAR_ENTRIES 92 #define MCAST_ALLOC_SIZE 256 93 94 /* 95 * MAX_COOKIES = max_LSO_packet_size(65535 + ethernet_header_len)/page_size 96 * + one for cross page split 97 * MAX_TX_DESC_PER_PACKET = MAX_COOKIES + one for the context descriptor + 98 * two for the workaround of the 82546 chip 99 */ 100 #define MAX_COOKIES 18 101 #define MAX_TX_DESC_PER_PACKET 21 102 103 /* 104 * constants used in setting flow control thresholds 105 */ 106 #define E1000_PBA_MASK 0xffff 107 #define E1000_PBA_SHIFT 10 108 #define E1000_FC_HIGH_DIFF 0x1638 /* High: 5688 bytes below Rx FIFO size */ 109 #define E1000_FC_LOW_DIFF 0x1640 /* Low: 5696 bytes below Rx FIFO size */ 110 #define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */ 111 112 #define MAX_NUM_TX_DESCRIPTOR 4096 113 #define MAX_NUM_RX_DESCRIPTOR 4096 114 #define MAX_NUM_RX_FREELIST 4096 115 #define MAX_NUM_TX_FREELIST 4096 116 #define MAX_RX_LIMIT_ON_INTR 4096 117 #define MAX_RX_INTR_DELAY 65535 118 #define MAX_RX_INTR_ABS_DELAY 65535 119 #define MAX_TX_INTR_DELAY 65535 120 #define MAX_TX_INTR_ABS_DELAY 65535 121 #define MAX_INTR_THROTTLING 65535 122 #define MAX_RX_BCOPY_THRESHOLD E1000_RX_BUFFER_SIZE_2K 123 #define MAX_TX_BCOPY_THRESHOLD E1000_TX_BUFFER_SIZE_2K 124 #define MAX_MCAST_NUM 8192 125 126 #define MIN_NUM_TX_DESCRIPTOR 80 127 #define MIN_NUM_RX_DESCRIPTOR 80 128 #define MIN_NUM_RX_FREELIST 64 129 #define MIN_NUM_TX_FREELIST 80 130 #define MIN_RX_LIMIT_ON_INTR 16 131 #define MIN_RX_INTR_DELAY 0 132 #define MIN_RX_INTR_ABS_DELAY 0 133 #define MIN_TX_INTR_DELAY 0 134 #define MIN_TX_INTR_ABS_DELAY 0 135 #define MIN_INTR_THROTTLING 0 136 #define MIN_RX_BCOPY_THRESHOLD 0 137 #define MIN_TX_BCOPY_THRESHOLD ETHERMIN 138 #define MIN_MCAST_NUM 8 139 140 #define DEFAULT_NUM_RX_DESCRIPTOR 2048 141 #define DEFAULT_NUM_TX_DESCRIPTOR 2048 142 #define DEFAULT_NUM_RX_FREELIST 4096 143 #define DEFAULT_NUM_TX_FREELIST 2304 144 #define DEFAULT_JUMBO_NUM_RX_DESC 1024 145 #define DEFAULT_JUMBO_NUM_TX_DESC 1024 146 #define DEFAULT_JUMBO_NUM_RX_BUF 2048 147 #define DEFAULT_JUMBO_NUM_TX_BUF 1152 148 #define DEFAULT_RX_LIMIT_ON_INTR 128 149 #define RX_FREELIST_INCREASE_SIZE 512 150 151 #ifdef __sparc 152 #define MAX_INTR_PER_SEC 7100 153 #define MIN_INTR_PER_SEC 3000 154 #define DEFAULT_INTR_PACKET_LOW 5 155 #define DEFAULT_INTR_PACKET_HIGH 128 156 #else 157 #define MAX_INTR_PER_SEC 15000 158 #define MIN_INTR_PER_SEC 4000 159 #define DEFAULT_INTR_PACKET_LOW 10 160 #define DEFAULT_INTR_PACKET_HIGH 48 161 #endif 162 163 #define DEFAULT_RX_INTR_DELAY 0 164 #define DEFAULT_RX_INTR_ABS_DELAY 64 165 #define DEFAULT_TX_INTR_DELAY 64 166 #define DEFAULT_TX_INTR_ABS_DELAY 64 167 #define DEFAULT_INTR_THROTTLING_HIGH 1000000000/(MIN_INTR_PER_SEC*256) 168 #define DEFAULT_INTR_THROTTLING_LOW 1000000000/(MAX_INTR_PER_SEC*256) 169 #define DEFAULT_INTR_THROTTLING DEFAULT_INTR_THROTTLING_LOW 170 171 #define DEFAULT_RX_BCOPY_THRESHOLD 128 172 #define DEFAULT_TX_BCOPY_THRESHOLD 512 173 #define DEFAULT_TX_UPDATE_THRESHOLD 256 174 #define DEFAULT_TX_NO_RESOURCE MAX_TX_DESC_PER_PACKET 175 176 #define DEFAULT_TX_INTR_ENABLE 1 177 #define DEFAULT_FLOW_CONTROL 3 178 #define DEFAULT_MASTER_LATENCY_TIMER 0 /* BIOS should decide */ 179 /* which is normally 0x040 */ 180 #define DEFAULT_TBI_COMPAT_ENABLE 1 /* Enable SBP workaround */ 181 #define DEFAULT_MSI_ENABLE 1 /* MSI Enable */ 182 #define DEFAULT_TX_HCKSUM_ENABLE 1 /* Hardware checksum enable */ 183 #define DEFAULT_LSO_ENABLE 1 /* LSO enable */ 184 #define DEFAULT_MEM_WORKAROUND_82546 1 /* 82546 memory workaround */ 185 186 #define TX_DRAIN_TIME (200) /* # milliseconds xmit drain */ 187 #define RX_DRAIN_TIME (200) /* # milliseconds recv drain */ 188 189 #define TX_STALL_TIME_2S (200) /* in unit of tick */ 190 #define TX_STALL_TIME_8S (800) /* in unit of tick */ 191 192 /* 193 * The size of the receive/transmite buffers 194 */ 195 #define E1000_RX_BUFFER_SIZE_2K (2048) 196 #define E1000_RX_BUFFER_SIZE_4K (4096) 197 #define E1000_RX_BUFFER_SIZE_8K (8192) 198 #define E1000_RX_BUFFER_SIZE_16K (16384) 199 200 #define E1000_TX_BUFFER_SIZE_2K (2048) 201 #define E1000_TX_BUFFER_SIZE_4K (4096) 202 #define E1000_TX_BUFFER_SIZE_8K (8192) 203 #define E1000_TX_BUFFER_SIZE_16K (16384) 204 205 #define E1000_TX_BUFFER_OEVRRUN_THRESHOLD (2015) 206 207 #define E1000G_RX_NORMAL 0x0 208 #define E1000G_RX_STOPPED 0x1 209 210 #define E1000G_CHAIN_NO_LIMIT 0 211 212 /* 213 * definitions for smartspeed workaround 214 */ 215 #define E1000_SMARTSPEED_MAX 30 /* 30 watchdog iterations */ 216 /* or 30 seconds */ 217 #define E1000_SMARTSPEED_DOWNSHIFT 6 /* 6 watchdog iterations */ 218 /* or 6 seconds */ 219 220 /* 221 * Definitions for module_info. 222 */ 223 #define WSNAME "e1000g" /* module name */ 224 225 /* 226 * Defined for IP header alignment. We also need to preserve space for 227 * VLAN tag (4 bytes) 228 */ 229 #define E1000G_IPALIGNROOM 2 230 231 /* 232 * bit flags for 'attach_progress' which is a member variable in struct e1000g 233 */ 234 #define ATTACH_PROGRESS_PCI_CONFIG 0x0001 /* PCI config setup */ 235 #define ATTACH_PROGRESS_REGS_MAP 0x0002 /* Registers mapped */ 236 #define ATTACH_PROGRESS_SETUP 0x0004 /* Setup driver parameters */ 237 #define ATTACH_PROGRESS_ADD_INTR 0x0008 /* Interrupt added */ 238 #define ATTACH_PROGRESS_LOCKS 0x0010 /* Locks initialized */ 239 #define ATTACH_PROGRESS_SOFT_INTR 0x0020 /* Soft interrupt added */ 240 #define ATTACH_PROGRESS_KSTATS 0x0040 /* Kstats created */ 241 #define ATTACH_PROGRESS_ALLOC 0x0080 /* DMA resources allocated */ 242 #define ATTACH_PROGRESS_INIT 0x0100 /* Driver initialization */ 243 /* 0200 used to be PROGRESS_NDD. Now unused */ 244 #define ATTACH_PROGRESS_MAC 0x0400 /* MAC registered */ 245 #define ATTACH_PROGRESS_ENABLE_INTR 0x0800 /* DDI interrupts enabled */ 246 #define ATTACH_PROGRESS_FMINIT 0x1000 /* FMA initiated */ 247 248 /* 249 * Speed and Duplex Settings 250 */ 251 #define GDIAG_10_HALF 1 252 #define GDIAG_10_FULL 2 253 #define GDIAG_100_HALF 3 254 #define GDIAG_100_FULL 4 255 #define GDIAG_1000_FULL 6 256 #define GDIAG_ANY 7 257 258 /* 259 * Coexist Workaround RP: 07/04/03 260 * 82544 Workaround : Co-existence 261 */ 262 #define MAX_TX_BUF_SIZE (8 * 1024) 263 264 /* 265 * Defines for Jumbo Frame 266 */ 267 #define FRAME_SIZE_UPTO_2K 2048 268 #define FRAME_SIZE_UPTO_4K 4096 269 #define FRAME_SIZE_UPTO_8K 8192 270 #define FRAME_SIZE_UPTO_16K 16384 271 #define FRAME_SIZE_UPTO_9K 9234 272 273 #define DEFAULT_MTU ETHERMTU 274 #define MAXIMUM_MTU_4K 4096 275 #define MAXIMUM_MTU_9K 9216 276 277 #define DEFAULT_FRAME_SIZE \ 278 (DEFAULT_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 279 #define MAXIMUM_FRAME_SIZE \ 280 (MAXIMUM_MTU + sizeof (struct ether_vlan_header) + ETHERFCSL) 281 282 #define E1000_LSO_MAXLEN 65535 283 #define E1000_LSO_FIRST_DESC_ALIGNMENT_BOUNDARY_4K 4096 284 #define E1000_LSO_FIRST_DESC_ALIGNMENT 128 285 286 /* Defines for Tx stall check */ 287 #define E1000G_STALL_WATCHDOG_COUNT 8 288 289 #define MAX_TX_LINK_DOWN_TIMEOUT 8 290 291 /* Defines for DVMA */ 292 #ifdef __sparc 293 #define E1000G_DEFAULT_DVMA_PAGE_NUM 2 294 #endif 295 296 /* 297 * Loopback definitions 298 */ 299 #define E1000G_LB_NONE 0 300 #define E1000G_LB_EXTERNAL_1000 1 301 #define E1000G_LB_EXTERNAL_100 2 302 #define E1000G_LB_EXTERNAL_10 3 303 #define E1000G_LB_INTERNAL_PHY 4 304 305 /* 306 * Private dip list definitions 307 */ 308 #define E1000G_PRIV_DEVI_ATTACH 0x0 309 #define E1000G_PRIV_DEVI_DETACH 0x1 310 311 /* 312 * Tx descriptor LENGTH field mask 313 */ 314 #define E1000G_TBD_LENGTH_MASK 0x000fffff 315 316 #define E1000G_IS_VLAN_PACKET(ptr) \ 317 ((((struct ether_vlan_header *)(uintptr_t)ptr)->ether_tpid) == \ 318 htons(ETHERTYPE_VLAN)) 319 320 /* 321 * QUEUE_INIT_LIST -- Macro which will init ialize a queue to NULL. 322 */ 323 #define QUEUE_INIT_LIST(_LH) \ 324 (_LH)->Flink = (_LH)->Blink = (PSINGLE_LIST_LINK)0 325 326 /* 327 * IS_QUEUE_EMPTY -- Macro which checks to see if a queue is empty. 328 */ 329 #define IS_QUEUE_EMPTY(_LH) \ 330 ((_LH)->Flink == (PSINGLE_LIST_LINK)0) 331 332 /* 333 * QUEUE_GET_HEAD -- Macro which returns the head of the queue, but does 334 * not remove the head from the queue. 335 */ 336 #define QUEUE_GET_HEAD(_LH) ((PSINGLE_LIST_LINK)((_LH)->Flink)) 337 338 /* 339 * QUEUE_REMOVE_HEAD -- Macro which removes the head of the head of a queue. 340 */ 341 #define QUEUE_REMOVE_HEAD(_LH) \ 342 { \ 343 PSINGLE_LIST_LINK ListElem; \ 344 if (ListElem = (_LH)->Flink) \ 345 { \ 346 if (!((_LH)->Flink = ListElem->Flink)) \ 347 (_LH)->Blink = (PSINGLE_LIST_LINK) 0; \ 348 } \ 349 } 350 351 /* 352 * QUEUE_POP_HEAD -- Macro which will pop the head off of a queue (list), 353 * and return it (this differs from QUEUE_REMOVE_HEAD only in 354 * the 1st line). 355 */ 356 #define QUEUE_POP_HEAD(_LH) \ 357 (PSINGLE_LIST_LINK)(_LH)->Flink; \ 358 { \ 359 PSINGLE_LIST_LINK ListElem; \ 360 ListElem = (_LH)->Flink; \ 361 if (ListElem) \ 362 { \ 363 (_LH)->Flink = ListElem->Flink; \ 364 if (!(_LH)->Flink) \ 365 (_LH)->Blink = (PSINGLE_LIST_LINK)0; \ 366 } \ 367 } 368 369 /* 370 * QUEUE_GET_TAIL -- Macro which returns the tail of the queue, but does not 371 * remove the tail from the queue. 372 */ 373 #define QUEUE_GET_TAIL(_LH) ((PSINGLE_LIST_LINK)((_LH)->Blink)) 374 375 /* 376 * QUEUE_PUSH_TAIL -- Macro which puts an element at the tail (end) of the queue 377 */ 378 #define QUEUE_PUSH_TAIL(_LH, _E) \ 379 if ((_LH)->Blink) \ 380 { \ 381 ((PSINGLE_LIST_LINK)(_LH)->Blink)->Flink = \ 382 (PSINGLE_LIST_LINK)(_E); \ 383 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 384 } else { \ 385 (_LH)->Flink = \ 386 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 387 } \ 388 (_E)->Flink = (PSINGLE_LIST_LINK)0; 389 390 /* 391 * QUEUE_PUSH_HEAD -- Macro which puts an element at the head of the queue. 392 */ 393 #define QUEUE_PUSH_HEAD(_LH, _E) \ 394 if (!((_E)->Flink = (_LH)->Flink)) \ 395 { \ 396 (_LH)->Blink = (PSINGLE_LIST_LINK)(_E); \ 397 } \ 398 (_LH)->Flink = (PSINGLE_LIST_LINK)(_E); 399 400 /* 401 * QUEUE_GET_NEXT -- Macro which returns the next element linked to the 402 * current element. 403 */ 404 #define QUEUE_GET_NEXT(_LH, _E) \ 405 (PSINGLE_LIST_LINK)((((_LH)->Blink) == (_E)) ? \ 406 (0) : ((_E)->Flink)) 407 408 /* 409 * QUEUE_APPEND -- Macro which appends a queue to the tail of another queue 410 */ 411 #define QUEUE_APPEND(_LH1, _LH2) \ 412 if ((_LH2)->Flink) { \ 413 if ((_LH1)->Flink) { \ 414 ((PSINGLE_LIST_LINK)(_LH1)->Blink)->Flink = \ 415 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 416 } else { \ 417 (_LH1)->Flink = \ 418 ((PSINGLE_LIST_LINK)(_LH2)->Flink); \ 419 } \ 420 (_LH1)->Blink = ((PSINGLE_LIST_LINK)(_LH2)->Blink); \ 421 } 422 423 424 #define QUEUE_SWITCH(_LH1, _LH2) \ 425 if ((_LH2)->Flink) { \ 426 (_LH1)->Flink = (_LH2)->Flink; \ 427 (_LH1)->Blink = (_LH2)->Blink; \ 428 (_LH2)->Flink = (_LH2)->Blink = (PSINGLE_LIST_LINK)0; \ 429 } 430 431 /* 432 * Property lookups 433 */ 434 #define E1000G_PROP_EXISTS(d, n) ddi_prop_exists(DDI_DEV_T_ANY, (d), \ 435 DDI_PROP_DONTPASS, (n)) 436 #define E1000G_PROP_GET_INT(d, n) ddi_prop_get_int(DDI_DEV_T_ANY, (d), \ 437 DDI_PROP_DONTPASS, (n), -1) 438 439 #ifdef E1000G_DEBUG 440 /* 441 * E1000G-specific ioctls ... 442 */ 443 #define E1000G_IOC ((((((('E' << 4) + '1') << 4) \ 444 + 'K') << 4) + 'G') << 4) 445 446 /* 447 * These diagnostic IOCTLS are enabled only in DEBUG drivers 448 */ 449 #define E1000G_IOC_REG_PEEK (E1000G_IOC | 1) 450 #define E1000G_IOC_REG_POKE (E1000G_IOC | 2) 451 #define E1000G_IOC_CHIP_RESET (E1000G_IOC | 3) 452 453 #define E1000G_PP_SPACE_REG 0 /* PCI memory space */ 454 #define E1000G_PP_SPACE_E1000G 1 /* driver's soft state */ 455 456 typedef struct { 457 uint64_t pp_acc_size; /* It's 1, 2, 4 or 8 */ 458 uint64_t pp_acc_space; /* See #defines below */ 459 uint64_t pp_acc_offset; /* See regs definition */ 460 uint64_t pp_acc_data; /* output for peek */ 461 /* input for poke */ 462 } e1000g_peekpoke_t; 463 #endif /* E1000G_DEBUG */ 464 465 /* 466 * (Internal) return values from ioctl subroutines 467 */ 468 enum ioc_reply { 469 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 470 IOC_DONE, /* OK, reply sent */ 471 IOC_ACK, /* OK, just send ACK */ 472 IOC_REPLY /* OK, just send reply */ 473 }; 474 475 /* 476 * Named Data (ND) Parameter Management Structure 477 */ 478 typedef struct { 479 uint32_t ndp_info; 480 uint32_t ndp_min; 481 uint32_t ndp_max; 482 uint32_t ndp_val; 483 struct e1000g *ndp_instance; 484 char *ndp_name; 485 } nd_param_t; 486 487 /* 488 * The entry of the private dip list 489 */ 490 typedef struct _private_devi_list { 491 dev_info_t *priv_dip; 492 uint32_t flag; 493 uint32_t pending_rx_count; 494 struct _private_devi_list *prev; 495 struct _private_devi_list *next; 496 } private_devi_list_t; 497 498 /* 499 * A structure that points to the next entry in the queue. 500 */ 501 typedef struct _SINGLE_LIST_LINK { 502 struct _SINGLE_LIST_LINK *Flink; 503 } SINGLE_LIST_LINK, *PSINGLE_LIST_LINK; 504 505 /* 506 * A "ListHead" structure that points to the head and tail of a queue 507 */ 508 typedef struct _LIST_DESCRIBER { 509 struct _SINGLE_LIST_LINK *volatile Flink; 510 struct _SINGLE_LIST_LINK *volatile Blink; 511 } LIST_DESCRIBER, *PLIST_DESCRIBER; 512 513 enum e1000g_bar_type { 514 E1000G_BAR_CONFIG = 0, 515 E1000G_BAR_IO, 516 E1000G_BAR_MEM32, 517 E1000G_BAR_MEM64 518 }; 519 520 typedef struct { 521 enum e1000g_bar_type type; 522 int rnumber; 523 } bar_info_t; 524 525 /* 526 * Address-Length pair structure that stores descriptor info 527 */ 528 typedef struct _sw_desc { 529 uint64_t address; 530 uint32_t length; 531 } sw_desc_t, *p_sw_desc_t; 532 533 typedef struct _desc_array { 534 sw_desc_t descriptor[4]; 535 uint32_t elements; 536 } desc_array_t, *p_desc_array_t; 537 538 typedef enum { 539 USE_NONE, 540 USE_BCOPY, 541 USE_DVMA, 542 USE_DMA 543 } dma_type_t; 544 545 typedef struct _dma_buffer { 546 caddr_t address; 547 uint64_t dma_address; 548 ddi_acc_handle_t acc_handle; 549 ddi_dma_handle_t dma_handle; 550 size_t size; 551 size_t len; 552 } dma_buffer_t, *p_dma_buffer_t; 553 554 /* 555 * Transmit Control Block (TCB), Ndis equiv of SWPacket This 556 * structure stores the additional information that is 557 * associated with every packet to be transmitted. It stores the 558 * message block pointer and the TBD addresses associated with 559 * the m_blk and also the link to the next tcb in the chain 560 */ 561 typedef struct _tx_sw_packet { 562 /* Link to the next tx_sw_packet in the list */ 563 SINGLE_LIST_LINK Link; 564 mblk_t *mp; 565 uint32_t num_desc; 566 uint32_t num_mblk_frag; 567 dma_type_t dma_type; 568 dma_type_t data_transfer_type; 569 ddi_dma_handle_t tx_dma_handle; 570 dma_buffer_t tx_buf[1]; 571 sw_desc_t desc[MAX_TX_DESC_PER_PACKET]; 572 int64_t tickstamp; 573 } tx_sw_packet_t, *p_tx_sw_packet_t; 574 575 /* 576 * This structure is similar to the rx_sw_packet structure used 577 * for Ndis. This structure stores information about the 2k 578 * aligned receive buffer into which the FX1000 DMA's frames. 579 * This structure is maintained as a linked list of many 580 * receiver buffer pointers. 581 */ 582 typedef struct _rx_sw_packet { 583 /* Link to the next rx_sw_packet_t in the list */ 584 SINGLE_LIST_LINK Link; 585 struct _rx_sw_packet *next; 586 uint32_t ref_cnt; 587 mblk_t *mp; 588 caddr_t rx_data; 589 dma_type_t dma_type; 590 frtn_t free_rtn; 591 dma_buffer_t rx_buf[1]; 592 } rx_sw_packet_t, *p_rx_sw_packet_t; 593 594 typedef struct _mblk_list { 595 mblk_t *head; 596 mblk_t *tail; 597 } mblk_list_t, *p_mblk_list_t; 598 599 typedef struct _context_data { 600 uint32_t ether_header_size; 601 uint32_t cksum_flags; 602 uint32_t cksum_start; 603 uint32_t cksum_stuff; 604 uint16_t mss; 605 uint8_t hdr_len; 606 uint32_t pay_len; 607 boolean_t lso_flag; 608 } context_data_t; 609 610 typedef union _e1000g_ether_addr { 611 struct { 612 uint32_t high; 613 uint32_t low; 614 } reg; 615 struct { 616 uint8_t set; 617 uint8_t redundant; 618 uint8_t addr[ETHERADDRL]; 619 } mac; 620 } e1000g_ether_addr_t; 621 622 typedef struct _e1000g_stat { 623 kstat_named_t reset_count; /* Reset Count */ 624 625 kstat_named_t rx_error; /* Rx Error in Packet */ 626 kstat_named_t rx_allocb_fail; /* Rx Allocb Failure */ 627 kstat_named_t rx_size_error; /* Rx Size Error */ 628 629 kstat_named_t tx_no_desc; /* Tx No Desc */ 630 kstat_named_t tx_no_swpkt; /* Tx No Pkt Buffer */ 631 kstat_named_t tx_send_fail; /* Tx SendPkt Failure */ 632 kstat_named_t tx_over_size; /* Tx Pkt Too Long */ 633 kstat_named_t tx_reschedule; /* Tx Reschedule */ 634 635 #ifdef E1000G_DEBUG 636 kstat_named_t rx_none; /* Rx No Incoming Data */ 637 kstat_named_t rx_multi_desc; /* Rx Multi Spanned Pkt */ 638 kstat_named_t rx_no_freepkt; /* Rx No Free Pkt */ 639 kstat_named_t rx_avail_freepkt; /* Rx Freelist Avail Buffers */ 640 641 kstat_named_t tx_under_size; /* Tx Packet Under Size */ 642 kstat_named_t tx_empty_frags; /* Tx Empty Frags */ 643 kstat_named_t tx_exceed_frags; /* Tx Exceed Max Frags */ 644 kstat_named_t tx_recycle; /* Tx Recycle */ 645 kstat_named_t tx_recycle_intr; /* Tx Recycle in Intr */ 646 kstat_named_t tx_recycle_retry; /* Tx Recycle Retry */ 647 kstat_named_t tx_recycle_none; /* Tx No Desc Recycled */ 648 kstat_named_t tx_copy; /* Tx Send Copy */ 649 kstat_named_t tx_bind; /* Tx Send Bind */ 650 kstat_named_t tx_multi_copy; /* Tx Copy Multi Fragments */ 651 kstat_named_t tx_multi_cookie; /* Tx Pkt Span Multi Cookies */ 652 kstat_named_t tx_lack_desc; /* Tx Lack of Desc */ 653 #endif 654 655 kstat_named_t Symerrs; /* Symbol Error Count */ 656 kstat_named_t Mpc; /* Missed Packet Count */ 657 kstat_named_t Rlec; /* Receive Length Error Count */ 658 kstat_named_t Xonrxc; /* XON Received Count */ 659 kstat_named_t Xontxc; /* XON Xmitted Count */ 660 kstat_named_t Xoffrxc; /* XOFF Received Count */ 661 kstat_named_t Xofftxc; /* Xoff Xmitted Count */ 662 kstat_named_t Fcruc; /* Unknown Flow Conrol Packet Rcvd Count */ 663 #ifdef E1000G_DEBUG 664 kstat_named_t Prc64; /* Packets Received - 64b */ 665 kstat_named_t Prc127; /* Packets Received - 65-127b */ 666 kstat_named_t Prc255; /* Packets Received - 127-255b */ 667 kstat_named_t Prc511; /* Packets Received - 256-511b */ 668 kstat_named_t Prc1023; /* Packets Received - 511-1023b */ 669 kstat_named_t Prc1522; /* Packets Received - 1024-1522b */ 670 #endif 671 kstat_named_t Gprc; /* Good Packets Received Count */ 672 kstat_named_t Gptc; /* Good Packets Xmitted Count */ 673 kstat_named_t Gorl; /* Good Octets Recvd Lo Count */ 674 kstat_named_t Gorh; /* Good Octets Recvd Hi Count */ 675 kstat_named_t Gotl; /* Good Octets Xmitd Lo Count */ 676 kstat_named_t Goth; /* Good Octets Xmitd Hi Count */ 677 kstat_named_t Rfc; /* Receive Frag Count */ 678 #ifdef E1000G_DEBUG 679 kstat_named_t Ptc64; /* Packets Xmitted (64b) */ 680 kstat_named_t Ptc127; /* Packets Xmitted (64-127b) */ 681 kstat_named_t Ptc255; /* Packets Xmitted (128-255b) */ 682 kstat_named_t Ptc511; /* Packets Xmitted (255-511b) */ 683 kstat_named_t Ptc1023; /* Packets Xmitted (512-1023b) */ 684 kstat_named_t Ptc1522; /* Packets Xmitted (1024-1522b */ 685 #endif 686 kstat_named_t Tncrs; /* Transmit with no CRS */ 687 kstat_named_t Tsctc; /* TCP seg contexts xmit count */ 688 kstat_named_t Tsctfc; /* TCP seg contexts xmit fail count */ 689 } e1000g_stat_t, *p_e1000g_stat_t; 690 691 typedef struct _e1000g_tx_ring { 692 kmutex_t tx_lock; 693 kmutex_t freelist_lock; 694 kmutex_t usedlist_lock; 695 /* 696 * Descriptor queue definitions 697 */ 698 ddi_dma_handle_t tbd_dma_handle; 699 ddi_acc_handle_t tbd_acc_handle; 700 struct e1000_tx_desc *tbd_area; 701 uint64_t tbd_dma_addr; 702 struct e1000_tx_desc *tbd_first; 703 struct e1000_tx_desc *tbd_last; 704 struct e1000_tx_desc *tbd_oldest; 705 struct e1000_tx_desc *tbd_next; 706 uint32_t tbd_avail; 707 /* 708 * Software packet structures definitions 709 */ 710 p_tx_sw_packet_t packet_area; 711 LIST_DESCRIBER used_list; 712 LIST_DESCRIBER free_list; 713 /* 714 * TCP/UDP Context Data Information 715 */ 716 context_data_t pre_context; 717 /* 718 * Timer definitions for 82547 719 */ 720 timeout_id_t timer_id_82547; 721 boolean_t timer_enable_82547; 722 /* 723 * reschedule when tx resource is available 724 */ 725 boolean_t resched_needed; 726 clock_t resched_timestamp; 727 mblk_list_t mblks; 728 /* 729 * Statistics 730 */ 731 uint32_t stat_no_swpkt; 732 uint32_t stat_no_desc; 733 uint32_t stat_send_fail; 734 uint32_t stat_reschedule; 735 uint32_t stat_timer_reschedule; 736 uint32_t stat_over_size; 737 #ifdef E1000G_DEBUG 738 uint32_t stat_under_size; 739 uint32_t stat_exceed_frags; 740 uint32_t stat_empty_frags; 741 uint32_t stat_recycle; 742 uint32_t stat_recycle_intr; 743 uint32_t stat_recycle_retry; 744 uint32_t stat_recycle_none; 745 uint32_t stat_copy; 746 uint32_t stat_bind; 747 uint32_t stat_multi_copy; 748 uint32_t stat_multi_cookie; 749 uint32_t stat_lack_desc; 750 uint32_t stat_lso_header_fail; 751 #endif 752 /* 753 * Pointer to the adapter 754 */ 755 struct e1000g *adapter; 756 } e1000g_tx_ring_t, *pe1000g_tx_ring_t; 757 758 typedef struct _e1000g_rx_data { 759 kmutex_t freelist_lock; 760 kmutex_t recycle_lock; 761 /* 762 * Descriptor queue definitions 763 */ 764 ddi_dma_handle_t rbd_dma_handle; 765 ddi_acc_handle_t rbd_acc_handle; 766 struct e1000_rx_desc *rbd_area; 767 uint64_t rbd_dma_addr; 768 struct e1000_rx_desc *rbd_first; 769 struct e1000_rx_desc *rbd_last; 770 struct e1000_rx_desc *rbd_next; 771 /* 772 * Software packet structures definitions 773 */ 774 p_rx_sw_packet_t packet_area; 775 LIST_DESCRIBER recv_list; 776 LIST_DESCRIBER free_list; 777 LIST_DESCRIBER recycle_list; 778 uint32_t flag; 779 780 uint32_t pending_count; 781 uint32_t avail_freepkt; 782 uint32_t recycle_freepkt; 783 uint32_t rx_mblk_len; 784 mblk_t *rx_mblk; 785 mblk_t *rx_mblk_tail; 786 787 private_devi_list_t *priv_devi_node; 788 struct _e1000g_rx_ring *rx_ring; 789 } e1000g_rx_data_t; 790 791 typedef struct _e1000g_rx_ring { 792 e1000g_rx_data_t *rx_data; 793 794 kmutex_t rx_lock; 795 796 mac_ring_handle_t mrh; 797 mac_ring_handle_t mrh_init; 798 uint64_t ring_gen_num; 799 boolean_t poll_flag; 800 801 /* 802 * Statistics 803 */ 804 uint32_t stat_error; 805 uint32_t stat_allocb_fail; 806 uint32_t stat_exceed_pkt; 807 uint32_t stat_size_error; 808 uint32_t stat_crc_only_pkt; 809 #ifdef E1000G_DEBUG 810 uint32_t stat_none; 811 uint32_t stat_multi_desc; 812 uint32_t stat_no_freepkt; 813 #endif 814 /* 815 * Pointer to the adapter 816 */ 817 struct e1000g *adapter; 818 } e1000g_rx_ring_t, *pe1000g_rx_ring_t; 819 820 typedef struct e1000g { 821 int instance; 822 dev_info_t *dip; 823 dev_info_t *priv_dip; 824 private_devi_list_t *priv_devi_node; 825 mac_handle_t mh; 826 mac_resource_handle_t mrh; 827 struct e1000_hw shared; 828 struct e1000g_osdep osdep; 829 830 uint32_t e1000g_state; 831 boolean_t e1000g_promisc; 832 boolean_t strip_crc; 833 boolean_t rx_buffer_setup; 834 boolean_t esb2_workaround; 835 link_state_t link_state; 836 uint64_t link_speed; 837 uint32_t link_duplex; 838 uint32_t master_latency_timer; 839 uint32_t smartspeed; /* smartspeed w/a counter */ 840 uint32_t init_count; 841 uint32_t reset_count; 842 boolean_t reset_flag; 843 uint32_t stall_threshold; 844 boolean_t stall_flag; 845 uint32_t attach_progress; /* attach tracking */ 846 uint32_t loopback_mode; 847 uint32_t pending_rx_count; 848 849 uint32_t align_errors; 850 uint32_t brdcstrcv; 851 uint32_t brdcstxmt; 852 uint32_t carrier_errors; 853 uint32_t collisions; 854 uint32_t defer_xmts; 855 uint32_t ex_collisions; 856 uint32_t fcs_errors; 857 uint32_t first_collisions; 858 uint32_t ipackets; 859 uint32_t jabber_errors; 860 uint32_t macrcv_errors; 861 uint32_t macxmt_errors; 862 uint32_t multi_collisions; 863 uint32_t multircv; 864 uint32_t multixmt; 865 uint32_t norcvbuf; 866 uint32_t oerrors; 867 uint32_t opackets; 868 uint32_t sqe_errors; 869 uint32_t toolong_errors; 870 uint32_t tooshort_errors; 871 uint32_t tx_late_collisions; 872 uint64_t obytes; 873 uint64_t rbytes; 874 875 uint32_t tx_desc_num; 876 uint32_t tx_freelist_num; 877 uint32_t rx_desc_num; 878 uint32_t rx_freelist_num; 879 uint32_t rx_freelist_limit; 880 uint32_t tx_buffer_size; 881 uint32_t rx_buffer_size; 882 883 uint32_t tx_link_down_timeout; 884 uint32_t tx_bcopy_thresh; 885 uint32_t rx_limit_onintr; 886 uint32_t rx_bcopy_thresh; 887 uint32_t rx_buf_align; 888 uint32_t desc_align; 889 890 boolean_t intr_adaptive; 891 boolean_t tx_intr_enable; 892 uint32_t tx_intr_delay; 893 uint32_t tx_intr_abs_delay; 894 uint32_t rx_intr_delay; 895 uint32_t rx_intr_abs_delay; 896 uint32_t intr_throttling_rate; 897 898 uint32_t tx_desc_num_flag:1, 899 rx_desc_num_flag:1, 900 tx_buf_num_flag:1, 901 rx_buf_num_flag:1, 902 pad_to_32:28; 903 904 uint32_t default_mtu; 905 uint32_t max_mtu; 906 uint32_t max_frame_size; 907 uint32_t min_frame_size; 908 909 boolean_t watchdog_timer_enabled; 910 boolean_t watchdog_timer_started; 911 timeout_id_t watchdog_tid; 912 boolean_t link_complete; 913 timeout_id_t link_tid; 914 915 e1000g_rx_ring_t rx_ring[1]; 916 e1000g_tx_ring_t tx_ring[1]; 917 mac_group_handle_t rx_group; 918 919 /* 920 * Rx and Tx packet count for interrupt adaptive setting 921 */ 922 uint32_t rx_pkt_cnt; 923 uint32_t tx_pkt_cnt; 924 925 /* 926 * The watchdog_lock must be held when updateing the 927 * timeout fields in struct e1000g, that is, 928 * watchdog_tid, watchdog_timer_started. 929 */ 930 kmutex_t watchdog_lock; 931 /* 932 * The link_lock protects the link_complete and link_tid 933 * fields in struct e1000g. 934 */ 935 kmutex_t link_lock; 936 /* 937 * The chip_lock assures that the Rx/Tx process must be 938 * stopped while other functions change the hardware 939 * configuration of e1000g card, such as e1000g_reset(), 940 * e1000g_reset_hw() etc are executed. 941 */ 942 krwlock_t chip_lock; 943 944 boolean_t unicst_init; 945 uint32_t unicst_avail; 946 uint32_t unicst_total; 947 e1000g_ether_addr_t unicst_addr[MAX_NUM_UNICAST_ADDRESSES]; 948 949 uint32_t mcast_count; 950 uint32_t mcast_max_num; 951 uint32_t mcast_alloc_count; 952 struct ether_addr *mcast_table; 953 954 ulong_t sys_page_sz; 955 #ifdef __sparc 956 uint_t dvma_page_num; 957 #endif 958 959 boolean_t msi_enable; 960 boolean_t tx_hcksum_enable; 961 boolean_t lso_enable; 962 boolean_t lso_premature_issue; 963 boolean_t mem_workaround_82546; 964 int intr_type; 965 int intr_cnt; 966 int intr_cap; 967 size_t intr_size; 968 uint_t intr_pri; 969 ddi_intr_handle_t *htable; 970 971 int tx_softint_pri; 972 ddi_softint_handle_t tx_softint_handle; 973 974 kstat_t *e1000g_ksp; 975 976 boolean_t poll_mode; 977 978 uint16_t phy_ctrl; /* contents of PHY_CTRL */ 979 uint16_t phy_status; /* contents of PHY_STATUS */ 980 uint16_t phy_an_adv; /* contents of PHY_AUTONEG_ADV */ 981 uint16_t phy_an_exp; /* contents of PHY_AUTONEG_EXP */ 982 uint16_t phy_ext_status; /* contents of PHY_EXT_STATUS */ 983 uint16_t phy_1000t_ctrl; /* contents of PHY_1000T_CTRL */ 984 uint16_t phy_1000t_status; /* contents of PHY_1000T_STATUS */ 985 uint16_t phy_lp_able; /* contents of PHY_LP_ABILITY */ 986 987 /* 988 * LED Controls 989 */ 990 kmutex_t e1000g_led_lock; 991 boolean_t e1000g_led_setup; 992 boolean_t e1000g_emul_blink; 993 boolean_t e1000g_emul_state; 994 ddi_periodic_t e1000g_blink; 995 996 /* 997 * FMA capabilities 998 */ 999 int fm_capabilities; 1000 1001 uint32_t param_en_1000fdx:1, 1002 param_en_1000hdx:1, 1003 param_en_100fdx:1, 1004 param_en_100hdx:1, 1005 param_en_10fdx:1, 1006 param_en_10hdx:1, 1007 param_autoneg_cap:1, 1008 param_pause_cap:1, 1009 param_asym_pause_cap:1, 1010 param_1000fdx_cap:1, 1011 param_1000hdx_cap:1, 1012 param_100t4_cap:1, 1013 param_100fdx_cap:1, 1014 param_100hdx_cap:1, 1015 param_10fdx_cap:1, 1016 param_10hdx_cap:1, 1017 param_adv_autoneg:1, 1018 param_adv_pause:1, 1019 param_adv_asym_pause:1, 1020 param_adv_1000fdx:1, 1021 param_adv_1000hdx:1, 1022 param_adv_100t4:1, 1023 param_adv_100fdx:1, 1024 param_adv_100hdx:1, 1025 param_adv_10fdx:1, 1026 param_adv_10hdx:1, 1027 param_lp_autoneg:1, 1028 param_lp_pause:1, 1029 param_lp_asym_pause:1, 1030 param_lp_1000fdx:1, 1031 param_lp_1000hdx:1, 1032 param_lp_100t4:1; 1033 1034 uint32_t param_lp_100fdx:1, 1035 param_lp_100hdx:1, 1036 param_lp_10fdx:1, 1037 param_lp_10hdx:1, 1038 param_pad_to_32:28; 1039 1040 } e1000g_t; 1041 1042 1043 /* 1044 * Function prototypes 1045 */ 1046 void e1000g_free_priv_devi_node(private_devi_list_t *devi_node); 1047 void e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data); 1048 void e1000g_free_rx_data(e1000g_rx_data_t *rx_data); 1049 int e1000g_alloc_dma_resources(struct e1000g *Adapter); 1050 void e1000g_release_dma_resources(struct e1000g *Adapter); 1051 void e1000g_free_rx_sw_packet(p_rx_sw_packet_t packet, boolean_t full_release); 1052 void e1000g_tx_setup(struct e1000g *Adapter); 1053 void e1000g_rx_setup(struct e1000g *Adapter); 1054 int e1000g_increase_rx_packets(e1000g_rx_data_t *rx_data); 1055 1056 int e1000g_recycle(e1000g_tx_ring_t *tx_ring); 1057 void e1000g_free_tx_swpkt(p_tx_sw_packet_t packet); 1058 void e1000g_tx_freemsg(e1000g_tx_ring_t *tx_ring); 1059 uint_t e1000g_tx_softint_worker(caddr_t arg1, caddr_t arg2); 1060 mblk_t *e1000g_m_tx(void *arg, mblk_t *mp); 1061 mblk_t *e1000g_receive(e1000g_rx_ring_t *rx_ring, mblk_t **tail, uint_t sz); 1062 void e1000g_rxfree_func(p_rx_sw_packet_t packet); 1063 1064 int e1000g_m_stat(void *arg, uint_t stat, uint64_t *val); 1065 int e1000g_init_stats(struct e1000g *Adapter); 1066 int e1000g_rx_ring_stat(mac_ring_driver_t, uint_t, uint64_t *); 1067 void e1000_tbi_adjust_stats(struct e1000g *Adapter, 1068 uint32_t frame_len, uint8_t *mac_addr); 1069 1070 void e1000g_clear_interrupt(struct e1000g *Adapter); 1071 void e1000g_mask_interrupt(struct e1000g *Adapter); 1072 void e1000g_clear_all_interrupts(struct e1000g *Adapter); 1073 void e1000g_clear_tx_interrupt(struct e1000g *Adapter); 1074 void e1000g_mask_tx_interrupt(struct e1000g *Adapter); 1075 void phy_spd_state(struct e1000_hw *hw, boolean_t enable); 1076 void e1000_destroy_hw_mutex(struct e1000_hw *hw); 1077 void e1000_enable_pciex_master(struct e1000_hw *hw); 1078 int e1000g_check_acc_handle(ddi_acc_handle_t handle); 1079 int e1000g_check_dma_handle(ddi_dma_handle_t handle); 1080 void e1000g_fm_ereport(struct e1000g *Adapter, char *detail); 1081 void e1000g_set_fma_flags(int dma_flag); 1082 int e1000g_reset_link(struct e1000g *Adapter); 1083 1084 /* 1085 * Functions for working around various problems, these used to be from the 1086 * common code. 1087 */ 1088 s32 e1000_fifo_workaround_82547(struct e1000_hw *hw, u16 length); 1089 void e1000_update_tx_fifo_head_82547(struct e1000_hw *hw, u32 length); 1090 void e1000_set_ttl_workaround_state_82541(struct e1000_hw *hw, bool state); 1091 bool e1000_ttl_workaround_enabled_82541(struct e1000_hw *hw); 1092 s32 e1000_igp_ttl_workaround_82547(struct e1000_hw *hw); 1093 1094 /* 1095 * I219 specific workarounds 1096 */ 1097 #define PCICFG_DESC_RING_STATUS 0xe4 1098 #define FLUSH_DESC_REQUIRED 0x100 1099 extern void e1000g_flush_rx_ring(struct e1000g *); 1100 extern void e1000g_flush_tx_ring(struct e1000g *); 1101 1102 /* 1103 * Global variables 1104 */ 1105 extern boolean_t e1000g_force_detach; 1106 extern uint32_t e1000g_mblks_pending; 1107 extern kmutex_t e1000g_rx_detach_lock; 1108 extern private_devi_list_t *e1000g_private_devi_list; 1109 extern int e1000g_poll_mode; 1110 1111 #ifdef __cplusplus 1112 } 1113 #endif 1114 1115 #endif /* _E1000G_SW_H */ 1116