1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_rx.c * 31 * * 32 * Abstract: * 33 * This file contains some routines that take care of Receive * 34 * interrupt and also for the received packets it sends up to * 35 * upper layer. * 36 * It tries to do a zero copy if free buffers are available in * 37 * the pool. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include "e1000g_sw.h" 43 #include "e1000g_debug.h" 44 45 static p_rx_sw_packet_t e1000g_get_buf(e1000g_rx_ring_t *rx_ring); 46 #pragma inline(e1000g_get_buf) 47 static void e1000g_priv_devi_list_clean(); 48 49 /* 50 * e1000g_rxfree_func - the call-back function to reclaim rx buffer 51 * 52 * This function is called when an mp is freed by the user thru 53 * freeb call (Only for mp constructed through desballoc call) 54 * It returns back the freed buffer to the freelist 55 */ 56 void 57 e1000g_rxfree_func(p_rx_sw_packet_t packet) 58 { 59 e1000g_rx_ring_t *rx_ring; 60 61 rx_ring = (e1000g_rx_ring_t *)(uintptr_t)packet->rx_ring; 62 63 /* 64 * Here the rx recycling processes different rx packets in different 65 * threads, so we protect it with RW_READER to ensure it won't block 66 * other rx recycling threads. 67 */ 68 rw_enter(&e1000g_rx_detach_lock, RW_READER); 69 70 if (packet->flag == E1000G_RX_SW_FREE) { 71 rw_exit(&e1000g_rx_detach_lock); 72 return; 73 } 74 75 if (packet->flag == E1000G_RX_SW_STOP) { 76 packet->flag = E1000G_RX_SW_FREE; 77 rw_exit(&e1000g_rx_detach_lock); 78 79 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 80 rx_ring->pending_count--; 81 e1000g_mblks_pending--; 82 83 if (rx_ring->pending_count == 0) { 84 while (rx_ring->pending_list != NULL) { 85 packet = rx_ring->pending_list; 86 rx_ring->pending_list = 87 rx_ring->pending_list->next; 88 89 ASSERT(packet->mp == NULL); 90 e1000g_free_rx_sw_packet(packet); 91 } 92 } 93 94 /* 95 * If e1000g_force_detach is enabled, we need to clean up 96 * the idle priv_dip entries in the private dip list while 97 * e1000g_mblks_pending is zero. 98 */ 99 if (e1000g_force_detach && (e1000g_mblks_pending == 0)) 100 e1000g_priv_devi_list_clean(); 101 rw_exit(&e1000g_rx_detach_lock); 102 return; 103 } 104 105 if (packet->flag == E1000G_RX_SW_DETACH) { 106 packet->flag = E1000G_RX_SW_FREE; 107 rw_exit(&e1000g_rx_detach_lock); 108 109 ASSERT(packet->mp == NULL); 110 e1000g_free_rx_sw_packet(packet); 111 112 /* 113 * Here the e1000g_mblks_pending may be modified by different 114 * rx recycling threads simultaneously, so we need to protect 115 * it with RW_WRITER. 116 */ 117 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 118 e1000g_mblks_pending--; 119 120 /* 121 * If e1000g_force_detach is enabled, we need to clean up 122 * the idle priv_dip entries in the private dip list while 123 * e1000g_mblks_pending is zero. 124 */ 125 if (e1000g_force_detach && (e1000g_mblks_pending == 0)) 126 e1000g_priv_devi_list_clean(); 127 rw_exit(&e1000g_rx_detach_lock); 128 return; 129 } 130 131 packet->flag = E1000G_RX_SW_FREE; 132 133 if (packet->mp == NULL) { 134 /* 135 * Allocate a mblk that binds to the data buffer 136 */ 137 packet->mp = desballoc((unsigned char *) 138 packet->rx_buf->address - E1000G_IPALIGNROOM, 139 packet->rx_buf->size + E1000G_IPALIGNROOM, 140 BPRI_MED, &packet->free_rtn); 141 142 if (packet->mp != NULL) { 143 packet->mp->b_rptr += E1000G_IPALIGNROOM; 144 packet->mp->b_wptr += E1000G_IPALIGNROOM; 145 } else { 146 E1000G_STAT(rx_ring->stat_esballoc_fail); 147 } 148 } 149 150 mutex_enter(&rx_ring->freelist_lock); 151 QUEUE_PUSH_TAIL(&rx_ring->free_list, &packet->Link); 152 rx_ring->avail_freepkt++; 153 mutex_exit(&rx_ring->freelist_lock); 154 155 rw_exit(&e1000g_rx_detach_lock); 156 } 157 158 /* 159 * e1000g_priv_devi_list_clean - clean up e1000g_private_devi_list 160 * 161 * We will walk the e1000g_private_devi_list to free the entry marked 162 * with the E1000G_PRIV_DEVI_DETACH flag. 163 */ 164 static void 165 e1000g_priv_devi_list_clean() 166 { 167 private_devi_list_t *devi_node, *devi_del; 168 169 if (e1000g_private_devi_list == NULL) 170 return; 171 172 devi_node = e1000g_private_devi_list; 173 while ((devi_node != NULL) && 174 (devi_node->flag == E1000G_PRIV_DEVI_DETACH)) { 175 e1000g_private_devi_list = devi_node->next; 176 kmem_free(devi_node->priv_dip, 177 sizeof (struct dev_info)); 178 kmem_free(devi_node, 179 sizeof (private_devi_list_t)); 180 devi_node = e1000g_private_devi_list; 181 } 182 if (e1000g_private_devi_list == NULL) 183 return; 184 while (devi_node->next != NULL) { 185 if (devi_node->next->flag == E1000G_PRIV_DEVI_DETACH) { 186 devi_del = devi_node->next; 187 devi_node->next = devi_del->next; 188 kmem_free(devi_del->priv_dip, 189 sizeof (struct dev_info)); 190 kmem_free(devi_del, 191 sizeof (private_devi_list_t)); 192 } else { 193 devi_node = devi_node->next; 194 } 195 } 196 } 197 198 /* 199 * e1000g_rx_setup - setup rx data structures 200 * 201 * This routine initializes all of the receive related 202 * structures. This includes the receive descriptors, the 203 * actual receive buffers, and the rx_sw_packet software 204 * structures. 205 */ 206 void 207 e1000g_rx_setup(struct e1000g *Adapter) 208 { 209 struct e1000_hw *hw; 210 p_rx_sw_packet_t packet; 211 struct e1000_rx_desc *descriptor; 212 uint32_t buf_low; 213 uint32_t buf_high; 214 uint32_t reg_val; 215 int i; 216 int size; 217 e1000g_rx_ring_t *rx_ring; 218 219 hw = &Adapter->shared; 220 rx_ring = Adapter->rx_ring; 221 222 /* 223 * zero out all of the receive buffer descriptor memory 224 * assures any previous data or status is erased 225 */ 226 bzero(rx_ring->rbd_area, 227 sizeof (struct e1000_rx_desc) * Adapter->rx_desc_num); 228 229 if (!Adapter->rx_buffer_setup) { 230 /* Init the list of "Receive Buffer" */ 231 QUEUE_INIT_LIST(&rx_ring->recv_list); 232 233 /* Init the list of "Free Receive Buffer" */ 234 QUEUE_INIT_LIST(&rx_ring->free_list); 235 236 /* 237 * Setup Receive list and the Free list. Note that 238 * the both were allocated in one packet area. 239 */ 240 packet = rx_ring->packet_area; 241 descriptor = rx_ring->rbd_first; 242 243 for (i = 0; i < Adapter->rx_desc_num; 244 i++, packet = packet->next, descriptor++) { 245 ASSERT(packet != NULL); 246 ASSERT(descriptor != NULL); 247 descriptor->buffer_addr = 248 packet->rx_buf->dma_address; 249 250 /* Add this rx_sw_packet to the receive list */ 251 QUEUE_PUSH_TAIL(&rx_ring->recv_list, 252 &packet->Link); 253 } 254 255 for (i = 0; i < Adapter->rx_freelist_num; 256 i++, packet = packet->next) { 257 ASSERT(packet != NULL); 258 /* Add this rx_sw_packet to the free list */ 259 QUEUE_PUSH_TAIL(&rx_ring->free_list, 260 &packet->Link); 261 } 262 rx_ring->avail_freepkt = Adapter->rx_freelist_num; 263 264 Adapter->rx_buffer_setup = B_TRUE; 265 } else { 266 /* Setup the initial pointer to the first rx descriptor */ 267 packet = (p_rx_sw_packet_t) 268 QUEUE_GET_HEAD(&rx_ring->recv_list); 269 descriptor = rx_ring->rbd_first; 270 271 for (i = 0; i < Adapter->rx_desc_num; i++) { 272 ASSERT(packet != NULL); 273 ASSERT(descriptor != NULL); 274 descriptor->buffer_addr = 275 packet->rx_buf->dma_address; 276 277 /* Get next rx_sw_packet */ 278 packet = (p_rx_sw_packet_t) 279 QUEUE_GET_NEXT(&rx_ring->recv_list, &packet->Link); 280 descriptor++; 281 } 282 } 283 284 E1000_WRITE_REG(&Adapter->shared, E1000_RDTR, Adapter->rx_intr_delay); 285 E1000G_DEBUGLOG_1(Adapter, E1000G_INFO_LEVEL, 286 "E1000_RDTR: 0x%x\n", Adapter->rx_intr_delay); 287 if (hw->mac.type >= e1000_82540) { 288 E1000_WRITE_REG(&Adapter->shared, E1000_RADV, 289 Adapter->rx_intr_abs_delay); 290 E1000G_DEBUGLOG_1(Adapter, E1000G_INFO_LEVEL, 291 "E1000_RADV: 0x%x\n", Adapter->rx_intr_abs_delay); 292 } 293 294 /* 295 * Setup our descriptor pointers 296 */ 297 rx_ring->rbd_next = rx_ring->rbd_first; 298 299 size = Adapter->rx_desc_num * sizeof (struct e1000_rx_desc); 300 E1000_WRITE_REG(hw, E1000_RDLEN(0), size); 301 size = E1000_READ_REG(hw, E1000_RDLEN(0)); 302 303 /* To get lower order bits */ 304 buf_low = (uint32_t)rx_ring->rbd_dma_addr; 305 /* To get the higher order bits */ 306 buf_high = (uint32_t)(rx_ring->rbd_dma_addr >> 32); 307 308 E1000_WRITE_REG(hw, E1000_RDBAH(0), buf_high); 309 E1000_WRITE_REG(hw, E1000_RDBAL(0), buf_low); 310 311 /* 312 * Setup our HW Rx Head & Tail descriptor pointers 313 */ 314 E1000_WRITE_REG(hw, E1000_RDT(0), 315 (uint32_t)(rx_ring->rbd_last - rx_ring->rbd_first)); 316 E1000_WRITE_REG(hw, E1000_RDH(0), 0); 317 318 /* 319 * Setup the Receive Control Register (RCTL), and ENABLE the 320 * receiver. The initial configuration is to: Enable the receiver, 321 * accept broadcasts, discard bad packets (and long packets), 322 * disable VLAN filter checking, set the receive descriptor 323 * minimum threshold size to 1/2, and the receive buffer size to 324 * 2k. 325 */ 326 reg_val = E1000_RCTL_EN | /* Enable Receive Unit */ 327 E1000_RCTL_BAM | /* Accept Broadcast Packets */ 328 E1000_RCTL_LPE | /* Large Packet Enable bit */ 329 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT) | 330 E1000_RCTL_RDMTS_HALF | 331 E1000_RCTL_LBM_NO; /* Loopback Mode = none */ 332 333 if (Adapter->strip_crc) 334 reg_val |= E1000_RCTL_SECRC; /* Strip Ethernet CRC */ 335 336 if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_2K) && 337 (Adapter->max_frame_size <= FRAME_SIZE_UPTO_4K)) 338 reg_val |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX; 339 else if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_4K) && 340 (Adapter->max_frame_size <= FRAME_SIZE_UPTO_8K)) 341 reg_val |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX; 342 else if ((Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) && 343 (Adapter->max_frame_size <= FRAME_SIZE_UPTO_16K)) 344 reg_val |= E1000_RCTL_SZ_16384 | E1000_RCTL_BSEX; 345 else 346 reg_val |= E1000_RCTL_SZ_2048; 347 348 if (e1000_tbi_sbp_enabled_82543(hw)) 349 reg_val |= E1000_RCTL_SBP; 350 351 /* 352 * Enable early receives on supported devices, only takes effect when 353 * packet size is equal or larger than the specified value (in 8 byte 354 * units), e.g. using jumbo frames when setting to E1000_ERT_2048 355 */ 356 if ((hw->mac.type == e1000_82573) || (hw->mac.type == e1000_ich9lan)) 357 E1000_WRITE_REG(hw, E1000_ERT, E1000_ERT_2048); 358 359 E1000_WRITE_REG(hw, E1000_RCTL, reg_val); 360 361 reg_val = 362 E1000_RXCSUM_TUOFL | /* TCP/UDP checksum offload Enable */ 363 E1000_RXCSUM_IPOFL; /* IP checksum offload Enable */ 364 365 E1000_WRITE_REG(hw, E1000_RXCSUM, reg_val); 366 367 /* 368 * Workaround: Set bit 16 (IPv6_ExDIS) to disable the 369 * processing of received IPV6 extension headers 370 */ 371 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) { 372 reg_val = E1000_READ_REG(hw, E1000_RFCTL); 373 reg_val |= (E1000_RFCTL_IPV6_EX_DIS | 374 E1000_RFCTL_NEW_IPV6_EXT_DIS); 375 E1000_WRITE_REG(hw, E1000_RFCTL, reg_val); 376 } 377 } 378 379 /* 380 * e1000g_get_buf - get an rx sw packet from the free_list 381 */ 382 static p_rx_sw_packet_t 383 e1000g_get_buf(e1000g_rx_ring_t *rx_ring) 384 { 385 p_rx_sw_packet_t packet; 386 387 mutex_enter(&rx_ring->freelist_lock); 388 packet = (p_rx_sw_packet_t) 389 QUEUE_POP_HEAD(&rx_ring->free_list); 390 if (packet != NULL) 391 rx_ring->avail_freepkt--; 392 mutex_exit(&rx_ring->freelist_lock); 393 394 return (packet); 395 } 396 397 /* 398 * e1000g_receive - main receive routine 399 * 400 * This routine will process packets received in an interrupt 401 */ 402 mblk_t * 403 e1000g_receive(struct e1000g *Adapter) 404 { 405 struct e1000_hw *hw; 406 mblk_t *nmp; 407 mblk_t *ret_mp; 408 mblk_t *ret_nmp; 409 struct e1000_rx_desc *current_desc; 410 struct e1000_rx_desc *last_desc; 411 p_rx_sw_packet_t packet; 412 p_rx_sw_packet_t newpkt; 413 USHORT length; 414 uint32_t pkt_count; 415 uint32_t desc_count; 416 boolean_t accept_frame; 417 boolean_t end_of_packet; 418 boolean_t need_copy; 419 e1000g_rx_ring_t *rx_ring; 420 dma_buffer_t *rx_buf; 421 uint16_t cksumflags; 422 423 ret_mp = NULL; 424 ret_nmp = NULL; 425 pkt_count = 0; 426 desc_count = 0; 427 cksumflags = 0; 428 429 hw = &Adapter->shared; 430 rx_ring = Adapter->rx_ring; 431 432 /* Sync the Rx descriptor DMA buffers */ 433 (void) ddi_dma_sync(rx_ring->rbd_dma_handle, 434 0, 0, DDI_DMA_SYNC_FORKERNEL); 435 436 if (e1000g_check_dma_handle(rx_ring->rbd_dma_handle) != DDI_FM_OK) { 437 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 438 Adapter->chip_state = E1000G_ERROR; 439 } 440 441 current_desc = rx_ring->rbd_next; 442 if (!(current_desc->status & E1000_RXD_STAT_DD)) { 443 /* 444 * don't send anything up. just clear the RFD 445 */ 446 E1000G_DEBUG_STAT(rx_ring->stat_none); 447 return (ret_mp); 448 } 449 450 /* 451 * Loop through the receive descriptors starting at the last known 452 * descriptor owned by the hardware that begins a packet. 453 */ 454 while ((current_desc->status & E1000_RXD_STAT_DD) && 455 (pkt_count < Adapter->rx_limit_onintr)) { 456 457 desc_count++; 458 /* 459 * Now this can happen in Jumbo frame situation. 460 */ 461 if (current_desc->status & E1000_RXD_STAT_EOP) { 462 /* packet has EOP set */ 463 end_of_packet = B_TRUE; 464 } else { 465 /* 466 * If this received buffer does not have the 467 * End-Of-Packet bit set, the received packet 468 * will consume multiple buffers. We won't send this 469 * packet upstack till we get all the related buffers. 470 */ 471 end_of_packet = B_FALSE; 472 } 473 474 /* 475 * Get a pointer to the actual receive buffer 476 * The mp->b_rptr is mapped to The CurrentDescriptor 477 * Buffer Address. 478 */ 479 packet = 480 (p_rx_sw_packet_t)QUEUE_GET_HEAD(&rx_ring->recv_list); 481 ASSERT(packet != NULL); 482 483 rx_buf = packet->rx_buf; 484 485 length = current_desc->length; 486 487 #ifdef __sparc 488 if (packet->dma_type == USE_DVMA) 489 dvma_sync(rx_buf->dma_handle, 0, 490 DDI_DMA_SYNC_FORKERNEL); 491 else 492 (void) ddi_dma_sync(rx_buf->dma_handle, 493 E1000G_IPALIGNROOM, length, 494 DDI_DMA_SYNC_FORKERNEL); 495 #else 496 (void) ddi_dma_sync(rx_buf->dma_handle, 497 E1000G_IPALIGNROOM, length, 498 DDI_DMA_SYNC_FORKERNEL); 499 #endif 500 501 if (e1000g_check_dma_handle( 502 rx_buf->dma_handle) != DDI_FM_OK) { 503 ddi_fm_service_impact(Adapter->dip, 504 DDI_SERVICE_DEGRADED); 505 Adapter->chip_state = E1000G_ERROR; 506 } 507 508 accept_frame = (current_desc->errors == 0) || 509 ((current_desc->errors & 510 (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) != 0); 511 512 if (hw->mac.type == e1000_82543) { 513 unsigned char last_byte; 514 515 last_byte = 516 *((unsigned char *)rx_buf->address + length - 1); 517 518 if (TBI_ACCEPT(hw, 519 current_desc->status, current_desc->errors, 520 current_desc->length, last_byte, 521 Adapter->min_frame_size, Adapter->max_frame_size)) { 522 523 e1000_tbi_adjust_stats(Adapter, 524 length, hw->mac.addr); 525 526 length--; 527 accept_frame = B_TRUE; 528 } else if (e1000_tbi_sbp_enabled_82543(hw) && 529 (current_desc->errors == E1000_RXD_ERR_CE)) { 530 accept_frame = B_TRUE; 531 } 532 } 533 534 /* 535 * Indicate the packet to the NOS if it was good. 536 * Normally, hardware will discard bad packets for us. 537 * Check for the packet to be a valid Ethernet packet 538 */ 539 if (!accept_frame) { 540 /* 541 * error in incoming packet, either the packet is not a 542 * ethernet size packet, or the packet has an error. In 543 * either case, the packet will simply be discarded. 544 */ 545 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 546 "Process Receive Interrupts: Error in Packet\n"); 547 548 E1000G_STAT(rx_ring->stat_error); 549 /* 550 * Returning here as we are done here. There is 551 * no point in waiting for while loop to elapse 552 * and the things which were done. More efficient 553 * and less error prone... 554 */ 555 goto rx_drop; 556 } 557 558 /* 559 * If the Ethernet CRC is not stripped by the hardware, 560 * we need to strip it before sending it up to the stack. 561 */ 562 if (end_of_packet && !Adapter->strip_crc) { 563 if (length > ETHERFCSL) { 564 length -= ETHERFCSL; 565 } else { 566 /* 567 * If the fragment is smaller than the CRC, 568 * drop this fragment, do the processing of 569 * the end of the packet. 570 */ 571 ASSERT(rx_ring->rx_mblk_tail != NULL); 572 rx_ring->rx_mblk_tail->b_wptr -= 573 ETHERFCSL - length; 574 rx_ring->rx_mblk_len -= 575 ETHERFCSL - length; 576 577 QUEUE_POP_HEAD(&rx_ring->recv_list); 578 579 goto rx_end_of_packet; 580 } 581 } 582 583 need_copy = B_TRUE; 584 585 if (length <= Adapter->rx_bcopy_thresh) 586 goto rx_copy; 587 588 /* 589 * Get the pre-constructed mblk that was associated 590 * to the receive data buffer. 591 */ 592 if (packet->mp == NULL) { 593 packet->mp = desballoc((unsigned char *) 594 rx_buf->address - E1000G_IPALIGNROOM, 595 length + E1000G_IPALIGNROOM, 596 BPRI_MED, &packet->free_rtn); 597 598 if (packet->mp != NULL) { 599 packet->mp->b_rptr += E1000G_IPALIGNROOM; 600 packet->mp->b_wptr += E1000G_IPALIGNROOM; 601 } else { 602 E1000G_STAT(rx_ring->stat_esballoc_fail); 603 } 604 } 605 606 if (packet->mp != NULL) { 607 /* 608 * We have two sets of buffer pool. One associated with 609 * the Rxdescriptors and other a freelist buffer pool. 610 * Each time we get a good packet, Try to get a buffer 611 * from the freelist pool using e1000g_get_buf. If we 612 * get free buffer, then replace the descriptor buffer 613 * address with the free buffer we just got, and pass 614 * the pre-constructed mblk upstack. (note no copying) 615 * 616 * If we failed to get a free buffer, then try to 617 * allocate a new buffer(mp) and copy the recv buffer 618 * content to our newly allocated buffer(mp). Don't 619 * disturb the desriptor buffer address. (note copying) 620 */ 621 newpkt = e1000g_get_buf(rx_ring); 622 623 if (newpkt != NULL) { 624 /* 625 * Get the mblk associated to the data, 626 * and strip it off the sw packet. 627 */ 628 nmp = packet->mp; 629 packet->mp = NULL; 630 packet->flag = E1000G_RX_SW_SENDUP; 631 632 /* 633 * Now replace old buffer with the new 634 * one we got from free list 635 * Both the RxSwPacket as well as the 636 * Receive Buffer Descriptor will now 637 * point to this new packet. 638 */ 639 packet = newpkt; 640 641 current_desc->buffer_addr = 642 newpkt->rx_buf->dma_address; 643 644 need_copy = B_FALSE; 645 } else { 646 E1000G_DEBUG_STAT(rx_ring->stat_no_freepkt); 647 } 648 } 649 650 rx_copy: 651 if (need_copy) { 652 /* 653 * No buffers available on free list, 654 * bcopy the data from the buffer and 655 * keep the original buffer. Dont want to 656 * do this.. Yack but no other way 657 */ 658 if ((nmp = allocb(length + E1000G_IPALIGNROOM, 659 BPRI_MED)) == NULL) { 660 /* 661 * The system has no buffers available 662 * to send up the incoming packet, hence 663 * the packet will have to be processed 664 * when there're more buffers available. 665 */ 666 E1000G_STAT(rx_ring->stat_allocb_fail); 667 goto rx_drop; 668 } 669 nmp->b_rptr += E1000G_IPALIGNROOM; 670 nmp->b_wptr += E1000G_IPALIGNROOM; 671 /* 672 * The free list did not have any buffers 673 * available, so, the received packet will 674 * have to be copied into a mp and the original 675 * buffer will have to be retained for future 676 * packet reception. 677 */ 678 bcopy(rx_buf->address, nmp->b_wptr, length); 679 } 680 681 /* 682 * The rx_sw_packet MUST be popped off the 683 * RxSwPacketList before either a putnext or freemsg 684 * is done on the mp that has now been created by the 685 * desballoc. If not, it is possible that the free 686 * routine will get called from the interrupt context 687 * and try to put this packet on the free list 688 */ 689 (p_rx_sw_packet_t)QUEUE_POP_HEAD(&rx_ring->recv_list); 690 691 ASSERT(nmp != NULL); 692 nmp->b_wptr += length; 693 694 if (rx_ring->rx_mblk == NULL) { 695 /* 696 * TCP/UDP checksum offload and 697 * IP checksum offload 698 */ 699 if (!(current_desc->status & E1000_RXD_STAT_IXSM)) { 700 /* 701 * Check TCP/UDP checksum 702 */ 703 if ((current_desc->status & 704 E1000_RXD_STAT_TCPCS) && 705 !(current_desc->errors & 706 E1000_RXD_ERR_TCPE)) 707 cksumflags |= HCK_FULLCKSUM | 708 HCK_FULLCKSUM_OK; 709 /* 710 * Check IP Checksum 711 */ 712 if ((current_desc->status & 713 E1000_RXD_STAT_IPCS) && 714 !(current_desc->errors & 715 E1000_RXD_ERR_IPE)) 716 cksumflags |= HCK_IPV4_HDRCKSUM; 717 } 718 } 719 720 /* 721 * We need to maintain our packet chain in the global 722 * Adapter structure, for the Rx processing can end 723 * with a fragment that has no EOP set. 724 */ 725 if (rx_ring->rx_mblk == NULL) { 726 /* Get the head of the message chain */ 727 rx_ring->rx_mblk = nmp; 728 rx_ring->rx_mblk_tail = nmp; 729 rx_ring->rx_mblk_len = length; 730 } else { /* Not the first packet */ 731 /* Continue adding buffers */ 732 rx_ring->rx_mblk_tail->b_cont = nmp; 733 rx_ring->rx_mblk_tail = nmp; 734 rx_ring->rx_mblk_len += length; 735 } 736 ASSERT(rx_ring->rx_mblk != NULL); 737 ASSERT(rx_ring->rx_mblk_tail != NULL); 738 ASSERT(rx_ring->rx_mblk_tail->b_cont == NULL); 739 740 /* 741 * Now this MP is ready to travel upwards but some more 742 * fragments are coming. 743 * We will send packet upwards as soon as we get EOP 744 * set on the packet. 745 */ 746 if (!end_of_packet) { 747 /* 748 * continue to get the next descriptor, 749 * Tail would be advanced at the end 750 */ 751 goto rx_next_desc; 752 } 753 754 rx_end_of_packet: 755 /* 756 * Found packet with EOP 757 * Process the last fragment. 758 */ 759 if (cksumflags != 0) { 760 (void) hcksum_assoc(rx_ring->rx_mblk, 761 NULL, NULL, 0, 0, 0, 0, cksumflags, 0); 762 cksumflags = 0; 763 } 764 765 /* 766 * Count packets that span multi-descriptors 767 */ 768 E1000G_DEBUG_STAT_COND(rx_ring->stat_multi_desc, 769 (rx_ring->rx_mblk->b_cont != NULL)); 770 771 /* 772 * Append to list to send upstream 773 */ 774 if (ret_mp == NULL) { 775 ret_mp = ret_nmp = rx_ring->rx_mblk; 776 } else { 777 ret_nmp->b_next = rx_ring->rx_mblk; 778 ret_nmp = rx_ring->rx_mblk; 779 } 780 ret_nmp->b_next = NULL; 781 782 rx_ring->rx_mblk = NULL; 783 rx_ring->rx_mblk_tail = NULL; 784 rx_ring->rx_mblk_len = 0; 785 786 pkt_count++; 787 788 rx_next_desc: 789 /* 790 * Zero out the receive descriptors status 791 */ 792 current_desc->status = 0; 793 794 if (current_desc == rx_ring->rbd_last) 795 rx_ring->rbd_next = rx_ring->rbd_first; 796 else 797 rx_ring->rbd_next++; 798 799 last_desc = current_desc; 800 current_desc = rx_ring->rbd_next; 801 802 /* 803 * Put the buffer that we just indicated back 804 * at the end of our list 805 */ 806 QUEUE_PUSH_TAIL(&rx_ring->recv_list, 807 &packet->Link); 808 } /* while loop */ 809 810 /* Sync the Rx descriptor DMA buffers */ 811 (void) ddi_dma_sync(rx_ring->rbd_dma_handle, 812 0, 0, DDI_DMA_SYNC_FORDEV); 813 814 /* 815 * Advance the E1000's Receive Queue #0 "Tail Pointer". 816 */ 817 E1000_WRITE_REG(hw, E1000_RDT(0), 818 (uint32_t)(last_desc - rx_ring->rbd_first)); 819 820 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 821 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 822 Adapter->chip_state = E1000G_ERROR; 823 } 824 825 Adapter->rx_pkt_cnt = pkt_count; 826 827 return (ret_mp); 828 829 rx_drop: 830 /* 831 * Zero out the receive descriptors status 832 */ 833 current_desc->status = 0; 834 835 /* Sync the Rx descriptor DMA buffers */ 836 (void) ddi_dma_sync(rx_ring->rbd_dma_handle, 837 0, 0, DDI_DMA_SYNC_FORDEV); 838 839 if (current_desc == rx_ring->rbd_last) 840 rx_ring->rbd_next = rx_ring->rbd_first; 841 else 842 rx_ring->rbd_next++; 843 844 last_desc = current_desc; 845 846 (p_rx_sw_packet_t)QUEUE_POP_HEAD(&rx_ring->recv_list); 847 848 QUEUE_PUSH_TAIL(&rx_ring->recv_list, &packet->Link); 849 /* 850 * Reclaim all old buffers already allocated during 851 * Jumbo receives.....for incomplete reception 852 */ 853 if (rx_ring->rx_mblk != NULL) { 854 freemsg(rx_ring->rx_mblk); 855 rx_ring->rx_mblk = NULL; 856 rx_ring->rx_mblk_tail = NULL; 857 rx_ring->rx_mblk_len = 0; 858 } 859 /* 860 * Advance the E1000's Receive Queue #0 "Tail Pointer". 861 */ 862 E1000_WRITE_REG(hw, E1000_RDT(0), 863 (uint32_t)(last_desc - rx_ring->rbd_first)); 864 865 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 866 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 867 Adapter->chip_state = E1000G_ERROR; 868 } 869 870 return (ret_mp); 871 } 872