1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.2.13"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 68 #pragma inline(e1000g_get_itr) 69 static int e1000g_init(struct e1000g *); 70 static int e1000g_start(struct e1000g *, boolean_t); 71 static void e1000g_stop(struct e1000g *, boolean_t); 72 static int e1000g_m_start(void *); 73 static void e1000g_m_stop(void *); 74 static int e1000g_m_promisc(void *, boolean_t); 75 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 76 static int e1000g_m_unicst(void *, const uint8_t *); 77 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 78 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 79 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 80 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 81 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 82 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 83 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 84 uint_t, const void *); 85 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 86 uint_t, uint_t, void *); 87 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 88 const void *); 89 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 90 uint_t, void *); 91 static void e1000g_init_locks(struct e1000g *); 92 static void e1000g_destroy_locks(struct e1000g *); 93 static int e1000g_identify_hardware(struct e1000g *); 94 static int e1000g_regs_map(struct e1000g *); 95 static int e1000g_set_driver_params(struct e1000g *); 96 static void e1000g_set_bufsize(struct e1000g *); 97 static int e1000g_register_mac(struct e1000g *); 98 static boolean_t e1000g_rx_drain(struct e1000g *); 99 static boolean_t e1000g_tx_drain(struct e1000g *); 100 static void e1000g_init_unicst(struct e1000g *); 101 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 102 103 /* 104 * Local routines 105 */ 106 static boolean_t e1000g_reset_adapter(struct e1000g *); 107 static void e1000g_tx_clean(struct e1000g *); 108 static void e1000g_rx_clean(struct e1000g *); 109 static void e1000g_link_timer(void *); 110 static void e1000g_local_timer(void *); 111 static boolean_t e1000g_link_check(struct e1000g *); 112 static boolean_t e1000g_stall_check(struct e1000g *); 113 static void e1000g_smartspeed(struct e1000g *); 114 static void e1000g_get_conf(struct e1000g *); 115 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 116 static void enable_watchdog_timer(struct e1000g *); 117 static void disable_watchdog_timer(struct e1000g *); 118 static void start_watchdog_timer(struct e1000g *); 119 static void restart_watchdog_timer(struct e1000g *); 120 static void stop_watchdog_timer(struct e1000g *); 121 static void stop_link_timer(struct e1000g *); 122 static void stop_82547_timer(e1000g_tx_ring_t *); 123 static void e1000g_force_speed_duplex(struct e1000g *); 124 static void e1000g_get_max_frame_size(struct e1000g *); 125 static boolean_t is_valid_mac_addr(uint8_t *); 126 static void e1000g_unattach(dev_info_t *, struct e1000g *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 154 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 155 const void *impl_data); 156 static void e1000g_fm_init(struct e1000g *Adapter); 157 static void e1000g_fm_fini(struct e1000g *Adapter); 158 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 159 static void e1000g_param_sync(struct e1000g *); 160 static void e1000g_get_driver_control(struct e1000_hw *); 161 static void e1000g_release_driver_control(struct e1000_hw *); 162 static void e1000g_restore_promisc(struct e1000g *Adapter); 163 164 mac_priv_prop_t e1000g_priv_props[] = { 165 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 166 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 167 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 168 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 169 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 170 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 171 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 172 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 173 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 174 {"_intr_adaptive", MAC_PROP_PERM_RW}, 175 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 176 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 177 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 178 {"_tx_recycle_num", MAC_PROP_PERM_RW} 179 }; 180 #define E1000G_MAX_PRIV_PROPS \ 181 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 182 183 184 static struct cb_ops cb_ws_ops = { 185 nulldev, /* cb_open */ 186 nulldev, /* cb_close */ 187 nodev, /* cb_strategy */ 188 nodev, /* cb_print */ 189 nodev, /* cb_dump */ 190 nodev, /* cb_read */ 191 nodev, /* cb_write */ 192 nodev, /* cb_ioctl */ 193 nodev, /* cb_devmap */ 194 nodev, /* cb_mmap */ 195 nodev, /* cb_segmap */ 196 nochpoll, /* cb_chpoll */ 197 ddi_prop_op, /* cb_prop_op */ 198 NULL, /* cb_stream */ 199 D_MP | D_HOTPLUG, /* cb_flag */ 200 CB_REV, /* cb_rev */ 201 nodev, /* cb_aread */ 202 nodev /* cb_awrite */ 203 }; 204 205 static struct dev_ops ws_ops = { 206 DEVO_REV, /* devo_rev */ 207 0, /* devo_refcnt */ 208 NULL, /* devo_getinfo */ 209 nulldev, /* devo_identify */ 210 nulldev, /* devo_probe */ 211 e1000g_attach, /* devo_attach */ 212 e1000g_detach, /* devo_detach */ 213 nodev, /* devo_reset */ 214 &cb_ws_ops, /* devo_cb_ops */ 215 NULL, /* devo_bus_ops */ 216 ddi_power, /* devo_power */ 217 e1000g_quiesce /* devo_quiesce */ 218 }; 219 220 static struct modldrv modldrv = { 221 &mod_driverops, /* Type of module. This one is a driver */ 222 ident, /* Discription string */ 223 &ws_ops, /* driver ops */ 224 }; 225 226 static struct modlinkage modlinkage = { 227 MODREV_1, &modldrv, NULL 228 }; 229 230 /* Access attributes for register mapping */ 231 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 232 DDI_DEVICE_ATTR_V0, 233 DDI_STRUCTURE_LE_ACC, 234 DDI_STRICTORDER_ACC, 235 DDI_FLAGERR_ACC 236 }; 237 238 #define E1000G_M_CALLBACK_FLAGS \ 239 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 240 241 static mac_callbacks_t e1000g_m_callbacks = { 242 E1000G_M_CALLBACK_FLAGS, 243 e1000g_m_stat, 244 e1000g_m_start, 245 e1000g_m_stop, 246 e1000g_m_promisc, 247 e1000g_m_multicst, 248 e1000g_m_unicst, 249 e1000g_m_tx, 250 NULL, 251 e1000g_m_ioctl, 252 e1000g_m_getcapab, 253 NULL, 254 NULL, 255 e1000g_m_setprop, 256 e1000g_m_getprop 257 }; 258 259 /* 260 * Global variables 261 */ 262 uint32_t e1000g_mblks_pending = 0; 263 /* 264 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 265 * Here we maintain a private dev_info list if e1000g_force_detach is 266 * enabled. If we force the driver to detach while there are still some 267 * rx buffers retained in the upper layer, we have to keep a copy of the 268 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 269 * structure will be freed after the driver is detached. However when we 270 * finally free those rx buffers released by the upper layer, we need to 271 * refer to the dev_info to free the dma buffers. So we save a copy of 272 * the dev_info for this purpose. On x86 platform, we assume this copy 273 * of dev_info is always valid, but on SPARC platform, it could be invalid 274 * after the system board level DR operation. For this reason, the global 275 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 276 */ 277 #ifdef __sparc 278 boolean_t e1000g_force_detach = B_FALSE; 279 #else 280 boolean_t e1000g_force_detach = B_TRUE; 281 #endif 282 private_devi_list_t *e1000g_private_devi_list = NULL; 283 284 /* 285 * The rwlock is defined to protect the whole processing of rx recycling 286 * and the rx packets release in detach processing to make them mutually 287 * exclusive. 288 * The rx recycling processes different rx packets in different threads, 289 * so it will be protected with RW_READER and it won't block any other rx 290 * recycling threads. 291 * While the detach processing will be protected with RW_WRITER to make 292 * it mutually exclusive with the rx recycling. 293 */ 294 krwlock_t e1000g_rx_detach_lock; 295 /* 296 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 297 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 298 * If there are many e1000g instances, the system may run out of DVMA 299 * resources during the initialization of the instances, then the flag will 300 * be changed to "USE_DMA". Because different e1000g instances are initialized 301 * in parallel, we need to use this lock to protect the flag. 302 */ 303 krwlock_t e1000g_dma_type_lock; 304 305 /* 306 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 307 * Based on the information from Intel, the 82546 chipset has some hardware 308 * problem. When one port is being reset and the other port is trying to 309 * access the eeprom, it could cause system hang or panic. To workaround this 310 * hardware problem, we use a global mutex to prevent such operations from 311 * happening simultaneously on different instances. This workaround is applied 312 * to all the devices supported by this driver. 313 */ 314 kmutex_t e1000g_nvm_lock; 315 316 /* 317 * Loadable module configuration entry points for the driver 318 */ 319 320 /* 321 * _init - module initialization 322 */ 323 int 324 _init(void) 325 { 326 int status; 327 328 mac_init_ops(&ws_ops, WSNAME); 329 status = mod_install(&modlinkage); 330 if (status != DDI_SUCCESS) 331 mac_fini_ops(&ws_ops); 332 else { 333 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 334 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 335 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 336 } 337 338 return (status); 339 } 340 341 /* 342 * _fini - module finalization 343 */ 344 int 345 _fini(void) 346 { 347 int status; 348 349 rw_enter(&e1000g_rx_detach_lock, RW_READER); 350 if (e1000g_mblks_pending != 0) { 351 rw_exit(&e1000g_rx_detach_lock); 352 return (EBUSY); 353 } 354 rw_exit(&e1000g_rx_detach_lock); 355 356 status = mod_remove(&modlinkage); 357 if (status == DDI_SUCCESS) { 358 mac_fini_ops(&ws_ops); 359 360 if (e1000g_force_detach) { 361 private_devi_list_t *devi_node; 362 363 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 364 while (e1000g_private_devi_list != NULL) { 365 devi_node = e1000g_private_devi_list; 366 e1000g_private_devi_list = 367 e1000g_private_devi_list->next; 368 369 kmem_free(devi_node->priv_dip, 370 sizeof (struct dev_info)); 371 kmem_free(devi_node, 372 sizeof (private_devi_list_t)); 373 } 374 rw_exit(&e1000g_rx_detach_lock); 375 } 376 377 rw_destroy(&e1000g_rx_detach_lock); 378 rw_destroy(&e1000g_dma_type_lock); 379 mutex_destroy(&e1000g_nvm_lock); 380 } 381 382 return (status); 383 } 384 385 /* 386 * _info - module information 387 */ 388 int 389 _info(struct modinfo *modinfop) 390 { 391 return (mod_info(&modlinkage, modinfop)); 392 } 393 394 /* 395 * e1000g_attach - driver attach 396 * 397 * This function is the device-specific initialization entry 398 * point. This entry point is required and must be written. 399 * The DDI_ATTACH command must be provided in the attach entry 400 * point. When attach() is called with cmd set to DDI_ATTACH, 401 * all normal kernel services (such as kmem_alloc(9F)) are 402 * available for use by the driver. 403 * 404 * The attach() function will be called once for each instance 405 * of the device on the system with cmd set to DDI_ATTACH. 406 * Until attach() succeeds, the only driver entry points which 407 * may be called are open(9E) and getinfo(9E). 408 */ 409 static int 410 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 411 { 412 struct e1000g *Adapter; 413 struct e1000_hw *hw; 414 struct e1000g_osdep *osdep; 415 int instance; 416 417 switch (cmd) { 418 default: 419 e1000g_log(NULL, CE_WARN, 420 "Unsupported command send to e1000g_attach... "); 421 return (DDI_FAILURE); 422 423 case DDI_RESUME: 424 return (e1000g_resume(devinfo)); 425 426 case DDI_ATTACH: 427 break; 428 } 429 430 /* 431 * get device instance number 432 */ 433 instance = ddi_get_instance(devinfo); 434 435 /* 436 * Allocate soft data structure 437 */ 438 Adapter = 439 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 440 441 Adapter->dip = devinfo; 442 Adapter->instance = instance; 443 Adapter->tx_ring->adapter = Adapter; 444 Adapter->rx_ring->adapter = Adapter; 445 446 hw = &Adapter->shared; 447 osdep = &Adapter->osdep; 448 hw->back = osdep; 449 osdep->adapter = Adapter; 450 451 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 452 453 /* 454 * Initialize for fma support 455 */ 456 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 457 0, 0x0f, 458 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 459 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 460 e1000g_fm_init(Adapter); 461 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 462 463 /* 464 * PCI Configure 465 */ 466 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 467 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 468 goto attach_fail; 469 } 470 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 471 472 /* 473 * Setup hardware 474 */ 475 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 476 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 477 goto attach_fail; 478 } 479 480 /* 481 * Map in the device registers. 482 */ 483 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 484 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 485 goto attach_fail; 486 } 487 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 488 489 /* 490 * Initialize driver parameters 491 */ 492 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 493 goto attach_fail; 494 } 495 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 496 497 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 498 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 499 goto attach_fail; 500 } 501 502 /* 503 * Initialize interrupts 504 */ 505 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 506 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 507 goto attach_fail; 508 } 509 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 510 511 /* 512 * Initialize mutex's for this device. 513 * Do this before enabling the interrupt handler and 514 * register the softint to avoid the condition where 515 * interrupt handler can try using uninitialized mutex 516 */ 517 e1000g_init_locks(Adapter); 518 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 519 520 /* 521 * Initialize Driver Counters 522 */ 523 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 524 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 525 goto attach_fail; 526 } 527 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 528 529 /* 530 * Initialize chip hardware and software structures 531 */ 532 if (e1000g_init(Adapter) != DDI_SUCCESS) { 533 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 534 goto attach_fail; 535 } 536 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 537 538 /* 539 * Register the driver to the MAC 540 */ 541 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 542 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 543 goto attach_fail; 544 } 545 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 546 547 /* 548 * Now that mutex locks are initialized, and the chip is also 549 * initialized, enable interrupts. 550 */ 551 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 552 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 553 goto attach_fail; 554 } 555 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 556 557 /* 558 * If e1000g_force_detach is enabled, in global private dip list, 559 * we will create a new entry, which maintains the priv_dip for DR 560 * supports after driver detached. 561 */ 562 if (e1000g_force_detach) { 563 private_devi_list_t *devi_node; 564 565 Adapter->priv_dip = 566 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 567 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 568 sizeof (struct dev_info)); 569 570 devi_node = 571 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 572 573 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 574 devi_node->priv_dip = Adapter->priv_dip; 575 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 576 devi_node->next = e1000g_private_devi_list; 577 e1000g_private_devi_list = devi_node; 578 rw_exit(&e1000g_rx_detach_lock); 579 } 580 581 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 582 583 return (DDI_SUCCESS); 584 585 attach_fail: 586 e1000g_unattach(devinfo, Adapter); 587 return (DDI_FAILURE); 588 } 589 590 static int 591 e1000g_register_mac(struct e1000g *Adapter) 592 { 593 struct e1000_hw *hw = &Adapter->shared; 594 mac_register_t *mac; 595 int err; 596 597 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 598 return (DDI_FAILURE); 599 600 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 601 mac->m_driver = Adapter; 602 mac->m_dip = Adapter->dip; 603 mac->m_src_addr = hw->mac.addr; 604 mac->m_callbacks = &e1000g_m_callbacks; 605 mac->m_min_sdu = 0; 606 mac->m_max_sdu = Adapter->default_mtu; 607 mac->m_margin = VLAN_TAGSZ; 608 mac->m_priv_props = e1000g_priv_props; 609 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 610 611 err = mac_register(mac, &Adapter->mh); 612 mac_free(mac); 613 614 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 615 } 616 617 static int 618 e1000g_identify_hardware(struct e1000g *Adapter) 619 { 620 struct e1000_hw *hw = &Adapter->shared; 621 struct e1000g_osdep *osdep = &Adapter->osdep; 622 623 /* Get the device id */ 624 hw->vendor_id = 625 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 626 hw->device_id = 627 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 628 hw->revision_id = 629 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 630 hw->subsystem_device_id = 631 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 632 hw->subsystem_vendor_id = 633 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 634 635 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 636 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 637 "MAC type could not be set properly."); 638 return (DDI_FAILURE); 639 } 640 641 return (DDI_SUCCESS); 642 } 643 644 static int 645 e1000g_regs_map(struct e1000g *Adapter) 646 { 647 dev_info_t *devinfo = Adapter->dip; 648 struct e1000_hw *hw = &Adapter->shared; 649 struct e1000g_osdep *osdep = &Adapter->osdep; 650 off_t mem_size; 651 652 /* Get size of adapter register memory */ 653 if (ddi_dev_regsize(devinfo, ADAPTER_REG_SET, &mem_size) != 654 DDI_SUCCESS) { 655 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 656 "ddi_dev_regsize for registers failed"); 657 return (DDI_FAILURE); 658 } 659 660 /* Map adapter register memory */ 661 if ((ddi_regs_map_setup(devinfo, ADAPTER_REG_SET, 662 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 663 &osdep->reg_handle)) != DDI_SUCCESS) { 664 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 665 "ddi_regs_map_setup for registers failed"); 666 goto regs_map_fail; 667 } 668 669 /* ICH needs to map flash memory */ 670 if (hw->mac.type == e1000_ich8lan || 671 hw->mac.type == e1000_ich9lan || 672 hw->mac.type == e1000_ich10lan) { 673 /* get flash size */ 674 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 675 &mem_size) != DDI_SUCCESS) { 676 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 677 "ddi_dev_regsize for ICH flash failed"); 678 goto regs_map_fail; 679 } 680 681 /* map flash in */ 682 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 683 (caddr_t *)&hw->flash_address, 0, 684 mem_size, &e1000g_regs_acc_attr, 685 &osdep->ich_flash_handle) != DDI_SUCCESS) { 686 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 687 "ddi_regs_map_setup for ICH flash failed"); 688 goto regs_map_fail; 689 } 690 } 691 692 return (DDI_SUCCESS); 693 694 regs_map_fail: 695 if (osdep->reg_handle != NULL) 696 ddi_regs_map_free(&osdep->reg_handle); 697 698 return (DDI_FAILURE); 699 } 700 701 static int 702 e1000g_set_driver_params(struct e1000g *Adapter) 703 { 704 struct e1000_hw *hw; 705 uint32_t mem_bar, io_bar, bar64; 706 707 hw = &Adapter->shared; 708 709 /* Set MAC type and initialize hardware functions */ 710 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 711 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 712 "Could not setup hardware functions"); 713 return (DDI_FAILURE); 714 } 715 716 /* Get bus information */ 717 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 718 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 719 "Could not get bus information"); 720 return (DDI_FAILURE); 721 } 722 723 /* get mem_base addr */ 724 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 725 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 726 727 /* get io_base addr */ 728 if (hw->mac.type >= e1000_82544) { 729 if (bar64) { 730 /* IO BAR is different for 64 bit BAR mode */ 731 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 732 PCI_CONF_BASE4); 733 } else { 734 /* normal 32-bit BAR mode */ 735 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 736 PCI_CONF_BASE2); 737 } 738 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 739 } else { 740 /* no I/O access for adapters prior to 82544 */ 741 hw->io_base = 0x0; 742 } 743 744 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 745 746 hw->mac.autoneg_failed = B_TRUE; 747 748 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 749 hw->phy.autoneg_wait_to_complete = B_FALSE; 750 751 /* Adaptive IFS related changes */ 752 hw->mac.adaptive_ifs = B_TRUE; 753 754 /* Enable phy init script for IGP phy of 82541/82547 */ 755 if ((hw->mac.type == e1000_82547) || 756 (hw->mac.type == e1000_82541) || 757 (hw->mac.type == e1000_82547_rev_2) || 758 (hw->mac.type == e1000_82541_rev_2)) 759 e1000_init_script_state_82541(hw, B_TRUE); 760 761 /* Enable the TTL workaround for 82541/82547 */ 762 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 763 764 #ifdef __sparc 765 Adapter->strip_crc = B_TRUE; 766 #else 767 Adapter->strip_crc = B_FALSE; 768 #endif 769 770 /* Get conf file properties */ 771 e1000g_get_conf(Adapter); 772 773 /* Get speed/duplex settings in conf file */ 774 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 775 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 776 e1000g_force_speed_duplex(Adapter); 777 778 /* Get Jumbo Frames settings in conf file */ 779 e1000g_get_max_frame_size(Adapter); 780 781 /* Set Rx/Tx buffer size */ 782 e1000g_set_bufsize(Adapter); 783 784 /* Master Latency Timer */ 785 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 786 787 /* copper options */ 788 if (hw->phy.media_type == e1000_media_type_copper) { 789 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 790 hw->phy.disable_polarity_correction = B_FALSE; 791 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 792 } 793 794 /* The initial link state should be "unknown" */ 795 Adapter->link_state = LINK_STATE_UNKNOWN; 796 797 /* Initialize rx parameters */ 798 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 799 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 800 801 /* Initialize tx parameters */ 802 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 803 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 804 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 805 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 806 807 /* Initialize rx parameters */ 808 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 809 810 return (DDI_SUCCESS); 811 } 812 813 static void 814 e1000g_set_bufsize(struct e1000g *Adapter) 815 { 816 struct e1000_mac_info *mac = &Adapter->shared.mac; 817 uint64_t rx_size; 818 uint64_t tx_size; 819 820 #ifdef __sparc 821 dev_info_t *devinfo = Adapter->dip; 822 ulong_t iommu_pagesize; 823 824 /* Get the system page size */ 825 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 826 iommu_pagesize = dvma_pagesize(devinfo); 827 if (iommu_pagesize != 0) { 828 if (Adapter->sys_page_sz == iommu_pagesize) { 829 if (iommu_pagesize > 0x4000) 830 Adapter->sys_page_sz = 0x4000; 831 } else { 832 if (Adapter->sys_page_sz > iommu_pagesize) 833 Adapter->sys_page_sz = iommu_pagesize; 834 } 835 } 836 if (Adapter->lso_enable) { 837 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 838 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 839 } else { 840 Adapter->dvma_page_num = Adapter->max_frame_size / 841 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 842 } 843 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 844 #endif 845 846 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 847 848 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 849 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 850 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 851 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 852 (rx_size <= FRAME_SIZE_UPTO_8K)) 853 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 854 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 855 (rx_size <= FRAME_SIZE_UPTO_16K)) 856 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 857 else 858 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 859 860 tx_size = Adapter->max_frame_size; 861 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 862 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 863 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 864 (tx_size <= FRAME_SIZE_UPTO_8K)) 865 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 866 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 867 (tx_size <= FRAME_SIZE_UPTO_16K)) 868 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 869 else 870 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 871 872 /* 873 * For Wiseman adapters we have an requirement of having receive 874 * buffers aligned at 256 byte boundary. Since Livengood does not 875 * require this and forcing it for all hardwares will have 876 * performance implications, I am making it applicable only for 877 * Wiseman and for Jumbo frames enabled mode as rest of the time, 878 * it is okay to have normal frames...but it does involve a 879 * potential risk where we may loose data if buffer is not 880 * aligned...so all wiseman boards to have 256 byte aligned 881 * buffers 882 */ 883 if (mac->type < e1000_82543) 884 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 885 else 886 Adapter->rx_buf_align = 1; 887 } 888 889 /* 890 * e1000g_detach - driver detach 891 * 892 * The detach() function is the complement of the attach routine. 893 * If cmd is set to DDI_DETACH, detach() is used to remove the 894 * state associated with a given instance of a device node 895 * prior to the removal of that instance from the system. 896 * 897 * The detach() function will be called once for each instance 898 * of the device for which there has been a successful attach() 899 * once there are no longer any opens on the device. 900 * 901 * Interrupts routine are disabled, All memory allocated by this 902 * driver are freed. 903 */ 904 static int 905 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 906 { 907 struct e1000g *Adapter; 908 boolean_t rx_drain; 909 910 switch (cmd) { 911 default: 912 return (DDI_FAILURE); 913 914 case DDI_SUSPEND: 915 return (e1000g_suspend(devinfo)); 916 917 case DDI_DETACH: 918 break; 919 } 920 921 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 922 if (Adapter == NULL) 923 return (DDI_FAILURE); 924 925 if (mac_unregister(Adapter->mh) != 0) { 926 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 927 return (DDI_FAILURE); 928 } 929 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 930 931 932 if (Adapter->chip_state != E1000G_STOP) 933 e1000g_stop(Adapter, B_TRUE); 934 935 rx_drain = e1000g_rx_drain(Adapter); 936 937 /* 938 * If e1000g_force_detach is enabled, driver detach is safe. 939 * We will let e1000g_free_priv_devi_node routine determine 940 * whether we need to free the priv_dip entry for current 941 * driver instance. 942 */ 943 if (e1000g_force_detach) { 944 e1000g_free_priv_devi_node(Adapter, rx_drain); 945 } else { 946 if (!rx_drain) 947 return (DDI_FAILURE); 948 } 949 950 e1000g_unattach(devinfo, Adapter); 951 952 return (DDI_SUCCESS); 953 } 954 955 /* 956 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 957 * 958 * If free_flag is true, that indicates the upper layer is not holding 959 * the rx buffers, we could free the priv_dip entry safely. 960 * 961 * Otherwise, we have to keep this entry even after driver detached, 962 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 963 * so that driver could free it while all of rx buffers are returned 964 * by upper layer later. 965 */ 966 static void 967 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 968 { 969 private_devi_list_t *devi_node, *devi_del; 970 971 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 972 ASSERT(e1000g_private_devi_list != NULL); 973 ASSERT(Adapter->priv_dip != NULL); 974 975 devi_node = e1000g_private_devi_list; 976 if (devi_node->priv_dip == Adapter->priv_dip) { 977 if (free_flag) { 978 e1000g_private_devi_list = 979 devi_node->next; 980 kmem_free(devi_node->priv_dip, 981 sizeof (struct dev_info)); 982 kmem_free(devi_node, 983 sizeof (private_devi_list_t)); 984 } else { 985 ASSERT(e1000g_mblks_pending != 0); 986 devi_node->flag = 987 E1000G_PRIV_DEVI_DETACH; 988 } 989 rw_exit(&e1000g_rx_detach_lock); 990 return; 991 } 992 993 devi_node = e1000g_private_devi_list; 994 while (devi_node->next != NULL) { 995 if (devi_node->next->priv_dip == Adapter->priv_dip) { 996 if (free_flag) { 997 devi_del = devi_node->next; 998 devi_node->next = devi_del->next; 999 kmem_free(devi_del->priv_dip, 1000 sizeof (struct dev_info)); 1001 kmem_free(devi_del, 1002 sizeof (private_devi_list_t)); 1003 } else { 1004 ASSERT(e1000g_mblks_pending != 0); 1005 devi_node->next->flag = 1006 E1000G_PRIV_DEVI_DETACH; 1007 } 1008 break; 1009 } 1010 devi_node = devi_node->next; 1011 } 1012 rw_exit(&e1000g_rx_detach_lock); 1013 } 1014 1015 static void 1016 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1017 { 1018 int result; 1019 1020 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1021 (void) e1000g_disable_intrs(Adapter); 1022 } 1023 1024 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1025 (void) mac_unregister(Adapter->mh); 1026 } 1027 1028 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1029 (void) e1000g_rem_intrs(Adapter); 1030 } 1031 1032 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1033 (void) ddi_prop_remove_all(devinfo); 1034 } 1035 1036 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1037 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1038 } 1039 1040 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1041 stop_link_timer(Adapter); 1042 1043 mutex_enter(&e1000g_nvm_lock); 1044 result = e1000_reset_hw(&Adapter->shared); 1045 mutex_exit(&e1000g_nvm_lock); 1046 1047 if (result != E1000_SUCCESS) { 1048 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1049 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1050 } 1051 } 1052 1053 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1054 if (Adapter->osdep.reg_handle != NULL) 1055 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1056 if (Adapter->osdep.ich_flash_handle != NULL) 1057 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1058 } 1059 1060 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1061 if (Adapter->osdep.cfg_handle != NULL) 1062 pci_config_teardown(&Adapter->osdep.cfg_handle); 1063 } 1064 1065 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1066 e1000g_destroy_locks(Adapter); 1067 } 1068 1069 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1070 e1000g_fm_fini(Adapter); 1071 } 1072 1073 e1000_remove_device(&Adapter->shared); 1074 1075 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1076 1077 /* 1078 * Another hotplug spec requirement, 1079 * run ddi_set_driver_private(devinfo, null); 1080 */ 1081 ddi_set_driver_private(devinfo, NULL); 1082 } 1083 1084 static void 1085 e1000g_init_locks(struct e1000g *Adapter) 1086 { 1087 e1000g_tx_ring_t *tx_ring; 1088 e1000g_rx_ring_t *rx_ring; 1089 1090 rw_init(&Adapter->chip_lock, NULL, 1091 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1092 mutex_init(&Adapter->link_lock, NULL, 1093 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1094 mutex_init(&Adapter->watchdog_lock, NULL, 1095 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1096 1097 tx_ring = Adapter->tx_ring; 1098 1099 mutex_init(&tx_ring->tx_lock, NULL, 1100 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1101 mutex_init(&tx_ring->usedlist_lock, NULL, 1102 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1103 mutex_init(&tx_ring->freelist_lock, NULL, 1104 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1105 1106 rx_ring = Adapter->rx_ring; 1107 1108 mutex_init(&rx_ring->rx_lock, NULL, 1109 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1110 mutex_init(&rx_ring->freelist_lock, NULL, 1111 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1112 } 1113 1114 static void 1115 e1000g_destroy_locks(struct e1000g *Adapter) 1116 { 1117 e1000g_tx_ring_t *tx_ring; 1118 e1000g_rx_ring_t *rx_ring; 1119 1120 tx_ring = Adapter->tx_ring; 1121 mutex_destroy(&tx_ring->tx_lock); 1122 mutex_destroy(&tx_ring->usedlist_lock); 1123 mutex_destroy(&tx_ring->freelist_lock); 1124 1125 rx_ring = Adapter->rx_ring; 1126 mutex_destroy(&rx_ring->rx_lock); 1127 mutex_destroy(&rx_ring->freelist_lock); 1128 1129 mutex_destroy(&Adapter->link_lock); 1130 mutex_destroy(&Adapter->watchdog_lock); 1131 rw_destroy(&Adapter->chip_lock); 1132 } 1133 1134 static int 1135 e1000g_resume(dev_info_t *devinfo) 1136 { 1137 struct e1000g *Adapter; 1138 1139 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1140 if (Adapter == NULL) 1141 return (DDI_FAILURE); 1142 1143 if (e1000g_start(Adapter, B_TRUE)) 1144 return (DDI_FAILURE); 1145 1146 return (DDI_SUCCESS); 1147 } 1148 1149 static int 1150 e1000g_suspend(dev_info_t *devinfo) 1151 { 1152 struct e1000g *Adapter; 1153 1154 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1155 if (Adapter == NULL) 1156 return (DDI_FAILURE); 1157 1158 e1000g_stop(Adapter, B_TRUE); 1159 1160 return (DDI_SUCCESS); 1161 } 1162 1163 static int 1164 e1000g_init(struct e1000g *Adapter) 1165 { 1166 uint32_t pba; 1167 uint32_t high_water; 1168 struct e1000_hw *hw; 1169 clock_t link_timeout; 1170 int result; 1171 1172 hw = &Adapter->shared; 1173 1174 rw_enter(&Adapter->chip_lock, RW_WRITER); 1175 1176 /* 1177 * reset to put the hardware in a known state 1178 * before we try to do anything with the eeprom 1179 */ 1180 mutex_enter(&e1000g_nvm_lock); 1181 result = e1000_reset_hw(hw); 1182 mutex_exit(&e1000g_nvm_lock); 1183 1184 if (result != E1000_SUCCESS) { 1185 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1186 goto init_fail; 1187 } 1188 1189 mutex_enter(&e1000g_nvm_lock); 1190 result = e1000_validate_nvm_checksum(hw); 1191 if (result < E1000_SUCCESS) { 1192 /* 1193 * Some PCI-E parts fail the first check due to 1194 * the link being in sleep state. Call it again, 1195 * if it fails a second time its a real issue. 1196 */ 1197 result = e1000_validate_nvm_checksum(hw); 1198 } 1199 mutex_exit(&e1000g_nvm_lock); 1200 1201 if (result < E1000_SUCCESS) { 1202 e1000g_log(Adapter, CE_WARN, 1203 "Invalid NVM checksum. Please contact " 1204 "the vendor to update the NVM."); 1205 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1206 goto init_fail; 1207 } 1208 1209 result = 0; 1210 #ifdef __sparc 1211 /* 1212 * First, we try to get the local ethernet address from OBP. If 1213 * failed, then we get it from the EEPROM of NIC card. 1214 */ 1215 result = e1000g_find_mac_address(Adapter); 1216 #endif 1217 /* Get the local ethernet address. */ 1218 if (!result) { 1219 mutex_enter(&e1000g_nvm_lock); 1220 result = e1000_read_mac_addr(hw); 1221 mutex_exit(&e1000g_nvm_lock); 1222 } 1223 1224 if (result < E1000_SUCCESS) { 1225 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1226 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1227 goto init_fail; 1228 } 1229 1230 /* check for valid mac address */ 1231 if (!is_valid_mac_addr(hw->mac.addr)) { 1232 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1233 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1234 goto init_fail; 1235 } 1236 1237 /* Set LAA state for 82571 chipset */ 1238 e1000_set_laa_state_82571(hw, B_TRUE); 1239 1240 /* Master Latency Timer implementation */ 1241 if (Adapter->master_latency_timer) { 1242 pci_config_put8(Adapter->osdep.cfg_handle, 1243 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1244 } 1245 1246 if (hw->mac.type < e1000_82547) { 1247 /* 1248 * Total FIFO is 64K 1249 */ 1250 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1251 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1252 else 1253 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1254 } else if ((hw->mac.type == e1000_82571) || 1255 (hw->mac.type == e1000_82572) || 1256 (hw->mac.type == e1000_80003es2lan)) { 1257 /* 1258 * Total FIFO is 48K 1259 */ 1260 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1261 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1262 else 1263 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1264 } else if (hw->mac.type == e1000_82573) { 1265 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1266 } else if (hw->mac.type == e1000_82574) { 1267 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1268 pba = E1000_READ_REG(hw, E1000_PBA); 1269 } else if (hw->mac.type == e1000_ich8lan) { 1270 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1271 } else if (hw->mac.type == e1000_ich9lan) { 1272 pba = E1000_PBA_10K; 1273 } else if (hw->mac.type == e1000_ich10lan) { 1274 pba = E1000_PBA_10K; 1275 } else { 1276 /* 1277 * Total FIFO is 40K 1278 */ 1279 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1280 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1281 else 1282 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1283 } 1284 E1000_WRITE_REG(hw, E1000_PBA, pba); 1285 1286 /* 1287 * These parameters set thresholds for the adapter's generation(Tx) 1288 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1289 * settings. Flow control is enabled or disabled in the configuration 1290 * file. 1291 * High-water mark is set down from the top of the rx fifo (not 1292 * sensitive to max_frame_size) and low-water is set just below 1293 * high-water mark. 1294 * The high water mark must be low enough to fit one full frame above 1295 * it in the rx FIFO. Should be the lower of: 1296 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1297 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1298 * Rx FIFO size minus one full frame. 1299 */ 1300 high_water = min(((pba << 10) * 9 / 10), 1301 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan || 1302 hw->mac.type == e1000_ich10lan) ? 1303 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1304 ((pba << 10) - Adapter->max_frame_size))); 1305 1306 hw->fc.high_water = high_water & 0xFFF8; 1307 hw->fc.low_water = hw->fc.high_water - 8; 1308 1309 if (hw->mac.type == e1000_80003es2lan) 1310 hw->fc.pause_time = 0xFFFF; 1311 else 1312 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1313 hw->fc.send_xon = B_TRUE; 1314 1315 /* 1316 * Reset the adapter hardware the second time. 1317 */ 1318 mutex_enter(&e1000g_nvm_lock); 1319 result = e1000_reset_hw(hw); 1320 mutex_exit(&e1000g_nvm_lock); 1321 1322 if (result != E1000_SUCCESS) { 1323 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1324 goto init_fail; 1325 } 1326 1327 /* disable wakeup control by default */ 1328 if (hw->mac.type >= e1000_82544) 1329 E1000_WRITE_REG(hw, E1000_WUC, 0); 1330 1331 /* MWI setup */ 1332 e1000_pci_set_mwi(hw); 1333 1334 /* 1335 * Configure/Initialize hardware 1336 */ 1337 mutex_enter(&e1000g_nvm_lock); 1338 result = e1000_init_hw(hw); 1339 mutex_exit(&e1000g_nvm_lock); 1340 1341 if (result < E1000_SUCCESS) { 1342 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1343 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1344 goto init_fail; 1345 } 1346 1347 /* 1348 * Restore LED settings to the default from EEPROM 1349 * to meet the standard for Sun platforms. 1350 */ 1351 (void) e1000_cleanup_led(hw); 1352 1353 /* Disable Smart Power Down */ 1354 phy_spd_state(hw, B_FALSE); 1355 1356 /* Make sure driver has control */ 1357 e1000g_get_driver_control(hw); 1358 1359 /* 1360 * Initialize unicast addresses. 1361 */ 1362 e1000g_init_unicst(Adapter); 1363 1364 /* 1365 * Setup and initialize the mctable structures. After this routine 1366 * completes Multicast table will be set 1367 */ 1368 e1000g_setup_multicast(Adapter); 1369 msec_delay(5); 1370 1371 /* 1372 * Implement Adaptive IFS 1373 */ 1374 e1000_reset_adaptive(hw); 1375 1376 /* Setup Interrupt Throttling Register */ 1377 if (hw->mac.type >= e1000_82540) { 1378 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1379 } else 1380 Adapter->intr_adaptive = B_FALSE; 1381 1382 /* Start the timer for link setup */ 1383 if (hw->mac.autoneg) 1384 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1385 else 1386 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1387 1388 mutex_enter(&Adapter->link_lock); 1389 if (hw->phy.autoneg_wait_to_complete) { 1390 Adapter->link_complete = B_TRUE; 1391 } else { 1392 Adapter->link_complete = B_FALSE; 1393 Adapter->link_tid = timeout(e1000g_link_timer, 1394 (void *)Adapter, link_timeout); 1395 } 1396 mutex_exit(&Adapter->link_lock); 1397 1398 /* Enable PCI-Ex master */ 1399 if (hw->bus.type == e1000_bus_type_pci_express) { 1400 e1000_enable_pciex_master(hw); 1401 } 1402 1403 /* Save the state of the phy */ 1404 e1000g_get_phy_state(Adapter); 1405 1406 e1000g_param_sync(Adapter); 1407 1408 Adapter->init_count++; 1409 1410 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1411 goto init_fail; 1412 } 1413 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1414 goto init_fail; 1415 } 1416 1417 rw_exit(&Adapter->chip_lock); 1418 1419 return (DDI_SUCCESS); 1420 1421 init_fail: 1422 rw_exit(&Adapter->chip_lock); 1423 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1424 return (DDI_FAILURE); 1425 } 1426 1427 /* 1428 * Check if the link is up 1429 */ 1430 static boolean_t 1431 e1000g_link_up(struct e1000g *Adapter) 1432 { 1433 struct e1000_hw *hw; 1434 boolean_t link_up; 1435 1436 hw = &Adapter->shared; 1437 1438 (void) e1000_check_for_link(hw); 1439 1440 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1441 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1442 ((hw->phy.media_type == e1000_media_type_internal_serdes) && 1443 (hw->mac.serdes_has_link))) { 1444 link_up = B_TRUE; 1445 } else { 1446 link_up = B_FALSE; 1447 } 1448 1449 return (link_up); 1450 } 1451 1452 static void 1453 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1454 { 1455 struct iocblk *iocp; 1456 struct e1000g *e1000gp; 1457 enum ioc_reply status; 1458 1459 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1460 iocp->ioc_error = 0; 1461 e1000gp = (struct e1000g *)arg; 1462 1463 ASSERT(e1000gp); 1464 if (e1000gp == NULL) { 1465 miocnak(q, mp, 0, EINVAL); 1466 return; 1467 } 1468 1469 switch (iocp->ioc_cmd) { 1470 1471 case LB_GET_INFO_SIZE: 1472 case LB_GET_INFO: 1473 case LB_GET_MODE: 1474 case LB_SET_MODE: 1475 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1476 break; 1477 1478 1479 #ifdef E1000G_DEBUG 1480 case E1000G_IOC_REG_PEEK: 1481 case E1000G_IOC_REG_POKE: 1482 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1483 break; 1484 case E1000G_IOC_CHIP_RESET: 1485 e1000gp->reset_count++; 1486 if (e1000g_reset_adapter(e1000gp)) 1487 status = IOC_ACK; 1488 else 1489 status = IOC_INVAL; 1490 break; 1491 #endif 1492 default: 1493 status = IOC_INVAL; 1494 break; 1495 } 1496 1497 /* 1498 * Decide how to reply 1499 */ 1500 switch (status) { 1501 default: 1502 case IOC_INVAL: 1503 /* 1504 * Error, reply with a NAK and EINVAL or the specified error 1505 */ 1506 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1507 EINVAL : iocp->ioc_error); 1508 break; 1509 1510 case IOC_DONE: 1511 /* 1512 * OK, reply already sent 1513 */ 1514 break; 1515 1516 case IOC_ACK: 1517 /* 1518 * OK, reply with an ACK 1519 */ 1520 miocack(q, mp, 0, 0); 1521 break; 1522 1523 case IOC_REPLY: 1524 /* 1525 * OK, send prepared reply as ACK or NAK 1526 */ 1527 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1528 M_IOCACK : M_IOCNAK; 1529 qreply(q, mp); 1530 break; 1531 } 1532 } 1533 1534 static int 1535 e1000g_m_start(void *arg) 1536 { 1537 struct e1000g *Adapter = (struct e1000g *)arg; 1538 1539 return (e1000g_start(Adapter, B_TRUE)); 1540 } 1541 1542 static int 1543 e1000g_start(struct e1000g *Adapter, boolean_t global) 1544 { 1545 if (global) { 1546 /* Allocate dma resources for descriptors and buffers */ 1547 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1548 e1000g_log(Adapter, CE_WARN, 1549 "Alloc DMA resources failed"); 1550 return (ENOTACTIVE); 1551 } 1552 Adapter->rx_buffer_setup = B_FALSE; 1553 } 1554 1555 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1556 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1557 e1000g_log(Adapter, CE_WARN, 1558 "Adapter initialization failed"); 1559 if (global) 1560 e1000g_release_dma_resources(Adapter); 1561 return (ENOTACTIVE); 1562 } 1563 } 1564 1565 rw_enter(&Adapter->chip_lock, RW_WRITER); 1566 1567 /* Setup and initialize the transmit structures */ 1568 e1000g_tx_setup(Adapter); 1569 msec_delay(5); 1570 1571 /* Setup and initialize the receive structures */ 1572 e1000g_rx_setup(Adapter); 1573 msec_delay(5); 1574 1575 /* Restore the e1000g promiscuous mode */ 1576 e1000g_restore_promisc(Adapter); 1577 1578 e1000g_mask_interrupt(Adapter); 1579 1580 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1581 rw_exit(&Adapter->chip_lock); 1582 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1583 return (ENOTACTIVE); 1584 } 1585 1586 Adapter->chip_state = E1000G_START; 1587 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1588 1589 rw_exit(&Adapter->chip_lock); 1590 1591 /* Enable and start the watchdog timer */ 1592 enable_watchdog_timer(Adapter); 1593 1594 return (0); 1595 } 1596 1597 static void 1598 e1000g_m_stop(void *arg) 1599 { 1600 struct e1000g *Adapter = (struct e1000g *)arg; 1601 1602 e1000g_stop(Adapter, B_TRUE); 1603 } 1604 1605 static void 1606 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1607 { 1608 int result; 1609 1610 /* Set stop flags */ 1611 rw_enter(&Adapter->chip_lock, RW_WRITER); 1612 1613 Adapter->chip_state = E1000G_STOP; 1614 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1615 1616 rw_exit(&Adapter->chip_lock); 1617 1618 /* Drain tx sessions */ 1619 (void) e1000g_tx_drain(Adapter); 1620 1621 /* Disable and stop all the timers */ 1622 disable_watchdog_timer(Adapter); 1623 stop_link_timer(Adapter); 1624 stop_82547_timer(Adapter->tx_ring); 1625 1626 /* Stop the chip and release pending resources */ 1627 rw_enter(&Adapter->chip_lock, RW_WRITER); 1628 1629 /* Tell firmware driver is no longer in control */ 1630 e1000g_release_driver_control(&Adapter->shared); 1631 1632 e1000g_clear_all_interrupts(Adapter); 1633 1634 mutex_enter(&e1000g_nvm_lock); 1635 result = e1000_reset_hw(&Adapter->shared); 1636 mutex_exit(&e1000g_nvm_lock); 1637 1638 if (result != E1000_SUCCESS) { 1639 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1640 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1641 } 1642 1643 /* Release resources still held by the TX descriptors */ 1644 e1000g_tx_clean(Adapter); 1645 1646 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1647 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1648 1649 /* Clean the pending rx jumbo packet fragment */ 1650 e1000g_rx_clean(Adapter); 1651 1652 rw_exit(&Adapter->chip_lock); 1653 1654 if (global) 1655 e1000g_release_dma_resources(Adapter); 1656 } 1657 1658 static void 1659 e1000g_rx_clean(struct e1000g *Adapter) 1660 { 1661 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1662 1663 if (rx_ring->rx_mblk != NULL) { 1664 freemsg(rx_ring->rx_mblk); 1665 rx_ring->rx_mblk = NULL; 1666 rx_ring->rx_mblk_tail = NULL; 1667 rx_ring->rx_mblk_len = 0; 1668 } 1669 } 1670 1671 static void 1672 e1000g_tx_clean(struct e1000g *Adapter) 1673 { 1674 e1000g_tx_ring_t *tx_ring; 1675 p_tx_sw_packet_t packet; 1676 mblk_t *mp; 1677 mblk_t *nmp; 1678 uint32_t packet_count; 1679 1680 tx_ring = Adapter->tx_ring; 1681 1682 /* 1683 * Here we don't need to protect the lists using 1684 * the usedlist_lock and freelist_lock, for they 1685 * have been protected by the chip_lock. 1686 */ 1687 mp = NULL; 1688 nmp = NULL; 1689 packet_count = 0; 1690 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1691 while (packet != NULL) { 1692 if (packet->mp != NULL) { 1693 /* Assemble the message chain */ 1694 if (mp == NULL) { 1695 mp = packet->mp; 1696 nmp = packet->mp; 1697 } else { 1698 nmp->b_next = packet->mp; 1699 nmp = packet->mp; 1700 } 1701 /* Disconnect the message from the sw packet */ 1702 packet->mp = NULL; 1703 } 1704 1705 e1000g_free_tx_swpkt(packet); 1706 packet_count++; 1707 1708 packet = (p_tx_sw_packet_t) 1709 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1710 } 1711 1712 if (mp != NULL) 1713 freemsgchain(mp); 1714 1715 if (packet_count > 0) { 1716 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1717 QUEUE_INIT_LIST(&tx_ring->used_list); 1718 1719 /* Setup TX descriptor pointers */ 1720 tx_ring->tbd_next = tx_ring->tbd_first; 1721 tx_ring->tbd_oldest = tx_ring->tbd_first; 1722 1723 /* Setup our HW Tx Head & Tail descriptor pointers */ 1724 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 1725 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 1726 } 1727 } 1728 1729 static boolean_t 1730 e1000g_tx_drain(struct e1000g *Adapter) 1731 { 1732 int i; 1733 boolean_t done; 1734 e1000g_tx_ring_t *tx_ring; 1735 1736 tx_ring = Adapter->tx_ring; 1737 1738 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1739 for (i = 0; i < TX_DRAIN_TIME; i++) { 1740 mutex_enter(&tx_ring->usedlist_lock); 1741 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1742 mutex_exit(&tx_ring->usedlist_lock); 1743 1744 if (done) 1745 break; 1746 1747 msec_delay(1); 1748 } 1749 1750 return (done); 1751 } 1752 1753 static boolean_t 1754 e1000g_rx_drain(struct e1000g *Adapter) 1755 { 1756 e1000g_rx_ring_t *rx_ring; 1757 p_rx_sw_packet_t packet; 1758 boolean_t done; 1759 1760 rx_ring = Adapter->rx_ring; 1761 done = B_TRUE; 1762 1763 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1764 1765 while (rx_ring->pending_list != NULL) { 1766 packet = rx_ring->pending_list; 1767 rx_ring->pending_list = 1768 rx_ring->pending_list->next; 1769 1770 if (packet->flag == E1000G_RX_SW_STOP) { 1771 packet->flag = E1000G_RX_SW_DETACH; 1772 done = B_FALSE; 1773 } else { 1774 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1775 ASSERT(packet->mp == NULL); 1776 e1000g_free_rx_sw_packet(packet); 1777 } 1778 } 1779 1780 rw_exit(&e1000g_rx_detach_lock); 1781 1782 return (done); 1783 } 1784 1785 static boolean_t 1786 e1000g_reset_adapter(struct e1000g *Adapter) 1787 { 1788 e1000g_stop(Adapter, B_FALSE); 1789 1790 if (e1000g_start(Adapter, B_FALSE)) { 1791 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1792 return (B_FALSE); 1793 } 1794 1795 return (B_TRUE); 1796 } 1797 1798 boolean_t 1799 e1000g_global_reset(struct e1000g *Adapter) 1800 { 1801 e1000g_stop(Adapter, B_TRUE); 1802 1803 Adapter->init_count = 0; 1804 1805 if (e1000g_start(Adapter, B_TRUE)) { 1806 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1807 return (B_FALSE); 1808 } 1809 1810 return (B_TRUE); 1811 } 1812 1813 /* 1814 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1815 * 1816 * This interrupt service routine is for PCI-Express adapters. 1817 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1818 * bit is set. 1819 */ 1820 static uint_t 1821 e1000g_intr_pciexpress(caddr_t arg) 1822 { 1823 struct e1000g *Adapter; 1824 uint32_t icr; 1825 1826 Adapter = (struct e1000g *)(uintptr_t)arg; 1827 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1828 1829 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1830 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1831 1832 if (icr & E1000_ICR_INT_ASSERTED) { 1833 /* 1834 * E1000_ICR_INT_ASSERTED bit was set: 1835 * Read(Clear) the ICR, claim this interrupt, 1836 * look for work to do. 1837 */ 1838 e1000g_intr_work(Adapter, icr); 1839 return (DDI_INTR_CLAIMED); 1840 } else { 1841 /* 1842 * E1000_ICR_INT_ASSERTED bit was not set: 1843 * Don't claim this interrupt, return immediately. 1844 */ 1845 return (DDI_INTR_UNCLAIMED); 1846 } 1847 } 1848 1849 /* 1850 * e1000g_intr - ISR for PCI/PCI-X chipsets 1851 * 1852 * This interrupt service routine is for PCI/PCI-X adapters. 1853 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1854 * bit is set or not. 1855 */ 1856 static uint_t 1857 e1000g_intr(caddr_t arg) 1858 { 1859 struct e1000g *Adapter; 1860 uint32_t icr; 1861 1862 Adapter = (struct e1000g *)(uintptr_t)arg; 1863 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1864 1865 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1866 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1867 1868 if (icr) { 1869 /* 1870 * Any bit was set in ICR: 1871 * Read(Clear) the ICR, claim this interrupt, 1872 * look for work to do. 1873 */ 1874 e1000g_intr_work(Adapter, icr); 1875 return (DDI_INTR_CLAIMED); 1876 } else { 1877 /* 1878 * No bit was set in ICR: 1879 * Don't claim this interrupt, return immediately. 1880 */ 1881 return (DDI_INTR_UNCLAIMED); 1882 } 1883 } 1884 1885 /* 1886 * e1000g_intr_work - actual processing of ISR 1887 * 1888 * Read(clear) the ICR contents and call appropriate interrupt 1889 * processing routines. 1890 */ 1891 static void 1892 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1893 { 1894 struct e1000_hw *hw; 1895 hw = &Adapter->shared; 1896 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1897 uint32_t itr; 1898 1899 Adapter->rx_pkt_cnt = 0; 1900 Adapter->tx_pkt_cnt = 0; 1901 1902 rw_enter(&Adapter->chip_lock, RW_READER); 1903 /* 1904 * Here we need to check the "chip_state" flag within the chip_lock to 1905 * ensure the receive routine will not execute when the adapter is 1906 * being reset. 1907 */ 1908 if (Adapter->chip_state != E1000G_START) { 1909 rw_exit(&Adapter->chip_lock); 1910 return; 1911 } 1912 1913 if (icr & E1000_ICR_RXT0) { 1914 mblk_t *mp; 1915 1916 mutex_enter(&Adapter->rx_ring->rx_lock); 1917 mp = e1000g_receive(Adapter); 1918 mutex_exit(&Adapter->rx_ring->rx_lock); 1919 1920 rw_exit(&Adapter->chip_lock); 1921 1922 if (mp != NULL) 1923 mac_rx(Adapter->mh, Adapter->mrh, mp); 1924 } else 1925 rw_exit(&Adapter->chip_lock); 1926 1927 if (icr & E1000_ICR_TXDW) { 1928 if (!Adapter->tx_intr_enable) 1929 e1000g_clear_tx_interrupt(Adapter); 1930 1931 /* Recycle the tx descriptors */ 1932 rw_enter(&Adapter->chip_lock, RW_READER); 1933 (void) e1000g_recycle(tx_ring); 1934 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1935 rw_exit(&Adapter->chip_lock); 1936 1937 /* Schedule the re-transmit */ 1938 if (tx_ring->resched_needed && 1939 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1940 tx_ring->resched_needed = B_FALSE; 1941 mac_tx_update(Adapter->mh); 1942 E1000G_STAT(tx_ring->stat_reschedule); 1943 } 1944 } 1945 1946 if (Adapter->intr_adaptive) { 1947 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1948 Adapter->intr_throttling_rate); 1949 if (itr) { 1950 E1000_WRITE_REG(hw, E1000_ITR, itr); 1951 Adapter->intr_throttling_rate = itr; 1952 } 1953 } 1954 1955 /* 1956 * The Receive Sequence errors RXSEQ and the link status change LSC 1957 * are checked to detect that the cable has been pulled out. For 1958 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1959 * are an indication that cable is not connected. 1960 */ 1961 if ((icr & E1000_ICR_RXSEQ) || 1962 (icr & E1000_ICR_LSC) || 1963 (icr & E1000_ICR_GPI_EN1)) { 1964 boolean_t link_changed; 1965 timeout_id_t tid = 0; 1966 1967 stop_watchdog_timer(Adapter); 1968 1969 rw_enter(&Adapter->chip_lock, RW_WRITER); 1970 1971 /* 1972 * Because we got a link-status-change interrupt, force 1973 * e1000_check_for_link() to look at phy 1974 */ 1975 Adapter->shared.mac.get_link_status = B_TRUE; 1976 1977 /* e1000g_link_check takes care of link status change */ 1978 link_changed = e1000g_link_check(Adapter); 1979 1980 /* Get new phy state */ 1981 e1000g_get_phy_state(Adapter); 1982 1983 /* 1984 * If the link timer has not timed out, we'll not notify 1985 * the upper layer with any link state until the link is up. 1986 */ 1987 if (link_changed && !Adapter->link_complete) { 1988 if (Adapter->link_state == LINK_STATE_UP) { 1989 mutex_enter(&Adapter->link_lock); 1990 Adapter->link_complete = B_TRUE; 1991 tid = Adapter->link_tid; 1992 Adapter->link_tid = 0; 1993 mutex_exit(&Adapter->link_lock); 1994 } else { 1995 link_changed = B_FALSE; 1996 } 1997 } 1998 rw_exit(&Adapter->chip_lock); 1999 2000 if (link_changed) { 2001 if (tid != 0) 2002 (void) untimeout(tid); 2003 2004 /* 2005 * Workaround for esb2. Data stuck in fifo on a link 2006 * down event. Stop receiver here and reset in watchdog. 2007 */ 2008 if ((Adapter->link_state == LINK_STATE_DOWN) && 2009 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2010 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2011 E1000_WRITE_REG(hw, E1000_RCTL, 2012 rctl & ~E1000_RCTL_EN); 2013 e1000g_log(Adapter, CE_WARN, 2014 "ESB2 receiver disabled"); 2015 Adapter->esb2_workaround = B_TRUE; 2016 } 2017 2018 mac_link_update(Adapter->mh, Adapter->link_state); 2019 } 2020 2021 start_watchdog_timer(Adapter); 2022 } 2023 } 2024 2025 static uint32_t 2026 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 2027 { 2028 uint32_t new_itr; 2029 2030 /* 2031 * Determine a propper itr according to rx/tx packet count 2032 * per interrupt, the value of itr are based on document 2033 * and testing. 2034 */ 2035 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 2036 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 2037 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2038 goto itr_done; 2039 } 2040 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 2041 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 2042 new_itr = DEFAULT_INTR_THROTTLING_LOW; 2043 goto itr_done; 2044 } 2045 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 2046 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 2047 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 2048 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2049 } else 2050 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 2051 2052 itr_done: 2053 if (cur_itr == new_itr) 2054 return (0); 2055 else 2056 return (new_itr); 2057 } 2058 2059 static void 2060 e1000g_init_unicst(struct e1000g *Adapter) 2061 { 2062 struct e1000_hw *hw; 2063 int slot; 2064 2065 hw = &Adapter->shared; 2066 2067 if (!Adapter->unicst_init) { 2068 /* Initialize the multiple unicast addresses */ 2069 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2070 2071 if ((hw->mac.type == e1000_82571) && 2072 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2073 Adapter->unicst_total--; 2074 2075 Adapter->unicst_avail = Adapter->unicst_total - 1; 2076 2077 /* Store the default mac address */ 2078 e1000_rar_set(hw, hw->mac.addr, 0); 2079 if ((hw->mac.type == e1000_82571) && 2080 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2081 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2082 2083 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2084 ETHERADDRL); 2085 Adapter->unicst_addr[0].mac.set = 1; 2086 2087 for (slot = 1; slot < Adapter->unicst_total; slot++) 2088 Adapter->unicst_addr[slot].mac.set = 0; 2089 2090 Adapter->unicst_init = B_TRUE; 2091 } else { 2092 /* Recover the default mac address */ 2093 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2094 ETHERADDRL); 2095 2096 /* Store the default mac address */ 2097 e1000_rar_set(hw, hw->mac.addr, 0); 2098 if ((hw->mac.type == e1000_82571) && 2099 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2100 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2101 2102 /* Re-configure the RAR registers */ 2103 for (slot = 1; slot < Adapter->unicst_total; slot++) 2104 e1000_rar_set(hw, 2105 Adapter->unicst_addr[slot].mac.addr, slot); 2106 } 2107 2108 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2109 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2110 } 2111 2112 static int 2113 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2114 { 2115 struct e1000g *Adapter; 2116 2117 Adapter = (struct e1000g *)arg; 2118 2119 /* Store the default MAC address */ 2120 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2121 2122 /* Set MAC address in address slot 0, which is the default address */ 2123 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2124 } 2125 2126 static int 2127 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2128 mac_addr_slot_t slot) 2129 { 2130 struct e1000_hw *hw; 2131 2132 hw = &Adapter->shared; 2133 2134 rw_enter(&Adapter->chip_lock, RW_WRITER); 2135 2136 /* 2137 * The first revision of Wiseman silicon (rev 2.0) has an errata 2138 * that requires the receiver to be in reset when any of the 2139 * receive address registers (RAR regs) are accessed. The first 2140 * rev of Wiseman silicon also requires MWI to be disabled when 2141 * a global reset or a receive reset is issued. So before we 2142 * initialize the RARs, we check the rev of the Wiseman controller 2143 * and work around any necessary HW errata. 2144 */ 2145 if ((hw->mac.type == e1000_82542) && 2146 (hw->revision_id == E1000_REVISION_2)) { 2147 e1000_pci_clear_mwi(hw); 2148 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2149 msec_delay(5); 2150 } 2151 2152 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2153 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2154 2155 if (slot == 0) { 2156 if ((hw->mac.type == e1000_82571) && 2157 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2158 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2159 } 2160 2161 /* 2162 * If we are using Wiseman rev 2.0 silicon, we will have previously 2163 * put the receive in reset, and disabled MWI, to work around some 2164 * HW errata. Now we should take the receiver out of reset, and 2165 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2166 */ 2167 if ((hw->mac.type == e1000_82542) && 2168 (hw->revision_id == E1000_REVISION_2)) { 2169 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2170 msec_delay(1); 2171 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2172 e1000_pci_set_mwi(hw); 2173 e1000g_rx_setup(Adapter); 2174 } 2175 2176 rw_exit(&Adapter->chip_lock); 2177 2178 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2179 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2180 return (EIO); 2181 } 2182 2183 return (0); 2184 } 2185 2186 /* 2187 * e1000g_m_unicst_add() - will find an unused address slot, set the 2188 * address value to the one specified, reserve that slot and enable 2189 * the NIC to start filtering on the new MAC address. 2190 * Returns 0 on success. 2191 */ 2192 static int 2193 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2194 { 2195 struct e1000g *Adapter = (struct e1000g *)arg; 2196 mac_addr_slot_t slot; 2197 int err; 2198 2199 if (mac_unicst_verify(Adapter->mh, 2200 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2201 return (EINVAL); 2202 2203 rw_enter(&Adapter->chip_lock, RW_WRITER); 2204 if (Adapter->unicst_avail == 0) { 2205 /* no slots available */ 2206 rw_exit(&Adapter->chip_lock); 2207 return (ENOSPC); 2208 } 2209 2210 /* 2211 * Primary/default address is in slot 0. The next addresses 2212 * are the multiple MAC addresses. So multiple MAC address 0 2213 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2214 * MAC address resides in slot 1. 2215 */ 2216 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2217 if (Adapter->unicst_addr[slot].mac.set == 0) { 2218 Adapter->unicst_addr[slot].mac.set = 1; 2219 break; 2220 } 2221 } 2222 2223 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2224 2225 Adapter->unicst_avail--; 2226 rw_exit(&Adapter->chip_lock); 2227 2228 maddr->mma_slot = slot; 2229 2230 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2231 rw_enter(&Adapter->chip_lock, RW_WRITER); 2232 Adapter->unicst_addr[slot].mac.set = 0; 2233 Adapter->unicst_avail++; 2234 rw_exit(&Adapter->chip_lock); 2235 } 2236 2237 return (err); 2238 } 2239 2240 /* 2241 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2242 * call to e1000g_m_unicst_add(). The slot number that was returned in 2243 * e1000g_m_unicst_add() is passed in the call to remove the address. 2244 * Returns 0 on success. 2245 */ 2246 static int 2247 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2248 { 2249 struct e1000g *Adapter = (struct e1000g *)arg; 2250 int err; 2251 2252 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2253 return (EINVAL); 2254 2255 rw_enter(&Adapter->chip_lock, RW_WRITER); 2256 if (Adapter->unicst_addr[slot].mac.set == 1) { 2257 Adapter->unicst_addr[slot].mac.set = 0; 2258 Adapter->unicst_avail++; 2259 rw_exit(&Adapter->chip_lock); 2260 2261 /* Copy the default address to the passed slot */ 2262 if ((err = e1000g_unicst_set(Adapter, 2263 Adapter->unicst_addr[0].mac.addr, slot)) != 0) { 2264 rw_enter(&Adapter->chip_lock, RW_WRITER); 2265 Adapter->unicst_addr[slot].mac.set = 1; 2266 Adapter->unicst_avail--; 2267 rw_exit(&Adapter->chip_lock); 2268 } 2269 return (err); 2270 } 2271 rw_exit(&Adapter->chip_lock); 2272 2273 return (EINVAL); 2274 } 2275 2276 /* 2277 * e1000g_m_unicst_modify() - modifies the value of an address that 2278 * has been added by e1000g_m_unicst_add(). The new address, address 2279 * length and the slot number that was returned in the call to add 2280 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2281 * set to 0. Returns 0 on success. 2282 */ 2283 static int 2284 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2285 { 2286 struct e1000g *Adapter = (struct e1000g *)arg; 2287 mac_addr_slot_t slot; 2288 2289 if (mac_unicst_verify(Adapter->mh, 2290 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2291 return (EINVAL); 2292 2293 slot = maddr->mma_slot; 2294 2295 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2296 return (EINVAL); 2297 2298 rw_enter(&Adapter->chip_lock, RW_WRITER); 2299 if (Adapter->unicst_addr[slot].mac.set == 1) { 2300 rw_exit(&Adapter->chip_lock); 2301 2302 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2303 } 2304 rw_exit(&Adapter->chip_lock); 2305 2306 return (EINVAL); 2307 } 2308 2309 /* 2310 * e1000g_m_unicst_get() - will get the MAC address and all other 2311 * information related to the address slot passed in mac_multi_addr_t. 2312 * mma_flags should be set to 0 in the call. 2313 * On return, mma_flags can take the following values: 2314 * 1) MMAC_SLOT_UNUSED 2315 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2316 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2317 * 4) MMAC_SLOT_USED 2318 */ 2319 static int 2320 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2321 { 2322 struct e1000g *Adapter = (struct e1000g *)arg; 2323 mac_addr_slot_t slot; 2324 2325 slot = maddr->mma_slot; 2326 2327 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2328 return (EINVAL); 2329 2330 rw_enter(&Adapter->chip_lock, RW_WRITER); 2331 if (Adapter->unicst_addr[slot].mac.set == 1) { 2332 bcopy(Adapter->unicst_addr[slot].mac.addr, 2333 maddr->mma_addr, ETHERADDRL); 2334 maddr->mma_flags = MMAC_SLOT_USED; 2335 } else { 2336 maddr->mma_flags = MMAC_SLOT_UNUSED; 2337 } 2338 rw_exit(&Adapter->chip_lock); 2339 2340 return (0); 2341 } 2342 2343 static int 2344 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2345 { 2346 struct e1000_hw *hw = &Adapter->shared; 2347 int res = 0; 2348 2349 rw_enter(&Adapter->chip_lock, RW_WRITER); 2350 2351 if ((multiaddr[0] & 01) == 0) { 2352 res = EINVAL; 2353 goto done; 2354 } 2355 2356 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2357 res = ENOENT; 2358 goto done; 2359 } 2360 2361 bcopy(multiaddr, 2362 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2363 Adapter->mcast_count++; 2364 2365 /* 2366 * Update the MC table in the hardware 2367 */ 2368 e1000g_clear_interrupt(Adapter); 2369 2370 e1000g_setup_multicast(Adapter); 2371 2372 if ((hw->mac.type == e1000_82542) && 2373 (hw->revision_id == E1000_REVISION_2)) 2374 e1000g_rx_setup(Adapter); 2375 2376 e1000g_mask_interrupt(Adapter); 2377 2378 done: 2379 rw_exit(&Adapter->chip_lock); 2380 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2381 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2382 res = EIO; 2383 } 2384 2385 return (res); 2386 } 2387 2388 static int 2389 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2390 { 2391 struct e1000_hw *hw = &Adapter->shared; 2392 unsigned i; 2393 2394 rw_enter(&Adapter->chip_lock, RW_WRITER); 2395 2396 for (i = 0; i < Adapter->mcast_count; i++) { 2397 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2398 ETHERADDRL) == 0) { 2399 for (i++; i < Adapter->mcast_count; i++) { 2400 Adapter->mcast_table[i - 1] = 2401 Adapter->mcast_table[i]; 2402 } 2403 Adapter->mcast_count--; 2404 break; 2405 } 2406 } 2407 2408 /* 2409 * Update the MC table in the hardware 2410 */ 2411 e1000g_clear_interrupt(Adapter); 2412 2413 e1000g_setup_multicast(Adapter); 2414 2415 if ((hw->mac.type == e1000_82542) && 2416 (hw->revision_id == E1000_REVISION_2)) 2417 e1000g_rx_setup(Adapter); 2418 2419 e1000g_mask_interrupt(Adapter); 2420 2421 done: 2422 rw_exit(&Adapter->chip_lock); 2423 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2424 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2425 return (EIO); 2426 } 2427 2428 return (0); 2429 } 2430 2431 /* 2432 * e1000g_setup_multicast - setup multicast data structures 2433 * 2434 * This routine initializes all of the multicast related structures. 2435 */ 2436 void 2437 e1000g_setup_multicast(struct e1000g *Adapter) 2438 { 2439 uint8_t *mc_addr_list; 2440 uint32_t mc_addr_count; 2441 uint32_t rctl; 2442 struct e1000_hw *hw; 2443 2444 hw = &Adapter->shared; 2445 2446 /* 2447 * The e1000g has the ability to do perfect filtering of 16 2448 * addresses. The driver uses one of the e1000g's 16 receive 2449 * address registers for its node/network/mac/individual address. 2450 * So, we have room for up to 15 multicast addresses in the CAM, 2451 * additional MC addresses are handled by the MTA (Multicast Table 2452 * Array) 2453 */ 2454 2455 rctl = E1000_READ_REG(hw, E1000_RCTL); 2456 2457 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2458 2459 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2460 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2461 "Adapter requested more than %d MC Addresses.\n", 2462 MAX_NUM_MULTICAST_ADDRESSES); 2463 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2464 } else { 2465 /* 2466 * Set the number of MC addresses that we are being 2467 * requested to use 2468 */ 2469 mc_addr_count = Adapter->mcast_count; 2470 } 2471 /* 2472 * The Wiseman 2.0 silicon has an errata by which the receiver will 2473 * hang while writing to the receive address registers if the receiver 2474 * is not in reset before writing to the registers. Updating the RAR 2475 * is done during the setting up of the multicast table, hence the 2476 * receiver has to be put in reset before updating the multicast table 2477 * and then taken out of reset at the end 2478 */ 2479 /* 2480 * if WMI was enabled then dis able it before issueing the global 2481 * reset to the hardware. 2482 */ 2483 /* 2484 * Only required for WISEMAN_2_0 2485 */ 2486 if ((hw->mac.type == e1000_82542) && 2487 (hw->revision_id == E1000_REVISION_2)) { 2488 e1000_pci_clear_mwi(hw); 2489 /* 2490 * The e1000g must be in reset before changing any RA 2491 * registers. Reset receive unit. The chip will remain in 2492 * the reset state until software explicitly restarts it. 2493 */ 2494 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2495 /* Allow receiver time to go in to reset */ 2496 msec_delay(5); 2497 } 2498 2499 e1000_update_mc_addr_list(hw, mc_addr_list, mc_addr_count, 2500 Adapter->unicst_total, hw->mac.rar_entry_count); 2501 2502 /* 2503 * Only for Wiseman_2_0 2504 * If MWI was enabled then re-enable it after issueing (as we 2505 * disabled it up there) the receive reset command. 2506 * Wainwright does not have a receive reset command and only thing 2507 * close to it is global reset which will require tx setup also 2508 */ 2509 if ((hw->mac.type == e1000_82542) && 2510 (hw->revision_id == E1000_REVISION_2)) { 2511 /* 2512 * if WMI was enabled then reenable it after issueing the 2513 * global or receive reset to the hardware. 2514 */ 2515 2516 /* 2517 * Take receiver out of reset 2518 * clear E1000_RCTL_RST bit (and all others) 2519 */ 2520 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2521 msec_delay(5); 2522 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2523 e1000_pci_set_mwi(hw); 2524 } 2525 2526 /* 2527 * Restore original value 2528 */ 2529 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2530 } 2531 2532 int 2533 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2534 { 2535 struct e1000g *Adapter = (struct e1000g *)arg; 2536 2537 return ((add) ? multicst_add(Adapter, addr) 2538 : multicst_remove(Adapter, addr)); 2539 } 2540 2541 int 2542 e1000g_m_promisc(void *arg, boolean_t on) 2543 { 2544 struct e1000g *Adapter = (struct e1000g *)arg; 2545 uint32_t rctl; 2546 2547 rw_enter(&Adapter->chip_lock, RW_WRITER); 2548 2549 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2550 2551 if (on) 2552 rctl |= 2553 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2554 else 2555 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2556 2557 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2558 2559 Adapter->e1000g_promisc = on; 2560 2561 rw_exit(&Adapter->chip_lock); 2562 2563 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2564 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2565 return (EIO); 2566 } 2567 2568 return (0); 2569 } 2570 2571 static boolean_t 2572 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2573 { 2574 struct e1000g *Adapter = (struct e1000g *)arg; 2575 2576 switch (cap) { 2577 case MAC_CAPAB_HCKSUM: { 2578 uint32_t *txflags = cap_data; 2579 2580 if (Adapter->tx_hcksum_enable) 2581 *txflags = HCKSUM_IPHDRCKSUM | 2582 HCKSUM_INET_PARTIAL; 2583 else 2584 return (B_FALSE); 2585 break; 2586 } 2587 case MAC_CAPAB_POLL: 2588 /* 2589 * There's nothing for us to fill in, simply returning 2590 * B_TRUE stating that we support polling is sufficient. 2591 */ 2592 break; 2593 2594 case MAC_CAPAB_MULTIADDRESS: { 2595 multiaddress_capab_t *mmacp = cap_data; 2596 2597 /* 2598 * The number of MAC addresses made available by 2599 * this capability is one less than the total as 2600 * the primary address in slot 0 is counted in 2601 * the total. 2602 */ 2603 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2604 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2605 /* No multiple factory addresses, set mma_flag to 0 */ 2606 mmacp->maddr_flag = 0; 2607 mmacp->maddr_handle = Adapter; 2608 mmacp->maddr_add = e1000g_m_unicst_add; 2609 mmacp->maddr_remove = e1000g_m_unicst_remove; 2610 mmacp->maddr_modify = e1000g_m_unicst_modify; 2611 mmacp->maddr_get = e1000g_m_unicst_get; 2612 mmacp->maddr_reserve = NULL; 2613 break; 2614 } 2615 2616 case MAC_CAPAB_LSO: { 2617 mac_capab_lso_t *cap_lso = cap_data; 2618 2619 if (Adapter->lso_enable) { 2620 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 2621 cap_lso->lso_basic_tcp_ipv4.lso_max = 2622 E1000_LSO_MAXLEN; 2623 } else 2624 return (B_FALSE); 2625 break; 2626 } 2627 2628 default: 2629 return (B_FALSE); 2630 } 2631 return (B_TRUE); 2632 } 2633 2634 static boolean_t 2635 e1000g_param_locked(mac_prop_id_t pr_num) 2636 { 2637 /* 2638 * All en_* parameters are locked (read-only) while 2639 * the device is in any sort of loopback mode ... 2640 */ 2641 switch (pr_num) { 2642 case MAC_PROP_EN_1000FDX_CAP: 2643 case MAC_PROP_EN_1000HDX_CAP: 2644 case MAC_PROP_EN_100FDX_CAP: 2645 case MAC_PROP_EN_100HDX_CAP: 2646 case MAC_PROP_EN_10FDX_CAP: 2647 case MAC_PROP_EN_10HDX_CAP: 2648 case MAC_PROP_AUTONEG: 2649 case MAC_PROP_FLOWCTRL: 2650 return (B_TRUE); 2651 } 2652 return (B_FALSE); 2653 } 2654 2655 /* 2656 * callback function for set/get of properties 2657 */ 2658 static int 2659 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2660 uint_t pr_valsize, const void *pr_val) 2661 { 2662 struct e1000g *Adapter = arg; 2663 struct e1000_mac_info *mac = &Adapter->shared.mac; 2664 struct e1000_phy_info *phy = &Adapter->shared.phy; 2665 struct e1000_fc_info *fc = &Adapter->shared.fc; 2666 int err = 0; 2667 link_flowctrl_t flowctrl; 2668 uint32_t cur_mtu, new_mtu; 2669 uint64_t tmp = 0; 2670 2671 rw_enter(&Adapter->chip_lock, RW_WRITER); 2672 if (Adapter->loopback_mode != E1000G_LB_NONE && 2673 e1000g_param_locked(pr_num)) { 2674 /* 2675 * All en_* parameters are locked (read-only) 2676 * while the device is in any sort of loopback mode. 2677 */ 2678 rw_exit(&Adapter->chip_lock); 2679 return (EBUSY); 2680 } 2681 2682 switch (pr_num) { 2683 case MAC_PROP_EN_1000FDX_CAP: 2684 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2685 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2686 goto reset; 2687 case MAC_PROP_EN_1000HDX_CAP: 2688 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2689 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2690 goto reset; 2691 case MAC_PROP_EN_100FDX_CAP: 2692 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2693 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2694 goto reset; 2695 case MAC_PROP_EN_100HDX_CAP: 2696 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2697 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2698 goto reset; 2699 case MAC_PROP_EN_10FDX_CAP: 2700 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2701 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2702 goto reset; 2703 case MAC_PROP_EN_10HDX_CAP: 2704 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2705 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2706 goto reset; 2707 case MAC_PROP_AUTONEG: 2708 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2709 goto reset; 2710 case MAC_PROP_FLOWCTRL: 2711 fc->send_xon = B_TRUE; 2712 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 2713 2714 switch (flowctrl) { 2715 default: 2716 err = EINVAL; 2717 break; 2718 case LINK_FLOWCTRL_NONE: 2719 fc->type = e1000_fc_none; 2720 break; 2721 case LINK_FLOWCTRL_RX: 2722 fc->type = e1000_fc_rx_pause; 2723 break; 2724 case LINK_FLOWCTRL_TX: 2725 fc->type = e1000_fc_tx_pause; 2726 break; 2727 case LINK_FLOWCTRL_BI: 2728 fc->type = e1000_fc_full; 2729 break; 2730 } 2731 reset: 2732 if (err == 0) { 2733 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2734 err = EINVAL; 2735 } 2736 break; 2737 case MAC_PROP_ADV_1000FDX_CAP: 2738 case MAC_PROP_ADV_1000HDX_CAP: 2739 case MAC_PROP_ADV_100FDX_CAP: 2740 case MAC_PROP_ADV_100HDX_CAP: 2741 case MAC_PROP_ADV_10FDX_CAP: 2742 case MAC_PROP_ADV_10HDX_CAP: 2743 case MAC_PROP_STATUS: 2744 case MAC_PROP_SPEED: 2745 case MAC_PROP_DUPLEX: 2746 err = ENOTSUP; /* read-only prop. Can't set this. */ 2747 break; 2748 case MAC_PROP_MTU: 2749 cur_mtu = Adapter->default_mtu; 2750 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2751 if (new_mtu == cur_mtu) { 2752 err = 0; 2753 break; 2754 } 2755 2756 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2757 ETHERFCSL; 2758 if ((tmp < DEFAULT_FRAME_SIZE) || 2759 (tmp > MAXIMUM_FRAME_SIZE)) { 2760 err = EINVAL; 2761 break; 2762 } 2763 2764 /* ich8 does not support jumbo frames */ 2765 if ((mac->type == e1000_ich8lan) && 2766 (tmp > DEFAULT_FRAME_SIZE)) { 2767 err = EINVAL; 2768 break; 2769 } 2770 /* ich9 does not do jumbo frames on one phy type */ 2771 if ((mac->type == e1000_ich9lan) && 2772 (phy->type == e1000_phy_ife) && 2773 (tmp > DEFAULT_FRAME_SIZE)) { 2774 err = EINVAL; 2775 break; 2776 } 2777 if (Adapter->chip_state != E1000G_STOP) { 2778 err = EBUSY; 2779 break; 2780 } 2781 2782 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2783 if (err == 0) { 2784 Adapter->max_frame_size = (uint32_t)tmp; 2785 Adapter->default_mtu = new_mtu; 2786 e1000g_set_bufsize(Adapter); 2787 } 2788 break; 2789 case MAC_PROP_PRIVATE: 2790 err = e1000g_set_priv_prop(Adapter, pr_name, 2791 pr_valsize, pr_val); 2792 break; 2793 default: 2794 err = ENOTSUP; 2795 break; 2796 } 2797 rw_exit(&Adapter->chip_lock); 2798 return (err); 2799 } 2800 2801 static int 2802 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2803 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2804 { 2805 struct e1000g *Adapter = arg; 2806 struct e1000_fc_info *fc = &Adapter->shared.fc; 2807 int err = 0; 2808 link_flowctrl_t flowctrl; 2809 uint64_t tmp = 0; 2810 2811 if (pr_valsize == 0) 2812 return (EINVAL); 2813 2814 bzero(pr_val, pr_valsize); 2815 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 2816 return (e1000g_get_def_val(Adapter, pr_num, 2817 pr_valsize, pr_val)); 2818 } 2819 2820 switch (pr_num) { 2821 case MAC_PROP_DUPLEX: 2822 if (pr_valsize >= sizeof (link_duplex_t)) { 2823 bcopy(&Adapter->link_duplex, pr_val, 2824 sizeof (link_duplex_t)); 2825 } else 2826 err = EINVAL; 2827 break; 2828 case MAC_PROP_SPEED: 2829 if (pr_valsize >= sizeof (uint64_t)) { 2830 tmp = Adapter->link_speed * 1000000ull; 2831 bcopy(&tmp, pr_val, sizeof (tmp)); 2832 } else 2833 err = EINVAL; 2834 break; 2835 case MAC_PROP_AUTONEG: 2836 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2837 break; 2838 case MAC_PROP_FLOWCTRL: 2839 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2840 switch (fc->type) { 2841 case e1000_fc_none: 2842 flowctrl = LINK_FLOWCTRL_NONE; 2843 break; 2844 case e1000_fc_rx_pause: 2845 flowctrl = LINK_FLOWCTRL_RX; 2846 break; 2847 case e1000_fc_tx_pause: 2848 flowctrl = LINK_FLOWCTRL_TX; 2849 break; 2850 case e1000_fc_full: 2851 flowctrl = LINK_FLOWCTRL_BI; 2852 break; 2853 } 2854 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 2855 } else 2856 err = EINVAL; 2857 break; 2858 case MAC_PROP_ADV_1000FDX_CAP: 2859 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2860 break; 2861 case MAC_PROP_EN_1000FDX_CAP: 2862 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2863 break; 2864 case MAC_PROP_ADV_1000HDX_CAP: 2865 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2866 break; 2867 case MAC_PROP_EN_1000HDX_CAP: 2868 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2869 break; 2870 case MAC_PROP_ADV_100FDX_CAP: 2871 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2872 break; 2873 case MAC_PROP_EN_100FDX_CAP: 2874 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2875 break; 2876 case MAC_PROP_ADV_100HDX_CAP: 2877 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2878 break; 2879 case MAC_PROP_EN_100HDX_CAP: 2880 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2881 break; 2882 case MAC_PROP_ADV_10FDX_CAP: 2883 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2884 break; 2885 case MAC_PROP_EN_10FDX_CAP: 2886 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2887 break; 2888 case MAC_PROP_ADV_10HDX_CAP: 2889 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2890 break; 2891 case MAC_PROP_EN_10HDX_CAP: 2892 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2893 break; 2894 case MAC_PROP_ADV_100T4_CAP: 2895 case MAC_PROP_EN_100T4_CAP: 2896 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2897 break; 2898 case MAC_PROP_PRIVATE: 2899 err = e1000g_get_priv_prop(Adapter, pr_name, 2900 pr_flags, pr_valsize, pr_val); 2901 break; 2902 default: 2903 err = ENOTSUP; 2904 break; 2905 } 2906 return (err); 2907 } 2908 2909 /* ARGSUSED2 */ 2910 static int 2911 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2912 uint_t pr_valsize, const void *pr_val) 2913 { 2914 int err = 0; 2915 long result; 2916 struct e1000_hw *hw = &Adapter->shared; 2917 2918 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2919 if (pr_val == NULL) { 2920 err = EINVAL; 2921 return (err); 2922 } 2923 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2924 if (result < MIN_TX_BCOPY_THRESHOLD || 2925 result > MAX_TX_BCOPY_THRESHOLD) 2926 err = EINVAL; 2927 else { 2928 Adapter->tx_bcopy_thresh = (uint32_t)result; 2929 } 2930 return (err); 2931 } 2932 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2933 if (pr_val == NULL) { 2934 err = EINVAL; 2935 return (err); 2936 } 2937 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2938 if (result < 0 || result > 1) 2939 err = EINVAL; 2940 else { 2941 Adapter->tx_intr_enable = (result == 1) ? 2942 B_TRUE: B_FALSE; 2943 if (Adapter->tx_intr_enable) 2944 e1000g_mask_tx_interrupt(Adapter); 2945 else 2946 e1000g_clear_tx_interrupt(Adapter); 2947 if (e1000g_check_acc_handle( 2948 Adapter->osdep.reg_handle) != DDI_FM_OK) 2949 ddi_fm_service_impact(Adapter->dip, 2950 DDI_SERVICE_DEGRADED); 2951 } 2952 return (err); 2953 } 2954 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2955 if (pr_val == NULL) { 2956 err = EINVAL; 2957 return (err); 2958 } 2959 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2960 if (result < MIN_TX_INTR_DELAY || 2961 result > MAX_TX_INTR_DELAY) 2962 err = EINVAL; 2963 else { 2964 Adapter->tx_intr_delay = (uint32_t)result; 2965 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2966 if (e1000g_check_acc_handle( 2967 Adapter->osdep.reg_handle) != DDI_FM_OK) 2968 ddi_fm_service_impact(Adapter->dip, 2969 DDI_SERVICE_DEGRADED); 2970 } 2971 return (err); 2972 } 2973 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2974 if (pr_val == NULL) { 2975 err = EINVAL; 2976 return (err); 2977 } 2978 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2979 if (result < MIN_TX_INTR_ABS_DELAY || 2980 result > MAX_TX_INTR_ABS_DELAY) 2981 err = EINVAL; 2982 else { 2983 Adapter->tx_intr_abs_delay = (uint32_t)result; 2984 E1000_WRITE_REG(hw, E1000_TADV, 2985 Adapter->tx_intr_abs_delay); 2986 if (e1000g_check_acc_handle( 2987 Adapter->osdep.reg_handle) != DDI_FM_OK) 2988 ddi_fm_service_impact(Adapter->dip, 2989 DDI_SERVICE_DEGRADED); 2990 } 2991 return (err); 2992 } 2993 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2994 if (pr_val == NULL) { 2995 err = EINVAL; 2996 return (err); 2997 } 2998 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2999 if (result < MIN_RX_BCOPY_THRESHOLD || 3000 result > MAX_RX_BCOPY_THRESHOLD) 3001 err = EINVAL; 3002 else 3003 Adapter->rx_bcopy_thresh = (uint32_t)result; 3004 return (err); 3005 } 3006 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3007 if (pr_val == NULL) { 3008 err = EINVAL; 3009 return (err); 3010 } 3011 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3012 if (result < MIN_RX_LIMIT_ON_INTR || 3013 result > MAX_RX_LIMIT_ON_INTR) 3014 err = EINVAL; 3015 else 3016 Adapter->rx_limit_onintr = (uint32_t)result; 3017 return (err); 3018 } 3019 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3020 if (pr_val == NULL) { 3021 err = EINVAL; 3022 return (err); 3023 } 3024 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3025 if (result < MIN_RX_INTR_DELAY || 3026 result > MAX_RX_INTR_DELAY) 3027 err = EINVAL; 3028 else { 3029 Adapter->rx_intr_delay = (uint32_t)result; 3030 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3031 if (e1000g_check_acc_handle( 3032 Adapter->osdep.reg_handle) != DDI_FM_OK) 3033 ddi_fm_service_impact(Adapter->dip, 3034 DDI_SERVICE_DEGRADED); 3035 } 3036 return (err); 3037 } 3038 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3039 if (pr_val == NULL) { 3040 err = EINVAL; 3041 return (err); 3042 } 3043 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3044 if (result < MIN_RX_INTR_ABS_DELAY || 3045 result > MAX_RX_INTR_ABS_DELAY) 3046 err = EINVAL; 3047 else { 3048 Adapter->rx_intr_abs_delay = (uint32_t)result; 3049 E1000_WRITE_REG(hw, E1000_RADV, 3050 Adapter->rx_intr_abs_delay); 3051 if (e1000g_check_acc_handle( 3052 Adapter->osdep.reg_handle) != DDI_FM_OK) 3053 ddi_fm_service_impact(Adapter->dip, 3054 DDI_SERVICE_DEGRADED); 3055 } 3056 return (err); 3057 } 3058 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3059 if (pr_val == NULL) { 3060 err = EINVAL; 3061 return (err); 3062 } 3063 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3064 if (result < MIN_INTR_THROTTLING || 3065 result > MAX_INTR_THROTTLING) 3066 err = EINVAL; 3067 else { 3068 if (hw->mac.type >= e1000_82540) { 3069 Adapter->intr_throttling_rate = 3070 (uint32_t)result; 3071 E1000_WRITE_REG(hw, E1000_ITR, 3072 Adapter->intr_throttling_rate); 3073 if (e1000g_check_acc_handle( 3074 Adapter->osdep.reg_handle) != DDI_FM_OK) 3075 ddi_fm_service_impact(Adapter->dip, 3076 DDI_SERVICE_DEGRADED); 3077 } else 3078 err = EINVAL; 3079 } 3080 return (err); 3081 } 3082 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3083 if (pr_val == NULL) { 3084 err = EINVAL; 3085 return (err); 3086 } 3087 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3088 if (result < 0 || result > 1) 3089 err = EINVAL; 3090 else { 3091 if (hw->mac.type >= e1000_82540) { 3092 Adapter->intr_adaptive = (result == 1) ? 3093 B_TRUE : B_FALSE; 3094 } else { 3095 err = EINVAL; 3096 } 3097 } 3098 return (err); 3099 } 3100 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3101 if (pr_val == NULL) { 3102 err = EINVAL; 3103 return (err); 3104 } 3105 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3106 if (result < MIN_TX_RECYCLE_THRESHOLD || 3107 result > MAX_TX_RECYCLE_THRESHOLD) 3108 err = EINVAL; 3109 else 3110 Adapter->tx_recycle_thresh = (uint32_t)result; 3111 return (err); 3112 } 3113 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3114 if (pr_val == NULL) { 3115 err = EINVAL; 3116 return (err); 3117 } 3118 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3119 if (result < MIN_TX_RECYCLE_NUM || 3120 result > MAX_TX_RECYCLE_NUM) 3121 err = EINVAL; 3122 else 3123 Adapter->tx_recycle_num = (uint32_t)result; 3124 return (err); 3125 } 3126 return (ENOTSUP); 3127 } 3128 3129 static int 3130 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3131 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3132 { 3133 int err = ENOTSUP; 3134 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3135 int value; 3136 3137 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3138 if (is_default) 3139 goto done; 3140 value = Adapter->param_adv_pause; 3141 err = 0; 3142 goto done; 3143 } 3144 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3145 if (is_default) 3146 goto done; 3147 value = Adapter->param_adv_asym_pause; 3148 err = 0; 3149 goto done; 3150 } 3151 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3152 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3153 Adapter->tx_bcopy_thresh); 3154 err = 0; 3155 goto done; 3156 } 3157 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3158 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3159 Adapter->tx_intr_enable); 3160 err = 0; 3161 goto done; 3162 } 3163 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3164 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3165 Adapter->tx_intr_delay); 3166 err = 0; 3167 goto done; 3168 } 3169 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3170 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3171 Adapter->tx_intr_abs_delay); 3172 err = 0; 3173 goto done; 3174 } 3175 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3176 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3177 Adapter->rx_bcopy_thresh); 3178 err = 0; 3179 goto done; 3180 } 3181 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3182 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3183 Adapter->rx_limit_onintr); 3184 err = 0; 3185 goto done; 3186 } 3187 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3188 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3189 Adapter->rx_intr_delay); 3190 err = 0; 3191 goto done; 3192 } 3193 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3194 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3195 Adapter->rx_intr_abs_delay); 3196 err = 0; 3197 goto done; 3198 } 3199 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3200 value = (is_default ? DEFAULT_INTR_THROTTLING : 3201 Adapter->intr_throttling_rate); 3202 err = 0; 3203 goto done; 3204 } 3205 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3206 value = (is_default ? 1 : Adapter->intr_adaptive); 3207 err = 0; 3208 goto done; 3209 } 3210 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3211 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3212 Adapter->tx_recycle_thresh); 3213 err = 0; 3214 goto done; 3215 } 3216 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3217 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3218 Adapter->tx_recycle_num); 3219 err = 0; 3220 goto done; 3221 } 3222 done: 3223 if (err == 0) { 3224 (void) snprintf(pr_val, pr_valsize, "%d", value); 3225 } 3226 return (err); 3227 } 3228 3229 /* 3230 * e1000g_get_conf - get configurations set in e1000g.conf 3231 * This routine gets user-configured values out of the configuration 3232 * file e1000g.conf. 3233 * 3234 * For each configurable value, there is a minimum, a maximum, and a 3235 * default. 3236 * If user does not configure a value, use the default. 3237 * If user configures below the minimum, use the minumum. 3238 * If user configures above the maximum, use the maxumum. 3239 */ 3240 static void 3241 e1000g_get_conf(struct e1000g *Adapter) 3242 { 3243 struct e1000_hw *hw = &Adapter->shared; 3244 boolean_t tbi_compatibility = B_FALSE; 3245 3246 /* 3247 * get each configurable property from e1000g.conf 3248 */ 3249 3250 /* 3251 * NumTxDescriptors 3252 */ 3253 Adapter->tx_desc_num = 3254 e1000g_get_prop(Adapter, "NumTxDescriptors", 3255 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3256 DEFAULT_NUM_TX_DESCRIPTOR); 3257 3258 /* 3259 * NumRxDescriptors 3260 */ 3261 Adapter->rx_desc_num = 3262 e1000g_get_prop(Adapter, "NumRxDescriptors", 3263 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3264 DEFAULT_NUM_RX_DESCRIPTOR); 3265 3266 /* 3267 * NumRxFreeList 3268 */ 3269 Adapter->rx_freelist_num = 3270 e1000g_get_prop(Adapter, "NumRxFreeList", 3271 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3272 DEFAULT_NUM_RX_FREELIST); 3273 3274 /* 3275 * NumTxPacketList 3276 */ 3277 Adapter->tx_freelist_num = 3278 e1000g_get_prop(Adapter, "NumTxPacketList", 3279 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3280 DEFAULT_NUM_TX_FREELIST); 3281 3282 /* 3283 * FlowControl 3284 */ 3285 hw->fc.send_xon = B_TRUE; 3286 hw->fc.type = 3287 e1000g_get_prop(Adapter, "FlowControl", 3288 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3289 /* 4 is the setting that says "let the eeprom decide" */ 3290 if (hw->fc.type == 4) 3291 hw->fc.type = e1000_fc_default; 3292 3293 /* 3294 * Max Num Receive Packets on Interrupt 3295 */ 3296 Adapter->rx_limit_onintr = 3297 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3298 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3299 DEFAULT_RX_LIMIT_ON_INTR); 3300 3301 /* 3302 * PHY master slave setting 3303 */ 3304 hw->phy.ms_type = 3305 e1000g_get_prop(Adapter, "SetMasterSlave", 3306 e1000_ms_hw_default, e1000_ms_auto, 3307 e1000_ms_hw_default); 3308 3309 /* 3310 * Parameter which controls TBI mode workaround, which is only 3311 * needed on certain switches such as Cisco 6500/Foundry 3312 */ 3313 tbi_compatibility = 3314 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3315 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3316 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3317 3318 /* 3319 * MSI Enable 3320 */ 3321 Adapter->msi_enable = 3322 e1000g_get_prop(Adapter, "MSIEnable", 3323 0, 1, DEFAULT_MSI_ENABLE); 3324 3325 /* 3326 * Interrupt Throttling Rate 3327 */ 3328 Adapter->intr_throttling_rate = 3329 e1000g_get_prop(Adapter, "intr_throttling_rate", 3330 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3331 DEFAULT_INTR_THROTTLING); 3332 3333 /* 3334 * Adaptive Interrupt Blanking Enable/Disable 3335 * It is enabled by default 3336 */ 3337 Adapter->intr_adaptive = 3338 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3339 B_TRUE : B_FALSE; 3340 3341 /* 3342 * Tx recycle threshold 3343 */ 3344 Adapter->tx_recycle_thresh = 3345 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3346 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3347 DEFAULT_TX_RECYCLE_THRESHOLD); 3348 3349 /* 3350 * Tx recycle descriptor number 3351 */ 3352 Adapter->tx_recycle_num = 3353 e1000g_get_prop(Adapter, "tx_recycle_num", 3354 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3355 DEFAULT_TX_RECYCLE_NUM); 3356 3357 /* 3358 * Hardware checksum enable/disable parameter 3359 */ 3360 Adapter->tx_hcksum_enable = 3361 e1000g_get_prop(Adapter, "tx_hcksum_enable", 3362 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3363 /* 3364 * Checksum on/off selection via global parameters. 3365 * 3366 * If the chip is flagged as not capable of (correctly) 3367 * handling checksumming, we don't enable it on either 3368 * Rx or Tx side. Otherwise, we take this chip's settings 3369 * from the patchable global defaults. 3370 * 3371 * We advertise our capabilities only if TX offload is 3372 * enabled. On receive, the stack will accept checksummed 3373 * packets anyway, even if we haven't said we can deliver 3374 * them. 3375 */ 3376 switch (hw->mac.type) { 3377 case e1000_82540: 3378 case e1000_82544: 3379 case e1000_82545: 3380 case e1000_82545_rev_3: 3381 case e1000_82546: 3382 case e1000_82546_rev_3: 3383 case e1000_82571: 3384 case e1000_82572: 3385 case e1000_82573: 3386 case e1000_80003es2lan: 3387 break; 3388 /* 3389 * For the following Intel PRO/1000 chipsets, we have not 3390 * tested the hardware checksum offload capability, so we 3391 * disable the capability for them. 3392 * e1000_82542, 3393 * e1000_82543, 3394 * e1000_82541, 3395 * e1000_82541_rev_2, 3396 * e1000_82547, 3397 * e1000_82547_rev_2, 3398 */ 3399 default: 3400 Adapter->tx_hcksum_enable = B_FALSE; 3401 } 3402 3403 /* 3404 * Large Send Offloading(LSO) Enable/Disable 3405 * If the tx hardware checksum is not enabled, LSO should be 3406 * disabled. 3407 */ 3408 Adapter->lso_enable = 3409 e1000g_get_prop(Adapter, "lso_enable", 3410 0, 1, DEFAULT_LSO_ENABLE); 3411 3412 switch (hw->mac.type) { 3413 case e1000_82546: 3414 case e1000_82546_rev_3: 3415 if (Adapter->lso_enable) 3416 Adapter->lso_premature_issue = B_TRUE; 3417 /* FALLTHRU */ 3418 case e1000_82571: 3419 case e1000_82572: 3420 case e1000_82573: 3421 break; 3422 default: 3423 Adapter->lso_enable = B_FALSE; 3424 } 3425 3426 if (!Adapter->tx_hcksum_enable) { 3427 Adapter->lso_premature_issue = B_FALSE; 3428 Adapter->lso_enable = B_FALSE; 3429 } 3430 } 3431 3432 /* 3433 * e1000g_get_prop - routine to read properties 3434 * 3435 * Get a user-configure property value out of the configuration 3436 * file e1000g.conf. 3437 * 3438 * Caller provides name of the property, a default value, a minimum 3439 * value, and a maximum value. 3440 * 3441 * Return configured value of the property, with default, minimum and 3442 * maximum properly applied. 3443 */ 3444 static int 3445 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3446 char *propname, /* name of the property */ 3447 int minval, /* minimum acceptable value */ 3448 int maxval, /* maximim acceptable value */ 3449 int defval) /* default value */ 3450 { 3451 int propval; /* value returned for requested property */ 3452 int *props; /* point to array of properties returned */ 3453 uint_t nprops; /* number of property value returned */ 3454 3455 /* 3456 * get the array of properties from the config file 3457 */ 3458 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3459 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3460 /* got some properties, test if we got enough */ 3461 if (Adapter->instance < nprops) { 3462 propval = props[Adapter->instance]; 3463 } else { 3464 /* not enough properties configured */ 3465 propval = defval; 3466 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3467 "Not Enough %s values found in e1000g.conf" 3468 " - set to %d\n", 3469 propname, propval); 3470 } 3471 3472 /* free memory allocated for properties */ 3473 ddi_prop_free(props); 3474 3475 } else { 3476 propval = defval; 3477 } 3478 3479 /* 3480 * enforce limits 3481 */ 3482 if (propval > maxval) { 3483 propval = maxval; 3484 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3485 "Too High %s value in e1000g.conf - set to %d\n", 3486 propname, propval); 3487 } 3488 3489 if (propval < minval) { 3490 propval = minval; 3491 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3492 "Too Low %s value in e1000g.conf - set to %d\n", 3493 propname, propval); 3494 } 3495 3496 return (propval); 3497 } 3498 3499 static boolean_t 3500 e1000g_link_check(struct e1000g *Adapter) 3501 { 3502 uint16_t speed, duplex, phydata; 3503 boolean_t link_changed = B_FALSE; 3504 struct e1000_hw *hw; 3505 uint32_t reg_tarc; 3506 3507 hw = &Adapter->shared; 3508 3509 if (e1000g_link_up(Adapter)) { 3510 /* 3511 * The Link is up, check whether it was marked as down earlier 3512 */ 3513 if (Adapter->link_state != LINK_STATE_UP) { 3514 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 3515 Adapter->link_speed = speed; 3516 Adapter->link_duplex = duplex; 3517 Adapter->link_state = LINK_STATE_UP; 3518 link_changed = B_TRUE; 3519 3520 Adapter->tx_link_down_timeout = 0; 3521 3522 if ((hw->mac.type == e1000_82571) || 3523 (hw->mac.type == e1000_82572)) { 3524 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 3525 if (speed == SPEED_1000) 3526 reg_tarc |= (1 << 21); 3527 else 3528 reg_tarc &= ~(1 << 21); 3529 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 3530 } 3531 } 3532 Adapter->smartspeed = 0; 3533 } else { 3534 if (Adapter->link_state != LINK_STATE_DOWN) { 3535 Adapter->link_speed = 0; 3536 Adapter->link_duplex = 0; 3537 Adapter->link_state = LINK_STATE_DOWN; 3538 link_changed = B_TRUE; 3539 3540 /* 3541 * SmartSpeed workaround for Tabor/TanaX, When the 3542 * driver loses link disable auto master/slave 3543 * resolution. 3544 */ 3545 if (hw->phy.type == e1000_phy_igp) { 3546 (void) e1000_read_phy_reg(hw, 3547 PHY_1000T_CTRL, &phydata); 3548 phydata |= CR_1000T_MS_ENABLE; 3549 (void) e1000_write_phy_reg(hw, 3550 PHY_1000T_CTRL, phydata); 3551 } 3552 } else { 3553 e1000g_smartspeed(Adapter); 3554 } 3555 3556 if (Adapter->chip_state == E1000G_START) { 3557 if (Adapter->tx_link_down_timeout < 3558 MAX_TX_LINK_DOWN_TIMEOUT) { 3559 Adapter->tx_link_down_timeout++; 3560 } else if (Adapter->tx_link_down_timeout == 3561 MAX_TX_LINK_DOWN_TIMEOUT) { 3562 e1000g_tx_clean(Adapter); 3563 Adapter->tx_link_down_timeout++; 3564 } 3565 } 3566 } 3567 3568 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3569 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3570 3571 return (link_changed); 3572 } 3573 3574 /* 3575 * e1000g_reset_link - Using the link properties to setup the link 3576 */ 3577 int 3578 e1000g_reset_link(struct e1000g *Adapter) 3579 { 3580 struct e1000_mac_info *mac; 3581 struct e1000_phy_info *phy; 3582 boolean_t invalid; 3583 3584 mac = &Adapter->shared.mac; 3585 phy = &Adapter->shared.phy; 3586 invalid = B_FALSE; 3587 3588 if (Adapter->param_adv_autoneg == 1) { 3589 mac->autoneg = B_TRUE; 3590 phy->autoneg_advertised = 0; 3591 3592 /* 3593 * 1000hdx is not supported for autonegotiation 3594 */ 3595 if (Adapter->param_adv_1000fdx == 1) 3596 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3597 3598 if (Adapter->param_adv_100fdx == 1) 3599 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3600 3601 if (Adapter->param_adv_100hdx == 1) 3602 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3603 3604 if (Adapter->param_adv_10fdx == 1) 3605 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3606 3607 if (Adapter->param_adv_10hdx == 1) 3608 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3609 3610 if (phy->autoneg_advertised == 0) 3611 invalid = B_TRUE; 3612 } else { 3613 mac->autoneg = B_FALSE; 3614 3615 /* 3616 * 1000fdx and 1000hdx are not supported for forced link 3617 */ 3618 if (Adapter->param_adv_100fdx == 1) 3619 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3620 else if (Adapter->param_adv_100hdx == 1) 3621 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3622 else if (Adapter->param_adv_10fdx == 1) 3623 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3624 else if (Adapter->param_adv_10hdx == 1) 3625 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3626 else 3627 invalid = B_TRUE; 3628 3629 } 3630 3631 if (invalid) { 3632 e1000g_log(Adapter, CE_WARN, 3633 "Invalid link sets. Setup link to" 3634 "support autonegotiation with all link capabilities."); 3635 mac->autoneg = B_TRUE; 3636 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3637 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3638 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3639 } 3640 3641 return (e1000_setup_link(&Adapter->shared)); 3642 } 3643 3644 static void 3645 e1000g_local_timer(void *ws) 3646 { 3647 struct e1000g *Adapter = (struct e1000g *)ws; 3648 struct e1000_hw *hw; 3649 e1000g_ether_addr_t ether_addr; 3650 boolean_t link_changed; 3651 3652 hw = &Adapter->shared; 3653 3654 if (Adapter->chip_state == E1000G_ERROR) { 3655 Adapter->reset_count++; 3656 if (e1000g_global_reset(Adapter)) 3657 ddi_fm_service_impact(Adapter->dip, 3658 DDI_SERVICE_RESTORED); 3659 else 3660 ddi_fm_service_impact(Adapter->dip, 3661 DDI_SERVICE_LOST); 3662 return; 3663 } 3664 3665 if (e1000g_stall_check(Adapter)) { 3666 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3667 "Tx stall detected. Activate automatic recovery.\n"); 3668 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3669 Adapter->reset_count++; 3670 if (e1000g_reset_adapter(Adapter)) 3671 ddi_fm_service_impact(Adapter->dip, 3672 DDI_SERVICE_RESTORED); 3673 else 3674 ddi_fm_service_impact(Adapter->dip, 3675 DDI_SERVICE_LOST); 3676 return; 3677 } 3678 3679 link_changed = B_FALSE; 3680 rw_enter(&Adapter->chip_lock, RW_READER); 3681 if (Adapter->link_complete) 3682 link_changed = e1000g_link_check(Adapter); 3683 rw_exit(&Adapter->chip_lock); 3684 3685 if (link_changed) 3686 mac_link_update(Adapter->mh, Adapter->link_state); 3687 3688 /* 3689 * Workaround for esb2. Data stuck in fifo on a link 3690 * down event. Reset the adapter to recover it. 3691 */ 3692 if (Adapter->esb2_workaround) { 3693 Adapter->esb2_workaround = B_FALSE; 3694 (void) e1000g_reset_adapter(Adapter); 3695 } 3696 3697 /* 3698 * With 82571 controllers, any locally administered address will 3699 * be overwritten when there is a reset on the other port. 3700 * Detect this circumstance and correct it. 3701 */ 3702 if ((hw->mac.type == e1000_82571) && 3703 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3704 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3705 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3706 3707 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3708 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3709 3710 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3711 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3712 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3713 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3714 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3715 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3716 e1000_rar_set(hw, hw->mac.addr, 0); 3717 } 3718 } 3719 3720 /* 3721 * Long TTL workaround for 82541/82547 3722 */ 3723 (void) e1000_igp_ttl_workaround_82547(hw); 3724 3725 /* 3726 * Check for Adaptive IFS settings If there are lots of collisions 3727 * change the value in steps... 3728 * These properties should only be set for 10/100 3729 */ 3730 if ((hw->phy.media_type == e1000_media_type_copper) && 3731 ((Adapter->link_speed == SPEED_100) || 3732 (Adapter->link_speed == SPEED_10))) { 3733 e1000_update_adaptive(hw); 3734 } 3735 /* 3736 * Set Timer Interrupts 3737 */ 3738 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3739 3740 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3741 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3742 3743 restart_watchdog_timer(Adapter); 3744 } 3745 3746 /* 3747 * The function e1000g_link_timer() is called when the timer for link setup 3748 * is expired, which indicates the completion of the link setup. The link 3749 * state will not be updated until the link setup is completed. And the 3750 * link state will not be sent to the upper layer through mac_link_update() 3751 * in this function. It will be updated in the local timer routine or the 3752 * interrupt service routine after the interface is started (plumbed). 3753 */ 3754 static void 3755 e1000g_link_timer(void *arg) 3756 { 3757 struct e1000g *Adapter = (struct e1000g *)arg; 3758 3759 mutex_enter(&Adapter->link_lock); 3760 Adapter->link_complete = B_TRUE; 3761 Adapter->link_tid = 0; 3762 mutex_exit(&Adapter->link_lock); 3763 } 3764 3765 /* 3766 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3767 * 3768 * This function read the forced speed and duplex for 10/100 Mbps speeds 3769 * and also for 1000 Mbps speeds from the e1000g.conf file 3770 */ 3771 static void 3772 e1000g_force_speed_duplex(struct e1000g *Adapter) 3773 { 3774 int forced; 3775 struct e1000_mac_info *mac = &Adapter->shared.mac; 3776 struct e1000_phy_info *phy = &Adapter->shared.phy; 3777 3778 /* 3779 * get value out of config file 3780 */ 3781 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3782 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3783 3784 switch (forced) { 3785 case GDIAG_10_HALF: 3786 /* 3787 * Disable Auto Negotiation 3788 */ 3789 mac->autoneg = B_FALSE; 3790 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3791 break; 3792 case GDIAG_10_FULL: 3793 /* 3794 * Disable Auto Negotiation 3795 */ 3796 mac->autoneg = B_FALSE; 3797 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3798 break; 3799 case GDIAG_100_HALF: 3800 /* 3801 * Disable Auto Negotiation 3802 */ 3803 mac->autoneg = B_FALSE; 3804 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3805 break; 3806 case GDIAG_100_FULL: 3807 /* 3808 * Disable Auto Negotiation 3809 */ 3810 mac->autoneg = B_FALSE; 3811 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3812 break; 3813 case GDIAG_1000_FULL: 3814 /* 3815 * The gigabit spec requires autonegotiation. Therefore, 3816 * when the user wants to force the speed to 1000Mbps, we 3817 * enable AutoNeg, but only allow the harware to advertise 3818 * 1000Mbps. This is different from 10/100 operation, where 3819 * we are allowed to link without any negotiation. 3820 */ 3821 mac->autoneg = B_TRUE; 3822 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3823 break; 3824 default: /* obey the setting of AutoNegAdvertised */ 3825 mac->autoneg = B_TRUE; 3826 phy->autoneg_advertised = 3827 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3828 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3829 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3830 break; 3831 } /* switch */ 3832 } 3833 3834 /* 3835 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3836 * 3837 * This function reads MaxFrameSize from e1000g.conf 3838 */ 3839 static void 3840 e1000g_get_max_frame_size(struct e1000g *Adapter) 3841 { 3842 int max_frame; 3843 struct e1000_mac_info *mac = &Adapter->shared.mac; 3844 struct e1000_phy_info *phy = &Adapter->shared.phy; 3845 3846 /* 3847 * get value out of config file 3848 */ 3849 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3850 3851 switch (max_frame) { 3852 case 0: 3853 Adapter->default_mtu = ETHERMTU; 3854 break; 3855 /* 3856 * To avoid excessive memory allocation for rx buffers, 3857 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3858 */ 3859 case 1: 3860 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3861 sizeof (struct ether_vlan_header) - ETHERFCSL - 3862 E1000G_IPALIGNPRESERVEROOM; 3863 break; 3864 case 2: 3865 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3866 sizeof (struct ether_vlan_header) - ETHERFCSL - 3867 E1000G_IPALIGNPRESERVEROOM; 3868 break; 3869 case 3: 3870 if (mac->type >= e1000_82571) 3871 Adapter->default_mtu = MAXIMUM_MTU; 3872 else 3873 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3874 sizeof (struct ether_vlan_header) - ETHERFCSL - 3875 E1000G_IPALIGNPRESERVEROOM; 3876 break; 3877 default: 3878 Adapter->default_mtu = ETHERMTU; 3879 break; 3880 } /* switch */ 3881 3882 Adapter->max_frame_size = Adapter->default_mtu + 3883 sizeof (struct ether_vlan_header) + ETHERFCSL; 3884 3885 /* ich8 does not do jumbo frames */ 3886 if (mac->type == e1000_ich8lan) { 3887 Adapter->max_frame_size = ETHERMTU + 3888 sizeof (struct ether_vlan_header) + ETHERFCSL; 3889 } 3890 3891 /* ich9 does not do jumbo frames on one phy type */ 3892 if ((mac->type == e1000_ich9lan) && 3893 (phy->type == e1000_phy_ife)) { 3894 Adapter->max_frame_size = ETHERMTU + 3895 sizeof (struct ether_vlan_header) + ETHERFCSL; 3896 } 3897 } 3898 3899 static void 3900 arm_watchdog_timer(struct e1000g *Adapter) 3901 { 3902 Adapter->watchdog_tid = 3903 timeout(e1000g_local_timer, 3904 (void *)Adapter, 1 * drv_usectohz(1000000)); 3905 } 3906 #pragma inline(arm_watchdog_timer) 3907 3908 static void 3909 enable_watchdog_timer(struct e1000g *Adapter) 3910 { 3911 mutex_enter(&Adapter->watchdog_lock); 3912 3913 if (!Adapter->watchdog_timer_enabled) { 3914 Adapter->watchdog_timer_enabled = B_TRUE; 3915 Adapter->watchdog_timer_started = B_TRUE; 3916 arm_watchdog_timer(Adapter); 3917 } 3918 3919 mutex_exit(&Adapter->watchdog_lock); 3920 } 3921 3922 static void 3923 disable_watchdog_timer(struct e1000g *Adapter) 3924 { 3925 timeout_id_t tid; 3926 3927 mutex_enter(&Adapter->watchdog_lock); 3928 3929 Adapter->watchdog_timer_enabled = B_FALSE; 3930 Adapter->watchdog_timer_started = B_FALSE; 3931 tid = Adapter->watchdog_tid; 3932 Adapter->watchdog_tid = 0; 3933 3934 mutex_exit(&Adapter->watchdog_lock); 3935 3936 if (tid != 0) 3937 (void) untimeout(tid); 3938 } 3939 3940 static void 3941 start_watchdog_timer(struct e1000g *Adapter) 3942 { 3943 mutex_enter(&Adapter->watchdog_lock); 3944 3945 if (Adapter->watchdog_timer_enabled) { 3946 if (!Adapter->watchdog_timer_started) { 3947 Adapter->watchdog_timer_started = B_TRUE; 3948 arm_watchdog_timer(Adapter); 3949 } 3950 } 3951 3952 mutex_exit(&Adapter->watchdog_lock); 3953 } 3954 3955 static void 3956 restart_watchdog_timer(struct e1000g *Adapter) 3957 { 3958 mutex_enter(&Adapter->watchdog_lock); 3959 3960 if (Adapter->watchdog_timer_started) 3961 arm_watchdog_timer(Adapter); 3962 3963 mutex_exit(&Adapter->watchdog_lock); 3964 } 3965 3966 static void 3967 stop_watchdog_timer(struct e1000g *Adapter) 3968 { 3969 timeout_id_t tid; 3970 3971 mutex_enter(&Adapter->watchdog_lock); 3972 3973 Adapter->watchdog_timer_started = B_FALSE; 3974 tid = Adapter->watchdog_tid; 3975 Adapter->watchdog_tid = 0; 3976 3977 mutex_exit(&Adapter->watchdog_lock); 3978 3979 if (tid != 0) 3980 (void) untimeout(tid); 3981 } 3982 3983 static void 3984 stop_link_timer(struct e1000g *Adapter) 3985 { 3986 timeout_id_t tid; 3987 3988 /* Disable the link timer */ 3989 mutex_enter(&Adapter->link_lock); 3990 3991 tid = Adapter->link_tid; 3992 Adapter->link_tid = 0; 3993 3994 mutex_exit(&Adapter->link_lock); 3995 3996 if (tid != 0) 3997 (void) untimeout(tid); 3998 } 3999 4000 static void 4001 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4002 { 4003 timeout_id_t tid; 4004 4005 /* Disable the tx timer for 82547 chipset */ 4006 mutex_enter(&tx_ring->tx_lock); 4007 4008 tx_ring->timer_enable_82547 = B_FALSE; 4009 tid = tx_ring->timer_id_82547; 4010 tx_ring->timer_id_82547 = 0; 4011 4012 mutex_exit(&tx_ring->tx_lock); 4013 4014 if (tid != 0) 4015 (void) untimeout(tid); 4016 } 4017 4018 void 4019 e1000g_clear_interrupt(struct e1000g *Adapter) 4020 { 4021 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4022 0xffffffff & ~E1000_IMS_RXSEQ); 4023 } 4024 4025 void 4026 e1000g_mask_interrupt(struct e1000g *Adapter) 4027 { 4028 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4029 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4030 4031 if (Adapter->tx_intr_enable) 4032 e1000g_mask_tx_interrupt(Adapter); 4033 } 4034 4035 /* 4036 * This routine is called by e1000g_quiesce(), therefore must not block. 4037 */ 4038 void 4039 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4040 { 4041 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4042 } 4043 4044 void 4045 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4046 { 4047 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4048 } 4049 4050 void 4051 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4052 { 4053 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4054 } 4055 4056 static void 4057 e1000g_smartspeed(struct e1000g *Adapter) 4058 { 4059 struct e1000_hw *hw = &Adapter->shared; 4060 uint16_t phy_status; 4061 uint16_t phy_ctrl; 4062 4063 /* 4064 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4065 * advertising 1000Full, we don't even use the workaround 4066 */ 4067 if ((hw->phy.type != e1000_phy_igp) || 4068 !hw->mac.autoneg || 4069 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4070 return; 4071 4072 /* 4073 * True if this is the first call of this function or after every 4074 * 30 seconds of not having link 4075 */ 4076 if (Adapter->smartspeed == 0) { 4077 /* 4078 * If Master/Slave config fault is asserted twice, we 4079 * assume back-to-back 4080 */ 4081 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4082 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4083 return; 4084 4085 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4086 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4087 return; 4088 /* 4089 * We're assuming back-2-back because our status register 4090 * insists! there's a fault in the master/slave 4091 * relationship that was "negotiated" 4092 */ 4093 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4094 /* 4095 * Is the phy configured for manual configuration of 4096 * master/slave? 4097 */ 4098 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4099 /* 4100 * Yes. Then disable manual configuration (enable 4101 * auto configuration) of master/slave 4102 */ 4103 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4104 (void) e1000_write_phy_reg(hw, 4105 PHY_1000T_CTRL, phy_ctrl); 4106 /* 4107 * Effectively starting the clock 4108 */ 4109 Adapter->smartspeed++; 4110 /* 4111 * Restart autonegotiation 4112 */ 4113 if (!e1000_phy_setup_autoneg(hw) && 4114 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4115 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4116 MII_CR_RESTART_AUTO_NEG); 4117 (void) e1000_write_phy_reg(hw, 4118 PHY_CONTROL, phy_ctrl); 4119 } 4120 } 4121 return; 4122 /* 4123 * Has 6 seconds transpired still without link? Remember, 4124 * you should reset the smartspeed counter once you obtain 4125 * link 4126 */ 4127 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4128 /* 4129 * Yes. Remember, we did at the start determine that 4130 * there's a master/slave configuration fault, so we're 4131 * still assuming there's someone on the other end, but we 4132 * just haven't yet been able to talk to it. We then 4133 * re-enable auto configuration of master/slave to see if 4134 * we're running 2/3 pair cables. 4135 */ 4136 /* 4137 * If still no link, perhaps using 2/3 pair cable 4138 */ 4139 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4140 phy_ctrl |= CR_1000T_MS_ENABLE; 4141 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4142 /* 4143 * Restart autoneg with phy enabled for manual 4144 * configuration of master/slave 4145 */ 4146 if (!e1000_phy_setup_autoneg(hw) && 4147 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4148 phy_ctrl |= 4149 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4150 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4151 } 4152 /* 4153 * Hopefully, there are no more faults and we've obtained 4154 * link as a result. 4155 */ 4156 } 4157 /* 4158 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4159 * seconds) 4160 */ 4161 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4162 Adapter->smartspeed = 0; 4163 } 4164 4165 static boolean_t 4166 is_valid_mac_addr(uint8_t *mac_addr) 4167 { 4168 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4169 const uint8_t addr_test2[6] = 4170 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4171 4172 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4173 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4174 return (B_FALSE); 4175 4176 return (B_TRUE); 4177 } 4178 4179 /* 4180 * e1000g_stall_check - check for tx stall 4181 * 4182 * This function checks if the adapter is stalled (in transmit). 4183 * 4184 * It is called each time the watchdog timeout is invoked. 4185 * If the transmit descriptor reclaim continuously fails, 4186 * the watchdog value will increment by 1. If the watchdog 4187 * value exceeds the threshold, the adapter is assumed to 4188 * have stalled and need to be reset. 4189 */ 4190 static boolean_t 4191 e1000g_stall_check(struct e1000g *Adapter) 4192 { 4193 e1000g_tx_ring_t *tx_ring; 4194 4195 tx_ring = Adapter->tx_ring; 4196 4197 if (Adapter->link_state != LINK_STATE_UP) 4198 return (B_FALSE); 4199 4200 if (tx_ring->recycle_fail > 0) 4201 tx_ring->stall_watchdog++; 4202 else 4203 tx_ring->stall_watchdog = 0; 4204 4205 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4206 return (B_FALSE); 4207 4208 tx_ring->stall_watchdog = 0; 4209 tx_ring->recycle_fail = 0; 4210 4211 return (B_TRUE); 4212 } 4213 4214 #ifdef E1000G_DEBUG 4215 static enum ioc_reply 4216 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4217 { 4218 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4219 e1000g_peekpoke_t *ppd; 4220 uint64_t mem_va; 4221 uint64_t maxoff; 4222 boolean_t peek; 4223 4224 switch (iocp->ioc_cmd) { 4225 4226 case E1000G_IOC_REG_PEEK: 4227 peek = B_TRUE; 4228 break; 4229 4230 case E1000G_IOC_REG_POKE: 4231 peek = B_FALSE; 4232 break; 4233 4234 deault: 4235 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4236 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4237 iocp->ioc_cmd); 4238 return (IOC_INVAL); 4239 } 4240 4241 /* 4242 * Validate format of ioctl 4243 */ 4244 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4245 return (IOC_INVAL); 4246 if (mp->b_cont == NULL) 4247 return (IOC_INVAL); 4248 4249 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4250 4251 /* 4252 * Validate request parameters 4253 */ 4254 switch (ppd->pp_acc_space) { 4255 4256 default: 4257 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4258 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4259 ppd->pp_acc_space); 4260 return (IOC_INVAL); 4261 4262 case E1000G_PP_SPACE_REG: 4263 /* 4264 * Memory-mapped I/O space 4265 */ 4266 ASSERT(ppd->pp_acc_size == 4); 4267 if (ppd->pp_acc_size != 4) 4268 return (IOC_INVAL); 4269 4270 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4271 return (IOC_INVAL); 4272 4273 mem_va = 0; 4274 maxoff = 0x10000; 4275 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4276 break; 4277 4278 case E1000G_PP_SPACE_E1000G: 4279 /* 4280 * E1000g data structure! 4281 */ 4282 mem_va = (uintptr_t)e1000gp; 4283 maxoff = sizeof (struct e1000g); 4284 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4285 break; 4286 4287 } 4288 4289 if (ppd->pp_acc_offset >= maxoff) 4290 return (IOC_INVAL); 4291 4292 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4293 return (IOC_INVAL); 4294 4295 /* 4296 * All OK - go! 4297 */ 4298 ppd->pp_acc_offset += mem_va; 4299 (*ppfn)(e1000gp, ppd); 4300 return (peek ? IOC_REPLY : IOC_ACK); 4301 } 4302 4303 static void 4304 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4305 { 4306 ddi_acc_handle_t handle; 4307 uint32_t *regaddr; 4308 4309 handle = e1000gp->osdep.reg_handle; 4310 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4311 (uintptr_t)ppd->pp_acc_offset); 4312 4313 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4314 } 4315 4316 static void 4317 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4318 { 4319 ddi_acc_handle_t handle; 4320 uint32_t *regaddr; 4321 uint32_t value; 4322 4323 handle = e1000gp->osdep.reg_handle; 4324 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4325 (uintptr_t)ppd->pp_acc_offset); 4326 value = (uint32_t)ppd->pp_acc_data; 4327 4328 ddi_put32(handle, regaddr, value); 4329 } 4330 4331 static void 4332 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4333 { 4334 uint64_t value; 4335 void *vaddr; 4336 4337 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4338 4339 switch (ppd->pp_acc_size) { 4340 case 1: 4341 value = *(uint8_t *)vaddr; 4342 break; 4343 4344 case 2: 4345 value = *(uint16_t *)vaddr; 4346 break; 4347 4348 case 4: 4349 value = *(uint32_t *)vaddr; 4350 break; 4351 4352 case 8: 4353 value = *(uint64_t *)vaddr; 4354 break; 4355 } 4356 4357 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4358 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4359 (void *)e1000gp, (void *)ppd, value, vaddr); 4360 4361 ppd->pp_acc_data = value; 4362 } 4363 4364 static void 4365 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4366 { 4367 uint64_t value; 4368 void *vaddr; 4369 4370 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4371 value = ppd->pp_acc_data; 4372 4373 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4374 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4375 (void *)e1000gp, (void *)ppd, value, vaddr); 4376 4377 switch (ppd->pp_acc_size) { 4378 case 1: 4379 *(uint8_t *)vaddr = (uint8_t)value; 4380 break; 4381 4382 case 2: 4383 *(uint16_t *)vaddr = (uint16_t)value; 4384 break; 4385 4386 case 4: 4387 *(uint32_t *)vaddr = (uint32_t)value; 4388 break; 4389 4390 case 8: 4391 *(uint64_t *)vaddr = (uint64_t)value; 4392 break; 4393 } 4394 } 4395 #endif 4396 4397 /* 4398 * Loopback Support 4399 */ 4400 static lb_property_t lb_normal = 4401 { normal, "normal", E1000G_LB_NONE }; 4402 static lb_property_t lb_external1000 = 4403 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4404 static lb_property_t lb_external100 = 4405 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4406 static lb_property_t lb_external10 = 4407 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4408 static lb_property_t lb_phy = 4409 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4410 4411 static enum ioc_reply 4412 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4413 { 4414 lb_info_sz_t *lbsp; 4415 lb_property_t *lbpp; 4416 struct e1000_hw *hw; 4417 uint32_t *lbmp; 4418 uint32_t size; 4419 uint32_t value; 4420 4421 hw = &Adapter->shared; 4422 4423 if (mp->b_cont == NULL) 4424 return (IOC_INVAL); 4425 4426 if (!e1000g_check_loopback_support(hw)) { 4427 e1000g_log(NULL, CE_WARN, 4428 "Loopback is not supported on e1000g%d", Adapter->instance); 4429 return (IOC_INVAL); 4430 } 4431 4432 switch (iocp->ioc_cmd) { 4433 default: 4434 return (IOC_INVAL); 4435 4436 case LB_GET_INFO_SIZE: 4437 size = sizeof (lb_info_sz_t); 4438 if (iocp->ioc_count != size) 4439 return (IOC_INVAL); 4440 4441 rw_enter(&Adapter->chip_lock, RW_WRITER); 4442 e1000g_get_phy_state(Adapter); 4443 4444 /* 4445 * Workaround for hardware faults. In order to get a stable 4446 * state of phy, we will wait for a specific interval and 4447 * try again. The time delay is an experiential value based 4448 * on our testing. 4449 */ 4450 msec_delay(100); 4451 e1000g_get_phy_state(Adapter); 4452 rw_exit(&Adapter->chip_lock); 4453 4454 value = sizeof (lb_normal); 4455 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4456 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4457 (hw->phy.media_type == e1000_media_type_fiber) || 4458 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4459 value += sizeof (lb_phy); 4460 switch (hw->mac.type) { 4461 case e1000_82571: 4462 case e1000_82572: 4463 case e1000_80003es2lan: 4464 value += sizeof (lb_external1000); 4465 break; 4466 } 4467 } 4468 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4469 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4470 value += sizeof (lb_external100); 4471 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4472 value += sizeof (lb_external10); 4473 4474 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 4475 *lbsp = value; 4476 break; 4477 4478 case LB_GET_INFO: 4479 value = sizeof (lb_normal); 4480 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4481 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4482 (hw->phy.media_type == e1000_media_type_fiber) || 4483 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4484 value += sizeof (lb_phy); 4485 switch (hw->mac.type) { 4486 case e1000_82571: 4487 case e1000_82572: 4488 case e1000_80003es2lan: 4489 value += sizeof (lb_external1000); 4490 break; 4491 } 4492 } 4493 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4494 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4495 value += sizeof (lb_external100); 4496 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4497 value += sizeof (lb_external10); 4498 4499 size = value; 4500 if (iocp->ioc_count != size) 4501 return (IOC_INVAL); 4502 4503 value = 0; 4504 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 4505 lbpp[value++] = lb_normal; 4506 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4507 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4508 (hw->phy.media_type == e1000_media_type_fiber) || 4509 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 4510 lbpp[value++] = lb_phy; 4511 switch (hw->mac.type) { 4512 case e1000_82571: 4513 case e1000_82572: 4514 case e1000_80003es2lan: 4515 lbpp[value++] = lb_external1000; 4516 break; 4517 } 4518 } 4519 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4520 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4521 lbpp[value++] = lb_external100; 4522 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4523 lbpp[value++] = lb_external10; 4524 break; 4525 4526 case LB_GET_MODE: 4527 size = sizeof (uint32_t); 4528 if (iocp->ioc_count != size) 4529 return (IOC_INVAL); 4530 4531 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4532 *lbmp = Adapter->loopback_mode; 4533 break; 4534 4535 case LB_SET_MODE: 4536 size = 0; 4537 if (iocp->ioc_count != sizeof (uint32_t)) 4538 return (IOC_INVAL); 4539 4540 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 4541 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4542 return (IOC_INVAL); 4543 break; 4544 } 4545 4546 iocp->ioc_count = size; 4547 iocp->ioc_error = 0; 4548 4549 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4550 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4551 return (IOC_INVAL); 4552 } 4553 4554 return (IOC_REPLY); 4555 } 4556 4557 static boolean_t 4558 e1000g_check_loopback_support(struct e1000_hw *hw) 4559 { 4560 switch (hw->mac.type) { 4561 case e1000_82540: 4562 case e1000_82545: 4563 case e1000_82545_rev_3: 4564 case e1000_82546: 4565 case e1000_82546_rev_3: 4566 case e1000_82541: 4567 case e1000_82541_rev_2: 4568 case e1000_82547: 4569 case e1000_82547_rev_2: 4570 case e1000_82571: 4571 case e1000_82572: 4572 case e1000_82573: 4573 case e1000_80003es2lan: 4574 return (B_TRUE); 4575 } 4576 return (B_FALSE); 4577 } 4578 4579 static boolean_t 4580 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4581 { 4582 struct e1000_hw *hw; 4583 int i, times; 4584 boolean_t link_up; 4585 4586 if (mode == Adapter->loopback_mode) 4587 return (B_TRUE); 4588 4589 hw = &Adapter->shared; 4590 times = 0; 4591 4592 Adapter->loopback_mode = mode; 4593 4594 if (mode == E1000G_LB_NONE) { 4595 /* Reset the chip */ 4596 hw->phy.autoneg_wait_to_complete = B_TRUE; 4597 (void) e1000g_reset_adapter(Adapter); 4598 hw->phy.autoneg_wait_to_complete = B_FALSE; 4599 return (B_TRUE); 4600 } 4601 4602 again: 4603 4604 rw_enter(&Adapter->chip_lock, RW_WRITER); 4605 4606 switch (mode) { 4607 default: 4608 rw_exit(&Adapter->chip_lock); 4609 return (B_FALSE); 4610 4611 case E1000G_LB_EXTERNAL_1000: 4612 e1000g_set_external_loopback_1000(Adapter); 4613 break; 4614 4615 case E1000G_LB_EXTERNAL_100: 4616 e1000g_set_external_loopback_100(Adapter); 4617 break; 4618 4619 case E1000G_LB_EXTERNAL_10: 4620 e1000g_set_external_loopback_10(Adapter); 4621 break; 4622 4623 case E1000G_LB_INTERNAL_PHY: 4624 e1000g_set_internal_loopback(Adapter); 4625 break; 4626 } 4627 4628 times++; 4629 4630 rw_exit(&Adapter->chip_lock); 4631 4632 /* Wait for link up */ 4633 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4634 msec_delay(100); 4635 4636 rw_enter(&Adapter->chip_lock, RW_WRITER); 4637 4638 link_up = e1000g_link_up(Adapter); 4639 4640 rw_exit(&Adapter->chip_lock); 4641 4642 if (!link_up) { 4643 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4644 "Failed to get the link up"); 4645 if (times < 2) { 4646 /* Reset the link */ 4647 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4648 "Reset the link ..."); 4649 (void) e1000g_reset_adapter(Adapter); 4650 goto again; 4651 } 4652 } 4653 4654 return (B_TRUE); 4655 } 4656 4657 /* 4658 * The following loopback settings are from Intel's technical 4659 * document - "How To Loopback". All the register settings and 4660 * time delay values are directly inherited from the document 4661 * without more explanations available. 4662 */ 4663 static void 4664 e1000g_set_internal_loopback(struct e1000g *Adapter) 4665 { 4666 struct e1000_hw *hw; 4667 uint32_t ctrl; 4668 uint32_t status; 4669 uint16_t phy_ctrl; 4670 uint32_t txcw; 4671 4672 hw = &Adapter->shared; 4673 4674 /* Disable Smart Power Down */ 4675 phy_spd_state(hw, B_FALSE); 4676 4677 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4678 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4679 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4680 4681 switch (hw->mac.type) { 4682 case e1000_82540: 4683 case e1000_82545: 4684 case e1000_82545_rev_3: 4685 case e1000_82546: 4686 case e1000_82546_rev_3: 4687 case e1000_82573: 4688 /* Auto-MDI/MDIX off */ 4689 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4690 /* Reset PHY to update Auto-MDI/MDIX */ 4691 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4692 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4693 /* Reset PHY to auto-neg off and force 1000 */ 4694 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4695 phy_ctrl | MII_CR_RESET); 4696 /* 4697 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4698 * See comments above e1000g_set_internal_loopback() for the 4699 * background. 4700 */ 4701 (void) e1000_write_phy_reg(hw, 29, 0x001F); 4702 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 4703 (void) e1000_write_phy_reg(hw, 29, 0x001A); 4704 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 4705 break; 4706 case e1000_80003es2lan: 4707 /* Force Link Up */ 4708 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 4709 0x1CC); 4710 /* Sets PCS loopback at 1Gbs */ 4711 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 4712 0x1046); 4713 break; 4714 } 4715 4716 /* Set loopback */ 4717 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4718 4719 msec_delay(250); 4720 4721 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4722 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4723 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4724 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4725 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4726 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4727 E1000_CTRL_FD); /* Force Duplex to FULL */ 4728 4729 switch (hw->mac.type) { 4730 case e1000_82540: 4731 case e1000_82545: 4732 case e1000_82545_rev_3: 4733 case e1000_82546: 4734 case e1000_82546_rev_3: 4735 /* 4736 * For some serdes we'll need to commit the writes now 4737 * so that the status is updated on link 4738 */ 4739 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 4740 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4741 msec_delay(100); 4742 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4743 } 4744 4745 if (hw->phy.media_type == e1000_media_type_copper) { 4746 /* Invert Loss of Signal */ 4747 ctrl |= E1000_CTRL_ILOS; 4748 } else { 4749 /* Set ILOS on fiber nic if half duplex is detected */ 4750 status = E1000_READ_REG(hw, E1000_STATUS); 4751 if ((status & E1000_STATUS_FD) == 0) 4752 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4753 } 4754 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4755 break; 4756 4757 case e1000_82571: 4758 case e1000_82572: 4759 /* 4760 * The fiber/SerDes versions of this adapter do not contain an 4761 * accessible PHY. Therefore, loopback beyond MAC must be done 4762 * using SerDes analog loopback. 4763 */ 4764 if (hw->phy.media_type != e1000_media_type_copper) { 4765 status = E1000_READ_REG(hw, E1000_STATUS); 4766 /* Set ILOS on fiber nic if half duplex is detected */ 4767 if (((status & E1000_STATUS_LU) == 0) || 4768 ((status & E1000_STATUS_FD) == 0) || 4769 (hw->phy.media_type == 4770 e1000_media_type_internal_serdes)) 4771 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4772 4773 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4774 txcw = E1000_READ_REG(hw, E1000_TXCW); 4775 txcw &= ~((uint32_t)1 << 31); 4776 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4777 4778 /* 4779 * Write 0x410 to Serdes Control register 4780 * to enable Serdes analog loopback 4781 */ 4782 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4783 msec_delay(10); 4784 } 4785 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4786 break; 4787 4788 case e1000_82573: 4789 ctrl |= E1000_CTRL_ILOS; 4790 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4791 break; 4792 } 4793 } 4794 4795 static void 4796 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4797 { 4798 struct e1000_hw *hw; 4799 uint32_t rctl; 4800 uint32_t ctrl_ext; 4801 uint32_t ctrl; 4802 uint32_t status; 4803 uint32_t txcw; 4804 uint16_t phydata; 4805 4806 hw = &Adapter->shared; 4807 4808 /* Disable Smart Power Down */ 4809 phy_spd_state(hw, B_FALSE); 4810 4811 switch (hw->mac.type) { 4812 case e1000_82571: 4813 case e1000_82572: 4814 switch (hw->phy.media_type) { 4815 case e1000_media_type_copper: 4816 /* Force link up (Must be done before the PHY writes) */ 4817 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4818 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4819 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4820 4821 rctl = E1000_READ_REG(hw, E1000_RCTL); 4822 rctl |= (E1000_RCTL_EN | 4823 E1000_RCTL_SBP | 4824 E1000_RCTL_UPE | 4825 E1000_RCTL_MPE | 4826 E1000_RCTL_LPE | 4827 E1000_RCTL_BAM); /* 0x803E */ 4828 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4829 4830 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4831 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4832 E1000_CTRL_EXT_SDP6_DATA | 4833 E1000_CTRL_EXT_SDP7_DATA | 4834 E1000_CTRL_EXT_SDP4_DIR | 4835 E1000_CTRL_EXT_SDP6_DIR | 4836 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4837 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4838 4839 /* 4840 * This sequence tunes the PHY's SDP and no customer 4841 * settable values. For background, see comments above 4842 * e1000g_set_internal_loopback(). 4843 */ 4844 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 4845 msec_delay(10); 4846 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 4847 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 4848 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 4849 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 4850 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 4851 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 4852 4853 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 4854 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4855 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4856 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4857 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4858 4859 msec_delay(50); 4860 break; 4861 case e1000_media_type_fiber: 4862 case e1000_media_type_internal_serdes: 4863 status = E1000_READ_REG(hw, E1000_STATUS); 4864 if (((status & E1000_STATUS_LU) == 0) || 4865 (hw->phy.media_type == 4866 e1000_media_type_internal_serdes)) { 4867 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4868 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4869 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4870 } 4871 4872 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4873 txcw = E1000_READ_REG(hw, E1000_TXCW); 4874 txcw &= ~((uint32_t)1 << 31); 4875 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4876 4877 /* 4878 * Write 0x410 to Serdes Control register 4879 * to enable Serdes analog loopback 4880 */ 4881 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4882 msec_delay(10); 4883 break; 4884 default: 4885 break; 4886 } 4887 break; 4888 case e1000_80003es2lan: 4889 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 4890 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 4891 phydata | (1 << 5)); 4892 Adapter->param_adv_autoneg = 1; 4893 Adapter->param_adv_1000fdx = 1; 4894 (void) e1000g_reset_link(Adapter); 4895 break; 4896 } 4897 } 4898 4899 static void 4900 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4901 { 4902 struct e1000_hw *hw; 4903 uint32_t ctrl; 4904 uint16_t phy_ctrl; 4905 4906 hw = &Adapter->shared; 4907 4908 /* Disable Smart Power Down */ 4909 phy_spd_state(hw, B_FALSE); 4910 4911 phy_ctrl = (MII_CR_FULL_DUPLEX | 4912 MII_CR_SPEED_100); 4913 4914 /* Force 100/FD, reset PHY */ 4915 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4916 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4917 msec_delay(10); 4918 4919 /* Force 100/FD */ 4920 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4921 phy_ctrl); /* 0x2100 */ 4922 msec_delay(10); 4923 4924 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4925 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4926 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4927 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4928 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4929 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4930 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4931 E1000_CTRL_FD); /* Force Duplex to FULL */ 4932 4933 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4934 } 4935 4936 static void 4937 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4938 { 4939 struct e1000_hw *hw; 4940 uint32_t ctrl; 4941 uint16_t phy_ctrl; 4942 4943 hw = &Adapter->shared; 4944 4945 /* Disable Smart Power Down */ 4946 phy_spd_state(hw, B_FALSE); 4947 4948 phy_ctrl = (MII_CR_FULL_DUPLEX | 4949 MII_CR_SPEED_10); 4950 4951 /* Force 10/FD, reset PHY */ 4952 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4953 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4954 msec_delay(10); 4955 4956 /* Force 10/FD */ 4957 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 4958 phy_ctrl); /* 0x0100 */ 4959 msec_delay(10); 4960 4961 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4962 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4963 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4964 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4965 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4966 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4967 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4968 E1000_CTRL_FD); /* Force Duplex to FULL */ 4969 4970 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4971 } 4972 4973 #ifdef __sparc 4974 static boolean_t 4975 e1000g_find_mac_address(struct e1000g *Adapter) 4976 { 4977 struct e1000_hw *hw = &Adapter->shared; 4978 uchar_t *bytes; 4979 struct ether_addr sysaddr; 4980 uint_t nelts; 4981 int err; 4982 boolean_t found = B_FALSE; 4983 4984 /* 4985 * The "vendor's factory-set address" may already have 4986 * been extracted from the chip, but if the property 4987 * "local-mac-address" is set we use that instead. 4988 * 4989 * We check whether it looks like an array of 6 4990 * bytes (which it should, if OBP set it). If we can't 4991 * make sense of it this way, we'll ignore it. 4992 */ 4993 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4994 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4995 if (err == DDI_PROP_SUCCESS) { 4996 if (nelts == ETHERADDRL) { 4997 while (nelts--) 4998 hw->mac.addr[nelts] = bytes[nelts]; 4999 found = B_TRUE; 5000 } 5001 ddi_prop_free(bytes); 5002 } 5003 5004 /* 5005 * Look up the OBP property "local-mac-address?". If the user has set 5006 * 'local-mac-address? = false', use "the system address" instead. 5007 */ 5008 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5009 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5010 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5011 if (localetheraddr(NULL, &sysaddr) != 0) { 5012 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5013 found = B_TRUE; 5014 } 5015 } 5016 ddi_prop_free(bytes); 5017 } 5018 5019 /* 5020 * Finally(!), if there's a valid "mac-address" property (created 5021 * if we netbooted from this interface), we must use this instead 5022 * of any of the above to ensure that the NFS/install server doesn't 5023 * get confused by the address changing as Solaris takes over! 5024 */ 5025 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5026 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5027 if (err == DDI_PROP_SUCCESS) { 5028 if (nelts == ETHERADDRL) { 5029 while (nelts--) 5030 hw->mac.addr[nelts] = bytes[nelts]; 5031 found = B_TRUE; 5032 } 5033 ddi_prop_free(bytes); 5034 } 5035 5036 if (found) { 5037 bcopy(hw->mac.addr, hw->mac.perm_addr, 5038 ETHERADDRL); 5039 } 5040 5041 return (found); 5042 } 5043 #endif 5044 5045 static int 5046 e1000g_add_intrs(struct e1000g *Adapter) 5047 { 5048 dev_info_t *devinfo; 5049 int intr_types; 5050 int rc; 5051 5052 devinfo = Adapter->dip; 5053 5054 /* Get supported interrupt types */ 5055 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5056 5057 if (rc != DDI_SUCCESS) { 5058 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5059 "Get supported interrupt types failed: %d\n", rc); 5060 return (DDI_FAILURE); 5061 } 5062 5063 /* 5064 * Based on Intel Technical Advisory document (TA-160), there are some 5065 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5066 * that it supports MSI, but in fact has problems. 5067 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5068 * PCI/PCI-X NICs. 5069 */ 5070 if (Adapter->shared.mac.type < e1000_82571) 5071 Adapter->msi_enable = B_FALSE; 5072 5073 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5074 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5075 5076 if (rc != DDI_SUCCESS) { 5077 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5078 "Add MSI failed, trying Legacy interrupts\n"); 5079 } else { 5080 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5081 } 5082 } 5083 5084 if ((Adapter->intr_type == 0) && 5085 (intr_types & DDI_INTR_TYPE_FIXED)) { 5086 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5087 5088 if (rc != DDI_SUCCESS) { 5089 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5090 "Add Legacy interrupts failed\n"); 5091 return (DDI_FAILURE); 5092 } 5093 5094 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5095 } 5096 5097 if (Adapter->intr_type == 0) { 5098 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5099 "No interrupts registered\n"); 5100 return (DDI_FAILURE); 5101 } 5102 5103 return (DDI_SUCCESS); 5104 } 5105 5106 /* 5107 * e1000g_intr_add() handles MSI/Legacy interrupts 5108 */ 5109 static int 5110 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5111 { 5112 dev_info_t *devinfo; 5113 int count, avail, actual; 5114 int x, y, rc, inum = 0; 5115 int flag; 5116 ddi_intr_handler_t *intr_handler; 5117 5118 devinfo = Adapter->dip; 5119 5120 /* get number of interrupts */ 5121 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5122 if ((rc != DDI_SUCCESS) || (count == 0)) { 5123 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5124 "Get interrupt number failed. Return: %d, count: %d\n", 5125 rc, count); 5126 return (DDI_FAILURE); 5127 } 5128 5129 /* get number of available interrupts */ 5130 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5131 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5132 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5133 "Get interrupt available number failed. " 5134 "Return: %d, available: %d\n", rc, avail); 5135 return (DDI_FAILURE); 5136 } 5137 5138 if (avail < count) { 5139 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5140 "Interrupts count: %d, available: %d\n", 5141 count, avail); 5142 } 5143 5144 /* Allocate an array of interrupt handles */ 5145 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5146 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5147 5148 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5149 flag = DDI_INTR_ALLOC_NORMAL; 5150 5151 /* call ddi_intr_alloc() */ 5152 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5153 count, &actual, flag); 5154 5155 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5156 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5157 "Allocate interrupts failed: %d\n", rc); 5158 5159 kmem_free(Adapter->htable, Adapter->intr_size); 5160 return (DDI_FAILURE); 5161 } 5162 5163 if (actual < count) { 5164 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5165 "Interrupts requested: %d, received: %d\n", 5166 count, actual); 5167 } 5168 5169 Adapter->intr_cnt = actual; 5170 5171 /* Get priority for first msi, assume remaining are all the same */ 5172 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5173 5174 if (rc != DDI_SUCCESS) { 5175 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5176 "Get interrupt priority failed: %d\n", rc); 5177 5178 /* Free already allocated intr */ 5179 for (y = 0; y < actual; y++) 5180 (void) ddi_intr_free(Adapter->htable[y]); 5181 5182 kmem_free(Adapter->htable, Adapter->intr_size); 5183 return (DDI_FAILURE); 5184 } 5185 5186 /* 5187 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5188 * use the interrupt service routine e1000g_intr_pciexpress() 5189 * to avoid interrupt stealing when sharing interrupt with other 5190 * devices. 5191 */ 5192 if (Adapter->shared.mac.type < e1000_82571) 5193 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5194 else 5195 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5196 5197 /* Call ddi_intr_add_handler() */ 5198 for (x = 0; x < actual; x++) { 5199 rc = ddi_intr_add_handler(Adapter->htable[x], 5200 intr_handler, (caddr_t)Adapter, NULL); 5201 5202 if (rc != DDI_SUCCESS) { 5203 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5204 "Add interrupt handler failed: %d\n", rc); 5205 5206 /* Remove already added handler */ 5207 for (y = 0; y < x; y++) 5208 (void) ddi_intr_remove_handler( 5209 Adapter->htable[y]); 5210 5211 /* Free already allocated intr */ 5212 for (y = 0; y < actual; y++) 5213 (void) ddi_intr_free(Adapter->htable[y]); 5214 5215 kmem_free(Adapter->htable, Adapter->intr_size); 5216 return (DDI_FAILURE); 5217 } 5218 } 5219 5220 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5221 5222 if (rc != DDI_SUCCESS) { 5223 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5224 "Get interrupt cap failed: %d\n", rc); 5225 5226 /* Free already allocated intr */ 5227 for (y = 0; y < actual; y++) { 5228 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5229 (void) ddi_intr_free(Adapter->htable[y]); 5230 } 5231 5232 kmem_free(Adapter->htable, Adapter->intr_size); 5233 return (DDI_FAILURE); 5234 } 5235 5236 return (DDI_SUCCESS); 5237 } 5238 5239 static int 5240 e1000g_rem_intrs(struct e1000g *Adapter) 5241 { 5242 int x; 5243 int rc; 5244 5245 for (x = 0; x < Adapter->intr_cnt; x++) { 5246 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5247 if (rc != DDI_SUCCESS) { 5248 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5249 "Remove intr handler failed: %d\n", rc); 5250 return (DDI_FAILURE); 5251 } 5252 5253 rc = ddi_intr_free(Adapter->htable[x]); 5254 if (rc != DDI_SUCCESS) { 5255 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5256 "Free intr failed: %d\n", rc); 5257 return (DDI_FAILURE); 5258 } 5259 } 5260 5261 kmem_free(Adapter->htable, Adapter->intr_size); 5262 5263 return (DDI_SUCCESS); 5264 } 5265 5266 static int 5267 e1000g_enable_intrs(struct e1000g *Adapter) 5268 { 5269 int x; 5270 int rc; 5271 5272 /* Enable interrupts */ 5273 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5274 /* Call ddi_intr_block_enable() for MSI */ 5275 rc = ddi_intr_block_enable(Adapter->htable, 5276 Adapter->intr_cnt); 5277 if (rc != DDI_SUCCESS) { 5278 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5279 "Enable block intr failed: %d\n", rc); 5280 return (DDI_FAILURE); 5281 } 5282 } else { 5283 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5284 for (x = 0; x < Adapter->intr_cnt; x++) { 5285 rc = ddi_intr_enable(Adapter->htable[x]); 5286 if (rc != DDI_SUCCESS) { 5287 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5288 "Enable intr failed: %d\n", rc); 5289 return (DDI_FAILURE); 5290 } 5291 } 5292 } 5293 5294 return (DDI_SUCCESS); 5295 } 5296 5297 static int 5298 e1000g_disable_intrs(struct e1000g *Adapter) 5299 { 5300 int x; 5301 int rc; 5302 5303 /* Disable all interrupts */ 5304 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5305 rc = ddi_intr_block_disable(Adapter->htable, 5306 Adapter->intr_cnt); 5307 if (rc != DDI_SUCCESS) { 5308 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5309 "Disable block intr failed: %d\n", rc); 5310 return (DDI_FAILURE); 5311 } 5312 } else { 5313 for (x = 0; x < Adapter->intr_cnt; x++) { 5314 rc = ddi_intr_disable(Adapter->htable[x]); 5315 if (rc != DDI_SUCCESS) { 5316 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5317 "Disable intr failed: %d\n", rc); 5318 return (DDI_FAILURE); 5319 } 5320 } 5321 } 5322 5323 return (DDI_SUCCESS); 5324 } 5325 5326 /* 5327 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5328 */ 5329 static void 5330 e1000g_get_phy_state(struct e1000g *Adapter) 5331 { 5332 struct e1000_hw *hw = &Adapter->shared; 5333 5334 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5335 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5336 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5337 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5338 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5339 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5340 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 5341 &Adapter->phy_1000t_status); 5342 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5343 5344 Adapter->param_autoneg_cap = 5345 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5346 Adapter->param_pause_cap = 5347 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5348 Adapter->param_asym_pause_cap = 5349 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5350 Adapter->param_1000fdx_cap = 5351 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5352 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5353 Adapter->param_1000hdx_cap = 5354 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5355 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5356 Adapter->param_100t4_cap = 5357 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5358 Adapter->param_100fdx_cap = 5359 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5360 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5361 Adapter->param_100hdx_cap = 5362 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5363 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5364 Adapter->param_10fdx_cap = 5365 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5366 Adapter->param_10hdx_cap = 5367 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5368 5369 Adapter->param_adv_autoneg = hw->mac.autoneg; 5370 Adapter->param_adv_pause = 5371 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5372 Adapter->param_adv_asym_pause = 5373 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5374 Adapter->param_adv_1000hdx = 5375 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5376 Adapter->param_adv_100t4 = 5377 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5378 if (Adapter->param_adv_autoneg == 1) { 5379 Adapter->param_adv_1000fdx = 5380 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5381 Adapter->param_adv_100fdx = 5382 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5383 Adapter->param_adv_100hdx = 5384 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5385 Adapter->param_adv_10fdx = 5386 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5387 Adapter->param_adv_10hdx = 5388 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5389 } 5390 5391 Adapter->param_lp_autoneg = 5392 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5393 Adapter->param_lp_pause = 5394 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5395 Adapter->param_lp_asym_pause = 5396 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5397 Adapter->param_lp_1000fdx = 5398 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5399 Adapter->param_lp_1000hdx = 5400 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5401 Adapter->param_lp_100t4 = 5402 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5403 Adapter->param_lp_100fdx = 5404 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5405 Adapter->param_lp_100hdx = 5406 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5407 Adapter->param_lp_10fdx = 5408 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5409 Adapter->param_lp_10hdx = 5410 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5411 } 5412 5413 /* 5414 * FMA support 5415 */ 5416 5417 int 5418 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5419 { 5420 ddi_fm_error_t de; 5421 5422 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5423 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5424 return (de.fme_status); 5425 } 5426 5427 int 5428 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5429 { 5430 ddi_fm_error_t de; 5431 5432 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5433 return (de.fme_status); 5434 } 5435 5436 /* 5437 * The IO fault service error handling callback function 5438 */ 5439 /* ARGSUSED2 */ 5440 static int 5441 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5442 { 5443 /* 5444 * as the driver can always deal with an error in any dma or 5445 * access handle, we can just return the fme_status value. 5446 */ 5447 pci_ereport_post(dip, err, NULL); 5448 return (err->fme_status); 5449 } 5450 5451 static void 5452 e1000g_fm_init(struct e1000g *Adapter) 5453 { 5454 ddi_iblock_cookie_t iblk; 5455 int fma_acc_flag, fma_dma_flag; 5456 5457 /* Only register with IO Fault Services if we have some capability */ 5458 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5459 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5460 fma_acc_flag = 1; 5461 } else { 5462 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5463 fma_acc_flag = 0; 5464 } 5465 5466 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5467 fma_dma_flag = 1; 5468 } else { 5469 fma_dma_flag = 0; 5470 } 5471 5472 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5473 5474 if (Adapter->fm_capabilities) { 5475 5476 /* Register capabilities with IO Fault Services */ 5477 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5478 5479 /* 5480 * Initialize pci ereport capabilities if ereport capable 5481 */ 5482 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5483 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5484 pci_ereport_setup(Adapter->dip); 5485 5486 /* 5487 * Register error callback if error callback capable 5488 */ 5489 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5490 ddi_fm_handler_register(Adapter->dip, 5491 e1000g_fm_error_cb, (void*) Adapter); 5492 } 5493 } 5494 5495 static void 5496 e1000g_fm_fini(struct e1000g *Adapter) 5497 { 5498 /* Only unregister FMA capabilities if we registered some */ 5499 if (Adapter->fm_capabilities) { 5500 5501 /* 5502 * Release any resources allocated by pci_ereport_setup() 5503 */ 5504 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5505 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5506 pci_ereport_teardown(Adapter->dip); 5507 5508 /* 5509 * Un-register error callback if error callback capable 5510 */ 5511 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5512 ddi_fm_handler_unregister(Adapter->dip); 5513 5514 /* Unregister from IO Fault Services */ 5515 ddi_fm_fini(Adapter->dip); 5516 } 5517 } 5518 5519 void 5520 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5521 { 5522 uint64_t ena; 5523 char buf[FM_MAX_CLASS]; 5524 5525 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5526 ena = fm_ena_generate(0, FM_ENA_FMT1); 5527 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5528 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5529 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5530 } 5531 } 5532 5533 /* 5534 * quiesce(9E) entry point. 5535 * 5536 * This function is called when the system is single-threaded at high 5537 * PIL with preemption disabled. Therefore, this function must not be 5538 * blocked. 5539 * 5540 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5541 * DDI_FAILURE indicates an error condition and should almost never happen. 5542 */ 5543 static int 5544 e1000g_quiesce(dev_info_t *devinfo) 5545 { 5546 struct e1000g *Adapter; 5547 5548 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 5549 5550 if (Adapter == NULL) 5551 return (DDI_FAILURE); 5552 5553 e1000g_clear_all_interrupts(Adapter); 5554 5555 (void) e1000_reset_hw(&Adapter->shared); 5556 5557 /* Setup our HW Tx Head & Tail descriptor pointers */ 5558 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 5559 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 5560 5561 /* Setup our HW Rx Head & Tail descriptor pointers */ 5562 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 5563 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 5564 5565 return (DDI_SUCCESS); 5566 } 5567 5568 static int 5569 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5570 uint_t pr_valsize, void *pr_val) 5571 { 5572 link_flowctrl_t fl; 5573 int err = 0; 5574 5575 ASSERT(pr_valsize > 0); 5576 switch (pr_num) { 5577 case MAC_PROP_AUTONEG: 5578 *(uint8_t *)pr_val = 5579 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5580 break; 5581 case MAC_PROP_FLOWCTRL: 5582 if (pr_valsize < sizeof (link_flowctrl_t)) 5583 return (EINVAL); 5584 fl = LINK_FLOWCTRL_BI; 5585 bcopy(&fl, pr_val, sizeof (fl)); 5586 break; 5587 case MAC_PROP_ADV_1000FDX_CAP: 5588 case MAC_PROP_EN_1000FDX_CAP: 5589 *(uint8_t *)pr_val = 5590 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5591 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5592 break; 5593 case MAC_PROP_ADV_1000HDX_CAP: 5594 case MAC_PROP_EN_1000HDX_CAP: 5595 *(uint8_t *)pr_val = 5596 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5597 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5598 break; 5599 case MAC_PROP_ADV_100FDX_CAP: 5600 case MAC_PROP_EN_100FDX_CAP: 5601 *(uint8_t *)pr_val = 5602 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5603 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5604 break; 5605 case MAC_PROP_ADV_100HDX_CAP: 5606 case MAC_PROP_EN_100HDX_CAP: 5607 *(uint8_t *)pr_val = 5608 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5609 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5610 break; 5611 case MAC_PROP_ADV_10FDX_CAP: 5612 case MAC_PROP_EN_10FDX_CAP: 5613 *(uint8_t *)pr_val = 5614 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5615 break; 5616 case MAC_PROP_ADV_10HDX_CAP: 5617 case MAC_PROP_EN_10HDX_CAP: 5618 *(uint8_t *)pr_val = 5619 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5620 break; 5621 default: 5622 err = ENOTSUP; 5623 break; 5624 } 5625 return (err); 5626 } 5627 5628 /* 5629 * synchronize the adv* and en* parameters. 5630 * 5631 * See comments in <sys/dld.h> for details of the *_en_* 5632 * parameters. The usage of ndd for setting adv parameters will 5633 * synchronize all the en parameters with the e1000g parameters, 5634 * implicitly disabling any settings made via dladm. 5635 */ 5636 static void 5637 e1000g_param_sync(struct e1000g *Adapter) 5638 { 5639 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5640 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5641 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5642 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5643 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5644 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5645 } 5646 5647 /* 5648 * e1000g_get_driver_control - tell manageability firmware that the driver 5649 * has control. 5650 */ 5651 static void 5652 e1000g_get_driver_control(struct e1000_hw *hw) 5653 { 5654 uint32_t ctrl_ext; 5655 uint32_t swsm; 5656 5657 /* tell manageability firmware the driver has taken over */ 5658 switch (hw->mac.type) { 5659 case e1000_82573: 5660 swsm = E1000_READ_REG(hw, E1000_SWSM); 5661 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 5662 break; 5663 case e1000_82571: 5664 case e1000_82572: 5665 case e1000_82574: 5666 case e1000_80003es2lan: 5667 case e1000_ich8lan: 5668 case e1000_ich9lan: 5669 case e1000_ich10lan: 5670 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5671 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5672 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 5673 break; 5674 default: 5675 /* no manageability firmware: do nothing */ 5676 break; 5677 } 5678 } 5679 5680 /* 5681 * e1000g_release_driver_control - tell manageability firmware that the driver 5682 * has released control. 5683 */ 5684 static void 5685 e1000g_release_driver_control(struct e1000_hw *hw) 5686 { 5687 uint32_t ctrl_ext; 5688 uint32_t swsm; 5689 5690 /* tell manageability firmware the driver has released control */ 5691 switch (hw->mac.type) { 5692 case e1000_82573: 5693 swsm = E1000_READ_REG(hw, E1000_SWSM); 5694 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 5695 break; 5696 case e1000_82571: 5697 case e1000_82572: 5698 case e1000_82574: 5699 case e1000_80003es2lan: 5700 case e1000_ich8lan: 5701 case e1000_ich9lan: 5702 case e1000_ich10lan: 5703 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5704 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 5705 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 5706 break; 5707 default: 5708 /* no manageability firmware: do nothing */ 5709 break; 5710 } 5711 } 5712 5713 /* 5714 * Restore e1000g promiscuous mode. 5715 */ 5716 static void 5717 e1000g_restore_promisc(struct e1000g *Adapter) 5718 { 5719 if (Adapter->e1000g_promisc) { 5720 uint32_t rctl; 5721 5722 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 5723 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 5724 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 5725 } 5726 } 5727