1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2008 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routines for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point routines. * 37 * * 38 * This file also contains routines that take care of initialization * 39 * uninit routine and interrupt routine. * 40 * * 41 * ********************************************************************** 42 */ 43 44 #include <sys/dlpi.h> 45 #include <sys/mac.h> 46 #include <sys/dld.h> 47 #include "e1000g_sw.h" 48 #include "e1000g_debug.h" 49 50 static char ident[] = "Intel PRO/1000 Ethernet 5.2.7"; 51 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 52 static char e1000g_version[] = "Driver Ver. 5.2.7"; 53 54 /* 55 * Proto types for DDI entry points 56 */ 57 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 58 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 59 60 /* 61 * init and intr routines prototype 62 */ 63 static int e1000g_resume(dev_info_t *); 64 static int e1000g_suspend(dev_info_t *); 65 static uint_t e1000g_intr_pciexpress(caddr_t); 66 static uint_t e1000g_intr(caddr_t); 67 static void e1000g_intr_work(struct e1000g *, uint32_t); 68 #pragma inline(e1000g_intr_work) 69 static uint32_t e1000g_get_itr(uint32_t, uint32_t, uint32_t); 70 #pragma inline(e1000g_get_itr) 71 static int e1000g_init(struct e1000g *); 72 static int e1000g_start(struct e1000g *, boolean_t); 73 static void e1000g_stop(struct e1000g *, boolean_t); 74 static int e1000g_m_start(void *); 75 static void e1000g_m_stop(void *); 76 static int e1000g_m_promisc(void *, boolean_t); 77 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 78 static int e1000g_m_unicst(void *, const uint8_t *); 79 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 80 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 81 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 82 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 83 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 84 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 85 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 86 uint_t, const void *); 87 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 88 uint_t, uint_t, void *); 89 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 90 const void *); 91 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 92 uint_t, void *); 93 static void e1000g_init_locks(struct e1000g *); 94 static void e1000g_destroy_locks(struct e1000g *); 95 static int e1000g_identify_hardware(struct e1000g *); 96 static int e1000g_regs_map(struct e1000g *); 97 static int e1000g_set_driver_params(struct e1000g *); 98 static void e1000g_set_bufsize(struct e1000g *); 99 static int e1000g_register_mac(struct e1000g *); 100 static boolean_t e1000g_rx_drain(struct e1000g *); 101 static boolean_t e1000g_tx_drain(struct e1000g *); 102 static void e1000g_init_unicst(struct e1000g *); 103 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 104 105 /* 106 * Local routines 107 */ 108 static void e1000g_tx_clean(struct e1000g *); 109 static void e1000g_rx_clean(struct e1000g *); 110 static void e1000g_link_timer(void *); 111 static void e1000g_local_timer(void *); 112 static boolean_t e1000g_link_check(struct e1000g *); 113 static boolean_t e1000g_stall_check(struct e1000g *); 114 static void e1000g_smartspeed(struct e1000g *); 115 static void e1000g_get_conf(struct e1000g *); 116 static int e1000g_get_prop(struct e1000g *, char *, int, int, int); 117 static void enable_watchdog_timer(struct e1000g *); 118 static void disable_watchdog_timer(struct e1000g *); 119 static void start_watchdog_timer(struct e1000g *); 120 static void restart_watchdog_timer(struct e1000g *); 121 static void stop_watchdog_timer(struct e1000g *); 122 static void stop_link_timer(struct e1000g *); 123 static void stop_82547_timer(e1000g_tx_ring_t *); 124 static void e1000g_force_speed_duplex(struct e1000g *); 125 static void e1000g_get_max_frame_size(struct e1000g *); 126 static boolean_t is_valid_mac_addr(uint8_t *); 127 static void e1000g_unattach(dev_info_t *, struct e1000g *); 128 #ifdef E1000G_DEBUG 129 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 133 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 134 struct iocblk *, mblk_t *); 135 #endif 136 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 137 struct iocblk *, mblk_t *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static void e1000g_free_priv_devi_node(struct e1000g *, boolean_t); 154 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 155 const void *impl_data); 156 static void e1000g_fm_init(struct e1000g *Adapter); 157 static void e1000g_fm_fini(struct e1000g *Adapter); 158 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 159 static void e1000g_param_sync(struct e1000g *); 160 161 mac_priv_prop_t e1000g_priv_props[] = { 162 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 163 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 164 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 165 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 166 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 167 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 168 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 169 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 170 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 171 {"_intr_adaptive", MAC_PROP_PERM_RW}, 172 {"_tx_recycle_thresh", MAC_PROP_PERM_RW}, 173 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 174 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 175 {"_tx_recycle_num", MAC_PROP_PERM_RW} 176 }; 177 #define E1000G_MAX_PRIV_PROPS \ 178 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 179 180 181 static struct cb_ops cb_ws_ops = { 182 nulldev, /* cb_open */ 183 nulldev, /* cb_close */ 184 nodev, /* cb_strategy */ 185 nodev, /* cb_print */ 186 nodev, /* cb_dump */ 187 nodev, /* cb_read */ 188 nodev, /* cb_write */ 189 nodev, /* cb_ioctl */ 190 nodev, /* cb_devmap */ 191 nodev, /* cb_mmap */ 192 nodev, /* cb_segmap */ 193 nochpoll, /* cb_chpoll */ 194 ddi_prop_op, /* cb_prop_op */ 195 NULL, /* cb_stream */ 196 D_MP | D_HOTPLUG, /* cb_flag */ 197 CB_REV, /* cb_rev */ 198 nodev, /* cb_aread */ 199 nodev /* cb_awrite */ 200 }; 201 202 static struct dev_ops ws_ops = { 203 DEVO_REV, /* devo_rev */ 204 0, /* devo_refcnt */ 205 NULL, /* devo_getinfo */ 206 nulldev, /* devo_identify */ 207 nulldev, /* devo_probe */ 208 e1000g_attach, /* devo_attach */ 209 e1000g_detach, /* devo_detach */ 210 nodev, /* devo_reset */ 211 &cb_ws_ops, /* devo_cb_ops */ 212 NULL, /* devo_bus_ops */ 213 ddi_power /* devo_power */ 214 }; 215 216 static struct modldrv modldrv = { 217 &mod_driverops, /* Type of module. This one is a driver */ 218 ident, /* Discription string */ 219 &ws_ops, /* driver ops */ 220 }; 221 222 static struct modlinkage modlinkage = { 223 MODREV_1, &modldrv, NULL 224 }; 225 226 /* Access attributes for register mapping */ 227 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 228 DDI_DEVICE_ATTR_V0, 229 DDI_STRUCTURE_LE_ACC, 230 DDI_STRICTORDER_ACC, 231 DDI_FLAGERR_ACC 232 }; 233 234 #define E1000G_M_CALLBACK_FLAGS \ 235 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 236 237 static mac_callbacks_t e1000g_m_callbacks = { 238 E1000G_M_CALLBACK_FLAGS, 239 e1000g_m_stat, 240 e1000g_m_start, 241 e1000g_m_stop, 242 e1000g_m_promisc, 243 e1000g_m_multicst, 244 e1000g_m_unicst, 245 e1000g_m_tx, 246 NULL, 247 e1000g_m_ioctl, 248 e1000g_m_getcapab, 249 NULL, 250 NULL, 251 e1000g_m_setprop, 252 e1000g_m_getprop 253 }; 254 255 /* 256 * Global variables 257 */ 258 uint32_t e1000g_mblks_pending = 0; 259 /* 260 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 261 * Here we maintain a private dev_info list if e1000g_force_detach is 262 * enabled. If we force the driver to detach while there are still some 263 * rx buffers retained in the upper layer, we have to keep a copy of the 264 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 265 * structure will be freed after the driver is detached. However when we 266 * finally free those rx buffers released by the upper layer, we need to 267 * refer to the dev_info to free the dma buffers. So we save a copy of 268 * the dev_info for this purpose. On x86 platform, we assume this copy 269 * of dev_info is always valid, but on SPARC platform, it could be invalid 270 * after the system board level DR operation. For this reason, the global 271 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 272 */ 273 #ifdef __sparc 274 boolean_t e1000g_force_detach = B_FALSE; 275 #else 276 boolean_t e1000g_force_detach = B_TRUE; 277 #endif 278 private_devi_list_t *e1000g_private_devi_list = NULL; 279 280 /* 281 * The rwlock is defined to protect the whole processing of rx recycling 282 * and the rx packets release in detach processing to make them mutually 283 * exclusive. 284 * The rx recycling processes different rx packets in different threads, 285 * so it will be protected with RW_READER and it won't block any other rx 286 * recycling threads. 287 * While the detach processing will be protected with RW_WRITER to make 288 * it mutually exclusive with the rx recycling. 289 */ 290 krwlock_t e1000g_rx_detach_lock; 291 /* 292 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 293 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 294 * If there are many e1000g instances, the system may run out of DVMA 295 * resources during the initialization of the instances, then the flag will 296 * be changed to "USE_DMA". Because different e1000g instances are initialized 297 * in parallel, we need to use this lock to protect the flag. 298 */ 299 krwlock_t e1000g_dma_type_lock; 300 301 302 /* 303 * Loadable module configuration entry points for the driver 304 */ 305 306 /* 307 * _init - module initialization 308 */ 309 int 310 _init(void) 311 { 312 int status; 313 314 mac_init_ops(&ws_ops, WSNAME); 315 status = mod_install(&modlinkage); 316 if (status != DDI_SUCCESS) 317 mac_fini_ops(&ws_ops); 318 else { 319 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 320 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 321 } 322 323 return (status); 324 } 325 326 /* 327 * _fini - module finalization 328 */ 329 int 330 _fini(void) 331 { 332 int status; 333 334 rw_enter(&e1000g_rx_detach_lock, RW_READER); 335 if (e1000g_mblks_pending != 0) { 336 rw_exit(&e1000g_rx_detach_lock); 337 return (EBUSY); 338 } 339 rw_exit(&e1000g_rx_detach_lock); 340 341 status = mod_remove(&modlinkage); 342 if (status == DDI_SUCCESS) { 343 mac_fini_ops(&ws_ops); 344 345 if (e1000g_force_detach) { 346 private_devi_list_t *devi_node; 347 348 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 349 while (e1000g_private_devi_list != NULL) { 350 devi_node = e1000g_private_devi_list; 351 e1000g_private_devi_list = 352 e1000g_private_devi_list->next; 353 354 kmem_free(devi_node->priv_dip, 355 sizeof (struct dev_info)); 356 kmem_free(devi_node, 357 sizeof (private_devi_list_t)); 358 } 359 rw_exit(&e1000g_rx_detach_lock); 360 } 361 362 rw_destroy(&e1000g_rx_detach_lock); 363 rw_destroy(&e1000g_dma_type_lock); 364 } 365 366 return (status); 367 } 368 369 /* 370 * _info - module information 371 */ 372 int 373 _info(struct modinfo *modinfop) 374 { 375 return (mod_info(&modlinkage, modinfop)); 376 } 377 378 /* 379 * e1000g_attach - driver attach 380 * 381 * This function is the device-specific initialization entry 382 * point. This entry point is required and must be written. 383 * The DDI_ATTACH command must be provided in the attach entry 384 * point. When attach() is called with cmd set to DDI_ATTACH, 385 * all normal kernel services (such as kmem_alloc(9F)) are 386 * available for use by the driver. 387 * 388 * The attach() function will be called once for each instance 389 * of the device on the system with cmd set to DDI_ATTACH. 390 * Until attach() succeeds, the only driver entry points which 391 * may be called are open(9E) and getinfo(9E). 392 */ 393 static int 394 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 395 { 396 struct e1000g *Adapter; 397 struct e1000_hw *hw; 398 struct e1000g_osdep *osdep; 399 int instance; 400 401 switch (cmd) { 402 default: 403 e1000g_log(NULL, CE_WARN, 404 "Unsupported command send to e1000g_attach... "); 405 return (DDI_FAILURE); 406 407 case DDI_RESUME: 408 return (e1000g_resume(devinfo)); 409 410 case DDI_ATTACH: 411 break; 412 } 413 414 /* 415 * get device instance number 416 */ 417 instance = ddi_get_instance(devinfo); 418 419 /* 420 * Allocate soft data structure 421 */ 422 Adapter = 423 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 424 425 Adapter->dip = devinfo; 426 Adapter->instance = instance; 427 Adapter->tx_ring->adapter = Adapter; 428 Adapter->rx_ring->adapter = Adapter; 429 430 hw = &Adapter->shared; 431 osdep = &Adapter->osdep; 432 hw->back = osdep; 433 osdep->adapter = Adapter; 434 435 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 436 437 /* 438 * Initialize for fma support 439 */ 440 Adapter->fm_capabilities = e1000g_get_prop(Adapter, "fm-capable", 441 0, 0x0f, 442 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 443 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 444 e1000g_fm_init(Adapter); 445 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 446 447 /* 448 * PCI Configure 449 */ 450 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 451 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 452 goto attach_fail; 453 } 454 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 455 456 /* 457 * Setup hardware 458 */ 459 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 460 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 461 goto attach_fail; 462 } 463 464 /* 465 * Map in the device registers. 466 */ 467 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 468 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 469 goto attach_fail; 470 } 471 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 472 473 /* 474 * Initialize driver parameters 475 */ 476 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 477 goto attach_fail; 478 } 479 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 480 481 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 482 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 483 goto attach_fail; 484 } 485 486 /* 487 * Initialize interrupts 488 */ 489 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 490 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 491 goto attach_fail; 492 } 493 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 494 495 /* 496 * Initialize mutex's for this device. 497 * Do this before enabling the interrupt handler and 498 * register the softint to avoid the condition where 499 * interrupt handler can try using uninitialized mutex 500 */ 501 e1000g_init_locks(Adapter); 502 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 503 504 /* 505 * Initialize Driver Counters 506 */ 507 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 508 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 509 goto attach_fail; 510 } 511 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 512 513 /* 514 * Initialize chip hardware and software structures 515 */ 516 if (e1000g_init(Adapter) != DDI_SUCCESS) { 517 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 518 goto attach_fail; 519 } 520 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 521 522 /* 523 * Register the driver to the MAC 524 */ 525 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 526 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 527 goto attach_fail; 528 } 529 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 530 531 /* 532 * Now that mutex locks are initialized, and the chip is also 533 * initialized, enable interrupts. 534 */ 535 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 536 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 537 goto attach_fail; 538 } 539 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 540 541 /* 542 * If e1000g_force_detach is enabled, in global private dip list, 543 * we will create a new entry, which maintains the priv_dip for DR 544 * supports after driver detached. 545 */ 546 if (e1000g_force_detach) { 547 private_devi_list_t *devi_node; 548 549 Adapter->priv_dip = 550 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 551 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 552 sizeof (struct dev_info)); 553 554 devi_node = 555 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 556 557 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 558 devi_node->priv_dip = Adapter->priv_dip; 559 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 560 devi_node->next = e1000g_private_devi_list; 561 e1000g_private_devi_list = devi_node; 562 rw_exit(&e1000g_rx_detach_lock); 563 } 564 565 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 566 567 return (DDI_SUCCESS); 568 569 attach_fail: 570 e1000g_unattach(devinfo, Adapter); 571 return (DDI_FAILURE); 572 } 573 574 static int 575 e1000g_register_mac(struct e1000g *Adapter) 576 { 577 struct e1000_hw *hw = &Adapter->shared; 578 mac_register_t *mac; 579 int err; 580 581 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 582 return (DDI_FAILURE); 583 584 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 585 mac->m_driver = Adapter; 586 mac->m_dip = Adapter->dip; 587 mac->m_src_addr = hw->mac.addr; 588 mac->m_callbacks = &e1000g_m_callbacks; 589 mac->m_min_sdu = 0; 590 mac->m_max_sdu = Adapter->default_mtu; 591 mac->m_margin = VLAN_TAGSZ; 592 mac->m_priv_props = e1000g_priv_props; 593 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 594 595 err = mac_register(mac, &Adapter->mh); 596 mac_free(mac); 597 598 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 599 } 600 601 static int 602 e1000g_identify_hardware(struct e1000g *Adapter) 603 { 604 struct e1000_hw *hw = &Adapter->shared; 605 struct e1000g_osdep *osdep = &Adapter->osdep; 606 607 /* Get the device id */ 608 hw->vendor_id = 609 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 610 hw->device_id = 611 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 612 hw->revision_id = 613 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 614 hw->subsystem_device_id = 615 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 616 hw->subsystem_vendor_id = 617 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 618 619 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 620 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 621 "MAC type could not be set properly."); 622 return (DDI_FAILURE); 623 } 624 625 return (DDI_SUCCESS); 626 } 627 628 static int 629 e1000g_regs_map(struct e1000g *Adapter) 630 { 631 dev_info_t *devinfo = Adapter->dip; 632 struct e1000_hw *hw = &Adapter->shared; 633 struct e1000g_osdep *osdep = &Adapter->osdep; 634 off_t mem_size; 635 636 /* 637 * first get the size of device register to be mapped. The 638 * second parameter is the register we are interested. I our 639 * wiseman 0 is for config registers and 1 is for memory mapped 640 * registers Mem size should have memory mapped region size 641 */ 642 if (ddi_dev_regsize(devinfo, 1, &mem_size) != DDI_SUCCESS) { 643 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 644 "ddi_dev_regsize for registers failed"); 645 return (DDI_FAILURE); 646 } 647 648 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 649 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 650 &osdep->reg_handle)) != DDI_SUCCESS) { 651 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 652 "ddi_regs_map_setup for registers failed"); 653 goto regs_map_fail; 654 } 655 656 /* ICH needs to map flash memory */ 657 if (hw->mac.type == e1000_ich8lan || hw->mac.type == e1000_ich9lan) { 658 /* get flash size */ 659 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 660 &mem_size) != DDI_SUCCESS) { 661 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 662 "ddi_dev_regsize for ICH flash failed"); 663 goto regs_map_fail; 664 } 665 666 /* map flash in */ 667 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 668 (caddr_t *)&hw->flash_address, 0, 669 mem_size, &e1000g_regs_acc_attr, 670 &osdep->ich_flash_handle) != DDI_SUCCESS) { 671 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 672 "ddi_regs_map_setup for ICH flash failed"); 673 goto regs_map_fail; 674 } 675 } 676 677 return (DDI_SUCCESS); 678 679 regs_map_fail: 680 if (osdep->reg_handle != NULL) 681 ddi_regs_map_free(&osdep->reg_handle); 682 683 return (DDI_FAILURE); 684 } 685 686 static int 687 e1000g_set_driver_params(struct e1000g *Adapter) 688 { 689 struct e1000_hw *hw; 690 e1000g_tx_ring_t *tx_ring; 691 uint32_t mem_bar, io_bar, bar64; 692 693 hw = &Adapter->shared; 694 695 /* Set MAC type and initialize hardware functions */ 696 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 697 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 698 "Could not setup hardware functions"); 699 return (DDI_FAILURE); 700 } 701 702 /* Get bus information */ 703 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 704 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 705 "Could not get bus information"); 706 return (DDI_FAILURE); 707 } 708 709 /* get mem_base addr */ 710 mem_bar = pci_config_get32(Adapter->osdep.cfg_handle, PCI_CONF_BASE0); 711 bar64 = mem_bar & PCI_BASE_TYPE_ALL; 712 713 /* get io_base addr */ 714 if (hw->mac.type >= e1000_82544) { 715 if (bar64) { 716 /* IO BAR is different for 64 bit BAR mode */ 717 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 718 PCI_CONF_BASE4); 719 } else { 720 /* normal 32-bit BAR mode */ 721 io_bar = pci_config_get32(Adapter->osdep.cfg_handle, 722 PCI_CONF_BASE2); 723 } 724 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 725 } else { 726 /* no I/O access for adapters prior to 82544 */ 727 hw->io_base = 0x0; 728 } 729 730 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 731 732 hw->mac.autoneg_failed = B_TRUE; 733 734 /* Set the wait_for_link flag to B_FALSE */ 735 hw->phy.wait_for_link = B_FALSE; 736 737 /* Adaptive IFS related changes */ 738 hw->mac.adaptive_ifs = B_TRUE; 739 740 /* Enable phy init script for IGP phy of 82541/82547 */ 741 if ((hw->mac.type == e1000_82547) || 742 (hw->mac.type == e1000_82541) || 743 (hw->mac.type == e1000_82547_rev_2) || 744 (hw->mac.type == e1000_82541_rev_2)) 745 e1000_init_script_state_82541(hw, B_TRUE); 746 747 /* Enable the TTL workaround for 82541/82547 */ 748 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 749 750 #ifdef __sparc 751 Adapter->strip_crc = B_TRUE; 752 #else 753 Adapter->strip_crc = B_FALSE; 754 #endif 755 756 /* Get conf file properties */ 757 e1000g_get_conf(Adapter); 758 759 /* Get speed/duplex settings in conf file */ 760 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 761 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 762 e1000g_force_speed_duplex(Adapter); 763 764 /* Get Jumbo Frames settings in conf file */ 765 e1000g_get_max_frame_size(Adapter); 766 767 /* Set Rx/Tx buffer size */ 768 e1000g_set_bufsize(Adapter); 769 770 /* Master Latency Timer */ 771 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 772 773 /* copper options */ 774 if (hw->media_type == e1000_media_type_copper) { 775 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 776 hw->phy.disable_polarity_correction = B_FALSE; 777 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 778 } 779 780 /* The initial link state should be "unknown" */ 781 Adapter->link_state = LINK_STATE_UNKNOWN; 782 783 /* Initialize rx parameters */ 784 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 785 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 786 787 /* Initialize tx parameters */ 788 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 789 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 790 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 791 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 792 793 tx_ring = Adapter->tx_ring; 794 tx_ring->frags_limit = 795 (hw->mac.max_frame_size / Adapter->tx_bcopy_thresh) + 2; 796 if (tx_ring->frags_limit > (MAX_TX_DESC_PER_PACKET >> 1)) 797 tx_ring->frags_limit = (MAX_TX_DESC_PER_PACKET >> 1); 798 799 /* Initialize rx parameters */ 800 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 801 802 return (DDI_SUCCESS); 803 } 804 805 static void 806 e1000g_set_bufsize(struct e1000g *Adapter) 807 { 808 struct e1000_mac_info *mac = &Adapter->shared.mac; 809 uint64_t rx_size; 810 uint64_t tx_size; 811 812 #ifdef __sparc 813 dev_info_t *devinfo = Adapter->dip; 814 ulong_t iommu_pagesize; 815 816 /* Get the system page size */ 817 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 818 iommu_pagesize = dvma_pagesize(devinfo); 819 if (iommu_pagesize != 0) { 820 if (Adapter->sys_page_sz == iommu_pagesize) { 821 if (iommu_pagesize > 0x4000) 822 Adapter->sys_page_sz = 0x4000; 823 } else { 824 if (Adapter->sys_page_sz > iommu_pagesize) 825 Adapter->sys_page_sz = iommu_pagesize; 826 } 827 } 828 Adapter->dvma_page_num = mac->max_frame_size / 829 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 830 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 831 #endif 832 833 mac->min_frame_size = ETHERMIN + ETHERFCSL; 834 835 rx_size = mac->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 836 if ((rx_size > FRAME_SIZE_UPTO_2K) && (rx_size <= FRAME_SIZE_UPTO_4K)) 837 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 838 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 839 (rx_size <= FRAME_SIZE_UPTO_8K)) 840 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 841 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 842 (rx_size <= FRAME_SIZE_UPTO_16K)) 843 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 844 else 845 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 846 847 tx_size = mac->max_frame_size; 848 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 849 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 850 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 851 (tx_size <= FRAME_SIZE_UPTO_8K)) 852 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 853 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 854 (tx_size <= FRAME_SIZE_UPTO_16K)) 855 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 856 else 857 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 858 859 #ifndef NO_82542_SUPPORT 860 /* 861 * For Wiseman adapters we have an requirement of having receive 862 * buffers aligned at 256 byte boundary. Since Livengood does not 863 * require this and forcing it for all hardwares will have 864 * performance implications, I am making it applicable only for 865 * Wiseman and for Jumbo frames enabled mode as rest of the time, 866 * it is okay to have normal frames...but it does involve a 867 * potential risk where we may loose data if buffer is not 868 * aligned...so all wiseman boards to have 256 byte aligned 869 * buffers 870 */ 871 if (mac->type < e1000_82543) 872 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 873 else 874 Adapter->rx_buf_align = 1; 875 #endif 876 } 877 878 /* 879 * e1000g_detach - driver detach 880 * 881 * The detach() function is the complement of the attach routine. 882 * If cmd is set to DDI_DETACH, detach() is used to remove the 883 * state associated with a given instance of a device node 884 * prior to the removal of that instance from the system. 885 * 886 * The detach() function will be called once for each instance 887 * of the device for which there has been a successful attach() 888 * once there are no longer any opens on the device. 889 * 890 * Interrupts routine are disabled, All memory allocated by this 891 * driver are freed. 892 */ 893 static int 894 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 895 { 896 struct e1000g *Adapter; 897 boolean_t rx_drain; 898 899 switch (cmd) { 900 default: 901 return (DDI_FAILURE); 902 903 case DDI_SUSPEND: 904 return (e1000g_suspend(devinfo)); 905 906 case DDI_DETACH: 907 break; 908 } 909 910 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 911 if (Adapter == NULL) 912 return (DDI_FAILURE); 913 914 if (mac_unregister(Adapter->mh) != 0) { 915 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 916 return (DDI_FAILURE); 917 } 918 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 919 920 921 if (Adapter->chip_state != E1000G_STOP) 922 e1000g_stop(Adapter, B_TRUE); 923 924 rx_drain = e1000g_rx_drain(Adapter); 925 926 /* 927 * If e1000g_force_detach is enabled, driver detach is safe. 928 * We will let e1000g_free_priv_devi_node routine determine 929 * whether we need to free the priv_dip entry for current 930 * driver instance. 931 */ 932 if (e1000g_force_detach) { 933 e1000g_free_priv_devi_node(Adapter, rx_drain); 934 } else { 935 if (!rx_drain) 936 return (DDI_FAILURE); 937 } 938 939 e1000g_unattach(devinfo, Adapter); 940 941 return (DDI_SUCCESS); 942 } 943 944 /* 945 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 946 * 947 * If free_flag is true, that indicates the upper layer is not holding 948 * the rx buffers, we could free the priv_dip entry safely. 949 * 950 * Otherwise, we have to keep this entry even after driver detached, 951 * and we also need to mark this entry with E1000G_PRIV_DEVI_DETACH flag, 952 * so that driver could free it while all of rx buffers are returned 953 * by upper layer later. 954 */ 955 static void 956 e1000g_free_priv_devi_node(struct e1000g *Adapter, boolean_t free_flag) 957 { 958 private_devi_list_t *devi_node, *devi_del; 959 960 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 961 ASSERT(e1000g_private_devi_list != NULL); 962 ASSERT(Adapter->priv_dip != NULL); 963 964 devi_node = e1000g_private_devi_list; 965 if (devi_node->priv_dip == Adapter->priv_dip) { 966 if (free_flag) { 967 e1000g_private_devi_list = 968 devi_node->next; 969 kmem_free(devi_node->priv_dip, 970 sizeof (struct dev_info)); 971 kmem_free(devi_node, 972 sizeof (private_devi_list_t)); 973 } else { 974 ASSERT(e1000g_mblks_pending != 0); 975 devi_node->flag = 976 E1000G_PRIV_DEVI_DETACH; 977 } 978 rw_exit(&e1000g_rx_detach_lock); 979 return; 980 } 981 982 devi_node = e1000g_private_devi_list; 983 while (devi_node->next != NULL) { 984 if (devi_node->next->priv_dip == Adapter->priv_dip) { 985 if (free_flag) { 986 devi_del = devi_node->next; 987 devi_node->next = devi_del->next; 988 kmem_free(devi_del->priv_dip, 989 sizeof (struct dev_info)); 990 kmem_free(devi_del, 991 sizeof (private_devi_list_t)); 992 } else { 993 ASSERT(e1000g_mblks_pending != 0); 994 devi_node->next->flag = 995 E1000G_PRIV_DEVI_DETACH; 996 } 997 break; 998 } 999 devi_node = devi_node->next; 1000 } 1001 rw_exit(&e1000g_rx_detach_lock); 1002 } 1003 1004 static void 1005 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1006 { 1007 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1008 (void) e1000g_disable_intrs(Adapter); 1009 } 1010 1011 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1012 (void) mac_unregister(Adapter->mh); 1013 } 1014 1015 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1016 (void) e1000g_rem_intrs(Adapter); 1017 } 1018 1019 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1020 (void) ddi_prop_remove_all(devinfo); 1021 } 1022 1023 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1024 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1025 } 1026 1027 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1028 stop_link_timer(Adapter); 1029 if (e1000_reset_hw(&Adapter->shared) != 0) { 1030 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1031 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1032 } 1033 } 1034 1035 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1036 if (Adapter->osdep.reg_handle != NULL) 1037 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1038 if (Adapter->osdep.ich_flash_handle != NULL) 1039 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1040 } 1041 1042 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1043 if (Adapter->osdep.cfg_handle != NULL) 1044 pci_config_teardown(&Adapter->osdep.cfg_handle); 1045 } 1046 1047 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1048 e1000g_destroy_locks(Adapter); 1049 } 1050 1051 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1052 e1000g_fm_fini(Adapter); 1053 } 1054 1055 e1000_remove_device(&Adapter->shared); 1056 1057 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1058 1059 /* 1060 * Another hotplug spec requirement, 1061 * run ddi_set_driver_private(devinfo, null); 1062 */ 1063 ddi_set_driver_private(devinfo, NULL); 1064 } 1065 1066 static void 1067 e1000g_init_locks(struct e1000g *Adapter) 1068 { 1069 e1000g_tx_ring_t *tx_ring; 1070 e1000g_rx_ring_t *rx_ring; 1071 1072 rw_init(&Adapter->chip_lock, NULL, 1073 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1074 mutex_init(&Adapter->link_lock, NULL, 1075 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1076 mutex_init(&Adapter->watchdog_lock, NULL, 1077 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1078 1079 tx_ring = Adapter->tx_ring; 1080 1081 mutex_init(&tx_ring->tx_lock, NULL, 1082 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1083 mutex_init(&tx_ring->usedlist_lock, NULL, 1084 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1085 mutex_init(&tx_ring->freelist_lock, NULL, 1086 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1087 1088 rx_ring = Adapter->rx_ring; 1089 1090 mutex_init(&rx_ring->freelist_lock, NULL, 1091 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1092 } 1093 1094 static void 1095 e1000g_destroy_locks(struct e1000g *Adapter) 1096 { 1097 e1000g_tx_ring_t *tx_ring; 1098 e1000g_rx_ring_t *rx_ring; 1099 1100 tx_ring = Adapter->tx_ring; 1101 mutex_destroy(&tx_ring->tx_lock); 1102 mutex_destroy(&tx_ring->usedlist_lock); 1103 mutex_destroy(&tx_ring->freelist_lock); 1104 1105 rx_ring = Adapter->rx_ring; 1106 mutex_destroy(&rx_ring->freelist_lock); 1107 1108 mutex_destroy(&Adapter->link_lock); 1109 mutex_destroy(&Adapter->watchdog_lock); 1110 rw_destroy(&Adapter->chip_lock); 1111 } 1112 1113 static int 1114 e1000g_resume(dev_info_t *devinfo) 1115 { 1116 struct e1000g *Adapter; 1117 1118 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1119 if (Adapter == NULL) 1120 return (DDI_FAILURE); 1121 1122 if (e1000g_start(Adapter, B_TRUE)) 1123 return (DDI_FAILURE); 1124 1125 return (DDI_SUCCESS); 1126 } 1127 1128 static int 1129 e1000g_suspend(dev_info_t *devinfo) 1130 { 1131 struct e1000g *Adapter; 1132 1133 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1134 if (Adapter == NULL) 1135 return (DDI_FAILURE); 1136 1137 e1000g_stop(Adapter, B_TRUE); 1138 1139 return (DDI_SUCCESS); 1140 } 1141 1142 static int 1143 e1000g_init(struct e1000g *Adapter) 1144 { 1145 uint32_t pba; 1146 uint32_t high_water; 1147 struct e1000_hw *hw; 1148 clock_t link_timeout; 1149 1150 hw = &Adapter->shared; 1151 1152 rw_enter(&Adapter->chip_lock, RW_WRITER); 1153 1154 /* 1155 * reset to put the hardware in a known state 1156 * before we try to do anything with the eeprom 1157 */ 1158 if (e1000_reset_hw(hw) != 0) { 1159 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1160 goto init_fail; 1161 } 1162 1163 if (e1000_validate_nvm_checksum(hw) < 0) { 1164 /* 1165 * Some PCI-E parts fail the first check due to 1166 * the link being in sleep state. Call it again, 1167 * if it fails a second time its a real issue. 1168 */ 1169 if (e1000_validate_nvm_checksum(hw) < 0) { 1170 e1000g_log(Adapter, CE_WARN, 1171 "Invalid NVM checksum. Please contact " 1172 "the vendor to update the NVM."); 1173 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1174 goto init_fail; 1175 } 1176 } 1177 1178 #ifdef __sparc 1179 /* 1180 * Firstly, we try to get the local ethernet address from OBP. If 1181 * fail, we get from EEPROM of NIC card. 1182 */ 1183 if (!e1000g_find_mac_address(Adapter)) { 1184 if (e1000_read_mac_addr(hw) < 0) { 1185 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1186 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1187 goto init_fail; 1188 } 1189 } 1190 #else 1191 /* Get the local ethernet address. */ 1192 if (e1000_read_mac_addr(hw) < 0) { 1193 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1194 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1195 goto init_fail; 1196 } 1197 #endif 1198 1199 /* check for valid mac address */ 1200 if (!is_valid_mac_addr(hw->mac.addr)) { 1201 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1202 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1203 goto init_fail; 1204 } 1205 1206 /* Set LAA state for 82571 chipset */ 1207 e1000_set_laa_state_82571(hw, B_TRUE); 1208 1209 /* Master Latency Timer implementation */ 1210 if (Adapter->master_latency_timer) { 1211 pci_config_put8(Adapter->osdep.cfg_handle, 1212 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1213 } 1214 1215 if (hw->mac.type < e1000_82547) { 1216 /* 1217 * Total FIFO is 64K 1218 */ 1219 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1220 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1221 else 1222 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1223 } else if (hw->mac.type >= e1000_82571 && 1224 hw->mac.type <= e1000_82572) { 1225 /* 1226 * Total FIFO is 48K 1227 */ 1228 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1229 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1230 else 1231 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1232 } else if (hw->mac.type == e1000_ich8lan) { 1233 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1234 } else if (hw->mac.type == e1000_ich9lan) { 1235 pba = E1000_PBA_12K; 1236 } else { 1237 /* 1238 * Total FIFO is 40K 1239 */ 1240 if (hw->mac.max_frame_size > FRAME_SIZE_UPTO_8K) 1241 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1242 else 1243 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1244 } 1245 E1000_WRITE_REG(hw, E1000_PBA, pba); 1246 1247 /* 1248 * These parameters set thresholds for the adapter's generation(Tx) 1249 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1250 * settings. Flow control is enabled or disabled in the configuration 1251 * file. 1252 * High-water mark is set down from the top of the rx fifo (not 1253 * sensitive to max_frame_size) and low-water is set just below 1254 * high-water mark. 1255 * The high water mark must be low enough to fit one full frame above 1256 * it in the rx FIFO. Should be the lower of: 1257 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1258 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1259 * Rx FIFO size minus one full frame. 1260 */ 1261 high_water = min(((pba << 10) * 9 / 10), 1262 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_ich9lan) ? 1263 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1264 ((pba << 10) - hw->mac.max_frame_size))); 1265 1266 hw->mac.fc_high_water = high_water & 0xFFF8; 1267 hw->mac.fc_low_water = hw->mac.fc_high_water - 8; 1268 1269 if (hw->mac.type == e1000_80003es2lan) 1270 hw->mac.fc_pause_time = 0xFFFF; 1271 else 1272 hw->mac.fc_pause_time = E1000_FC_PAUSE_TIME; 1273 hw->mac.fc_send_xon = B_TRUE; 1274 hw->mac.fc = hw->mac.original_fc; 1275 1276 /* 1277 * Reset the adapter hardware the second time. 1278 */ 1279 if (e1000_reset_hw(hw) != 0) { 1280 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1281 goto init_fail; 1282 } 1283 1284 /* disable wakeup control by default */ 1285 if (hw->mac.type >= e1000_82544) 1286 E1000_WRITE_REG(hw, E1000_WUC, 0); 1287 1288 /* MWI setup */ 1289 e1000_pci_set_mwi(hw); 1290 1291 /* 1292 * Configure/Initialize hardware 1293 */ 1294 if (e1000_init_hw(hw) < 0) { 1295 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1296 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1297 goto init_fail; 1298 } 1299 1300 /* Disable Smart Power Down */ 1301 phy_spd_state(hw, B_FALSE); 1302 1303 /* Make sure driver has control */ 1304 e1000g_get_driver_control(hw); 1305 1306 /* 1307 * Initialize unicast addresses. 1308 */ 1309 e1000g_init_unicst(Adapter); 1310 1311 /* 1312 * Setup and initialize the mctable structures. After this routine 1313 * completes Multicast table will be set 1314 */ 1315 e1000g_setup_multicast(Adapter); 1316 msec_delay(5); 1317 1318 /* 1319 * Implement Adaptive IFS 1320 */ 1321 e1000_reset_adaptive(hw); 1322 1323 /* Setup Interrupt Throttling Register */ 1324 if (hw->mac.type >= e1000_82540) { 1325 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1326 } else 1327 Adapter->intr_adaptive = B_FALSE; 1328 1329 /* Start the timer for link setup */ 1330 if (hw->mac.autoneg) 1331 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1332 else 1333 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1334 1335 mutex_enter(&Adapter->link_lock); 1336 if (hw->phy.wait_for_link) { 1337 Adapter->link_complete = B_TRUE; 1338 } else { 1339 Adapter->link_complete = B_FALSE; 1340 Adapter->link_tid = timeout(e1000g_link_timer, 1341 (void *)Adapter, link_timeout); 1342 } 1343 mutex_exit(&Adapter->link_lock); 1344 1345 /* Enable PCI-Ex master */ 1346 if (hw->bus.type == e1000_bus_type_pci_express) { 1347 e1000_enable_pciex_master(hw); 1348 } 1349 1350 /* Save the state of the phy */ 1351 e1000g_get_phy_state(Adapter); 1352 1353 e1000g_param_sync(Adapter); 1354 1355 Adapter->init_count++; 1356 1357 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1358 goto init_fail; 1359 } 1360 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1361 goto init_fail; 1362 } 1363 1364 rw_exit(&Adapter->chip_lock); 1365 1366 return (DDI_SUCCESS); 1367 1368 init_fail: 1369 rw_exit(&Adapter->chip_lock); 1370 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1371 return (DDI_FAILURE); 1372 } 1373 1374 /* 1375 * Check if the link is up 1376 */ 1377 static boolean_t 1378 e1000g_link_up(struct e1000g *Adapter) 1379 { 1380 struct e1000_hw *hw; 1381 boolean_t link_up; 1382 1383 hw = &Adapter->shared; 1384 1385 e1000_check_for_link(hw); 1386 1387 if ((E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU) || 1388 ((!hw->mac.get_link_status) && (hw->mac.type == e1000_82543)) || 1389 ((hw->media_type == e1000_media_type_internal_serdes) && 1390 (hw->mac.serdes_has_link))) { 1391 link_up = B_TRUE; 1392 } else { 1393 link_up = B_FALSE; 1394 } 1395 1396 return (link_up); 1397 } 1398 1399 static void 1400 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1401 { 1402 struct iocblk *iocp; 1403 struct e1000g *e1000gp; 1404 enum ioc_reply status; 1405 int err; 1406 1407 iocp = (struct iocblk *)mp->b_rptr; 1408 iocp->ioc_error = 0; 1409 e1000gp = (struct e1000g *)arg; 1410 1411 ASSERT(e1000gp); 1412 if (e1000gp == NULL) { 1413 miocnak(q, mp, 0, EINVAL); 1414 return; 1415 } 1416 1417 switch (iocp->ioc_cmd) { 1418 1419 case LB_GET_INFO_SIZE: 1420 case LB_GET_INFO: 1421 case LB_GET_MODE: 1422 case LB_SET_MODE: 1423 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1424 break; 1425 1426 1427 #ifdef E1000G_DEBUG 1428 case E1000G_IOC_REG_PEEK: 1429 case E1000G_IOC_REG_POKE: 1430 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1431 break; 1432 case E1000G_IOC_CHIP_RESET: 1433 e1000gp->reset_count++; 1434 if (e1000g_reset(e1000gp)) 1435 status = IOC_ACK; 1436 else 1437 status = IOC_INVAL; 1438 break; 1439 #endif 1440 default: 1441 status = IOC_INVAL; 1442 break; 1443 } 1444 1445 /* 1446 * Decide how to reply 1447 */ 1448 switch (status) { 1449 default: 1450 case IOC_INVAL: 1451 /* 1452 * Error, reply with a NAK and EINVAL or the specified error 1453 */ 1454 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1455 EINVAL : iocp->ioc_error); 1456 break; 1457 1458 case IOC_DONE: 1459 /* 1460 * OK, reply already sent 1461 */ 1462 break; 1463 1464 case IOC_ACK: 1465 /* 1466 * OK, reply with an ACK 1467 */ 1468 miocack(q, mp, 0, 0); 1469 break; 1470 1471 case IOC_REPLY: 1472 /* 1473 * OK, send prepared reply as ACK or NAK 1474 */ 1475 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1476 M_IOCACK : M_IOCNAK; 1477 qreply(q, mp); 1478 break; 1479 } 1480 } 1481 1482 static int 1483 e1000g_m_start(void *arg) 1484 { 1485 struct e1000g *Adapter = (struct e1000g *)arg; 1486 1487 return (e1000g_start(Adapter, B_TRUE)); 1488 } 1489 1490 static int 1491 e1000g_start(struct e1000g *Adapter, boolean_t global) 1492 { 1493 if (global) { 1494 /* Allocate dma resources for descriptors and buffers */ 1495 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1496 e1000g_log(Adapter, CE_WARN, 1497 "Alloc DMA resources failed"); 1498 return (ENOTACTIVE); 1499 } 1500 Adapter->rx_buffer_setup = B_FALSE; 1501 } 1502 1503 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1504 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1505 e1000g_log(Adapter, CE_WARN, 1506 "Adapter initialization failed"); 1507 if (global) 1508 e1000g_release_dma_resources(Adapter); 1509 return (ENOTACTIVE); 1510 } 1511 } 1512 1513 rw_enter(&Adapter->chip_lock, RW_WRITER); 1514 1515 /* Setup and initialize the transmit structures */ 1516 e1000g_tx_setup(Adapter); 1517 msec_delay(5); 1518 1519 /* Setup and initialize the receive structures */ 1520 e1000g_rx_setup(Adapter); 1521 msec_delay(5); 1522 1523 e1000g_mask_interrupt(Adapter); 1524 1525 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1526 rw_exit(&Adapter->chip_lock); 1527 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1528 return (ENOTACTIVE); 1529 } 1530 1531 Adapter->chip_state = E1000G_START; 1532 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1533 1534 rw_exit(&Adapter->chip_lock); 1535 1536 /* Enable and start the watchdog timer */ 1537 enable_watchdog_timer(Adapter); 1538 1539 return (0); 1540 } 1541 1542 static void 1543 e1000g_m_stop(void *arg) 1544 { 1545 struct e1000g *Adapter = (struct e1000g *)arg; 1546 1547 e1000g_stop(Adapter, B_TRUE); 1548 } 1549 1550 static void 1551 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1552 { 1553 /* Set stop flags */ 1554 rw_enter(&Adapter->chip_lock, RW_WRITER); 1555 1556 Adapter->chip_state = E1000G_STOP; 1557 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1558 1559 rw_exit(&Adapter->chip_lock); 1560 1561 /* Drain tx sessions */ 1562 (void) e1000g_tx_drain(Adapter); 1563 1564 /* Disable and stop all the timers */ 1565 disable_watchdog_timer(Adapter); 1566 stop_link_timer(Adapter); 1567 stop_82547_timer(Adapter->tx_ring); 1568 1569 /* Stop the chip and release pending resources */ 1570 rw_enter(&Adapter->chip_lock, RW_WRITER); 1571 1572 e1000g_clear_all_interrupts(Adapter); 1573 if (e1000_reset_hw(&Adapter->shared) != 0) { 1574 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1575 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1576 } 1577 1578 /* Release resources still held by the TX descriptors */ 1579 e1000g_tx_clean(Adapter); 1580 1581 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1582 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1583 1584 /* Clean the pending rx jumbo packet fragment */ 1585 e1000g_rx_clean(Adapter); 1586 1587 rw_exit(&Adapter->chip_lock); 1588 1589 if (global) 1590 e1000g_release_dma_resources(Adapter); 1591 } 1592 1593 static void 1594 e1000g_rx_clean(struct e1000g *Adapter) 1595 { 1596 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 1597 1598 if (rx_ring->rx_mblk != NULL) { 1599 freemsg(rx_ring->rx_mblk); 1600 rx_ring->rx_mblk = NULL; 1601 rx_ring->rx_mblk_tail = NULL; 1602 rx_ring->rx_mblk_len = 0; 1603 } 1604 } 1605 1606 static void 1607 e1000g_tx_clean(struct e1000g *Adapter) 1608 { 1609 e1000g_tx_ring_t *tx_ring; 1610 p_tx_sw_packet_t packet; 1611 mblk_t *mp; 1612 mblk_t *nmp; 1613 uint32_t packet_count; 1614 1615 tx_ring = Adapter->tx_ring; 1616 1617 /* 1618 * Here we don't need to protect the lists using 1619 * the usedlist_lock and freelist_lock, for they 1620 * have been protected by the chip_lock. 1621 */ 1622 mp = NULL; 1623 nmp = NULL; 1624 packet_count = 0; 1625 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 1626 while (packet != NULL) { 1627 if (packet->mp != NULL) { 1628 /* Assemble the message chain */ 1629 if (mp == NULL) { 1630 mp = packet->mp; 1631 nmp = packet->mp; 1632 } else { 1633 nmp->b_next = packet->mp; 1634 nmp = packet->mp; 1635 } 1636 /* Disconnect the message from the sw packet */ 1637 packet->mp = NULL; 1638 } 1639 1640 e1000g_free_tx_swpkt(packet); 1641 packet_count++; 1642 1643 packet = (p_tx_sw_packet_t) 1644 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1645 } 1646 1647 if (mp != NULL) 1648 freemsgchain(mp); 1649 1650 if (packet_count > 0) { 1651 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1652 QUEUE_INIT_LIST(&tx_ring->used_list); 1653 1654 /* Setup TX descriptor pointers */ 1655 tx_ring->tbd_next = tx_ring->tbd_first; 1656 tx_ring->tbd_oldest = tx_ring->tbd_first; 1657 1658 /* Setup our HW Tx Head & Tail descriptor pointers */ 1659 E1000_WRITE_REG(&Adapter->shared, E1000_TDH, 0); 1660 E1000_WRITE_REG(&Adapter->shared, E1000_TDT, 0); 1661 } 1662 } 1663 1664 static boolean_t 1665 e1000g_tx_drain(struct e1000g *Adapter) 1666 { 1667 int i; 1668 boolean_t done; 1669 e1000g_tx_ring_t *tx_ring; 1670 1671 tx_ring = Adapter->tx_ring; 1672 1673 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1674 for (i = 0; i < TX_DRAIN_TIME; i++) { 1675 mutex_enter(&tx_ring->usedlist_lock); 1676 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1677 mutex_exit(&tx_ring->usedlist_lock); 1678 1679 if (done) 1680 break; 1681 1682 msec_delay(1); 1683 } 1684 1685 return (done); 1686 } 1687 1688 static boolean_t 1689 e1000g_rx_drain(struct e1000g *Adapter) 1690 { 1691 e1000g_rx_ring_t *rx_ring; 1692 p_rx_sw_packet_t packet; 1693 boolean_t done; 1694 1695 rx_ring = Adapter->rx_ring; 1696 done = B_TRUE; 1697 1698 rw_enter(&e1000g_rx_detach_lock, RW_WRITER); 1699 1700 while (rx_ring->pending_list != NULL) { 1701 packet = rx_ring->pending_list; 1702 rx_ring->pending_list = 1703 rx_ring->pending_list->next; 1704 1705 if (packet->flag == E1000G_RX_SW_STOP) { 1706 packet->flag = E1000G_RX_SW_DETACH; 1707 done = B_FALSE; 1708 } else { 1709 ASSERT(packet->flag == E1000G_RX_SW_FREE); 1710 ASSERT(packet->mp == NULL); 1711 e1000g_free_rx_sw_packet(packet); 1712 } 1713 } 1714 1715 rw_exit(&e1000g_rx_detach_lock); 1716 1717 return (done); 1718 } 1719 1720 boolean_t 1721 e1000g_reset(struct e1000g *Adapter) 1722 { 1723 e1000g_stop(Adapter, B_FALSE); 1724 1725 if (e1000g_start(Adapter, B_FALSE)) { 1726 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1727 return (B_FALSE); 1728 } 1729 1730 return (B_TRUE); 1731 } 1732 1733 boolean_t 1734 e1000g_global_reset(struct e1000g *Adapter) 1735 { 1736 e1000g_stop(Adapter, B_TRUE); 1737 1738 Adapter->init_count = 0; 1739 1740 if (e1000g_start(Adapter, B_TRUE)) { 1741 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1742 return (B_FALSE); 1743 } 1744 1745 return (B_TRUE); 1746 } 1747 1748 /* 1749 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 1750 * 1751 * This interrupt service routine is for PCI-Express adapters. 1752 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 1753 * bit is set. 1754 */ 1755 static uint_t 1756 e1000g_intr_pciexpress(caddr_t arg) 1757 { 1758 struct e1000g *Adapter; 1759 uint32_t icr; 1760 1761 Adapter = (struct e1000g *)arg; 1762 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1763 1764 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1765 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1766 1767 if (icr & E1000_ICR_INT_ASSERTED) { 1768 /* 1769 * E1000_ICR_INT_ASSERTED bit was set: 1770 * Read(Clear) the ICR, claim this interrupt, 1771 * look for work to do. 1772 */ 1773 e1000g_intr_work(Adapter, icr); 1774 return (DDI_INTR_CLAIMED); 1775 } else { 1776 /* 1777 * E1000_ICR_INT_ASSERTED bit was not set: 1778 * Don't claim this interrupt, return immediately. 1779 */ 1780 return (DDI_INTR_UNCLAIMED); 1781 } 1782 } 1783 1784 /* 1785 * e1000g_intr - ISR for PCI/PCI-X chipsets 1786 * 1787 * This interrupt service routine is for PCI/PCI-X adapters. 1788 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 1789 * bit is set or not. 1790 */ 1791 static uint_t 1792 e1000g_intr(caddr_t arg) 1793 { 1794 struct e1000g *Adapter; 1795 uint32_t icr; 1796 1797 Adapter = (struct e1000g *)arg; 1798 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 1799 1800 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1801 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 1802 1803 if (icr) { 1804 /* 1805 * Any bit was set in ICR: 1806 * Read(Clear) the ICR, claim this interrupt, 1807 * look for work to do. 1808 */ 1809 e1000g_intr_work(Adapter, icr); 1810 return (DDI_INTR_CLAIMED); 1811 } else { 1812 /* 1813 * No bit was set in ICR: 1814 * Don't claim this interrupt, return immediately. 1815 */ 1816 return (DDI_INTR_UNCLAIMED); 1817 } 1818 } 1819 1820 /* 1821 * e1000g_intr_work - actual processing of ISR 1822 * 1823 * Read(clear) the ICR contents and call appropriate interrupt 1824 * processing routines. 1825 */ 1826 static void 1827 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 1828 { 1829 struct e1000_hw *hw; 1830 hw = &Adapter->shared; 1831 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 1832 uint32_t itr; 1833 1834 Adapter->rx_pkt_cnt = 0; 1835 Adapter->tx_pkt_cnt = 0; 1836 1837 rw_enter(&Adapter->chip_lock, RW_READER); 1838 /* 1839 * Here we need to check the "chip_state" flag within the chip_lock to 1840 * ensure the receive routine will not execute when the adapter is 1841 * being reset. 1842 */ 1843 if (Adapter->chip_state != E1000G_START) { 1844 rw_exit(&Adapter->chip_lock); 1845 return; 1846 } 1847 1848 if (icr & E1000_ICR_RXT0) { 1849 mblk_t *mp; 1850 1851 mp = e1000g_receive(Adapter); 1852 1853 rw_exit(&Adapter->chip_lock); 1854 1855 if (mp != NULL) 1856 mac_rx(Adapter->mh, Adapter->mrh, mp); 1857 } else 1858 rw_exit(&Adapter->chip_lock); 1859 1860 if (icr & E1000_ICR_TXDW) { 1861 if (!Adapter->tx_intr_enable) 1862 e1000g_clear_tx_interrupt(Adapter); 1863 1864 /* Recycle the tx descriptors */ 1865 rw_enter(&Adapter->chip_lock, RW_READER); 1866 e1000g_recycle(tx_ring); 1867 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 1868 rw_exit(&Adapter->chip_lock); 1869 1870 /* Schedule the re-transmit */ 1871 if (tx_ring->resched_needed && 1872 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 1873 tx_ring->resched_needed = B_FALSE; 1874 mac_tx_update(Adapter->mh); 1875 E1000G_STAT(tx_ring->stat_reschedule); 1876 } 1877 } 1878 1879 if (Adapter->intr_adaptive) { 1880 itr = e1000g_get_itr(Adapter->rx_pkt_cnt, Adapter->tx_pkt_cnt, 1881 Adapter->intr_throttling_rate); 1882 if (itr) { 1883 E1000_WRITE_REG(hw, E1000_ITR, itr); 1884 Adapter->intr_throttling_rate = itr; 1885 } 1886 } 1887 1888 /* 1889 * The Receive Sequence errors RXSEQ and the link status change LSC 1890 * are checked to detect that the cable has been pulled out. For 1891 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1892 * are an indication that cable is not connected. 1893 */ 1894 if ((icr & E1000_ICR_RXSEQ) || 1895 (icr & E1000_ICR_LSC) || 1896 (icr & E1000_ICR_GPI_EN1)) { 1897 boolean_t link_changed; 1898 timeout_id_t tid = 0; 1899 1900 stop_watchdog_timer(Adapter); 1901 1902 rw_enter(&Adapter->chip_lock, RW_WRITER); 1903 1904 /* 1905 * Because we got a link-status-change interrupt, force 1906 * e1000_check_for_link() to look at phy 1907 */ 1908 Adapter->shared.mac.get_link_status = B_TRUE; 1909 1910 /* e1000g_link_check takes care of link status change */ 1911 link_changed = e1000g_link_check(Adapter); 1912 1913 /* Get new phy state */ 1914 e1000g_get_phy_state(Adapter); 1915 1916 /* 1917 * If the link timer has not timed out, we'll not notify 1918 * the upper layer with any link state until the link is up. 1919 */ 1920 if (link_changed && !Adapter->link_complete) { 1921 if (Adapter->link_state == LINK_STATE_UP) { 1922 mutex_enter(&Adapter->link_lock); 1923 Adapter->link_complete = B_TRUE; 1924 tid = Adapter->link_tid; 1925 Adapter->link_tid = 0; 1926 mutex_exit(&Adapter->link_lock); 1927 } else { 1928 link_changed = B_FALSE; 1929 } 1930 } 1931 rw_exit(&Adapter->chip_lock); 1932 1933 if (link_changed) { 1934 if (tid != 0) 1935 (void) untimeout(tid); 1936 1937 /* 1938 * Workaround for esb2. Data stuck in fifo on a link 1939 * down event. Reset the adapter to recover it. 1940 */ 1941 if ((Adapter->link_state == LINK_STATE_DOWN) && 1942 (Adapter->shared.mac.type == e1000_80003es2lan)) 1943 (void) e1000g_reset(Adapter); 1944 1945 mac_link_update(Adapter->mh, Adapter->link_state); 1946 } 1947 1948 start_watchdog_timer(Adapter); 1949 } 1950 } 1951 1952 static uint32_t 1953 e1000g_get_itr(uint32_t rx_packet, uint32_t tx_packet, uint32_t cur_itr) 1954 { 1955 uint32_t new_itr; 1956 1957 /* 1958 * Determine a propper itr according to rx/tx packet count 1959 * per interrupt, the value of itr are based on document 1960 * and testing. 1961 */ 1962 if ((rx_packet < DEFAULT_INTR_PACKET_LOW) || 1963 (tx_packet < DEFAULT_INTR_PACKET_LOW)) { 1964 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1965 goto itr_done; 1966 } 1967 if ((rx_packet > DEFAULT_INTR_PACKET_HIGH) || 1968 (tx_packet > DEFAULT_INTR_PACKET_HIGH)) { 1969 new_itr = DEFAULT_INTR_THROTTLING_LOW; 1970 goto itr_done; 1971 } 1972 if (cur_itr < DEFAULT_INTR_THROTTLING_HIGH) { 1973 new_itr = cur_itr + (DEFAULT_INTR_THROTTLING_HIGH >> 2); 1974 if (new_itr > DEFAULT_INTR_THROTTLING_HIGH) 1975 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1976 } else 1977 new_itr = DEFAULT_INTR_THROTTLING_HIGH; 1978 1979 itr_done: 1980 if (cur_itr == new_itr) 1981 return (0); 1982 else 1983 return (new_itr); 1984 } 1985 1986 static void 1987 e1000g_init_unicst(struct e1000g *Adapter) 1988 { 1989 struct e1000_hw *hw; 1990 int slot; 1991 1992 hw = &Adapter->shared; 1993 1994 if (!Adapter->unicst_init) { 1995 /* Initialize the multiple unicast addresses */ 1996 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1997 1998 if ((hw->mac.type == e1000_82571) && 1999 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2000 Adapter->unicst_total--; 2001 2002 Adapter->unicst_avail = Adapter->unicst_total - 1; 2003 2004 /* Store the default mac address */ 2005 e1000_rar_set(hw, hw->mac.addr, 0); 2006 if ((hw->mac.type == e1000_82571) && 2007 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2008 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2009 2010 bcopy(hw->mac.addr, Adapter->unicst_addr[0].mac.addr, 2011 ETHERADDRL); 2012 Adapter->unicst_addr[0].mac.set = 1; 2013 2014 for (slot = 1; slot < Adapter->unicst_total; slot++) 2015 Adapter->unicst_addr[slot].mac.set = 0; 2016 2017 Adapter->unicst_init = B_TRUE; 2018 } else { 2019 /* Recover the default mac address */ 2020 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac.addr, 2021 ETHERADDRL); 2022 2023 /* Store the default mac address */ 2024 e1000_rar_set(hw, hw->mac.addr, 0); 2025 if ((hw->mac.type == e1000_82571) && 2026 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2027 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2028 2029 /* Re-configure the RAR registers */ 2030 for (slot = 1; slot < Adapter->unicst_total; slot++) 2031 e1000_rar_set(hw, 2032 Adapter->unicst_addr[slot].mac.addr, slot); 2033 } 2034 2035 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2036 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2037 } 2038 2039 static int 2040 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 2041 { 2042 struct e1000g *Adapter; 2043 2044 Adapter = (struct e1000g *)arg; 2045 2046 /* Store the default MAC address */ 2047 bcopy(mac_addr, Adapter->shared.mac.addr, ETHERADDRL); 2048 2049 /* Set MAC address in address slot 0, which is the default address */ 2050 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 2051 } 2052 2053 static int 2054 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2055 mac_addr_slot_t slot) 2056 { 2057 struct e1000_hw *hw; 2058 2059 hw = &Adapter->shared; 2060 2061 rw_enter(&Adapter->chip_lock, RW_WRITER); 2062 2063 #ifndef NO_82542_SUPPORT 2064 /* 2065 * The first revision of Wiseman silicon (rev 2.0) has an errata 2066 * that requires the receiver to be in reset when any of the 2067 * receive address registers (RAR regs) are accessed. The first 2068 * rev of Wiseman silicon also requires MWI to be disabled when 2069 * a global reset or a receive reset is issued. So before we 2070 * initialize the RARs, we check the rev of the Wiseman controller 2071 * and work around any necessary HW errata. 2072 */ 2073 if ((hw->mac.type == e1000_82542) && 2074 (hw->revision_id == E1000_REVISION_2)) { 2075 e1000_pci_clear_mwi(hw); 2076 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2077 msec_delay(5); 2078 } 2079 #endif 2080 2081 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 2082 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2083 2084 if (slot == 0) { 2085 if ((hw->mac.type == e1000_82571) && 2086 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2087 e1000_rar_set(hw, (uint8_t *)mac_addr, LAST_RAR_ENTRY); 2088 } 2089 2090 #ifndef NO_82542_SUPPORT 2091 /* 2092 * If we are using Wiseman rev 2.0 silicon, we will have previously 2093 * put the receive in reset, and disabled MWI, to work around some 2094 * HW errata. Now we should take the receiver out of reset, and 2095 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2096 */ 2097 if ((hw->mac.type == e1000_82542) && 2098 (hw->revision_id == E1000_REVISION_2)) { 2099 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2100 msec_delay(1); 2101 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2102 e1000_pci_set_mwi(hw); 2103 e1000g_rx_setup(Adapter); 2104 } 2105 #endif 2106 2107 rw_exit(&Adapter->chip_lock); 2108 2109 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2110 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2111 return (EIO); 2112 } 2113 2114 return (0); 2115 } 2116 2117 /* 2118 * e1000g_m_unicst_add() - will find an unused address slot, set the 2119 * address value to the one specified, reserve that slot and enable 2120 * the NIC to start filtering on the new MAC address. 2121 * Returns 0 on success. 2122 */ 2123 static int 2124 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 2125 { 2126 struct e1000g *Adapter = (struct e1000g *)arg; 2127 mac_addr_slot_t slot; 2128 int err; 2129 2130 if (mac_unicst_verify(Adapter->mh, 2131 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2132 return (EINVAL); 2133 2134 rw_enter(&Adapter->chip_lock, RW_WRITER); 2135 if (Adapter->unicst_avail == 0) { 2136 /* no slots available */ 2137 rw_exit(&Adapter->chip_lock); 2138 return (ENOSPC); 2139 } 2140 2141 /* 2142 * Primary/default address is in slot 0. The next addresses 2143 * are the multiple MAC addresses. So multiple MAC address 0 2144 * is in slot 1, 1 in slot 2, and so on. So the first multiple 2145 * MAC address resides in slot 1. 2146 */ 2147 for (slot = 1; slot < Adapter->unicst_total; slot++) { 2148 if (Adapter->unicst_addr[slot].mac.set == 0) { 2149 Adapter->unicst_addr[slot].mac.set = 1; 2150 break; 2151 } 2152 } 2153 2154 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 2155 2156 Adapter->unicst_avail--; 2157 rw_exit(&Adapter->chip_lock); 2158 2159 maddr->mma_slot = slot; 2160 2161 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 2162 rw_enter(&Adapter->chip_lock, RW_WRITER); 2163 Adapter->unicst_addr[slot].mac.set = 0; 2164 Adapter->unicst_avail++; 2165 rw_exit(&Adapter->chip_lock); 2166 } 2167 2168 return (err); 2169 } 2170 2171 /* 2172 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 2173 * call to e1000g_m_unicst_add(). The slot number that was returned in 2174 * e1000g_m_unicst_add() is passed in the call to remove the address. 2175 * Returns 0 on success. 2176 */ 2177 static int 2178 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 2179 { 2180 struct e1000g *Adapter = (struct e1000g *)arg; 2181 int err; 2182 2183 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2184 return (EINVAL); 2185 2186 rw_enter(&Adapter->chip_lock, RW_WRITER); 2187 if (Adapter->unicst_addr[slot].mac.set == 1) { 2188 Adapter->unicst_addr[slot].mac.set = 0; 2189 Adapter->unicst_avail++; 2190 rw_exit(&Adapter->chip_lock); 2191 2192 /* Copy the default address to the passed slot */ 2193 if (err = e1000g_unicst_set(Adapter, 2194 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 2195 rw_enter(&Adapter->chip_lock, RW_WRITER); 2196 Adapter->unicst_addr[slot].mac.set = 1; 2197 Adapter->unicst_avail--; 2198 rw_exit(&Adapter->chip_lock); 2199 } 2200 return (err); 2201 } 2202 rw_exit(&Adapter->chip_lock); 2203 2204 return (EINVAL); 2205 } 2206 2207 /* 2208 * e1000g_m_unicst_modify() - modifies the value of an address that 2209 * has been added by e1000g_m_unicst_add(). The new address, address 2210 * length and the slot number that was returned in the call to add 2211 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 2212 * set to 0. Returns 0 on success. 2213 */ 2214 static int 2215 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 2216 { 2217 struct e1000g *Adapter = (struct e1000g *)arg; 2218 mac_addr_slot_t slot; 2219 2220 if (mac_unicst_verify(Adapter->mh, 2221 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 2222 return (EINVAL); 2223 2224 slot = maddr->mma_slot; 2225 2226 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2227 return (EINVAL); 2228 2229 rw_enter(&Adapter->chip_lock, RW_WRITER); 2230 if (Adapter->unicst_addr[slot].mac.set == 1) { 2231 rw_exit(&Adapter->chip_lock); 2232 2233 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 2234 } 2235 rw_exit(&Adapter->chip_lock); 2236 2237 return (EINVAL); 2238 } 2239 2240 /* 2241 * e1000g_m_unicst_get() - will get the MAC address and all other 2242 * information related to the address slot passed in mac_multi_addr_t. 2243 * mma_flags should be set to 0 in the call. 2244 * On return, mma_flags can take the following values: 2245 * 1) MMAC_SLOT_UNUSED 2246 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 2247 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 2248 * 4) MMAC_SLOT_USED 2249 */ 2250 static int 2251 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 2252 { 2253 struct e1000g *Adapter = (struct e1000g *)arg; 2254 mac_addr_slot_t slot; 2255 2256 slot = maddr->mma_slot; 2257 2258 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2259 return (EINVAL); 2260 2261 rw_enter(&Adapter->chip_lock, RW_WRITER); 2262 if (Adapter->unicst_addr[slot].mac.set == 1) { 2263 bcopy(Adapter->unicst_addr[slot].mac.addr, 2264 maddr->mma_addr, ETHERADDRL); 2265 maddr->mma_flags = MMAC_SLOT_USED; 2266 } else { 2267 maddr->mma_flags = MMAC_SLOT_UNUSED; 2268 } 2269 rw_exit(&Adapter->chip_lock); 2270 2271 return (0); 2272 } 2273 2274 static int 2275 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2276 { 2277 struct e1000_hw *hw = &Adapter->shared; 2278 unsigned i; 2279 int res = 0; 2280 2281 rw_enter(&Adapter->chip_lock, RW_WRITER); 2282 2283 if ((multiaddr[0] & 01) == 0) { 2284 res = EINVAL; 2285 goto done; 2286 } 2287 2288 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2289 res = ENOENT; 2290 goto done; 2291 } 2292 2293 bcopy(multiaddr, 2294 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2295 Adapter->mcast_count++; 2296 2297 /* 2298 * Update the MC table in the hardware 2299 */ 2300 e1000g_clear_interrupt(Adapter); 2301 2302 e1000g_setup_multicast(Adapter); 2303 2304 #ifndef NO_82542_SUPPORT 2305 if ((hw->mac.type == e1000_82542) && 2306 (hw->revision_id == E1000_REVISION_2)) 2307 e1000g_rx_setup(Adapter); 2308 #endif 2309 2310 e1000g_mask_interrupt(Adapter); 2311 2312 done: 2313 rw_exit(&Adapter->chip_lock); 2314 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2315 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2316 res = EIO; 2317 } 2318 2319 return (res); 2320 } 2321 2322 static int 2323 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2324 { 2325 struct e1000_hw *hw = &Adapter->shared; 2326 unsigned i; 2327 2328 rw_enter(&Adapter->chip_lock, RW_WRITER); 2329 2330 for (i = 0; i < Adapter->mcast_count; i++) { 2331 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2332 ETHERADDRL) == 0) { 2333 for (i++; i < Adapter->mcast_count; i++) { 2334 Adapter->mcast_table[i - 1] = 2335 Adapter->mcast_table[i]; 2336 } 2337 Adapter->mcast_count--; 2338 break; 2339 } 2340 } 2341 2342 /* 2343 * Update the MC table in the hardware 2344 */ 2345 e1000g_clear_interrupt(Adapter); 2346 2347 e1000g_setup_multicast(Adapter); 2348 2349 #ifndef NO_82542_SUPPORT 2350 if ((hw->mac.type == e1000_82542) && 2351 (hw->revision_id == E1000_REVISION_2)) 2352 e1000g_rx_setup(Adapter); 2353 #endif 2354 2355 e1000g_mask_interrupt(Adapter); 2356 2357 done: 2358 rw_exit(&Adapter->chip_lock); 2359 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2360 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2361 return (EIO); 2362 } 2363 2364 return (0); 2365 } 2366 2367 /* 2368 * e1000g_setup_multicast - setup multicast data structures 2369 * 2370 * This routine initializes all of the multicast related structures. 2371 */ 2372 void 2373 e1000g_setup_multicast(struct e1000g *Adapter) 2374 { 2375 uint8_t *mc_addr_list; 2376 uint32_t mc_addr_count; 2377 uint32_t rctl; 2378 struct e1000_hw *hw; 2379 2380 hw = &Adapter->shared; 2381 2382 /* 2383 * The e1000g has the ability to do perfect filtering of 16 2384 * addresses. The driver uses one of the e1000g's 16 receive 2385 * address registers for its node/network/mac/individual address. 2386 * So, we have room for up to 15 multicast addresses in the CAM, 2387 * additional MC addresses are handled by the MTA (Multicast Table 2388 * Array) 2389 */ 2390 2391 rctl = E1000_READ_REG(hw, E1000_RCTL); 2392 2393 mc_addr_list = (uint8_t *)Adapter->mcast_table; 2394 2395 if (Adapter->mcast_count > MAX_NUM_MULTICAST_ADDRESSES) { 2396 E1000G_DEBUGLOG_1(Adapter, CE_WARN, 2397 "Adapter requested more than %d MC Addresses.\n", 2398 MAX_NUM_MULTICAST_ADDRESSES); 2399 mc_addr_count = MAX_NUM_MULTICAST_ADDRESSES; 2400 } else { 2401 /* 2402 * Set the number of MC addresses that we are being 2403 * requested to use 2404 */ 2405 mc_addr_count = Adapter->mcast_count; 2406 } 2407 #ifndef NO_82542_SUPPORT 2408 /* 2409 * The Wiseman 2.0 silicon has an errata by which the receiver will 2410 * hang while writing to the receive address registers if the receiver 2411 * is not in reset before writing to the registers. Updating the RAR 2412 * is done during the setting up of the multicast table, hence the 2413 * receiver has to be put in reset before updating the multicast table 2414 * and then taken out of reset at the end 2415 */ 2416 /* 2417 * if WMI was enabled then dis able it before issueing the global 2418 * reset to the hardware. 2419 */ 2420 /* 2421 * Only required for WISEMAN_2_0 2422 */ 2423 if ((hw->mac.type == e1000_82542) && 2424 (hw->revision_id == E1000_REVISION_2)) { 2425 e1000_pci_clear_mwi(hw); 2426 /* 2427 * The e1000g must be in reset before changing any RA 2428 * registers. Reset receive unit. The chip will remain in 2429 * the reset state until software explicitly restarts it. 2430 */ 2431 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2432 /* Allow receiver time to go in to reset */ 2433 msec_delay(5); 2434 } 2435 #endif 2436 2437 e1000_mc_addr_list_update(hw, mc_addr_list, mc_addr_count, 2438 Adapter->unicst_total, hw->mac.rar_entry_count); 2439 2440 #ifndef NO_82542_SUPPORT 2441 /* 2442 * Only for Wiseman_2_0 2443 * If MWI was enabled then re-enable it after issueing (as we 2444 * disabled it up there) the receive reset command. 2445 * Wainwright does not have a receive reset command and only thing 2446 * close to it is global reset which will require tx setup also 2447 */ 2448 if ((hw->mac.type == e1000_82542) && 2449 (hw->revision_id == E1000_REVISION_2)) { 2450 /* 2451 * if WMI was enabled then reenable it after issueing the 2452 * global or receive reset to the hardware. 2453 */ 2454 2455 /* 2456 * Take receiver out of reset 2457 * clear E1000_RCTL_RST bit (and all others) 2458 */ 2459 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2460 msec_delay(5); 2461 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2462 e1000_pci_set_mwi(hw); 2463 } 2464 #endif 2465 2466 /* 2467 * Restore original value 2468 */ 2469 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 2470 } 2471 2472 int 2473 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2474 { 2475 struct e1000g *Adapter = (struct e1000g *)arg; 2476 2477 return ((add) ? multicst_add(Adapter, addr) 2478 : multicst_remove(Adapter, addr)); 2479 } 2480 2481 int 2482 e1000g_m_promisc(void *arg, boolean_t on) 2483 { 2484 struct e1000g *Adapter = (struct e1000g *)arg; 2485 uint32_t rctl; 2486 2487 rw_enter(&Adapter->chip_lock, RW_WRITER); 2488 2489 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2490 2491 if (on) 2492 rctl |= 2493 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2494 else 2495 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2496 2497 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2498 2499 Adapter->e1000g_promisc = on; 2500 2501 rw_exit(&Adapter->chip_lock); 2502 2503 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2504 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2505 return (EIO); 2506 } 2507 2508 return (0); 2509 } 2510 2511 static boolean_t 2512 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2513 { 2514 struct e1000g *Adapter = (struct e1000g *)arg; 2515 struct e1000_hw *hw = &Adapter->shared; 2516 2517 switch (cap) { 2518 case MAC_CAPAB_HCKSUM: { 2519 uint32_t *txflags = cap_data; 2520 /* 2521 * Checksum on/off selection via global parameters. 2522 * 2523 * If the chip is flagged as not capable of (correctly) 2524 * handling checksumming, we don't enable it on either 2525 * Rx or Tx side. Otherwise, we take this chip's settings 2526 * from the patchable global defaults. 2527 * 2528 * We advertise our capabilities only if TX offload is 2529 * enabled. On receive, the stack will accept checksummed 2530 * packets anyway, even if we haven't said we can deliver 2531 * them. 2532 */ 2533 switch (hw->mac.type) { 2534 case e1000_82540: 2535 case e1000_82544: 2536 case e1000_82545: 2537 case e1000_82545_rev_3: 2538 case e1000_82546: 2539 case e1000_82546_rev_3: 2540 case e1000_82571: 2541 case e1000_82572: 2542 case e1000_82573: 2543 case e1000_80003es2lan: 2544 if (Adapter->tx_hcksum_enabled) 2545 *txflags = HCKSUM_IPHDRCKSUM | 2546 HCKSUM_INET_PARTIAL; 2547 else 2548 return (B_FALSE); 2549 break; 2550 2551 /* 2552 * For the following Intel PRO/1000 chipsets, we have not 2553 * tested the hardware checksum offload capability, so we 2554 * disable the capability for them. 2555 * e1000_82542, 2556 * e1000_82543, 2557 * e1000_82541, 2558 * e1000_82541_rev_2, 2559 * e1000_82547, 2560 * e1000_82547_rev_2, 2561 */ 2562 default: 2563 return (B_FALSE); 2564 } 2565 2566 break; 2567 } 2568 case MAC_CAPAB_POLL: 2569 /* 2570 * There's nothing for us to fill in, simply returning 2571 * B_TRUE stating that we support polling is sufficient. 2572 */ 2573 break; 2574 2575 case MAC_CAPAB_MULTIADDRESS: { 2576 multiaddress_capab_t *mmacp = cap_data; 2577 2578 /* 2579 * The number of MAC addresses made available by 2580 * this capability is one less than the total as 2581 * the primary address in slot 0 is counted in 2582 * the total. 2583 */ 2584 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2585 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2586 /* No multiple factory addresses, set mma_flag to 0 */ 2587 mmacp->maddr_flag = 0; 2588 mmacp->maddr_handle = Adapter; 2589 mmacp->maddr_add = e1000g_m_unicst_add; 2590 mmacp->maddr_remove = e1000g_m_unicst_remove; 2591 mmacp->maddr_modify = e1000g_m_unicst_modify; 2592 mmacp->maddr_get = e1000g_m_unicst_get; 2593 mmacp->maddr_reserve = NULL; 2594 break; 2595 } 2596 default: 2597 return (B_FALSE); 2598 } 2599 return (B_TRUE); 2600 } 2601 2602 static boolean_t 2603 e1000g_param_locked(mac_prop_id_t pr_num) 2604 { 2605 /* 2606 * All en_* parameters are locked (read-only) while 2607 * the device is in any sort of loopback mode ... 2608 */ 2609 switch (pr_num) { 2610 case DLD_PROP_EN_1000FDX_CAP: 2611 case DLD_PROP_EN_1000HDX_CAP: 2612 case DLD_PROP_EN_100FDX_CAP: 2613 case DLD_PROP_EN_100HDX_CAP: 2614 case DLD_PROP_EN_10FDX_CAP: 2615 case DLD_PROP_EN_10HDX_CAP: 2616 case DLD_PROP_AUTONEG: 2617 case DLD_PROP_FLOWCTRL: 2618 return (B_TRUE); 2619 } 2620 return (B_FALSE); 2621 } 2622 2623 /* 2624 * callback function for set/get of properties 2625 */ 2626 static int 2627 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2628 uint_t pr_valsize, const void *pr_val) 2629 { 2630 struct e1000g *Adapter = arg; 2631 struct e1000_mac_info *mac = &Adapter->shared.mac; 2632 struct e1000_phy_info *phy = &Adapter->shared.phy; 2633 e1000g_tx_ring_t *tx_ring; 2634 int err = 0; 2635 link_flowctrl_t fc; 2636 uint32_t cur_mtu, new_mtu; 2637 uint64_t tmp = 0; 2638 2639 rw_enter(&Adapter->chip_lock, RW_WRITER); 2640 if (Adapter->loopback_mode != E1000G_LB_NONE && 2641 e1000g_param_locked(pr_num)) { 2642 /* 2643 * All en_* parameters are locked (read-only) 2644 * while the device is in any sort of loopback mode. 2645 */ 2646 rw_exit(&Adapter->chip_lock); 2647 return (EBUSY); 2648 } 2649 2650 switch (pr_num) { 2651 case DLD_PROP_EN_1000FDX_CAP: 2652 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 2653 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 2654 goto reset; 2655 case DLD_PROP_EN_1000HDX_CAP: 2656 Adapter->param_en_1000hdx = *(uint8_t *)pr_val; 2657 Adapter->param_adv_1000hdx = *(uint8_t *)pr_val; 2658 goto reset; 2659 case DLD_PROP_EN_100FDX_CAP: 2660 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 2661 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 2662 goto reset; 2663 case DLD_PROP_EN_100HDX_CAP: 2664 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 2665 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 2666 goto reset; 2667 case DLD_PROP_EN_10FDX_CAP: 2668 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 2669 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 2670 goto reset; 2671 case DLD_PROP_EN_10HDX_CAP: 2672 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 2673 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 2674 goto reset; 2675 case DLD_PROP_AUTONEG: 2676 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 2677 goto reset; 2678 case DLD_PROP_FLOWCTRL: 2679 mac->fc_send_xon = B_TRUE; 2680 bcopy(pr_val, &fc, sizeof (fc)); 2681 2682 switch (fc) { 2683 default: 2684 err = EINVAL; 2685 break; 2686 case LINK_FLOWCTRL_NONE: 2687 mac->fc = e1000_fc_none; 2688 break; 2689 case LINK_FLOWCTRL_RX: 2690 mac->fc = e1000_fc_rx_pause; 2691 break; 2692 case LINK_FLOWCTRL_TX: 2693 mac->fc = e1000_fc_tx_pause; 2694 break; 2695 case LINK_FLOWCTRL_BI: 2696 mac->fc = e1000_fc_full; 2697 break; 2698 } 2699 reset: 2700 if (err == 0) { 2701 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 2702 err = EINVAL; 2703 } 2704 break; 2705 case DLD_PROP_ADV_1000FDX_CAP: 2706 case DLD_PROP_ADV_1000HDX_CAP: 2707 case DLD_PROP_ADV_100FDX_CAP: 2708 case DLD_PROP_ADV_100HDX_CAP: 2709 case DLD_PROP_ADV_10FDX_CAP: 2710 case DLD_PROP_ADV_10HDX_CAP: 2711 case DLD_PROP_STATUS: 2712 case DLD_PROP_SPEED: 2713 case DLD_PROP_DUPLEX: 2714 err = ENOTSUP; /* read-only prop. Can't set this. */ 2715 break; 2716 case DLD_PROP_MTU: 2717 cur_mtu = Adapter->default_mtu; 2718 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 2719 if (new_mtu == cur_mtu) { 2720 err = 0; 2721 break; 2722 } 2723 2724 tmp = new_mtu + sizeof (struct ether_vlan_header) + 2725 ETHERFCSL; 2726 if ((tmp < DEFAULT_FRAME_SIZE) || 2727 (tmp > MAXIMUM_FRAME_SIZE)) { 2728 err = EINVAL; 2729 break; 2730 } 2731 2732 /* ich8 doed not support jumbo frames */ 2733 if ((mac->type == e1000_ich8lan) && 2734 (tmp > DEFAULT_FRAME_SIZE)) { 2735 err = EINVAL; 2736 break; 2737 } 2738 /* ich9 does not do jumbo frames on one phy type */ 2739 if ((mac->type == e1000_ich9lan) && 2740 (phy->type == e1000_phy_ife) && 2741 (tmp > DEFAULT_FRAME_SIZE)) { 2742 err = EINVAL; 2743 break; 2744 } 2745 if (Adapter->chip_state != E1000G_STOP) { 2746 err = EBUSY; 2747 break; 2748 } 2749 2750 err = mac_maxsdu_update(Adapter->mh, new_mtu); 2751 if (err == 0) { 2752 mac->max_frame_size = tmp; 2753 Adapter->default_mtu = new_mtu; 2754 e1000g_set_bufsize(Adapter); 2755 tx_ring = Adapter->tx_ring; 2756 tx_ring->frags_limit = (mac->max_frame_size / 2757 Adapter->tx_bcopy_thresh) + 2; 2758 if (tx_ring->frags_limit > 2759 (MAX_TX_DESC_PER_PACKET >> 1)) 2760 tx_ring->frags_limit = 2761 (MAX_TX_DESC_PER_PACKET >> 1); 2762 } 2763 break; 2764 case DLD_PROP_PRIVATE: 2765 err = e1000g_set_priv_prop(Adapter, pr_name, 2766 pr_valsize, pr_val); 2767 break; 2768 default: 2769 err = ENOTSUP; 2770 break; 2771 } 2772 rw_exit(&Adapter->chip_lock); 2773 return (err); 2774 } 2775 2776 static int 2777 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 2778 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 2779 { 2780 struct e1000g *Adapter = arg; 2781 struct e1000_mac_info *mac = &Adapter->shared.mac; 2782 int err = 0; 2783 link_flowctrl_t fc; 2784 uint64_t tmp = 0; 2785 2786 if (pr_valsize == 0) 2787 return (EINVAL); 2788 2789 bzero(pr_val, pr_valsize); 2790 if ((pr_flags & DLD_DEFAULT) && (pr_num != DLD_PROP_PRIVATE)) { 2791 return (e1000g_get_def_val(Adapter, pr_num, 2792 pr_valsize, pr_val)); 2793 } 2794 2795 switch (pr_num) { 2796 case DLD_PROP_DUPLEX: 2797 if (pr_valsize >= sizeof (link_duplex_t)) { 2798 bcopy(&Adapter->link_duplex, pr_val, 2799 sizeof (link_duplex_t)); 2800 } else 2801 err = EINVAL; 2802 break; 2803 case DLD_PROP_SPEED: 2804 if (pr_valsize >= sizeof (uint64_t)) { 2805 tmp = Adapter->link_speed * 1000000ull; 2806 bcopy(&tmp, pr_val, sizeof (tmp)); 2807 } else 2808 err = EINVAL; 2809 break; 2810 case DLD_PROP_AUTONEG: 2811 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 2812 break; 2813 case DLD_PROP_FLOWCTRL: 2814 if (pr_valsize >= sizeof (link_flowctrl_t)) { 2815 switch (mac->fc) { 2816 case e1000_fc_none: 2817 fc = LINK_FLOWCTRL_NONE; 2818 break; 2819 case e1000_fc_rx_pause: 2820 fc = LINK_FLOWCTRL_RX; 2821 break; 2822 case e1000_fc_tx_pause: 2823 fc = LINK_FLOWCTRL_TX; 2824 break; 2825 case e1000_fc_full: 2826 fc = LINK_FLOWCTRL_BI; 2827 break; 2828 } 2829 bcopy(&fc, pr_val, sizeof (fc)); 2830 } else 2831 err = EINVAL; 2832 break; 2833 case DLD_PROP_ADV_1000FDX_CAP: 2834 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 2835 break; 2836 case DLD_PROP_EN_1000FDX_CAP: 2837 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 2838 break; 2839 case DLD_PROP_ADV_1000HDX_CAP: 2840 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 2841 break; 2842 case DLD_PROP_EN_1000HDX_CAP: 2843 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 2844 break; 2845 case DLD_PROP_ADV_100FDX_CAP: 2846 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 2847 break; 2848 case DLD_PROP_EN_100FDX_CAP: 2849 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 2850 break; 2851 case DLD_PROP_ADV_100HDX_CAP: 2852 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 2853 break; 2854 case DLD_PROP_EN_100HDX_CAP: 2855 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 2856 break; 2857 case DLD_PROP_ADV_10FDX_CAP: 2858 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 2859 break; 2860 case DLD_PROP_EN_10FDX_CAP: 2861 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 2862 break; 2863 case DLD_PROP_ADV_10HDX_CAP: 2864 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 2865 break; 2866 case DLD_PROP_EN_10HDX_CAP: 2867 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 2868 break; 2869 case DLD_PROP_ADV_100T4_CAP: 2870 case DLD_PROP_EN_100T4_CAP: 2871 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 2872 break; 2873 case DLD_PROP_PRIVATE: 2874 err = e1000g_get_priv_prop(Adapter, pr_name, 2875 pr_flags, pr_valsize, pr_val); 2876 break; 2877 default: 2878 err = ENOTSUP; 2879 break; 2880 } 2881 return (err); 2882 } 2883 2884 /* ARGUSED */ 2885 static int 2886 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 2887 uint_t pr_valsize, const void *pr_val) 2888 { 2889 int err = 0; 2890 long result; 2891 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2892 struct e1000_hw *hw = &Adapter->shared; 2893 2894 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 2895 if (pr_val == NULL) { 2896 err = EINVAL; 2897 return (err); 2898 } 2899 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2900 if (result < MIN_TX_BCOPY_THRESHOLD || 2901 result > MAX_TX_BCOPY_THRESHOLD) 2902 err = EINVAL; 2903 else { 2904 Adapter->tx_bcopy_thresh = (uint32_t)result; 2905 tx_ring->frags_limit = (hw->mac.max_frame_size / 2906 Adapter->tx_bcopy_thresh) + 2; 2907 if (tx_ring->frags_limit > 2908 (MAX_TX_DESC_PER_PACKET >> 1)) 2909 tx_ring->frags_limit = 2910 (MAX_TX_DESC_PER_PACKET >> 1); 2911 } 2912 return (err); 2913 } 2914 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 2915 if (pr_val == NULL) { 2916 err = EINVAL; 2917 return (err); 2918 } 2919 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2920 if (result < 0 || result > 1) 2921 err = EINVAL; 2922 else { 2923 Adapter->tx_intr_enable = (result == 1) ? 2924 B_TRUE: B_FALSE; 2925 if (Adapter->tx_intr_enable) 2926 e1000g_mask_tx_interrupt(Adapter); 2927 else 2928 e1000g_clear_tx_interrupt(Adapter); 2929 if (e1000g_check_acc_handle( 2930 Adapter->osdep.reg_handle) != DDI_FM_OK) 2931 ddi_fm_service_impact(Adapter->dip, 2932 DDI_SERVICE_DEGRADED); 2933 } 2934 return (err); 2935 } 2936 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 2937 if (pr_val == NULL) { 2938 err = EINVAL; 2939 return (err); 2940 } 2941 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2942 if (result < MIN_TX_INTR_DELAY || 2943 result > MAX_TX_INTR_DELAY) 2944 err = EINVAL; 2945 else { 2946 Adapter->tx_intr_delay = (uint32_t)result; 2947 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 2948 if (e1000g_check_acc_handle( 2949 Adapter->osdep.reg_handle) != DDI_FM_OK) 2950 ddi_fm_service_impact(Adapter->dip, 2951 DDI_SERVICE_DEGRADED); 2952 } 2953 return (err); 2954 } 2955 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 2956 if (pr_val == NULL) { 2957 err = EINVAL; 2958 return (err); 2959 } 2960 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2961 if (result < MIN_TX_INTR_ABS_DELAY || 2962 result > MAX_TX_INTR_ABS_DELAY) 2963 err = EINVAL; 2964 else { 2965 Adapter->tx_intr_abs_delay = (uint32_t)result; 2966 E1000_WRITE_REG(hw, E1000_TADV, 2967 Adapter->tx_intr_abs_delay); 2968 if (e1000g_check_acc_handle( 2969 Adapter->osdep.reg_handle) != DDI_FM_OK) 2970 ddi_fm_service_impact(Adapter->dip, 2971 DDI_SERVICE_DEGRADED); 2972 } 2973 return (err); 2974 } 2975 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 2976 if (pr_val == NULL) { 2977 err = EINVAL; 2978 return (err); 2979 } 2980 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2981 if (result < MIN_RX_BCOPY_THRESHOLD || 2982 result > MAX_RX_BCOPY_THRESHOLD) 2983 err = EINVAL; 2984 else 2985 Adapter->rx_bcopy_thresh = (uint32_t)result; 2986 return (err); 2987 } 2988 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 2989 if (pr_val == NULL) { 2990 err = EINVAL; 2991 return (err); 2992 } 2993 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 2994 if (result < MIN_RX_LIMIT_ON_INTR || 2995 result > MAX_RX_LIMIT_ON_INTR) 2996 err = EINVAL; 2997 else 2998 Adapter->rx_limit_onintr = (uint32_t)result; 2999 return (err); 3000 } 3001 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3002 if (pr_val == NULL) { 3003 err = EINVAL; 3004 return (err); 3005 } 3006 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3007 if (result < MIN_RX_INTR_DELAY || 3008 result > MAX_RX_INTR_DELAY) 3009 err = EINVAL; 3010 else { 3011 Adapter->rx_intr_delay = (uint32_t)result; 3012 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3013 if (e1000g_check_acc_handle( 3014 Adapter->osdep.reg_handle) != DDI_FM_OK) 3015 ddi_fm_service_impact(Adapter->dip, 3016 DDI_SERVICE_DEGRADED); 3017 } 3018 return (err); 3019 } 3020 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3021 if (pr_val == NULL) { 3022 err = EINVAL; 3023 return (err); 3024 } 3025 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3026 if (result < MIN_RX_INTR_ABS_DELAY || 3027 result > MAX_RX_INTR_ABS_DELAY) 3028 err = EINVAL; 3029 else { 3030 Adapter->rx_intr_abs_delay = (uint32_t)result; 3031 E1000_WRITE_REG(hw, E1000_RADV, 3032 Adapter->rx_intr_abs_delay); 3033 if (e1000g_check_acc_handle( 3034 Adapter->osdep.reg_handle) != DDI_FM_OK) 3035 ddi_fm_service_impact(Adapter->dip, 3036 DDI_SERVICE_DEGRADED); 3037 } 3038 return (err); 3039 } 3040 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3041 if (pr_val == NULL) { 3042 err = EINVAL; 3043 return (err); 3044 } 3045 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3046 if (result < MIN_INTR_THROTTLING || 3047 result > MAX_INTR_THROTTLING) 3048 err = EINVAL; 3049 else { 3050 if (hw->mac.type >= e1000_82540) { 3051 Adapter->intr_throttling_rate = 3052 (uint32_t)result; 3053 E1000_WRITE_REG(hw, E1000_ITR, 3054 Adapter->intr_throttling_rate); 3055 if (e1000g_check_acc_handle( 3056 Adapter->osdep.reg_handle) != DDI_FM_OK) 3057 ddi_fm_service_impact(Adapter->dip, 3058 DDI_SERVICE_DEGRADED); 3059 } else 3060 err = EINVAL; 3061 } 3062 return (err); 3063 } 3064 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3065 if (pr_val == NULL) { 3066 err = EINVAL; 3067 return (err); 3068 } 3069 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3070 if (result < 0 || result > 1) 3071 err = EINVAL; 3072 else { 3073 if (hw->mac.type >= e1000_82540) { 3074 Adapter->intr_adaptive = (result == 1) ? 3075 B_TRUE : B_FALSE; 3076 } else { 3077 err = EINVAL; 3078 } 3079 } 3080 return (err); 3081 } 3082 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3083 if (pr_val == NULL) { 3084 err = EINVAL; 3085 return (err); 3086 } 3087 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3088 if (result < MIN_TX_RECYCLE_THRESHOLD || 3089 result > MAX_TX_RECYCLE_THRESHOLD) 3090 err = EINVAL; 3091 else 3092 Adapter->tx_recycle_thresh = (uint32_t)result; 3093 return (err); 3094 } 3095 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3096 if (pr_val == NULL) { 3097 err = EINVAL; 3098 return (err); 3099 } 3100 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3101 if (result < MIN_TX_RECYCLE_NUM || 3102 result > MAX_TX_RECYCLE_NUM) 3103 err = EINVAL; 3104 else 3105 Adapter->tx_recycle_num = (uint32_t)result; 3106 return (err); 3107 } 3108 return (ENOTSUP); 3109 } 3110 3111 static int 3112 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3113 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 3114 { 3115 char valstr[MAXNAMELEN]; 3116 int err = ENOTSUP; 3117 uint_t strsize; 3118 boolean_t is_default = (pr_flags & DLD_DEFAULT); 3119 int value; 3120 3121 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3122 if (is_default) 3123 goto done; 3124 value = Adapter->param_adv_pause; 3125 err = 0; 3126 goto done; 3127 } 3128 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3129 if (is_default) 3130 goto done; 3131 value = Adapter->param_adv_asym_pause; 3132 err = 0; 3133 goto done; 3134 } 3135 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3136 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3137 Adapter->tx_bcopy_thresh); 3138 err = 0; 3139 goto done; 3140 } 3141 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3142 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3143 Adapter->tx_intr_enable); 3144 err = 0; 3145 goto done; 3146 } 3147 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3148 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3149 Adapter->tx_intr_delay); 3150 err = 0; 3151 goto done; 3152 } 3153 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3154 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3155 Adapter->tx_intr_abs_delay); 3156 err = 0; 3157 goto done; 3158 } 3159 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3160 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3161 Adapter->rx_bcopy_thresh); 3162 err = 0; 3163 goto done; 3164 } 3165 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3166 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3167 Adapter->rx_limit_onintr); 3168 err = 0; 3169 goto done; 3170 } 3171 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3172 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3173 Adapter->rx_intr_delay); 3174 err = 0; 3175 goto done; 3176 } 3177 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3178 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3179 Adapter->rx_intr_abs_delay); 3180 err = 0; 3181 goto done; 3182 } 3183 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3184 value = (is_default ? DEFAULT_INTR_THROTTLING : 3185 Adapter->intr_throttling_rate); 3186 err = 0; 3187 goto done; 3188 } 3189 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3190 value = (is_default ? 1 : Adapter->intr_adaptive); 3191 err = 0; 3192 goto done; 3193 } 3194 if (strcmp(pr_name, "_tx_recycle_thresh") == 0) { 3195 value = (is_default ? DEFAULT_TX_RECYCLE_THRESHOLD : 3196 Adapter->tx_recycle_thresh); 3197 err = 0; 3198 goto done; 3199 } 3200 if (strcmp(pr_name, "_tx_recycle_num") == 0) { 3201 value = (is_default ? DEFAULT_TX_RECYCLE_NUM : 3202 Adapter->tx_recycle_num); 3203 err = 0; 3204 goto done; 3205 } 3206 done: 3207 if (err == 0) { 3208 (void) snprintf(pr_val, pr_valsize, "%d", value); 3209 } 3210 return (err); 3211 } 3212 3213 /* 3214 * e1000g_get_conf - get configurations set in e1000g.conf 3215 * This routine gets user-configured values out of the configuration 3216 * file e1000g.conf. 3217 * 3218 * For each configurable value, there is a minimum, a maximum, and a 3219 * default. 3220 * If user does not configure a value, use the default. 3221 * If user configures below the minimum, use the minumum. 3222 * If user configures above the maximum, use the maxumum. 3223 */ 3224 static void 3225 e1000g_get_conf(struct e1000g *Adapter) 3226 { 3227 struct e1000_hw *hw = &Adapter->shared; 3228 boolean_t tbi_compatibility = B_FALSE; 3229 3230 /* 3231 * get each configurable property from e1000g.conf 3232 */ 3233 3234 /* 3235 * NumTxDescriptors 3236 */ 3237 Adapter->tx_desc_num = 3238 e1000g_get_prop(Adapter, "NumTxDescriptors", 3239 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3240 DEFAULT_NUM_TX_DESCRIPTOR); 3241 3242 /* 3243 * NumRxDescriptors 3244 */ 3245 Adapter->rx_desc_num = 3246 e1000g_get_prop(Adapter, "NumRxDescriptors", 3247 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3248 DEFAULT_NUM_RX_DESCRIPTOR); 3249 3250 /* 3251 * NumRxFreeList 3252 */ 3253 Adapter->rx_freelist_num = 3254 e1000g_get_prop(Adapter, "NumRxFreeList", 3255 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3256 DEFAULT_NUM_RX_FREELIST); 3257 3258 /* 3259 * NumTxPacketList 3260 */ 3261 Adapter->tx_freelist_num = 3262 e1000g_get_prop(Adapter, "NumTxPacketList", 3263 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3264 DEFAULT_NUM_TX_FREELIST); 3265 3266 /* 3267 * FlowControl 3268 */ 3269 hw->mac.fc_send_xon = B_TRUE; 3270 hw->mac.fc = 3271 e1000g_get_prop(Adapter, "FlowControl", 3272 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL); 3273 /* 4 is the setting that says "let the eeprom decide" */ 3274 if (hw->mac.fc == 4) 3275 hw->mac.fc = e1000_fc_default; 3276 3277 /* 3278 * Max Num Receive Packets on Interrupt 3279 */ 3280 Adapter->rx_limit_onintr = 3281 e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3282 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3283 DEFAULT_RX_LIMIT_ON_INTR); 3284 3285 /* 3286 * PHY master slave setting 3287 */ 3288 hw->phy.ms_type = 3289 e1000g_get_prop(Adapter, "SetMasterSlave", 3290 e1000_ms_hw_default, e1000_ms_auto, 3291 e1000_ms_hw_default); 3292 3293 /* 3294 * Parameter which controls TBI mode workaround, which is only 3295 * needed on certain switches such as Cisco 6500/Foundry 3296 */ 3297 tbi_compatibility = 3298 e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3299 0, 1, DEFAULT_TBI_COMPAT_ENABLE); 3300 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3301 3302 /* 3303 * MSI Enable 3304 */ 3305 Adapter->msi_enabled = 3306 e1000g_get_prop(Adapter, "MSIEnable", 3307 0, 1, DEFAULT_MSI_ENABLE); 3308 3309 /* 3310 * Interrupt Throttling Rate 3311 */ 3312 Adapter->intr_throttling_rate = 3313 e1000g_get_prop(Adapter, "intr_throttling_rate", 3314 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3315 DEFAULT_INTR_THROTTLING); 3316 3317 /* 3318 * Adaptive Interrupt Blanking Enable/Disable 3319 * It is enabled by default 3320 */ 3321 Adapter->intr_adaptive = 3322 (e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 3323 B_TRUE : B_FALSE; 3324 3325 /* 3326 * Tx recycle threshold 3327 */ 3328 Adapter->tx_recycle_thresh = 3329 e1000g_get_prop(Adapter, "tx_recycle_thresh", 3330 MIN_TX_RECYCLE_THRESHOLD, MAX_TX_RECYCLE_THRESHOLD, 3331 DEFAULT_TX_RECYCLE_THRESHOLD); 3332 3333 /* 3334 * Tx recycle descriptor number 3335 */ 3336 Adapter->tx_recycle_num = 3337 e1000g_get_prop(Adapter, "tx_recycle_num", 3338 MIN_TX_RECYCLE_NUM, MAX_TX_RECYCLE_NUM, 3339 DEFAULT_TX_RECYCLE_NUM); 3340 3341 /* 3342 * Hardware checksum enable/disable parameter 3343 */ 3344 Adapter->tx_hcksum_enabled = 3345 e1000g_get_prop(Adapter, "tx_hcksum_enabled", 3346 0, 1, DEFAULT_TX_HCKSUM_ENABLE); 3347 3348 } 3349 3350 /* 3351 * e1000g_get_prop - routine to read properties 3352 * 3353 * Get a user-configure property value out of the configuration 3354 * file e1000g.conf. 3355 * 3356 * Caller provides name of the property, a default value, a minimum 3357 * value, and a maximum value. 3358 * 3359 * Return configured value of the property, with default, minimum and 3360 * maximum properly applied. 3361 */ 3362 static int 3363 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3364 char *propname, /* name of the property */ 3365 int minval, /* minimum acceptable value */ 3366 int maxval, /* maximim acceptable value */ 3367 int defval) /* default value */ 3368 { 3369 int propval; /* value returned for requested property */ 3370 int *props; /* point to array of properties returned */ 3371 uint_t nprops; /* number of property value returned */ 3372 3373 /* 3374 * get the array of properties from the config file 3375 */ 3376 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3377 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3378 /* got some properties, test if we got enough */ 3379 if (Adapter->instance < nprops) { 3380 propval = props[Adapter->instance]; 3381 } else { 3382 /* not enough properties configured */ 3383 propval = defval; 3384 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3385 "Not Enough %s values found in e1000g.conf" 3386 " - set to %d\n", 3387 propname, propval); 3388 } 3389 3390 /* free memory allocated for properties */ 3391 ddi_prop_free(props); 3392 3393 } else { 3394 propval = defval; 3395 } 3396 3397 /* 3398 * enforce limits 3399 */ 3400 if (propval > maxval) { 3401 propval = maxval; 3402 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3403 "Too High %s value in e1000g.conf - set to %d\n", 3404 propname, propval); 3405 } 3406 3407 if (propval < minval) { 3408 propval = minval; 3409 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3410 "Too Low %s value in e1000g.conf - set to %d\n", 3411 propname, propval); 3412 } 3413 3414 return (propval); 3415 } 3416 3417 static boolean_t 3418 e1000g_link_check(struct e1000g *Adapter) 3419 { 3420 uint16_t speed, duplex, phydata; 3421 boolean_t link_changed = B_FALSE; 3422 struct e1000_hw *hw; 3423 uint32_t reg_tarc; 3424 3425 hw = &Adapter->shared; 3426 3427 if (e1000g_link_up(Adapter)) { 3428 /* 3429 * The Link is up, check whether it was marked as down earlier 3430 */ 3431 if (Adapter->link_state != LINK_STATE_UP) { 3432 e1000_get_speed_and_duplex(hw, &speed, &duplex); 3433 Adapter->link_speed = speed; 3434 Adapter->link_duplex = duplex; 3435 Adapter->link_state = LINK_STATE_UP; 3436 link_changed = B_TRUE; 3437 3438 Adapter->tx_link_down_timeout = 0; 3439 3440 if ((hw->mac.type == e1000_82571) || 3441 (hw->mac.type == e1000_82572)) { 3442 reg_tarc = E1000_READ_REG(hw, E1000_TARC0); 3443 if (speed == SPEED_1000) 3444 reg_tarc |= (1 << 21); 3445 else 3446 reg_tarc &= ~(1 << 21); 3447 E1000_WRITE_REG(hw, E1000_TARC0, reg_tarc); 3448 } 3449 } 3450 Adapter->smartspeed = 0; 3451 } else { 3452 if (Adapter->link_state != LINK_STATE_DOWN) { 3453 Adapter->link_speed = 0; 3454 Adapter->link_duplex = 0; 3455 Adapter->link_state = LINK_STATE_DOWN; 3456 link_changed = B_TRUE; 3457 3458 /* 3459 * SmartSpeed workaround for Tabor/TanaX, When the 3460 * driver loses link disable auto master/slave 3461 * resolution. 3462 */ 3463 if (hw->phy.type == e1000_phy_igp) { 3464 e1000_read_phy_reg(hw, 3465 PHY_1000T_CTRL, &phydata); 3466 phydata |= CR_1000T_MS_ENABLE; 3467 e1000_write_phy_reg(hw, 3468 PHY_1000T_CTRL, phydata); 3469 } 3470 } else { 3471 e1000g_smartspeed(Adapter); 3472 } 3473 3474 if (Adapter->chip_state == E1000G_START) { 3475 if (Adapter->tx_link_down_timeout < 3476 MAX_TX_LINK_DOWN_TIMEOUT) { 3477 Adapter->tx_link_down_timeout++; 3478 } else if (Adapter->tx_link_down_timeout == 3479 MAX_TX_LINK_DOWN_TIMEOUT) { 3480 e1000g_tx_clean(Adapter); 3481 Adapter->tx_link_down_timeout++; 3482 } 3483 } 3484 } 3485 3486 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3487 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3488 3489 return (link_changed); 3490 } 3491 3492 /* 3493 * e1000g_reset_link - Using the link properties to setup the link 3494 */ 3495 int 3496 e1000g_reset_link(struct e1000g *Adapter) 3497 { 3498 struct e1000_mac_info *mac; 3499 struct e1000_phy_info *phy; 3500 boolean_t invalid; 3501 3502 mac = &Adapter->shared.mac; 3503 phy = &Adapter->shared.phy; 3504 invalid = B_FALSE; 3505 3506 if (Adapter->param_adv_autoneg == 1) { 3507 mac->autoneg = B_TRUE; 3508 phy->autoneg_advertised = 0; 3509 3510 /* 3511 * 1000hdx is not supported for autonegotiation 3512 */ 3513 if (Adapter->param_adv_1000fdx == 1) 3514 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 3515 3516 if (Adapter->param_adv_100fdx == 1) 3517 phy->autoneg_advertised |= ADVERTISE_100_FULL; 3518 3519 if (Adapter->param_adv_100hdx == 1) 3520 phy->autoneg_advertised |= ADVERTISE_100_HALF; 3521 3522 if (Adapter->param_adv_10fdx == 1) 3523 phy->autoneg_advertised |= ADVERTISE_10_FULL; 3524 3525 if (Adapter->param_adv_10hdx == 1) 3526 phy->autoneg_advertised |= ADVERTISE_10_HALF; 3527 3528 if (phy->autoneg_advertised == 0) 3529 invalid = B_TRUE; 3530 } else { 3531 mac->autoneg = B_FALSE; 3532 3533 /* 3534 * 1000fdx and 1000hdx are not supported for forced link 3535 */ 3536 if (Adapter->param_adv_100fdx == 1) 3537 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3538 else if (Adapter->param_adv_100hdx == 1) 3539 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3540 else if (Adapter->param_adv_10fdx == 1) 3541 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3542 else if (Adapter->param_adv_10hdx == 1) 3543 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3544 else 3545 invalid = B_TRUE; 3546 3547 } 3548 3549 if (invalid) { 3550 e1000g_log(Adapter, CE_WARN, 3551 "Invalid link sets. Setup link to" 3552 "support autonegotiation with all link capabilities."); 3553 mac->autoneg = B_TRUE; 3554 phy->autoneg_advertised = ADVERTISE_1000_FULL | 3555 ADVERTISE_100_FULL | ADVERTISE_100_HALF | 3556 ADVERTISE_10_FULL | ADVERTISE_10_HALF; 3557 } 3558 3559 return (e1000_setup_link(&Adapter->shared)); 3560 } 3561 3562 static void 3563 e1000g_local_timer(void *ws) 3564 { 3565 struct e1000g *Adapter = (struct e1000g *)ws; 3566 struct e1000_hw *hw; 3567 e1000g_ether_addr_t ether_addr; 3568 boolean_t link_changed; 3569 3570 hw = &Adapter->shared; 3571 3572 if (Adapter->chip_state == E1000G_ERROR) { 3573 Adapter->reset_count++; 3574 if (e1000g_global_reset(Adapter)) 3575 ddi_fm_service_impact(Adapter->dip, 3576 DDI_SERVICE_RESTORED); 3577 else 3578 ddi_fm_service_impact(Adapter->dip, 3579 DDI_SERVICE_LOST); 3580 return; 3581 } 3582 3583 if (e1000g_stall_check(Adapter)) { 3584 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 3585 "Tx stall detected. Activate automatic recovery.\n"); 3586 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 3587 Adapter->reset_count++; 3588 if (e1000g_reset(Adapter)) 3589 ddi_fm_service_impact(Adapter->dip, 3590 DDI_SERVICE_RESTORED); 3591 else 3592 ddi_fm_service_impact(Adapter->dip, 3593 DDI_SERVICE_LOST); 3594 return; 3595 } 3596 3597 link_changed = B_FALSE; 3598 rw_enter(&Adapter->chip_lock, RW_READER); 3599 if (Adapter->link_complete) 3600 link_changed = e1000g_link_check(Adapter); 3601 rw_exit(&Adapter->chip_lock); 3602 3603 if (link_changed) { 3604 /* 3605 * Workaround for esb2. Data stuck in fifo on a link 3606 * down event. Reset the adapter to recover it. 3607 */ 3608 if ((Adapter->link_state == LINK_STATE_DOWN) && 3609 (hw->mac.type == e1000_80003es2lan)) 3610 (void) e1000g_reset(Adapter); 3611 3612 mac_link_update(Adapter->mh, Adapter->link_state); 3613 } 3614 3615 /* 3616 * With 82571 controllers, any locally administered address will 3617 * be overwritten when there is a reset on the other port. 3618 * Detect this circumstance and correct it. 3619 */ 3620 if ((hw->mac.type == e1000_82571) && 3621 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 3622 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 3623 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 3624 3625 ether_addr.reg.low = ntohl(ether_addr.reg.low); 3626 ether_addr.reg.high = ntohl(ether_addr.reg.high); 3627 3628 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 3629 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 3630 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 3631 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 3632 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 3633 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 3634 e1000_rar_set(hw, hw->mac.addr, 0); 3635 } 3636 } 3637 3638 /* 3639 * Long TTL workaround for 82541/82547 3640 */ 3641 e1000_igp_ttl_workaround_82547(hw); 3642 3643 /* 3644 * Check for Adaptive IFS settings If there are lots of collisions 3645 * change the value in steps... 3646 * These properties should only be set for 10/100 3647 */ 3648 if ((hw->media_type == e1000_media_type_copper) && 3649 ((Adapter->link_speed == SPEED_100) || 3650 (Adapter->link_speed == SPEED_10))) { 3651 e1000_update_adaptive(hw); 3652 } 3653 /* 3654 * Set Timer Interrupts 3655 */ 3656 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 3657 3658 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 3659 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 3660 3661 restart_watchdog_timer(Adapter); 3662 } 3663 3664 /* 3665 * The function e1000g_link_timer() is called when the timer for link setup 3666 * is expired, which indicates the completion of the link setup. The link 3667 * state will not be updated until the link setup is completed. And the 3668 * link state will not be sent to the upper layer through mac_link_update() 3669 * in this function. It will be updated in the local timer routine or the 3670 * interrupt service routine after the interface is started (plumbed). 3671 */ 3672 static void 3673 e1000g_link_timer(void *arg) 3674 { 3675 struct e1000g *Adapter = (struct e1000g *)arg; 3676 3677 mutex_enter(&Adapter->link_lock); 3678 Adapter->link_complete = B_TRUE; 3679 Adapter->link_tid = 0; 3680 mutex_exit(&Adapter->link_lock); 3681 } 3682 3683 /* 3684 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 3685 * 3686 * This function read the forced speed and duplex for 10/100 Mbps speeds 3687 * and also for 1000 Mbps speeds from the e1000g.conf file 3688 */ 3689 static void 3690 e1000g_force_speed_duplex(struct e1000g *Adapter) 3691 { 3692 int forced; 3693 struct e1000_mac_info *mac = &Adapter->shared.mac; 3694 struct e1000_phy_info *phy = &Adapter->shared.phy; 3695 3696 /* 3697 * get value out of config file 3698 */ 3699 forced = e1000g_get_prop(Adapter, "ForceSpeedDuplex", 3700 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 3701 3702 switch (forced) { 3703 case GDIAG_10_HALF: 3704 /* 3705 * Disable Auto Negotiation 3706 */ 3707 mac->autoneg = B_FALSE; 3708 mac->forced_speed_duplex = ADVERTISE_10_HALF; 3709 break; 3710 case GDIAG_10_FULL: 3711 /* 3712 * Disable Auto Negotiation 3713 */ 3714 mac->autoneg = B_FALSE; 3715 mac->forced_speed_duplex = ADVERTISE_10_FULL; 3716 break; 3717 case GDIAG_100_HALF: 3718 /* 3719 * Disable Auto Negotiation 3720 */ 3721 mac->autoneg = B_FALSE; 3722 mac->forced_speed_duplex = ADVERTISE_100_HALF; 3723 break; 3724 case GDIAG_100_FULL: 3725 /* 3726 * Disable Auto Negotiation 3727 */ 3728 mac->autoneg = B_FALSE; 3729 mac->forced_speed_duplex = ADVERTISE_100_FULL; 3730 break; 3731 case GDIAG_1000_FULL: 3732 /* 3733 * The gigabit spec requires autonegotiation. Therefore, 3734 * when the user wants to force the speed to 1000Mbps, we 3735 * enable AutoNeg, but only allow the harware to advertise 3736 * 1000Mbps. This is different from 10/100 operation, where 3737 * we are allowed to link without any negotiation. 3738 */ 3739 mac->autoneg = B_TRUE; 3740 phy->autoneg_advertised = ADVERTISE_1000_FULL; 3741 break; 3742 default: /* obey the setting of AutoNegAdvertised */ 3743 mac->autoneg = B_TRUE; 3744 phy->autoneg_advertised = 3745 (uint16_t)e1000g_get_prop(Adapter, "AutoNegAdvertised", 3746 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 3747 AUTONEG_ADVERTISE_SPEED_DEFAULT); 3748 break; 3749 } /* switch */ 3750 } 3751 3752 /* 3753 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 3754 * 3755 * This function reads MaxFrameSize from e1000g.conf 3756 */ 3757 static void 3758 e1000g_get_max_frame_size(struct e1000g *Adapter) 3759 { 3760 int max_frame; 3761 struct e1000_mac_info *mac = &Adapter->shared.mac; 3762 struct e1000_phy_info *phy = &Adapter->shared.phy; 3763 3764 /* 3765 * get value out of config file 3766 */ 3767 max_frame = e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0); 3768 3769 switch (max_frame) { 3770 case 0: 3771 Adapter->default_mtu = ETHERMTU; 3772 break; 3773 /* 3774 * To avoid excessive memory allocation for rx buffers, 3775 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 3776 */ 3777 case 1: 3778 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 3779 sizeof (struct ether_vlan_header) - ETHERFCSL - 3780 E1000G_IPALIGNPRESERVEROOM; 3781 break; 3782 case 2: 3783 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 3784 sizeof (struct ether_vlan_header) - ETHERFCSL - 3785 E1000G_IPALIGNPRESERVEROOM; 3786 break; 3787 case 3: 3788 if (mac->type >= e1000_82571) 3789 Adapter->default_mtu = MAXIMUM_MTU; 3790 else 3791 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 3792 sizeof (struct ether_vlan_header) - ETHERFCSL - 3793 E1000G_IPALIGNPRESERVEROOM; 3794 break; 3795 default: 3796 Adapter->default_mtu = ETHERMTU; 3797 break; 3798 } /* switch */ 3799 3800 mac->max_frame_size = Adapter->default_mtu + 3801 sizeof (struct ether_vlan_header) + ETHERFCSL; 3802 3803 /* ich8 does not do jumbo frames */ 3804 if (mac->type == e1000_ich8lan) { 3805 mac->max_frame_size = ETHERMAX; 3806 } 3807 3808 /* ich9 does not do jumbo frames on one phy type */ 3809 if ((mac->type == e1000_ich9lan) && 3810 (phy->type == e1000_phy_ife)) { 3811 mac->max_frame_size = ETHERMAX; 3812 } 3813 } 3814 3815 static void 3816 arm_watchdog_timer(struct e1000g *Adapter) 3817 { 3818 Adapter->watchdog_tid = 3819 timeout(e1000g_local_timer, 3820 (void *)Adapter, 1 * drv_usectohz(1000000)); 3821 } 3822 #pragma inline(arm_watchdog_timer) 3823 3824 static void 3825 enable_watchdog_timer(struct e1000g *Adapter) 3826 { 3827 mutex_enter(&Adapter->watchdog_lock); 3828 3829 if (!Adapter->watchdog_timer_enabled) { 3830 Adapter->watchdog_timer_enabled = B_TRUE; 3831 Adapter->watchdog_timer_started = B_TRUE; 3832 arm_watchdog_timer(Adapter); 3833 } 3834 3835 mutex_exit(&Adapter->watchdog_lock); 3836 } 3837 3838 static void 3839 disable_watchdog_timer(struct e1000g *Adapter) 3840 { 3841 timeout_id_t tid; 3842 3843 mutex_enter(&Adapter->watchdog_lock); 3844 3845 Adapter->watchdog_timer_enabled = B_FALSE; 3846 Adapter->watchdog_timer_started = B_FALSE; 3847 tid = Adapter->watchdog_tid; 3848 Adapter->watchdog_tid = 0; 3849 3850 mutex_exit(&Adapter->watchdog_lock); 3851 3852 if (tid != 0) 3853 (void) untimeout(tid); 3854 } 3855 3856 static void 3857 start_watchdog_timer(struct e1000g *Adapter) 3858 { 3859 mutex_enter(&Adapter->watchdog_lock); 3860 3861 if (Adapter->watchdog_timer_enabled) { 3862 if (!Adapter->watchdog_timer_started) { 3863 Adapter->watchdog_timer_started = B_TRUE; 3864 arm_watchdog_timer(Adapter); 3865 } 3866 } 3867 3868 mutex_exit(&Adapter->watchdog_lock); 3869 } 3870 3871 static void 3872 restart_watchdog_timer(struct e1000g *Adapter) 3873 { 3874 mutex_enter(&Adapter->watchdog_lock); 3875 3876 if (Adapter->watchdog_timer_started) 3877 arm_watchdog_timer(Adapter); 3878 3879 mutex_exit(&Adapter->watchdog_lock); 3880 } 3881 3882 static void 3883 stop_watchdog_timer(struct e1000g *Adapter) 3884 { 3885 timeout_id_t tid; 3886 3887 mutex_enter(&Adapter->watchdog_lock); 3888 3889 Adapter->watchdog_timer_started = B_FALSE; 3890 tid = Adapter->watchdog_tid; 3891 Adapter->watchdog_tid = 0; 3892 3893 mutex_exit(&Adapter->watchdog_lock); 3894 3895 if (tid != 0) 3896 (void) untimeout(tid); 3897 } 3898 3899 static void 3900 stop_link_timer(struct e1000g *Adapter) 3901 { 3902 timeout_id_t tid; 3903 3904 /* Disable the link timer */ 3905 mutex_enter(&Adapter->link_lock); 3906 3907 tid = Adapter->link_tid; 3908 Adapter->link_tid = 0; 3909 3910 mutex_exit(&Adapter->link_lock); 3911 3912 if (tid != 0) 3913 (void) untimeout(tid); 3914 } 3915 3916 static void 3917 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 3918 { 3919 timeout_id_t tid; 3920 3921 /* Disable the tx timer for 82547 chipset */ 3922 mutex_enter(&tx_ring->tx_lock); 3923 3924 tx_ring->timer_enable_82547 = B_FALSE; 3925 tid = tx_ring->timer_id_82547; 3926 tx_ring->timer_id_82547 = 0; 3927 3928 mutex_exit(&tx_ring->tx_lock); 3929 3930 if (tid != 0) 3931 (void) untimeout(tid); 3932 } 3933 3934 void 3935 e1000g_clear_interrupt(struct e1000g *Adapter) 3936 { 3937 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 3938 0xffffffff & ~E1000_IMS_RXSEQ); 3939 } 3940 3941 void 3942 e1000g_mask_interrupt(struct e1000g *Adapter) 3943 { 3944 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 3945 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 3946 3947 if (Adapter->tx_intr_enable) 3948 e1000g_mask_tx_interrupt(Adapter); 3949 } 3950 3951 void 3952 e1000g_clear_all_interrupts(struct e1000g *Adapter) 3953 { 3954 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 3955 } 3956 3957 void 3958 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 3959 { 3960 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 3961 } 3962 3963 void 3964 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 3965 { 3966 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 3967 } 3968 3969 static void 3970 e1000g_smartspeed(struct e1000g *Adapter) 3971 { 3972 struct e1000_hw *hw = &Adapter->shared; 3973 uint16_t phy_status; 3974 uint16_t phy_ctrl; 3975 3976 /* 3977 * If we're not T-or-T, or we're not autoneg'ing, or we're not 3978 * advertising 1000Full, we don't even use the workaround 3979 */ 3980 if ((hw->phy.type != e1000_phy_igp) || 3981 !hw->mac.autoneg || 3982 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 3983 return; 3984 3985 /* 3986 * True if this is the first call of this function or after every 3987 * 30 seconds of not having link 3988 */ 3989 if (Adapter->smartspeed == 0) { 3990 /* 3991 * If Master/Slave config fault is asserted twice, we 3992 * assume back-to-back 3993 */ 3994 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3995 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 3996 return; 3997 3998 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 3999 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4000 return; 4001 /* 4002 * We're assuming back-2-back because our status register 4003 * insists! there's a fault in the master/slave 4004 * relationship that was "negotiated" 4005 */ 4006 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4007 /* 4008 * Is the phy configured for manual configuration of 4009 * master/slave? 4010 */ 4011 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4012 /* 4013 * Yes. Then disable manual configuration (enable 4014 * auto configuration) of master/slave 4015 */ 4016 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4017 e1000_write_phy_reg(hw, 4018 PHY_1000T_CTRL, phy_ctrl); 4019 /* 4020 * Effectively starting the clock 4021 */ 4022 Adapter->smartspeed++; 4023 /* 4024 * Restart autonegotiation 4025 */ 4026 if (!e1000_phy_setup_autoneg(hw) && 4027 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4028 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4029 MII_CR_RESTART_AUTO_NEG); 4030 e1000_write_phy_reg(hw, 4031 PHY_CONTROL, phy_ctrl); 4032 } 4033 } 4034 return; 4035 /* 4036 * Has 6 seconds transpired still without link? Remember, 4037 * you should reset the smartspeed counter once you obtain 4038 * link 4039 */ 4040 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4041 /* 4042 * Yes. Remember, we did at the start determine that 4043 * there's a master/slave configuration fault, so we're 4044 * still assuming there's someone on the other end, but we 4045 * just haven't yet been able to talk to it. We then 4046 * re-enable auto configuration of master/slave to see if 4047 * we're running 2/3 pair cables. 4048 */ 4049 /* 4050 * If still no link, perhaps using 2/3 pair cable 4051 */ 4052 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4053 phy_ctrl |= CR_1000T_MS_ENABLE; 4054 e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4055 /* 4056 * Restart autoneg with phy enabled for manual 4057 * configuration of master/slave 4058 */ 4059 if (!e1000_phy_setup_autoneg(hw) && 4060 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4061 phy_ctrl |= 4062 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4063 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4064 } 4065 /* 4066 * Hopefully, there are no more faults and we've obtained 4067 * link as a result. 4068 */ 4069 } 4070 /* 4071 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4072 * seconds) 4073 */ 4074 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4075 Adapter->smartspeed = 0; 4076 } 4077 4078 static boolean_t 4079 is_valid_mac_addr(uint8_t *mac_addr) 4080 { 4081 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4082 const uint8_t addr_test2[6] = 4083 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4084 4085 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4086 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4087 return (B_FALSE); 4088 4089 return (B_TRUE); 4090 } 4091 4092 /* 4093 * e1000g_stall_check - check for tx stall 4094 * 4095 * This function checks if the adapter is stalled (in transmit). 4096 * 4097 * It is called each time the watchdog timeout is invoked. 4098 * If the transmit descriptor reclaim continuously fails, 4099 * the watchdog value will increment by 1. If the watchdog 4100 * value exceeds the threshold, the adapter is assumed to 4101 * have stalled and need to be reset. 4102 */ 4103 static boolean_t 4104 e1000g_stall_check(struct e1000g *Adapter) 4105 { 4106 e1000g_tx_ring_t *tx_ring; 4107 4108 tx_ring = Adapter->tx_ring; 4109 4110 if (Adapter->link_state != LINK_STATE_UP) 4111 return (B_FALSE); 4112 4113 if (tx_ring->recycle_fail > 0) 4114 tx_ring->stall_watchdog++; 4115 else 4116 tx_ring->stall_watchdog = 0; 4117 4118 if (tx_ring->stall_watchdog < E1000G_STALL_WATCHDOG_COUNT) 4119 return (B_FALSE); 4120 4121 tx_ring->stall_watchdog = 0; 4122 tx_ring->recycle_fail = 0; 4123 4124 return (B_TRUE); 4125 } 4126 4127 #ifdef E1000G_DEBUG 4128 static enum ioc_reply 4129 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4130 { 4131 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4132 e1000g_peekpoke_t *ppd; 4133 uint64_t mem_va; 4134 uint64_t maxoff; 4135 boolean_t peek; 4136 4137 switch (iocp->ioc_cmd) { 4138 4139 case E1000G_IOC_REG_PEEK: 4140 peek = B_TRUE; 4141 break; 4142 4143 case E1000G_IOC_REG_POKE: 4144 peek = B_FALSE; 4145 break; 4146 4147 deault: 4148 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4149 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4150 iocp->ioc_cmd); 4151 return (IOC_INVAL); 4152 } 4153 4154 /* 4155 * Validate format of ioctl 4156 */ 4157 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4158 return (IOC_INVAL); 4159 if (mp->b_cont == NULL) 4160 return (IOC_INVAL); 4161 4162 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 4163 4164 /* 4165 * Validate request parameters 4166 */ 4167 switch (ppd->pp_acc_space) { 4168 4169 default: 4170 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4171 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4172 ppd->pp_acc_space); 4173 return (IOC_INVAL); 4174 4175 case E1000G_PP_SPACE_REG: 4176 /* 4177 * Memory-mapped I/O space 4178 */ 4179 ASSERT(ppd->pp_acc_size == 4); 4180 if (ppd->pp_acc_size != 4) 4181 return (IOC_INVAL); 4182 4183 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4184 return (IOC_INVAL); 4185 4186 mem_va = 0; 4187 maxoff = 0x10000; 4188 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4189 break; 4190 4191 case E1000G_PP_SPACE_E1000G: 4192 /* 4193 * E1000g data structure! 4194 */ 4195 mem_va = (uintptr_t)e1000gp; 4196 maxoff = sizeof (struct e1000g); 4197 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4198 break; 4199 4200 } 4201 4202 if (ppd->pp_acc_offset >= maxoff) 4203 return (IOC_INVAL); 4204 4205 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4206 return (IOC_INVAL); 4207 4208 /* 4209 * All OK - go! 4210 */ 4211 ppd->pp_acc_offset += mem_va; 4212 (*ppfn)(e1000gp, ppd); 4213 return (peek ? IOC_REPLY : IOC_ACK); 4214 } 4215 4216 static void 4217 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4218 { 4219 ddi_acc_handle_t handle; 4220 uint32_t *regaddr; 4221 4222 handle = e1000gp->osdep.reg_handle; 4223 regaddr = 4224 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4225 4226 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4227 } 4228 4229 static void 4230 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4231 { 4232 ddi_acc_handle_t handle; 4233 uint32_t *regaddr; 4234 uint32_t value; 4235 4236 handle = e1000gp->osdep.reg_handle; 4237 regaddr = 4238 (uint32_t *)(e1000gp->shared.hw_addr + ppd->pp_acc_offset); 4239 value = (uint32_t)ppd->pp_acc_data; 4240 4241 ddi_put32(handle, regaddr, value); 4242 } 4243 4244 static void 4245 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4246 { 4247 uint64_t value; 4248 void *vaddr; 4249 4250 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4251 4252 switch (ppd->pp_acc_size) { 4253 case 1: 4254 value = *(uint8_t *)vaddr; 4255 break; 4256 4257 case 2: 4258 value = *(uint16_t *)vaddr; 4259 break; 4260 4261 case 4: 4262 value = *(uint32_t *)vaddr; 4263 break; 4264 4265 case 8: 4266 value = *(uint64_t *)vaddr; 4267 break; 4268 } 4269 4270 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4271 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4272 (void *)e1000gp, (void *)ppd, value, vaddr); 4273 4274 ppd->pp_acc_data = value; 4275 } 4276 4277 static void 4278 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4279 { 4280 uint64_t value; 4281 void *vaddr; 4282 4283 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4284 value = ppd->pp_acc_data; 4285 4286 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4287 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4288 (void *)e1000gp, (void *)ppd, value, vaddr); 4289 4290 switch (ppd->pp_acc_size) { 4291 case 1: 4292 *(uint8_t *)vaddr = (uint8_t)value; 4293 break; 4294 4295 case 2: 4296 *(uint16_t *)vaddr = (uint16_t)value; 4297 break; 4298 4299 case 4: 4300 *(uint32_t *)vaddr = (uint32_t)value; 4301 break; 4302 4303 case 8: 4304 *(uint64_t *)vaddr = (uint64_t)value; 4305 break; 4306 } 4307 } 4308 #endif 4309 4310 /* 4311 * Loopback Support 4312 */ 4313 static lb_property_t lb_normal = 4314 { normal, "normal", E1000G_LB_NONE }; 4315 static lb_property_t lb_external1000 = 4316 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 4317 static lb_property_t lb_external100 = 4318 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 4319 static lb_property_t lb_external10 = 4320 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 4321 static lb_property_t lb_phy = 4322 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 4323 4324 static enum ioc_reply 4325 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 4326 { 4327 lb_info_sz_t *lbsp; 4328 lb_property_t *lbpp; 4329 struct e1000_hw *hw; 4330 uint32_t *lbmp; 4331 uint32_t size; 4332 uint32_t value; 4333 4334 hw = &Adapter->shared; 4335 4336 if (mp->b_cont == NULL) 4337 return (IOC_INVAL); 4338 4339 switch (iocp->ioc_cmd) { 4340 default: 4341 return (IOC_INVAL); 4342 4343 case LB_GET_INFO_SIZE: 4344 size = sizeof (lb_info_sz_t); 4345 if (iocp->ioc_count != size) 4346 return (IOC_INVAL); 4347 4348 rw_enter(&Adapter->chip_lock, RW_WRITER); 4349 e1000g_get_phy_state(Adapter); 4350 4351 /* 4352 * Workaround for hardware faults. In order to get a stable 4353 * state of phy, we will wait for a specific interval and 4354 * try again. The time delay is an experiential value based 4355 * on our testing. 4356 */ 4357 msec_delay(100); 4358 e1000g_get_phy_state(Adapter); 4359 rw_exit(&Adapter->chip_lock); 4360 4361 value = sizeof (lb_normal); 4362 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4363 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4364 (hw->media_type == e1000_media_type_fiber) || 4365 (hw->media_type == e1000_media_type_internal_serdes)) { 4366 value += sizeof (lb_phy); 4367 switch (hw->mac.type) { 4368 case e1000_82571: 4369 case e1000_82572: 4370 value += sizeof (lb_external1000); 4371 break; 4372 } 4373 } 4374 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4375 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4376 value += sizeof (lb_external100); 4377 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4378 value += sizeof (lb_external10); 4379 4380 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 4381 *lbsp = value; 4382 break; 4383 4384 case LB_GET_INFO: 4385 value = sizeof (lb_normal); 4386 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4387 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4388 (hw->media_type == e1000_media_type_fiber) || 4389 (hw->media_type == e1000_media_type_internal_serdes)) { 4390 value += sizeof (lb_phy); 4391 switch (hw->mac.type) { 4392 case e1000_82571: 4393 case e1000_82572: 4394 value += sizeof (lb_external1000); 4395 break; 4396 } 4397 } 4398 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4399 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4400 value += sizeof (lb_external100); 4401 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4402 value += sizeof (lb_external10); 4403 4404 size = value; 4405 if (iocp->ioc_count != size) 4406 return (IOC_INVAL); 4407 4408 value = 0; 4409 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 4410 lbpp[value++] = lb_normal; 4411 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 4412 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 4413 (hw->media_type == e1000_media_type_fiber) || 4414 (hw->media_type == e1000_media_type_internal_serdes)) { 4415 lbpp[value++] = lb_phy; 4416 switch (hw->mac.type) { 4417 case e1000_82571: 4418 case e1000_82572: 4419 lbpp[value++] = lb_external1000; 4420 break; 4421 } 4422 } 4423 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 4424 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 4425 lbpp[value++] = lb_external100; 4426 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 4427 lbpp[value++] = lb_external10; 4428 break; 4429 4430 case LB_GET_MODE: 4431 size = sizeof (uint32_t); 4432 if (iocp->ioc_count != size) 4433 return (IOC_INVAL); 4434 4435 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4436 *lbmp = Adapter->loopback_mode; 4437 break; 4438 4439 case LB_SET_MODE: 4440 size = 0; 4441 if (iocp->ioc_count != sizeof (uint32_t)) 4442 return (IOC_INVAL); 4443 4444 lbmp = (uint32_t *)mp->b_cont->b_rptr; 4445 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 4446 return (IOC_INVAL); 4447 break; 4448 } 4449 4450 iocp->ioc_count = size; 4451 iocp->ioc_error = 0; 4452 4453 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 4454 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4455 return (IOC_INVAL); 4456 } 4457 4458 return (IOC_REPLY); 4459 } 4460 4461 static boolean_t 4462 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 4463 { 4464 struct e1000_hw *hw; 4465 int i, times; 4466 boolean_t link_up; 4467 4468 if (mode == Adapter->loopback_mode) 4469 return (B_TRUE); 4470 4471 hw = &Adapter->shared; 4472 times = 0; 4473 4474 Adapter->loopback_mode = mode; 4475 4476 if (mode == E1000G_LB_NONE) { 4477 /* Reset the chip */ 4478 hw->phy.wait_for_link = B_TRUE; 4479 (void) e1000g_reset(Adapter); 4480 hw->phy.wait_for_link = B_FALSE; 4481 return (B_TRUE); 4482 } 4483 4484 again: 4485 4486 rw_enter(&Adapter->chip_lock, RW_WRITER); 4487 4488 switch (mode) { 4489 default: 4490 rw_exit(&Adapter->chip_lock); 4491 return (B_FALSE); 4492 4493 case E1000G_LB_EXTERNAL_1000: 4494 e1000g_set_external_loopback_1000(Adapter); 4495 break; 4496 4497 case E1000G_LB_EXTERNAL_100: 4498 e1000g_set_external_loopback_100(Adapter); 4499 break; 4500 4501 case E1000G_LB_EXTERNAL_10: 4502 e1000g_set_external_loopback_10(Adapter); 4503 break; 4504 4505 case E1000G_LB_INTERNAL_PHY: 4506 e1000g_set_internal_loopback(Adapter); 4507 break; 4508 } 4509 4510 times++; 4511 4512 rw_exit(&Adapter->chip_lock); 4513 4514 /* Wait for link up */ 4515 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 4516 msec_delay(100); 4517 4518 rw_enter(&Adapter->chip_lock, RW_WRITER); 4519 4520 link_up = e1000g_link_up(Adapter); 4521 4522 rw_exit(&Adapter->chip_lock); 4523 4524 if (!link_up) { 4525 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4526 "Failed to get the link up"); 4527 if (times < 2) { 4528 /* Reset the link */ 4529 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4530 "Reset the link ..."); 4531 (void) e1000g_reset(Adapter); 4532 goto again; 4533 } 4534 } 4535 4536 return (B_TRUE); 4537 } 4538 4539 /* 4540 * The following loopback settings are from Intel's technical 4541 * document - "How To Loopback". All the register settings and 4542 * time delay values are directly inherited from the document 4543 * without more explanations available. 4544 */ 4545 static void 4546 e1000g_set_internal_loopback(struct e1000g *Adapter) 4547 { 4548 struct e1000_hw *hw; 4549 uint32_t ctrl; 4550 uint32_t status; 4551 uint16_t phy_ctrl; 4552 uint32_t txcw; 4553 4554 hw = &Adapter->shared; 4555 4556 /* Disable Smart Power Down */ 4557 phy_spd_state(hw, B_FALSE); 4558 4559 e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 4560 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 4561 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 4562 4563 switch (hw->mac.type) { 4564 case e1000_82540: 4565 case e1000_82545: 4566 case e1000_82545_rev_3: 4567 case e1000_82546: 4568 case e1000_82546_rev_3: 4569 case e1000_82573: 4570 /* Auto-MDI/MDIX off */ 4571 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 4572 /* Reset PHY to update Auto-MDI/MDIX */ 4573 e1000_write_phy_reg(hw, PHY_CONTROL, 4574 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 4575 /* Reset PHY to auto-neg off and force 1000 */ 4576 e1000_write_phy_reg(hw, PHY_CONTROL, 4577 phy_ctrl | MII_CR_RESET); 4578 /* 4579 * Disable PHY receiver for 82540/545/546 and 82573 Family. 4580 * See comments above e1000g_set_internal_loopback() for the 4581 * background. 4582 */ 4583 e1000_write_phy_reg(hw, 29, 0x001F); 4584 e1000_write_phy_reg(hw, 30, 0x8FFC); 4585 e1000_write_phy_reg(hw, 29, 0x001A); 4586 e1000_write_phy_reg(hw, 30, 0x8FF0); 4587 break; 4588 } 4589 4590 /* Set loopback */ 4591 e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 4592 4593 msec_delay(250); 4594 4595 /* Now set up the MAC to the same speed/duplex as the PHY. */ 4596 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4597 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4598 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4599 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4600 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 4601 E1000_CTRL_FD); /* Force Duplex to FULL */ 4602 4603 switch (hw->mac.type) { 4604 case e1000_82540: 4605 case e1000_82545: 4606 case e1000_82545_rev_3: 4607 case e1000_82546: 4608 case e1000_82546_rev_3: 4609 /* 4610 * For some serdes we'll need to commit the writes now 4611 * so that the status is updated on link 4612 */ 4613 if (hw->media_type == e1000_media_type_internal_serdes) { 4614 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4615 msec_delay(100); 4616 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4617 } 4618 4619 if (hw->media_type == e1000_media_type_copper) { 4620 /* Invert Loss of Signal */ 4621 ctrl |= E1000_CTRL_ILOS; 4622 } else { 4623 /* Set ILOS on fiber nic if half duplex is detected */ 4624 status = E1000_READ_REG(hw, E1000_STATUS); 4625 if ((status & E1000_STATUS_FD) == 0) 4626 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4627 } 4628 break; 4629 4630 case e1000_82571: 4631 case e1000_82572: 4632 /* 4633 * The fiber/SerDes versions of this adapter do not contain an 4634 * accessible PHY. Therefore, loopback beyond MAC must be done 4635 * using SerDes analog loopback. 4636 */ 4637 if (hw->media_type != e1000_media_type_copper) { 4638 status = E1000_READ_REG(hw, E1000_STATUS); 4639 /* Set ILOS on fiber nic if half duplex is detected */ 4640 if (((status & E1000_STATUS_LU) == 0) || 4641 ((status & E1000_STATUS_FD) == 0) || 4642 (hw->media_type == 4643 e1000_media_type_internal_serdes)) 4644 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4645 4646 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4647 txcw = E1000_READ_REG(hw, E1000_TXCW); 4648 txcw &= ~((uint32_t)1 << 31); 4649 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4650 4651 /* 4652 * Write 0x410 to Serdes Control register 4653 * to enable Serdes analog loopback 4654 */ 4655 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4656 msec_delay(10); 4657 } 4658 break; 4659 4660 case e1000_82573: 4661 ctrl |= E1000_CTRL_ILOS; 4662 break; 4663 } 4664 4665 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4666 4667 } 4668 4669 static void 4670 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 4671 { 4672 struct e1000_hw *hw; 4673 uint32_t rctl; 4674 uint32_t ctrl_ext; 4675 uint32_t ctrl; 4676 uint32_t status; 4677 uint32_t txcw; 4678 4679 hw = &Adapter->shared; 4680 4681 /* Disable Smart Power Down */ 4682 phy_spd_state(hw, B_FALSE); 4683 4684 switch (hw->media_type) { 4685 case e1000_media_type_copper: 4686 /* Force link up (Must be done before the PHY writes) */ 4687 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4688 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 4689 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4690 4691 rctl = E1000_READ_REG(hw, E1000_RCTL); 4692 rctl |= (E1000_RCTL_EN | 4693 E1000_RCTL_SBP | 4694 E1000_RCTL_UPE | 4695 E1000_RCTL_MPE | 4696 E1000_RCTL_LPE | 4697 E1000_RCTL_BAM); /* 0x803E */ 4698 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 4699 4700 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 4701 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 4702 E1000_CTRL_EXT_SDP6_DATA | 4703 E1000_CTRL_EXT_SDP7_DATA | 4704 E1000_CTRL_EXT_SDP4_DIR | 4705 E1000_CTRL_EXT_SDP6_DIR | 4706 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 4707 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 4708 4709 /* 4710 * This sequence tunes the PHY's SDP and no customer 4711 * settable values. For background, see comments above 4712 * e1000g_set_internal_loopback(). 4713 */ 4714 e1000_write_phy_reg(hw, 0x0, 0x140); 4715 msec_delay(10); 4716 e1000_write_phy_reg(hw, 0x9, 0x1A00); 4717 e1000_write_phy_reg(hw, 0x12, 0xC10); 4718 e1000_write_phy_reg(hw, 0x12, 0x1C10); 4719 e1000_write_phy_reg(hw, 0x1F37, 0x76); 4720 e1000_write_phy_reg(hw, 0x1F33, 0x1); 4721 e1000_write_phy_reg(hw, 0x1F33, 0x0); 4722 4723 e1000_write_phy_reg(hw, 0x1F35, 0x65); 4724 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 4725 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 4726 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 4727 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 4728 4729 msec_delay(50); 4730 break; 4731 case e1000_media_type_fiber: 4732 case e1000_media_type_internal_serdes: 4733 status = E1000_READ_REG(hw, E1000_STATUS); 4734 if (((status & E1000_STATUS_LU) == 0) || 4735 (hw->media_type == e1000_media_type_internal_serdes)) { 4736 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4737 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 4738 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4739 } 4740 4741 /* Disable autoneg by setting bit 31 of TXCW to zero */ 4742 txcw = E1000_READ_REG(hw, E1000_TXCW); 4743 txcw &= ~((uint32_t)1 << 31); 4744 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 4745 4746 /* 4747 * Write 0x410 to Serdes Control register 4748 * to enable Serdes analog loopback 4749 */ 4750 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 4751 msec_delay(10); 4752 break; 4753 default: 4754 break; 4755 } 4756 } 4757 4758 static void 4759 e1000g_set_external_loopback_100(struct e1000g *Adapter) 4760 { 4761 struct e1000_hw *hw; 4762 uint32_t ctrl; 4763 uint16_t phy_ctrl; 4764 4765 hw = &Adapter->shared; 4766 4767 /* Disable Smart Power Down */ 4768 phy_spd_state(hw, B_FALSE); 4769 4770 phy_ctrl = (MII_CR_FULL_DUPLEX | 4771 MII_CR_SPEED_100); 4772 4773 /* Force 100/FD, reset PHY */ 4774 e1000_write_phy_reg(hw, PHY_CONTROL, 4775 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 4776 msec_delay(10); 4777 4778 /* Force 100/FD */ 4779 e1000_write_phy_reg(hw, PHY_CONTROL, 4780 phy_ctrl); /* 0x2100 */ 4781 msec_delay(10); 4782 4783 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4784 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4785 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4786 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4787 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4788 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4789 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 4790 E1000_CTRL_FD); /* Force Duplex to FULL */ 4791 4792 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4793 } 4794 4795 static void 4796 e1000g_set_external_loopback_10(struct e1000g *Adapter) 4797 { 4798 struct e1000_hw *hw; 4799 uint32_t ctrl; 4800 uint16_t phy_ctrl; 4801 4802 hw = &Adapter->shared; 4803 4804 /* Disable Smart Power Down */ 4805 phy_spd_state(hw, B_FALSE); 4806 4807 phy_ctrl = (MII_CR_FULL_DUPLEX | 4808 MII_CR_SPEED_10); 4809 4810 /* Force 10/FD, reset PHY */ 4811 e1000_write_phy_reg(hw, PHY_CONTROL, 4812 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 4813 msec_delay(10); 4814 4815 /* Force 10/FD */ 4816 e1000_write_phy_reg(hw, PHY_CONTROL, 4817 phy_ctrl); /* 0x0100 */ 4818 msec_delay(10); 4819 4820 /* Now setup the MAC to the same speed/duplex as the PHY. */ 4821 ctrl = E1000_READ_REG(hw, E1000_CTRL); 4822 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 4823 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 4824 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 4825 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 4826 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 4827 E1000_CTRL_FD); /* Force Duplex to FULL */ 4828 4829 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 4830 } 4831 4832 #ifdef __sparc 4833 static boolean_t 4834 e1000g_find_mac_address(struct e1000g *Adapter) 4835 { 4836 struct e1000_hw *hw = &Adapter->shared; 4837 uchar_t *bytes; 4838 struct ether_addr sysaddr; 4839 uint_t nelts; 4840 int err; 4841 boolean_t found = B_FALSE; 4842 4843 /* 4844 * The "vendor's factory-set address" may already have 4845 * been extracted from the chip, but if the property 4846 * "local-mac-address" is set we use that instead. 4847 * 4848 * We check whether it looks like an array of 6 4849 * bytes (which it should, if OBP set it). If we can't 4850 * make sense of it this way, we'll ignore it. 4851 */ 4852 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4853 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 4854 if (err == DDI_PROP_SUCCESS) { 4855 if (nelts == ETHERADDRL) { 4856 while (nelts--) 4857 hw->mac.addr[nelts] = bytes[nelts]; 4858 found = B_TRUE; 4859 } 4860 ddi_prop_free(bytes); 4861 } 4862 4863 /* 4864 * Look up the OBP property "local-mac-address?". If the user has set 4865 * 'local-mac-address? = false', use "the system address" instead. 4866 */ 4867 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 4868 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 4869 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 4870 if (localetheraddr(NULL, &sysaddr) != 0) { 4871 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 4872 found = B_TRUE; 4873 } 4874 } 4875 ddi_prop_free(bytes); 4876 } 4877 4878 /* 4879 * Finally(!), if there's a valid "mac-address" property (created 4880 * if we netbooted from this interface), we must use this instead 4881 * of any of the above to ensure that the NFS/install server doesn't 4882 * get confused by the address changing as Solaris takes over! 4883 */ 4884 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 4885 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 4886 if (err == DDI_PROP_SUCCESS) { 4887 if (nelts == ETHERADDRL) { 4888 while (nelts--) 4889 hw->mac.addr[nelts] = bytes[nelts]; 4890 found = B_TRUE; 4891 } 4892 ddi_prop_free(bytes); 4893 } 4894 4895 if (found) { 4896 bcopy(hw->mac.addr, hw->mac.perm_addr, 4897 ETHERADDRL); 4898 } 4899 4900 return (found); 4901 } 4902 #endif 4903 4904 static int 4905 e1000g_add_intrs(struct e1000g *Adapter) 4906 { 4907 dev_info_t *devinfo; 4908 int intr_types; 4909 int rc; 4910 4911 devinfo = Adapter->dip; 4912 4913 /* Get supported interrupt types */ 4914 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 4915 4916 if (rc != DDI_SUCCESS) { 4917 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 4918 "Get supported interrupt types failed: %d\n", rc); 4919 return (DDI_FAILURE); 4920 } 4921 4922 /* 4923 * Based on Intel Technical Advisory document (TA-160), there are some 4924 * cases where some older Intel PCI-X NICs may "advertise" to the OS 4925 * that it supports MSI, but in fact has problems. 4926 * So we should only enable MSI for PCI-E NICs and disable MSI for old 4927 * PCI/PCI-X NICs. 4928 */ 4929 if (Adapter->shared.mac.type < e1000_82571) 4930 Adapter->msi_enabled = B_FALSE; 4931 4932 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 4933 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 4934 4935 if (rc != DDI_SUCCESS) { 4936 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4937 "Add MSI failed, trying Legacy interrupts\n"); 4938 } else { 4939 Adapter->intr_type = DDI_INTR_TYPE_MSI; 4940 } 4941 } 4942 4943 if ((Adapter->intr_type == 0) && 4944 (intr_types & DDI_INTR_TYPE_FIXED)) { 4945 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 4946 4947 if (rc != DDI_SUCCESS) { 4948 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4949 "Add Legacy interrupts failed\n"); 4950 return (DDI_FAILURE); 4951 } 4952 4953 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 4954 } 4955 4956 if (Adapter->intr_type == 0) { 4957 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 4958 "No interrupts registered\n"); 4959 return (DDI_FAILURE); 4960 } 4961 4962 return (DDI_SUCCESS); 4963 } 4964 4965 /* 4966 * e1000g_intr_add() handles MSI/Legacy interrupts 4967 */ 4968 static int 4969 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 4970 { 4971 dev_info_t *devinfo; 4972 int count, avail, actual; 4973 int x, y, rc, inum = 0; 4974 int flag; 4975 ddi_intr_handler_t *intr_handler; 4976 4977 devinfo = Adapter->dip; 4978 4979 /* get number of interrupts */ 4980 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 4981 if ((rc != DDI_SUCCESS) || (count == 0)) { 4982 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4983 "Get interrupt number failed. Return: %d, count: %d\n", 4984 rc, count); 4985 return (DDI_FAILURE); 4986 } 4987 4988 /* get number of available interrupts */ 4989 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 4990 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4991 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4992 "Get interrupt available number failed. " 4993 "Return: %d, available: %d\n", rc, avail); 4994 return (DDI_FAILURE); 4995 } 4996 4997 if (avail < count) { 4998 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 4999 "Interrupts count: %d, available: %d\n", 5000 count, avail); 5001 } 5002 5003 /* Allocate an array of interrupt handles */ 5004 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5005 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5006 5007 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5008 flag = DDI_INTR_ALLOC_NORMAL; 5009 5010 /* call ddi_intr_alloc() */ 5011 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5012 count, &actual, flag); 5013 5014 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5015 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5016 "Allocate interrupts failed: %d\n", rc); 5017 5018 kmem_free(Adapter->htable, Adapter->intr_size); 5019 return (DDI_FAILURE); 5020 } 5021 5022 if (actual < count) { 5023 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5024 "Interrupts requested: %d, received: %d\n", 5025 count, actual); 5026 } 5027 5028 Adapter->intr_cnt = actual; 5029 5030 /* Get priority for first msi, assume remaining are all the same */ 5031 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5032 5033 if (rc != DDI_SUCCESS) { 5034 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5035 "Get interrupt priority failed: %d\n", rc); 5036 5037 /* Free already allocated intr */ 5038 for (y = 0; y < actual; y++) 5039 (void) ddi_intr_free(Adapter->htable[y]); 5040 5041 kmem_free(Adapter->htable, Adapter->intr_size); 5042 return (DDI_FAILURE); 5043 } 5044 5045 /* 5046 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5047 * use the interrupt service routine e1000g_intr_pciexpress() 5048 * to avoid interrupt stealing when sharing interrupt with other 5049 * devices. 5050 */ 5051 if (Adapter->shared.mac.type < e1000_82571) 5052 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5053 else 5054 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5055 5056 /* Call ddi_intr_add_handler() */ 5057 for (x = 0; x < actual; x++) { 5058 rc = ddi_intr_add_handler(Adapter->htable[x], 5059 intr_handler, (caddr_t)Adapter, NULL); 5060 5061 if (rc != DDI_SUCCESS) { 5062 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5063 "Add interrupt handler failed: %d\n", rc); 5064 5065 /* Remove already added handler */ 5066 for (y = 0; y < x; y++) 5067 (void) ddi_intr_remove_handler( 5068 Adapter->htable[y]); 5069 5070 /* Free already allocated intr */ 5071 for (y = 0; y < actual; y++) 5072 (void) ddi_intr_free(Adapter->htable[y]); 5073 5074 kmem_free(Adapter->htable, Adapter->intr_size); 5075 return (DDI_FAILURE); 5076 } 5077 } 5078 5079 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5080 5081 if (rc != DDI_SUCCESS) { 5082 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5083 "Get interrupt cap failed: %d\n", rc); 5084 5085 /* Free already allocated intr */ 5086 for (y = 0; y < actual; y++) { 5087 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5088 (void) ddi_intr_free(Adapter->htable[y]); 5089 } 5090 5091 kmem_free(Adapter->htable, Adapter->intr_size); 5092 return (DDI_FAILURE); 5093 } 5094 5095 return (DDI_SUCCESS); 5096 } 5097 5098 static int 5099 e1000g_rem_intrs(struct e1000g *Adapter) 5100 { 5101 int x; 5102 int rc; 5103 5104 for (x = 0; x < Adapter->intr_cnt; x++) { 5105 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5106 if (rc != DDI_SUCCESS) { 5107 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5108 "Remove intr handler failed: %d\n", rc); 5109 return (DDI_FAILURE); 5110 } 5111 5112 rc = ddi_intr_free(Adapter->htable[x]); 5113 if (rc != DDI_SUCCESS) { 5114 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5115 "Free intr failed: %d\n", rc); 5116 return (DDI_FAILURE); 5117 } 5118 } 5119 5120 kmem_free(Adapter->htable, Adapter->intr_size); 5121 5122 return (DDI_SUCCESS); 5123 } 5124 5125 static int 5126 e1000g_enable_intrs(struct e1000g *Adapter) 5127 { 5128 int x; 5129 int rc; 5130 5131 /* Enable interrupts */ 5132 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5133 /* Call ddi_intr_block_enable() for MSI */ 5134 rc = ddi_intr_block_enable(Adapter->htable, 5135 Adapter->intr_cnt); 5136 if (rc != DDI_SUCCESS) { 5137 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5138 "Enable block intr failed: %d\n", rc); 5139 return (DDI_FAILURE); 5140 } 5141 } else { 5142 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5143 for (x = 0; x < Adapter->intr_cnt; x++) { 5144 rc = ddi_intr_enable(Adapter->htable[x]); 5145 if (rc != DDI_SUCCESS) { 5146 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5147 "Enable intr failed: %d\n", rc); 5148 return (DDI_FAILURE); 5149 } 5150 } 5151 } 5152 5153 return (DDI_SUCCESS); 5154 } 5155 5156 static int 5157 e1000g_disable_intrs(struct e1000g *Adapter) 5158 { 5159 int x; 5160 int rc; 5161 5162 /* Disable all interrupts */ 5163 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5164 rc = ddi_intr_block_disable(Adapter->htable, 5165 Adapter->intr_cnt); 5166 if (rc != DDI_SUCCESS) { 5167 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5168 "Disable block intr failed: %d\n", rc); 5169 return (DDI_FAILURE); 5170 } 5171 } else { 5172 for (x = 0; x < Adapter->intr_cnt; x++) { 5173 rc = ddi_intr_disable(Adapter->htable[x]); 5174 if (rc != DDI_SUCCESS) { 5175 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5176 "Disable intr failed: %d\n", rc); 5177 return (DDI_FAILURE); 5178 } 5179 } 5180 } 5181 5182 return (DDI_SUCCESS); 5183 } 5184 5185 /* 5186 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5187 */ 5188 static void 5189 e1000g_get_phy_state(struct e1000g *Adapter) 5190 { 5191 struct e1000_hw *hw = &Adapter->shared; 5192 5193 e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 5194 e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 5195 e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &Adapter->phy_an_adv); 5196 e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &Adapter->phy_an_exp); 5197 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &Adapter->phy_ext_status); 5198 e1000_read_phy_reg(hw, PHY_1000T_CTRL, &Adapter->phy_1000t_ctrl); 5199 e1000_read_phy_reg(hw, PHY_1000T_STATUS, &Adapter->phy_1000t_status); 5200 e1000_read_phy_reg(hw, PHY_LP_ABILITY, &Adapter->phy_lp_able); 5201 5202 Adapter->param_autoneg_cap = 5203 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 5204 Adapter->param_pause_cap = 5205 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5206 Adapter->param_asym_pause_cap = 5207 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5208 Adapter->param_1000fdx_cap = 5209 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5210 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5211 Adapter->param_1000hdx_cap = 5212 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5213 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5214 Adapter->param_100t4_cap = 5215 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 5216 Adapter->param_100fdx_cap = 5217 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5218 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5219 Adapter->param_100hdx_cap = 5220 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5221 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5222 Adapter->param_10fdx_cap = 5223 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5224 Adapter->param_10hdx_cap = 5225 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5226 5227 Adapter->param_adv_autoneg = hw->mac.autoneg; 5228 Adapter->param_adv_pause = 5229 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 5230 Adapter->param_adv_asym_pause = 5231 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 5232 Adapter->param_adv_1000hdx = 5233 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 5234 Adapter->param_adv_100t4 = 5235 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 5236 if (Adapter->param_adv_autoneg == 1) { 5237 Adapter->param_adv_1000fdx = 5238 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) ? 1 : 0; 5239 Adapter->param_adv_100fdx = 5240 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) ? 1 : 0; 5241 Adapter->param_adv_100hdx = 5242 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) ? 1 : 0; 5243 Adapter->param_adv_10fdx = 5244 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 5245 Adapter->param_adv_10hdx = 5246 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 5247 } 5248 5249 Adapter->param_lp_autoneg = 5250 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 5251 Adapter->param_lp_pause = 5252 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 5253 Adapter->param_lp_asym_pause = 5254 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 5255 Adapter->param_lp_1000fdx = 5256 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 5257 Adapter->param_lp_1000hdx = 5258 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 5259 Adapter->param_lp_100t4 = 5260 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 5261 Adapter->param_lp_100fdx = 5262 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 5263 Adapter->param_lp_100hdx = 5264 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 5265 Adapter->param_lp_10fdx = 5266 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 5267 Adapter->param_lp_10hdx = 5268 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 5269 } 5270 5271 /* 5272 * FMA support 5273 */ 5274 5275 int 5276 e1000g_check_acc_handle(ddi_acc_handle_t handle) 5277 { 5278 ddi_fm_error_t de; 5279 5280 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 5281 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 5282 return (de.fme_status); 5283 } 5284 5285 int 5286 e1000g_check_dma_handle(ddi_dma_handle_t handle) 5287 { 5288 ddi_fm_error_t de; 5289 5290 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 5291 return (de.fme_status); 5292 } 5293 5294 /* 5295 * The IO fault service error handling callback function 5296 */ 5297 static int 5298 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 5299 { 5300 /* 5301 * as the driver can always deal with an error in any dma or 5302 * access handle, we can just return the fme_status value. 5303 */ 5304 pci_ereport_post(dip, err, NULL); 5305 return (err->fme_status); 5306 } 5307 5308 static void 5309 e1000g_fm_init(struct e1000g *Adapter) 5310 { 5311 ddi_iblock_cookie_t iblk; 5312 int fma_acc_flag, fma_dma_flag; 5313 5314 /* Only register with IO Fault Services if we have some capability */ 5315 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 5316 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 5317 fma_acc_flag = 1; 5318 } else { 5319 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 5320 fma_acc_flag = 0; 5321 } 5322 5323 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 5324 fma_dma_flag = 1; 5325 } else { 5326 fma_dma_flag = 0; 5327 } 5328 5329 (void) e1000g_set_fma_flags(Adapter, fma_acc_flag, fma_dma_flag); 5330 5331 if (Adapter->fm_capabilities) { 5332 5333 /* Register capabilities with IO Fault Services */ 5334 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 5335 5336 /* 5337 * Initialize pci ereport capabilities if ereport capable 5338 */ 5339 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5340 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5341 pci_ereport_setup(Adapter->dip); 5342 5343 /* 5344 * Register error callback if error callback capable 5345 */ 5346 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5347 ddi_fm_handler_register(Adapter->dip, 5348 e1000g_fm_error_cb, (void*) Adapter); 5349 } 5350 } 5351 5352 static void 5353 e1000g_fm_fini(struct e1000g *Adapter) 5354 { 5355 /* Only unregister FMA capabilities if we registered some */ 5356 if (Adapter->fm_capabilities) { 5357 5358 /* 5359 * Release any resources allocated by pci_ereport_setup() 5360 */ 5361 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 5362 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5363 pci_ereport_teardown(Adapter->dip); 5364 5365 /* 5366 * Un-register error callback if error callback capable 5367 */ 5368 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 5369 ddi_fm_handler_unregister(Adapter->dip); 5370 5371 /* Unregister from IO Fault Services */ 5372 ddi_fm_fini(Adapter->dip); 5373 } 5374 } 5375 5376 void 5377 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 5378 { 5379 uint64_t ena; 5380 char buf[FM_MAX_CLASS]; 5381 5382 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 5383 ena = fm_ena_generate(0, FM_ENA_FMT1); 5384 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 5385 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 5386 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 5387 } 5388 } 5389 5390 static int 5391 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 5392 uint_t pr_valsize, void *pr_val) 5393 { 5394 link_flowctrl_t fl; 5395 uint32_t fc; 5396 int err = 0; 5397 5398 ASSERT(pr_valsize > 0); 5399 switch (pr_num) { 5400 case DLD_PROP_AUTONEG: 5401 *(uint8_t *)pr_val = 5402 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0); 5403 break; 5404 case DLD_PROP_FLOWCTRL: 5405 if (pr_valsize < sizeof (link_flowctrl_t)) 5406 return (EINVAL); 5407 fl = LINK_FLOWCTRL_BI; 5408 bcopy(&fl, pr_val, sizeof (fl)); 5409 break; 5410 case DLD_PROP_ADV_1000FDX_CAP: 5411 case DLD_PROP_EN_1000FDX_CAP: 5412 *(uint8_t *)pr_val = 5413 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5414 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 5415 break; 5416 case DLD_PROP_ADV_1000HDX_CAP: 5417 case DLD_PROP_EN_1000HDX_CAP: 5418 *(uint8_t *)pr_val = 5419 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 5420 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 5421 break; 5422 case DLD_PROP_ADV_100FDX_CAP: 5423 case DLD_PROP_EN_100FDX_CAP: 5424 *(uint8_t *)pr_val = 5425 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5426 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 5427 case DLD_PROP_ADV_100HDX_CAP: 5428 case DLD_PROP_EN_100HDX_CAP: 5429 *(uint8_t *)pr_val = 5430 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 5431 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 5432 break; 5433 case DLD_PROP_ADV_10FDX_CAP: 5434 case DLD_PROP_EN_10FDX_CAP: 5435 *(uint8_t *)pr_val = 5436 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 5437 break; 5438 case DLD_PROP_ADV_10HDX_CAP: 5439 case DLD_PROP_EN_10HDX_CAP: 5440 *(uint8_t *)pr_val = 5441 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 5442 break; 5443 default: 5444 err = ENOTSUP; 5445 break; 5446 } 5447 return (err); 5448 } 5449 5450 /* 5451 * synchronize the adv* and en* parameters. 5452 * 5453 * See comments in <sys/dld.h> for details of the *_en_* 5454 * parameters. The usage of ndd for setting adv parameters will 5455 * synchronize all the en parameters with the e1000g parameters, 5456 * implicity disalbing any settings made via dladm. 5457 */ 5458 static void 5459 e1000g_param_sync(struct e1000g *Adapter) 5460 { 5461 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 5462 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 5463 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 5464 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 5465 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 5466 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 5467 } 5468