1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2007 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * ********************************************************************** 30 * * 31 * Module Name: * 32 * e1000g_main.c * 33 * * 34 * Abstract: * 35 * This file contains the interface routine for the solaris OS. * 36 * It has all DDI entry point routines and GLD entry point * 37 * routines. * 38 * This file also contains routines that takes care of initialization * 39 * uninit routine and interrupt routine * 40 * * 41 * * 42 * Environment: * 43 * Kernel Mode - * 44 * * 45 * ********************************************************************** 46 */ 47 48 #include <sys/dlpi.h> 49 #include <sys/mac.h> 50 #include "e1000g_sw.h" 51 #include "e1000g_debug.h" 52 53 #define E1000_RX_INTPT_TIME 128 54 #define E1000_RX_PKT_CNT 8 55 56 static char ident[] = "Intel PRO/1000 Ethernet 5.1.6"; 57 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 58 static char e1000g_version[] = "Driver Ver. 5.1.6"; 59 60 /* 61 * Proto types for DDI entry points 62 */ 63 static int e1000gattach(dev_info_t *, ddi_attach_cmd_t); 64 static int e1000gdetach(dev_info_t *, ddi_detach_cmd_t); 65 66 /* 67 * init and intr routines prototype 68 */ 69 static int e1000g_resume(dev_info_t *devinfo); 70 static int e1000g_suspend(dev_info_t *devinfo); 71 static uint_t e1000g_intr_pciexpress(caddr_t); 72 static uint_t e1000g_intr(caddr_t); 73 static void e1000g_intr_work(struct e1000g *, uint32_t); 74 #pragma inline(e1000g_intr_work) 75 static int e1000g_init(struct e1000g *); 76 static int e1000g_start(struct e1000g *); 77 static void e1000g_stop(struct e1000g *); 78 static boolean_t e1000g_reset(struct e1000g *); 79 static int e1000g_m_start(void *); 80 static void e1000g_m_stop(void *); 81 static int e1000g_m_promisc(void *, boolean_t); 82 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 83 static int e1000g_m_unicst(void *, const uint8_t *); 84 static int e1000g_m_unicst_add(void *, mac_multi_addr_t *); 85 static int e1000g_m_unicst_remove(void *, mac_addr_slot_t); 86 static int e1000g_m_unicst_modify(void *, mac_multi_addr_t *); 87 static int e1000g_m_unicst_get(void *, mac_multi_addr_t *); 88 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 89 static void e1000g_m_blank(void *, time_t, uint32_t); 90 static void e1000g_m_resources(void *); 91 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 92 static void e1000g_init_locks(struct e1000g *Adapter); 93 static void e1000g_destroy_locks(struct e1000g *Adapter); 94 static int e1000g_set_driver_params(struct e1000g *Adapter); 95 static int e1000g_register_mac(struct e1000g *Adapter); 96 static boolean_t e1000g_rx_drain(struct e1000g *Adapter); 97 static boolean_t e1000g_tx_drain(struct e1000g *Adapter); 98 static void e1000g_init_unicst(struct e1000g *Adapter); 99 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, mac_addr_slot_t); 100 101 /* 102 * Local routines 103 */ 104 static void e1000g_LocalTimer(void *); 105 static boolean_t e1000g_LocalTimerWork(struct e1000g *); 106 static boolean_t e1000g_stall_check(struct e1000g *); 107 static void e1000g_smartspeed(struct e1000g *); 108 static void e1000g_getparam(struct e1000g *Adapter); 109 static int e1000g_getprop(struct e1000g *, char *, int, int, int); 110 static void e1000g_error(dev_info_t *dip, char *fmt, char *a1, 111 char *a2, char *a3, char *a4, char *a5, char *a6); 112 static void enable_timeout(struct e1000g *Adapter); 113 static void disable_timeout(struct e1000g *Adapter); 114 static void start_timeout(struct e1000g *Adapter); 115 static void restart_timeout(struct e1000g *Adapter); 116 static void stop_timeout(struct e1000g *Adapter); 117 static void e1000g_force_speed_duplex(struct e1000g *Adapter); 118 static void e1000g_get_max_frame_size(struct e1000g *Adapter); 119 static boolean_t is_valid_mac_addr(uint8_t *mac_addr); 120 static void e1000g_unattach(dev_info_t *, struct e1000g *); 121 static void e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 122 static void e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 123 static void e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 124 static void e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 125 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *e1000gp, 126 struct iocblk *iocp, mblk_t *mp); 127 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *Adapter, 128 struct iocblk *iocp, mblk_t *mp); 129 static boolean_t e1000g_set_loopback_mode(struct e1000g *Adapter, 130 uint32_t mode); 131 static void e1000g_set_internal_loopback(struct e1000g *Adapter); 132 static void e1000g_set_external_loopback_1000(struct e1000g *Adapter); 133 static void e1000g_set_external_loopback_100(struct e1000g *Adapter); 134 static void e1000g_set_external_loopback_10(struct e1000g *Adapter); 135 static int e1000g_add_intrs(struct e1000g *Adapter); 136 static int e1000g_intr_add(struct e1000g *Adapter, int intr_type); 137 static int e1000g_rem_intrs(struct e1000g *Adapter); 138 static int e1000g_enable_intrs(struct e1000g *Adapter); 139 static int e1000g_disable_intrs(struct e1000g *Adapter); 140 static boolean_t e1000g_link_up(struct e1000g *Adapter); 141 #ifdef __sparc 142 static boolean_t e1000g_find_mac_address(struct e1000g *Adapter); 143 #endif 144 145 static struct cb_ops cb_ws_ops = { 146 nulldev, /* cb_open */ 147 nulldev, /* cb_close */ 148 nodev, /* cb_strategy */ 149 nodev, /* cb_print */ 150 nodev, /* cb_dump */ 151 nodev, /* cb_read */ 152 nodev, /* cb_write */ 153 nodev, /* cb_ioctl */ 154 nodev, /* cb_devmap */ 155 nodev, /* cb_mmap */ 156 nodev, /* cb_segmap */ 157 nochpoll, /* cb_chpoll */ 158 ddi_prop_op, /* cb_prop_op */ 159 NULL, /* cb_stream */ 160 D_MP | D_HOTPLUG, /* cb_flag */ 161 CB_REV, /* cb_rev */ 162 nodev, /* cb_aread */ 163 nodev /* cb_awrite */ 164 }; 165 166 static struct dev_ops ws_ops = { 167 DEVO_REV, /* devo_rev */ 168 0, /* devo_refcnt */ 169 NULL, /* devo_getinfo */ 170 nulldev, /* devo_identify */ 171 nulldev, /* devo_probe */ 172 e1000gattach, /* devo_attach */ 173 e1000gdetach, /* devo_detach */ 174 nodev, /* devo_reset */ 175 &cb_ws_ops, /* devo_cb_ops */ 176 NULL, /* devo_bus_ops */ 177 ddi_power /* devo_power */ 178 }; 179 180 static struct modldrv modldrv = { 181 &mod_driverops, /* Type of module. This one is a driver */ 182 ident, /* Discription string */ 183 &ws_ops, /* driver ops */ 184 }; 185 186 static struct modlinkage modlinkage = { 187 MODREV_1, &modldrv, NULL 188 }; 189 190 /* 191 * DMA access attributes <Little Endian Card> 192 */ 193 static ddi_device_acc_attr_t accattr1 = { 194 DDI_DEVICE_ATTR_V0, 195 DDI_STRUCTURE_LE_ACC, 196 DDI_STRICTORDER_ACC, 197 }; 198 199 #define E1000G_M_CALLBACK_FLAGS (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB) 200 201 static mac_callbacks_t e1000g_m_callbacks = { 202 E1000G_M_CALLBACK_FLAGS, 203 e1000g_m_stat, 204 e1000g_m_start, 205 e1000g_m_stop, 206 e1000g_m_promisc, 207 e1000g_m_multicst, 208 e1000g_m_unicst, 209 e1000g_m_tx, 210 e1000g_m_resources, 211 e1000g_m_ioctl, 212 e1000g_m_getcapab 213 }; 214 215 /* 216 * Global variables 217 */ 218 boolean_t force_detach_enabled = B_FALSE; 219 uint32_t e1000g_mblks_pending = 0; 220 /* 221 * The rwlock is defined to protect the whole processing of rx recycling 222 * and the rx packets release in detach processing to make them mutually 223 * exclusive. 224 * The rx recycling processes different rx packets in different threads, 225 * so it will be protected with RW_READER and it won't block any other rx 226 * recycling threads. 227 * While the detach processing will be protected with RW_WRITER to make 228 * it mutually exclusive with the rx recycling. 229 */ 230 krwlock_t e1000g_rx_detach_lock; 231 /* 232 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 233 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 234 * If there are many e1000g instances, the system may run out of DVMA 235 * resources during the initialization of the instances, then the flag will 236 * be changed to "USE_DMA". Because different e1000g instances are initialized 237 * in parallel, we need to use this lock to protect the flag. 238 */ 239 krwlock_t e1000g_dma_type_lock; 240 241 242 /* 243 * Loadable module configuration entry points for the driver 244 */ 245 246 /* 247 * ********************************************************************** 248 * Name: _init * 249 * * 250 * Description: * 251 * Initializes a loadable module. It is called before * 252 * any other routine in a loadable module. * 253 * All global locks are intialised here and it returns the retun * 254 * value from mod_install() * 255 * This is mandotary function for the driver * 256 * Parameter Passed: * 257 * None * 258 * Return Value: * 259 * 0 on success * 260 * Functions called * 261 * mod_install() (system call) * 262 * * 263 * ********************************************************************** 264 */ 265 int 266 _init(void) 267 { 268 int status; 269 270 mac_init_ops(&ws_ops, WSNAME); 271 status = mod_install(&modlinkage); 272 if (status != DDI_SUCCESS) 273 mac_fini_ops(&ws_ops); 274 else { 275 rw_init(&e1000g_rx_detach_lock, NULL, RW_DRIVER, NULL); 276 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 277 } 278 279 return (status); 280 } 281 282 /* 283 * ********************************************************************** 284 * Name: _fini * 285 * * 286 * Description: * 287 * Prepares a loadable module for unloading. It is * 288 * called when the system wants to unload a module. * 289 * This is mandotary function for the driver * 290 * Parameter Passed: * 291 * None * 292 * Return Value: * 293 * 0 on success * 294 * Functions called * 295 * mod_remove() (system call) * 296 * * 297 * * 298 * * 299 * ********************************************************************** 300 */ 301 int 302 _fini(void) 303 { 304 int status; 305 306 rw_enter(&e1000g_rx_detach_lock, RW_READER); 307 if (e1000g_mblks_pending != 0) { 308 rw_exit(&e1000g_rx_detach_lock); 309 return (EBUSY); 310 } 311 rw_exit(&e1000g_rx_detach_lock); 312 313 status = mod_remove(&modlinkage); 314 if (status == DDI_SUCCESS) { 315 mac_fini_ops(&ws_ops); 316 rw_destroy(&e1000g_rx_detach_lock); 317 rw_destroy(&e1000g_dma_type_lock); 318 } 319 320 return (status); 321 } 322 323 /* 324 * ********************************************************************** 325 * Name: _info * 326 * * 327 * Description: * 328 * Returns information about a loadable module. * 329 * This is mandotary function for the driver * 330 * Parameter Passed: * 331 * module info structure * 332 * Return Value: * 333 * 0 on success * 334 * Functions called * 335 * mod_info() (system call) * 336 * * 337 * * 338 * ********************************************************************** 339 */ 340 int 341 _info(struct modinfo *modinfop) 342 { 343 return (mod_info(&modlinkage, modinfop)); 344 } 345 346 /* 347 * Interface exists: make available by filling in network interface 348 * record. System will initialize the interface when it is ready 349 * to accept packets. 350 */ 351 352 /* 353 * ********************************************************************** 354 * Name: e1000gattach * 355 * * 356 * Description: * 357 * This function is the device-specific initialization * 358 * entry point. This entry point is required and must be writ- * 359 * ten. The DDI_ATTACH command must be provided in the attach * 360 * entry point. When attach() is called with cmd set to DDI_ATTACH, * 361 * all normal kernel services (such as kmem_alloc(9F)) are * 362 * available for use by the driver. Device interrupts are not * 363 * blocked when attaching a device to the system. * 364 * * 365 * The attach() function will be called once for each instance * 366 * of the device on the system with cmd set to DDI_ATTACH. * 367 * Until attach() succeeds, the only driver entry points which * 368 * may be called are open(9E) and getinfo(9E). * 369 * * 370 * * 371 * * 372 * Parameter Passed: * 373 * * 374 * Return Value: * 375 * * 376 * Functions called * 377 * * 378 * * 379 * ********************************************************************** 380 */ 381 static int 382 e1000gattach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 383 { 384 struct e1000g *Adapter; 385 struct e1000_hw *hw; 386 ddi_acc_handle_t handle; 387 off_t mem_size; 388 int instance; 389 390 switch (cmd) { 391 default: 392 e1000g_log(NULL, CE_WARN, 393 "Unsupported command send to e1000gattach... "); 394 return (DDI_FAILURE); 395 396 case DDI_RESUME: 397 return (e1000g_resume(devinfo)); 398 399 case DDI_ATTACH: 400 break; 401 } 402 403 /* 404 * get device instance number 405 */ 406 instance = ddi_get_instance(devinfo); 407 408 /* 409 * Allocate soft data structure 410 */ 411 Adapter = 412 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 413 414 Adapter->dip = devinfo; 415 Adapter->AdapterInstance = instance; 416 Adapter->tx_ring->adapter = Adapter; 417 Adapter->rx_ring->adapter = Adapter; 418 419 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 420 421 hw = &Adapter->Shared; 422 423 /* 424 * Map in the device registers. 425 * 426 * first get the size of device register to be mapped. The 427 * second parameter is the register we are interested. I our 428 * wiseman 0 is for config registers and 1 is for memory mapped 429 * registers Mem size should have memory mapped region size 430 */ 431 ddi_dev_regsize(devinfo, 1, /* register of interest */ 432 (off_t *)&mem_size); 433 434 if ((ddi_regs_map_setup(devinfo, 1, /* register of interest */ 435 (caddr_t *)&hw->hw_addr, 436 0, mem_size, &accattr1, &Adapter->E1000_handle)) 437 != DDI_SUCCESS) { 438 e1000g_log(Adapter, CE_WARN, "ddi_regs_map_setup failed"); 439 goto attach_fail; 440 } 441 Adapter->attach_progress |= ATTACH_PROGRESS_REGSMAPPED; 442 443 Adapter->osdep.E1000_handle = Adapter->E1000_handle; 444 hw->back = &Adapter->osdep; 445 446 /* 447 * PCI Configure 448 */ 449 if (pci_config_setup(devinfo, &handle) != DDI_SUCCESS) { 450 e1000g_log(Adapter, CE_WARN, 451 "PCI configuration could not be read."); 452 goto attach_fail; 453 } 454 455 Adapter->handle = handle; 456 Adapter->osdep.handle = handle; 457 458 hw->vendor_id = 459 pci_config_get16(handle, PCI_CONF_VENID); 460 hw->device_id = 461 pci_config_get16(handle, PCI_CONF_DEVID); 462 hw->revision_id = 463 pci_config_get8(handle, PCI_CONF_REVID); 464 hw->subsystem_id = 465 pci_config_get16(handle, PCI_CONF_SUBSYSID); 466 hw->subsystem_vendor_id = 467 pci_config_get16(handle, PCI_CONF_SUBVENID); 468 469 Adapter->attach_progress |= ATTACH_PROGRESS_PCICONFIG; 470 471 /* 472 * Initialize driver parameters 473 */ 474 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 475 goto attach_fail; 476 } 477 Adapter->attach_progress |= ATTACH_PROGRESS_PROP; 478 479 /* 480 * Initialize interrupts 481 */ 482 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 483 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 484 goto attach_fail; 485 } 486 Adapter->tx_softint_pri = DDI_INTR_SOFTPRI_MAX; 487 Adapter->attach_progress |= ATTACH_PROGRESS_INTRADDED; 488 489 /* 490 * Initialize mutex's for this device. 491 * Do this before enabling the interrupt handler and 492 * register the softint to avoid the condition where 493 * interrupt handler can try using uninitialized mutex 494 */ 495 e1000g_init_locks(Adapter); 496 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 497 498 if (ddi_intr_add_softint(devinfo, 499 &Adapter->tx_softint_handle, Adapter->tx_softint_pri, 500 e1000g_tx_freemsg, (caddr_t)Adapter) != DDI_SUCCESS) { 501 e1000g_log(Adapter, CE_WARN, "Add soft intr failed"); 502 goto attach_fail; 503 } 504 Adapter->attach_progress |= ATTACH_PROGRESS_SOFTINTR; 505 506 /* 507 * Initialize Driver Counters 508 */ 509 if (InitStatsCounters(Adapter) != DDI_SUCCESS) { 510 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 511 goto attach_fail; 512 } 513 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 514 515 /* 516 * Allocate dma resources for descriptors and buffers 517 */ 518 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 519 e1000g_log(Adapter, CE_WARN, "Alloc dma resources failed"); 520 goto attach_fail; 521 } 522 Adapter->attach_progress |= ATTACH_PROGRESS_ALLOC; 523 524 /* 525 * Initialize chip hardware and software structures 526 */ 527 if (e1000g_init(Adapter) != DDI_SUCCESS) { 528 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 529 goto attach_fail; 530 } 531 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 532 533 /* 534 * Initialize NDD parameters 535 */ 536 if (e1000g_nd_init(Adapter) != DDI_SUCCESS) { 537 e1000g_log(Adapter, CE_WARN, "Init NDD failed"); 538 goto attach_fail; 539 } 540 Adapter->attach_progress |= ATTACH_PROGRESS_NDD; 541 542 /* 543 * Register the driver to the MAC 544 */ 545 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 546 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 547 goto attach_fail; 548 } 549 Adapter->attach_progress |= ATTACH_PROGRESS_MACREGISTERED; 550 551 /* 552 * Now that mutex locks are initialized, and the chip is also 553 * initialized, enable interrupts. 554 */ 555 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 556 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 557 goto attach_fail; 558 } 559 Adapter->attach_progress |= ATTACH_PROGRESS_INTRENABLED; 560 561 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 562 563 /* 564 * Tell the world about the link state of e1000g 565 */ 566 mac_link_update(Adapter->mh, 567 (Adapter->LinkIsActive) ? LINK_STATE_UP : LINK_STATE_DOWN); 568 569 return (DDI_SUCCESS); 570 571 attach_fail: 572 e1000g_unattach(devinfo, Adapter); 573 return (DDI_FAILURE); 574 } 575 576 static int 577 e1000g_register_mac(struct e1000g *Adapter) 578 { 579 struct e1000_hw *hw = &Adapter->Shared; 580 mac_register_t *mac; 581 int err; 582 583 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 584 return (DDI_FAILURE); 585 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 586 mac->m_driver = Adapter; 587 mac->m_dip = Adapter->dip; 588 mac->m_src_addr = hw->mac_addr; 589 mac->m_callbacks = &e1000g_m_callbacks; 590 mac->m_min_sdu = 0; 591 mac->m_max_sdu = 592 (hw->max_frame_size > FRAME_SIZE_UPTO_8K) ? 593 hw->max_frame_size - 256 : 594 (hw->max_frame_size != ETHERMAX) ? 595 hw->max_frame_size - 24 : ETHERMTU; 596 err = mac_register(mac, &Adapter->mh); 597 mac_free(mac); 598 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 599 } 600 601 static int 602 e1000g_set_driver_params(struct e1000g *Adapter) 603 { 604 dev_info_t *devinfo; 605 ddi_acc_handle_t handle; 606 struct e1000_hw *hw; 607 uint32_t mem_bar, io_bar; 608 #ifdef __sparc 609 ulong_t iommu_pagesize; 610 #endif 611 612 devinfo = Adapter->dip; 613 handle = Adapter->handle; 614 hw = &Adapter->Shared; 615 616 /* Set Mac Type */ 617 if (e1000_set_mac_type(hw) != 0) { 618 e1000g_log(Adapter, CE_WARN, 619 "Could not identify hardware"); 620 return (DDI_FAILURE); 621 } 622 623 /* ich8 needs to map flash memory */ 624 if (hw->mac_type == e1000_ich8lan) { 625 /* get flash size */ 626 if (ddi_dev_regsize(devinfo, ICH_FLASH_REG_SET, 627 &Adapter->osdep.ich_flash_size) != DDI_SUCCESS) { 628 e1000g_log(Adapter, CE_WARN, 629 "ddi_dev_regsize for ich8 flash failed"); 630 return (DDI_FAILURE); 631 } 632 633 /* map flash in */ 634 if (ddi_regs_map_setup(devinfo, ICH_FLASH_REG_SET, 635 &Adapter->osdep.ich_flash_base, 0, 636 Adapter->osdep.ich_flash_size, 637 &accattr1, 638 &Adapter->osdep.ich_flash_handle) != DDI_SUCCESS) { 639 e1000g_log(Adapter, CE_WARN, 640 "ddi_regs_map_setup for for ich8 flash failed"); 641 return (DDI_FAILURE); 642 } 643 } 644 645 /* get mem_base addr */ 646 mem_bar = pci_config_get32(handle, PCI_CONF_BASE0); 647 Adapter->bar64 = mem_bar & PCI_BASE_TYPE_ALL; 648 649 /* get io_base addr */ 650 if (hw->mac_type >= e1000_82544) { 651 if (Adapter->bar64) { 652 /* IO BAR is different for 64 bit BAR mode */ 653 io_bar = pci_config_get32(handle, PCI_CONF_BASE4); 654 } else { 655 /* normal 32-bit BAR mode */ 656 io_bar = pci_config_get32(handle, PCI_CONF_BASE2); 657 } 658 hw->io_base = io_bar & PCI_BASE_IO_ADDR_M; 659 } else { 660 /* no I/O access for adapters prior to 82544 */ 661 hw->io_base = 0x0; 662 } 663 664 e1000_read_pci_cfg(hw, 665 PCI_COMMAND_REGISTER, &(hw->pci_cmd_word)); 666 667 /* Set the wait_autoneg_complete flag to B_FALSE */ 668 hw->wait_autoneg_complete = B_FALSE; 669 670 /* Adaptive IFS related changes */ 671 hw->adaptive_ifs = B_TRUE; 672 673 /* set phy init script revision */ 674 if ((hw->mac_type == e1000_82547) || 675 (hw->mac_type == e1000_82541) || 676 (hw->mac_type == e1000_82547_rev_2) || 677 (hw->mac_type == e1000_82541_rev_2)) 678 hw->phy_init_script = 1; 679 680 /* Enable the TTL workaround for TnT: DCR 49 */ 681 hw->ttl_wa_activation = 1; 682 683 if (hw->mac_type == e1000_82571) 684 hw->laa_is_present = B_TRUE; 685 686 /* Get conf file properties */ 687 e1000g_getparam(Adapter); 688 689 e1000g_force_speed_duplex(Adapter); 690 691 e1000g_get_max_frame_size(Adapter); 692 hw->min_frame_size = 693 MINIMUM_ETHERNET_PACKET_SIZE + CRC_LENGTH; 694 695 #ifdef __sparc 696 /* Get the system page size */ 697 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 698 iommu_pagesize = dvma_pagesize(devinfo); 699 if (iommu_pagesize != 0) { 700 if (Adapter->sys_page_sz == iommu_pagesize) { 701 if (iommu_pagesize > 0x4000) 702 Adapter->sys_page_sz = 0x4000; 703 } else { 704 if (Adapter->sys_page_sz > iommu_pagesize) 705 Adapter->sys_page_sz = iommu_pagesize; 706 } 707 } 708 Adapter->dvma_page_num = hw->max_frame_size / 709 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 710 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 711 #endif 712 713 /* Set Rx/Tx buffer size */ 714 switch (hw->max_frame_size) { 715 case ETHERMAX: 716 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 717 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 718 break; 719 case FRAME_SIZE_UPTO_4K: 720 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_4K; 721 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_4K; 722 break; 723 case FRAME_SIZE_UPTO_8K: 724 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_8K; 725 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_8K; 726 break; 727 case FRAME_SIZE_UPTO_10K: 728 case FRAME_SIZE_UPTO_16K: 729 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_16K; 730 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_16K; 731 break; 732 default: 733 Adapter->RxBufferSize = E1000_RX_BUFFER_SIZE_2K; 734 Adapter->TxBufferSize = E1000_TX_BUFFER_SIZE_2K; 735 break; 736 } 737 Adapter->RxBufferSize += E1000G_IPALIGNPRESERVEROOM; 738 739 /* 740 * For Wiseman adapters we have an requirement of having receive 741 * buffers aligned at 256 byte boundary. Since Livengood does not 742 * require this and forcing it for all hardwares will have 743 * performance implications, I am making it applicable only for 744 * Wiseman and for Jumbo frames enabled mode as rest of the time, 745 * it is okay to have normal frames...but it does involve a 746 * potential risk where we may loose data if buffer is not 747 * aligned...so all wiseman boards to have 256 byte aligned 748 * buffers 749 */ 750 if (hw->mac_type < e1000_82543) 751 Adapter->RcvBufferAlignment = RECEIVE_BUFFER_ALIGN_SIZE; 752 else 753 /* 754 * For livengood, there is no such Rcv buf alignment 755 * requirement 756 */ 757 Adapter->RcvBufferAlignment = 1; 758 759 /* DmaFairness */ 760 if (hw->mac_type <= e1000_82543) 761 hw->dma_fairness = DEFAULTRXPCIPRIORITYVAL; 762 else 763 hw->dma_fairness = 0; 764 765 /* MasterLatencyTimer */ 766 Adapter->MasterLatencyTimer = DEFAULTMASTERLATENCYTIMERVAL; 767 768 /* MWIEnable */ 769 Adapter->MWIEnable = DEFAULTMWIENABLEVAL; 770 771 /* profile jumbo traffic */ 772 Adapter->ProfileJumboTraffic = DEFAULTPROFILEJUMBOTRAFFIC; 773 774 e1000_set_media_type(hw); 775 /* copper options */ 776 if (hw->media_type == e1000_media_type_copper) { 777 hw->mdix = 0; /* AUTO_ALL_MODES */ 778 hw->disable_polarity_correction = B_FALSE; 779 hw->master_slave = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 780 } 781 782 return (DDI_SUCCESS); 783 } 784 785 /* 786 * ********************************************************************** 787 * Name: e1000gdettach * 788 * * 789 * Description: * 790 * The detach() function is the complement of the attach routine. * 791 * If cmd is set to DDI_DETACH, detach() is used to remove the * 792 * state associated with a given instance of a device node * 793 * prior to the removal of that instance from the system. * 794 * * 795 * The detach() function will be called once for each instance * 796 * of the device for which there has been a successful attach() * 797 * once there are no longer any opens on the device. * 798 * * 799 * Interrupts routine are disabled, All memory allocated by this * 800 * driver are freed. * 801 * * 802 * Parameter Passed: * 803 * devinfo structure, cmd * 804 * * 805 * Return Value: * 806 * DDI_SUCCESS on success * 807 * * 808 * Functions called * 809 * * 810 * * 811 * ********************************************************************** 812 */ 813 static int 814 e1000gdetach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 815 { 816 struct e1000g *Adapter; 817 818 switch (cmd) { 819 default: 820 return (DDI_FAILURE); 821 822 case DDI_SUSPEND: 823 return (e1000g_suspend(devinfo)); 824 825 case DDI_DETACH: 826 break; 827 } 828 829 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 830 if (Adapter == NULL) 831 return (DDI_FAILURE); 832 833 if (Adapter->started) 834 e1000g_stop(Adapter); 835 836 if (!e1000g_rx_drain(Adapter)) { 837 if (!force_detach_enabled) 838 return (DDI_FAILURE); 839 } 840 841 if (e1000g_disable_intrs(Adapter) != DDI_SUCCESS) { 842 e1000g_log(Adapter, CE_WARN, 843 "Disable DDI interrupts failed"); 844 return (DDI_FAILURE); 845 } 846 Adapter->attach_progress &= ~ATTACH_PROGRESS_INTRENABLED; 847 848 if (mac_unregister(Adapter->mh) != 0) { 849 e1000g_log(Adapter, CE_WARN, 850 "Unregister MAC failed"); 851 return (DDI_FAILURE); 852 } 853 Adapter->attach_progress &= ~ATTACH_PROGRESS_MACREGISTERED; 854 855 e1000g_unattach(devinfo, Adapter); 856 857 return (DDI_SUCCESS); 858 } 859 860 static void 861 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 862 { 863 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRENABLED) { 864 (void) e1000g_disable_intrs(Adapter); 865 } 866 867 if (Adapter->attach_progress & ATTACH_PROGRESS_MACREGISTERED) { 868 (void) mac_unregister(Adapter->mh); 869 } 870 871 if (Adapter->attach_progress & ATTACH_PROGRESS_NDD) { 872 e1000g_nd_cleanup(Adapter); 873 } 874 875 if (Adapter->attach_progress & ATTACH_PROGRESS_INTRADDED) { 876 (void) e1000g_rem_intrs(Adapter); 877 } 878 879 if (Adapter->attach_progress & ATTACH_PROGRESS_SOFTINTR) { 880 (void) ddi_intr_remove_softint(Adapter->tx_softint_handle); 881 } 882 883 if (Adapter->attach_progress & ATTACH_PROGRESS_PROP) { 884 (void) ddi_prop_remove_all(devinfo); 885 } 886 887 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 888 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 889 } 890 891 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 892 e1000_reset_hw(&Adapter->Shared); 893 } 894 895 if (Adapter->attach_progress & ATTACH_PROGRESS_REGSMAPPED) { 896 ddi_regs_map_free(&Adapter->E1000_handle); 897 } 898 899 if (Adapter->attach_progress & ATTACH_PROGRESS_PCICONFIG) { 900 pci_config_teardown(&Adapter->handle); 901 } 902 903 if (Adapter->attach_progress & ATTACH_PROGRESS_ALLOC) { 904 e1000g_release_dma_resources(Adapter); 905 } 906 907 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 908 e1000g_destroy_locks(Adapter); 909 } 910 911 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 912 913 /* 914 * Another hotplug spec requirement, 915 * run ddi_set_driver_private(devinfo, null); 916 */ 917 ddi_set_driver_private(devinfo, NULL); 918 } 919 920 static void 921 e1000g_init_locks(struct e1000g *Adapter) 922 { 923 e1000g_tx_ring_t *tx_ring; 924 e1000g_rx_ring_t *rx_ring; 925 926 rw_init(&Adapter->chip_lock, NULL, 927 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 928 mutex_init(&Adapter->e1000g_linklock, NULL, 929 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 930 mutex_init(&Adapter->e1000g_timeout_lock, NULL, 931 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 932 mutex_init(&Adapter->TbiCntrMutex, NULL, 933 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 934 935 mutex_init(&Adapter->tx_msg_chain->lock, NULL, 936 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->tx_softint_pri)); 937 938 tx_ring = Adapter->tx_ring; 939 940 mutex_init(&tx_ring->tx_lock, NULL, 941 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 942 mutex_init(&tx_ring->usedlist_lock, NULL, 943 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 944 mutex_init(&tx_ring->freelist_lock, NULL, 945 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 946 947 rx_ring = Adapter->rx_ring; 948 949 mutex_init(&rx_ring->rx_lock, NULL, 950 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 951 mutex_init(&rx_ring->freelist_lock, NULL, 952 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 953 } 954 955 static void 956 e1000g_destroy_locks(struct e1000g *Adapter) 957 { 958 e1000g_tx_ring_t *tx_ring; 959 e1000g_rx_ring_t *rx_ring; 960 961 tx_ring = Adapter->tx_ring; 962 mutex_destroy(&tx_ring->tx_lock); 963 mutex_destroy(&tx_ring->usedlist_lock); 964 mutex_destroy(&tx_ring->freelist_lock); 965 966 rx_ring = Adapter->rx_ring; 967 mutex_destroy(&rx_ring->rx_lock); 968 mutex_destroy(&rx_ring->freelist_lock); 969 970 mutex_destroy(&Adapter->tx_msg_chain->lock); 971 mutex_destroy(&Adapter->e1000g_linklock); 972 mutex_destroy(&Adapter->TbiCntrMutex); 973 mutex_destroy(&Adapter->e1000g_timeout_lock); 974 rw_destroy(&Adapter->chip_lock); 975 } 976 977 static int 978 e1000g_resume(dev_info_t *devinfo) 979 { 980 struct e1000g *Adapter; 981 982 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 983 if (Adapter == NULL) 984 return (DDI_FAILURE); 985 986 if (e1000g_start(Adapter)) 987 return (DDI_FAILURE); 988 989 return (DDI_SUCCESS); 990 } 991 992 static int 993 e1000g_suspend(dev_info_t *devinfo) 994 { 995 struct e1000g *Adapter; 996 997 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 998 if (Adapter == NULL) 999 return (DDI_FAILURE); 1000 1001 e1000g_stop(Adapter); 1002 1003 return (DDI_SUCCESS); 1004 } 1005 1006 static int 1007 e1000g_init(struct e1000g *Adapter) 1008 { 1009 UINT16 LineSpeed, Duplex; 1010 uint32_t pba; 1011 uint32_t ctrl; 1012 struct e1000_hw *hw; 1013 1014 hw = &Adapter->Shared; 1015 1016 rw_enter(&Adapter->chip_lock, RW_WRITER); 1017 1018 /* Preserve manageability features */ 1019 e1000_check_phy_reset_block(hw); 1020 1021 /* 1022 * reset to put the hardware in a known state 1023 * before we try to do anything with the eeprom 1024 */ 1025 (void) e1000_reset_hw(hw); 1026 1027 (void) e1000_init_eeprom_params(hw); 1028 1029 if (e1000_validate_eeprom_checksum(hw) < 0) { 1030 e1000g_log(Adapter, CE_WARN, "Eeprom checksum failed"); 1031 goto init_fail; 1032 } 1033 1034 #ifdef __sparc 1035 /* 1036 * Firstly, we try to get the local ethernet address from OBP. If 1037 * fail, we get from EEPROM of NIC card. 1038 */ 1039 if (!e1000g_find_mac_address(Adapter)) { 1040 if (e1000_read_mac_addr(hw) < 0) { 1041 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1042 goto init_fail; 1043 } 1044 } 1045 #else 1046 /* Get the local ethernet address. */ 1047 if (e1000_read_mac_addr(hw) < 0) { 1048 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1049 goto init_fail; 1050 } 1051 #endif 1052 1053 /* check for valid mac address */ 1054 if (!is_valid_mac_addr(hw->mac_addr)) { 1055 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1056 goto init_fail; 1057 } 1058 1059 e1000_get_bus_info(hw); 1060 1061 /* Master Latency Timer implementation */ 1062 if (Adapter->MasterLatencyTimer) { 1063 pci_config_put8(Adapter->handle, PCI_CONF_LATENCY_TIMER, 1064 Adapter->MasterLatencyTimer); 1065 } 1066 1067 if (hw->mac_type < e1000_82547) { 1068 /* 1069 * Total FIFO is 64K 1070 */ 1071 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1072 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1073 else 1074 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1075 } else if (hw->mac_type >= e1000_82571 && 1076 hw->mac_type <= e1000_82572) { 1077 /* 1078 * Total FIFO is 48K 1079 */ 1080 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1081 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1082 else 1083 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1084 } else if (hw->mac_type == e1000_ich8lan) { 1085 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1086 } else { 1087 /* 1088 * Total FIFO is 40K 1089 */ 1090 if (hw->max_frame_size > FRAME_SIZE_UPTO_8K) 1091 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1092 else 1093 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1094 } 1095 E1000_WRITE_REG(hw, PBA, pba); 1096 1097 /* 1098 * These parameters set thresholds for the adapter's generation(Tx) 1099 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1100 * settings. Flow control is enabled or disabled in the configuration 1101 * file. 1102 * High-water mark is set down from the top of the rx fifo (not 1103 * sensitive to max_frame_size) and low-water is set just below 1104 * high-water mark. 1105 */ 1106 hw->fc_high_water = 1107 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1108 E1000_FC_HIGH_DIFF; 1109 hw->fc_low_water = 1110 ((pba & E1000_PBA_MASK) << E1000_PBA_SHIFT) - 1111 E1000_FC_LOW_DIFF; 1112 hw->fc_pause_time = E1000_FC_PAUSE_TIME; 1113 hw->fc_send_xon = B_TRUE; 1114 1115 /* 1116 * Reset the adapter hardware the second time. 1117 */ 1118 (void) e1000_reset_hw(hw); 1119 1120 /* disable wakeup control by default */ 1121 if (hw->mac_type >= e1000_82544) 1122 E1000_WRITE_REG(hw, WUC, 0); 1123 1124 /* MWI setup */ 1125 if (Adapter->MWIEnable) { 1126 hw->pci_cmd_word |= CMD_MEM_WRT_INVALIDATE; 1127 e1000_pci_set_mwi(hw); 1128 } else 1129 e1000_pci_clear_mwi(hw); 1130 1131 /* 1132 * Configure/Initialize hardware 1133 */ 1134 if (e1000_init_hw(hw) < 0) { 1135 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1136 goto init_fail; 1137 } 1138 1139 /* Disable Smart Power Down */ 1140 phy_spd_state(hw, B_FALSE); 1141 1142 /* 1143 * Initialize unicast addresses. 1144 */ 1145 e1000g_init_unicst(Adapter); 1146 1147 /* 1148 * Setup and initialize the transmit structures. 1149 */ 1150 SetupTransmitStructures(Adapter); 1151 DelayInMilliseconds(5); 1152 1153 /* 1154 * Setup and initialize the mctable structures. After this routine 1155 * completes Multicast table will be set 1156 */ 1157 SetupMulticastTable(Adapter); 1158 DelayInMilliseconds(5); 1159 1160 /* 1161 * Setup and initialize the receive structures. After this routine 1162 * completes we can receive packets off of the wire. 1163 */ 1164 SetupReceiveStructures(Adapter); 1165 DelayInMilliseconds(5); 1166 1167 /* 1168 * Implement Adaptive IFS 1169 */ 1170 e1000_reset_adaptive(hw); 1171 1172 /* Setup Interrupt Throttling Register */ 1173 E1000_WRITE_REG(hw, ITR, Adapter->intr_throttling_rate); 1174 1175 /* 1176 * Check for link status 1177 */ 1178 if (e1000g_link_up(Adapter)) { 1179 e1000_get_speed_and_duplex(hw, &LineSpeed, &Duplex); 1180 Adapter->link_speed = LineSpeed; 1181 Adapter->link_duplex = Duplex; 1182 Adapter->LinkIsActive = B_TRUE; 1183 } else { 1184 Adapter->link_speed = 0; 1185 Adapter->link_duplex = 0; 1186 Adapter->LinkIsActive = B_FALSE; 1187 } 1188 1189 /* Enable PCI-Ex master */ 1190 if (hw->bus_type == e1000_bus_type_pci_express) { 1191 e1000_enable_pciex_master(hw); 1192 } 1193 1194 Adapter->init_count++; 1195 1196 rw_exit(&Adapter->chip_lock); 1197 1198 return (DDI_SUCCESS); 1199 1200 init_fail: 1201 rw_exit(&Adapter->chip_lock); 1202 return (DDI_FAILURE); 1203 } 1204 1205 /* 1206 * Check if the link is up 1207 */ 1208 static boolean_t 1209 e1000g_link_up(struct e1000g *Adapter) 1210 { 1211 struct e1000_hw *hw; 1212 boolean_t link_up; 1213 1214 hw = &Adapter->Shared; 1215 1216 /* Ensure this is set to get accurate copper link status */ 1217 hw->get_link_status = B_TRUE; 1218 1219 e1000_check_for_link(hw); 1220 1221 if ((E1000_READ_REG(hw, STATUS) & E1000_STATUS_LU) || 1222 ((!hw->get_link_status) && (hw->mac_type == e1000_82543)) || 1223 ((hw->media_type == e1000_media_type_internal_serdes) && 1224 (!hw->serdes_link_down))) { 1225 link_up = B_TRUE; 1226 } else { 1227 link_up = B_FALSE; 1228 } 1229 1230 return (link_up); 1231 } 1232 1233 static void 1234 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1235 { 1236 struct iocblk *iocp; 1237 struct e1000g *e1000gp; 1238 enum ioc_reply status; 1239 int err; 1240 1241 iocp = (struct iocblk *)mp->b_rptr; 1242 iocp->ioc_error = 0; 1243 e1000gp = (struct e1000g *)arg; 1244 1245 ASSERT(e1000gp); 1246 if (e1000gp == NULL) { 1247 miocnak(q, mp, 0, EINVAL); 1248 return; 1249 } 1250 1251 switch (iocp->ioc_cmd) { 1252 1253 case LB_GET_INFO_SIZE: 1254 case LB_GET_INFO: 1255 case LB_GET_MODE: 1256 case LB_SET_MODE: 1257 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1258 break; 1259 1260 case ND_GET: 1261 case ND_SET: 1262 status = e1000g_nd_ioctl(e1000gp, q, mp, iocp); 1263 break; 1264 1265 case E1000G_IOC_REG_PEEK: 1266 case E1000G_IOC_REG_POKE: 1267 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1268 break; 1269 case E1000G_IOC_CHIP_RESET: 1270 e1000gp->reset_count++; 1271 if (e1000g_reset(e1000gp)) 1272 status = IOC_ACK; 1273 else 1274 status = IOC_INVAL; 1275 break; 1276 default: 1277 status = IOC_INVAL; 1278 break; 1279 } 1280 1281 /* 1282 * Decide how to reply 1283 */ 1284 switch (status) { 1285 default: 1286 case IOC_INVAL: 1287 /* 1288 * Error, reply with a NAK and EINVAL or the specified error 1289 */ 1290 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1291 EINVAL : iocp->ioc_error); 1292 break; 1293 1294 case IOC_DONE: 1295 /* 1296 * OK, reply already sent 1297 */ 1298 break; 1299 1300 case IOC_ACK: 1301 /* 1302 * OK, reply with an ACK 1303 */ 1304 miocack(q, mp, 0, 0); 1305 break; 1306 1307 case IOC_REPLY: 1308 /* 1309 * OK, send prepared reply as ACK or NAK 1310 */ 1311 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1312 M_IOCACK : M_IOCNAK; 1313 qreply(q, mp); 1314 break; 1315 } 1316 } 1317 1318 static void e1000g_m_blank(void *arg, time_t ticks, uint32_t count) 1319 { 1320 struct e1000g *Adapter; 1321 1322 Adapter = (struct e1000g *)arg; 1323 1324 /* 1325 * Adjust ITR (Interrupt Throttling Register) to coalesce 1326 * interrupts. This formula and its coefficient come from 1327 * our experiments. 1328 */ 1329 if (Adapter->intr_adaptive) { 1330 Adapter->intr_throttling_rate = count << 5; 1331 E1000_WRITE_REG(&Adapter->Shared, ITR, 1332 Adapter->intr_throttling_rate); 1333 } 1334 } 1335 1336 static void 1337 e1000g_m_resources(void *arg) 1338 { 1339 struct e1000g *adapter = (struct e1000g *)arg; 1340 mac_rx_fifo_t mrf; 1341 1342 mrf.mrf_type = MAC_RX_FIFO; 1343 mrf.mrf_blank = e1000g_m_blank; 1344 mrf.mrf_arg = (void *)adapter; 1345 mrf.mrf_normal_blank_time = E1000_RX_INTPT_TIME; 1346 mrf.mrf_normal_pkt_count = E1000_RX_PKT_CNT; 1347 1348 adapter->mrh = mac_resource_add(adapter->mh, (mac_resource_t *)&mrf); 1349 } 1350 1351 static int 1352 e1000g_m_start(void *arg) 1353 { 1354 struct e1000g *Adapter = (struct e1000g *)arg; 1355 1356 return (e1000g_start(Adapter)); 1357 } 1358 1359 static int 1360 e1000g_start(struct e1000g *Adapter) 1361 { 1362 /* 1363 * We set Adapter->PseudoLinkChanged here, so that e1000g_LocalTimer 1364 * will tell the upper network modules about the link state of e1000g 1365 */ 1366 Adapter->PseudoLinkChanged = B_TRUE; 1367 1368 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1369 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1370 e1000g_log(Adapter, CE_WARN, 1371 "Adapter initialization failed"); 1372 return (ENOTACTIVE); 1373 } 1374 } 1375 1376 enable_timeout(Adapter); 1377 1378 rw_enter(&Adapter->chip_lock, RW_WRITER); 1379 1380 e1000g_EnableInterrupt(Adapter); 1381 if (Adapter->tx_intr_enable) 1382 e1000g_EnableTxInterrupt(Adapter); 1383 1384 Adapter->started = B_TRUE; 1385 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1386 1387 rw_exit(&Adapter->chip_lock); 1388 1389 return (0); 1390 } 1391 1392 static void 1393 e1000g_m_stop(void *arg) 1394 { 1395 struct e1000g *Adapter = (struct e1000g *)arg; 1396 1397 e1000g_stop(Adapter); 1398 } 1399 1400 static void 1401 e1000g_stop(struct e1000g *Adapter) 1402 { 1403 PTX_SW_PACKET packet; 1404 timeout_id_t tid; 1405 e1000g_tx_ring_t *tx_ring; 1406 e1000g_msg_chain_t *msg_chain; 1407 mblk_t *mp; 1408 mblk_t *nmp; 1409 1410 tx_ring = Adapter->tx_ring; 1411 1412 /* Set stop flags */ 1413 rw_enter(&Adapter->chip_lock, RW_WRITER); 1414 1415 Adapter->started = B_FALSE; 1416 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1417 1418 rw_exit(&Adapter->chip_lock); 1419 1420 /* Drain tx sessions */ 1421 (void) e1000g_tx_drain(Adapter); 1422 1423 /* Disable timers */ 1424 disable_timeout(Adapter); 1425 1426 mutex_enter(&tx_ring->tx_lock); 1427 1428 tx_ring->timer_enable_82547 = B_FALSE; 1429 tid = tx_ring->timer_id_82547; 1430 tx_ring->timer_id_82547 = 0; 1431 1432 mutex_exit(&tx_ring->tx_lock); 1433 1434 if (tid != 0) 1435 (void) untimeout(tid); 1436 1437 /* Stop the chip and release pending resources */ 1438 rw_enter(&Adapter->chip_lock, RW_WRITER); 1439 1440 e1000g_DisableAllInterrupts(Adapter); 1441 1442 e1000_reset_hw(&Adapter->Shared); 1443 1444 /* Release resources still held by the TX descriptors */ 1445 /* 1446 * Here we don't need to protect the lists using 1447 * the usedlist_lock and freelist_lock, for they 1448 * have been protected by the chip_lock. 1449 */ 1450 mp = NULL; 1451 nmp = NULL; 1452 packet = (PTX_SW_PACKET) QUEUE_GET_HEAD(&tx_ring->used_list); 1453 while (packet != NULL) { 1454 if (packet->mp != NULL) { 1455 /* Assemble the message chain */ 1456 if (mp == NULL) { 1457 mp = packet->mp; 1458 nmp = packet->mp; 1459 } else { 1460 nmp->b_next = packet->mp; 1461 nmp = packet->mp; 1462 } 1463 /* Disconnect the message from the sw packet */ 1464 packet->mp = NULL; 1465 } 1466 1467 FreeTxSwPacket(packet); 1468 1469 packet = (PTX_SW_PACKET) 1470 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 1471 } 1472 1473 if (mp != NULL) { 1474 msg_chain = Adapter->tx_msg_chain; 1475 mutex_enter(&msg_chain->lock); 1476 if (msg_chain->head == NULL) { 1477 msg_chain->head = mp; 1478 msg_chain->tail = nmp; 1479 } else { 1480 msg_chain->tail->b_next = mp; 1481 msg_chain->tail = nmp; 1482 } 1483 mutex_exit(&msg_chain->lock); 1484 } 1485 1486 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 1487 QUEUE_INIT_LIST(&tx_ring->used_list); 1488 1489 /* Clean the pending rx jumbo packet fragment */ 1490 if (Adapter->rx_mblk != NULL) { 1491 freemsg(Adapter->rx_mblk); 1492 Adapter->rx_mblk = NULL; 1493 Adapter->rx_mblk_tail = NULL; 1494 Adapter->rx_packet_len = 0; 1495 } 1496 1497 rw_exit(&Adapter->chip_lock); 1498 1499 (void) e1000g_tx_freemsg((caddr_t)Adapter, NULL); 1500 } 1501 1502 static boolean_t 1503 e1000g_tx_drain(struct e1000g *Adapter) 1504 { 1505 int i; 1506 boolean_t done; 1507 e1000g_tx_ring_t *tx_ring; 1508 1509 tx_ring = Adapter->tx_ring; 1510 1511 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 1512 for (i = 0; i < WSDRAINTIME; i++) { 1513 mutex_enter(&tx_ring->usedlist_lock); 1514 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 1515 mutex_exit(&tx_ring->usedlist_lock); 1516 1517 if (done) 1518 break; 1519 1520 msec_delay(1); 1521 } 1522 1523 return (done); 1524 } 1525 1526 static boolean_t 1527 e1000g_rx_drain(struct e1000g *Adapter) 1528 { 1529 boolean_t done; 1530 1531 mutex_enter(&Adapter->rx_ring->freelist_lock); 1532 done = (Adapter->rx_avail_freepkt == Adapter->NumRxFreeList); 1533 mutex_exit(&Adapter->rx_ring->freelist_lock); 1534 1535 return (done); 1536 } 1537 1538 static boolean_t 1539 e1000g_reset(struct e1000g *Adapter) 1540 { 1541 e1000g_stop(Adapter); 1542 1543 if (e1000g_start(Adapter)) { 1544 e1000g_log(Adapter, CE_WARN, "Reset failed"); 1545 return (B_FALSE); 1546 } 1547 1548 return (B_TRUE); 1549 } 1550 1551 /* 1552 * ********************************************************************** 1553 * Name: e1000g_intr_pciexpress * 1554 * * 1555 * Description: * 1556 * This interrupt service routine is for PCI-Express adapters. * 1557 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED * 1558 * bit is set. * 1559 * * 1560 * Parameter Passed: * 1561 * * 1562 * Return Value: * 1563 * * 1564 * Functions called: * 1565 * e1000g_intr_work * 1566 * * 1567 * ********************************************************************** 1568 */ 1569 static uint_t 1570 e1000g_intr_pciexpress(caddr_t arg) 1571 { 1572 struct e1000g *Adapter; 1573 uint32_t ICRContents; 1574 1575 Adapter = (struct e1000g *)arg; 1576 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1577 1578 if (ICRContents & E1000_ICR_INT_ASSERTED) { 1579 /* 1580 * E1000_ICR_INT_ASSERTED bit was set: 1581 * Read(Clear) the ICR, claim this interrupt, 1582 * look for work to do. 1583 */ 1584 e1000g_intr_work(Adapter, ICRContents); 1585 return (DDI_INTR_CLAIMED); 1586 } else { 1587 /* 1588 * E1000_ICR_INT_ASSERTED bit was not set: 1589 * Don't claim this interrupt, return immediately. 1590 */ 1591 return (DDI_INTR_UNCLAIMED); 1592 } 1593 } 1594 1595 /* 1596 * ********************************************************************** 1597 * Name: e1000g_intr * 1598 * * 1599 * Description: * 1600 * This interrupt service routine is for PCI/PCI-X adapters. * 1601 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED * 1602 * bit is set or not. * 1603 * * 1604 * Parameter Passed: * 1605 * * 1606 * Return Value: * 1607 * * 1608 * Functions called: * 1609 * e1000g_intr_work * 1610 * * 1611 * ********************************************************************** 1612 */ 1613 static uint_t 1614 e1000g_intr(caddr_t arg) 1615 { 1616 struct e1000g *Adapter; 1617 uint32_t ICRContents; 1618 1619 Adapter = (struct e1000g *)arg; 1620 ICRContents = E1000_READ_REG(&Adapter->Shared, ICR); 1621 1622 if (ICRContents) { 1623 /* 1624 * Any bit was set in ICR: 1625 * Read(Clear) the ICR, claim this interrupt, 1626 * look for work to do. 1627 */ 1628 e1000g_intr_work(Adapter, ICRContents); 1629 return (DDI_INTR_CLAIMED); 1630 } else { 1631 /* 1632 * No bit was set in ICR: 1633 * Don't claim this interrupt, return immediately. 1634 */ 1635 return (DDI_INTR_UNCLAIMED); 1636 } 1637 } 1638 1639 /* 1640 * ********************************************************************** 1641 * Name: e1000g_intr_work * 1642 * * 1643 * Description: * 1644 * Called from interrupt service routines. * 1645 * Read(clear) the ICR contents and call appropriate interrupt * 1646 * processing routines. * 1647 * * 1648 * Parameter Passed: * 1649 * * 1650 * Return Value: * 1651 * * 1652 * Functions called: * 1653 * ProcessRxInterruptArray * 1654 * e1000g_LocalTimerWork * 1655 * * 1656 * ********************************************************************** 1657 */ 1658 static void 1659 e1000g_intr_work(struct e1000g *Adapter, uint32_t ICRContents) 1660 { 1661 if (ICRContents & E1000_ICR_RXT0) { 1662 mblk_t *mp; 1663 1664 rw_enter(&Adapter->chip_lock, RW_READER); 1665 /* 1666 * Here we need to check the "started" flag to ensure the 1667 * receive routine will not execute when the adapter is 1668 * stopped or being reset. 1669 */ 1670 if (Adapter->started) { 1671 mutex_enter(&Adapter->rx_ring->rx_lock); 1672 mp = e1000g_receive(Adapter); 1673 mutex_exit(&Adapter->rx_ring->rx_lock); 1674 1675 rw_exit(&Adapter->chip_lock); 1676 1677 if (mp != NULL) 1678 mac_rx(Adapter->mh, Adapter->mrh, mp); 1679 } else { 1680 rw_exit(&Adapter->chip_lock); 1681 } 1682 } 1683 1684 /* 1685 * The Receive Sequence errors RXSEQ and the link status change LSC 1686 * are checked to detect that the cable has been pulled out. For 1687 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 1688 * are an indication that cable is not connected. 1689 */ 1690 if ((ICRContents & E1000_ICR_RXSEQ) || 1691 (ICRContents & E1000_ICR_LSC) || 1692 (ICRContents & E1000_ICR_GPI_EN1)) { 1693 boolean_t linkstate_changed; 1694 1695 /* 1696 * Encountered RX Sequence Error!!! Link maybe forced and 1697 * the cable may have just been disconnected so we will 1698 * read the LOS to see. 1699 */ 1700 if (ICRContents & E1000_ICR_RXSEQ) 1701 Adapter->rx_seq_intr++; 1702 1703 stop_timeout(Adapter); 1704 1705 mutex_enter(&Adapter->e1000g_linklock); 1706 /* e1000g_LocalTimerWork takes care of link status change */ 1707 linkstate_changed = e1000g_LocalTimerWork(Adapter); 1708 mutex_exit(&Adapter->e1000g_linklock); 1709 1710 if (linkstate_changed) { 1711 mac_link_update(Adapter->mh, 1712 (Adapter->LinkIsActive) ? 1713 LINK_STATE_UP : LINK_STATE_DOWN); 1714 } 1715 1716 start_timeout(Adapter); 1717 } 1718 1719 if (ICRContents & E1000G_ICR_TX_INTR) { 1720 if (!Adapter->tx_intr_enable) 1721 e1000g_DisableTxInterrupt(Adapter); 1722 /* Schedule the re-transmit */ 1723 if (Adapter->resched_needed) { 1724 Adapter->tx_reschedule++; 1725 Adapter->resched_needed = B_FALSE; 1726 mac_tx_update(Adapter->mh); 1727 } 1728 if (Adapter->tx_intr_enable) { 1729 /* Recycle the tx descriptors */ 1730 rw_enter(&Adapter->chip_lock, RW_READER); 1731 Adapter->tx_recycle_intr++; 1732 e1000g_recycle(Adapter->tx_ring); 1733 rw_exit(&Adapter->chip_lock); 1734 /* Free the recycled messages */ 1735 ddi_intr_trigger_softint(Adapter->tx_softint_handle, 1736 NULL); 1737 } 1738 } 1739 } 1740 1741 static void 1742 e1000g_init_unicst(struct e1000g *Adapter) 1743 { 1744 struct e1000_hw *hw; 1745 int slot; 1746 1747 hw = &Adapter->Shared; 1748 1749 if (Adapter->init_count == 0) { 1750 /* Initialize the multiple unicast addresses */ 1751 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 1752 1753 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1754 Adapter->unicst_total--; 1755 1756 Adapter->unicst_avail = Adapter->unicst_total - 1; 1757 1758 /* Store the default mac address */ 1759 e1000_rar_set(hw, hw->mac_addr, 0); 1760 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1761 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1762 1763 bcopy(hw->mac_addr, Adapter->unicst_addr[0].mac.addr, 1764 ETHERADDRL); 1765 Adapter->unicst_addr[0].mac.set = 1; 1766 1767 for (slot = 1; slot < Adapter->unicst_total; slot++) 1768 Adapter->unicst_addr[slot].mac.set = 0; 1769 } else { 1770 /* Recover the default mac address */ 1771 bcopy(Adapter->unicst_addr[0].mac.addr, hw->mac_addr, 1772 ETHERADDRL); 1773 1774 /* Store the default mac address */ 1775 e1000_rar_set(hw, hw->mac_addr, 0); 1776 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1777 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1778 1779 /* Re-configure the RAR registers */ 1780 for (slot = 1; slot < Adapter->unicst_total; slot++) 1781 e1000_rar_set(hw, 1782 Adapter->unicst_addr[slot].mac.addr, slot); 1783 } 1784 } 1785 1786 static int 1787 e1000g_m_unicst(void *arg, const uint8_t *mac_addr) 1788 { 1789 struct e1000g *Adapter; 1790 1791 Adapter = (struct e1000g *)arg; 1792 1793 /* Store the default MAC address */ 1794 bcopy(mac_addr, Adapter->Shared.mac_addr, ETHERADDRL); 1795 1796 /* Set MAC address in address slot 0, which is the default address */ 1797 return (e1000g_unicst_set(Adapter, mac_addr, 0)); 1798 } 1799 1800 static int 1801 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 1802 mac_addr_slot_t slot) 1803 { 1804 struct e1000_hw *hw; 1805 1806 hw = &Adapter->Shared; 1807 1808 /* 1809 * Error if the address specified is a multicast or broadcast 1810 * address. 1811 */ 1812 if (((mac_addr[0] & 01) == 1) || 1813 (bcmp(mac_addr, ðerbroadcastaddr, ETHERADDRL) == 0)) 1814 return (EINVAL); 1815 1816 rw_enter(&Adapter->chip_lock, RW_WRITER); 1817 1818 /* 1819 * The first revision of Wiseman silicon (rev 2.0) has an errata 1820 * that requires the receiver to be in reset when any of the 1821 * receive address registers (RAR regs) are accessed. The first 1822 * rev of Wiseman silicon also requires MWI to be disabled when 1823 * a global reset or a receive reset is issued. So before we 1824 * initialize the RARs, we check the rev of the Wiseman controller 1825 * and work around any necessary HW errata. 1826 */ 1827 if (hw->mac_type == e1000_82542_rev2_0) { 1828 e1000_pci_clear_mwi(hw); 1829 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); 1830 DelayInMilliseconds(5); 1831 } 1832 1833 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, ETHERADDRL); 1834 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 1835 1836 if (slot == 0) { 1837 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) 1838 e1000_rar_set(hw, hw->mac_addr, LAST_RAR_ENTRY); 1839 } 1840 1841 /* 1842 * If we are using Wiseman rev 2.0 silicon, we will have previously 1843 * put the receive in reset, and disabled MWI, to work around some 1844 * HW errata. Now we should take the receiver out of reset, and 1845 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 1846 */ 1847 if (hw->mac_type == e1000_82542_rev2_0) { 1848 E1000_WRITE_REG(hw, RCTL, 0); 1849 DelayInMilliseconds(1); 1850 if (hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 1851 e1000_pci_set_mwi(hw); 1852 SetupReceiveStructures(Adapter); 1853 } 1854 1855 rw_exit(&Adapter->chip_lock); 1856 1857 return (0); 1858 } 1859 1860 /* 1861 * e1000g_m_unicst_add() - will find an unused address slot, set the 1862 * address value to the one specified, reserve that slot and enable 1863 * the NIC to start filtering on the new MAC address. 1864 * Returns 0 on success. 1865 */ 1866 static int 1867 e1000g_m_unicst_add(void *arg, mac_multi_addr_t *maddr) 1868 { 1869 struct e1000g *Adapter = (struct e1000g *)arg; 1870 mac_addr_slot_t slot; 1871 int err; 1872 1873 if (mac_unicst_verify(Adapter->mh, 1874 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 1875 return (EINVAL); 1876 1877 rw_enter(&Adapter->chip_lock, RW_WRITER); 1878 if (Adapter->unicst_avail == 0) { 1879 /* no slots available */ 1880 rw_exit(&Adapter->chip_lock); 1881 return (ENOSPC); 1882 } 1883 1884 /* 1885 * Primary/default address is in slot 0. The next addresses 1886 * are the multiple MAC addresses. So multiple MAC address 0 1887 * is in slot 1, 1 in slot 2, and so on. So the first multiple 1888 * MAC address resides in slot 1. 1889 */ 1890 for (slot = 1; slot < Adapter->unicst_total; slot++) { 1891 if (Adapter->unicst_addr[slot].mac.set == 0) { 1892 Adapter->unicst_addr[slot].mac.set = 1; 1893 break; 1894 } 1895 } 1896 1897 ASSERT((slot > 0) && (slot < Adapter->unicst_total)); 1898 1899 Adapter->unicst_avail--; 1900 rw_exit(&Adapter->chip_lock); 1901 1902 maddr->mma_slot = slot; 1903 1904 if ((err = e1000g_unicst_set(Adapter, maddr->mma_addr, slot)) != 0) { 1905 rw_enter(&Adapter->chip_lock, RW_WRITER); 1906 Adapter->unicst_addr[slot].mac.set = 0; 1907 Adapter->unicst_avail++; 1908 rw_exit(&Adapter->chip_lock); 1909 } 1910 1911 return (err); 1912 } 1913 1914 /* 1915 * e1000g_m_unicst_remove() - removes a MAC address that was added by a 1916 * call to e1000g_m_unicst_add(). The slot number that was returned in 1917 * e1000g_m_unicst_add() is passed in the call to remove the address. 1918 * Returns 0 on success. 1919 */ 1920 static int 1921 e1000g_m_unicst_remove(void *arg, mac_addr_slot_t slot) 1922 { 1923 struct e1000g *Adapter = (struct e1000g *)arg; 1924 int err; 1925 1926 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 1927 return (EINVAL); 1928 1929 rw_enter(&Adapter->chip_lock, RW_WRITER); 1930 if (Adapter->unicst_addr[slot].mac.set == 1) { 1931 Adapter->unicst_addr[slot].mac.set = 0; 1932 Adapter->unicst_avail++; 1933 rw_exit(&Adapter->chip_lock); 1934 1935 /* Copy the default address to the passed slot */ 1936 if (err = e1000g_unicst_set(Adapter, 1937 Adapter->unicst_addr[0].mac.addr, slot) != 0) { 1938 rw_enter(&Adapter->chip_lock, RW_WRITER); 1939 Adapter->unicst_addr[slot].mac.set = 1; 1940 Adapter->unicst_avail--; 1941 rw_exit(&Adapter->chip_lock); 1942 } 1943 return (err); 1944 } 1945 rw_exit(&Adapter->chip_lock); 1946 1947 return (EINVAL); 1948 } 1949 1950 /* 1951 * e1000g_m_unicst_modify() - modifies the value of an address that 1952 * has been added by e1000g_m_unicst_add(). The new address, address 1953 * length and the slot number that was returned in the call to add 1954 * should be passed to e1000g_m_unicst_modify(). mma_flags should be 1955 * set to 0. Returns 0 on success. 1956 */ 1957 static int 1958 e1000g_m_unicst_modify(void *arg, mac_multi_addr_t *maddr) 1959 { 1960 struct e1000g *Adapter = (struct e1000g *)arg; 1961 mac_addr_slot_t slot; 1962 1963 if (mac_unicst_verify(Adapter->mh, 1964 maddr->mma_addr, maddr->mma_addrlen) == B_FALSE) 1965 return (EINVAL); 1966 1967 slot = maddr->mma_slot; 1968 1969 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 1970 return (EINVAL); 1971 1972 rw_enter(&Adapter->chip_lock, RW_WRITER); 1973 if (Adapter->unicst_addr[slot].mac.set == 1) { 1974 rw_exit(&Adapter->chip_lock); 1975 1976 return (e1000g_unicst_set(Adapter, maddr->mma_addr, slot)); 1977 } 1978 rw_exit(&Adapter->chip_lock); 1979 1980 return (EINVAL); 1981 } 1982 1983 /* 1984 * e1000g_m_unicst_get() - will get the MAC address and all other 1985 * information related to the address slot passed in mac_multi_addr_t. 1986 * mma_flags should be set to 0 in the call. 1987 * On return, mma_flags can take the following values: 1988 * 1) MMAC_SLOT_UNUSED 1989 * 2) MMAC_SLOT_USED | MMAC_VENDOR_ADDR 1990 * 3) MMAC_SLOT_UNUSED | MMAC_VENDOR_ADDR 1991 * 4) MMAC_SLOT_USED 1992 */ 1993 static int 1994 e1000g_m_unicst_get(void *arg, mac_multi_addr_t *maddr) 1995 { 1996 struct e1000g *Adapter = (struct e1000g *)arg; 1997 mac_addr_slot_t slot; 1998 1999 slot = maddr->mma_slot; 2000 2001 if ((slot <= 0) || (slot >= Adapter->unicst_total)) 2002 return (EINVAL); 2003 2004 rw_enter(&Adapter->chip_lock, RW_WRITER); 2005 if (Adapter->unicst_addr[slot].mac.set == 1) { 2006 bcopy(Adapter->unicst_addr[slot].mac.addr, 2007 maddr->mma_addr, ETHERADDRL); 2008 maddr->mma_flags = MMAC_SLOT_USED; 2009 } else { 2010 maddr->mma_flags = MMAC_SLOT_UNUSED; 2011 } 2012 rw_exit(&Adapter->chip_lock); 2013 2014 return (0); 2015 } 2016 2017 static int 2018 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2019 { 2020 unsigned i; 2021 int res = 0; 2022 2023 rw_enter(&Adapter->chip_lock, RW_WRITER); 2024 2025 if ((multiaddr[0] & 01) == 0) { 2026 res = EINVAL; 2027 goto done; 2028 } 2029 2030 if (Adapter->mcast_count >= MAX_NUM_MULTICAST_ADDRESSES) { 2031 res = ENOENT; 2032 goto done; 2033 } 2034 2035 bcopy(multiaddr, 2036 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2037 Adapter->mcast_count++; 2038 2039 /* 2040 * Update the MC table in the hardware 2041 */ 2042 e1000g_DisableInterrupt(Adapter); 2043 2044 SetupMulticastTable(Adapter); 2045 2046 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2047 SetupReceiveStructures(Adapter); 2048 2049 e1000g_EnableInterrupt(Adapter); 2050 2051 done: 2052 rw_exit(&Adapter->chip_lock); 2053 return (res); 2054 } 2055 2056 static int 2057 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2058 { 2059 unsigned i; 2060 2061 rw_enter(&Adapter->chip_lock, RW_WRITER); 2062 2063 for (i = 0; i < Adapter->mcast_count; i++) { 2064 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2065 ETHERADDRL) == 0) { 2066 for (i++; i < Adapter->mcast_count; i++) { 2067 Adapter->mcast_table[i - 1] = 2068 Adapter->mcast_table[i]; 2069 } 2070 Adapter->mcast_count--; 2071 break; 2072 } 2073 } 2074 2075 /* 2076 * Update the MC table in the hardware 2077 */ 2078 e1000g_DisableInterrupt(Adapter); 2079 2080 SetupMulticastTable(Adapter); 2081 2082 if (Adapter->Shared.mac_type == e1000_82542_rev2_0) 2083 SetupReceiveStructures(Adapter); 2084 2085 e1000g_EnableInterrupt(Adapter); 2086 2087 done: 2088 rw_exit(&Adapter->chip_lock); 2089 return (0); 2090 } 2091 2092 int 2093 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2094 { 2095 struct e1000g *Adapter = (struct e1000g *)arg; 2096 2097 return ((add) ? multicst_add(Adapter, addr) 2098 : multicst_remove(Adapter, addr)); 2099 } 2100 2101 int 2102 e1000g_m_promisc(void *arg, boolean_t on) 2103 { 2104 struct e1000g *Adapter = (struct e1000g *)arg; 2105 ULONG RctlRegValue; 2106 2107 rw_enter(&Adapter->chip_lock, RW_WRITER); 2108 2109 RctlRegValue = E1000_READ_REG(&Adapter->Shared, RCTL); 2110 2111 if (on) 2112 RctlRegValue |= 2113 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2114 else 2115 RctlRegValue &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2116 2117 E1000_WRITE_REG(&Adapter->Shared, RCTL, RctlRegValue); 2118 2119 Adapter->e1000g_promisc = on; 2120 2121 rw_exit(&Adapter->chip_lock); 2122 2123 return (0); 2124 } 2125 2126 static boolean_t 2127 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 2128 { 2129 struct e1000g *Adapter = (struct e1000g *)arg; 2130 2131 switch (cap) { 2132 case MAC_CAPAB_HCKSUM: { 2133 uint32_t *txflags = cap_data; 2134 2135 /* 2136 * In Jumbo mode, enabling hardware checksum will cause 2137 * port hang. 2138 */ 2139 if (Adapter->Shared.max_frame_size > ETHERMAX) 2140 return (B_FALSE); 2141 2142 /* 2143 * Checksum on/off selection via global parameters. 2144 * 2145 * If the chip is flagged as not capable of (correctly) 2146 * handling FULL checksumming, we don't enable it on either 2147 * Rx or Tx side. Otherwise, we take this chip's settings 2148 * from the patchable global defaults. 2149 * 2150 * We advertise our capabilities only if TX offload is 2151 * enabled. On receive, the stack will accept checksummed 2152 * packets anyway, even if we haven't said we can deliver 2153 * them. 2154 */ 2155 switch (Adapter->Shared.mac_type) { 2156 /* 2157 * Switch on hardware checksum offload of 2158 * chip 82540, 82545, 82546 2159 */ 2160 case e1000_82540: 2161 case e1000_82544: /* pci8086,1008 */ 2162 case e1000_82545: 2163 case e1000_82545_rev_3: /* pci8086,1026 */ 2164 case e1000_82571: 2165 case e1000_82572: 2166 case e1000_82573: 2167 case e1000_80003es2lan: 2168 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2169 break; 2170 2171 case e1000_82546: /* 82546EB. devID: 1010, 101d */ 2172 case e1000_82546_rev_3: /* 82546GB. devID: 1079, 107a */ 2173 #if !defined(__sparc) && !defined(__amd64) 2174 /* Workaround for Galaxy on 32bit */ 2175 return (B_FALSE); 2176 #else 2177 *txflags = HCKSUM_IPHDRCKSUM | HCKSUM_INET_PARTIAL; 2178 break; 2179 #endif 2180 2181 /* 2182 * We don't have the following PRO 1000 chip types at 2183 * hand and haven't tested their hardware checksum 2184 * offload capability. We had better switch them off. 2185 * e1000_undefined = 0, 2186 * e1000_82542_rev2_0, 2187 * e1000_82542_rev2_1, 2188 * e1000_82543, 2189 * e1000_82541, 2190 * e1000_82541_rev_2, 2191 * e1000_82547, 2192 * e1000_82547_rev_2, 2193 * e1000_num_macs 2194 */ 2195 default: 2196 return (B_FALSE); 2197 } 2198 2199 break; 2200 } 2201 case MAC_CAPAB_POLL: 2202 /* 2203 * There's nothing for us to fill in, simply returning 2204 * B_TRUE stating that we support polling is sufficient. 2205 */ 2206 break; 2207 2208 case MAC_CAPAB_MULTIADDRESS: { 2209 multiaddress_capab_t *mmacp = cap_data; 2210 2211 /* 2212 * The number of MAC addresses made available by 2213 * this capability is one less than the total as 2214 * the primary address in slot 0 is counted in 2215 * the total. 2216 */ 2217 mmacp->maddr_naddr = Adapter->unicst_total - 1; 2218 mmacp->maddr_naddrfree = Adapter->unicst_avail; 2219 /* No multiple factory addresses, set mma_flag to 0 */ 2220 mmacp->maddr_flag = 0; 2221 mmacp->maddr_handle = Adapter; 2222 mmacp->maddr_add = e1000g_m_unicst_add; 2223 mmacp->maddr_remove = e1000g_m_unicst_remove; 2224 mmacp->maddr_modify = e1000g_m_unicst_modify; 2225 mmacp->maddr_get = e1000g_m_unicst_get; 2226 mmacp->maddr_reserve = NULL; 2227 break; 2228 } 2229 default: 2230 return (B_FALSE); 2231 } 2232 return (B_TRUE); 2233 } 2234 2235 /* 2236 * ********************************************************************** 2237 * Name: e1000g_getparam * 2238 * * 2239 * Description: This routine gets user-configured values out of the * 2240 * configuration file e1000g.conf. * 2241 * For each configurable value, there is a minimum, a maximum, and a * 2242 * default. * 2243 * If user does not configure a value, use the default. * 2244 * If user configures below the minimum, use the minumum. * 2245 * If user configures above the maximum, use the maxumum. * 2246 * * 2247 * Arguments: * 2248 * Adapter - A pointer to our adapter structure * 2249 * * 2250 * Returns: None * 2251 * ********************************************************************** 2252 */ 2253 static void 2254 e1000g_getparam(struct e1000g *Adapter) 2255 { 2256 /* 2257 * get each configurable property from e1000g.conf 2258 */ 2259 2260 /* 2261 * NumTxDescriptors 2262 */ 2263 Adapter->NumTxDescriptors = 2264 e1000g_getprop(Adapter, "NumTxDescriptors", 2265 MINNUMTXDESCRIPTOR, MAXNUMTXDESCRIPTOR, 2266 DEFAULTNUMTXDESCRIPTOR); 2267 2268 /* 2269 * NumRxDescriptors 2270 */ 2271 Adapter->NumRxDescriptors = 2272 e1000g_getprop(Adapter, "NumRxDescriptors", 2273 MINNUMRXDESCRIPTOR, MAXNUMRXDESCRIPTOR, 2274 DEFAULTNUMRXDESCRIPTOR); 2275 2276 /* 2277 * NumRxFreeList 2278 */ 2279 Adapter->NumRxFreeList = 2280 e1000g_getprop(Adapter, "NumRxFreeList", 2281 MINNUMRXFREELIST, MAXNUMRXFREELIST, 2282 DEFAULTNUMRXFREELIST); 2283 2284 /* 2285 * NumTxPacketList 2286 */ 2287 Adapter->NumTxSwPacket = 2288 e1000g_getprop(Adapter, "NumTxPacketList", 2289 MINNUMTXSWPACKET, MAXNUMTXSWPACKET, 2290 DEFAULTNUMTXSWPACKET); 2291 2292 /* 2293 * FlowControl 2294 */ 2295 Adapter->Shared.fc_send_xon = B_TRUE; 2296 Adapter->Shared.fc = 2297 e1000g_getprop(Adapter, "FlowControl", 2298 E1000_FC_NONE, 4, DEFAULTFLOWCONTROLVAL); 2299 /* 4 is the setting that says "let the eeprom decide" */ 2300 if (Adapter->Shared.fc == 4) 2301 Adapter->Shared.fc = E1000_FC_DEFAULT; 2302 2303 /* 2304 * MaxNumReceivePackets 2305 */ 2306 Adapter->MaxNumReceivePackets = 2307 e1000g_getprop(Adapter, "MaxNumReceivePackets", 2308 MINNUMRCVPKTONINTR, MAXNUMRCVPKTONINTR, 2309 DEFAULTMAXNUMRCVPKTONINTR); 2310 2311 /* 2312 * TxInterruptDelay 2313 */ 2314 Adapter->TxInterruptDelay = 2315 e1000g_getprop(Adapter, "TxInterruptDelay", 2316 MINTXINTERRUPTDELAYVAL, MAXTXINTERRUPTDELAYVAL, 2317 DEFAULTTXINTERRUPTDELAYVAL); 2318 2319 /* 2320 * PHY master slave setting 2321 */ 2322 Adapter->Shared.master_slave = 2323 e1000g_getprop(Adapter, "SetMasterSlave", 2324 e1000_ms_hw_default, e1000_ms_auto, 2325 e1000_ms_hw_default); 2326 2327 /* 2328 * Parameter which controls TBI mode workaround, which is only 2329 * needed on certain switches such as Cisco 6500/Foundry 2330 */ 2331 Adapter->Shared.tbi_compatibility_en = 2332 e1000g_getprop(Adapter, "TbiCompatibilityEnable", 2333 0, 1, DEFAULTTBICOMPATIBILITYENABLE); 2334 2335 /* 2336 * MSI Enable 2337 */ 2338 Adapter->msi_enabled = 2339 e1000g_getprop(Adapter, "MSIEnable", 2340 0, 1, DEFAULTMSIENABLE); 2341 2342 /* 2343 * Interrupt Throttling Rate 2344 */ 2345 Adapter->intr_throttling_rate = 2346 e1000g_getprop(Adapter, "intr_throttling_rate", 2347 MININTERRUPTTHROTTLINGVAL, MAXINTERRUPTTHROTTLINGVAL, 2348 DEFAULTINTERRUPTTHROTTLINGVAL); 2349 2350 /* 2351 * Adaptive Interrupt Blanking Enable/Disable 2352 * It is enabled by default 2353 */ 2354 Adapter->intr_adaptive = 2355 (e1000g_getprop(Adapter, "intr_adaptive", 0, 1, 1) == 1) ? 2356 B_TRUE : B_FALSE; 2357 } 2358 2359 /* 2360 * ********************************************************************** 2361 * Name: e1000g_getprop * 2362 * * 2363 * Description: get a user-configure property value out of the * 2364 * configuration file e1000g.conf. * 2365 * Caller provides name of the property, a default value, a * 2366 * minimum value, and a maximum value. * 2367 * * 2368 * Returns: configured value of the property, with default, minimum and * 2369 * maximum properly applied. * 2370 * ********************************************************************** 2371 */ 2372 static int 2373 e1000g_getprop(struct e1000g *Adapter, /* point to per-adapter structure */ 2374 char *propname, /* name of the property */ 2375 int minval, /* minimum acceptable value */ 2376 int maxval, /* maximim acceptable value */ 2377 int defval) /* default value */ 2378 { 2379 int propval; /* value returned for requested property */ 2380 int *props; /* point to array of properties returned */ 2381 uint_t nprops; /* number of property value returned */ 2382 2383 /* 2384 * get the array of properties from the config file 2385 */ 2386 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 2387 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 2388 /* got some properties, test if we got enough */ 2389 if (Adapter->AdapterInstance < nprops) { 2390 propval = props[Adapter->AdapterInstance]; 2391 } else { 2392 /* not enough properties configured */ 2393 propval = defval; 2394 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2395 "Not Enough %s values found in e1000g.conf" 2396 " - set to %d\n", 2397 propname, propval); 2398 } 2399 2400 /* free memory allocated for properties */ 2401 ddi_prop_free(props); 2402 2403 } else { 2404 propval = defval; 2405 } 2406 2407 /* 2408 * enforce limits 2409 */ 2410 if (propval > maxval) { 2411 propval = maxval; 2412 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2413 "Too High %s value in e1000g.conf - set to %d\n", 2414 propname, propval); 2415 } 2416 2417 if (propval < minval) { 2418 propval = minval; 2419 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 2420 "Too Low %s value in e1000g.conf - set to %d\n", 2421 propname, propval); 2422 } 2423 2424 return (propval); 2425 } 2426 2427 static boolean_t 2428 e1000g_LocalTimerWork(struct e1000g *Adapter) 2429 { 2430 UINT16 LineSpeed, Duplex, phydata; 2431 boolean_t linkstate_changed = B_FALSE; 2432 struct e1000_hw *hw; 2433 e1000g_ether_addr_t ether_addr; 2434 uint32_t reg_tarc; 2435 2436 hw = &Adapter->Shared; 2437 2438 if (e1000g_link_up(Adapter)) { 2439 /* 2440 * The Link is up, check whether it was marked as down earlier 2441 */ 2442 if (!Adapter->LinkIsActive) { 2443 e1000_get_speed_and_duplex(hw, &LineSpeed, &Duplex); 2444 Adapter->link_speed = LineSpeed; 2445 Adapter->link_duplex = Duplex; 2446 2447 if (!Adapter->PseudoLinkChanged) { 2448 if ((hw->mac_type == e1000_82571) || 2449 (hw->mac_type == e1000_82572)) { 2450 reg_tarc = E1000_READ_REG(hw, TARC0); 2451 if (LineSpeed == SPEED_1000) 2452 reg_tarc |= (1 << 21); 2453 else 2454 reg_tarc &= ~(1 << 21); 2455 E1000_WRITE_REG(hw, TARC0, reg_tarc); 2456 } 2457 2458 e1000g_log(Adapter, CE_NOTE, 2459 "Adapter %dMbps %s %s link is up.", 2460 LineSpeed, 2461 ((Duplex == FULL_DUPLEX) ? 2462 "full duplex" : "half duplex"), 2463 ((hw->media_type == 2464 e1000_media_type_copper) ? 2465 "copper" : "fiber")); 2466 } 2467 2468 Adapter->LinkIsActive = B_TRUE; 2469 linkstate_changed = B_TRUE; 2470 } 2471 Adapter->smartspeed = 0; 2472 } else { 2473 if (Adapter->LinkIsActive) { 2474 Adapter->link_speed = 0; 2475 Adapter->link_duplex = 0; 2476 2477 if (!Adapter->PseudoLinkChanged) { 2478 e1000g_log(Adapter, CE_NOTE, 2479 "Adapter %s link is down.", 2480 ((hw->media_type == 2481 e1000_media_type_copper) ? 2482 "copper" : "fiber")); 2483 } 2484 2485 Adapter->LinkIsActive = B_FALSE; 2486 linkstate_changed = B_TRUE; 2487 /* 2488 * SmartSpeed workaround for Tabor/TanaX, When the 2489 * driver loses link disable auto master/slave 2490 * resolution. 2491 */ 2492 if (hw->phy_type == e1000_phy_igp) { 2493 e1000_read_phy_reg(hw, 2494 PHY_1000T_CTRL, &phydata); 2495 phydata |= CR_1000T_MS_ENABLE; 2496 e1000_write_phy_reg(hw, 2497 PHY_1000T_CTRL, phydata); 2498 } 2499 /* 2500 * Workaround for esb2. Data stuck in fifo on a link 2501 * down event. Reset the adapter to recover it. 2502 */ 2503 if (hw->mac_type == e1000_80003es2lan) { 2504 (void) e1000g_reset(Adapter); 2505 } 2506 } else { 2507 e1000g_smartspeed(Adapter); 2508 } 2509 } 2510 2511 /* 2512 * With 82571 controllers, any locally administered address will 2513 * be overwritten when there is a reset on the other port. 2514 * Detect this circumstance and correct it. 2515 */ 2516 if ((hw->mac_type == e1000_82571) && hw->laa_is_present) { 2517 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, RA, 0); 2518 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, RA, 1); 2519 2520 ether_addr.reg.low = ntohl(ether_addr.reg.low); 2521 ether_addr.reg.high = ntohl(ether_addr.reg.high); 2522 2523 if ((ether_addr.mac.addr[5] != hw->mac_addr[0]) || 2524 (ether_addr.mac.addr[4] != hw->mac_addr[1]) || 2525 (ether_addr.mac.addr[3] != hw->mac_addr[2]) || 2526 (ether_addr.mac.addr[2] != hw->mac_addr[3]) || 2527 (ether_addr.mac.addr[1] != hw->mac_addr[4]) || 2528 (ether_addr.mac.addr[0] != hw->mac_addr[5])) { 2529 e1000_rar_set(hw, hw->mac_addr, 0); 2530 } 2531 } 2532 2533 /* 2534 * RP: ttl_workaround : DCR 49 2535 */ 2536 e1000_igp_ttl_workaround(hw); 2537 2538 /* 2539 * Check for Adaptive IFS settings If there are lots of collisions 2540 * change the value in steps... 2541 * These properties should only be set for 10/100 2542 */ 2543 if ((hw->media_type == e1000_media_type_copper) && 2544 (Adapter->link_speed != SPEED_1000)) { 2545 e1000_update_adaptive(hw); 2546 } 2547 /* 2548 * Set Timer Interrupts 2549 */ 2550 E1000_WRITE_REG(hw, ICS, E1000_IMS_RXT0); 2551 2552 return (linkstate_changed); 2553 } 2554 2555 static void 2556 e1000g_LocalTimer(void *ws) 2557 { 2558 struct e1000g *Adapter = (struct e1000g *)ws; 2559 boolean_t linkstate_changed; 2560 2561 (void) e1000g_tx_freemsg((caddr_t)Adapter, NULL); 2562 2563 if (e1000g_stall_check(Adapter)) { 2564 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 2565 "Tx stall detected. Activate automatic recovery.\n"); 2566 Adapter->StallWatchdog = 0; 2567 Adapter->tx_recycle_fail = 0; 2568 Adapter->reset_count++; 2569 (void) e1000g_reset(Adapter); 2570 } 2571 2572 mutex_enter(&Adapter->e1000g_linklock); 2573 linkstate_changed = e1000g_LocalTimerWork(Adapter); 2574 mutex_exit(&Adapter->e1000g_linklock); 2575 2576 if (linkstate_changed || Adapter->PseudoLinkChanged) { 2577 mac_link_update(Adapter->mh, 2578 (Adapter->LinkIsActive) ? 2579 LINK_STATE_UP : LINK_STATE_DOWN); 2580 Adapter->PseudoLinkChanged = B_FALSE; 2581 } 2582 2583 restart_timeout(Adapter); 2584 } 2585 2586 /* 2587 * ********************************************************************** 2588 * Name: e1000g_force_speed_duplex * 2589 * * 2590 * Description: * 2591 * This function forces speed and duplex for 10/100 Mbps speeds * 2592 * and also for 1000 Mbps speeds, it advertises half or full duplex * 2593 * * 2594 * Parameter Passed: * 2595 * struct e1000g* (information of adpater) * 2596 * * 2597 * Return Value: * 2598 * * 2599 * Functions called: * 2600 * ********************************************************************** 2601 */ 2602 static void 2603 e1000g_force_speed_duplex(struct e1000g *Adapter) 2604 { 2605 int forced; 2606 2607 /* 2608 * get value out of config file 2609 */ 2610 forced = e1000g_getprop(Adapter, "ForceSpeedDuplex", 2611 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY); 2612 2613 switch (forced) { 2614 case GDIAG_10_HALF: 2615 /* 2616 * Disable Auto Negotiation 2617 */ 2618 Adapter->Shared.autoneg = B_FALSE; 2619 Adapter->Shared.forced_speed_duplex = e1000_10_half; 2620 break; 2621 case GDIAG_10_FULL: 2622 /* 2623 * Disable Auto Negotiation 2624 */ 2625 Adapter->Shared.autoneg = B_FALSE; 2626 Adapter->Shared.forced_speed_duplex = e1000_10_full; 2627 break; 2628 case GDIAG_100_HALF: 2629 /* 2630 * Disable Auto Negotiation 2631 */ 2632 Adapter->Shared.autoneg = B_FALSE; 2633 Adapter->Shared.forced_speed_duplex = e1000_100_half; 2634 break; 2635 case GDIAG_100_FULL: 2636 /* 2637 * Disable Auto Negotiation 2638 */ 2639 Adapter->Shared.autoneg = B_FALSE; 2640 Adapter->Shared.forced_speed_duplex = e1000_100_full; 2641 break; 2642 case GDIAG_1000_FULL: 2643 /* 2644 * The gigabit spec requires autonegotiation. Therefore, 2645 * when the user wants to force the speed to 1000Mbps, we 2646 * enable AutoNeg, but only allow the harware to advertise 2647 * 1000Mbps. This is different from 10/100 operation, where 2648 * we are allowed to link without any negotiation. 2649 */ 2650 Adapter->Shared.autoneg = B_TRUE; 2651 Adapter->Shared.autoneg_advertised = ADVERTISE_1000_FULL; 2652 break; 2653 default: /* obey the setting of AutoNegAdvertised */ 2654 Adapter->Shared.autoneg = B_TRUE; 2655 Adapter->Shared.autoneg_advertised = 2656 (uint16_t)e1000g_getprop(Adapter, "AutoNegAdvertised", 2657 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 2658 AUTONEG_ADVERTISE_SPEED_DEFAULT); 2659 break; 2660 } /* switch */ 2661 } 2662 2663 /* 2664 * ********************************************************************** 2665 * Name: e1000g_get_max_frame_size * 2666 * * 2667 * Description: * 2668 * This function reads MaxFrameSize from e1000g.conf and sets it for * 2669 * adapter. * 2670 * * 2671 * Parameter Passed: * 2672 * struct e1000g* (information of adpater) * 2673 * * 2674 * Return Value: * 2675 * * 2676 * Functions called: * 2677 * ********************************************************************** 2678 */ 2679 static void 2680 e1000g_get_max_frame_size(struct e1000g *Adapter) 2681 { 2682 int max_frame; 2683 2684 /* 2685 * get value out of config file 2686 */ 2687 max_frame = e1000g_getprop(Adapter, "MaxFrameSize", 0, 3, 0); 2688 2689 switch (max_frame) { 2690 case 0: 2691 Adapter->Shared.max_frame_size = ETHERMAX; 2692 break; 2693 case 1: 2694 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_4K; 2695 break; 2696 case 2: 2697 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_8K; 2698 break; 2699 case 3: 2700 if (Adapter->Shared.mac_type < e1000_82571) 2701 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_16K; 2702 else 2703 Adapter->Shared.max_frame_size = FRAME_SIZE_UPTO_10K; 2704 break; 2705 default: 2706 Adapter->Shared.max_frame_size = ETHERMAX; 2707 break; 2708 } /* switch */ 2709 2710 /* ich8 does not do jumbo frames */ 2711 if (Adapter->Shared.mac_type == e1000_ich8lan) { 2712 Adapter->Shared.max_frame_size = ETHERMAX; 2713 } 2714 } 2715 2716 static void 2717 arm_timer(struct e1000g *Adapter) 2718 { 2719 Adapter->WatchDogTimer_id = 2720 timeout(e1000g_LocalTimer, 2721 (void *)Adapter, 1 * drv_usectohz(1000000)); 2722 } 2723 2724 static void 2725 enable_timeout(struct e1000g *Adapter) 2726 { 2727 mutex_enter(&Adapter->e1000g_timeout_lock); 2728 2729 if (!Adapter->timeout_enabled) { 2730 Adapter->timeout_enabled = B_TRUE; 2731 Adapter->timeout_started = B_TRUE; 2732 2733 arm_timer(Adapter); 2734 } 2735 2736 mutex_exit(&Adapter->e1000g_timeout_lock); 2737 } 2738 2739 static void 2740 disable_timeout(struct e1000g *Adapter) 2741 { 2742 timeout_id_t tid; 2743 2744 mutex_enter(&Adapter->e1000g_timeout_lock); 2745 2746 Adapter->timeout_enabled = B_FALSE; 2747 Adapter->timeout_started = B_FALSE; 2748 2749 tid = Adapter->WatchDogTimer_id; 2750 Adapter->WatchDogTimer_id = 0; 2751 2752 mutex_exit(&Adapter->e1000g_timeout_lock); 2753 2754 if (tid != 0) 2755 (void) untimeout(tid); 2756 } 2757 2758 static void 2759 start_timeout(struct e1000g *Adapter) 2760 { 2761 mutex_enter(&Adapter->e1000g_timeout_lock); 2762 2763 if (Adapter->timeout_enabled) { 2764 if (!Adapter->timeout_started) { 2765 Adapter->timeout_started = B_TRUE; 2766 arm_timer(Adapter); 2767 } 2768 } 2769 2770 mutex_exit(&Adapter->e1000g_timeout_lock); 2771 } 2772 2773 static void 2774 restart_timeout(struct e1000g *Adapter) 2775 { 2776 mutex_enter(&Adapter->e1000g_timeout_lock); 2777 2778 if (Adapter->timeout_started) 2779 arm_timer(Adapter); 2780 2781 mutex_exit(&Adapter->e1000g_timeout_lock); 2782 } 2783 2784 static void 2785 stop_timeout(struct e1000g *Adapter) 2786 { 2787 timeout_id_t tid; 2788 2789 mutex_enter(&Adapter->e1000g_timeout_lock); 2790 2791 Adapter->timeout_started = B_FALSE; 2792 2793 tid = Adapter->WatchDogTimer_id; 2794 Adapter->WatchDogTimer_id = 0; 2795 2796 mutex_exit(&Adapter->e1000g_timeout_lock); 2797 2798 if (tid != 0) 2799 (void) untimeout(tid); 2800 } 2801 2802 void 2803 e1000g_DisableInterrupt(struct e1000g *Adapter) 2804 { 2805 E1000_WRITE_REG(&Adapter->Shared, IMC, 2806 0xffffffff & ~E1000_IMC_RXSEQ); 2807 } 2808 2809 void 2810 e1000g_EnableInterrupt(struct e1000g *Adapter) 2811 { 2812 E1000_WRITE_REG(&Adapter->Shared, IMS, 2813 IMS_ENABLE_MASK & ~E1000_IMS_TXDW & ~E1000_IMS_TXQE); 2814 } 2815 2816 void 2817 e1000g_DisableAllInterrupts(struct e1000g *Adapter) 2818 { 2819 E1000_WRITE_REG(&Adapter->Shared, IMC, 0xffffffff) 2820 } 2821 2822 void 2823 e1000g_EnableTxInterrupt(struct e1000g *Adapter) 2824 { 2825 E1000_WRITE_REG(&Adapter->Shared, IMS, E1000G_IMS_TX_INTR); 2826 } 2827 2828 void 2829 e1000g_DisableTxInterrupt(struct e1000g *Adapter) 2830 { 2831 E1000_WRITE_REG(&Adapter->Shared, IMC, E1000G_IMC_TX_INTR); 2832 } 2833 2834 void 2835 e1000_pci_set_mwi(struct e1000_hw *hw) 2836 { 2837 uint16_t val = hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE; 2838 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2839 } 2840 2841 void 2842 e1000_pci_clear_mwi(struct e1000_hw *hw) 2843 { 2844 uint16_t val = hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE; 2845 e1000_write_pci_cfg(hw, PCI_COMMAND_REGISTER, &val); 2846 } 2847 2848 void 2849 e1000_write_pci_cfg(struct e1000_hw *adapter, 2850 uint32_t reg, uint16_t *value) 2851 { 2852 pci_config_put16(((struct e1000g_osdep *)(adapter->back))->handle, 2853 reg, *value); 2854 } 2855 2856 void 2857 e1000_read_pci_cfg(struct e1000_hw *adapter, 2858 uint32_t reg, uint16_t *value) 2859 { 2860 *value = 2861 pci_config_get16(((struct e1000g_osdep *)(adapter->back))-> 2862 handle, reg); 2863 } 2864 2865 #ifndef __sparc 2866 void 2867 e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value) 2868 { 2869 outl(port, value); 2870 } 2871 2872 uint32_t 2873 e1000_io_read(struct e1000_hw *hw, unsigned long port) 2874 { 2875 return (inl(port)); 2876 } 2877 #endif 2878 2879 static void 2880 e1000g_smartspeed(struct e1000g *adapter) 2881 { 2882 uint16_t phy_status; 2883 uint16_t phy_ctrl; 2884 2885 /* 2886 * If we're not T-or-T, or we're not autoneg'ing, or we're not 2887 * advertising 1000Full, we don't even use the workaround 2888 */ 2889 if ((adapter->Shared.phy_type != e1000_phy_igp) || 2890 !adapter->Shared.autoneg || 2891 !(adapter->Shared.autoneg_advertised & ADVERTISE_1000_FULL)) 2892 return; 2893 2894 /* 2895 * True if this is the first call of this function or after every 2896 * 30 seconds of not having link 2897 */ 2898 if (adapter->smartspeed == 0) { 2899 /* 2900 * If Master/Slave config fault is asserted twice, we 2901 * assume back-to-back 2902 */ 2903 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 2904 &phy_status); 2905 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 2906 return; 2907 2908 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_STATUS, 2909 &phy_status); 2910 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 2911 return; 2912 /* 2913 * We're assuming back-2-back because our status register 2914 * insists! there's a fault in the master/slave 2915 * relationship that was "negotiated" 2916 */ 2917 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 2918 &phy_ctrl); 2919 /* 2920 * Is the phy configured for manual configuration of 2921 * master/slave? 2922 */ 2923 if (phy_ctrl & CR_1000T_MS_ENABLE) { 2924 /* 2925 * Yes. Then disable manual configuration (enable 2926 * auto configuration) of master/slave 2927 */ 2928 phy_ctrl &= ~CR_1000T_MS_ENABLE; 2929 e1000_write_phy_reg(&adapter->Shared, 2930 PHY_1000T_CTRL, phy_ctrl); 2931 /* 2932 * Effectively starting the clock 2933 */ 2934 adapter->smartspeed++; 2935 /* 2936 * Restart autonegotiation 2937 */ 2938 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 2939 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 2940 &phy_ctrl)) { 2941 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 2942 MII_CR_RESTART_AUTO_NEG); 2943 e1000_write_phy_reg(&adapter->Shared, 2944 PHY_CTRL, phy_ctrl); 2945 } 2946 } 2947 return; 2948 /* 2949 * Has 6 seconds transpired still without link? Remember, 2950 * you should reset the smartspeed counter once you obtain 2951 * link 2952 */ 2953 } else if (adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 2954 /* 2955 * Yes. Remember, we did at the start determine that 2956 * there's a master/slave configuration fault, so we're 2957 * still assuming there's someone on the other end, but we 2958 * just haven't yet been able to talk to it. We then 2959 * re-enable auto configuration of master/slave to see if 2960 * we're running 2/3 pair cables. 2961 */ 2962 /* 2963 * If still no link, perhaps using 2/3 pair cable 2964 */ 2965 e1000_read_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 2966 &phy_ctrl); 2967 phy_ctrl |= CR_1000T_MS_ENABLE; 2968 e1000_write_phy_reg(&adapter->Shared, PHY_1000T_CTRL, 2969 phy_ctrl); 2970 /* 2971 * Restart autoneg with phy enabled for manual 2972 * configuration of master/slave 2973 */ 2974 if (!e1000_phy_setup_autoneg(&adapter->Shared) && 2975 !e1000_read_phy_reg(&adapter->Shared, PHY_CTRL, 2976 &phy_ctrl)) { 2977 phy_ctrl |= 2978 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 2979 e1000_write_phy_reg(&adapter->Shared, PHY_CTRL, 2980 phy_ctrl); 2981 } 2982 /* 2983 * Hopefully, there are no more faults and we've obtained 2984 * link as a result. 2985 */ 2986 } 2987 /* 2988 * Restart process after E1000_SMARTSPEED_MAX iterations (30 2989 * seconds) 2990 */ 2991 if (adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 2992 adapter->smartspeed = 0; 2993 } 2994 2995 static boolean_t 2996 is_valid_mac_addr(uint8_t *mac_addr) 2997 { 2998 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 2999 const uint8_t addr_test2[6] = 3000 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 3001 3002 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 3003 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 3004 return (B_FALSE); 3005 3006 return (B_TRUE); 3007 } 3008 3009 /* 3010 * ********************************************************************** 3011 * Name: * 3012 * e1000g_stall_check * 3013 * * 3014 * Description: * 3015 * This function checks if the adapter is stalled. (In transmit) * 3016 * * 3017 * It is called each time the timeout is invoked. * 3018 * If the transmit descriptor reclaim continuously fails, * 3019 * the watchdog value will increment by 1. If the watchdog * 3020 * value exceeds the threshold, the adapter is assumed to * 3021 * have stalled and need to be reset. * 3022 * * 3023 * Arguments: * 3024 * Adapter - A pointer to our context sensitive "Adapter" * 3025 * structure. * 3026 * * 3027 * Returns: * 3028 * B_TRUE - The dapter is assumed to have stalled. * 3029 * B_FALSE * 3030 * * 3031 * ********************************************************************** 3032 */ 3033 static boolean_t 3034 e1000g_stall_check(struct e1000g *Adapter) 3035 { 3036 if (!Adapter->LinkIsActive) 3037 return (B_FALSE); 3038 3039 if (Adapter->tx_recycle_fail > 0) 3040 Adapter->StallWatchdog++; 3041 else 3042 Adapter->StallWatchdog = 0; 3043 3044 if (Adapter->StallWatchdog < E1000G_STALL_WATCHDOG_COUNT) 3045 return (B_FALSE); 3046 3047 return (B_TRUE); 3048 } 3049 3050 3051 static enum ioc_reply 3052 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 3053 { 3054 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 3055 e1000g_peekpoke_t *ppd; 3056 uint64_t mem_va; 3057 uint64_t maxoff; 3058 boolean_t peek; 3059 3060 switch (iocp->ioc_cmd) { 3061 3062 case E1000G_IOC_REG_PEEK: 3063 peek = B_TRUE; 3064 break; 3065 3066 case E1000G_IOC_REG_POKE: 3067 peek = B_FALSE; 3068 break; 3069 3070 deault: 3071 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3072 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 3073 iocp->ioc_cmd); 3074 return (IOC_INVAL); 3075 } 3076 3077 /* 3078 * Validate format of ioctl 3079 */ 3080 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 3081 return (IOC_INVAL); 3082 if (mp->b_cont == NULL) 3083 return (IOC_INVAL); 3084 3085 ppd = (e1000g_peekpoke_t *)mp->b_cont->b_rptr; 3086 3087 /* 3088 * Validate request parameters 3089 */ 3090 switch (ppd->pp_acc_space) { 3091 3092 default: 3093 e1000g_DEBUGLOG_1(e1000gp, e1000g_INFO_LEVEL, 3094 "e1000g_diag_ioctl: invalid access space 0x%X\n", 3095 ppd->pp_acc_space); 3096 return (IOC_INVAL); 3097 3098 case E1000G_PP_SPACE_REG: 3099 /* 3100 * Memory-mapped I/O space 3101 */ 3102 ASSERT(ppd->pp_acc_size == 4); 3103 if (ppd->pp_acc_size != 4) 3104 return (IOC_INVAL); 3105 3106 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 3107 return (IOC_INVAL); 3108 3109 mem_va = 0; 3110 maxoff = 0x10000; 3111 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 3112 break; 3113 3114 case E1000G_PP_SPACE_E1000G: 3115 /* 3116 * E1000g data structure! 3117 */ 3118 mem_va = (uintptr_t)e1000gp; 3119 maxoff = sizeof (struct e1000g); 3120 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 3121 break; 3122 3123 } 3124 3125 if (ppd->pp_acc_offset >= maxoff) 3126 return (IOC_INVAL); 3127 3128 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 3129 return (IOC_INVAL); 3130 3131 /* 3132 * All OK - go! 3133 */ 3134 ppd->pp_acc_offset += mem_va; 3135 (*ppfn)(e1000gp, ppd); 3136 return (peek ? IOC_REPLY : IOC_ACK); 3137 } 3138 3139 static void 3140 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3141 { 3142 ddi_acc_handle_t handle; 3143 uint32_t *regaddr; 3144 3145 handle = 3146 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle, 3147 regaddr = 3148 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3149 3150 ppd->pp_acc_data = ddi_get32(handle, regaddr); 3151 } 3152 3153 static void 3154 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3155 { 3156 ddi_acc_handle_t handle; 3157 uint32_t *regaddr; 3158 uint32_t value; 3159 3160 handle = 3161 ((struct e1000g_osdep *)(&e1000gp->Shared)->back)->E1000_handle, 3162 regaddr = 3163 (uint32_t *)((&e1000gp->Shared)->hw_addr + ppd->pp_acc_offset); 3164 value = (uint32_t)ppd->pp_acc_data; 3165 3166 ddi_put32(handle, regaddr, value); 3167 } 3168 3169 static void 3170 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3171 { 3172 uint64_t value; 3173 void *vaddr; 3174 3175 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3176 3177 switch (ppd->pp_acc_size) { 3178 case 1: 3179 value = *(uint8_t *)vaddr; 3180 break; 3181 3182 case 2: 3183 value = *(uint16_t *)vaddr; 3184 break; 3185 3186 case 4: 3187 value = *(uint32_t *)vaddr; 3188 break; 3189 3190 case 8: 3191 value = *(uint64_t *)vaddr; 3192 break; 3193 } 3194 3195 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3196 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 3197 (void *)e1000gp, (void *)ppd, value, vaddr); 3198 3199 ppd->pp_acc_data = value; 3200 } 3201 3202 static void 3203 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 3204 { 3205 uint64_t value; 3206 void *vaddr; 3207 3208 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 3209 value = ppd->pp_acc_data; 3210 3211 e1000g_DEBUGLOG_4(e1000gp, e1000g_INFO_LEVEL, 3212 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 3213 (void *)e1000gp, (void *)ppd, value, vaddr); 3214 3215 switch (ppd->pp_acc_size) { 3216 case 1: 3217 *(uint8_t *)vaddr = (uint8_t)value; 3218 break; 3219 3220 case 2: 3221 *(uint16_t *)vaddr = (uint16_t)value; 3222 break; 3223 3224 case 4: 3225 *(uint32_t *)vaddr = (uint32_t)value; 3226 break; 3227 3228 case 8: 3229 *(uint64_t *)vaddr = (uint64_t)value; 3230 break; 3231 } 3232 } 3233 3234 /* 3235 * Loopback Support 3236 */ 3237 static lb_property_t lb_normal = 3238 { normal, "normal", E1000G_LB_NONE }; 3239 static lb_property_t lb_external1000 = 3240 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 3241 static lb_property_t lb_external100 = 3242 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 3243 static lb_property_t lb_external10 = 3244 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 3245 static lb_property_t lb_phy = 3246 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 3247 3248 static enum ioc_reply 3249 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 3250 { 3251 lb_info_sz_t *lbsp; 3252 lb_property_t *lbpp; 3253 struct e1000_hw *hw; 3254 uint32_t *lbmp; 3255 uint32_t size; 3256 uint32_t value; 3257 uint16_t phy_status; 3258 uint16_t phy_ext_status; 3259 3260 hw = &Adapter->Shared; 3261 3262 if (mp->b_cont == NULL) 3263 return (IOC_INVAL); 3264 3265 switch (iocp->ioc_cmd) { 3266 default: 3267 return (IOC_INVAL); 3268 3269 case LB_GET_INFO_SIZE: 3270 size = sizeof (lb_info_sz_t); 3271 if (iocp->ioc_count != size) 3272 return (IOC_INVAL); 3273 3274 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3275 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3276 3277 value = sizeof (lb_normal); 3278 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3279 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3280 (hw->media_type == e1000_media_type_fiber) || 3281 (hw->media_type == e1000_media_type_internal_serdes)) { 3282 value += sizeof (lb_phy); 3283 switch (hw->mac_type) { 3284 case e1000_82571: 3285 case e1000_82572: 3286 value += sizeof (lb_external1000); 3287 break; 3288 } 3289 } 3290 if ((phy_status & MII_SR_100X_FD_CAPS) || 3291 (phy_status & MII_SR_100T2_FD_CAPS)) 3292 value += sizeof (lb_external100); 3293 if (phy_status & MII_SR_10T_FD_CAPS) 3294 value += sizeof (lb_external10); 3295 3296 lbsp = (lb_info_sz_t *)mp->b_cont->b_rptr; 3297 *lbsp = value; 3298 break; 3299 3300 case LB_GET_INFO: 3301 e1000_read_phy_reg(hw, PHY_EXT_STATUS, &phy_ext_status); 3302 e1000_read_phy_reg(hw, PHY_STATUS, &phy_status); 3303 3304 value = sizeof (lb_normal); 3305 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3306 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3307 (hw->media_type == e1000_media_type_fiber) || 3308 (hw->media_type == e1000_media_type_internal_serdes)) { 3309 value += sizeof (lb_phy); 3310 switch (hw->mac_type) { 3311 case e1000_82571: 3312 case e1000_82572: 3313 value += sizeof (lb_external1000); 3314 break; 3315 } 3316 } 3317 if ((phy_status & MII_SR_100X_FD_CAPS) || 3318 (phy_status & MII_SR_100T2_FD_CAPS)) 3319 value += sizeof (lb_external100); 3320 if (phy_status & MII_SR_10T_FD_CAPS) 3321 value += sizeof (lb_external10); 3322 3323 size = value; 3324 if (iocp->ioc_count != size) 3325 return (IOC_INVAL); 3326 3327 value = 0; 3328 lbpp = (lb_property_t *)mp->b_cont->b_rptr; 3329 lbpp[value++] = lb_normal; 3330 if ((phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 3331 (phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 3332 (hw->media_type == e1000_media_type_fiber) || 3333 (hw->media_type == e1000_media_type_internal_serdes)) { 3334 lbpp[value++] = lb_phy; 3335 switch (hw->mac_type) { 3336 case e1000_82571: 3337 case e1000_82572: 3338 lbpp[value++] = lb_external1000; 3339 break; 3340 } 3341 } 3342 if ((phy_status & MII_SR_100X_FD_CAPS) || 3343 (phy_status & MII_SR_100T2_FD_CAPS)) 3344 lbpp[value++] = lb_external100; 3345 if (phy_status & MII_SR_10T_FD_CAPS) 3346 lbpp[value++] = lb_external10; 3347 break; 3348 3349 case LB_GET_MODE: 3350 size = sizeof (uint32_t); 3351 if (iocp->ioc_count != size) 3352 return (IOC_INVAL); 3353 3354 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3355 *lbmp = Adapter->loopback_mode; 3356 break; 3357 3358 case LB_SET_MODE: 3359 size = 0; 3360 if (iocp->ioc_count != sizeof (uint32_t)) 3361 return (IOC_INVAL); 3362 3363 Adapter->PseudoLinkChanged = B_TRUE; 3364 lbmp = (uint32_t *)mp->b_cont->b_rptr; 3365 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 3366 return (IOC_INVAL); 3367 break; 3368 } 3369 3370 iocp->ioc_count = size; 3371 iocp->ioc_error = 0; 3372 3373 return (IOC_REPLY); 3374 } 3375 3376 static boolean_t 3377 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 3378 { 3379 struct e1000_hw *hw; 3380 #ifndef __sparc 3381 uint32_t reg_rctl; 3382 #endif 3383 int i, times; 3384 3385 if (mode == Adapter->loopback_mode) 3386 return (B_TRUE); 3387 3388 hw = &Adapter->Shared; 3389 times = 0; 3390 3391 again: 3392 switch (mode) { 3393 default: 3394 return (B_FALSE); 3395 3396 case E1000G_LB_NONE: 3397 /* Get original speed and duplex settings */ 3398 e1000g_force_speed_duplex(Adapter); 3399 /* Reset the chip */ 3400 hw->wait_autoneg_complete = B_TRUE; 3401 (void) e1000g_reset(Adapter); 3402 hw->wait_autoneg_complete = B_FALSE; 3403 break; 3404 3405 case E1000G_LB_EXTERNAL_1000: 3406 e1000g_set_external_loopback_1000(Adapter); 3407 break; 3408 3409 case E1000G_LB_EXTERNAL_100: 3410 e1000g_set_external_loopback_100(Adapter); 3411 break; 3412 3413 case E1000G_LB_EXTERNAL_10: 3414 e1000g_set_external_loopback_10(Adapter); 3415 break; 3416 3417 case E1000G_LB_INTERNAL_PHY: 3418 e1000g_set_internal_loopback(Adapter); 3419 break; 3420 } 3421 3422 times++; 3423 3424 switch (mode) { 3425 case E1000G_LB_EXTERNAL_1000: 3426 case E1000G_LB_EXTERNAL_100: 3427 case E1000G_LB_EXTERNAL_10: 3428 case E1000G_LB_INTERNAL_PHY: 3429 #ifndef __sparc 3430 /* Enable the CRC stripping for loopback */ 3431 reg_rctl = E1000_READ_REG(hw, RCTL); 3432 reg_rctl |= E1000_RCTL_SECRC; 3433 E1000_WRITE_REG(hw, RCTL, reg_rctl); 3434 #endif 3435 /* Wait for link up */ 3436 for (i = (PHY_FORCE_TIME * 2); i > 0; i--) 3437 msec_delay(100); 3438 3439 if (!e1000g_link_up(Adapter)) { 3440 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3441 "Failed to get the link up"); 3442 if (times < 2) { 3443 /* Reset the link */ 3444 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3445 "Reset the link ..."); 3446 (void) e1000g_reset(Adapter); 3447 goto again; 3448 } 3449 } 3450 break; 3451 } 3452 3453 Adapter->loopback_mode = mode; 3454 3455 return (B_TRUE); 3456 } 3457 3458 /* 3459 * The following loopback settings are from Intel's technical 3460 * document - "How To Loopback". All the register settings and 3461 * time delay values are directly inherited from the document 3462 * without more explanations available. 3463 */ 3464 static void 3465 e1000g_set_internal_loopback(struct e1000g *Adapter) 3466 { 3467 struct e1000_hw *hw; 3468 uint32_t ctrl; 3469 uint32_t status; 3470 uint16_t phy_ctrl; 3471 3472 hw = &Adapter->Shared; 3473 3474 /* Disable Smart Power Down */ 3475 phy_spd_state(hw, B_FALSE); 3476 3477 e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl); 3478 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 3479 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 3480 3481 switch (hw->mac_type) { 3482 case e1000_82540: 3483 case e1000_82545: 3484 case e1000_82545_rev_3: 3485 case e1000_82546: 3486 case e1000_82546_rev_3: 3487 case e1000_82573: 3488 /* Auto-MDI/MDIX off */ 3489 e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 3490 /* Reset PHY to update Auto-MDI/MDIX */ 3491 e1000_write_phy_reg(hw, PHY_CTRL, 3492 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 3493 /* Reset PHY to auto-neg off and force 1000 */ 3494 e1000_write_phy_reg(hw, PHY_CTRL, 3495 phy_ctrl | MII_CR_RESET); 3496 break; 3497 } 3498 3499 /* Set loopback */ 3500 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl | MII_CR_LOOPBACK); 3501 3502 msec_delay(250); 3503 3504 /* Now set up the MAC to the same speed/duplex as the PHY. */ 3505 ctrl = E1000_READ_REG(hw, CTRL); 3506 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3507 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3508 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3509 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 3510 E1000_CTRL_FD); /* Force Duplex to FULL */ 3511 3512 switch (hw->mac_type) { 3513 case e1000_82540: 3514 case e1000_82545: 3515 case e1000_82545_rev_3: 3516 case e1000_82546: 3517 case e1000_82546_rev_3: 3518 /* 3519 * For some serdes we'll need to commit the writes now 3520 * so that the status is updated on link 3521 */ 3522 if (hw->media_type == e1000_media_type_internal_serdes) { 3523 E1000_WRITE_REG(hw, CTRL, ctrl); 3524 msec_delay(100); 3525 ctrl = E1000_READ_REG(hw, CTRL); 3526 } 3527 3528 if (hw->media_type == e1000_media_type_copper) { 3529 /* Invert Loss of Signal */ 3530 ctrl |= E1000_CTRL_ILOS; 3531 } else { 3532 /* Set ILOS on fiber nic if half duplex is detected */ 3533 status = E1000_READ_REG(hw, STATUS); 3534 if ((status & E1000_STATUS_FD) == 0) 3535 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3536 } 3537 break; 3538 3539 case e1000_82571: 3540 case e1000_82572: 3541 if (hw->media_type != e1000_media_type_copper) { 3542 /* Set ILOS on fiber nic if half duplex is detected */ 3543 status = E1000_READ_REG(hw, STATUS); 3544 if ((status & E1000_STATUS_FD) == 0) 3545 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3546 } 3547 break; 3548 3549 case e1000_82573: 3550 ctrl |= E1000_CTRL_ILOS; 3551 break; 3552 } 3553 3554 E1000_WRITE_REG(hw, CTRL, ctrl); 3555 3556 /* 3557 * Disable PHY receiver for 82540/545/546 and 82573 Family. 3558 * For background, see comments above e1000g_set_internal_loopback(). 3559 */ 3560 switch (hw->mac_type) { 3561 case e1000_82540: 3562 case e1000_82545: 3563 case e1000_82545_rev_3: 3564 case e1000_82546: 3565 case e1000_82546_rev_3: 3566 case e1000_82573: 3567 e1000_write_phy_reg(hw, 29, 0x001F); 3568 e1000_write_phy_reg(hw, 30, 0x8FFC); 3569 e1000_write_phy_reg(hw, 29, 0x001A); 3570 e1000_write_phy_reg(hw, 30, 0x8FF0); 3571 break; 3572 } 3573 } 3574 3575 static void 3576 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 3577 { 3578 struct e1000_hw *hw; 3579 uint32_t rctl; 3580 uint32_t ctrl_ext; 3581 uint32_t ctrl; 3582 uint32_t status; 3583 uint32_t txcw; 3584 3585 hw = &Adapter->Shared; 3586 3587 /* Disable Smart Power Down */ 3588 phy_spd_state(hw, B_FALSE); 3589 3590 switch (hw->media_type) { 3591 case e1000_media_type_copper: 3592 /* Force link up (Must be done before the PHY writes) */ 3593 ctrl = E1000_READ_REG(hw, CTRL); 3594 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 3595 E1000_WRITE_REG(hw, CTRL, ctrl); 3596 3597 rctl = E1000_READ_REG(hw, RCTL); 3598 rctl |= (E1000_RCTL_EN | 3599 E1000_RCTL_SBP | 3600 E1000_RCTL_UPE | 3601 E1000_RCTL_MPE | 3602 E1000_RCTL_LPE | 3603 E1000_RCTL_BAM); /* 0x803E */ 3604 E1000_WRITE_REG(hw, RCTL, rctl); 3605 3606 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); 3607 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 3608 E1000_CTRL_EXT_SDP6_DATA | 3609 E1000_CTRL_EXT_SDP7_DATA | 3610 E1000_CTRL_EXT_SDP4_DIR | 3611 E1000_CTRL_EXT_SDP6_DIR | 3612 E1000_CTRL_EXT_SDP7_DIR); /* 0x0DD0 */ 3613 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); 3614 3615 /* 3616 * This sequence tunes the PHY's SDP and no customer 3617 * settable values. For background, see comments above 3618 * e1000g_set_internal_loopback(). 3619 */ 3620 e1000_write_phy_reg(hw, 0x0, 0x140); 3621 msec_delay(10); 3622 e1000_write_phy_reg(hw, 0x9, 0x1A00); 3623 e1000_write_phy_reg(hw, 0x12, 0xC10); 3624 e1000_write_phy_reg(hw, 0x12, 0x1C10); 3625 e1000_write_phy_reg(hw, 0x1F37, 0x76); 3626 e1000_write_phy_reg(hw, 0x1F33, 0x1); 3627 e1000_write_phy_reg(hw, 0x1F33, 0x0); 3628 3629 e1000_write_phy_reg(hw, 0x1F35, 0x65); 3630 e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 3631 e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 3632 e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 3633 e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 3634 3635 msec_delay(50); 3636 break; 3637 case e1000_media_type_fiber: 3638 case e1000_media_type_internal_serdes: 3639 status = E1000_READ_REG(hw, STATUS); 3640 if (((status & E1000_STATUS_LU) == 0) || 3641 (hw->media_type == e1000_media_type_internal_serdes)) { 3642 ctrl = E1000_READ_REG(hw, CTRL); 3643 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 3644 E1000_WRITE_REG(hw, CTRL, ctrl); 3645 } 3646 3647 /* Disable autoneg by setting bit 31 of TXCW to zero */ 3648 txcw = E1000_READ_REG(hw, TXCW); 3649 txcw &= ~((uint32_t)1 << 31); 3650 E1000_WRITE_REG(hw, TXCW, txcw); 3651 3652 /* 3653 * Write 0x410 to Serdes Control register 3654 * to enable Serdes analog loopback 3655 */ 3656 E1000_WRITE_REG(hw, SCTL, 0x0410); 3657 msec_delay(10); 3658 break; 3659 default: 3660 break; 3661 } 3662 } 3663 3664 static void 3665 e1000g_set_external_loopback_100(struct e1000g *Adapter) 3666 { 3667 struct e1000_hw *hw; 3668 uint32_t ctrl; 3669 uint16_t phy_ctrl; 3670 3671 hw = &Adapter->Shared; 3672 3673 /* Disable Smart Power Down */ 3674 phy_spd_state(hw, B_FALSE); 3675 3676 phy_ctrl = (MII_CR_FULL_DUPLEX | 3677 MII_CR_SPEED_100); 3678 3679 /* Force 100/FD, reset PHY */ 3680 e1000_write_phy_reg(hw, PHY_CTRL, 3681 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 3682 msec_delay(10); 3683 3684 /* Force 100/FD */ 3685 e1000_write_phy_reg(hw, PHY_CTRL, 3686 phy_ctrl); /* 0x2100 */ 3687 msec_delay(10); 3688 3689 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3690 ctrl = E1000_READ_REG(hw, CTRL); 3691 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3692 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3693 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3694 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3695 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 3696 E1000_CTRL_FD); /* Force Duplex to FULL */ 3697 3698 E1000_WRITE_REG(hw, CTRL, ctrl); 3699 } 3700 3701 static void 3702 e1000g_set_external_loopback_10(struct e1000g *Adapter) 3703 { 3704 struct e1000_hw *hw; 3705 uint32_t ctrl; 3706 uint16_t phy_ctrl; 3707 3708 hw = &Adapter->Shared; 3709 3710 /* Disable Smart Power Down */ 3711 phy_spd_state(hw, B_FALSE); 3712 3713 phy_ctrl = (MII_CR_FULL_DUPLEX | 3714 MII_CR_SPEED_10); 3715 3716 /* Force 10/FD, reset PHY */ 3717 e1000_write_phy_reg(hw, PHY_CTRL, 3718 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 3719 msec_delay(10); 3720 3721 /* Force 10/FD */ 3722 e1000_write_phy_reg(hw, PHY_CTRL, 3723 phy_ctrl); /* 0x0100 */ 3724 msec_delay(10); 3725 3726 /* Now setup the MAC to the same speed/duplex as the PHY. */ 3727 ctrl = E1000_READ_REG(hw, CTRL); 3728 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 3729 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 3730 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 3731 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 3732 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 3733 E1000_CTRL_FD); /* Force Duplex to FULL */ 3734 3735 E1000_WRITE_REG(hw, CTRL, ctrl); 3736 } 3737 3738 #ifdef __sparc 3739 static boolean_t 3740 e1000g_find_mac_address(struct e1000g *Adapter) 3741 { 3742 uchar_t *bytes; 3743 struct ether_addr sysaddr; 3744 uint_t nelts; 3745 int err; 3746 boolean_t found = B_FALSE; 3747 3748 /* 3749 * The "vendor's factory-set address" may already have 3750 * been extracted from the chip, but if the property 3751 * "local-mac-address" is set we use that instead. 3752 * 3753 * We check whether it looks like an array of 6 3754 * bytes (which it should, if OBP set it). If we can't 3755 * make sense of it this way, we'll ignore it. 3756 */ 3757 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3758 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 3759 if (err == DDI_PROP_SUCCESS) { 3760 if (nelts == ETHERADDRL) { 3761 while (nelts--) 3762 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3763 found = B_TRUE; 3764 } 3765 ddi_prop_free(bytes); 3766 } 3767 3768 /* 3769 * Look up the OBP property "local-mac-address?". If the user has set 3770 * 'local-mac-address? = false', use "the system address" instead. 3771 */ 3772 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 3773 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 3774 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 3775 if (localetheraddr(NULL, &sysaddr) != 0) { 3776 bcopy(&sysaddr, Adapter->Shared.mac_addr, 3777 ETHERADDRL); 3778 found = B_TRUE; 3779 } 3780 } 3781 ddi_prop_free(bytes); 3782 } 3783 3784 /* 3785 * Finally(!), if there's a valid "mac-address" property (created 3786 * if we netbooted from this interface), we must use this instead 3787 * of any of the above to ensure that the NFS/install server doesn't 3788 * get confused by the address changing as Solaris takes over! 3789 */ 3790 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 3791 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 3792 if (err == DDI_PROP_SUCCESS) { 3793 if (nelts == ETHERADDRL) { 3794 while (nelts--) 3795 Adapter->Shared.mac_addr[nelts] = bytes[nelts]; 3796 found = B_TRUE; 3797 } 3798 ddi_prop_free(bytes); 3799 } 3800 3801 if (found) { 3802 bcopy(Adapter->Shared.mac_addr, Adapter->Shared.perm_mac_addr, 3803 ETHERADDRL); 3804 } 3805 3806 return (found); 3807 } 3808 #endif 3809 3810 static int 3811 e1000g_add_intrs(struct e1000g *Adapter) 3812 { 3813 dev_info_t *devinfo; 3814 int intr_types; 3815 int rc; 3816 3817 devinfo = Adapter->dip; 3818 3819 /* Get supported interrupt types */ 3820 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 3821 3822 if (rc != DDI_SUCCESS) { 3823 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3824 "Get supported interrupt types failed: %d\n", rc); 3825 return (DDI_FAILURE); 3826 } 3827 3828 /* 3829 * Based on Intel Technical Advisory document (TA-160), there are some 3830 * cases where some older Intel PCI-X NICs may "advertise" to the OS 3831 * that it supports MSI, but in fact has problems. 3832 * So we should only enable MSI for PCI-E NICs and disable MSI for old 3833 * PCI/PCI-X NICs. 3834 */ 3835 if (Adapter->Shared.mac_type < e1000_82571) 3836 Adapter->msi_enabled = B_FALSE; 3837 3838 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enabled) { 3839 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 3840 3841 if (rc != DDI_SUCCESS) { 3842 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3843 "Add MSI failed, trying Legacy interrupts\n"); 3844 } else { 3845 Adapter->intr_type = DDI_INTR_TYPE_MSI; 3846 } 3847 } 3848 3849 if ((Adapter->intr_type == 0) && 3850 (intr_types & DDI_INTR_TYPE_FIXED)) { 3851 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 3852 3853 if (rc != DDI_SUCCESS) { 3854 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3855 "Add Legacy interrupts failed\n"); 3856 return (DDI_FAILURE); 3857 } 3858 3859 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 3860 } 3861 3862 if (Adapter->intr_type == 0) { 3863 e1000g_DEBUGLOG_0(Adapter, e1000g_INFO_LEVEL, 3864 "No interrupts registered\n"); 3865 return (DDI_FAILURE); 3866 } 3867 3868 return (DDI_SUCCESS); 3869 } 3870 3871 /* 3872 * e1000g_intr_add() handles MSI/Legacy interrupts 3873 */ 3874 static int 3875 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 3876 { 3877 dev_info_t *devinfo; 3878 int count, avail, actual; 3879 int x, y, rc, inum = 0; 3880 int flag; 3881 ddi_intr_handler_t *intr_handler; 3882 3883 devinfo = Adapter->dip; 3884 3885 /* get number of interrupts */ 3886 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 3887 if ((rc != DDI_SUCCESS) || (count == 0)) { 3888 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3889 "Get interrupt number failed. Return: %d, count: %d\n", 3890 rc, count); 3891 return (DDI_FAILURE); 3892 } 3893 3894 /* get number of available interrupts */ 3895 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 3896 if ((rc != DDI_SUCCESS) || (avail == 0)) { 3897 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3898 "Get interrupt available number failed. " 3899 "Return: %d, available: %d\n", rc, avail); 3900 return (DDI_FAILURE); 3901 } 3902 3903 if (avail < count) { 3904 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3905 "Interrupts count: %d, available: %d\n", 3906 count, avail); 3907 } 3908 3909 /* Allocate an array of interrupt handles */ 3910 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 3911 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 3912 3913 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 3914 flag = DDI_INTR_ALLOC_NORMAL; 3915 3916 /* call ddi_intr_alloc() */ 3917 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 3918 count, &actual, flag); 3919 3920 if ((rc != DDI_SUCCESS) || (actual == 0)) { 3921 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3922 "Allocate interrupts failed: %d\n", rc); 3923 3924 kmem_free(Adapter->htable, Adapter->intr_size); 3925 return (DDI_FAILURE); 3926 } 3927 3928 if (actual < count) { 3929 e1000g_DEBUGLOG_2(Adapter, e1000g_INFO_LEVEL, 3930 "Interrupts requested: %d, received: %d\n", 3931 count, actual); 3932 } 3933 3934 Adapter->intr_cnt = actual; 3935 3936 /* Get priority for first msi, assume remaining are all the same */ 3937 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 3938 3939 if (rc != DDI_SUCCESS) { 3940 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3941 "Get interrupt priority failed: %d\n", rc); 3942 3943 /* Free already allocated intr */ 3944 for (y = 0; y < actual; y++) 3945 (void) ddi_intr_free(Adapter->htable[y]); 3946 3947 kmem_free(Adapter->htable, Adapter->intr_size); 3948 return (DDI_FAILURE); 3949 } 3950 3951 /* 3952 * In Legacy Interrupt mode, for PCI-Express adapters, we should 3953 * use the interrupt service routine e1000g_intr_pciexpress() 3954 * to avoid interrupt stealing when sharing interrupt with other 3955 * devices. 3956 */ 3957 if (Adapter->Shared.mac_type < e1000_82571) 3958 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 3959 else 3960 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 3961 3962 /* Call ddi_intr_add_handler() */ 3963 for (x = 0; x < actual; x++) { 3964 rc = ddi_intr_add_handler(Adapter->htable[x], 3965 intr_handler, (caddr_t)Adapter, NULL); 3966 3967 if (rc != DDI_SUCCESS) { 3968 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3969 "Add interrupt handler failed: %d\n", rc); 3970 3971 /* Remove already added handler */ 3972 for (y = 0; y < x; y++) 3973 (void) ddi_intr_remove_handler( 3974 Adapter->htable[y]); 3975 3976 /* Free already allocated intr */ 3977 for (y = 0; y < actual; y++) 3978 (void) ddi_intr_free(Adapter->htable[y]); 3979 3980 kmem_free(Adapter->htable, Adapter->intr_size); 3981 return (DDI_FAILURE); 3982 } 3983 } 3984 3985 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 3986 3987 if (rc != DDI_SUCCESS) { 3988 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 3989 "Get interrupt cap failed: %d\n", rc); 3990 3991 /* Free already allocated intr */ 3992 for (y = 0; y < actual; y++) { 3993 (void) ddi_intr_remove_handler(Adapter->htable[y]); 3994 (void) ddi_intr_free(Adapter->htable[y]); 3995 } 3996 3997 kmem_free(Adapter->htable, Adapter->intr_size); 3998 return (DDI_FAILURE); 3999 } 4000 4001 return (DDI_SUCCESS); 4002 } 4003 4004 static int 4005 e1000g_rem_intrs(struct e1000g *Adapter) 4006 { 4007 int x; 4008 int rc; 4009 4010 for (x = 0; x < Adapter->intr_cnt; x++) { 4011 rc = ddi_intr_remove_handler(Adapter->htable[x]); 4012 if (rc != DDI_SUCCESS) { 4013 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4014 "Remove intr handler failed: %d\n", rc); 4015 return (DDI_FAILURE); 4016 } 4017 4018 rc = ddi_intr_free(Adapter->htable[x]); 4019 if (rc != DDI_SUCCESS) { 4020 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4021 "Free intr failed: %d\n", rc); 4022 return (DDI_FAILURE); 4023 } 4024 } 4025 4026 kmem_free(Adapter->htable, Adapter->intr_size); 4027 4028 return (DDI_SUCCESS); 4029 } 4030 4031 static int 4032 e1000g_enable_intrs(struct e1000g *Adapter) 4033 { 4034 int x; 4035 int rc; 4036 4037 /* Enable interrupts */ 4038 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4039 /* Call ddi_intr_block_enable() for MSI */ 4040 rc = ddi_intr_block_enable(Adapter->htable, 4041 Adapter->intr_cnt); 4042 if (rc != DDI_SUCCESS) { 4043 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4044 "Enable block intr failed: %d\n", rc); 4045 return (DDI_FAILURE); 4046 } 4047 } else { 4048 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 4049 for (x = 0; x < Adapter->intr_cnt; x++) { 4050 rc = ddi_intr_enable(Adapter->htable[x]); 4051 if (rc != DDI_SUCCESS) { 4052 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4053 "Enable intr failed: %d\n", rc); 4054 return (DDI_FAILURE); 4055 } 4056 } 4057 } 4058 4059 return (DDI_SUCCESS); 4060 } 4061 4062 static int 4063 e1000g_disable_intrs(struct e1000g *Adapter) 4064 { 4065 int x; 4066 int rc; 4067 4068 /* Disable all interrupts */ 4069 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 4070 rc = ddi_intr_block_disable(Adapter->htable, 4071 Adapter->intr_cnt); 4072 if (rc != DDI_SUCCESS) { 4073 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4074 "Disable block intr failed: %d\n", rc); 4075 return (DDI_FAILURE); 4076 } 4077 } else { 4078 for (x = 0; x < Adapter->intr_cnt; x++) { 4079 rc = ddi_intr_disable(Adapter->htable[x]); 4080 if (rc != DDI_SUCCESS) { 4081 e1000g_DEBUGLOG_1(Adapter, e1000g_INFO_LEVEL, 4082 "Disable intr failed: %d\n", rc); 4083 return (DDI_FAILURE); 4084 } 4085 } 4086 } 4087 4088 return (DDI_SUCCESS); 4089 } 4090 4091 /* 4092 * phy_spd_state - set smart-power-down (SPD) state 4093 * 4094 * This only acts on the 82541/47 family and the 82571/72 family. 4095 * For any others, return without doing anything. 4096 */ 4097 void 4098 phy_spd_state(struct e1000_hw *hw, boolean_t enable) 4099 { 4100 int32_t offset; /* offset to register */ 4101 uint16_t spd_bit; /* bit to be set */ 4102 uint16_t reg; /* register contents */ 4103 4104 switch (hw->mac_type) { 4105 case e1000_82541: 4106 case e1000_82547: 4107 case e1000_82541_rev_2: 4108 case e1000_82547_rev_2: 4109 offset = IGP01E1000_GMII_FIFO; 4110 spd_bit = IGP01E1000_GMII_SPD; 4111 break; 4112 case e1000_82571: 4113 case e1000_82572: 4114 offset = IGP02E1000_PHY_POWER_MGMT; 4115 spd_bit = IGP02E1000_PM_SPD; 4116 break; 4117 default: 4118 return; /* no action */ 4119 } 4120 4121 e1000_read_phy_reg(hw, offset, ®); 4122 4123 if (enable) 4124 reg |= spd_bit; /* enable: set the spd bit */ 4125 else 4126 reg &= ~spd_bit; /* disable: clear the spd bit */ 4127 4128 e1000_write_phy_reg(hw, offset, reg); 4129 } 4130 4131 /* 4132 * The real intent of this routine is to return the value from pci-e 4133 * config space at offset reg into the capability space. 4134 * ICH devices are "PCI Express"-ish. They have a configuration space, 4135 * but do not contain PCI Express Capability registers, so this returns 4136 * the equivalent of "not supported" 4137 */ 4138 int32_t 4139 e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value) 4140 { 4141 *value = pci_config_get16(((struct e1000g_osdep *)hw->back)->handle, 4142 PCI_EX_CONF_CAP + reg); 4143 4144 return (0); 4145 } 4146 4147 /* 4148 * Enables PCI-Express master access. 4149 * 4150 * hw: Struct containing variables accessed by shared code 4151 * 4152 * returns: - none. 4153 */ 4154 void 4155 e1000_enable_pciex_master(struct e1000_hw *hw) 4156 { 4157 uint32_t ctrl; 4158 4159 if (hw->bus_type != e1000_bus_type_pci_express) 4160 return; 4161 4162 ctrl = E1000_READ_REG(hw, CTRL); 4163 ctrl &= ~E1000_CTRL_GIO_MASTER_DISABLE; 4164 E1000_WRITE_REG(hw, CTRL, ctrl); 4165 } 4166