1 /* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * ********************************************************************** 28 * * 29 * Module Name: * 30 * e1000g_main.c * 31 * * 32 * Abstract: * 33 * This file contains the interface routines for the solaris OS. * 34 * It has all DDI entry point routines and GLD entry point routines. * 35 * * 36 * This file also contains routines that take care of initialization * 37 * uninit routine and interrupt routine. * 38 * * 39 * ********************************************************************** 40 */ 41 42 #include <sys/dlpi.h> 43 #include <sys/mac.h> 44 #include "e1000g_sw.h" 45 #include "e1000g_debug.h" 46 47 static char ident[] = "Intel PRO/1000 Ethernet"; 48 static char e1000g_string[] = "Intel(R) PRO/1000 Network Connection"; 49 static char e1000g_version[] = "Driver Ver. 5.3.22"; 50 51 /* 52 * Proto types for DDI entry points 53 */ 54 static int e1000g_attach(dev_info_t *, ddi_attach_cmd_t); 55 static int e1000g_detach(dev_info_t *, ddi_detach_cmd_t); 56 static int e1000g_quiesce(dev_info_t *); 57 58 /* 59 * init and intr routines prototype 60 */ 61 static int e1000g_resume(dev_info_t *); 62 static int e1000g_suspend(dev_info_t *); 63 static uint_t e1000g_intr_pciexpress(caddr_t); 64 static uint_t e1000g_intr(caddr_t); 65 static void e1000g_intr_work(struct e1000g *, uint32_t); 66 #pragma inline(e1000g_intr_work) 67 static int e1000g_init(struct e1000g *); 68 static int e1000g_start(struct e1000g *, boolean_t); 69 static void e1000g_stop(struct e1000g *, boolean_t); 70 static int e1000g_m_start(void *); 71 static void e1000g_m_stop(void *); 72 static int e1000g_m_promisc(void *, boolean_t); 73 static boolean_t e1000g_m_getcapab(void *, mac_capab_t, void *); 74 static int e1000g_m_multicst(void *, boolean_t, const uint8_t *); 75 static void e1000g_m_ioctl(void *, queue_t *, mblk_t *); 76 static int e1000g_m_setprop(void *, const char *, mac_prop_id_t, 77 uint_t, const void *); 78 static int e1000g_m_getprop(void *, const char *, mac_prop_id_t, 79 uint_t, uint_t, void *, uint_t *); 80 static int e1000g_set_priv_prop(struct e1000g *, const char *, uint_t, 81 const void *); 82 static int e1000g_get_priv_prop(struct e1000g *, const char *, uint_t, 83 uint_t, void *, uint_t *); 84 static void e1000g_init_locks(struct e1000g *); 85 static void e1000g_destroy_locks(struct e1000g *); 86 static int e1000g_identify_hardware(struct e1000g *); 87 static int e1000g_regs_map(struct e1000g *); 88 static int e1000g_set_driver_params(struct e1000g *); 89 static void e1000g_set_bufsize(struct e1000g *); 90 static int e1000g_register_mac(struct e1000g *); 91 static boolean_t e1000g_rx_drain(struct e1000g *); 92 static boolean_t e1000g_tx_drain(struct e1000g *); 93 static void e1000g_init_unicst(struct e1000g *); 94 static int e1000g_unicst_set(struct e1000g *, const uint8_t *, int); 95 static int e1000g_alloc_rx_data(struct e1000g *); 96 static void e1000g_release_multicast(struct e1000g *); 97 static void e1000g_pch_limits(struct e1000g *); 98 static uint32_t e1000g_mtu2maxframe(uint32_t); 99 100 /* 101 * Local routines 102 */ 103 static boolean_t e1000g_reset_adapter(struct e1000g *); 104 static void e1000g_tx_clean(struct e1000g *); 105 static void e1000g_rx_clean(struct e1000g *); 106 static void e1000g_link_timer(void *); 107 static void e1000g_local_timer(void *); 108 static boolean_t e1000g_link_check(struct e1000g *); 109 static boolean_t e1000g_stall_check(struct e1000g *); 110 static void e1000g_smartspeed(struct e1000g *); 111 static void e1000g_get_conf(struct e1000g *); 112 static boolean_t e1000g_get_prop(struct e1000g *, char *, int, int, int, 113 int *); 114 static void enable_watchdog_timer(struct e1000g *); 115 static void disable_watchdog_timer(struct e1000g *); 116 static void start_watchdog_timer(struct e1000g *); 117 static void restart_watchdog_timer(struct e1000g *); 118 static void stop_watchdog_timer(struct e1000g *); 119 static void stop_link_timer(struct e1000g *); 120 static void stop_82547_timer(e1000g_tx_ring_t *); 121 static void e1000g_force_speed_duplex(struct e1000g *); 122 static void e1000g_setup_max_mtu(struct e1000g *); 123 static void e1000g_get_max_frame_size(struct e1000g *); 124 static boolean_t is_valid_mac_addr(uint8_t *); 125 static void e1000g_unattach(dev_info_t *, struct e1000g *); 126 static int e1000g_get_bar_info(dev_info_t *, int, bar_info_t *); 127 #ifdef E1000G_DEBUG 128 static void e1000g_ioc_peek_reg(struct e1000g *, e1000g_peekpoke_t *); 129 static void e1000g_ioc_poke_reg(struct e1000g *, e1000g_peekpoke_t *); 130 static void e1000g_ioc_peek_mem(struct e1000g *, e1000g_peekpoke_t *); 131 static void e1000g_ioc_poke_mem(struct e1000g *, e1000g_peekpoke_t *); 132 static enum ioc_reply e1000g_pp_ioctl(struct e1000g *, 133 struct iocblk *, mblk_t *); 134 #endif 135 static enum ioc_reply e1000g_loopback_ioctl(struct e1000g *, 136 struct iocblk *, mblk_t *); 137 static boolean_t e1000g_check_loopback_support(struct e1000_hw *); 138 static boolean_t e1000g_set_loopback_mode(struct e1000g *, uint32_t); 139 static void e1000g_set_internal_loopback(struct e1000g *); 140 static void e1000g_set_external_loopback_1000(struct e1000g *); 141 static void e1000g_set_external_loopback_100(struct e1000g *); 142 static void e1000g_set_external_loopback_10(struct e1000g *); 143 static int e1000g_add_intrs(struct e1000g *); 144 static int e1000g_intr_add(struct e1000g *, int); 145 static int e1000g_rem_intrs(struct e1000g *); 146 static int e1000g_enable_intrs(struct e1000g *); 147 static int e1000g_disable_intrs(struct e1000g *); 148 static boolean_t e1000g_link_up(struct e1000g *); 149 #ifdef __sparc 150 static boolean_t e1000g_find_mac_address(struct e1000g *); 151 #endif 152 static void e1000g_get_phy_state(struct e1000g *); 153 static int e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, 154 const void *impl_data); 155 static void e1000g_fm_init(struct e1000g *Adapter); 156 static void e1000g_fm_fini(struct e1000g *Adapter); 157 static int e1000g_get_def_val(struct e1000g *, mac_prop_id_t, uint_t, void *); 158 static void e1000g_param_sync(struct e1000g *); 159 static void e1000g_get_driver_control(struct e1000_hw *); 160 static void e1000g_release_driver_control(struct e1000_hw *); 161 static void e1000g_restore_promisc(struct e1000g *Adapter); 162 163 mac_priv_prop_t e1000g_priv_props[] = { 164 {"_tx_bcopy_threshold", MAC_PROP_PERM_RW}, 165 {"_tx_interrupt_enable", MAC_PROP_PERM_RW}, 166 {"_tx_intr_delay", MAC_PROP_PERM_RW}, 167 {"_tx_intr_abs_delay", MAC_PROP_PERM_RW}, 168 {"_rx_bcopy_threshold", MAC_PROP_PERM_RW}, 169 {"_max_num_rcv_packets", MAC_PROP_PERM_RW}, 170 {"_rx_intr_delay", MAC_PROP_PERM_RW}, 171 {"_rx_intr_abs_delay", MAC_PROP_PERM_RW}, 172 {"_intr_throttling_rate", MAC_PROP_PERM_RW}, 173 {"_intr_adaptive", MAC_PROP_PERM_RW}, 174 {"_adv_pause_cap", MAC_PROP_PERM_READ}, 175 {"_adv_asym_pause_cap", MAC_PROP_PERM_READ}, 176 }; 177 #define E1000G_MAX_PRIV_PROPS \ 178 (sizeof (e1000g_priv_props)/sizeof (mac_priv_prop_t)) 179 180 181 static struct cb_ops cb_ws_ops = { 182 nulldev, /* cb_open */ 183 nulldev, /* cb_close */ 184 nodev, /* cb_strategy */ 185 nodev, /* cb_print */ 186 nodev, /* cb_dump */ 187 nodev, /* cb_read */ 188 nodev, /* cb_write */ 189 nodev, /* cb_ioctl */ 190 nodev, /* cb_devmap */ 191 nodev, /* cb_mmap */ 192 nodev, /* cb_segmap */ 193 nochpoll, /* cb_chpoll */ 194 ddi_prop_op, /* cb_prop_op */ 195 NULL, /* cb_stream */ 196 D_MP | D_HOTPLUG, /* cb_flag */ 197 CB_REV, /* cb_rev */ 198 nodev, /* cb_aread */ 199 nodev /* cb_awrite */ 200 }; 201 202 static struct dev_ops ws_ops = { 203 DEVO_REV, /* devo_rev */ 204 0, /* devo_refcnt */ 205 NULL, /* devo_getinfo */ 206 nulldev, /* devo_identify */ 207 nulldev, /* devo_probe */ 208 e1000g_attach, /* devo_attach */ 209 e1000g_detach, /* devo_detach */ 210 nodev, /* devo_reset */ 211 &cb_ws_ops, /* devo_cb_ops */ 212 NULL, /* devo_bus_ops */ 213 ddi_power, /* devo_power */ 214 e1000g_quiesce /* devo_quiesce */ 215 }; 216 217 static struct modldrv modldrv = { 218 &mod_driverops, /* Type of module. This one is a driver */ 219 ident, /* Discription string */ 220 &ws_ops, /* driver ops */ 221 }; 222 223 static struct modlinkage modlinkage = { 224 MODREV_1, &modldrv, NULL 225 }; 226 227 /* Access attributes for register mapping */ 228 static ddi_device_acc_attr_t e1000g_regs_acc_attr = { 229 DDI_DEVICE_ATTR_V1, 230 DDI_STRUCTURE_LE_ACC, 231 DDI_STRICTORDER_ACC, 232 DDI_FLAGERR_ACC 233 }; 234 235 #define E1000G_M_CALLBACK_FLAGS \ 236 (MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 237 238 static mac_callbacks_t e1000g_m_callbacks = { 239 E1000G_M_CALLBACK_FLAGS, 240 e1000g_m_stat, 241 e1000g_m_start, 242 e1000g_m_stop, 243 e1000g_m_promisc, 244 e1000g_m_multicst, 245 NULL, 246 e1000g_m_tx, 247 e1000g_m_ioctl, 248 e1000g_m_getcapab, 249 NULL, 250 NULL, 251 e1000g_m_setprop, 252 e1000g_m_getprop 253 }; 254 255 /* 256 * Global variables 257 */ 258 uint32_t e1000g_mblks_pending = 0; 259 /* 260 * Workaround for Dynamic Reconfiguration support, for x86 platform only. 261 * Here we maintain a private dev_info list if e1000g_force_detach is 262 * enabled. If we force the driver to detach while there are still some 263 * rx buffers retained in the upper layer, we have to keep a copy of the 264 * dev_info. In some cases (Dynamic Reconfiguration), the dev_info data 265 * structure will be freed after the driver is detached. However when we 266 * finally free those rx buffers released by the upper layer, we need to 267 * refer to the dev_info to free the dma buffers. So we save a copy of 268 * the dev_info for this purpose. On x86 platform, we assume this copy 269 * of dev_info is always valid, but on SPARC platform, it could be invalid 270 * after the system board level DR operation. For this reason, the global 271 * variable e1000g_force_detach must be B_FALSE on SPARC platform. 272 */ 273 #ifdef __sparc 274 boolean_t e1000g_force_detach = B_FALSE; 275 #else 276 boolean_t e1000g_force_detach = B_TRUE; 277 #endif 278 private_devi_list_t *e1000g_private_devi_list = NULL; 279 280 /* 281 * The mutex e1000g_rx_detach_lock is defined to protect the processing of 282 * the private dev_info list, and to serialize the processing of rx buffer 283 * freeing and rx buffer recycling. 284 */ 285 kmutex_t e1000g_rx_detach_lock; 286 /* 287 * The rwlock e1000g_dma_type_lock is defined to protect the global flag 288 * e1000g_dma_type. For SPARC, the initial value of the flag is "USE_DVMA". 289 * If there are many e1000g instances, the system may run out of DVMA 290 * resources during the initialization of the instances, then the flag will 291 * be changed to "USE_DMA". Because different e1000g instances are initialized 292 * in parallel, we need to use this lock to protect the flag. 293 */ 294 krwlock_t e1000g_dma_type_lock; 295 296 /* 297 * The 82546 chipset is a dual-port device, both the ports share one eeprom. 298 * Based on the information from Intel, the 82546 chipset has some hardware 299 * problem. When one port is being reset and the other port is trying to 300 * access the eeprom, it could cause system hang or panic. To workaround this 301 * hardware problem, we use a global mutex to prevent such operations from 302 * happening simultaneously on different instances. This workaround is applied 303 * to all the devices supported by this driver. 304 */ 305 kmutex_t e1000g_nvm_lock; 306 307 /* 308 * Loadable module configuration entry points for the driver 309 */ 310 311 /* 312 * _init - module initialization 313 */ 314 int 315 _init(void) 316 { 317 int status; 318 319 mac_init_ops(&ws_ops, WSNAME); 320 status = mod_install(&modlinkage); 321 if (status != DDI_SUCCESS) 322 mac_fini_ops(&ws_ops); 323 else { 324 mutex_init(&e1000g_rx_detach_lock, NULL, MUTEX_DRIVER, NULL); 325 rw_init(&e1000g_dma_type_lock, NULL, RW_DRIVER, NULL); 326 mutex_init(&e1000g_nvm_lock, NULL, MUTEX_DRIVER, NULL); 327 } 328 329 return (status); 330 } 331 332 /* 333 * _fini - module finalization 334 */ 335 int 336 _fini(void) 337 { 338 int status; 339 340 if (e1000g_mblks_pending != 0) 341 return (EBUSY); 342 343 status = mod_remove(&modlinkage); 344 if (status == DDI_SUCCESS) { 345 mac_fini_ops(&ws_ops); 346 347 if (e1000g_force_detach) { 348 private_devi_list_t *devi_node; 349 350 mutex_enter(&e1000g_rx_detach_lock); 351 while (e1000g_private_devi_list != NULL) { 352 devi_node = e1000g_private_devi_list; 353 e1000g_private_devi_list = 354 e1000g_private_devi_list->next; 355 356 kmem_free(devi_node->priv_dip, 357 sizeof (struct dev_info)); 358 kmem_free(devi_node, 359 sizeof (private_devi_list_t)); 360 } 361 mutex_exit(&e1000g_rx_detach_lock); 362 } 363 364 mutex_destroy(&e1000g_rx_detach_lock); 365 rw_destroy(&e1000g_dma_type_lock); 366 mutex_destroy(&e1000g_nvm_lock); 367 } 368 369 return (status); 370 } 371 372 /* 373 * _info - module information 374 */ 375 int 376 _info(struct modinfo *modinfop) 377 { 378 return (mod_info(&modlinkage, modinfop)); 379 } 380 381 /* 382 * e1000g_attach - driver attach 383 * 384 * This function is the device-specific initialization entry 385 * point. This entry point is required and must be written. 386 * The DDI_ATTACH command must be provided in the attach entry 387 * point. When attach() is called with cmd set to DDI_ATTACH, 388 * all normal kernel services (such as kmem_alloc(9F)) are 389 * available for use by the driver. 390 * 391 * The attach() function will be called once for each instance 392 * of the device on the system with cmd set to DDI_ATTACH. 393 * Until attach() succeeds, the only driver entry points which 394 * may be called are open(9E) and getinfo(9E). 395 */ 396 static int 397 e1000g_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 398 { 399 struct e1000g *Adapter; 400 struct e1000_hw *hw; 401 struct e1000g_osdep *osdep; 402 int instance; 403 404 switch (cmd) { 405 default: 406 e1000g_log(NULL, CE_WARN, 407 "Unsupported command send to e1000g_attach... "); 408 return (DDI_FAILURE); 409 410 case DDI_RESUME: 411 return (e1000g_resume(devinfo)); 412 413 case DDI_ATTACH: 414 break; 415 } 416 417 /* 418 * get device instance number 419 */ 420 instance = ddi_get_instance(devinfo); 421 422 /* 423 * Allocate soft data structure 424 */ 425 Adapter = 426 (struct e1000g *)kmem_zalloc(sizeof (*Adapter), KM_SLEEP); 427 428 Adapter->dip = devinfo; 429 Adapter->instance = instance; 430 Adapter->tx_ring->adapter = Adapter; 431 Adapter->rx_ring->adapter = Adapter; 432 433 hw = &Adapter->shared; 434 osdep = &Adapter->osdep; 435 hw->back = osdep; 436 osdep->adapter = Adapter; 437 438 ddi_set_driver_private(devinfo, (caddr_t)Adapter); 439 440 /* 441 * Initialize for fma support 442 */ 443 (void) e1000g_get_prop(Adapter, "fm-capable", 444 0, 0x0f, 445 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 446 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE, 447 &Adapter->fm_capabilities); 448 e1000g_fm_init(Adapter); 449 Adapter->attach_progress |= ATTACH_PROGRESS_FMINIT; 450 451 /* 452 * PCI Configure 453 */ 454 if (pci_config_setup(devinfo, &osdep->cfg_handle) != DDI_SUCCESS) { 455 e1000g_log(Adapter, CE_WARN, "PCI configuration failed"); 456 goto attach_fail; 457 } 458 Adapter->attach_progress |= ATTACH_PROGRESS_PCI_CONFIG; 459 460 /* 461 * Setup hardware 462 */ 463 if (e1000g_identify_hardware(Adapter) != DDI_SUCCESS) { 464 e1000g_log(Adapter, CE_WARN, "Identify hardware failed"); 465 goto attach_fail; 466 } 467 468 /* 469 * Map in the device registers. 470 */ 471 if (e1000g_regs_map(Adapter) != DDI_SUCCESS) { 472 e1000g_log(Adapter, CE_WARN, "Mapping registers failed"); 473 goto attach_fail; 474 } 475 Adapter->attach_progress |= ATTACH_PROGRESS_REGS_MAP; 476 477 /* 478 * Initialize driver parameters 479 */ 480 if (e1000g_set_driver_params(Adapter) != DDI_SUCCESS) { 481 goto attach_fail; 482 } 483 Adapter->attach_progress |= ATTACH_PROGRESS_SETUP; 484 485 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 486 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 487 goto attach_fail; 488 } 489 490 /* 491 * Initialize interrupts 492 */ 493 if (e1000g_add_intrs(Adapter) != DDI_SUCCESS) { 494 e1000g_log(Adapter, CE_WARN, "Add interrupts failed"); 495 goto attach_fail; 496 } 497 Adapter->attach_progress |= ATTACH_PROGRESS_ADD_INTR; 498 499 /* 500 * Initialize mutex's for this device. 501 * Do this before enabling the interrupt handler and 502 * register the softint to avoid the condition where 503 * interrupt handler can try using uninitialized mutex 504 */ 505 e1000g_init_locks(Adapter); 506 Adapter->attach_progress |= ATTACH_PROGRESS_LOCKS; 507 508 /* 509 * Initialize Driver Counters 510 */ 511 if (e1000g_init_stats(Adapter) != DDI_SUCCESS) { 512 e1000g_log(Adapter, CE_WARN, "Init stats failed"); 513 goto attach_fail; 514 } 515 Adapter->attach_progress |= ATTACH_PROGRESS_KSTATS; 516 517 /* 518 * Initialize chip hardware and software structures 519 */ 520 rw_enter(&Adapter->chip_lock, RW_WRITER); 521 if (e1000g_init(Adapter) != DDI_SUCCESS) { 522 rw_exit(&Adapter->chip_lock); 523 e1000g_log(Adapter, CE_WARN, "Adapter initialization failed"); 524 goto attach_fail; 525 } 526 rw_exit(&Adapter->chip_lock); 527 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 528 529 /* 530 * Register the driver to the MAC 531 */ 532 if (e1000g_register_mac(Adapter) != DDI_SUCCESS) { 533 e1000g_log(Adapter, CE_WARN, "Register MAC failed"); 534 goto attach_fail; 535 } 536 Adapter->attach_progress |= ATTACH_PROGRESS_MAC; 537 538 /* 539 * Now that mutex locks are initialized, and the chip is also 540 * initialized, enable interrupts. 541 */ 542 if (e1000g_enable_intrs(Adapter) != DDI_SUCCESS) { 543 e1000g_log(Adapter, CE_WARN, "Enable DDI interrupts failed"); 544 goto attach_fail; 545 } 546 Adapter->attach_progress |= ATTACH_PROGRESS_ENABLE_INTR; 547 548 /* 549 * If e1000g_force_detach is enabled, in global private dip list, 550 * we will create a new entry, which maintains the priv_dip for DR 551 * supports after driver detached. 552 */ 553 if (e1000g_force_detach) { 554 private_devi_list_t *devi_node; 555 556 Adapter->priv_dip = 557 kmem_zalloc(sizeof (struct dev_info), KM_SLEEP); 558 bcopy(DEVI(devinfo), DEVI(Adapter->priv_dip), 559 sizeof (struct dev_info)); 560 561 devi_node = 562 kmem_zalloc(sizeof (private_devi_list_t), KM_SLEEP); 563 564 mutex_enter(&e1000g_rx_detach_lock); 565 devi_node->priv_dip = Adapter->priv_dip; 566 devi_node->flag = E1000G_PRIV_DEVI_ATTACH; 567 devi_node->pending_rx_count = 0; 568 569 Adapter->priv_devi_node = devi_node; 570 571 if (e1000g_private_devi_list == NULL) { 572 devi_node->prev = NULL; 573 devi_node->next = NULL; 574 e1000g_private_devi_list = devi_node; 575 } else { 576 devi_node->prev = NULL; 577 devi_node->next = e1000g_private_devi_list; 578 e1000g_private_devi_list->prev = devi_node; 579 e1000g_private_devi_list = devi_node; 580 } 581 mutex_exit(&e1000g_rx_detach_lock); 582 } 583 584 cmn_err(CE_CONT, "!%s, %s\n", e1000g_string, e1000g_version); 585 Adapter->e1000g_state = E1000G_INITIALIZED; 586 587 return (DDI_SUCCESS); 588 589 attach_fail: 590 e1000g_unattach(devinfo, Adapter); 591 return (DDI_FAILURE); 592 } 593 594 static int 595 e1000g_register_mac(struct e1000g *Adapter) 596 { 597 struct e1000_hw *hw = &Adapter->shared; 598 mac_register_t *mac; 599 int err; 600 601 if ((mac = mac_alloc(MAC_VERSION)) == NULL) 602 return (DDI_FAILURE); 603 604 mac->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 605 mac->m_driver = Adapter; 606 mac->m_dip = Adapter->dip; 607 mac->m_src_addr = hw->mac.addr; 608 mac->m_callbacks = &e1000g_m_callbacks; 609 mac->m_min_sdu = 0; 610 mac->m_max_sdu = Adapter->default_mtu; 611 mac->m_margin = VLAN_TAGSZ; 612 mac->m_priv_props = e1000g_priv_props; 613 mac->m_priv_prop_count = E1000G_MAX_PRIV_PROPS; 614 mac->m_v12n = MAC_VIRT_LEVEL1; 615 616 err = mac_register(mac, &Adapter->mh); 617 mac_free(mac); 618 619 return (err == 0 ? DDI_SUCCESS : DDI_FAILURE); 620 } 621 622 static int 623 e1000g_identify_hardware(struct e1000g *Adapter) 624 { 625 struct e1000_hw *hw = &Adapter->shared; 626 struct e1000g_osdep *osdep = &Adapter->osdep; 627 628 /* Get the device id */ 629 hw->vendor_id = 630 pci_config_get16(osdep->cfg_handle, PCI_CONF_VENID); 631 hw->device_id = 632 pci_config_get16(osdep->cfg_handle, PCI_CONF_DEVID); 633 hw->revision_id = 634 pci_config_get8(osdep->cfg_handle, PCI_CONF_REVID); 635 hw->subsystem_device_id = 636 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBSYSID); 637 hw->subsystem_vendor_id = 638 pci_config_get16(osdep->cfg_handle, PCI_CONF_SUBVENID); 639 640 if (e1000_set_mac_type(hw) != E1000_SUCCESS) { 641 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 642 "MAC type could not be set properly."); 643 return (DDI_FAILURE); 644 } 645 646 return (DDI_SUCCESS); 647 } 648 649 static int 650 e1000g_regs_map(struct e1000g *Adapter) 651 { 652 dev_info_t *devinfo = Adapter->dip; 653 struct e1000_hw *hw = &Adapter->shared; 654 struct e1000g_osdep *osdep = &Adapter->osdep; 655 off_t mem_size; 656 bar_info_t bar_info; 657 int offset, rnumber; 658 659 rnumber = ADAPTER_REG_SET; 660 /* Get size of adapter register memory */ 661 if (ddi_dev_regsize(devinfo, rnumber, &mem_size) != 662 DDI_SUCCESS) { 663 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 664 "ddi_dev_regsize for registers failed"); 665 return (DDI_FAILURE); 666 } 667 668 /* Map adapter register memory */ 669 if ((ddi_regs_map_setup(devinfo, rnumber, 670 (caddr_t *)&hw->hw_addr, 0, mem_size, &e1000g_regs_acc_attr, 671 &osdep->reg_handle)) != DDI_SUCCESS) { 672 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 673 "ddi_regs_map_setup for registers failed"); 674 goto regs_map_fail; 675 } 676 677 /* ICH needs to map flash memory */ 678 switch (hw->mac.type) { 679 case e1000_ich8lan: 680 case e1000_ich9lan: 681 case e1000_ich10lan: 682 case e1000_pchlan: 683 rnumber = ICH_FLASH_REG_SET; 684 685 /* get flash size */ 686 if (ddi_dev_regsize(devinfo, rnumber, 687 &mem_size) != DDI_SUCCESS) { 688 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 689 "ddi_dev_regsize for ICH flash failed"); 690 goto regs_map_fail; 691 } 692 693 /* map flash in */ 694 if (ddi_regs_map_setup(devinfo, rnumber, 695 (caddr_t *)&hw->flash_address, 0, 696 mem_size, &e1000g_regs_acc_attr, 697 &osdep->ich_flash_handle) != DDI_SUCCESS) { 698 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 699 "ddi_regs_map_setup for ICH flash failed"); 700 goto regs_map_fail; 701 } 702 break; 703 default: 704 break; 705 } 706 707 /* map io space */ 708 switch (hw->mac.type) { 709 case e1000_82544: 710 case e1000_82540: 711 case e1000_82545: 712 case e1000_82546: 713 case e1000_82541: 714 case e1000_82541_rev_2: 715 /* find the IO bar */ 716 rnumber = -1; 717 for (offset = PCI_CONF_BASE1; 718 offset <= PCI_CONF_BASE5; offset += 4) { 719 if (e1000g_get_bar_info(devinfo, offset, &bar_info) 720 != DDI_SUCCESS) 721 continue; 722 if (bar_info.type == E1000G_BAR_IO) { 723 rnumber = bar_info.rnumber; 724 break; 725 } 726 } 727 728 if (rnumber < 0) { 729 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 730 "No io space is found"); 731 goto regs_map_fail; 732 } 733 734 /* get io space size */ 735 if (ddi_dev_regsize(devinfo, rnumber, 736 &mem_size) != DDI_SUCCESS) { 737 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 738 "ddi_dev_regsize for io space failed"); 739 goto regs_map_fail; 740 } 741 742 /* map io space */ 743 if ((ddi_regs_map_setup(devinfo, rnumber, 744 (caddr_t *)&hw->io_base, 0, mem_size, 745 &e1000g_regs_acc_attr, 746 &osdep->io_reg_handle)) != DDI_SUCCESS) { 747 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 748 "ddi_regs_map_setup for io space failed"); 749 goto regs_map_fail; 750 } 751 break; 752 default: 753 hw->io_base = 0; 754 break; 755 } 756 757 return (DDI_SUCCESS); 758 759 regs_map_fail: 760 if (osdep->reg_handle != NULL) 761 ddi_regs_map_free(&osdep->reg_handle); 762 if (osdep->ich_flash_handle != NULL) 763 ddi_regs_map_free(&osdep->ich_flash_handle); 764 return (DDI_FAILURE); 765 } 766 767 static int 768 e1000g_set_driver_params(struct e1000g *Adapter) 769 { 770 struct e1000_hw *hw; 771 772 hw = &Adapter->shared; 773 774 /* Set MAC type and initialize hardware functions */ 775 if (e1000_setup_init_funcs(hw, B_TRUE) != E1000_SUCCESS) { 776 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 777 "Could not setup hardware functions"); 778 return (DDI_FAILURE); 779 } 780 781 /* Get bus information */ 782 if (e1000_get_bus_info(hw) != E1000_SUCCESS) { 783 E1000G_DEBUGLOG_0(Adapter, CE_WARN, 784 "Could not get bus information"); 785 return (DDI_FAILURE); 786 } 787 788 e1000_read_pci_cfg(hw, PCI_COMMAND_REGISTER, &hw->bus.pci_cmd_word); 789 790 hw->mac.autoneg_failed = B_TRUE; 791 792 /* Set the autoneg_wait_to_complete flag to B_FALSE */ 793 hw->phy.autoneg_wait_to_complete = B_FALSE; 794 795 /* Adaptive IFS related changes */ 796 hw->mac.adaptive_ifs = B_TRUE; 797 798 /* Enable phy init script for IGP phy of 82541/82547 */ 799 if ((hw->mac.type == e1000_82547) || 800 (hw->mac.type == e1000_82541) || 801 (hw->mac.type == e1000_82547_rev_2) || 802 (hw->mac.type == e1000_82541_rev_2)) 803 e1000_init_script_state_82541(hw, B_TRUE); 804 805 /* Enable the TTL workaround for 82541/82547 */ 806 e1000_set_ttl_workaround_state_82541(hw, B_TRUE); 807 808 #ifdef __sparc 809 Adapter->strip_crc = B_TRUE; 810 #else 811 Adapter->strip_crc = B_FALSE; 812 #endif 813 814 /* setup the maximum MTU size of the chip */ 815 e1000g_setup_max_mtu(Adapter); 816 817 /* Get speed/duplex settings in conf file */ 818 hw->mac.forced_speed_duplex = ADVERTISE_100_FULL; 819 hw->phy.autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 820 e1000g_force_speed_duplex(Adapter); 821 822 /* Get Jumbo Frames settings in conf file */ 823 e1000g_get_max_frame_size(Adapter); 824 825 /* Get conf file properties */ 826 e1000g_get_conf(Adapter); 827 828 /* enforce PCH limits */ 829 e1000g_pch_limits(Adapter); 830 831 /* Set Rx/Tx buffer size */ 832 e1000g_set_bufsize(Adapter); 833 834 /* Master Latency Timer */ 835 Adapter->master_latency_timer = DEFAULT_MASTER_LATENCY_TIMER; 836 837 /* copper options */ 838 if (hw->phy.media_type == e1000_media_type_copper) { 839 hw->phy.mdix = 0; /* AUTO_ALL_MODES */ 840 hw->phy.disable_polarity_correction = B_FALSE; 841 hw->phy.ms_type = e1000_ms_hw_default; /* E1000_MASTER_SLAVE */ 842 } 843 844 /* The initial link state should be "unknown" */ 845 Adapter->link_state = LINK_STATE_UNKNOWN; 846 847 /* Initialize rx parameters */ 848 Adapter->rx_intr_delay = DEFAULT_RX_INTR_DELAY; 849 Adapter->rx_intr_abs_delay = DEFAULT_RX_INTR_ABS_DELAY; 850 851 /* Initialize tx parameters */ 852 Adapter->tx_intr_enable = DEFAULT_TX_INTR_ENABLE; 853 Adapter->tx_bcopy_thresh = DEFAULT_TX_BCOPY_THRESHOLD; 854 Adapter->tx_intr_delay = DEFAULT_TX_INTR_DELAY; 855 Adapter->tx_intr_abs_delay = DEFAULT_TX_INTR_ABS_DELAY; 856 857 /* Initialize rx parameters */ 858 Adapter->rx_bcopy_thresh = DEFAULT_RX_BCOPY_THRESHOLD; 859 860 return (DDI_SUCCESS); 861 } 862 863 static void 864 e1000g_setup_max_mtu(struct e1000g *Adapter) 865 { 866 struct e1000_mac_info *mac = &Adapter->shared.mac; 867 struct e1000_phy_info *phy = &Adapter->shared.phy; 868 869 switch (mac->type) { 870 /* types that do not support jumbo frames */ 871 case e1000_ich8lan: 872 case e1000_82573: 873 case e1000_82583: 874 Adapter->max_mtu = ETHERMTU; 875 break; 876 /* ich9 supports jumbo frames except on one phy type */ 877 case e1000_ich9lan: 878 if (phy->type == e1000_phy_ife) 879 Adapter->max_mtu = ETHERMTU; 880 else 881 Adapter->max_mtu = MAXIMUM_MTU_9K; 882 break; 883 /* pch can do jumbo frames up to 4K */ 884 case e1000_pchlan: 885 Adapter->max_mtu = MAXIMUM_MTU_4K; 886 break; 887 /* types with a special limit */ 888 case e1000_82571: 889 case e1000_82572: 890 case e1000_82574: 891 case e1000_80003es2lan: 892 case e1000_ich10lan: 893 Adapter->max_mtu = MAXIMUM_MTU_9K; 894 break; 895 /* default limit is 16K */ 896 default: 897 Adapter->max_mtu = FRAME_SIZE_UPTO_16K - 898 sizeof (struct ether_vlan_header) - ETHERFCSL - 899 E1000G_IPALIGNPRESERVEROOM; 900 break; 901 } 902 } 903 904 static void 905 e1000g_set_bufsize(struct e1000g *Adapter) 906 { 907 struct e1000_mac_info *mac = &Adapter->shared.mac; 908 uint64_t rx_size; 909 uint64_t tx_size; 910 911 dev_info_t *devinfo = Adapter->dip; 912 #ifdef __sparc 913 ulong_t iommu_pagesize; 914 #endif 915 /* Get the system page size */ 916 Adapter->sys_page_sz = ddi_ptob(devinfo, (ulong_t)1); 917 918 #ifdef __sparc 919 iommu_pagesize = dvma_pagesize(devinfo); 920 if (iommu_pagesize != 0) { 921 if (Adapter->sys_page_sz == iommu_pagesize) { 922 if (iommu_pagesize > 0x4000) 923 Adapter->sys_page_sz = 0x4000; 924 } else { 925 if (Adapter->sys_page_sz > iommu_pagesize) 926 Adapter->sys_page_sz = iommu_pagesize; 927 } 928 } 929 if (Adapter->lso_enable) { 930 Adapter->dvma_page_num = E1000_LSO_MAXLEN / 931 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 932 } else { 933 Adapter->dvma_page_num = Adapter->max_frame_size / 934 Adapter->sys_page_sz + E1000G_DEFAULT_DVMA_PAGE_NUM; 935 } 936 ASSERT(Adapter->dvma_page_num >= E1000G_DEFAULT_DVMA_PAGE_NUM); 937 #endif 938 939 Adapter->min_frame_size = ETHERMIN + ETHERFCSL; 940 941 if (Adapter->mem_workaround_82546 && 942 ((mac->type == e1000_82545) || 943 (mac->type == e1000_82546) || 944 (mac->type == e1000_82546_rev_3))) { 945 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K + 946 E1000G_IPALIGNROOM; 947 } else { 948 rx_size = Adapter->max_frame_size + E1000G_IPALIGNPRESERVEROOM; 949 if ((rx_size > FRAME_SIZE_UPTO_2K) && 950 (rx_size <= FRAME_SIZE_UPTO_4K)) 951 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_4K; 952 else if ((rx_size > FRAME_SIZE_UPTO_4K) && 953 (rx_size <= FRAME_SIZE_UPTO_8K)) 954 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_8K; 955 else if ((rx_size > FRAME_SIZE_UPTO_8K) && 956 (rx_size <= FRAME_SIZE_UPTO_16K)) 957 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_16K; 958 else 959 Adapter->rx_buffer_size = E1000_RX_BUFFER_SIZE_2K; 960 } 961 962 tx_size = Adapter->max_frame_size; 963 if ((tx_size > FRAME_SIZE_UPTO_2K) && (tx_size <= FRAME_SIZE_UPTO_4K)) 964 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_4K; 965 else if ((tx_size > FRAME_SIZE_UPTO_4K) && 966 (tx_size <= FRAME_SIZE_UPTO_8K)) 967 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_8K; 968 else if ((tx_size > FRAME_SIZE_UPTO_8K) && 969 (tx_size <= FRAME_SIZE_UPTO_16K)) 970 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_16K; 971 else 972 Adapter->tx_buffer_size = E1000_TX_BUFFER_SIZE_2K; 973 974 /* 975 * For Wiseman adapters we have an requirement of having receive 976 * buffers aligned at 256 byte boundary. Since Livengood does not 977 * require this and forcing it for all hardwares will have 978 * performance implications, I am making it applicable only for 979 * Wiseman and for Jumbo frames enabled mode as rest of the time, 980 * it is okay to have normal frames...but it does involve a 981 * potential risk where we may loose data if buffer is not 982 * aligned...so all wiseman boards to have 256 byte aligned 983 * buffers 984 */ 985 if (mac->type < e1000_82543) 986 Adapter->rx_buf_align = RECEIVE_BUFFER_ALIGN_SIZE; 987 else 988 Adapter->rx_buf_align = 1; 989 } 990 991 /* 992 * e1000g_detach - driver detach 993 * 994 * The detach() function is the complement of the attach routine. 995 * If cmd is set to DDI_DETACH, detach() is used to remove the 996 * state associated with a given instance of a device node 997 * prior to the removal of that instance from the system. 998 * 999 * The detach() function will be called once for each instance 1000 * of the device for which there has been a successful attach() 1001 * once there are no longer any opens on the device. 1002 * 1003 * Interrupts routine are disabled, All memory allocated by this 1004 * driver are freed. 1005 */ 1006 static int 1007 e1000g_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 1008 { 1009 struct e1000g *Adapter; 1010 boolean_t rx_drain; 1011 1012 switch (cmd) { 1013 default: 1014 return (DDI_FAILURE); 1015 1016 case DDI_SUSPEND: 1017 return (e1000g_suspend(devinfo)); 1018 1019 case DDI_DETACH: 1020 break; 1021 } 1022 1023 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1024 if (Adapter == NULL) 1025 return (DDI_FAILURE); 1026 1027 rx_drain = e1000g_rx_drain(Adapter); 1028 if (!rx_drain && !e1000g_force_detach) 1029 return (DDI_FAILURE); 1030 1031 if (mac_unregister(Adapter->mh) != 0) { 1032 e1000g_log(Adapter, CE_WARN, "Unregister MAC failed"); 1033 return (DDI_FAILURE); 1034 } 1035 Adapter->attach_progress &= ~ATTACH_PROGRESS_MAC; 1036 1037 ASSERT(!(Adapter->e1000g_state & E1000G_STARTED)); 1038 1039 if (!e1000g_force_detach && !rx_drain) 1040 return (DDI_FAILURE); 1041 1042 e1000g_unattach(devinfo, Adapter); 1043 1044 return (DDI_SUCCESS); 1045 } 1046 1047 /* 1048 * e1000g_free_priv_devi_node - free a priv_dip entry for driver instance 1049 */ 1050 void 1051 e1000g_free_priv_devi_node(private_devi_list_t *devi_node) 1052 { 1053 ASSERT(e1000g_private_devi_list != NULL); 1054 ASSERT(devi_node != NULL); 1055 1056 if (devi_node->prev != NULL) 1057 devi_node->prev->next = devi_node->next; 1058 if (devi_node->next != NULL) 1059 devi_node->next->prev = devi_node->prev; 1060 if (devi_node == e1000g_private_devi_list) 1061 e1000g_private_devi_list = devi_node->next; 1062 1063 kmem_free(devi_node->priv_dip, 1064 sizeof (struct dev_info)); 1065 kmem_free(devi_node, 1066 sizeof (private_devi_list_t)); 1067 } 1068 1069 static void 1070 e1000g_unattach(dev_info_t *devinfo, struct e1000g *Adapter) 1071 { 1072 private_devi_list_t *devi_node; 1073 int result; 1074 1075 if (Adapter->attach_progress & ATTACH_PROGRESS_ENABLE_INTR) { 1076 (void) e1000g_disable_intrs(Adapter); 1077 } 1078 1079 if (Adapter->attach_progress & ATTACH_PROGRESS_MAC) { 1080 (void) mac_unregister(Adapter->mh); 1081 } 1082 1083 if (Adapter->attach_progress & ATTACH_PROGRESS_ADD_INTR) { 1084 (void) e1000g_rem_intrs(Adapter); 1085 } 1086 1087 if (Adapter->attach_progress & ATTACH_PROGRESS_SETUP) { 1088 (void) ddi_prop_remove_all(devinfo); 1089 } 1090 1091 if (Adapter->attach_progress & ATTACH_PROGRESS_KSTATS) { 1092 kstat_delete((kstat_t *)Adapter->e1000g_ksp); 1093 } 1094 1095 if (Adapter->attach_progress & ATTACH_PROGRESS_INIT) { 1096 stop_link_timer(Adapter); 1097 1098 mutex_enter(&e1000g_nvm_lock); 1099 result = e1000_reset_hw(&Adapter->shared); 1100 mutex_exit(&e1000g_nvm_lock); 1101 1102 if (result != E1000_SUCCESS) { 1103 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1104 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1105 } 1106 } 1107 1108 e1000g_release_multicast(Adapter); 1109 1110 if (Adapter->attach_progress & ATTACH_PROGRESS_REGS_MAP) { 1111 if (Adapter->osdep.reg_handle != NULL) 1112 ddi_regs_map_free(&Adapter->osdep.reg_handle); 1113 if (Adapter->osdep.ich_flash_handle != NULL) 1114 ddi_regs_map_free(&Adapter->osdep.ich_flash_handle); 1115 if (Adapter->osdep.io_reg_handle != NULL) 1116 ddi_regs_map_free(&Adapter->osdep.io_reg_handle); 1117 } 1118 1119 if (Adapter->attach_progress & ATTACH_PROGRESS_PCI_CONFIG) { 1120 if (Adapter->osdep.cfg_handle != NULL) 1121 pci_config_teardown(&Adapter->osdep.cfg_handle); 1122 } 1123 1124 if (Adapter->attach_progress & ATTACH_PROGRESS_LOCKS) { 1125 e1000g_destroy_locks(Adapter); 1126 } 1127 1128 if (Adapter->attach_progress & ATTACH_PROGRESS_FMINIT) { 1129 e1000g_fm_fini(Adapter); 1130 } 1131 1132 mutex_enter(&e1000g_rx_detach_lock); 1133 if (e1000g_force_detach && (Adapter->priv_devi_node != NULL)) { 1134 devi_node = Adapter->priv_devi_node; 1135 devi_node->flag |= E1000G_PRIV_DEVI_DETACH; 1136 1137 if (devi_node->pending_rx_count == 0) { 1138 e1000g_free_priv_devi_node(devi_node); 1139 } 1140 } 1141 mutex_exit(&e1000g_rx_detach_lock); 1142 1143 kmem_free((caddr_t)Adapter, sizeof (struct e1000g)); 1144 1145 /* 1146 * Another hotplug spec requirement, 1147 * run ddi_set_driver_private(devinfo, null); 1148 */ 1149 ddi_set_driver_private(devinfo, NULL); 1150 } 1151 1152 /* 1153 * Get the BAR type and rnumber for a given PCI BAR offset 1154 */ 1155 static int 1156 e1000g_get_bar_info(dev_info_t *dip, int bar_offset, bar_info_t *bar_info) 1157 { 1158 pci_regspec_t *regs; 1159 uint_t regs_length; 1160 int type, rnumber, rcount; 1161 1162 ASSERT((bar_offset >= PCI_CONF_BASE0) && 1163 (bar_offset <= PCI_CONF_BASE5)); 1164 1165 /* 1166 * Get the DDI "reg" property 1167 */ 1168 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 1169 DDI_PROP_DONTPASS, "reg", (int **)®s, 1170 ®s_length) != DDI_PROP_SUCCESS) { 1171 return (DDI_FAILURE); 1172 } 1173 1174 rcount = regs_length * sizeof (int) / sizeof (pci_regspec_t); 1175 /* 1176 * Check the BAR offset 1177 */ 1178 for (rnumber = 0; rnumber < rcount; ++rnumber) { 1179 if (PCI_REG_REG_G(regs[rnumber].pci_phys_hi) == bar_offset) { 1180 type = regs[rnumber].pci_phys_hi & PCI_ADDR_MASK; 1181 break; 1182 } 1183 } 1184 1185 ddi_prop_free(regs); 1186 1187 if (rnumber >= rcount) 1188 return (DDI_FAILURE); 1189 1190 switch (type) { 1191 case PCI_ADDR_CONFIG: 1192 bar_info->type = E1000G_BAR_CONFIG; 1193 break; 1194 case PCI_ADDR_IO: 1195 bar_info->type = E1000G_BAR_IO; 1196 break; 1197 case PCI_ADDR_MEM32: 1198 bar_info->type = E1000G_BAR_MEM32; 1199 break; 1200 case PCI_ADDR_MEM64: 1201 bar_info->type = E1000G_BAR_MEM64; 1202 break; 1203 default: 1204 return (DDI_FAILURE); 1205 } 1206 bar_info->rnumber = rnumber; 1207 return (DDI_SUCCESS); 1208 } 1209 1210 static void 1211 e1000g_init_locks(struct e1000g *Adapter) 1212 { 1213 e1000g_tx_ring_t *tx_ring; 1214 e1000g_rx_ring_t *rx_ring; 1215 1216 rw_init(&Adapter->chip_lock, NULL, 1217 RW_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1218 mutex_init(&Adapter->link_lock, NULL, 1219 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1220 mutex_init(&Adapter->watchdog_lock, NULL, 1221 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1222 1223 tx_ring = Adapter->tx_ring; 1224 1225 mutex_init(&tx_ring->tx_lock, NULL, 1226 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1227 mutex_init(&tx_ring->usedlist_lock, NULL, 1228 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1229 mutex_init(&tx_ring->freelist_lock, NULL, 1230 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1231 1232 rx_ring = Adapter->rx_ring; 1233 1234 mutex_init(&rx_ring->rx_lock, NULL, 1235 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1236 } 1237 1238 static void 1239 e1000g_destroy_locks(struct e1000g *Adapter) 1240 { 1241 e1000g_tx_ring_t *tx_ring; 1242 e1000g_rx_ring_t *rx_ring; 1243 1244 tx_ring = Adapter->tx_ring; 1245 mutex_destroy(&tx_ring->tx_lock); 1246 mutex_destroy(&tx_ring->usedlist_lock); 1247 mutex_destroy(&tx_ring->freelist_lock); 1248 1249 rx_ring = Adapter->rx_ring; 1250 mutex_destroy(&rx_ring->rx_lock); 1251 1252 mutex_destroy(&Adapter->link_lock); 1253 mutex_destroy(&Adapter->watchdog_lock); 1254 rw_destroy(&Adapter->chip_lock); 1255 1256 /* destory mutex initialized in shared code */ 1257 e1000_destroy_hw_mutex(&Adapter->shared); 1258 } 1259 1260 static int 1261 e1000g_resume(dev_info_t *devinfo) 1262 { 1263 struct e1000g *Adapter; 1264 1265 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1266 if (Adapter == NULL) 1267 e1000g_log(Adapter, CE_PANIC, 1268 "Instance pointer is null\n"); 1269 1270 if (Adapter->dip != devinfo) 1271 e1000g_log(Adapter, CE_PANIC, 1272 "Devinfo is not the same as saved devinfo\n"); 1273 1274 rw_enter(&Adapter->chip_lock, RW_WRITER); 1275 1276 if (Adapter->e1000g_state & E1000G_STARTED) { 1277 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 1278 rw_exit(&Adapter->chip_lock); 1279 /* 1280 * We note the failure, but return success, as the 1281 * system is still usable without this controller. 1282 */ 1283 e1000g_log(Adapter, CE_WARN, 1284 "e1000g_resume: failed to restart controller\n"); 1285 return (DDI_SUCCESS); 1286 } 1287 /* Enable and start the watchdog timer */ 1288 enable_watchdog_timer(Adapter); 1289 } 1290 1291 Adapter->e1000g_state &= ~E1000G_SUSPENDED; 1292 1293 rw_exit(&Adapter->chip_lock); 1294 1295 return (DDI_SUCCESS); 1296 } 1297 1298 static int 1299 e1000g_suspend(dev_info_t *devinfo) 1300 { 1301 struct e1000g *Adapter; 1302 1303 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 1304 if (Adapter == NULL) 1305 return (DDI_FAILURE); 1306 1307 rw_enter(&Adapter->chip_lock, RW_WRITER); 1308 1309 Adapter->e1000g_state |= E1000G_SUSPENDED; 1310 1311 /* if the port isn't plumbed, we can simply return */ 1312 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 1313 rw_exit(&Adapter->chip_lock); 1314 return (DDI_SUCCESS); 1315 } 1316 1317 e1000g_stop(Adapter, B_FALSE); 1318 1319 rw_exit(&Adapter->chip_lock); 1320 1321 /* Disable and stop all the timers */ 1322 disable_watchdog_timer(Adapter); 1323 stop_link_timer(Adapter); 1324 stop_82547_timer(Adapter->tx_ring); 1325 1326 return (DDI_SUCCESS); 1327 } 1328 1329 static int 1330 e1000g_init(struct e1000g *Adapter) 1331 { 1332 uint32_t pba; 1333 uint32_t high_water; 1334 struct e1000_hw *hw; 1335 clock_t link_timeout; 1336 int result; 1337 1338 hw = &Adapter->shared; 1339 1340 /* 1341 * reset to put the hardware in a known state 1342 * before we try to do anything with the eeprom 1343 */ 1344 mutex_enter(&e1000g_nvm_lock); 1345 result = e1000_reset_hw(hw); 1346 mutex_exit(&e1000g_nvm_lock); 1347 1348 if (result != E1000_SUCCESS) { 1349 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1350 goto init_fail; 1351 } 1352 1353 mutex_enter(&e1000g_nvm_lock); 1354 result = e1000_validate_nvm_checksum(hw); 1355 if (result < E1000_SUCCESS) { 1356 /* 1357 * Some PCI-E parts fail the first check due to 1358 * the link being in sleep state. Call it again, 1359 * if it fails a second time its a real issue. 1360 */ 1361 result = e1000_validate_nvm_checksum(hw); 1362 } 1363 mutex_exit(&e1000g_nvm_lock); 1364 1365 if (result < E1000_SUCCESS) { 1366 e1000g_log(Adapter, CE_WARN, 1367 "Invalid NVM checksum. Please contact " 1368 "the vendor to update the NVM."); 1369 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1370 goto init_fail; 1371 } 1372 1373 result = 0; 1374 #ifdef __sparc 1375 /* 1376 * First, we try to get the local ethernet address from OBP. If 1377 * failed, then we get it from the EEPROM of NIC card. 1378 */ 1379 result = e1000g_find_mac_address(Adapter); 1380 #endif 1381 /* Get the local ethernet address. */ 1382 if (!result) { 1383 mutex_enter(&e1000g_nvm_lock); 1384 result = e1000_read_mac_addr(hw); 1385 mutex_exit(&e1000g_nvm_lock); 1386 } 1387 1388 if (result < E1000_SUCCESS) { 1389 e1000g_log(Adapter, CE_WARN, "Read mac addr failed"); 1390 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1391 goto init_fail; 1392 } 1393 1394 /* check for valid mac address */ 1395 if (!is_valid_mac_addr(hw->mac.addr)) { 1396 e1000g_log(Adapter, CE_WARN, "Invalid mac addr"); 1397 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1398 goto init_fail; 1399 } 1400 1401 /* Set LAA state for 82571 chipset */ 1402 e1000_set_laa_state_82571(hw, B_TRUE); 1403 1404 /* Master Latency Timer implementation */ 1405 if (Adapter->master_latency_timer) { 1406 pci_config_put8(Adapter->osdep.cfg_handle, 1407 PCI_CONF_LATENCY_TIMER, Adapter->master_latency_timer); 1408 } 1409 1410 if (hw->mac.type < e1000_82547) { 1411 /* 1412 * Total FIFO is 64K 1413 */ 1414 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1415 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */ 1416 else 1417 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */ 1418 } else if ((hw->mac.type == e1000_82571) || 1419 (hw->mac.type == e1000_82572) || 1420 (hw->mac.type == e1000_80003es2lan)) { 1421 /* 1422 * Total FIFO is 48K 1423 */ 1424 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1425 pba = E1000_PBA_30K; /* 30K for Rx, 18K for Tx */ 1426 else 1427 pba = E1000_PBA_38K; /* 38K for Rx, 10K for Tx */ 1428 } else if (hw->mac.type == e1000_82573) { 1429 pba = E1000_PBA_20K; /* 20K for Rx, 12K for Tx */ 1430 } else if (hw->mac.type == e1000_82574) { 1431 /* Keep adapter default: 20K for Rx, 20K for Tx */ 1432 pba = E1000_READ_REG(hw, E1000_PBA); 1433 } else if (hw->mac.type == e1000_ich8lan) { 1434 pba = E1000_PBA_8K; /* 8K for Rx, 12K for Tx */ 1435 } else if (hw->mac.type == e1000_ich9lan) { 1436 pba = E1000_PBA_10K; 1437 } else if (hw->mac.type == e1000_ich10lan) { 1438 pba = E1000_PBA_10K; 1439 } else if (hw->mac.type == e1000_pchlan) { 1440 pba = E1000_PBA_26K; 1441 } else { 1442 /* 1443 * Total FIFO is 40K 1444 */ 1445 if (Adapter->max_frame_size > FRAME_SIZE_UPTO_8K) 1446 pba = E1000_PBA_22K; /* 22K for Rx, 18K for Tx */ 1447 else 1448 pba = E1000_PBA_30K; /* 30K for Rx, 10K for Tx */ 1449 } 1450 E1000_WRITE_REG(hw, E1000_PBA, pba); 1451 1452 /* 1453 * These parameters set thresholds for the adapter's generation(Tx) 1454 * and response(Rx) to Ethernet PAUSE frames. These are just threshold 1455 * settings. Flow control is enabled or disabled in the configuration 1456 * file. 1457 * High-water mark is set down from the top of the rx fifo (not 1458 * sensitive to max_frame_size) and low-water is set just below 1459 * high-water mark. 1460 * The high water mark must be low enough to fit one full frame above 1461 * it in the rx FIFO. Should be the lower of: 1462 * 90% of the Rx FIFO size and the full Rx FIFO size minus the early 1463 * receive size (assuming ERT set to E1000_ERT_2048), or the full 1464 * Rx FIFO size minus one full frame. 1465 */ 1466 high_water = min(((pba << 10) * 9 / 10), 1467 ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574 || 1468 hw->mac.type == e1000_ich9lan || hw->mac.type == e1000_ich10lan) ? 1469 ((pba << 10) - (E1000_ERT_2048 << 3)) : 1470 ((pba << 10) - Adapter->max_frame_size))); 1471 1472 hw->fc.high_water = high_water & 0xFFF8; 1473 hw->fc.low_water = hw->fc.high_water - 8; 1474 1475 if (hw->mac.type == e1000_80003es2lan) 1476 hw->fc.pause_time = 0xFFFF; 1477 else 1478 hw->fc.pause_time = E1000_FC_PAUSE_TIME; 1479 hw->fc.send_xon = B_TRUE; 1480 1481 /* 1482 * Reset the adapter hardware the second time. 1483 */ 1484 mutex_enter(&e1000g_nvm_lock); 1485 result = e1000_reset_hw(hw); 1486 mutex_exit(&e1000g_nvm_lock); 1487 1488 if (result != E1000_SUCCESS) { 1489 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1490 goto init_fail; 1491 } 1492 1493 /* disable wakeup control by default */ 1494 if (hw->mac.type >= e1000_82544) 1495 E1000_WRITE_REG(hw, E1000_WUC, 0); 1496 1497 /* 1498 * MWI should be disabled on 82546. 1499 */ 1500 if (hw->mac.type == e1000_82546) 1501 e1000_pci_clear_mwi(hw); 1502 else 1503 e1000_pci_set_mwi(hw); 1504 1505 /* 1506 * Configure/Initialize hardware 1507 */ 1508 mutex_enter(&e1000g_nvm_lock); 1509 result = e1000_init_hw(hw); 1510 mutex_exit(&e1000g_nvm_lock); 1511 1512 if (result < E1000_SUCCESS) { 1513 e1000g_log(Adapter, CE_WARN, "Initialize hw failed"); 1514 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1515 goto init_fail; 1516 } 1517 1518 /* 1519 * Restore LED settings to the default from EEPROM 1520 * to meet the standard for Sun platforms. 1521 */ 1522 (void) e1000_cleanup_led(hw); 1523 1524 /* Disable Smart Power Down */ 1525 phy_spd_state(hw, B_FALSE); 1526 1527 /* Make sure driver has control */ 1528 e1000g_get_driver_control(hw); 1529 1530 /* 1531 * Initialize unicast addresses. 1532 */ 1533 e1000g_init_unicst(Adapter); 1534 1535 /* 1536 * Setup and initialize the mctable structures. After this routine 1537 * completes Multicast table will be set 1538 */ 1539 e1000_update_mc_addr_list(hw, 1540 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 1541 msec_delay(5); 1542 1543 /* 1544 * Implement Adaptive IFS 1545 */ 1546 e1000_reset_adaptive(hw); 1547 1548 /* Setup Interrupt Throttling Register */ 1549 if (hw->mac.type >= e1000_82540) { 1550 E1000_WRITE_REG(hw, E1000_ITR, Adapter->intr_throttling_rate); 1551 } else 1552 Adapter->intr_adaptive = B_FALSE; 1553 1554 /* Start the timer for link setup */ 1555 if (hw->mac.autoneg) 1556 link_timeout = PHY_AUTO_NEG_LIMIT * drv_usectohz(100000); 1557 else 1558 link_timeout = PHY_FORCE_LIMIT * drv_usectohz(100000); 1559 1560 mutex_enter(&Adapter->link_lock); 1561 if (hw->phy.autoneg_wait_to_complete) { 1562 Adapter->link_complete = B_TRUE; 1563 } else { 1564 Adapter->link_complete = B_FALSE; 1565 Adapter->link_tid = timeout(e1000g_link_timer, 1566 (void *)Adapter, link_timeout); 1567 } 1568 mutex_exit(&Adapter->link_lock); 1569 1570 /* Save the state of the phy */ 1571 e1000g_get_phy_state(Adapter); 1572 1573 e1000g_param_sync(Adapter); 1574 1575 Adapter->init_count++; 1576 1577 if (e1000g_check_acc_handle(Adapter->osdep.cfg_handle) != DDI_FM_OK) { 1578 goto init_fail; 1579 } 1580 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1581 goto init_fail; 1582 } 1583 1584 Adapter->poll_mode = e1000g_poll_mode; 1585 1586 return (DDI_SUCCESS); 1587 1588 init_fail: 1589 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1590 return (DDI_FAILURE); 1591 } 1592 1593 static int 1594 e1000g_alloc_rx_data(struct e1000g *Adapter) 1595 { 1596 e1000g_rx_ring_t *rx_ring; 1597 e1000g_rx_data_t *rx_data; 1598 1599 rx_ring = Adapter->rx_ring; 1600 1601 rx_data = kmem_zalloc(sizeof (e1000g_rx_data_t), KM_NOSLEEP); 1602 1603 if (rx_data == NULL) 1604 return (DDI_FAILURE); 1605 1606 rx_data->priv_devi_node = Adapter->priv_devi_node; 1607 rx_data->rx_ring = rx_ring; 1608 1609 mutex_init(&rx_data->freelist_lock, NULL, 1610 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1611 mutex_init(&rx_data->recycle_lock, NULL, 1612 MUTEX_DRIVER, DDI_INTR_PRI(Adapter->intr_pri)); 1613 1614 rx_ring->rx_data = rx_data; 1615 1616 return (DDI_SUCCESS); 1617 } 1618 1619 void 1620 e1000g_free_rx_pending_buffers(e1000g_rx_data_t *rx_data) 1621 { 1622 rx_sw_packet_t *packet, *next_packet; 1623 1624 if (rx_data == NULL) 1625 return; 1626 1627 packet = rx_data->packet_area; 1628 while (packet != NULL) { 1629 next_packet = packet->next; 1630 e1000g_free_rx_sw_packet(packet, B_TRUE); 1631 packet = next_packet; 1632 } 1633 rx_data->packet_area = NULL; 1634 } 1635 1636 void 1637 e1000g_free_rx_data(e1000g_rx_data_t *rx_data) 1638 { 1639 if (rx_data == NULL) 1640 return; 1641 1642 mutex_destroy(&rx_data->freelist_lock); 1643 mutex_destroy(&rx_data->recycle_lock); 1644 1645 kmem_free(rx_data, sizeof (e1000g_rx_data_t)); 1646 } 1647 1648 /* 1649 * Check if the link is up 1650 */ 1651 static boolean_t 1652 e1000g_link_up(struct e1000g *Adapter) 1653 { 1654 struct e1000_hw *hw = &Adapter->shared; 1655 boolean_t link_up = B_FALSE; 1656 1657 /* 1658 * get_link_status is set in the interrupt handler on link-status-change 1659 * or rx sequence error interrupt. get_link_status will stay 1660 * false until the e1000_check_for_link establishes link only 1661 * for copper adapters. 1662 */ 1663 switch (hw->phy.media_type) { 1664 case e1000_media_type_copper: 1665 if (hw->mac.get_link_status) { 1666 (void) e1000_check_for_link(hw); 1667 link_up = !hw->mac.get_link_status; 1668 } else { 1669 link_up = B_TRUE; 1670 } 1671 break; 1672 case e1000_media_type_fiber: 1673 (void) e1000_check_for_link(hw); 1674 link_up = (E1000_READ_REG(hw, E1000_STATUS) & 1675 E1000_STATUS_LU); 1676 break; 1677 case e1000_media_type_internal_serdes: 1678 (void) e1000_check_for_link(hw); 1679 link_up = hw->mac.serdes_has_link; 1680 break; 1681 } 1682 1683 return (link_up); 1684 } 1685 1686 static void 1687 e1000g_m_ioctl(void *arg, queue_t *q, mblk_t *mp) 1688 { 1689 struct iocblk *iocp; 1690 struct e1000g *e1000gp; 1691 enum ioc_reply status; 1692 1693 iocp = (struct iocblk *)(uintptr_t)mp->b_rptr; 1694 iocp->ioc_error = 0; 1695 e1000gp = (struct e1000g *)arg; 1696 1697 ASSERT(e1000gp); 1698 if (e1000gp == NULL) { 1699 miocnak(q, mp, 0, EINVAL); 1700 return; 1701 } 1702 1703 rw_enter(&e1000gp->chip_lock, RW_READER); 1704 if (e1000gp->e1000g_state & E1000G_SUSPENDED) { 1705 rw_exit(&e1000gp->chip_lock); 1706 miocnak(q, mp, 0, EINVAL); 1707 return; 1708 } 1709 rw_exit(&e1000gp->chip_lock); 1710 1711 switch (iocp->ioc_cmd) { 1712 1713 case LB_GET_INFO_SIZE: 1714 case LB_GET_INFO: 1715 case LB_GET_MODE: 1716 case LB_SET_MODE: 1717 status = e1000g_loopback_ioctl(e1000gp, iocp, mp); 1718 break; 1719 1720 1721 #ifdef E1000G_DEBUG 1722 case E1000G_IOC_REG_PEEK: 1723 case E1000G_IOC_REG_POKE: 1724 status = e1000g_pp_ioctl(e1000gp, iocp, mp); 1725 break; 1726 case E1000G_IOC_CHIP_RESET: 1727 e1000gp->reset_count++; 1728 if (e1000g_reset_adapter(e1000gp)) 1729 status = IOC_ACK; 1730 else 1731 status = IOC_INVAL; 1732 break; 1733 #endif 1734 default: 1735 status = IOC_INVAL; 1736 break; 1737 } 1738 1739 /* 1740 * Decide how to reply 1741 */ 1742 switch (status) { 1743 default: 1744 case IOC_INVAL: 1745 /* 1746 * Error, reply with a NAK and EINVAL or the specified error 1747 */ 1748 miocnak(q, mp, 0, iocp->ioc_error == 0 ? 1749 EINVAL : iocp->ioc_error); 1750 break; 1751 1752 case IOC_DONE: 1753 /* 1754 * OK, reply already sent 1755 */ 1756 break; 1757 1758 case IOC_ACK: 1759 /* 1760 * OK, reply with an ACK 1761 */ 1762 miocack(q, mp, 0, 0); 1763 break; 1764 1765 case IOC_REPLY: 1766 /* 1767 * OK, send prepared reply as ACK or NAK 1768 */ 1769 mp->b_datap->db_type = iocp->ioc_error == 0 ? 1770 M_IOCACK : M_IOCNAK; 1771 qreply(q, mp); 1772 break; 1773 } 1774 } 1775 1776 /* 1777 * The default value of e1000g_poll_mode == 0 assumes that the NIC is 1778 * capable of supporting only one interrupt and we shouldn't disable 1779 * the physical interrupt. In this case we let the interrupt come and 1780 * we queue the packets in the rx ring itself in case we are in polling 1781 * mode (better latency but slightly lower performance and a very 1782 * high intrrupt count in mpstat which is harmless). 1783 * 1784 * e1000g_poll_mode == 1 assumes that we have per Rx ring interrupt 1785 * which can be disabled in poll mode. This gives better overall 1786 * throughput (compared to the mode above), shows very low interrupt 1787 * count but has slightly higher latency since we pick the packets when 1788 * the poll thread does polling. 1789 * 1790 * Currently, this flag should be enabled only while doing performance 1791 * measurement or when it can be guaranteed that entire NIC going 1792 * in poll mode will not harm any traffic like cluster heartbeat etc. 1793 */ 1794 int e1000g_poll_mode = 0; 1795 1796 /* 1797 * Called from the upper layers when driver is in polling mode to 1798 * pick up any queued packets. Care should be taken to not block 1799 * this thread. 1800 */ 1801 static mblk_t *e1000g_poll_ring(void *arg, int bytes_to_pickup) 1802 { 1803 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)arg; 1804 mblk_t *mp = NULL; 1805 mblk_t *tail; 1806 struct e1000g *adapter; 1807 1808 adapter = rx_ring->adapter; 1809 1810 rw_enter(&adapter->chip_lock, RW_READER); 1811 1812 if (adapter->e1000g_state & E1000G_SUSPENDED) { 1813 rw_exit(&adapter->chip_lock); 1814 return (NULL); 1815 } 1816 1817 mutex_enter(&rx_ring->rx_lock); 1818 mp = e1000g_receive(rx_ring, &tail, bytes_to_pickup); 1819 mutex_exit(&rx_ring->rx_lock); 1820 rw_exit(&adapter->chip_lock); 1821 return (mp); 1822 } 1823 1824 static int 1825 e1000g_m_start(void *arg) 1826 { 1827 struct e1000g *Adapter = (struct e1000g *)arg; 1828 1829 rw_enter(&Adapter->chip_lock, RW_WRITER); 1830 1831 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1832 rw_exit(&Adapter->chip_lock); 1833 return (ECANCELED); 1834 } 1835 1836 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 1837 rw_exit(&Adapter->chip_lock); 1838 return (ENOTACTIVE); 1839 } 1840 1841 Adapter->e1000g_state |= E1000G_STARTED; 1842 1843 rw_exit(&Adapter->chip_lock); 1844 1845 /* Enable and start the watchdog timer */ 1846 enable_watchdog_timer(Adapter); 1847 1848 return (0); 1849 } 1850 1851 static int 1852 e1000g_start(struct e1000g *Adapter, boolean_t global) 1853 { 1854 e1000g_rx_data_t *rx_data; 1855 1856 if (global) { 1857 if (e1000g_alloc_rx_data(Adapter) != DDI_SUCCESS) { 1858 e1000g_log(Adapter, CE_WARN, "Allocate rx data failed"); 1859 goto start_fail; 1860 } 1861 1862 /* Allocate dma resources for descriptors and buffers */ 1863 if (e1000g_alloc_dma_resources(Adapter) != DDI_SUCCESS) { 1864 e1000g_log(Adapter, CE_WARN, 1865 "Alloc DMA resources failed"); 1866 goto start_fail; 1867 } 1868 Adapter->rx_buffer_setup = B_FALSE; 1869 } 1870 1871 if (!(Adapter->attach_progress & ATTACH_PROGRESS_INIT)) { 1872 if (e1000g_init(Adapter) != DDI_SUCCESS) { 1873 e1000g_log(Adapter, CE_WARN, 1874 "Adapter initialization failed"); 1875 goto start_fail; 1876 } 1877 } 1878 1879 /* Setup and initialize the transmit structures */ 1880 e1000g_tx_setup(Adapter); 1881 msec_delay(5); 1882 1883 /* Setup and initialize the receive structures */ 1884 e1000g_rx_setup(Adapter); 1885 msec_delay(5); 1886 1887 /* Restore the e1000g promiscuous mode */ 1888 e1000g_restore_promisc(Adapter); 1889 1890 e1000g_mask_interrupt(Adapter); 1891 1892 Adapter->attach_progress |= ATTACH_PROGRESS_INIT; 1893 1894 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 1895 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1896 goto start_fail; 1897 } 1898 1899 return (DDI_SUCCESS); 1900 1901 start_fail: 1902 rx_data = Adapter->rx_ring->rx_data; 1903 1904 if (global) { 1905 e1000g_release_dma_resources(Adapter); 1906 e1000g_free_rx_pending_buffers(rx_data); 1907 e1000g_free_rx_data(rx_data); 1908 } 1909 1910 mutex_enter(&e1000g_nvm_lock); 1911 (void) e1000_reset_hw(&Adapter->shared); 1912 mutex_exit(&e1000g_nvm_lock); 1913 1914 return (DDI_FAILURE); 1915 } 1916 1917 static void 1918 e1000g_m_stop(void *arg) 1919 { 1920 struct e1000g *Adapter = (struct e1000g *)arg; 1921 1922 /* Drain tx sessions */ 1923 (void) e1000g_tx_drain(Adapter); 1924 1925 rw_enter(&Adapter->chip_lock, RW_WRITER); 1926 1927 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 1928 rw_exit(&Adapter->chip_lock); 1929 return; 1930 } 1931 Adapter->e1000g_state &= ~E1000G_STARTED; 1932 e1000g_stop(Adapter, B_TRUE); 1933 1934 rw_exit(&Adapter->chip_lock); 1935 1936 /* Disable and stop all the timers */ 1937 disable_watchdog_timer(Adapter); 1938 stop_link_timer(Adapter); 1939 stop_82547_timer(Adapter->tx_ring); 1940 } 1941 1942 static void 1943 e1000g_stop(struct e1000g *Adapter, boolean_t global) 1944 { 1945 private_devi_list_t *devi_node; 1946 e1000g_rx_data_t *rx_data; 1947 int result; 1948 1949 Adapter->attach_progress &= ~ATTACH_PROGRESS_INIT; 1950 1951 /* Stop the chip and release pending resources */ 1952 1953 /* Tell firmware driver is no longer in control */ 1954 e1000g_release_driver_control(&Adapter->shared); 1955 1956 e1000g_clear_all_interrupts(Adapter); 1957 1958 mutex_enter(&e1000g_nvm_lock); 1959 result = e1000_reset_hw(&Adapter->shared); 1960 mutex_exit(&e1000g_nvm_lock); 1961 1962 if (result != E1000_SUCCESS) { 1963 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_INVAL_STATE); 1964 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1965 } 1966 1967 /* Release resources still held by the TX descriptors */ 1968 e1000g_tx_clean(Adapter); 1969 1970 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 1971 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 1972 1973 /* Clean the pending rx jumbo packet fragment */ 1974 e1000g_rx_clean(Adapter); 1975 1976 if (global) { 1977 e1000g_release_dma_resources(Adapter); 1978 1979 mutex_enter(&e1000g_rx_detach_lock); 1980 rx_data = Adapter->rx_ring->rx_data; 1981 rx_data->flag |= E1000G_RX_STOPPED; 1982 1983 if (rx_data->pending_count == 0) { 1984 e1000g_free_rx_pending_buffers(rx_data); 1985 e1000g_free_rx_data(rx_data); 1986 } else { 1987 devi_node = rx_data->priv_devi_node; 1988 if (devi_node != NULL) 1989 atomic_inc_32(&devi_node->pending_rx_count); 1990 else 1991 atomic_inc_32(&Adapter->pending_rx_count); 1992 } 1993 mutex_exit(&e1000g_rx_detach_lock); 1994 } 1995 1996 if (Adapter->link_state == LINK_STATE_UP) { 1997 Adapter->link_state = LINK_STATE_UNKNOWN; 1998 if (!Adapter->reset_flag) 1999 mac_link_update(Adapter->mh, Adapter->link_state); 2000 } 2001 } 2002 2003 static void 2004 e1000g_rx_clean(struct e1000g *Adapter) 2005 { 2006 e1000g_rx_data_t *rx_data = Adapter->rx_ring->rx_data; 2007 2008 if (rx_data == NULL) 2009 return; 2010 2011 if (rx_data->rx_mblk != NULL) { 2012 freemsg(rx_data->rx_mblk); 2013 rx_data->rx_mblk = NULL; 2014 rx_data->rx_mblk_tail = NULL; 2015 rx_data->rx_mblk_len = 0; 2016 } 2017 } 2018 2019 static void 2020 e1000g_tx_clean(struct e1000g *Adapter) 2021 { 2022 e1000g_tx_ring_t *tx_ring; 2023 p_tx_sw_packet_t packet; 2024 mblk_t *mp; 2025 mblk_t *nmp; 2026 uint32_t packet_count; 2027 2028 tx_ring = Adapter->tx_ring; 2029 2030 /* 2031 * Here we don't need to protect the lists using 2032 * the usedlist_lock and freelist_lock, for they 2033 * have been protected by the chip_lock. 2034 */ 2035 mp = NULL; 2036 nmp = NULL; 2037 packet_count = 0; 2038 packet = (p_tx_sw_packet_t)QUEUE_GET_HEAD(&tx_ring->used_list); 2039 while (packet != NULL) { 2040 if (packet->mp != NULL) { 2041 /* Assemble the message chain */ 2042 if (mp == NULL) { 2043 mp = packet->mp; 2044 nmp = packet->mp; 2045 } else { 2046 nmp->b_next = packet->mp; 2047 nmp = packet->mp; 2048 } 2049 /* Disconnect the message from the sw packet */ 2050 packet->mp = NULL; 2051 } 2052 2053 e1000g_free_tx_swpkt(packet); 2054 packet_count++; 2055 2056 packet = (p_tx_sw_packet_t) 2057 QUEUE_GET_NEXT(&tx_ring->used_list, &packet->Link); 2058 } 2059 2060 if (mp != NULL) 2061 freemsgchain(mp); 2062 2063 if (packet_count > 0) { 2064 QUEUE_APPEND(&tx_ring->free_list, &tx_ring->used_list); 2065 QUEUE_INIT_LIST(&tx_ring->used_list); 2066 2067 /* Setup TX descriptor pointers */ 2068 tx_ring->tbd_next = tx_ring->tbd_first; 2069 tx_ring->tbd_oldest = tx_ring->tbd_first; 2070 2071 /* Setup our HW Tx Head & Tail descriptor pointers */ 2072 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 2073 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 2074 } 2075 } 2076 2077 static boolean_t 2078 e1000g_tx_drain(struct e1000g *Adapter) 2079 { 2080 int i; 2081 boolean_t done; 2082 e1000g_tx_ring_t *tx_ring; 2083 2084 tx_ring = Adapter->tx_ring; 2085 2086 /* Allow up to 'wsdraintime' for pending xmit's to complete. */ 2087 for (i = 0; i < TX_DRAIN_TIME; i++) { 2088 mutex_enter(&tx_ring->usedlist_lock); 2089 done = IS_QUEUE_EMPTY(&tx_ring->used_list); 2090 mutex_exit(&tx_ring->usedlist_lock); 2091 2092 if (done) 2093 break; 2094 2095 msec_delay(1); 2096 } 2097 2098 return (done); 2099 } 2100 2101 static boolean_t 2102 e1000g_rx_drain(struct e1000g *Adapter) 2103 { 2104 int i; 2105 boolean_t done; 2106 2107 /* 2108 * Allow up to RX_DRAIN_TIME for pending received packets to complete. 2109 */ 2110 for (i = 0; i < RX_DRAIN_TIME; i++) { 2111 done = (Adapter->pending_rx_count == 0); 2112 2113 if (done) 2114 break; 2115 2116 msec_delay(1); 2117 } 2118 2119 return (done); 2120 } 2121 2122 static boolean_t 2123 e1000g_reset_adapter(struct e1000g *Adapter) 2124 { 2125 /* Disable and stop all the timers */ 2126 disable_watchdog_timer(Adapter); 2127 stop_link_timer(Adapter); 2128 stop_82547_timer(Adapter->tx_ring); 2129 2130 rw_enter(&Adapter->chip_lock, RW_WRITER); 2131 2132 if (Adapter->stall_flag) { 2133 Adapter->stall_flag = B_FALSE; 2134 Adapter->reset_flag = B_TRUE; 2135 } 2136 2137 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2138 rw_exit(&Adapter->chip_lock); 2139 return (B_TRUE); 2140 } 2141 2142 e1000g_stop(Adapter, B_FALSE); 2143 2144 if (e1000g_start(Adapter, B_FALSE) != DDI_SUCCESS) { 2145 rw_exit(&Adapter->chip_lock); 2146 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2147 return (B_FALSE); 2148 } 2149 2150 rw_exit(&Adapter->chip_lock); 2151 2152 /* Enable and start the watchdog timer */ 2153 enable_watchdog_timer(Adapter); 2154 2155 return (B_TRUE); 2156 } 2157 2158 boolean_t 2159 e1000g_global_reset(struct e1000g *Adapter) 2160 { 2161 /* Disable and stop all the timers */ 2162 disable_watchdog_timer(Adapter); 2163 stop_link_timer(Adapter); 2164 stop_82547_timer(Adapter->tx_ring); 2165 2166 rw_enter(&Adapter->chip_lock, RW_WRITER); 2167 2168 e1000g_stop(Adapter, B_TRUE); 2169 2170 Adapter->init_count = 0; 2171 2172 if (e1000g_start(Adapter, B_TRUE) != DDI_SUCCESS) { 2173 rw_exit(&Adapter->chip_lock); 2174 e1000g_log(Adapter, CE_WARN, "Reset failed"); 2175 return (B_FALSE); 2176 } 2177 2178 rw_exit(&Adapter->chip_lock); 2179 2180 /* Enable and start the watchdog timer */ 2181 enable_watchdog_timer(Adapter); 2182 2183 return (B_TRUE); 2184 } 2185 2186 /* 2187 * e1000g_intr_pciexpress - ISR for PCI Express chipsets 2188 * 2189 * This interrupt service routine is for PCI-Express adapters. 2190 * The ICR contents is valid only when the E1000_ICR_INT_ASSERTED 2191 * bit is set. 2192 */ 2193 static uint_t 2194 e1000g_intr_pciexpress(caddr_t arg) 2195 { 2196 struct e1000g *Adapter; 2197 uint32_t icr; 2198 2199 Adapter = (struct e1000g *)(uintptr_t)arg; 2200 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2201 2202 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2203 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2204 return (DDI_INTR_CLAIMED); 2205 } 2206 2207 if (icr & E1000_ICR_INT_ASSERTED) { 2208 /* 2209 * E1000_ICR_INT_ASSERTED bit was set: 2210 * Read(Clear) the ICR, claim this interrupt, 2211 * look for work to do. 2212 */ 2213 e1000g_intr_work(Adapter, icr); 2214 return (DDI_INTR_CLAIMED); 2215 } else { 2216 /* 2217 * E1000_ICR_INT_ASSERTED bit was not set: 2218 * Don't claim this interrupt, return immediately. 2219 */ 2220 return (DDI_INTR_UNCLAIMED); 2221 } 2222 } 2223 2224 /* 2225 * e1000g_intr - ISR for PCI/PCI-X chipsets 2226 * 2227 * This interrupt service routine is for PCI/PCI-X adapters. 2228 * We check the ICR contents no matter the E1000_ICR_INT_ASSERTED 2229 * bit is set or not. 2230 */ 2231 static uint_t 2232 e1000g_intr(caddr_t arg) 2233 { 2234 struct e1000g *Adapter; 2235 uint32_t icr; 2236 2237 Adapter = (struct e1000g *)(uintptr_t)arg; 2238 icr = E1000_READ_REG(&Adapter->shared, E1000_ICR); 2239 2240 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2241 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2242 return (DDI_INTR_CLAIMED); 2243 } 2244 2245 if (icr) { 2246 /* 2247 * Any bit was set in ICR: 2248 * Read(Clear) the ICR, claim this interrupt, 2249 * look for work to do. 2250 */ 2251 e1000g_intr_work(Adapter, icr); 2252 return (DDI_INTR_CLAIMED); 2253 } else { 2254 /* 2255 * No bit was set in ICR: 2256 * Don't claim this interrupt, return immediately. 2257 */ 2258 return (DDI_INTR_UNCLAIMED); 2259 } 2260 } 2261 2262 /* 2263 * e1000g_intr_work - actual processing of ISR 2264 * 2265 * Read(clear) the ICR contents and call appropriate interrupt 2266 * processing routines. 2267 */ 2268 static void 2269 e1000g_intr_work(struct e1000g *Adapter, uint32_t icr) 2270 { 2271 struct e1000_hw *hw; 2272 hw = &Adapter->shared; 2273 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 2274 2275 Adapter->rx_pkt_cnt = 0; 2276 Adapter->tx_pkt_cnt = 0; 2277 2278 rw_enter(&Adapter->chip_lock, RW_READER); 2279 2280 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2281 rw_exit(&Adapter->chip_lock); 2282 return; 2283 } 2284 /* 2285 * Here we need to check the "e1000g_state" flag within the chip_lock to 2286 * ensure the receive routine will not execute when the adapter is 2287 * being reset. 2288 */ 2289 if (!(Adapter->e1000g_state & E1000G_STARTED)) { 2290 rw_exit(&Adapter->chip_lock); 2291 return; 2292 } 2293 2294 if (icr & E1000_ICR_RXT0) { 2295 mblk_t *mp = NULL; 2296 mblk_t *tail = NULL; 2297 e1000g_rx_ring_t *rx_ring; 2298 2299 rx_ring = Adapter->rx_ring; 2300 mutex_enter(&rx_ring->rx_lock); 2301 /* 2302 * Sometimes with legacy interrupts, it possible that 2303 * there is a single interrupt for Rx/Tx. In which 2304 * case, if poll flag is set, we shouldn't really 2305 * be doing Rx processing. 2306 */ 2307 if (!rx_ring->poll_flag) 2308 mp = e1000g_receive(rx_ring, &tail, 2309 E1000G_CHAIN_NO_LIMIT); 2310 mutex_exit(&rx_ring->rx_lock); 2311 rw_exit(&Adapter->chip_lock); 2312 if (mp != NULL) 2313 mac_rx_ring(Adapter->mh, rx_ring->mrh, 2314 mp, rx_ring->ring_gen_num); 2315 } else 2316 rw_exit(&Adapter->chip_lock); 2317 2318 if (icr & E1000_ICR_TXDW) { 2319 if (!Adapter->tx_intr_enable) 2320 e1000g_clear_tx_interrupt(Adapter); 2321 2322 /* Recycle the tx descriptors */ 2323 rw_enter(&Adapter->chip_lock, RW_READER); 2324 (void) e1000g_recycle(tx_ring); 2325 E1000G_DEBUG_STAT(tx_ring->stat_recycle_intr); 2326 rw_exit(&Adapter->chip_lock); 2327 2328 if (tx_ring->resched_needed && 2329 (tx_ring->tbd_avail > DEFAULT_TX_UPDATE_THRESHOLD)) { 2330 tx_ring->resched_needed = B_FALSE; 2331 mac_tx_update(Adapter->mh); 2332 E1000G_STAT(tx_ring->stat_reschedule); 2333 } 2334 } 2335 2336 /* 2337 * The Receive Sequence errors RXSEQ and the link status change LSC 2338 * are checked to detect that the cable has been pulled out. For 2339 * the Wiseman 2.0 silicon, the receive sequence errors interrupt 2340 * are an indication that cable is not connected. 2341 */ 2342 if ((icr & E1000_ICR_RXSEQ) || 2343 (icr & E1000_ICR_LSC) || 2344 (icr & E1000_ICR_GPI_EN1)) { 2345 boolean_t link_changed; 2346 timeout_id_t tid = 0; 2347 2348 stop_watchdog_timer(Adapter); 2349 2350 rw_enter(&Adapter->chip_lock, RW_WRITER); 2351 2352 /* 2353 * Because we got a link-status-change interrupt, force 2354 * e1000_check_for_link() to look at phy 2355 */ 2356 Adapter->shared.mac.get_link_status = B_TRUE; 2357 2358 /* e1000g_link_check takes care of link status change */ 2359 link_changed = e1000g_link_check(Adapter); 2360 2361 /* Get new phy state */ 2362 e1000g_get_phy_state(Adapter); 2363 2364 /* 2365 * If the link timer has not timed out, we'll not notify 2366 * the upper layer with any link state until the link is up. 2367 */ 2368 if (link_changed && !Adapter->link_complete) { 2369 if (Adapter->link_state == LINK_STATE_UP) { 2370 mutex_enter(&Adapter->link_lock); 2371 Adapter->link_complete = B_TRUE; 2372 tid = Adapter->link_tid; 2373 Adapter->link_tid = 0; 2374 mutex_exit(&Adapter->link_lock); 2375 } else { 2376 link_changed = B_FALSE; 2377 } 2378 } 2379 rw_exit(&Adapter->chip_lock); 2380 2381 if (link_changed) { 2382 if (tid != 0) 2383 (void) untimeout(tid); 2384 2385 /* 2386 * Workaround for esb2. Data stuck in fifo on a link 2387 * down event. Stop receiver here and reset in watchdog. 2388 */ 2389 if ((Adapter->link_state == LINK_STATE_DOWN) && 2390 (Adapter->shared.mac.type == e1000_80003es2lan)) { 2391 uint32_t rctl = E1000_READ_REG(hw, E1000_RCTL); 2392 E1000_WRITE_REG(hw, E1000_RCTL, 2393 rctl & ~E1000_RCTL_EN); 2394 e1000g_log(Adapter, CE_WARN, 2395 "ESB2 receiver disabled"); 2396 Adapter->esb2_workaround = B_TRUE; 2397 } 2398 if (!Adapter->reset_flag) 2399 mac_link_update(Adapter->mh, 2400 Adapter->link_state); 2401 if (Adapter->link_state == LINK_STATE_UP) 2402 Adapter->reset_flag = B_FALSE; 2403 } 2404 2405 start_watchdog_timer(Adapter); 2406 } 2407 } 2408 2409 static void 2410 e1000g_init_unicst(struct e1000g *Adapter) 2411 { 2412 struct e1000_hw *hw; 2413 int slot; 2414 2415 hw = &Adapter->shared; 2416 2417 if (Adapter->init_count == 0) { 2418 /* Initialize the multiple unicast addresses */ 2419 Adapter->unicst_total = MAX_NUM_UNICAST_ADDRESSES; 2420 2421 /* Workaround for an erratum of 82571 chipst */ 2422 if ((hw->mac.type == e1000_82571) && 2423 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2424 Adapter->unicst_total--; 2425 2426 Adapter->unicst_avail = Adapter->unicst_total; 2427 2428 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2429 /* Clear both the flag and MAC address */ 2430 Adapter->unicst_addr[slot].reg.high = 0; 2431 Adapter->unicst_addr[slot].reg.low = 0; 2432 } 2433 } else { 2434 /* Workaround for an erratum of 82571 chipst */ 2435 if ((hw->mac.type == e1000_82571) && 2436 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2437 e1000_rar_set(hw, hw->mac.addr, LAST_RAR_ENTRY); 2438 2439 /* Re-configure the RAR registers */ 2440 for (slot = 0; slot < Adapter->unicst_total; slot++) 2441 if (Adapter->unicst_addr[slot].mac.set == 1) 2442 e1000_rar_set(hw, 2443 Adapter->unicst_addr[slot].mac.addr, slot); 2444 } 2445 2446 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 2447 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2448 } 2449 2450 static int 2451 e1000g_unicst_set(struct e1000g *Adapter, const uint8_t *mac_addr, 2452 int slot) 2453 { 2454 struct e1000_hw *hw; 2455 2456 hw = &Adapter->shared; 2457 2458 /* 2459 * The first revision of Wiseman silicon (rev 2.0) has an errata 2460 * that requires the receiver to be in reset when any of the 2461 * receive address registers (RAR regs) are accessed. The first 2462 * rev of Wiseman silicon also requires MWI to be disabled when 2463 * a global reset or a receive reset is issued. So before we 2464 * initialize the RARs, we check the rev of the Wiseman controller 2465 * and work around any necessary HW errata. 2466 */ 2467 if ((hw->mac.type == e1000_82542) && 2468 (hw->revision_id == E1000_REVISION_2)) { 2469 e1000_pci_clear_mwi(hw); 2470 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 2471 msec_delay(5); 2472 } 2473 if (mac_addr == NULL) { 2474 E1000_WRITE_REG_ARRAY(hw, E1000_RA, slot << 1, 0); 2475 E1000_WRITE_FLUSH(hw); 2476 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (slot << 1) + 1, 0); 2477 E1000_WRITE_FLUSH(hw); 2478 /* Clear both the flag and MAC address */ 2479 Adapter->unicst_addr[slot].reg.high = 0; 2480 Adapter->unicst_addr[slot].reg.low = 0; 2481 } else { 2482 bcopy(mac_addr, Adapter->unicst_addr[slot].mac.addr, 2483 ETHERADDRL); 2484 e1000_rar_set(hw, (uint8_t *)mac_addr, slot); 2485 Adapter->unicst_addr[slot].mac.set = 1; 2486 } 2487 2488 /* Workaround for an erratum of 82571 chipst */ 2489 if (slot == 0) { 2490 if ((hw->mac.type == e1000_82571) && 2491 (e1000_get_laa_state_82571(hw) == B_TRUE)) 2492 if (mac_addr == NULL) { 2493 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2494 slot << 1, 0); 2495 E1000_WRITE_FLUSH(hw); 2496 E1000_WRITE_REG_ARRAY(hw, E1000_RA, 2497 (slot << 1) + 1, 0); 2498 E1000_WRITE_FLUSH(hw); 2499 } else { 2500 e1000_rar_set(hw, (uint8_t *)mac_addr, 2501 LAST_RAR_ENTRY); 2502 } 2503 } 2504 2505 /* 2506 * If we are using Wiseman rev 2.0 silicon, we will have previously 2507 * put the receive in reset, and disabled MWI, to work around some 2508 * HW errata. Now we should take the receiver out of reset, and 2509 * re-enabled if MWI if it was previously enabled by the PCI BIOS. 2510 */ 2511 if ((hw->mac.type == e1000_82542) && 2512 (hw->revision_id == E1000_REVISION_2)) { 2513 E1000_WRITE_REG(hw, E1000_RCTL, 0); 2514 msec_delay(1); 2515 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 2516 e1000_pci_set_mwi(hw); 2517 e1000g_rx_setup(Adapter); 2518 } 2519 2520 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2521 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2522 return (EIO); 2523 } 2524 2525 return (0); 2526 } 2527 2528 static int 2529 multicst_add(struct e1000g *Adapter, const uint8_t *multiaddr) 2530 { 2531 struct e1000_hw *hw = &Adapter->shared; 2532 struct ether_addr *newtable; 2533 size_t new_len; 2534 size_t old_len; 2535 int res = 0; 2536 2537 if ((multiaddr[0] & 01) == 0) { 2538 res = EINVAL; 2539 e1000g_log(Adapter, CE_WARN, "Illegal multicast address"); 2540 goto done; 2541 } 2542 2543 if (Adapter->mcast_count >= Adapter->mcast_max_num) { 2544 res = ENOENT; 2545 e1000g_log(Adapter, CE_WARN, 2546 "Adapter requested more than %d mcast addresses", 2547 Adapter->mcast_max_num); 2548 goto done; 2549 } 2550 2551 2552 if (Adapter->mcast_count == Adapter->mcast_alloc_count) { 2553 old_len = Adapter->mcast_alloc_count * 2554 sizeof (struct ether_addr); 2555 new_len = (Adapter->mcast_alloc_count + MCAST_ALLOC_SIZE) * 2556 sizeof (struct ether_addr); 2557 2558 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2559 if (newtable == NULL) { 2560 res = ENOMEM; 2561 e1000g_log(Adapter, CE_WARN, 2562 "Not enough memory to alloc mcast table"); 2563 goto done; 2564 } 2565 2566 if (Adapter->mcast_table != NULL) { 2567 bcopy(Adapter->mcast_table, newtable, old_len); 2568 kmem_free(Adapter->mcast_table, old_len); 2569 } 2570 Adapter->mcast_alloc_count += MCAST_ALLOC_SIZE; 2571 Adapter->mcast_table = newtable; 2572 } 2573 2574 bcopy(multiaddr, 2575 &Adapter->mcast_table[Adapter->mcast_count], ETHERADDRL); 2576 Adapter->mcast_count++; 2577 2578 /* 2579 * Update the MC table in the hardware 2580 */ 2581 e1000g_clear_interrupt(Adapter); 2582 2583 e1000_update_mc_addr_list(hw, 2584 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2585 2586 e1000g_mask_interrupt(Adapter); 2587 2588 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2589 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2590 res = EIO; 2591 } 2592 2593 done: 2594 return (res); 2595 } 2596 2597 static int 2598 multicst_remove(struct e1000g *Adapter, const uint8_t *multiaddr) 2599 { 2600 struct e1000_hw *hw = &Adapter->shared; 2601 struct ether_addr *newtable; 2602 size_t new_len; 2603 size_t old_len; 2604 unsigned i; 2605 2606 for (i = 0; i < Adapter->mcast_count; i++) { 2607 if (bcmp(multiaddr, &Adapter->mcast_table[i], 2608 ETHERADDRL) == 0) { 2609 for (i++; i < Adapter->mcast_count; i++) { 2610 Adapter->mcast_table[i - 1] = 2611 Adapter->mcast_table[i]; 2612 } 2613 Adapter->mcast_count--; 2614 break; 2615 } 2616 } 2617 2618 if ((Adapter->mcast_alloc_count - Adapter->mcast_count) > 2619 MCAST_ALLOC_SIZE) { 2620 old_len = Adapter->mcast_alloc_count * 2621 sizeof (struct ether_addr); 2622 new_len = (Adapter->mcast_alloc_count - MCAST_ALLOC_SIZE) * 2623 sizeof (struct ether_addr); 2624 2625 newtable = kmem_alloc(new_len, KM_NOSLEEP); 2626 if (newtable != NULL) { 2627 bcopy(Adapter->mcast_table, newtable, new_len); 2628 kmem_free(Adapter->mcast_table, old_len); 2629 2630 Adapter->mcast_alloc_count -= MCAST_ALLOC_SIZE; 2631 Adapter->mcast_table = newtable; 2632 } 2633 } 2634 2635 /* 2636 * Update the MC table in the hardware 2637 */ 2638 e1000g_clear_interrupt(Adapter); 2639 2640 e1000_update_mc_addr_list(hw, 2641 (uint8_t *)Adapter->mcast_table, Adapter->mcast_count); 2642 2643 e1000g_mask_interrupt(Adapter); 2644 2645 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2646 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2647 return (EIO); 2648 } 2649 2650 return (0); 2651 } 2652 2653 static void 2654 e1000g_release_multicast(struct e1000g *Adapter) 2655 { 2656 if (Adapter->mcast_table != NULL) { 2657 kmem_free(Adapter->mcast_table, 2658 Adapter->mcast_alloc_count * sizeof (struct ether_addr)); 2659 Adapter->mcast_table = NULL; 2660 } 2661 } 2662 2663 int 2664 e1000g_m_multicst(void *arg, boolean_t add, const uint8_t *addr) 2665 { 2666 struct e1000g *Adapter = (struct e1000g *)arg; 2667 int result; 2668 2669 rw_enter(&Adapter->chip_lock, RW_WRITER); 2670 2671 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2672 result = ECANCELED; 2673 goto done; 2674 } 2675 2676 result = (add) ? multicst_add(Adapter, addr) 2677 : multicst_remove(Adapter, addr); 2678 2679 done: 2680 rw_exit(&Adapter->chip_lock); 2681 return (result); 2682 2683 } 2684 2685 int 2686 e1000g_m_promisc(void *arg, boolean_t on) 2687 { 2688 struct e1000g *Adapter = (struct e1000g *)arg; 2689 uint32_t rctl; 2690 2691 rw_enter(&Adapter->chip_lock, RW_WRITER); 2692 2693 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2694 rw_exit(&Adapter->chip_lock); 2695 return (ECANCELED); 2696 } 2697 2698 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 2699 2700 if (on) 2701 rctl |= 2702 (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 2703 else 2704 rctl &= (~(E1000_RCTL_UPE | E1000_RCTL_MPE)); 2705 2706 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 2707 2708 Adapter->e1000g_promisc = on; 2709 2710 rw_exit(&Adapter->chip_lock); 2711 2712 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 2713 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 2714 return (EIO); 2715 } 2716 2717 return (0); 2718 } 2719 2720 /* 2721 * Entry points to enable and disable interrupts at the granularity of 2722 * a group. 2723 * Turns the poll_mode for the whole adapter on and off to enable or 2724 * override the ring level polling control over the hardware interrupts. 2725 */ 2726 static int 2727 e1000g_rx_group_intr_enable(mac_intr_handle_t arg) 2728 { 2729 struct e1000g *adapter = (struct e1000g *)arg; 2730 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2731 2732 /* 2733 * Later interrupts at the granularity of the this ring will 2734 * invoke mac_rx() with NULL, indicating the need for another 2735 * software classification. 2736 * We have a single ring usable per adapter now, so we only need to 2737 * reset the rx handle for that one. 2738 * When more RX rings can be used, we should update each one of them. 2739 */ 2740 mutex_enter(&rx_ring->rx_lock); 2741 rx_ring->mrh = NULL; 2742 adapter->poll_mode = B_FALSE; 2743 mutex_exit(&rx_ring->rx_lock); 2744 return (0); 2745 } 2746 2747 static int 2748 e1000g_rx_group_intr_disable(mac_intr_handle_t arg) 2749 { 2750 struct e1000g *adapter = (struct e1000g *)arg; 2751 e1000g_rx_ring_t *rx_ring = adapter->rx_ring; 2752 2753 mutex_enter(&rx_ring->rx_lock); 2754 2755 /* 2756 * Later interrupts at the granularity of the this ring will 2757 * invoke mac_rx() with the handle for this ring; 2758 */ 2759 adapter->poll_mode = B_TRUE; 2760 rx_ring->mrh = rx_ring->mrh_init; 2761 mutex_exit(&rx_ring->rx_lock); 2762 return (0); 2763 } 2764 2765 /* 2766 * Entry points to enable and disable interrupts at the granularity of 2767 * a ring. 2768 * adapter poll_mode controls whether we actually proceed with hardware 2769 * interrupt toggling. 2770 */ 2771 static int 2772 e1000g_rx_ring_intr_enable(mac_intr_handle_t intrh) 2773 { 2774 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2775 struct e1000g *adapter = rx_ring->adapter; 2776 struct e1000_hw *hw = &adapter->shared; 2777 uint32_t intr_mask; 2778 2779 rw_enter(&adapter->chip_lock, RW_READER); 2780 2781 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2782 rw_exit(&adapter->chip_lock); 2783 return (0); 2784 } 2785 2786 mutex_enter(&rx_ring->rx_lock); 2787 rx_ring->poll_flag = 0; 2788 mutex_exit(&rx_ring->rx_lock); 2789 2790 /* Rx interrupt enabling for MSI and legacy */ 2791 intr_mask = E1000_READ_REG(hw, E1000_IMS); 2792 intr_mask |= E1000_IMS_RXT0; 2793 E1000_WRITE_REG(hw, E1000_IMS, intr_mask); 2794 E1000_WRITE_FLUSH(hw); 2795 2796 /* Trigger a Rx interrupt to check Rx ring */ 2797 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 2798 E1000_WRITE_FLUSH(hw); 2799 2800 rw_exit(&adapter->chip_lock); 2801 return (0); 2802 } 2803 2804 static int 2805 e1000g_rx_ring_intr_disable(mac_intr_handle_t intrh) 2806 { 2807 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)intrh; 2808 struct e1000g *adapter = rx_ring->adapter; 2809 struct e1000_hw *hw = &adapter->shared; 2810 2811 rw_enter(&adapter->chip_lock, RW_READER); 2812 2813 if (adapter->e1000g_state & E1000G_SUSPENDED) { 2814 rw_exit(&adapter->chip_lock); 2815 return (0); 2816 } 2817 mutex_enter(&rx_ring->rx_lock); 2818 rx_ring->poll_flag = 1; 2819 mutex_exit(&rx_ring->rx_lock); 2820 2821 /* Rx interrupt disabling for MSI and legacy */ 2822 E1000_WRITE_REG(hw, E1000_IMC, E1000_IMS_RXT0); 2823 E1000_WRITE_FLUSH(hw); 2824 2825 rw_exit(&adapter->chip_lock); 2826 return (0); 2827 } 2828 2829 /* 2830 * e1000g_unicst_find - Find the slot for the specified unicast address 2831 */ 2832 static int 2833 e1000g_unicst_find(struct e1000g *Adapter, const uint8_t *mac_addr) 2834 { 2835 int slot; 2836 2837 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2838 if ((Adapter->unicst_addr[slot].mac.set == 1) && 2839 (bcmp(Adapter->unicst_addr[slot].mac.addr, 2840 mac_addr, ETHERADDRL) == 0)) 2841 return (slot); 2842 } 2843 2844 return (-1); 2845 } 2846 2847 /* 2848 * Entry points to add and remove a MAC address to a ring group. 2849 * The caller takes care of adding and removing the MAC addresses 2850 * to the filter via these two routines. 2851 */ 2852 2853 static int 2854 e1000g_addmac(void *arg, const uint8_t *mac_addr) 2855 { 2856 struct e1000g *Adapter = (struct e1000g *)arg; 2857 int slot, err; 2858 2859 rw_enter(&Adapter->chip_lock, RW_WRITER); 2860 2861 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2862 rw_exit(&Adapter->chip_lock); 2863 return (ECANCELED); 2864 } 2865 2866 if (e1000g_unicst_find(Adapter, mac_addr) != -1) { 2867 /* The same address is already in slot */ 2868 rw_exit(&Adapter->chip_lock); 2869 return (0); 2870 } 2871 2872 if (Adapter->unicst_avail == 0) { 2873 /* no slots available */ 2874 rw_exit(&Adapter->chip_lock); 2875 return (ENOSPC); 2876 } 2877 2878 /* Search for a free slot */ 2879 for (slot = 0; slot < Adapter->unicst_total; slot++) { 2880 if (Adapter->unicst_addr[slot].mac.set == 0) 2881 break; 2882 } 2883 ASSERT(slot < Adapter->unicst_total); 2884 2885 err = e1000g_unicst_set(Adapter, mac_addr, slot); 2886 if (err == 0) 2887 Adapter->unicst_avail--; 2888 2889 rw_exit(&Adapter->chip_lock); 2890 2891 return (err); 2892 } 2893 2894 static int 2895 e1000g_remmac(void *arg, const uint8_t *mac_addr) 2896 { 2897 struct e1000g *Adapter = (struct e1000g *)arg; 2898 int slot, err; 2899 2900 rw_enter(&Adapter->chip_lock, RW_WRITER); 2901 2902 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 2903 rw_exit(&Adapter->chip_lock); 2904 return (ECANCELED); 2905 } 2906 2907 slot = e1000g_unicst_find(Adapter, mac_addr); 2908 if (slot == -1) { 2909 rw_exit(&Adapter->chip_lock); 2910 return (EINVAL); 2911 } 2912 2913 ASSERT(Adapter->unicst_addr[slot].mac.set); 2914 2915 /* Clear this slot */ 2916 err = e1000g_unicst_set(Adapter, NULL, slot); 2917 if (err == 0) 2918 Adapter->unicst_avail++; 2919 2920 rw_exit(&Adapter->chip_lock); 2921 2922 return (err); 2923 } 2924 2925 static int 2926 e1000g_ring_start(mac_ring_driver_t rh, uint64_t mr_gen_num) 2927 { 2928 e1000g_rx_ring_t *rx_ring = (e1000g_rx_ring_t *)rh; 2929 2930 mutex_enter(&rx_ring->rx_lock); 2931 rx_ring->ring_gen_num = mr_gen_num; 2932 mutex_exit(&rx_ring->rx_lock); 2933 return (0); 2934 } 2935 2936 /* 2937 * Callback funtion for MAC layer to register all rings. 2938 * 2939 * The hardware supports a single group with currently only one ring 2940 * available. 2941 * Though not offering virtualization ability per se, exposing the 2942 * group/ring still enables the polling and interrupt toggling. 2943 */ 2944 /* ARGSUSED */ 2945 void 2946 e1000g_fill_ring(void *arg, mac_ring_type_t rtype, const int grp_index, 2947 const int ring_index, mac_ring_info_t *infop, mac_ring_handle_t rh) 2948 { 2949 struct e1000g *Adapter = (struct e1000g *)arg; 2950 e1000g_rx_ring_t *rx_ring = Adapter->rx_ring; 2951 mac_intr_t *mintr; 2952 2953 /* 2954 * We advertised only RX group/rings, so the MAC framework shouldn't 2955 * ask for any thing else. 2956 */ 2957 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0 && ring_index == 0); 2958 2959 rx_ring->mrh = rx_ring->mrh_init = rh; 2960 infop->mri_driver = (mac_ring_driver_t)rx_ring; 2961 infop->mri_start = e1000g_ring_start; 2962 infop->mri_stop = NULL; 2963 infop->mri_poll = e1000g_poll_ring; 2964 2965 /* Ring level interrupts */ 2966 mintr = &infop->mri_intr; 2967 mintr->mi_handle = (mac_intr_handle_t)rx_ring; 2968 mintr->mi_enable = e1000g_rx_ring_intr_enable; 2969 mintr->mi_disable = e1000g_rx_ring_intr_disable; 2970 } 2971 2972 /* ARGSUSED */ 2973 static void 2974 e1000g_fill_group(void *arg, mac_ring_type_t rtype, const int grp_index, 2975 mac_group_info_t *infop, mac_group_handle_t gh) 2976 { 2977 struct e1000g *Adapter = (struct e1000g *)arg; 2978 mac_intr_t *mintr; 2979 2980 /* 2981 * We advertised a single RX ring. Getting a request for anything else 2982 * signifies a bug in the MAC framework. 2983 */ 2984 ASSERT(rtype == MAC_RING_TYPE_RX && grp_index == 0); 2985 2986 Adapter->rx_group = gh; 2987 2988 infop->mgi_driver = (mac_group_driver_t)Adapter; 2989 infop->mgi_start = NULL; 2990 infop->mgi_stop = NULL; 2991 infop->mgi_addmac = e1000g_addmac; 2992 infop->mgi_remmac = e1000g_remmac; 2993 infop->mgi_count = 1; 2994 2995 /* Group level interrupts */ 2996 mintr = &infop->mgi_intr; 2997 mintr->mi_handle = (mac_intr_handle_t)Adapter; 2998 mintr->mi_enable = e1000g_rx_group_intr_enable; 2999 mintr->mi_disable = e1000g_rx_group_intr_disable; 3000 } 3001 3002 static boolean_t 3003 e1000g_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 3004 { 3005 struct e1000g *Adapter = (struct e1000g *)arg; 3006 3007 switch (cap) { 3008 case MAC_CAPAB_HCKSUM: { 3009 uint32_t *txflags = cap_data; 3010 3011 if (Adapter->tx_hcksum_enable) 3012 *txflags = HCKSUM_IPHDRCKSUM | 3013 HCKSUM_INET_PARTIAL; 3014 else 3015 return (B_FALSE); 3016 break; 3017 } 3018 3019 case MAC_CAPAB_LSO: { 3020 mac_capab_lso_t *cap_lso = cap_data; 3021 3022 if (Adapter->lso_enable) { 3023 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 3024 cap_lso->lso_basic_tcp_ipv4.lso_max = 3025 E1000_LSO_MAXLEN; 3026 } else 3027 return (B_FALSE); 3028 break; 3029 } 3030 case MAC_CAPAB_RINGS: { 3031 mac_capab_rings_t *cap_rings = cap_data; 3032 3033 /* No TX rings exposed yet */ 3034 if (cap_rings->mr_type != MAC_RING_TYPE_RX) 3035 return (B_FALSE); 3036 3037 cap_rings->mr_group_type = MAC_GROUP_TYPE_STATIC; 3038 cap_rings->mr_rnum = 1; 3039 cap_rings->mr_gnum = 1; 3040 cap_rings->mr_rget = e1000g_fill_ring; 3041 cap_rings->mr_gget = e1000g_fill_group; 3042 break; 3043 } 3044 default: 3045 return (B_FALSE); 3046 } 3047 return (B_TRUE); 3048 } 3049 3050 static boolean_t 3051 e1000g_param_locked(mac_prop_id_t pr_num) 3052 { 3053 /* 3054 * All en_* parameters are locked (read-only) while 3055 * the device is in any sort of loopback mode ... 3056 */ 3057 switch (pr_num) { 3058 case MAC_PROP_EN_1000FDX_CAP: 3059 case MAC_PROP_EN_1000HDX_CAP: 3060 case MAC_PROP_EN_100FDX_CAP: 3061 case MAC_PROP_EN_100HDX_CAP: 3062 case MAC_PROP_EN_10FDX_CAP: 3063 case MAC_PROP_EN_10HDX_CAP: 3064 case MAC_PROP_AUTONEG: 3065 case MAC_PROP_FLOWCTRL: 3066 return (B_TRUE); 3067 } 3068 return (B_FALSE); 3069 } 3070 3071 /* 3072 * callback function for set/get of properties 3073 */ 3074 static int 3075 e1000g_m_setprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3076 uint_t pr_valsize, const void *pr_val) 3077 { 3078 struct e1000g *Adapter = arg; 3079 struct e1000_hw *hw = &Adapter->shared; 3080 struct e1000_fc_info *fc = &Adapter->shared.fc; 3081 int err = 0; 3082 link_flowctrl_t flowctrl; 3083 uint32_t cur_mtu, new_mtu; 3084 3085 rw_enter(&Adapter->chip_lock, RW_WRITER); 3086 3087 if (Adapter->e1000g_state & E1000G_SUSPENDED) { 3088 rw_exit(&Adapter->chip_lock); 3089 return (ECANCELED); 3090 } 3091 3092 if (Adapter->loopback_mode != E1000G_LB_NONE && 3093 e1000g_param_locked(pr_num)) { 3094 /* 3095 * All en_* parameters are locked (read-only) 3096 * while the device is in any sort of loopback mode. 3097 */ 3098 rw_exit(&Adapter->chip_lock); 3099 return (EBUSY); 3100 } 3101 3102 switch (pr_num) { 3103 case MAC_PROP_EN_1000FDX_CAP: 3104 if (hw->phy.media_type != e1000_media_type_copper) { 3105 err = ENOTSUP; 3106 break; 3107 } 3108 Adapter->param_en_1000fdx = *(uint8_t *)pr_val; 3109 Adapter->param_adv_1000fdx = *(uint8_t *)pr_val; 3110 goto reset; 3111 case MAC_PROP_EN_100FDX_CAP: 3112 if (hw->phy.media_type != e1000_media_type_copper) { 3113 err = ENOTSUP; 3114 break; 3115 } 3116 Adapter->param_en_100fdx = *(uint8_t *)pr_val; 3117 Adapter->param_adv_100fdx = *(uint8_t *)pr_val; 3118 goto reset; 3119 case MAC_PROP_EN_100HDX_CAP: 3120 if (hw->phy.media_type != e1000_media_type_copper) { 3121 err = ENOTSUP; 3122 break; 3123 } 3124 Adapter->param_en_100hdx = *(uint8_t *)pr_val; 3125 Adapter->param_adv_100hdx = *(uint8_t *)pr_val; 3126 goto reset; 3127 case MAC_PROP_EN_10FDX_CAP: 3128 if (hw->phy.media_type != e1000_media_type_copper) { 3129 err = ENOTSUP; 3130 break; 3131 } 3132 Adapter->param_en_10fdx = *(uint8_t *)pr_val; 3133 Adapter->param_adv_10fdx = *(uint8_t *)pr_val; 3134 goto reset; 3135 case MAC_PROP_EN_10HDX_CAP: 3136 if (hw->phy.media_type != e1000_media_type_copper) { 3137 err = ENOTSUP; 3138 break; 3139 } 3140 Adapter->param_en_10hdx = *(uint8_t *)pr_val; 3141 Adapter->param_adv_10hdx = *(uint8_t *)pr_val; 3142 goto reset; 3143 case MAC_PROP_AUTONEG: 3144 if (hw->phy.media_type != e1000_media_type_copper) { 3145 err = ENOTSUP; 3146 break; 3147 } 3148 Adapter->param_adv_autoneg = *(uint8_t *)pr_val; 3149 goto reset; 3150 case MAC_PROP_FLOWCTRL: 3151 fc->send_xon = B_TRUE; 3152 bcopy(pr_val, &flowctrl, sizeof (flowctrl)); 3153 3154 switch (flowctrl) { 3155 default: 3156 err = EINVAL; 3157 break; 3158 case LINK_FLOWCTRL_NONE: 3159 fc->requested_mode = e1000_fc_none; 3160 break; 3161 case LINK_FLOWCTRL_RX: 3162 fc->requested_mode = e1000_fc_rx_pause; 3163 break; 3164 case LINK_FLOWCTRL_TX: 3165 fc->requested_mode = e1000_fc_tx_pause; 3166 break; 3167 case LINK_FLOWCTRL_BI: 3168 fc->requested_mode = e1000_fc_full; 3169 break; 3170 } 3171 reset: 3172 if (err == 0) { 3173 /* check PCH limits & reset the link */ 3174 e1000g_pch_limits(Adapter); 3175 if (e1000g_reset_link(Adapter) != DDI_SUCCESS) 3176 err = EINVAL; 3177 } 3178 break; 3179 case MAC_PROP_ADV_1000FDX_CAP: 3180 case MAC_PROP_ADV_1000HDX_CAP: 3181 case MAC_PROP_ADV_100FDX_CAP: 3182 case MAC_PROP_ADV_100HDX_CAP: 3183 case MAC_PROP_ADV_10FDX_CAP: 3184 case MAC_PROP_ADV_10HDX_CAP: 3185 case MAC_PROP_EN_1000HDX_CAP: 3186 case MAC_PROP_STATUS: 3187 case MAC_PROP_SPEED: 3188 case MAC_PROP_DUPLEX: 3189 err = ENOTSUP; /* read-only prop. Can't set this. */ 3190 break; 3191 case MAC_PROP_MTU: 3192 /* adapter must be stopped for an MTU change */ 3193 if (Adapter->e1000g_state & E1000G_STARTED) { 3194 err = EBUSY; 3195 break; 3196 } 3197 3198 cur_mtu = Adapter->default_mtu; 3199 3200 /* get new requested MTU */ 3201 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 3202 if (new_mtu == cur_mtu) { 3203 err = 0; 3204 break; 3205 } 3206 3207 if ((new_mtu < DEFAULT_MTU) || 3208 (new_mtu > Adapter->max_mtu)) { 3209 err = EINVAL; 3210 break; 3211 } 3212 3213 /* inform MAC framework of new MTU */ 3214 err = mac_maxsdu_update(Adapter->mh, new_mtu); 3215 3216 if (err == 0) { 3217 Adapter->default_mtu = new_mtu; 3218 Adapter->max_frame_size = 3219 e1000g_mtu2maxframe(new_mtu); 3220 3221 /* 3222 * check PCH limits & set buffer sizes to 3223 * match new MTU 3224 */ 3225 e1000g_pch_limits(Adapter); 3226 e1000g_set_bufsize(Adapter); 3227 3228 /* 3229 * decrease the number of descriptors and free 3230 * packets for jumbo frames to reduce tx/rx 3231 * resource consumption 3232 */ 3233 if (Adapter->max_frame_size >= 3234 (FRAME_SIZE_UPTO_4K - 3235 E1000G_IPALIGNPRESERVEROOM)) { 3236 3237 if (Adapter->tx_desc_num_flag == 0) 3238 Adapter->tx_desc_num = 3239 DEFAULT_JUMBO_NUM_TX_DESC; 3240 3241 if (Adapter->rx_desc_num_flag == 0) 3242 Adapter->rx_desc_num = 3243 DEFAULT_JUMBO_NUM_RX_DESC; 3244 3245 if (Adapter->tx_buf_num_flag == 0) 3246 Adapter->tx_freelist_num = 3247 DEFAULT_JUMBO_NUM_TX_BUF; 3248 3249 if (Adapter->rx_buf_num_flag == 0) 3250 Adapter->rx_freelist_num = 3251 DEFAULT_JUMBO_NUM_RX_BUF; 3252 } else { 3253 if (Adapter->tx_desc_num_flag == 0) 3254 Adapter->tx_desc_num = 3255 DEFAULT_NUM_TX_DESCRIPTOR; 3256 3257 if (Adapter->rx_desc_num_flag == 0) 3258 Adapter->rx_desc_num = 3259 DEFAULT_NUM_RX_DESCRIPTOR; 3260 3261 if (Adapter->tx_buf_num_flag == 0) 3262 Adapter->tx_freelist_num = 3263 DEFAULT_NUM_TX_FREELIST; 3264 3265 if (Adapter->rx_buf_num_flag == 0) 3266 Adapter->rx_freelist_num = 3267 DEFAULT_NUM_RX_FREELIST; 3268 } 3269 } 3270 break; 3271 case MAC_PROP_PRIVATE: 3272 err = e1000g_set_priv_prop(Adapter, pr_name, 3273 pr_valsize, pr_val); 3274 break; 3275 default: 3276 err = ENOTSUP; 3277 break; 3278 } 3279 rw_exit(&Adapter->chip_lock); 3280 return (err); 3281 } 3282 3283 static int 3284 e1000g_m_getprop(void *arg, const char *pr_name, mac_prop_id_t pr_num, 3285 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3286 { 3287 struct e1000g *Adapter = arg; 3288 struct e1000_fc_info *fc = &Adapter->shared.fc; 3289 struct e1000_hw *hw = &Adapter->shared; 3290 int err = 0; 3291 link_flowctrl_t flowctrl; 3292 uint64_t tmp = 0; 3293 3294 if (pr_valsize == 0) 3295 return (EINVAL); 3296 3297 *perm = MAC_PROP_PERM_RW; 3298 3299 bzero(pr_val, pr_valsize); 3300 if ((pr_flags & MAC_PROP_DEFAULT) && (pr_num != MAC_PROP_PRIVATE)) { 3301 return (e1000g_get_def_val(Adapter, pr_num, 3302 pr_valsize, pr_val)); 3303 } 3304 3305 switch (pr_num) { 3306 case MAC_PROP_DUPLEX: 3307 *perm = MAC_PROP_PERM_READ; 3308 if (pr_valsize >= sizeof (link_duplex_t)) { 3309 bcopy(&Adapter->link_duplex, pr_val, 3310 sizeof (link_duplex_t)); 3311 } else 3312 err = EINVAL; 3313 break; 3314 case MAC_PROP_SPEED: 3315 *perm = MAC_PROP_PERM_READ; 3316 if (pr_valsize >= sizeof (uint64_t)) { 3317 tmp = Adapter->link_speed * 1000000ull; 3318 bcopy(&tmp, pr_val, sizeof (tmp)); 3319 } else 3320 err = EINVAL; 3321 break; 3322 case MAC_PROP_AUTONEG: 3323 if (hw->phy.media_type != e1000_media_type_copper) 3324 *perm = MAC_PROP_PERM_READ; 3325 *(uint8_t *)pr_val = Adapter->param_adv_autoneg; 3326 break; 3327 case MAC_PROP_FLOWCTRL: 3328 if (pr_valsize >= sizeof (link_flowctrl_t)) { 3329 switch (fc->current_mode) { 3330 case e1000_fc_none: 3331 flowctrl = LINK_FLOWCTRL_NONE; 3332 break; 3333 case e1000_fc_rx_pause: 3334 flowctrl = LINK_FLOWCTRL_RX; 3335 break; 3336 case e1000_fc_tx_pause: 3337 flowctrl = LINK_FLOWCTRL_TX; 3338 break; 3339 case e1000_fc_full: 3340 flowctrl = LINK_FLOWCTRL_BI; 3341 break; 3342 } 3343 bcopy(&flowctrl, pr_val, sizeof (flowctrl)); 3344 } else 3345 err = EINVAL; 3346 break; 3347 case MAC_PROP_ADV_1000FDX_CAP: 3348 *perm = MAC_PROP_PERM_READ; 3349 *(uint8_t *)pr_val = Adapter->param_adv_1000fdx; 3350 break; 3351 case MAC_PROP_EN_1000FDX_CAP: 3352 if (hw->phy.media_type != e1000_media_type_copper) 3353 *perm = MAC_PROP_PERM_READ; 3354 *(uint8_t *)pr_val = Adapter->param_en_1000fdx; 3355 break; 3356 case MAC_PROP_ADV_1000HDX_CAP: 3357 *perm = MAC_PROP_PERM_READ; 3358 *(uint8_t *)pr_val = Adapter->param_adv_1000hdx; 3359 break; 3360 case MAC_PROP_EN_1000HDX_CAP: 3361 *perm = MAC_PROP_PERM_READ; 3362 *(uint8_t *)pr_val = Adapter->param_en_1000hdx; 3363 break; 3364 case MAC_PROP_ADV_100FDX_CAP: 3365 *perm = MAC_PROP_PERM_READ; 3366 *(uint8_t *)pr_val = Adapter->param_adv_100fdx; 3367 break; 3368 case MAC_PROP_EN_100FDX_CAP: 3369 if (hw->phy.media_type != e1000_media_type_copper) 3370 *perm = MAC_PROP_PERM_READ; 3371 *(uint8_t *)pr_val = Adapter->param_en_100fdx; 3372 break; 3373 case MAC_PROP_ADV_100HDX_CAP: 3374 *perm = MAC_PROP_PERM_READ; 3375 *(uint8_t *)pr_val = Adapter->param_adv_100hdx; 3376 break; 3377 case MAC_PROP_EN_100HDX_CAP: 3378 if (hw->phy.media_type != e1000_media_type_copper) 3379 *perm = MAC_PROP_PERM_READ; 3380 *(uint8_t *)pr_val = Adapter->param_en_100hdx; 3381 break; 3382 case MAC_PROP_ADV_10FDX_CAP: 3383 *perm = MAC_PROP_PERM_READ; 3384 *(uint8_t *)pr_val = Adapter->param_adv_10fdx; 3385 break; 3386 case MAC_PROP_EN_10FDX_CAP: 3387 if (hw->phy.media_type != e1000_media_type_copper) 3388 *perm = MAC_PROP_PERM_READ; 3389 *(uint8_t *)pr_val = Adapter->param_en_10fdx; 3390 break; 3391 case MAC_PROP_ADV_10HDX_CAP: 3392 *perm = MAC_PROP_PERM_READ; 3393 *(uint8_t *)pr_val = Adapter->param_adv_10hdx; 3394 break; 3395 case MAC_PROP_EN_10HDX_CAP: 3396 if (hw->phy.media_type != e1000_media_type_copper) 3397 *perm = MAC_PROP_PERM_READ; 3398 *(uint8_t *)pr_val = Adapter->param_en_10hdx; 3399 break; 3400 case MAC_PROP_ADV_100T4_CAP: 3401 case MAC_PROP_EN_100T4_CAP: 3402 *perm = MAC_PROP_PERM_READ; 3403 *(uint8_t *)pr_val = Adapter->param_adv_100t4; 3404 break; 3405 case MAC_PROP_PRIVATE: 3406 err = e1000g_get_priv_prop(Adapter, pr_name, 3407 pr_flags, pr_valsize, pr_val, perm); 3408 break; 3409 case MAC_PROP_MTU: { 3410 struct e1000_mac_info *mac = &Adapter->shared.mac; 3411 struct e1000_phy_info *phy = &Adapter->shared.phy; 3412 mac_propval_range_t range; 3413 3414 if (!(pr_flags & MAC_PROP_POSSIBLE)) 3415 return (ENOTSUP); 3416 if (pr_valsize < sizeof (mac_propval_range_t)) 3417 return (EINVAL); 3418 range.mpr_count = 1; 3419 range.mpr_type = MAC_PROPVAL_UINT32; 3420 range.range_uint32[0].mpur_min = DEFAULT_MTU; 3421 range.range_uint32[0].mpur_max = Adapter->max_mtu; 3422 /* following MAC type do not support jumbo frames */ 3423 if ((mac->type == e1000_ich8lan) || 3424 ((mac->type == e1000_ich9lan) && (phy->type == 3425 e1000_phy_ife))) { 3426 range.range_uint32[0].mpur_max = DEFAULT_MTU; 3427 } 3428 bcopy(&range, pr_val, sizeof (range)); 3429 break; 3430 } 3431 default: 3432 err = ENOTSUP; 3433 break; 3434 } 3435 return (err); 3436 } 3437 3438 /* ARGSUSED2 */ 3439 static int 3440 e1000g_set_priv_prop(struct e1000g *Adapter, const char *pr_name, 3441 uint_t pr_valsize, const void *pr_val) 3442 { 3443 int err = 0; 3444 long result; 3445 struct e1000_hw *hw = &Adapter->shared; 3446 3447 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3448 if (pr_val == NULL) { 3449 err = EINVAL; 3450 return (err); 3451 } 3452 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3453 if (result < MIN_TX_BCOPY_THRESHOLD || 3454 result > MAX_TX_BCOPY_THRESHOLD) 3455 err = EINVAL; 3456 else { 3457 Adapter->tx_bcopy_thresh = (uint32_t)result; 3458 } 3459 return (err); 3460 } 3461 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3462 if (pr_val == NULL) { 3463 err = EINVAL; 3464 return (err); 3465 } 3466 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3467 if (result < 0 || result > 1) 3468 err = EINVAL; 3469 else { 3470 Adapter->tx_intr_enable = (result == 1) ? 3471 B_TRUE: B_FALSE; 3472 if (Adapter->tx_intr_enable) 3473 e1000g_mask_tx_interrupt(Adapter); 3474 else 3475 e1000g_clear_tx_interrupt(Adapter); 3476 if (e1000g_check_acc_handle( 3477 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3478 ddi_fm_service_impact(Adapter->dip, 3479 DDI_SERVICE_DEGRADED); 3480 err = EIO; 3481 } 3482 } 3483 return (err); 3484 } 3485 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3486 if (pr_val == NULL) { 3487 err = EINVAL; 3488 return (err); 3489 } 3490 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3491 if (result < MIN_TX_INTR_DELAY || 3492 result > MAX_TX_INTR_DELAY) 3493 err = EINVAL; 3494 else { 3495 Adapter->tx_intr_delay = (uint32_t)result; 3496 E1000_WRITE_REG(hw, E1000_TIDV, Adapter->tx_intr_delay); 3497 if (e1000g_check_acc_handle( 3498 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3499 ddi_fm_service_impact(Adapter->dip, 3500 DDI_SERVICE_DEGRADED); 3501 err = EIO; 3502 } 3503 } 3504 return (err); 3505 } 3506 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3507 if (pr_val == NULL) { 3508 err = EINVAL; 3509 return (err); 3510 } 3511 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3512 if (result < MIN_TX_INTR_ABS_DELAY || 3513 result > MAX_TX_INTR_ABS_DELAY) 3514 err = EINVAL; 3515 else { 3516 Adapter->tx_intr_abs_delay = (uint32_t)result; 3517 E1000_WRITE_REG(hw, E1000_TADV, 3518 Adapter->tx_intr_abs_delay); 3519 if (e1000g_check_acc_handle( 3520 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3521 ddi_fm_service_impact(Adapter->dip, 3522 DDI_SERVICE_DEGRADED); 3523 err = EIO; 3524 } 3525 } 3526 return (err); 3527 } 3528 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3529 if (pr_val == NULL) { 3530 err = EINVAL; 3531 return (err); 3532 } 3533 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3534 if (result < MIN_RX_BCOPY_THRESHOLD || 3535 result > MAX_RX_BCOPY_THRESHOLD) 3536 err = EINVAL; 3537 else 3538 Adapter->rx_bcopy_thresh = (uint32_t)result; 3539 return (err); 3540 } 3541 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3542 if (pr_val == NULL) { 3543 err = EINVAL; 3544 return (err); 3545 } 3546 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3547 if (result < MIN_RX_LIMIT_ON_INTR || 3548 result > MAX_RX_LIMIT_ON_INTR) 3549 err = EINVAL; 3550 else 3551 Adapter->rx_limit_onintr = (uint32_t)result; 3552 return (err); 3553 } 3554 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3555 if (pr_val == NULL) { 3556 err = EINVAL; 3557 return (err); 3558 } 3559 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3560 if (result < MIN_RX_INTR_DELAY || 3561 result > MAX_RX_INTR_DELAY) 3562 err = EINVAL; 3563 else { 3564 Adapter->rx_intr_delay = (uint32_t)result; 3565 E1000_WRITE_REG(hw, E1000_RDTR, Adapter->rx_intr_delay); 3566 if (e1000g_check_acc_handle( 3567 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3568 ddi_fm_service_impact(Adapter->dip, 3569 DDI_SERVICE_DEGRADED); 3570 err = EIO; 3571 } 3572 } 3573 return (err); 3574 } 3575 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3576 if (pr_val == NULL) { 3577 err = EINVAL; 3578 return (err); 3579 } 3580 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3581 if (result < MIN_RX_INTR_ABS_DELAY || 3582 result > MAX_RX_INTR_ABS_DELAY) 3583 err = EINVAL; 3584 else { 3585 Adapter->rx_intr_abs_delay = (uint32_t)result; 3586 E1000_WRITE_REG(hw, E1000_RADV, 3587 Adapter->rx_intr_abs_delay); 3588 if (e1000g_check_acc_handle( 3589 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3590 ddi_fm_service_impact(Adapter->dip, 3591 DDI_SERVICE_DEGRADED); 3592 err = EIO; 3593 } 3594 } 3595 return (err); 3596 } 3597 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3598 if (pr_val == NULL) { 3599 err = EINVAL; 3600 return (err); 3601 } 3602 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3603 if (result < MIN_INTR_THROTTLING || 3604 result > MAX_INTR_THROTTLING) 3605 err = EINVAL; 3606 else { 3607 if (hw->mac.type >= e1000_82540) { 3608 Adapter->intr_throttling_rate = 3609 (uint32_t)result; 3610 E1000_WRITE_REG(hw, E1000_ITR, 3611 Adapter->intr_throttling_rate); 3612 if (e1000g_check_acc_handle( 3613 Adapter->osdep.reg_handle) != DDI_FM_OK) { 3614 ddi_fm_service_impact(Adapter->dip, 3615 DDI_SERVICE_DEGRADED); 3616 err = EIO; 3617 } 3618 } else 3619 err = EINVAL; 3620 } 3621 return (err); 3622 } 3623 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3624 if (pr_val == NULL) { 3625 err = EINVAL; 3626 return (err); 3627 } 3628 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 3629 if (result < 0 || result > 1) 3630 err = EINVAL; 3631 else { 3632 if (hw->mac.type >= e1000_82540) { 3633 Adapter->intr_adaptive = (result == 1) ? 3634 B_TRUE : B_FALSE; 3635 } else { 3636 err = EINVAL; 3637 } 3638 } 3639 return (err); 3640 } 3641 return (ENOTSUP); 3642 } 3643 3644 static int 3645 e1000g_get_priv_prop(struct e1000g *Adapter, const char *pr_name, 3646 uint_t pr_flags, uint_t pr_valsize, void *pr_val, uint_t *perm) 3647 { 3648 int err = ENOTSUP; 3649 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 3650 int value; 3651 3652 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 3653 *perm = MAC_PROP_PERM_READ; 3654 if (is_default) 3655 goto done; 3656 value = Adapter->param_adv_pause; 3657 err = 0; 3658 goto done; 3659 } 3660 if (strcmp(pr_name, "_adv_asym_pause_cap") == 0) { 3661 *perm = MAC_PROP_PERM_READ; 3662 if (is_default) 3663 goto done; 3664 value = Adapter->param_adv_asym_pause; 3665 err = 0; 3666 goto done; 3667 } 3668 if (strcmp(pr_name, "_tx_bcopy_threshold") == 0) { 3669 value = (is_default ? DEFAULT_TX_BCOPY_THRESHOLD : 3670 Adapter->tx_bcopy_thresh); 3671 err = 0; 3672 goto done; 3673 } 3674 if (strcmp(pr_name, "_tx_interrupt_enable") == 0) { 3675 value = (is_default ? DEFAULT_TX_INTR_ENABLE : 3676 Adapter->tx_intr_enable); 3677 err = 0; 3678 goto done; 3679 } 3680 if (strcmp(pr_name, "_tx_intr_delay") == 0) { 3681 value = (is_default ? DEFAULT_TX_INTR_DELAY : 3682 Adapter->tx_intr_delay); 3683 err = 0; 3684 goto done; 3685 } 3686 if (strcmp(pr_name, "_tx_intr_abs_delay") == 0) { 3687 value = (is_default ? DEFAULT_TX_INTR_ABS_DELAY : 3688 Adapter->tx_intr_abs_delay); 3689 err = 0; 3690 goto done; 3691 } 3692 if (strcmp(pr_name, "_rx_bcopy_threshold") == 0) { 3693 value = (is_default ? DEFAULT_RX_BCOPY_THRESHOLD : 3694 Adapter->rx_bcopy_thresh); 3695 err = 0; 3696 goto done; 3697 } 3698 if (strcmp(pr_name, "_max_num_rcv_packets") == 0) { 3699 value = (is_default ? DEFAULT_RX_LIMIT_ON_INTR : 3700 Adapter->rx_limit_onintr); 3701 err = 0; 3702 goto done; 3703 } 3704 if (strcmp(pr_name, "_rx_intr_delay") == 0) { 3705 value = (is_default ? DEFAULT_RX_INTR_DELAY : 3706 Adapter->rx_intr_delay); 3707 err = 0; 3708 goto done; 3709 } 3710 if (strcmp(pr_name, "_rx_intr_abs_delay") == 0) { 3711 value = (is_default ? DEFAULT_RX_INTR_ABS_DELAY : 3712 Adapter->rx_intr_abs_delay); 3713 err = 0; 3714 goto done; 3715 } 3716 if (strcmp(pr_name, "_intr_throttling_rate") == 0) { 3717 value = (is_default ? DEFAULT_INTR_THROTTLING : 3718 Adapter->intr_throttling_rate); 3719 err = 0; 3720 goto done; 3721 } 3722 if (strcmp(pr_name, "_intr_adaptive") == 0) { 3723 value = (is_default ? 1 : Adapter->intr_adaptive); 3724 err = 0; 3725 goto done; 3726 } 3727 done: 3728 if (err == 0) { 3729 (void) snprintf(pr_val, pr_valsize, "%d", value); 3730 } 3731 return (err); 3732 } 3733 3734 /* 3735 * e1000g_get_conf - get configurations set in e1000g.conf 3736 * This routine gets user-configured values out of the configuration 3737 * file e1000g.conf. 3738 * 3739 * For each configurable value, there is a minimum, a maximum, and a 3740 * default. 3741 * If user does not configure a value, use the default. 3742 * If user configures below the minimum, use the minumum. 3743 * If user configures above the maximum, use the maxumum. 3744 */ 3745 static void 3746 e1000g_get_conf(struct e1000g *Adapter) 3747 { 3748 struct e1000_hw *hw = &Adapter->shared; 3749 boolean_t tbi_compatibility = B_FALSE; 3750 boolean_t is_jumbo = B_FALSE; 3751 int propval; 3752 /* 3753 * decrease the number of descriptors and free packets 3754 * for jumbo frames to reduce tx/rx resource consumption 3755 */ 3756 if (Adapter->max_frame_size >= 3757 (FRAME_SIZE_UPTO_4K - 3758 E1000G_IPALIGNPRESERVEROOM)) { 3759 is_jumbo = B_TRUE; 3760 } 3761 3762 /* 3763 * get each configurable property from e1000g.conf 3764 */ 3765 3766 /* 3767 * NumTxDescriptors 3768 */ 3769 Adapter->tx_desc_num_flag = 3770 e1000g_get_prop(Adapter, "NumTxDescriptors", 3771 MIN_NUM_TX_DESCRIPTOR, MAX_NUM_TX_DESCRIPTOR, 3772 is_jumbo ? DEFAULT_JUMBO_NUM_TX_DESC 3773 : DEFAULT_NUM_TX_DESCRIPTOR, &propval); 3774 Adapter->tx_desc_num = propval; 3775 3776 /* 3777 * NumRxDescriptors 3778 */ 3779 Adapter->rx_desc_num_flag = 3780 e1000g_get_prop(Adapter, "NumRxDescriptors", 3781 MIN_NUM_RX_DESCRIPTOR, MAX_NUM_RX_DESCRIPTOR, 3782 is_jumbo ? DEFAULT_JUMBO_NUM_RX_DESC 3783 : DEFAULT_NUM_RX_DESCRIPTOR, &propval); 3784 Adapter->rx_desc_num = propval; 3785 3786 /* 3787 * NumRxFreeList 3788 */ 3789 Adapter->rx_buf_num_flag = 3790 e1000g_get_prop(Adapter, "NumRxFreeList", 3791 MIN_NUM_RX_FREELIST, MAX_NUM_RX_FREELIST, 3792 is_jumbo ? DEFAULT_JUMBO_NUM_RX_BUF 3793 : DEFAULT_NUM_RX_FREELIST, &propval); 3794 Adapter->rx_freelist_num = propval; 3795 3796 /* 3797 * NumTxPacketList 3798 */ 3799 Adapter->tx_buf_num_flag = 3800 e1000g_get_prop(Adapter, "NumTxPacketList", 3801 MIN_NUM_TX_FREELIST, MAX_NUM_TX_FREELIST, 3802 is_jumbo ? DEFAULT_JUMBO_NUM_TX_BUF 3803 : DEFAULT_NUM_TX_FREELIST, &propval); 3804 Adapter->tx_freelist_num = propval; 3805 3806 /* 3807 * FlowControl 3808 */ 3809 hw->fc.send_xon = B_TRUE; 3810 (void) e1000g_get_prop(Adapter, "FlowControl", 3811 e1000_fc_none, 4, DEFAULT_FLOW_CONTROL, &propval); 3812 hw->fc.requested_mode = propval; 3813 /* 4 is the setting that says "let the eeprom decide" */ 3814 if (hw->fc.requested_mode == 4) 3815 hw->fc.requested_mode = e1000_fc_default; 3816 3817 /* 3818 * Max Num Receive Packets on Interrupt 3819 */ 3820 (void) e1000g_get_prop(Adapter, "MaxNumReceivePackets", 3821 MIN_RX_LIMIT_ON_INTR, MAX_RX_LIMIT_ON_INTR, 3822 DEFAULT_RX_LIMIT_ON_INTR, &propval); 3823 Adapter->rx_limit_onintr = propval; 3824 3825 /* 3826 * PHY master slave setting 3827 */ 3828 (void) e1000g_get_prop(Adapter, "SetMasterSlave", 3829 e1000_ms_hw_default, e1000_ms_auto, 3830 e1000_ms_hw_default, &propval); 3831 hw->phy.ms_type = propval; 3832 3833 /* 3834 * Parameter which controls TBI mode workaround, which is only 3835 * needed on certain switches such as Cisco 6500/Foundry 3836 */ 3837 (void) e1000g_get_prop(Adapter, "TbiCompatibilityEnable", 3838 0, 1, DEFAULT_TBI_COMPAT_ENABLE, &propval); 3839 tbi_compatibility = (propval == 1); 3840 e1000_set_tbi_compatibility_82543(hw, tbi_compatibility); 3841 3842 /* 3843 * MSI Enable 3844 */ 3845 (void) e1000g_get_prop(Adapter, "MSIEnable", 3846 0, 1, DEFAULT_MSI_ENABLE, &propval); 3847 Adapter->msi_enable = (propval == 1); 3848 3849 /* 3850 * Interrupt Throttling Rate 3851 */ 3852 (void) e1000g_get_prop(Adapter, "intr_throttling_rate", 3853 MIN_INTR_THROTTLING, MAX_INTR_THROTTLING, 3854 DEFAULT_INTR_THROTTLING, &propval); 3855 Adapter->intr_throttling_rate = propval; 3856 3857 /* 3858 * Adaptive Interrupt Blanking Enable/Disable 3859 * It is enabled by default 3860 */ 3861 (void) e1000g_get_prop(Adapter, "intr_adaptive", 0, 1, 1, 3862 &propval); 3863 Adapter->intr_adaptive = (propval == 1); 3864 3865 /* 3866 * Hardware checksum enable/disable parameter 3867 */ 3868 (void) e1000g_get_prop(Adapter, "tx_hcksum_enable", 3869 0, 1, DEFAULT_TX_HCKSUM_ENABLE, &propval); 3870 Adapter->tx_hcksum_enable = (propval == 1); 3871 /* 3872 * Checksum on/off selection via global parameters. 3873 * 3874 * If the chip is flagged as not capable of (correctly) 3875 * handling checksumming, we don't enable it on either 3876 * Rx or Tx side. Otherwise, we take this chip's settings 3877 * from the patchable global defaults. 3878 * 3879 * We advertise our capabilities only if TX offload is 3880 * enabled. On receive, the stack will accept checksummed 3881 * packets anyway, even if we haven't said we can deliver 3882 * them. 3883 */ 3884 switch (hw->mac.type) { 3885 case e1000_82540: 3886 case e1000_82544: 3887 case e1000_82545: 3888 case e1000_82545_rev_3: 3889 case e1000_82546: 3890 case e1000_82546_rev_3: 3891 case e1000_82571: 3892 case e1000_82572: 3893 case e1000_82573: 3894 case e1000_80003es2lan: 3895 break; 3896 /* 3897 * For the following Intel PRO/1000 chipsets, we have not 3898 * tested the hardware checksum offload capability, so we 3899 * disable the capability for them. 3900 * e1000_82542, 3901 * e1000_82543, 3902 * e1000_82541, 3903 * e1000_82541_rev_2, 3904 * e1000_82547, 3905 * e1000_82547_rev_2, 3906 */ 3907 default: 3908 Adapter->tx_hcksum_enable = B_FALSE; 3909 } 3910 3911 /* 3912 * Large Send Offloading(LSO) Enable/Disable 3913 * If the tx hardware checksum is not enabled, LSO should be 3914 * disabled. 3915 */ 3916 (void) e1000g_get_prop(Adapter, "lso_enable", 3917 0, 1, DEFAULT_LSO_ENABLE, &propval); 3918 Adapter->lso_enable = (propval == 1); 3919 3920 switch (hw->mac.type) { 3921 case e1000_82546: 3922 case e1000_82546_rev_3: 3923 if (Adapter->lso_enable) 3924 Adapter->lso_premature_issue = B_TRUE; 3925 /* FALLTHRU */ 3926 case e1000_82571: 3927 case e1000_82572: 3928 case e1000_82573: 3929 case e1000_80003es2lan: 3930 break; 3931 default: 3932 Adapter->lso_enable = B_FALSE; 3933 } 3934 3935 if (!Adapter->tx_hcksum_enable) { 3936 Adapter->lso_premature_issue = B_FALSE; 3937 Adapter->lso_enable = B_FALSE; 3938 } 3939 3940 /* 3941 * If mem_workaround_82546 is enabled, the rx buffer allocated by 3942 * e1000_82545, e1000_82546 and e1000_82546_rev_3 3943 * will not cross 64k boundary. 3944 */ 3945 (void) e1000g_get_prop(Adapter, "mem_workaround_82546", 3946 0, 1, DEFAULT_MEM_WORKAROUND_82546, &propval); 3947 Adapter->mem_workaround_82546 = (propval == 1); 3948 3949 /* 3950 * Max number of multicast addresses 3951 */ 3952 (void) e1000g_get_prop(Adapter, "mcast_max_num", 3953 MIN_MCAST_NUM, MAX_MCAST_NUM, hw->mac.mta_reg_count * 32, 3954 &propval); 3955 Adapter->mcast_max_num = propval; 3956 } 3957 3958 /* 3959 * e1000g_get_prop - routine to read properties 3960 * 3961 * Get a user-configure property value out of the configuration 3962 * file e1000g.conf. 3963 * 3964 * Caller provides name of the property, a default value, a minimum 3965 * value, a maximum value and a pointer to the returned property 3966 * value. 3967 * 3968 * Return B_TRUE if the configured value of the property is not a default 3969 * value, otherwise return B_FALSE. 3970 */ 3971 static boolean_t 3972 e1000g_get_prop(struct e1000g *Adapter, /* point to per-adapter structure */ 3973 char *propname, /* name of the property */ 3974 int minval, /* minimum acceptable value */ 3975 int maxval, /* maximim acceptable value */ 3976 int defval, /* default value */ 3977 int *propvalue) /* property value return to caller */ 3978 { 3979 int propval; /* value returned for requested property */ 3980 int *props; /* point to array of properties returned */ 3981 uint_t nprops; /* number of property value returned */ 3982 boolean_t ret = B_TRUE; 3983 3984 /* 3985 * get the array of properties from the config file 3986 */ 3987 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, Adapter->dip, 3988 DDI_PROP_DONTPASS, propname, &props, &nprops) == DDI_PROP_SUCCESS) { 3989 /* got some properties, test if we got enough */ 3990 if (Adapter->instance < nprops) { 3991 propval = props[Adapter->instance]; 3992 } else { 3993 /* not enough properties configured */ 3994 propval = defval; 3995 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 3996 "Not Enough %s values found in e1000g.conf" 3997 " - set to %d\n", 3998 propname, propval); 3999 ret = B_FALSE; 4000 } 4001 4002 /* free memory allocated for properties */ 4003 ddi_prop_free(props); 4004 4005 } else { 4006 propval = defval; 4007 ret = B_FALSE; 4008 } 4009 4010 /* 4011 * enforce limits 4012 */ 4013 if (propval > maxval) { 4014 propval = maxval; 4015 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4016 "Too High %s value in e1000g.conf - set to %d\n", 4017 propname, propval); 4018 } 4019 4020 if (propval < minval) { 4021 propval = minval; 4022 E1000G_DEBUGLOG_2(Adapter, E1000G_INFO_LEVEL, 4023 "Too Low %s value in e1000g.conf - set to %d\n", 4024 propname, propval); 4025 } 4026 4027 *propvalue = propval; 4028 return (ret); 4029 } 4030 4031 static boolean_t 4032 e1000g_link_check(struct e1000g *Adapter) 4033 { 4034 uint16_t speed, duplex, phydata; 4035 boolean_t link_changed = B_FALSE; 4036 struct e1000_hw *hw; 4037 uint32_t reg_tarc; 4038 4039 hw = &Adapter->shared; 4040 4041 if (e1000g_link_up(Adapter)) { 4042 /* 4043 * The Link is up, check whether it was marked as down earlier 4044 */ 4045 if (Adapter->link_state != LINK_STATE_UP) { 4046 (void) e1000_get_speed_and_duplex(hw, &speed, &duplex); 4047 Adapter->link_speed = speed; 4048 Adapter->link_duplex = duplex; 4049 Adapter->link_state = LINK_STATE_UP; 4050 link_changed = B_TRUE; 4051 4052 if (Adapter->link_speed == SPEED_1000) 4053 Adapter->stall_threshold = TX_STALL_TIME_2S; 4054 else 4055 Adapter->stall_threshold = TX_STALL_TIME_8S; 4056 4057 Adapter->tx_link_down_timeout = 0; 4058 4059 if ((hw->mac.type == e1000_82571) || 4060 (hw->mac.type == e1000_82572)) { 4061 reg_tarc = E1000_READ_REG(hw, E1000_TARC(0)); 4062 if (speed == SPEED_1000) 4063 reg_tarc |= (1 << 21); 4064 else 4065 reg_tarc &= ~(1 << 21); 4066 E1000_WRITE_REG(hw, E1000_TARC(0), reg_tarc); 4067 } 4068 } 4069 Adapter->smartspeed = 0; 4070 } else { 4071 if (Adapter->link_state != LINK_STATE_DOWN) { 4072 Adapter->link_speed = 0; 4073 Adapter->link_duplex = 0; 4074 Adapter->link_state = LINK_STATE_DOWN; 4075 link_changed = B_TRUE; 4076 4077 /* 4078 * SmartSpeed workaround for Tabor/TanaX, When the 4079 * driver loses link disable auto master/slave 4080 * resolution. 4081 */ 4082 if (hw->phy.type == e1000_phy_igp) { 4083 (void) e1000_read_phy_reg(hw, 4084 PHY_1000T_CTRL, &phydata); 4085 phydata |= CR_1000T_MS_ENABLE; 4086 (void) e1000_write_phy_reg(hw, 4087 PHY_1000T_CTRL, phydata); 4088 } 4089 } else { 4090 e1000g_smartspeed(Adapter); 4091 } 4092 4093 if (Adapter->e1000g_state & E1000G_STARTED) { 4094 if (Adapter->tx_link_down_timeout < 4095 MAX_TX_LINK_DOWN_TIMEOUT) { 4096 Adapter->tx_link_down_timeout++; 4097 } else if (Adapter->tx_link_down_timeout == 4098 MAX_TX_LINK_DOWN_TIMEOUT) { 4099 e1000g_tx_clean(Adapter); 4100 Adapter->tx_link_down_timeout++; 4101 } 4102 } 4103 } 4104 4105 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4106 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4107 4108 return (link_changed); 4109 } 4110 4111 /* 4112 * e1000g_reset_link - Using the link properties to setup the link 4113 */ 4114 int 4115 e1000g_reset_link(struct e1000g *Adapter) 4116 { 4117 struct e1000_mac_info *mac; 4118 struct e1000_phy_info *phy; 4119 struct e1000_hw *hw; 4120 boolean_t invalid; 4121 4122 mac = &Adapter->shared.mac; 4123 phy = &Adapter->shared.phy; 4124 hw = &Adapter->shared; 4125 invalid = B_FALSE; 4126 4127 if (hw->phy.media_type != e1000_media_type_copper) 4128 goto out; 4129 4130 if (Adapter->param_adv_autoneg == 1) { 4131 mac->autoneg = B_TRUE; 4132 phy->autoneg_advertised = 0; 4133 4134 /* 4135 * 1000hdx is not supported for autonegotiation 4136 */ 4137 if (Adapter->param_adv_1000fdx == 1) 4138 phy->autoneg_advertised |= ADVERTISE_1000_FULL; 4139 4140 if (Adapter->param_adv_100fdx == 1) 4141 phy->autoneg_advertised |= ADVERTISE_100_FULL; 4142 4143 if (Adapter->param_adv_100hdx == 1) 4144 phy->autoneg_advertised |= ADVERTISE_100_HALF; 4145 4146 if (Adapter->param_adv_10fdx == 1) 4147 phy->autoneg_advertised |= ADVERTISE_10_FULL; 4148 4149 if (Adapter->param_adv_10hdx == 1) 4150 phy->autoneg_advertised |= ADVERTISE_10_HALF; 4151 4152 if (phy->autoneg_advertised == 0) 4153 invalid = B_TRUE; 4154 } else { 4155 mac->autoneg = B_FALSE; 4156 4157 /* 4158 * For Intel copper cards, 1000fdx and 1000hdx are not 4159 * supported for forced link 4160 */ 4161 if (Adapter->param_adv_100fdx == 1) 4162 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4163 else if (Adapter->param_adv_100hdx == 1) 4164 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4165 else if (Adapter->param_adv_10fdx == 1) 4166 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4167 else if (Adapter->param_adv_10hdx == 1) 4168 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4169 else 4170 invalid = B_TRUE; 4171 4172 } 4173 4174 if (invalid) { 4175 e1000g_log(Adapter, CE_WARN, 4176 "Invalid link settings. Setup link to " 4177 "support autonegotiation with all link capabilities."); 4178 mac->autoneg = B_TRUE; 4179 phy->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; 4180 } 4181 4182 out: 4183 return (e1000_setup_link(&Adapter->shared)); 4184 } 4185 4186 static void 4187 e1000g_timer_tx_resched(struct e1000g *Adapter) 4188 { 4189 e1000g_tx_ring_t *tx_ring = Adapter->tx_ring; 4190 4191 rw_enter(&Adapter->chip_lock, RW_READER); 4192 4193 if (tx_ring->resched_needed && 4194 ((ddi_get_lbolt() - tx_ring->resched_timestamp) > 4195 drv_usectohz(1000000)) && 4196 (Adapter->e1000g_state & E1000G_STARTED) && 4197 (tx_ring->tbd_avail >= DEFAULT_TX_NO_RESOURCE)) { 4198 tx_ring->resched_needed = B_FALSE; 4199 mac_tx_update(Adapter->mh); 4200 E1000G_STAT(tx_ring->stat_reschedule); 4201 E1000G_STAT(tx_ring->stat_timer_reschedule); 4202 } 4203 4204 rw_exit(&Adapter->chip_lock); 4205 } 4206 4207 static void 4208 e1000g_local_timer(void *ws) 4209 { 4210 struct e1000g *Adapter = (struct e1000g *)ws; 4211 struct e1000_hw *hw; 4212 e1000g_ether_addr_t ether_addr; 4213 boolean_t link_changed; 4214 4215 hw = &Adapter->shared; 4216 4217 if (Adapter->e1000g_state & E1000G_ERROR) { 4218 rw_enter(&Adapter->chip_lock, RW_WRITER); 4219 Adapter->e1000g_state &= ~E1000G_ERROR; 4220 rw_exit(&Adapter->chip_lock); 4221 4222 Adapter->reset_count++; 4223 if (e1000g_global_reset(Adapter)) { 4224 ddi_fm_service_impact(Adapter->dip, 4225 DDI_SERVICE_RESTORED); 4226 e1000g_timer_tx_resched(Adapter); 4227 } else 4228 ddi_fm_service_impact(Adapter->dip, 4229 DDI_SERVICE_LOST); 4230 return; 4231 } 4232 4233 if (e1000g_stall_check(Adapter)) { 4234 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 4235 "Tx stall detected. Activate automatic recovery.\n"); 4236 e1000g_fm_ereport(Adapter, DDI_FM_DEVICE_STALL); 4237 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_LOST); 4238 Adapter->reset_count++; 4239 if (e1000g_reset_adapter(Adapter)) { 4240 ddi_fm_service_impact(Adapter->dip, 4241 DDI_SERVICE_RESTORED); 4242 e1000g_timer_tx_resched(Adapter); 4243 } 4244 return; 4245 } 4246 4247 link_changed = B_FALSE; 4248 rw_enter(&Adapter->chip_lock, RW_READER); 4249 if (Adapter->link_complete) 4250 link_changed = e1000g_link_check(Adapter); 4251 rw_exit(&Adapter->chip_lock); 4252 4253 if (link_changed) { 4254 if (!Adapter->reset_flag && 4255 (Adapter->e1000g_state & E1000G_STARTED) && 4256 !(Adapter->e1000g_state & E1000G_SUSPENDED)) 4257 mac_link_update(Adapter->mh, Adapter->link_state); 4258 if (Adapter->link_state == LINK_STATE_UP) 4259 Adapter->reset_flag = B_FALSE; 4260 } 4261 /* 4262 * Workaround for esb2. Data stuck in fifo on a link 4263 * down event. Reset the adapter to recover it. 4264 */ 4265 if (Adapter->esb2_workaround) { 4266 Adapter->esb2_workaround = B_FALSE; 4267 (void) e1000g_reset_adapter(Adapter); 4268 return; 4269 } 4270 4271 /* 4272 * With 82571 controllers, any locally administered address will 4273 * be overwritten when there is a reset on the other port. 4274 * Detect this circumstance and correct it. 4275 */ 4276 if ((hw->mac.type == e1000_82571) && 4277 (e1000_get_laa_state_82571(hw) == B_TRUE)) { 4278 ether_addr.reg.low = E1000_READ_REG_ARRAY(hw, E1000_RA, 0); 4279 ether_addr.reg.high = E1000_READ_REG_ARRAY(hw, E1000_RA, 1); 4280 4281 ether_addr.reg.low = ntohl(ether_addr.reg.low); 4282 ether_addr.reg.high = ntohl(ether_addr.reg.high); 4283 4284 if ((ether_addr.mac.addr[5] != hw->mac.addr[0]) || 4285 (ether_addr.mac.addr[4] != hw->mac.addr[1]) || 4286 (ether_addr.mac.addr[3] != hw->mac.addr[2]) || 4287 (ether_addr.mac.addr[2] != hw->mac.addr[3]) || 4288 (ether_addr.mac.addr[1] != hw->mac.addr[4]) || 4289 (ether_addr.mac.addr[0] != hw->mac.addr[5])) { 4290 e1000_rar_set(hw, hw->mac.addr, 0); 4291 } 4292 } 4293 4294 /* 4295 * Long TTL workaround for 82541/82547 4296 */ 4297 (void) e1000_igp_ttl_workaround_82547(hw); 4298 4299 /* 4300 * Check for Adaptive IFS settings If there are lots of collisions 4301 * change the value in steps... 4302 * These properties should only be set for 10/100 4303 */ 4304 if ((hw->phy.media_type == e1000_media_type_copper) && 4305 ((Adapter->link_speed == SPEED_100) || 4306 (Adapter->link_speed == SPEED_10))) { 4307 e1000_update_adaptive(hw); 4308 } 4309 /* 4310 * Set Timer Interrupts 4311 */ 4312 E1000_WRITE_REG(hw, E1000_ICS, E1000_IMS_RXT0); 4313 4314 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) 4315 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 4316 else 4317 e1000g_timer_tx_resched(Adapter); 4318 4319 restart_watchdog_timer(Adapter); 4320 } 4321 4322 /* 4323 * The function e1000g_link_timer() is called when the timer for link setup 4324 * is expired, which indicates the completion of the link setup. The link 4325 * state will not be updated until the link setup is completed. And the 4326 * link state will not be sent to the upper layer through mac_link_update() 4327 * in this function. It will be updated in the local timer routine or the 4328 * interrupt service routine after the interface is started (plumbed). 4329 */ 4330 static void 4331 e1000g_link_timer(void *arg) 4332 { 4333 struct e1000g *Adapter = (struct e1000g *)arg; 4334 4335 mutex_enter(&Adapter->link_lock); 4336 Adapter->link_complete = B_TRUE; 4337 Adapter->link_tid = 0; 4338 mutex_exit(&Adapter->link_lock); 4339 } 4340 4341 /* 4342 * e1000g_force_speed_duplex - read forced speed/duplex out of e1000g.conf 4343 * 4344 * This function read the forced speed and duplex for 10/100 Mbps speeds 4345 * and also for 1000 Mbps speeds from the e1000g.conf file 4346 */ 4347 static void 4348 e1000g_force_speed_duplex(struct e1000g *Adapter) 4349 { 4350 int forced; 4351 int propval; 4352 struct e1000_mac_info *mac = &Adapter->shared.mac; 4353 struct e1000_phy_info *phy = &Adapter->shared.phy; 4354 4355 /* 4356 * get value out of config file 4357 */ 4358 (void) e1000g_get_prop(Adapter, "ForceSpeedDuplex", 4359 GDIAG_10_HALF, GDIAG_ANY, GDIAG_ANY, &forced); 4360 4361 switch (forced) { 4362 case GDIAG_10_HALF: 4363 /* 4364 * Disable Auto Negotiation 4365 */ 4366 mac->autoneg = B_FALSE; 4367 mac->forced_speed_duplex = ADVERTISE_10_HALF; 4368 break; 4369 case GDIAG_10_FULL: 4370 /* 4371 * Disable Auto Negotiation 4372 */ 4373 mac->autoneg = B_FALSE; 4374 mac->forced_speed_duplex = ADVERTISE_10_FULL; 4375 break; 4376 case GDIAG_100_HALF: 4377 /* 4378 * Disable Auto Negotiation 4379 */ 4380 mac->autoneg = B_FALSE; 4381 mac->forced_speed_duplex = ADVERTISE_100_HALF; 4382 break; 4383 case GDIAG_100_FULL: 4384 /* 4385 * Disable Auto Negotiation 4386 */ 4387 mac->autoneg = B_FALSE; 4388 mac->forced_speed_duplex = ADVERTISE_100_FULL; 4389 break; 4390 case GDIAG_1000_FULL: 4391 /* 4392 * The gigabit spec requires autonegotiation. Therefore, 4393 * when the user wants to force the speed to 1000Mbps, we 4394 * enable AutoNeg, but only allow the harware to advertise 4395 * 1000Mbps. This is different from 10/100 operation, where 4396 * we are allowed to link without any negotiation. 4397 */ 4398 mac->autoneg = B_TRUE; 4399 phy->autoneg_advertised = ADVERTISE_1000_FULL; 4400 break; 4401 default: /* obey the setting of AutoNegAdvertised */ 4402 mac->autoneg = B_TRUE; 4403 (void) e1000g_get_prop(Adapter, "AutoNegAdvertised", 4404 0, AUTONEG_ADVERTISE_SPEED_DEFAULT, 4405 AUTONEG_ADVERTISE_SPEED_DEFAULT, &propval); 4406 phy->autoneg_advertised = (uint16_t)propval; 4407 break; 4408 } /* switch */ 4409 } 4410 4411 /* 4412 * e1000g_get_max_frame_size - get jumbo frame setting from e1000g.conf 4413 * 4414 * This function reads MaxFrameSize from e1000g.conf 4415 */ 4416 static void 4417 e1000g_get_max_frame_size(struct e1000g *Adapter) 4418 { 4419 int max_frame; 4420 4421 /* 4422 * get value out of config file 4423 */ 4424 (void) e1000g_get_prop(Adapter, "MaxFrameSize", 0, 3, 0, 4425 &max_frame); 4426 4427 switch (max_frame) { 4428 case 0: 4429 Adapter->default_mtu = ETHERMTU; 4430 break; 4431 /* 4432 * To avoid excessive memory allocation for rx buffers, 4433 * the bytes of E1000G_IPALIGNPRESERVEROOM are reserved. 4434 */ 4435 case 1: 4436 Adapter->default_mtu = FRAME_SIZE_UPTO_4K - 4437 sizeof (struct ether_vlan_header) - ETHERFCSL - 4438 E1000G_IPALIGNPRESERVEROOM; 4439 break; 4440 case 2: 4441 Adapter->default_mtu = FRAME_SIZE_UPTO_8K - 4442 sizeof (struct ether_vlan_header) - ETHERFCSL - 4443 E1000G_IPALIGNPRESERVEROOM; 4444 break; 4445 case 3: 4446 Adapter->default_mtu = FRAME_SIZE_UPTO_16K - 4447 sizeof (struct ether_vlan_header) - ETHERFCSL - 4448 E1000G_IPALIGNPRESERVEROOM; 4449 break; 4450 default: 4451 Adapter->default_mtu = ETHERMTU; 4452 break; 4453 } /* switch */ 4454 4455 /* 4456 * If the user configed MTU is larger than the deivce's maximum MTU, 4457 * the MTU is set to the deivce's maximum value. 4458 */ 4459 if (Adapter->default_mtu > Adapter->max_mtu) 4460 Adapter->default_mtu = Adapter->max_mtu; 4461 4462 Adapter->max_frame_size = e1000g_mtu2maxframe(Adapter->default_mtu); 4463 } 4464 4465 /* 4466 * e1000g_pch_limits - Apply limits of the PCH silicon type 4467 * 4468 * At any frame size larger than the ethernet default, 4469 * prevent linking at 10/100 speeds. 4470 */ 4471 static void 4472 e1000g_pch_limits(struct e1000g *Adapter) 4473 { 4474 struct e1000_hw *hw = &Adapter->shared; 4475 4476 /* only applies to PCH silicon type */ 4477 if (hw->mac.type != e1000_pchlan) 4478 return; 4479 4480 /* only applies to frames larger than ethernet default */ 4481 if (Adapter->max_frame_size > DEFAULT_FRAME_SIZE) { 4482 hw->mac.autoneg = B_TRUE; 4483 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL; 4484 4485 Adapter->param_adv_autoneg = 1; 4486 Adapter->param_adv_1000fdx = 1; 4487 4488 Adapter->param_adv_100fdx = 0; 4489 Adapter->param_adv_100hdx = 0; 4490 Adapter->param_adv_10fdx = 0; 4491 Adapter->param_adv_10hdx = 0; 4492 4493 e1000g_param_sync(Adapter); 4494 } 4495 } 4496 4497 /* 4498 * e1000g_mtu2maxframe - convert given MTU to maximum frame size 4499 */ 4500 static uint32_t 4501 e1000g_mtu2maxframe(uint32_t mtu) 4502 { 4503 uint32_t maxframe; 4504 4505 maxframe = mtu + sizeof (struct ether_vlan_header) + ETHERFCSL; 4506 4507 return (maxframe); 4508 } 4509 4510 static void 4511 arm_watchdog_timer(struct e1000g *Adapter) 4512 { 4513 Adapter->watchdog_tid = 4514 timeout(e1000g_local_timer, 4515 (void *)Adapter, 1 * drv_usectohz(1000000)); 4516 } 4517 #pragma inline(arm_watchdog_timer) 4518 4519 static void 4520 enable_watchdog_timer(struct e1000g *Adapter) 4521 { 4522 mutex_enter(&Adapter->watchdog_lock); 4523 4524 if (!Adapter->watchdog_timer_enabled) { 4525 Adapter->watchdog_timer_enabled = B_TRUE; 4526 Adapter->watchdog_timer_started = B_TRUE; 4527 arm_watchdog_timer(Adapter); 4528 } 4529 4530 mutex_exit(&Adapter->watchdog_lock); 4531 } 4532 4533 static void 4534 disable_watchdog_timer(struct e1000g *Adapter) 4535 { 4536 timeout_id_t tid; 4537 4538 mutex_enter(&Adapter->watchdog_lock); 4539 4540 Adapter->watchdog_timer_enabled = B_FALSE; 4541 Adapter->watchdog_timer_started = B_FALSE; 4542 tid = Adapter->watchdog_tid; 4543 Adapter->watchdog_tid = 0; 4544 4545 mutex_exit(&Adapter->watchdog_lock); 4546 4547 if (tid != 0) 4548 (void) untimeout(tid); 4549 } 4550 4551 static void 4552 start_watchdog_timer(struct e1000g *Adapter) 4553 { 4554 mutex_enter(&Adapter->watchdog_lock); 4555 4556 if (Adapter->watchdog_timer_enabled) { 4557 if (!Adapter->watchdog_timer_started) { 4558 Adapter->watchdog_timer_started = B_TRUE; 4559 arm_watchdog_timer(Adapter); 4560 } 4561 } 4562 4563 mutex_exit(&Adapter->watchdog_lock); 4564 } 4565 4566 static void 4567 restart_watchdog_timer(struct e1000g *Adapter) 4568 { 4569 mutex_enter(&Adapter->watchdog_lock); 4570 4571 if (Adapter->watchdog_timer_started) 4572 arm_watchdog_timer(Adapter); 4573 4574 mutex_exit(&Adapter->watchdog_lock); 4575 } 4576 4577 static void 4578 stop_watchdog_timer(struct e1000g *Adapter) 4579 { 4580 timeout_id_t tid; 4581 4582 mutex_enter(&Adapter->watchdog_lock); 4583 4584 Adapter->watchdog_timer_started = B_FALSE; 4585 tid = Adapter->watchdog_tid; 4586 Adapter->watchdog_tid = 0; 4587 4588 mutex_exit(&Adapter->watchdog_lock); 4589 4590 if (tid != 0) 4591 (void) untimeout(tid); 4592 } 4593 4594 static void 4595 stop_link_timer(struct e1000g *Adapter) 4596 { 4597 timeout_id_t tid; 4598 4599 /* Disable the link timer */ 4600 mutex_enter(&Adapter->link_lock); 4601 4602 tid = Adapter->link_tid; 4603 Adapter->link_tid = 0; 4604 4605 mutex_exit(&Adapter->link_lock); 4606 4607 if (tid != 0) 4608 (void) untimeout(tid); 4609 } 4610 4611 static void 4612 stop_82547_timer(e1000g_tx_ring_t *tx_ring) 4613 { 4614 timeout_id_t tid; 4615 4616 /* Disable the tx timer for 82547 chipset */ 4617 mutex_enter(&tx_ring->tx_lock); 4618 4619 tx_ring->timer_enable_82547 = B_FALSE; 4620 tid = tx_ring->timer_id_82547; 4621 tx_ring->timer_id_82547 = 0; 4622 4623 mutex_exit(&tx_ring->tx_lock); 4624 4625 if (tid != 0) 4626 (void) untimeout(tid); 4627 } 4628 4629 void 4630 e1000g_clear_interrupt(struct e1000g *Adapter) 4631 { 4632 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 4633 0xffffffff & ~E1000_IMS_RXSEQ); 4634 } 4635 4636 void 4637 e1000g_mask_interrupt(struct e1000g *Adapter) 4638 { 4639 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, 4640 IMS_ENABLE_MASK & ~E1000_IMS_TXDW); 4641 4642 if (Adapter->tx_intr_enable) 4643 e1000g_mask_tx_interrupt(Adapter); 4644 } 4645 4646 /* 4647 * This routine is called by e1000g_quiesce(), therefore must not block. 4648 */ 4649 void 4650 e1000g_clear_all_interrupts(struct e1000g *Adapter) 4651 { 4652 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, 0xffffffff); 4653 } 4654 4655 void 4656 e1000g_mask_tx_interrupt(struct e1000g *Adapter) 4657 { 4658 E1000_WRITE_REG(&Adapter->shared, E1000_IMS, E1000_IMS_TXDW); 4659 } 4660 4661 void 4662 e1000g_clear_tx_interrupt(struct e1000g *Adapter) 4663 { 4664 E1000_WRITE_REG(&Adapter->shared, E1000_IMC, E1000_IMS_TXDW); 4665 } 4666 4667 static void 4668 e1000g_smartspeed(struct e1000g *Adapter) 4669 { 4670 struct e1000_hw *hw = &Adapter->shared; 4671 uint16_t phy_status; 4672 uint16_t phy_ctrl; 4673 4674 /* 4675 * If we're not T-or-T, or we're not autoneg'ing, or we're not 4676 * advertising 1000Full, we don't even use the workaround 4677 */ 4678 if ((hw->phy.type != e1000_phy_igp) || 4679 !hw->mac.autoneg || 4680 !(hw->phy.autoneg_advertised & ADVERTISE_1000_FULL)) 4681 return; 4682 4683 /* 4684 * True if this is the first call of this function or after every 4685 * 30 seconds of not having link 4686 */ 4687 if (Adapter->smartspeed == 0) { 4688 /* 4689 * If Master/Slave config fault is asserted twice, we 4690 * assume back-to-back 4691 */ 4692 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4693 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4694 return; 4695 4696 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_status); 4697 if (!(phy_status & SR_1000T_MS_CONFIG_FAULT)) 4698 return; 4699 /* 4700 * We're assuming back-2-back because our status register 4701 * insists! there's a fault in the master/slave 4702 * relationship that was "negotiated" 4703 */ 4704 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4705 /* 4706 * Is the phy configured for manual configuration of 4707 * master/slave? 4708 */ 4709 if (phy_ctrl & CR_1000T_MS_ENABLE) { 4710 /* 4711 * Yes. Then disable manual configuration (enable 4712 * auto configuration) of master/slave 4713 */ 4714 phy_ctrl &= ~CR_1000T_MS_ENABLE; 4715 (void) e1000_write_phy_reg(hw, 4716 PHY_1000T_CTRL, phy_ctrl); 4717 /* 4718 * Effectively starting the clock 4719 */ 4720 Adapter->smartspeed++; 4721 /* 4722 * Restart autonegotiation 4723 */ 4724 if (!e1000_phy_setup_autoneg(hw) && 4725 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4726 phy_ctrl |= (MII_CR_AUTO_NEG_EN | 4727 MII_CR_RESTART_AUTO_NEG); 4728 (void) e1000_write_phy_reg(hw, 4729 PHY_CONTROL, phy_ctrl); 4730 } 4731 } 4732 return; 4733 /* 4734 * Has 6 seconds transpired still without link? Remember, 4735 * you should reset the smartspeed counter once you obtain 4736 * link 4737 */ 4738 } else if (Adapter->smartspeed == E1000_SMARTSPEED_DOWNSHIFT) { 4739 /* 4740 * Yes. Remember, we did at the start determine that 4741 * there's a master/slave configuration fault, so we're 4742 * still assuming there's someone on the other end, but we 4743 * just haven't yet been able to talk to it. We then 4744 * re-enable auto configuration of master/slave to see if 4745 * we're running 2/3 pair cables. 4746 */ 4747 /* 4748 * If still no link, perhaps using 2/3 pair cable 4749 */ 4750 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_ctrl); 4751 phy_ctrl |= CR_1000T_MS_ENABLE; 4752 (void) e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_ctrl); 4753 /* 4754 * Restart autoneg with phy enabled for manual 4755 * configuration of master/slave 4756 */ 4757 if (!e1000_phy_setup_autoneg(hw) && 4758 !e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl)) { 4759 phy_ctrl |= 4760 (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 4761 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl); 4762 } 4763 /* 4764 * Hopefully, there are no more faults and we've obtained 4765 * link as a result. 4766 */ 4767 } 4768 /* 4769 * Restart process after E1000_SMARTSPEED_MAX iterations (30 4770 * seconds) 4771 */ 4772 if (Adapter->smartspeed++ == E1000_SMARTSPEED_MAX) 4773 Adapter->smartspeed = 0; 4774 } 4775 4776 static boolean_t 4777 is_valid_mac_addr(uint8_t *mac_addr) 4778 { 4779 const uint8_t addr_test1[6] = { 0, 0, 0, 0, 0, 0 }; 4780 const uint8_t addr_test2[6] = 4781 { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; 4782 4783 if (!(bcmp(addr_test1, mac_addr, ETHERADDRL)) || 4784 !(bcmp(addr_test2, mac_addr, ETHERADDRL))) 4785 return (B_FALSE); 4786 4787 return (B_TRUE); 4788 } 4789 4790 /* 4791 * e1000g_stall_check - check for tx stall 4792 * 4793 * This function checks if the adapter is stalled (in transmit). 4794 * 4795 * It is called each time the watchdog timeout is invoked. 4796 * If the transmit descriptor reclaim continuously fails, 4797 * the watchdog value will increment by 1. If the watchdog 4798 * value exceeds the threshold, the adapter is assumed to 4799 * have stalled and need to be reset. 4800 */ 4801 static boolean_t 4802 e1000g_stall_check(struct e1000g *Adapter) 4803 { 4804 e1000g_tx_ring_t *tx_ring; 4805 4806 tx_ring = Adapter->tx_ring; 4807 4808 if (Adapter->link_state != LINK_STATE_UP) 4809 return (B_FALSE); 4810 4811 (void) e1000g_recycle(tx_ring); 4812 4813 if (Adapter->stall_flag) 4814 return (B_TRUE); 4815 4816 return (B_FALSE); 4817 } 4818 4819 #ifdef E1000G_DEBUG 4820 static enum ioc_reply 4821 e1000g_pp_ioctl(struct e1000g *e1000gp, struct iocblk *iocp, mblk_t *mp) 4822 { 4823 void (*ppfn)(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd); 4824 e1000g_peekpoke_t *ppd; 4825 uint64_t mem_va; 4826 uint64_t maxoff; 4827 boolean_t peek; 4828 4829 switch (iocp->ioc_cmd) { 4830 4831 case E1000G_IOC_REG_PEEK: 4832 peek = B_TRUE; 4833 break; 4834 4835 case E1000G_IOC_REG_POKE: 4836 peek = B_FALSE; 4837 break; 4838 4839 deault: 4840 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4841 "e1000g_diag_ioctl: invalid ioctl command 0x%X\n", 4842 iocp->ioc_cmd); 4843 return (IOC_INVAL); 4844 } 4845 4846 /* 4847 * Validate format of ioctl 4848 */ 4849 if (iocp->ioc_count != sizeof (e1000g_peekpoke_t)) 4850 return (IOC_INVAL); 4851 if (mp->b_cont == NULL) 4852 return (IOC_INVAL); 4853 4854 ppd = (e1000g_peekpoke_t *)(uintptr_t)mp->b_cont->b_rptr; 4855 4856 /* 4857 * Validate request parameters 4858 */ 4859 switch (ppd->pp_acc_space) { 4860 4861 default: 4862 E1000G_DEBUGLOG_1(e1000gp, E1000G_INFO_LEVEL, 4863 "e1000g_diag_ioctl: invalid access space 0x%X\n", 4864 ppd->pp_acc_space); 4865 return (IOC_INVAL); 4866 4867 case E1000G_PP_SPACE_REG: 4868 /* 4869 * Memory-mapped I/O space 4870 */ 4871 ASSERT(ppd->pp_acc_size == 4); 4872 if (ppd->pp_acc_size != 4) 4873 return (IOC_INVAL); 4874 4875 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 4876 return (IOC_INVAL); 4877 4878 mem_va = 0; 4879 maxoff = 0x10000; 4880 ppfn = peek ? e1000g_ioc_peek_reg : e1000g_ioc_poke_reg; 4881 break; 4882 4883 case E1000G_PP_SPACE_E1000G: 4884 /* 4885 * E1000g data structure! 4886 */ 4887 mem_va = (uintptr_t)e1000gp; 4888 maxoff = sizeof (struct e1000g); 4889 ppfn = peek ? e1000g_ioc_peek_mem : e1000g_ioc_poke_mem; 4890 break; 4891 4892 } 4893 4894 if (ppd->pp_acc_offset >= maxoff) 4895 return (IOC_INVAL); 4896 4897 if (ppd->pp_acc_offset + ppd->pp_acc_size > maxoff) 4898 return (IOC_INVAL); 4899 4900 /* 4901 * All OK - go! 4902 */ 4903 ppd->pp_acc_offset += mem_va; 4904 (*ppfn)(e1000gp, ppd); 4905 return (peek ? IOC_REPLY : IOC_ACK); 4906 } 4907 4908 static void 4909 e1000g_ioc_peek_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4910 { 4911 ddi_acc_handle_t handle; 4912 uint32_t *regaddr; 4913 4914 handle = e1000gp->osdep.reg_handle; 4915 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4916 (uintptr_t)ppd->pp_acc_offset); 4917 4918 ppd->pp_acc_data = ddi_get32(handle, regaddr); 4919 } 4920 4921 static void 4922 e1000g_ioc_poke_reg(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4923 { 4924 ddi_acc_handle_t handle; 4925 uint32_t *regaddr; 4926 uint32_t value; 4927 4928 handle = e1000gp->osdep.reg_handle; 4929 regaddr = (uint32_t *)((uintptr_t)e1000gp->shared.hw_addr + 4930 (uintptr_t)ppd->pp_acc_offset); 4931 value = (uint32_t)ppd->pp_acc_data; 4932 4933 ddi_put32(handle, regaddr, value); 4934 } 4935 4936 static void 4937 e1000g_ioc_peek_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4938 { 4939 uint64_t value; 4940 void *vaddr; 4941 4942 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4943 4944 switch (ppd->pp_acc_size) { 4945 case 1: 4946 value = *(uint8_t *)vaddr; 4947 break; 4948 4949 case 2: 4950 value = *(uint16_t *)vaddr; 4951 break; 4952 4953 case 4: 4954 value = *(uint32_t *)vaddr; 4955 break; 4956 4957 case 8: 4958 value = *(uint64_t *)vaddr; 4959 break; 4960 } 4961 4962 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4963 "e1000g_ioc_peek_mem($%p, $%p) peeked 0x%llx from $%p\n", 4964 (void *)e1000gp, (void *)ppd, value, vaddr); 4965 4966 ppd->pp_acc_data = value; 4967 } 4968 4969 static void 4970 e1000g_ioc_poke_mem(struct e1000g *e1000gp, e1000g_peekpoke_t *ppd) 4971 { 4972 uint64_t value; 4973 void *vaddr; 4974 4975 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 4976 value = ppd->pp_acc_data; 4977 4978 E1000G_DEBUGLOG_4(e1000gp, E1000G_INFO_LEVEL, 4979 "e1000g_ioc_poke_mem($%p, $%p) poking 0x%llx at $%p\n", 4980 (void *)e1000gp, (void *)ppd, value, vaddr); 4981 4982 switch (ppd->pp_acc_size) { 4983 case 1: 4984 *(uint8_t *)vaddr = (uint8_t)value; 4985 break; 4986 4987 case 2: 4988 *(uint16_t *)vaddr = (uint16_t)value; 4989 break; 4990 4991 case 4: 4992 *(uint32_t *)vaddr = (uint32_t)value; 4993 break; 4994 4995 case 8: 4996 *(uint64_t *)vaddr = (uint64_t)value; 4997 break; 4998 } 4999 } 5000 #endif 5001 5002 /* 5003 * Loopback Support 5004 */ 5005 static lb_property_t lb_normal = 5006 { normal, "normal", E1000G_LB_NONE }; 5007 static lb_property_t lb_external1000 = 5008 { external, "1000Mbps", E1000G_LB_EXTERNAL_1000 }; 5009 static lb_property_t lb_external100 = 5010 { external, "100Mbps", E1000G_LB_EXTERNAL_100 }; 5011 static lb_property_t lb_external10 = 5012 { external, "10Mbps", E1000G_LB_EXTERNAL_10 }; 5013 static lb_property_t lb_phy = 5014 { internal, "PHY", E1000G_LB_INTERNAL_PHY }; 5015 5016 static enum ioc_reply 5017 e1000g_loopback_ioctl(struct e1000g *Adapter, struct iocblk *iocp, mblk_t *mp) 5018 { 5019 lb_info_sz_t *lbsp; 5020 lb_property_t *lbpp; 5021 struct e1000_hw *hw; 5022 uint32_t *lbmp; 5023 uint32_t size; 5024 uint32_t value; 5025 5026 hw = &Adapter->shared; 5027 5028 if (mp->b_cont == NULL) 5029 return (IOC_INVAL); 5030 5031 if (!e1000g_check_loopback_support(hw)) { 5032 e1000g_log(NULL, CE_WARN, 5033 "Loopback is not supported on e1000g%d", Adapter->instance); 5034 return (IOC_INVAL); 5035 } 5036 5037 switch (iocp->ioc_cmd) { 5038 default: 5039 return (IOC_INVAL); 5040 5041 case LB_GET_INFO_SIZE: 5042 size = sizeof (lb_info_sz_t); 5043 if (iocp->ioc_count != size) 5044 return (IOC_INVAL); 5045 5046 rw_enter(&Adapter->chip_lock, RW_WRITER); 5047 e1000g_get_phy_state(Adapter); 5048 5049 /* 5050 * Workaround for hardware faults. In order to get a stable 5051 * state of phy, we will wait for a specific interval and 5052 * try again. The time delay is an experiential value based 5053 * on our testing. 5054 */ 5055 msec_delay(100); 5056 e1000g_get_phy_state(Adapter); 5057 rw_exit(&Adapter->chip_lock); 5058 5059 value = sizeof (lb_normal); 5060 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5061 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5062 (hw->phy.media_type == e1000_media_type_fiber) || 5063 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5064 value += sizeof (lb_phy); 5065 switch (hw->mac.type) { 5066 case e1000_82571: 5067 case e1000_82572: 5068 case e1000_80003es2lan: 5069 value += sizeof (lb_external1000); 5070 break; 5071 } 5072 } 5073 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5074 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5075 value += sizeof (lb_external100); 5076 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5077 value += sizeof (lb_external10); 5078 5079 lbsp = (lb_info_sz_t *)(uintptr_t)mp->b_cont->b_rptr; 5080 *lbsp = value; 5081 break; 5082 5083 case LB_GET_INFO: 5084 value = sizeof (lb_normal); 5085 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5086 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5087 (hw->phy.media_type == e1000_media_type_fiber) || 5088 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5089 value += sizeof (lb_phy); 5090 switch (hw->mac.type) { 5091 case e1000_82571: 5092 case e1000_82572: 5093 case e1000_80003es2lan: 5094 value += sizeof (lb_external1000); 5095 break; 5096 } 5097 } 5098 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5099 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5100 value += sizeof (lb_external100); 5101 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5102 value += sizeof (lb_external10); 5103 5104 size = value; 5105 if (iocp->ioc_count != size) 5106 return (IOC_INVAL); 5107 5108 value = 0; 5109 lbpp = (lb_property_t *)(uintptr_t)mp->b_cont->b_rptr; 5110 lbpp[value++] = lb_normal; 5111 if ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 5112 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS) || 5113 (hw->phy.media_type == e1000_media_type_fiber) || 5114 (hw->phy.media_type == e1000_media_type_internal_serdes)) { 5115 lbpp[value++] = lb_phy; 5116 switch (hw->mac.type) { 5117 case e1000_82571: 5118 case e1000_82572: 5119 case e1000_80003es2lan: 5120 lbpp[value++] = lb_external1000; 5121 break; 5122 } 5123 } 5124 if ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 5125 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 5126 lbpp[value++] = lb_external100; 5127 if (Adapter->phy_status & MII_SR_10T_FD_CAPS) 5128 lbpp[value++] = lb_external10; 5129 break; 5130 5131 case LB_GET_MODE: 5132 size = sizeof (uint32_t); 5133 if (iocp->ioc_count != size) 5134 return (IOC_INVAL); 5135 5136 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5137 *lbmp = Adapter->loopback_mode; 5138 break; 5139 5140 case LB_SET_MODE: 5141 size = 0; 5142 if (iocp->ioc_count != sizeof (uint32_t)) 5143 return (IOC_INVAL); 5144 5145 lbmp = (uint32_t *)(uintptr_t)mp->b_cont->b_rptr; 5146 if (!e1000g_set_loopback_mode(Adapter, *lbmp)) 5147 return (IOC_INVAL); 5148 break; 5149 } 5150 5151 iocp->ioc_count = size; 5152 iocp->ioc_error = 0; 5153 5154 if (e1000g_check_acc_handle(Adapter->osdep.reg_handle) != DDI_FM_OK) { 5155 ddi_fm_service_impact(Adapter->dip, DDI_SERVICE_DEGRADED); 5156 return (IOC_INVAL); 5157 } 5158 5159 return (IOC_REPLY); 5160 } 5161 5162 static boolean_t 5163 e1000g_check_loopback_support(struct e1000_hw *hw) 5164 { 5165 switch (hw->mac.type) { 5166 case e1000_82540: 5167 case e1000_82545: 5168 case e1000_82545_rev_3: 5169 case e1000_82546: 5170 case e1000_82546_rev_3: 5171 case e1000_82541: 5172 case e1000_82541_rev_2: 5173 case e1000_82547: 5174 case e1000_82547_rev_2: 5175 case e1000_82571: 5176 case e1000_82572: 5177 case e1000_82573: 5178 case e1000_82574: 5179 case e1000_80003es2lan: 5180 case e1000_ich9lan: 5181 case e1000_ich10lan: 5182 return (B_TRUE); 5183 } 5184 return (B_FALSE); 5185 } 5186 5187 static boolean_t 5188 e1000g_set_loopback_mode(struct e1000g *Adapter, uint32_t mode) 5189 { 5190 struct e1000_hw *hw; 5191 int i, times; 5192 boolean_t link_up; 5193 5194 if (mode == Adapter->loopback_mode) 5195 return (B_TRUE); 5196 5197 hw = &Adapter->shared; 5198 times = 0; 5199 5200 Adapter->loopback_mode = mode; 5201 5202 if (mode == E1000G_LB_NONE) { 5203 /* Reset the chip */ 5204 hw->phy.autoneg_wait_to_complete = B_TRUE; 5205 (void) e1000g_reset_adapter(Adapter); 5206 hw->phy.autoneg_wait_to_complete = B_FALSE; 5207 return (B_TRUE); 5208 } 5209 5210 again: 5211 5212 rw_enter(&Adapter->chip_lock, RW_WRITER); 5213 5214 switch (mode) { 5215 default: 5216 rw_exit(&Adapter->chip_lock); 5217 return (B_FALSE); 5218 5219 case E1000G_LB_EXTERNAL_1000: 5220 e1000g_set_external_loopback_1000(Adapter); 5221 break; 5222 5223 case E1000G_LB_EXTERNAL_100: 5224 e1000g_set_external_loopback_100(Adapter); 5225 break; 5226 5227 case E1000G_LB_EXTERNAL_10: 5228 e1000g_set_external_loopback_10(Adapter); 5229 break; 5230 5231 case E1000G_LB_INTERNAL_PHY: 5232 e1000g_set_internal_loopback(Adapter); 5233 break; 5234 } 5235 5236 times++; 5237 5238 rw_exit(&Adapter->chip_lock); 5239 5240 /* Wait for link up */ 5241 for (i = (PHY_FORCE_LIMIT * 2); i > 0; i--) 5242 msec_delay(100); 5243 5244 rw_enter(&Adapter->chip_lock, RW_WRITER); 5245 5246 link_up = e1000g_link_up(Adapter); 5247 5248 rw_exit(&Adapter->chip_lock); 5249 5250 if (!link_up) { 5251 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5252 "Failed to get the link up"); 5253 if (times < 2) { 5254 /* Reset the link */ 5255 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5256 "Reset the link ..."); 5257 (void) e1000g_reset_adapter(Adapter); 5258 goto again; 5259 } 5260 5261 /* 5262 * Reset driver to loopback none when set loopback failed 5263 * for the second time. 5264 */ 5265 Adapter->loopback_mode = E1000G_LB_NONE; 5266 5267 /* Reset the chip */ 5268 hw->phy.autoneg_wait_to_complete = B_TRUE; 5269 (void) e1000g_reset_adapter(Adapter); 5270 hw->phy.autoneg_wait_to_complete = B_FALSE; 5271 5272 E1000G_DEBUGLOG_0(Adapter, E1000G_INFO_LEVEL, 5273 "Set loopback mode failed, reset to loopback none"); 5274 5275 return (B_FALSE); 5276 } 5277 5278 return (B_TRUE); 5279 } 5280 5281 /* 5282 * The following loopback settings are from Intel's technical 5283 * document - "How To Loopback". All the register settings and 5284 * time delay values are directly inherited from the document 5285 * without more explanations available. 5286 */ 5287 static void 5288 e1000g_set_internal_loopback(struct e1000g *Adapter) 5289 { 5290 struct e1000_hw *hw; 5291 uint32_t ctrl; 5292 uint32_t status; 5293 uint16_t phy_ctrl; 5294 uint16_t phy_reg; 5295 uint32_t txcw; 5296 5297 hw = &Adapter->shared; 5298 5299 /* Disable Smart Power Down */ 5300 phy_spd_state(hw, B_FALSE); 5301 5302 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &phy_ctrl); 5303 phy_ctrl &= ~(MII_CR_AUTO_NEG_EN | MII_CR_SPEED_100 | MII_CR_SPEED_10); 5304 phy_ctrl |= MII_CR_FULL_DUPLEX | MII_CR_SPEED_1000; 5305 5306 switch (hw->mac.type) { 5307 case e1000_82540: 5308 case e1000_82545: 5309 case e1000_82545_rev_3: 5310 case e1000_82546: 5311 case e1000_82546_rev_3: 5312 case e1000_82573: 5313 /* Auto-MDI/MDIX off */ 5314 (void) e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 5315 /* Reset PHY to update Auto-MDI/MDIX */ 5316 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5317 phy_ctrl | MII_CR_RESET | MII_CR_AUTO_NEG_EN); 5318 /* Reset PHY to auto-neg off and force 1000 */ 5319 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5320 phy_ctrl | MII_CR_RESET); 5321 /* 5322 * Disable PHY receiver for 82540/545/546 and 82573 Family. 5323 * See comments above e1000g_set_internal_loopback() for the 5324 * background. 5325 */ 5326 (void) e1000_write_phy_reg(hw, 29, 0x001F); 5327 (void) e1000_write_phy_reg(hw, 30, 0x8FFC); 5328 (void) e1000_write_phy_reg(hw, 29, 0x001A); 5329 (void) e1000_write_phy_reg(hw, 30, 0x8FF0); 5330 break; 5331 case e1000_80003es2lan: 5332 /* Force Link Up */ 5333 (void) e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 5334 0x1CC); 5335 /* Sets PCS loopback at 1Gbs */ 5336 (void) e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 5337 0x1046); 5338 break; 5339 } 5340 5341 /* 5342 * The following registers should be set for e1000_phy_bm phy type. 5343 * e1000_82574, e1000_ich10lan and some e1000_ich9lan use this phy. 5344 * For others, we do not need to set these registers. 5345 */ 5346 if (hw->phy.type == e1000_phy_bm) { 5347 /* Set Default MAC Interface speed to 1GB */ 5348 (void) e1000_read_phy_reg(hw, PHY_REG(2, 21), &phy_reg); 5349 phy_reg &= ~0x0007; 5350 phy_reg |= 0x006; 5351 (void) e1000_write_phy_reg(hw, PHY_REG(2, 21), phy_reg); 5352 /* Assert SW reset for above settings to take effect */ 5353 (void) e1000_phy_commit(hw); 5354 msec_delay(1); 5355 /* Force Full Duplex */ 5356 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5357 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5358 phy_reg | 0x000C); 5359 /* Set Link Up (in force link) */ 5360 (void) e1000_read_phy_reg(hw, PHY_REG(776, 16), &phy_reg); 5361 (void) e1000_write_phy_reg(hw, PHY_REG(776, 16), 5362 phy_reg | 0x0040); 5363 /* Force Link */ 5364 (void) e1000_read_phy_reg(hw, PHY_REG(769, 16), &phy_reg); 5365 (void) e1000_write_phy_reg(hw, PHY_REG(769, 16), 5366 phy_reg | 0x0040); 5367 /* Set Early Link Enable */ 5368 (void) e1000_read_phy_reg(hw, PHY_REG(769, 20), &phy_reg); 5369 (void) e1000_write_phy_reg(hw, PHY_REG(769, 20), 5370 phy_reg | 0x0400); 5371 } 5372 5373 /* Set loopback */ 5374 (void) e1000_write_phy_reg(hw, PHY_CONTROL, phy_ctrl | MII_CR_LOOPBACK); 5375 5376 msec_delay(250); 5377 5378 /* Now set up the MAC to the same speed/duplex as the PHY. */ 5379 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5380 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5381 ctrl |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5382 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5383 E1000_CTRL_SPD_1000 | /* Force Speed to 1000 */ 5384 E1000_CTRL_FD); /* Force Duplex to FULL */ 5385 5386 switch (hw->mac.type) { 5387 case e1000_82540: 5388 case e1000_82545: 5389 case e1000_82545_rev_3: 5390 case e1000_82546: 5391 case e1000_82546_rev_3: 5392 /* 5393 * For some serdes we'll need to commit the writes now 5394 * so that the status is updated on link 5395 */ 5396 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 5397 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5398 msec_delay(100); 5399 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5400 } 5401 5402 if (hw->phy.media_type == e1000_media_type_copper) { 5403 /* Invert Loss of Signal */ 5404 ctrl |= E1000_CTRL_ILOS; 5405 } else { 5406 /* Set ILOS on fiber nic if half duplex is detected */ 5407 status = E1000_READ_REG(hw, E1000_STATUS); 5408 if ((status & E1000_STATUS_FD) == 0) 5409 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5410 } 5411 break; 5412 5413 case e1000_82571: 5414 case e1000_82572: 5415 /* 5416 * The fiber/SerDes versions of this adapter do not contain an 5417 * accessible PHY. Therefore, loopback beyond MAC must be done 5418 * using SerDes analog loopback. 5419 */ 5420 if (hw->phy.media_type != e1000_media_type_copper) { 5421 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5422 txcw = E1000_READ_REG(hw, E1000_TXCW); 5423 txcw &= ~((uint32_t)1 << 31); 5424 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5425 5426 /* 5427 * Write 0x410 to Serdes Control register 5428 * to enable Serdes analog loopback 5429 */ 5430 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5431 msec_delay(10); 5432 } 5433 5434 status = E1000_READ_REG(hw, E1000_STATUS); 5435 /* Set ILOS on fiber nic if half duplex is detected */ 5436 if ((hw->phy.media_type == e1000_media_type_fiber) && 5437 ((status & E1000_STATUS_FD) == 0 || 5438 (status & E1000_STATUS_LU) == 0)) 5439 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5440 else if (hw->phy.media_type == e1000_media_type_internal_serdes) 5441 ctrl |= E1000_CTRL_SLU; 5442 break; 5443 5444 case e1000_82573: 5445 ctrl |= E1000_CTRL_ILOS; 5446 break; 5447 case e1000_ich9lan: 5448 case e1000_ich10lan: 5449 ctrl |= E1000_CTRL_SLU; 5450 break; 5451 } 5452 if (hw->phy.type == e1000_phy_bm) 5453 ctrl |= E1000_CTRL_SLU | E1000_CTRL_ILOS; 5454 5455 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5456 } 5457 5458 static void 5459 e1000g_set_external_loopback_1000(struct e1000g *Adapter) 5460 { 5461 struct e1000_hw *hw; 5462 uint32_t rctl; 5463 uint32_t ctrl_ext; 5464 uint32_t ctrl; 5465 uint32_t status; 5466 uint32_t txcw; 5467 uint16_t phydata; 5468 5469 hw = &Adapter->shared; 5470 5471 /* Disable Smart Power Down */ 5472 phy_spd_state(hw, B_FALSE); 5473 5474 switch (hw->mac.type) { 5475 case e1000_82571: 5476 case e1000_82572: 5477 switch (hw->phy.media_type) { 5478 case e1000_media_type_copper: 5479 /* Force link up (Must be done before the PHY writes) */ 5480 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5481 ctrl |= E1000_CTRL_SLU; /* Force Link Up */ 5482 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5483 5484 rctl = E1000_READ_REG(hw, E1000_RCTL); 5485 rctl |= (E1000_RCTL_EN | 5486 E1000_RCTL_SBP | 5487 E1000_RCTL_UPE | 5488 E1000_RCTL_MPE | 5489 E1000_RCTL_LPE | 5490 E1000_RCTL_BAM); /* 0x803E */ 5491 E1000_WRITE_REG(hw, E1000_RCTL, rctl); 5492 5493 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 5494 ctrl_ext |= (E1000_CTRL_EXT_SDP4_DATA | 5495 E1000_CTRL_EXT_SDP6_DATA | 5496 E1000_CTRL_EXT_SDP3_DATA | 5497 E1000_CTRL_EXT_SDP4_DIR | 5498 E1000_CTRL_EXT_SDP6_DIR | 5499 E1000_CTRL_EXT_SDP3_DIR); /* 0x0DD0 */ 5500 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 5501 5502 /* 5503 * This sequence tunes the PHY's SDP and no customer 5504 * settable values. For background, see comments above 5505 * e1000g_set_internal_loopback(). 5506 */ 5507 (void) e1000_write_phy_reg(hw, 0x0, 0x140); 5508 msec_delay(10); 5509 (void) e1000_write_phy_reg(hw, 0x9, 0x1A00); 5510 (void) e1000_write_phy_reg(hw, 0x12, 0xC10); 5511 (void) e1000_write_phy_reg(hw, 0x12, 0x1C10); 5512 (void) e1000_write_phy_reg(hw, 0x1F37, 0x76); 5513 (void) e1000_write_phy_reg(hw, 0x1F33, 0x1); 5514 (void) e1000_write_phy_reg(hw, 0x1F33, 0x0); 5515 5516 (void) e1000_write_phy_reg(hw, 0x1F35, 0x65); 5517 (void) e1000_write_phy_reg(hw, 0x1837, 0x3F7C); 5518 (void) e1000_write_phy_reg(hw, 0x1437, 0x3FDC); 5519 (void) e1000_write_phy_reg(hw, 0x1237, 0x3F7C); 5520 (void) e1000_write_phy_reg(hw, 0x1137, 0x3FDC); 5521 5522 msec_delay(50); 5523 break; 5524 case e1000_media_type_fiber: 5525 case e1000_media_type_internal_serdes: 5526 status = E1000_READ_REG(hw, E1000_STATUS); 5527 if (((status & E1000_STATUS_LU) == 0) || 5528 (hw->phy.media_type == 5529 e1000_media_type_internal_serdes)) { 5530 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5531 ctrl |= E1000_CTRL_ILOS | E1000_CTRL_SLU; 5532 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5533 } 5534 5535 /* Disable autoneg by setting bit 31 of TXCW to zero */ 5536 txcw = E1000_READ_REG(hw, E1000_TXCW); 5537 txcw &= ~((uint32_t)1 << 31); 5538 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 5539 5540 /* 5541 * Write 0x410 to Serdes Control register 5542 * to enable Serdes analog loopback 5543 */ 5544 E1000_WRITE_REG(hw, E1000_SCTL, 0x0410); 5545 msec_delay(10); 5546 break; 5547 default: 5548 break; 5549 } 5550 break; 5551 case e1000_82574: 5552 case e1000_80003es2lan: 5553 case e1000_ich9lan: 5554 case e1000_ich10lan: 5555 (void) e1000_read_phy_reg(hw, GG82563_REG(6, 16), &phydata); 5556 (void) e1000_write_phy_reg(hw, GG82563_REG(6, 16), 5557 phydata | (1 << 5)); 5558 Adapter->param_adv_autoneg = 1; 5559 Adapter->param_adv_1000fdx = 1; 5560 (void) e1000g_reset_link(Adapter); 5561 break; 5562 } 5563 } 5564 5565 static void 5566 e1000g_set_external_loopback_100(struct e1000g *Adapter) 5567 { 5568 struct e1000_hw *hw; 5569 uint32_t ctrl; 5570 uint16_t phy_ctrl; 5571 5572 hw = &Adapter->shared; 5573 5574 /* Disable Smart Power Down */ 5575 phy_spd_state(hw, B_FALSE); 5576 5577 phy_ctrl = (MII_CR_FULL_DUPLEX | 5578 MII_CR_SPEED_100); 5579 5580 /* Force 100/FD, reset PHY */ 5581 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5582 phy_ctrl | MII_CR_RESET); /* 0xA100 */ 5583 msec_delay(10); 5584 5585 /* Force 100/FD */ 5586 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5587 phy_ctrl); /* 0x2100 */ 5588 msec_delay(10); 5589 5590 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5591 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5592 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5593 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5594 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5595 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5596 E1000_CTRL_SPD_100 | /* Force Speed to 100 */ 5597 E1000_CTRL_FD); /* Force Duplex to FULL */ 5598 5599 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5600 } 5601 5602 static void 5603 e1000g_set_external_loopback_10(struct e1000g *Adapter) 5604 { 5605 struct e1000_hw *hw; 5606 uint32_t ctrl; 5607 uint16_t phy_ctrl; 5608 5609 hw = &Adapter->shared; 5610 5611 /* Disable Smart Power Down */ 5612 phy_spd_state(hw, B_FALSE); 5613 5614 phy_ctrl = (MII_CR_FULL_DUPLEX | 5615 MII_CR_SPEED_10); 5616 5617 /* Force 10/FD, reset PHY */ 5618 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5619 phy_ctrl | MII_CR_RESET); /* 0x8100 */ 5620 msec_delay(10); 5621 5622 /* Force 10/FD */ 5623 (void) e1000_write_phy_reg(hw, PHY_CONTROL, 5624 phy_ctrl); /* 0x0100 */ 5625 msec_delay(10); 5626 5627 /* Now setup the MAC to the same speed/duplex as the PHY. */ 5628 ctrl = E1000_READ_REG(hw, E1000_CTRL); 5629 ctrl &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 5630 ctrl |= (E1000_CTRL_SLU | /* Force Link Up */ 5631 E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 5632 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 5633 E1000_CTRL_SPD_10 | /* Force Speed to 10 */ 5634 E1000_CTRL_FD); /* Force Duplex to FULL */ 5635 5636 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 5637 } 5638 5639 #ifdef __sparc 5640 static boolean_t 5641 e1000g_find_mac_address(struct e1000g *Adapter) 5642 { 5643 struct e1000_hw *hw = &Adapter->shared; 5644 uchar_t *bytes; 5645 struct ether_addr sysaddr; 5646 uint_t nelts; 5647 int err; 5648 boolean_t found = B_FALSE; 5649 5650 /* 5651 * The "vendor's factory-set address" may already have 5652 * been extracted from the chip, but if the property 5653 * "local-mac-address" is set we use that instead. 5654 * 5655 * We check whether it looks like an array of 6 5656 * bytes (which it should, if OBP set it). If we can't 5657 * make sense of it this way, we'll ignore it. 5658 */ 5659 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5660 DDI_PROP_DONTPASS, "local-mac-address", &bytes, &nelts); 5661 if (err == DDI_PROP_SUCCESS) { 5662 if (nelts == ETHERADDRL) { 5663 while (nelts--) 5664 hw->mac.addr[nelts] = bytes[nelts]; 5665 found = B_TRUE; 5666 } 5667 ddi_prop_free(bytes); 5668 } 5669 5670 /* 5671 * Look up the OBP property "local-mac-address?". If the user has set 5672 * 'local-mac-address? = false', use "the system address" instead. 5673 */ 5674 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 0, 5675 "local-mac-address?", &bytes, &nelts) == DDI_PROP_SUCCESS) { 5676 if (strncmp("false", (caddr_t)bytes, (size_t)nelts) == 0) { 5677 if (localetheraddr(NULL, &sysaddr) != 0) { 5678 bcopy(&sysaddr, hw->mac.addr, ETHERADDRL); 5679 found = B_TRUE; 5680 } 5681 } 5682 ddi_prop_free(bytes); 5683 } 5684 5685 /* 5686 * Finally(!), if there's a valid "mac-address" property (created 5687 * if we netbooted from this interface), we must use this instead 5688 * of any of the above to ensure that the NFS/install server doesn't 5689 * get confused by the address changing as Solaris takes over! 5690 */ 5691 err = ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, Adapter->dip, 5692 DDI_PROP_DONTPASS, "mac-address", &bytes, &nelts); 5693 if (err == DDI_PROP_SUCCESS) { 5694 if (nelts == ETHERADDRL) { 5695 while (nelts--) 5696 hw->mac.addr[nelts] = bytes[nelts]; 5697 found = B_TRUE; 5698 } 5699 ddi_prop_free(bytes); 5700 } 5701 5702 if (found) { 5703 bcopy(hw->mac.addr, hw->mac.perm_addr, 5704 ETHERADDRL); 5705 } 5706 5707 return (found); 5708 } 5709 #endif 5710 5711 static int 5712 e1000g_add_intrs(struct e1000g *Adapter) 5713 { 5714 dev_info_t *devinfo; 5715 int intr_types; 5716 int rc; 5717 5718 devinfo = Adapter->dip; 5719 5720 /* Get supported interrupt types */ 5721 rc = ddi_intr_get_supported_types(devinfo, &intr_types); 5722 5723 if (rc != DDI_SUCCESS) { 5724 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5725 "Get supported interrupt types failed: %d\n", rc); 5726 return (DDI_FAILURE); 5727 } 5728 5729 /* 5730 * Based on Intel Technical Advisory document (TA-160), there are some 5731 * cases where some older Intel PCI-X NICs may "advertise" to the OS 5732 * that it supports MSI, but in fact has problems. 5733 * So we should only enable MSI for PCI-E NICs and disable MSI for old 5734 * PCI/PCI-X NICs. 5735 */ 5736 if (Adapter->shared.mac.type < e1000_82571) 5737 Adapter->msi_enable = B_FALSE; 5738 5739 if ((intr_types & DDI_INTR_TYPE_MSI) && Adapter->msi_enable) { 5740 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_MSI); 5741 5742 if (rc != DDI_SUCCESS) { 5743 /* EMPTY */ 5744 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5745 "Add MSI failed, trying Legacy interrupts\n"); 5746 } else { 5747 Adapter->intr_type = DDI_INTR_TYPE_MSI; 5748 } 5749 } 5750 5751 if ((Adapter->intr_type == 0) && 5752 (intr_types & DDI_INTR_TYPE_FIXED)) { 5753 rc = e1000g_intr_add(Adapter, DDI_INTR_TYPE_FIXED); 5754 5755 if (rc != DDI_SUCCESS) { 5756 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5757 "Add Legacy interrupts failed\n"); 5758 return (DDI_FAILURE); 5759 } 5760 5761 Adapter->intr_type = DDI_INTR_TYPE_FIXED; 5762 } 5763 5764 if (Adapter->intr_type == 0) { 5765 E1000G_DEBUGLOG_0(Adapter, E1000G_WARN_LEVEL, 5766 "No interrupts registered\n"); 5767 return (DDI_FAILURE); 5768 } 5769 5770 return (DDI_SUCCESS); 5771 } 5772 5773 /* 5774 * e1000g_intr_add() handles MSI/Legacy interrupts 5775 */ 5776 static int 5777 e1000g_intr_add(struct e1000g *Adapter, int intr_type) 5778 { 5779 dev_info_t *devinfo; 5780 int count, avail, actual; 5781 int x, y, rc, inum = 0; 5782 int flag; 5783 ddi_intr_handler_t *intr_handler; 5784 5785 devinfo = Adapter->dip; 5786 5787 /* get number of interrupts */ 5788 rc = ddi_intr_get_nintrs(devinfo, intr_type, &count); 5789 if ((rc != DDI_SUCCESS) || (count == 0)) { 5790 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5791 "Get interrupt number failed. Return: %d, count: %d\n", 5792 rc, count); 5793 return (DDI_FAILURE); 5794 } 5795 5796 /* get number of available interrupts */ 5797 rc = ddi_intr_get_navail(devinfo, intr_type, &avail); 5798 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5799 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5800 "Get interrupt available number failed. " 5801 "Return: %d, available: %d\n", rc, avail); 5802 return (DDI_FAILURE); 5803 } 5804 5805 if (avail < count) { 5806 /* EMPTY */ 5807 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5808 "Interrupts count: %d, available: %d\n", 5809 count, avail); 5810 } 5811 5812 /* Allocate an array of interrupt handles */ 5813 Adapter->intr_size = count * sizeof (ddi_intr_handle_t); 5814 Adapter->htable = kmem_alloc(Adapter->intr_size, KM_SLEEP); 5815 5816 /* Set NORMAL behavior for both MSI and FIXED interrupt */ 5817 flag = DDI_INTR_ALLOC_NORMAL; 5818 5819 /* call ddi_intr_alloc() */ 5820 rc = ddi_intr_alloc(devinfo, Adapter->htable, intr_type, inum, 5821 count, &actual, flag); 5822 5823 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5824 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5825 "Allocate interrupts failed: %d\n", rc); 5826 5827 kmem_free(Adapter->htable, Adapter->intr_size); 5828 return (DDI_FAILURE); 5829 } 5830 5831 if (actual < count) { 5832 /* EMPTY */ 5833 E1000G_DEBUGLOG_2(Adapter, E1000G_WARN_LEVEL, 5834 "Interrupts requested: %d, received: %d\n", 5835 count, actual); 5836 } 5837 5838 Adapter->intr_cnt = actual; 5839 5840 /* Get priority for first msi, assume remaining are all the same */ 5841 rc = ddi_intr_get_pri(Adapter->htable[0], &Adapter->intr_pri); 5842 5843 if (rc != DDI_SUCCESS) { 5844 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5845 "Get interrupt priority failed: %d\n", rc); 5846 5847 /* Free already allocated intr */ 5848 for (y = 0; y < actual; y++) 5849 (void) ddi_intr_free(Adapter->htable[y]); 5850 5851 kmem_free(Adapter->htable, Adapter->intr_size); 5852 return (DDI_FAILURE); 5853 } 5854 5855 /* 5856 * In Legacy Interrupt mode, for PCI-Express adapters, we should 5857 * use the interrupt service routine e1000g_intr_pciexpress() 5858 * to avoid interrupt stealing when sharing interrupt with other 5859 * devices. 5860 */ 5861 if (Adapter->shared.mac.type < e1000_82571) 5862 intr_handler = (ddi_intr_handler_t *)e1000g_intr; 5863 else 5864 intr_handler = (ddi_intr_handler_t *)e1000g_intr_pciexpress; 5865 5866 /* Call ddi_intr_add_handler() */ 5867 for (x = 0; x < actual; x++) { 5868 rc = ddi_intr_add_handler(Adapter->htable[x], 5869 intr_handler, (caddr_t)Adapter, NULL); 5870 5871 if (rc != DDI_SUCCESS) { 5872 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5873 "Add interrupt handler failed: %d\n", rc); 5874 5875 /* Remove already added handler */ 5876 for (y = 0; y < x; y++) 5877 (void) ddi_intr_remove_handler( 5878 Adapter->htable[y]); 5879 5880 /* Free already allocated intr */ 5881 for (y = 0; y < actual; y++) 5882 (void) ddi_intr_free(Adapter->htable[y]); 5883 5884 kmem_free(Adapter->htable, Adapter->intr_size); 5885 return (DDI_FAILURE); 5886 } 5887 } 5888 5889 rc = ddi_intr_get_cap(Adapter->htable[0], &Adapter->intr_cap); 5890 5891 if (rc != DDI_SUCCESS) { 5892 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5893 "Get interrupt cap failed: %d\n", rc); 5894 5895 /* Free already allocated intr */ 5896 for (y = 0; y < actual; y++) { 5897 (void) ddi_intr_remove_handler(Adapter->htable[y]); 5898 (void) ddi_intr_free(Adapter->htable[y]); 5899 } 5900 5901 kmem_free(Adapter->htable, Adapter->intr_size); 5902 return (DDI_FAILURE); 5903 } 5904 5905 return (DDI_SUCCESS); 5906 } 5907 5908 static int 5909 e1000g_rem_intrs(struct e1000g *Adapter) 5910 { 5911 int x; 5912 int rc; 5913 5914 for (x = 0; x < Adapter->intr_cnt; x++) { 5915 rc = ddi_intr_remove_handler(Adapter->htable[x]); 5916 if (rc != DDI_SUCCESS) { 5917 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5918 "Remove intr handler failed: %d\n", rc); 5919 return (DDI_FAILURE); 5920 } 5921 5922 rc = ddi_intr_free(Adapter->htable[x]); 5923 if (rc != DDI_SUCCESS) { 5924 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5925 "Free intr failed: %d\n", rc); 5926 return (DDI_FAILURE); 5927 } 5928 } 5929 5930 kmem_free(Adapter->htable, Adapter->intr_size); 5931 5932 return (DDI_SUCCESS); 5933 } 5934 5935 static int 5936 e1000g_enable_intrs(struct e1000g *Adapter) 5937 { 5938 int x; 5939 int rc; 5940 5941 /* Enable interrupts */ 5942 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5943 /* Call ddi_intr_block_enable() for MSI */ 5944 rc = ddi_intr_block_enable(Adapter->htable, 5945 Adapter->intr_cnt); 5946 if (rc != DDI_SUCCESS) { 5947 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5948 "Enable block intr failed: %d\n", rc); 5949 return (DDI_FAILURE); 5950 } 5951 } else { 5952 /* Call ddi_intr_enable() for Legacy/MSI non block enable */ 5953 for (x = 0; x < Adapter->intr_cnt; x++) { 5954 rc = ddi_intr_enable(Adapter->htable[x]); 5955 if (rc != DDI_SUCCESS) { 5956 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5957 "Enable intr failed: %d\n", rc); 5958 return (DDI_FAILURE); 5959 } 5960 } 5961 } 5962 5963 return (DDI_SUCCESS); 5964 } 5965 5966 static int 5967 e1000g_disable_intrs(struct e1000g *Adapter) 5968 { 5969 int x; 5970 int rc; 5971 5972 /* Disable all interrupts */ 5973 if (Adapter->intr_cap & DDI_INTR_FLAG_BLOCK) { 5974 rc = ddi_intr_block_disable(Adapter->htable, 5975 Adapter->intr_cnt); 5976 if (rc != DDI_SUCCESS) { 5977 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5978 "Disable block intr failed: %d\n", rc); 5979 return (DDI_FAILURE); 5980 } 5981 } else { 5982 for (x = 0; x < Adapter->intr_cnt; x++) { 5983 rc = ddi_intr_disable(Adapter->htable[x]); 5984 if (rc != DDI_SUCCESS) { 5985 E1000G_DEBUGLOG_1(Adapter, E1000G_WARN_LEVEL, 5986 "Disable intr failed: %d\n", rc); 5987 return (DDI_FAILURE); 5988 } 5989 } 5990 } 5991 5992 return (DDI_SUCCESS); 5993 } 5994 5995 /* 5996 * e1000g_get_phy_state - get the state of PHY registers, save in the adapter 5997 */ 5998 static void 5999 e1000g_get_phy_state(struct e1000g *Adapter) 6000 { 6001 struct e1000_hw *hw = &Adapter->shared; 6002 6003 if (hw->phy.media_type == e1000_media_type_copper) { 6004 (void) e1000_read_phy_reg(hw, PHY_CONTROL, &Adapter->phy_ctrl); 6005 (void) e1000_read_phy_reg(hw, PHY_STATUS, &Adapter->phy_status); 6006 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, 6007 &Adapter->phy_an_adv); 6008 (void) e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, 6009 &Adapter->phy_an_exp); 6010 (void) e1000_read_phy_reg(hw, PHY_EXT_STATUS, 6011 &Adapter->phy_ext_status); 6012 (void) e1000_read_phy_reg(hw, PHY_1000T_CTRL, 6013 &Adapter->phy_1000t_ctrl); 6014 (void) e1000_read_phy_reg(hw, PHY_1000T_STATUS, 6015 &Adapter->phy_1000t_status); 6016 (void) e1000_read_phy_reg(hw, PHY_LP_ABILITY, 6017 &Adapter->phy_lp_able); 6018 6019 Adapter->param_autoneg_cap = 6020 (Adapter->phy_status & MII_SR_AUTONEG_CAPS) ? 1 : 0; 6021 Adapter->param_pause_cap = 6022 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6023 Adapter->param_asym_pause_cap = 6024 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6025 Adapter->param_1000fdx_cap = 6026 ((Adapter->phy_ext_status & IEEE_ESR_1000T_FD_CAPS) || 6027 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) ? 1 : 0; 6028 Adapter->param_1000hdx_cap = 6029 ((Adapter->phy_ext_status & IEEE_ESR_1000T_HD_CAPS) || 6030 (Adapter->phy_ext_status & IEEE_ESR_1000X_HD_CAPS)) ? 1 : 0; 6031 Adapter->param_100t4_cap = 6032 (Adapter->phy_status & MII_SR_100T4_CAPS) ? 1 : 0; 6033 Adapter->param_100fdx_cap = 6034 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6035 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) ? 1 : 0; 6036 Adapter->param_100hdx_cap = 6037 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6038 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) ? 1 : 0; 6039 Adapter->param_10fdx_cap = 6040 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6041 Adapter->param_10hdx_cap = 6042 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6043 6044 Adapter->param_adv_autoneg = hw->mac.autoneg; 6045 Adapter->param_adv_pause = 6046 (Adapter->phy_an_adv & NWAY_AR_PAUSE) ? 1 : 0; 6047 Adapter->param_adv_asym_pause = 6048 (Adapter->phy_an_adv & NWAY_AR_ASM_DIR) ? 1 : 0; 6049 Adapter->param_adv_1000hdx = 6050 (Adapter->phy_1000t_ctrl & CR_1000T_HD_CAPS) ? 1 : 0; 6051 Adapter->param_adv_100t4 = 6052 (Adapter->phy_an_adv & NWAY_AR_100T4_CAPS) ? 1 : 0; 6053 if (Adapter->param_adv_autoneg == 1) { 6054 Adapter->param_adv_1000fdx = 6055 (Adapter->phy_1000t_ctrl & CR_1000T_FD_CAPS) 6056 ? 1 : 0; 6057 Adapter->param_adv_100fdx = 6058 (Adapter->phy_an_adv & NWAY_AR_100TX_FD_CAPS) 6059 ? 1 : 0; 6060 Adapter->param_adv_100hdx = 6061 (Adapter->phy_an_adv & NWAY_AR_100TX_HD_CAPS) 6062 ? 1 : 0; 6063 Adapter->param_adv_10fdx = 6064 (Adapter->phy_an_adv & NWAY_AR_10T_FD_CAPS) ? 1 : 0; 6065 Adapter->param_adv_10hdx = 6066 (Adapter->phy_an_adv & NWAY_AR_10T_HD_CAPS) ? 1 : 0; 6067 } 6068 6069 Adapter->param_lp_autoneg = 6070 (Adapter->phy_an_exp & NWAY_ER_LP_NWAY_CAPS) ? 1 : 0; 6071 Adapter->param_lp_pause = 6072 (Adapter->phy_lp_able & NWAY_LPAR_PAUSE) ? 1 : 0; 6073 Adapter->param_lp_asym_pause = 6074 (Adapter->phy_lp_able & NWAY_LPAR_ASM_DIR) ? 1 : 0; 6075 Adapter->param_lp_1000fdx = 6076 (Adapter->phy_1000t_status & SR_1000T_LP_FD_CAPS) ? 1 : 0; 6077 Adapter->param_lp_1000hdx = 6078 (Adapter->phy_1000t_status & SR_1000T_LP_HD_CAPS) ? 1 : 0; 6079 Adapter->param_lp_100t4 = 6080 (Adapter->phy_lp_able & NWAY_LPAR_100T4_CAPS) ? 1 : 0; 6081 Adapter->param_lp_100fdx = 6082 (Adapter->phy_lp_able & NWAY_LPAR_100TX_FD_CAPS) ? 1 : 0; 6083 Adapter->param_lp_100hdx = 6084 (Adapter->phy_lp_able & NWAY_LPAR_100TX_HD_CAPS) ? 1 : 0; 6085 Adapter->param_lp_10fdx = 6086 (Adapter->phy_lp_able & NWAY_LPAR_10T_FD_CAPS) ? 1 : 0; 6087 Adapter->param_lp_10hdx = 6088 (Adapter->phy_lp_able & NWAY_LPAR_10T_HD_CAPS) ? 1 : 0; 6089 } else { 6090 /* 6091 * 1Gig Fiber adapter only offers 1Gig Full Duplex. Meaning, 6092 * it can only work with 1Gig Full Duplex Link Partner. 6093 */ 6094 Adapter->param_autoneg_cap = 0; 6095 Adapter->param_pause_cap = 1; 6096 Adapter->param_asym_pause_cap = 1; 6097 Adapter->param_1000fdx_cap = 1; 6098 Adapter->param_1000hdx_cap = 0; 6099 Adapter->param_100t4_cap = 0; 6100 Adapter->param_100fdx_cap = 0; 6101 Adapter->param_100hdx_cap = 0; 6102 Adapter->param_10fdx_cap = 0; 6103 Adapter->param_10hdx_cap = 0; 6104 6105 Adapter->param_adv_autoneg = 0; 6106 Adapter->param_adv_pause = 1; 6107 Adapter->param_adv_asym_pause = 1; 6108 Adapter->param_adv_1000fdx = 1; 6109 Adapter->param_adv_1000hdx = 0; 6110 Adapter->param_adv_100t4 = 0; 6111 Adapter->param_adv_100fdx = 0; 6112 Adapter->param_adv_100hdx = 0; 6113 Adapter->param_adv_10fdx = 0; 6114 Adapter->param_adv_10hdx = 0; 6115 6116 Adapter->param_lp_autoneg = 0; 6117 Adapter->param_lp_pause = 0; 6118 Adapter->param_lp_asym_pause = 0; 6119 Adapter->param_lp_1000fdx = 0; 6120 Adapter->param_lp_1000hdx = 0; 6121 Adapter->param_lp_100t4 = 0; 6122 Adapter->param_lp_100fdx = 0; 6123 Adapter->param_lp_100hdx = 0; 6124 Adapter->param_lp_10fdx = 0; 6125 Adapter->param_lp_10hdx = 0; 6126 } 6127 } 6128 6129 /* 6130 * FMA support 6131 */ 6132 6133 int 6134 e1000g_check_acc_handle(ddi_acc_handle_t handle) 6135 { 6136 ddi_fm_error_t de; 6137 6138 ddi_fm_acc_err_get(handle, &de, DDI_FME_VERSION); 6139 ddi_fm_acc_err_clear(handle, DDI_FME_VERSION); 6140 return (de.fme_status); 6141 } 6142 6143 int 6144 e1000g_check_dma_handle(ddi_dma_handle_t handle) 6145 { 6146 ddi_fm_error_t de; 6147 6148 ddi_fm_dma_err_get(handle, &de, DDI_FME_VERSION); 6149 return (de.fme_status); 6150 } 6151 6152 /* 6153 * The IO fault service error handling callback function 6154 */ 6155 /* ARGSUSED2 */ 6156 static int 6157 e1000g_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 6158 { 6159 /* 6160 * as the driver can always deal with an error in any dma or 6161 * access handle, we can just return the fme_status value. 6162 */ 6163 pci_ereport_post(dip, err, NULL); 6164 return (err->fme_status); 6165 } 6166 6167 static void 6168 e1000g_fm_init(struct e1000g *Adapter) 6169 { 6170 ddi_iblock_cookie_t iblk; 6171 int fma_dma_flag; 6172 6173 /* Only register with IO Fault Services if we have some capability */ 6174 if (Adapter->fm_capabilities & DDI_FM_ACCCHK_CAPABLE) { 6175 e1000g_regs_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 6176 } else { 6177 e1000g_regs_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 6178 } 6179 6180 if (Adapter->fm_capabilities & DDI_FM_DMACHK_CAPABLE) { 6181 fma_dma_flag = 1; 6182 } else { 6183 fma_dma_flag = 0; 6184 } 6185 6186 (void) e1000g_set_fma_flags(fma_dma_flag); 6187 6188 if (Adapter->fm_capabilities) { 6189 6190 /* Register capabilities with IO Fault Services */ 6191 ddi_fm_init(Adapter->dip, &Adapter->fm_capabilities, &iblk); 6192 6193 /* 6194 * Initialize pci ereport capabilities if ereport capable 6195 */ 6196 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6197 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6198 pci_ereport_setup(Adapter->dip); 6199 6200 /* 6201 * Register error callback if error callback capable 6202 */ 6203 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6204 ddi_fm_handler_register(Adapter->dip, 6205 e1000g_fm_error_cb, (void*) Adapter); 6206 } 6207 } 6208 6209 static void 6210 e1000g_fm_fini(struct e1000g *Adapter) 6211 { 6212 /* Only unregister FMA capabilities if we registered some */ 6213 if (Adapter->fm_capabilities) { 6214 6215 /* 6216 * Release any resources allocated by pci_ereport_setup() 6217 */ 6218 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities) || 6219 DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6220 pci_ereport_teardown(Adapter->dip); 6221 6222 /* 6223 * Un-register error callback if error callback capable 6224 */ 6225 if (DDI_FM_ERRCB_CAP(Adapter->fm_capabilities)) 6226 ddi_fm_handler_unregister(Adapter->dip); 6227 6228 /* Unregister from IO Fault Services */ 6229 mutex_enter(&e1000g_rx_detach_lock); 6230 ddi_fm_fini(Adapter->dip); 6231 if (Adapter->priv_dip != NULL) { 6232 DEVI(Adapter->priv_dip)->devi_fmhdl = NULL; 6233 } 6234 mutex_exit(&e1000g_rx_detach_lock); 6235 } 6236 } 6237 6238 void 6239 e1000g_fm_ereport(struct e1000g *Adapter, char *detail) 6240 { 6241 uint64_t ena; 6242 char buf[FM_MAX_CLASS]; 6243 6244 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 6245 ena = fm_ena_generate(0, FM_ENA_FMT1); 6246 if (DDI_FM_EREPORT_CAP(Adapter->fm_capabilities)) { 6247 ddi_fm_ereport_post(Adapter->dip, buf, ena, DDI_NOSLEEP, 6248 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 6249 } 6250 } 6251 6252 /* 6253 * quiesce(9E) entry point. 6254 * 6255 * This function is called when the system is single-threaded at high 6256 * PIL with preemption disabled. Therefore, this function must not be 6257 * blocked. 6258 * 6259 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6260 * DDI_FAILURE indicates an error condition and should almost never happen. 6261 */ 6262 static int 6263 e1000g_quiesce(dev_info_t *devinfo) 6264 { 6265 struct e1000g *Adapter; 6266 6267 Adapter = (struct e1000g *)ddi_get_driver_private(devinfo); 6268 6269 if (Adapter == NULL) 6270 return (DDI_FAILURE); 6271 6272 e1000g_clear_all_interrupts(Adapter); 6273 6274 (void) e1000_reset_hw(&Adapter->shared); 6275 6276 /* Setup our HW Tx Head & Tail descriptor pointers */ 6277 E1000_WRITE_REG(&Adapter->shared, E1000_TDH(0), 0); 6278 E1000_WRITE_REG(&Adapter->shared, E1000_TDT(0), 0); 6279 6280 /* Setup our HW Rx Head & Tail descriptor pointers */ 6281 E1000_WRITE_REG(&Adapter->shared, E1000_RDH(0), 0); 6282 E1000_WRITE_REG(&Adapter->shared, E1000_RDT(0), 0); 6283 6284 return (DDI_SUCCESS); 6285 } 6286 6287 static int 6288 e1000g_get_def_val(struct e1000g *Adapter, mac_prop_id_t pr_num, 6289 uint_t pr_valsize, void *pr_val) 6290 { 6291 link_flowctrl_t fl; 6292 struct e1000_hw *hw = &Adapter->shared; 6293 int err = 0; 6294 6295 ASSERT(pr_valsize > 0); 6296 switch (pr_num) { 6297 case MAC_PROP_AUTONEG: 6298 if (hw->phy.media_type != e1000_media_type_copper) 6299 *(uint8_t *)pr_val = 0; 6300 else 6301 *(uint8_t *)pr_val = 6302 ((Adapter->phy_status & MII_SR_AUTONEG_CAPS) 6303 ? 1 : 0); 6304 break; 6305 case MAC_PROP_FLOWCTRL: 6306 if (pr_valsize < sizeof (link_flowctrl_t)) 6307 return (EINVAL); 6308 fl = LINK_FLOWCTRL_BI; 6309 bcopy(&fl, pr_val, sizeof (fl)); 6310 break; 6311 case MAC_PROP_ADV_1000FDX_CAP: 6312 case MAC_PROP_EN_1000FDX_CAP: 6313 if (hw->phy.media_type != e1000_media_type_copper) 6314 *(uint8_t *)pr_val = 1; 6315 else 6316 *(uint8_t *)pr_val = 6317 ((Adapter->phy_ext_status & 6318 IEEE_ESR_1000T_FD_CAPS) || 6319 (Adapter->phy_ext_status & IEEE_ESR_1000X_FD_CAPS)) 6320 ? 1 : 0; 6321 break; 6322 case MAC_PROP_ADV_1000HDX_CAP: 6323 case MAC_PROP_EN_1000HDX_CAP: 6324 *(uint8_t *)pr_val = 0; 6325 break; 6326 case MAC_PROP_ADV_100FDX_CAP: 6327 case MAC_PROP_EN_100FDX_CAP: 6328 if (hw->phy.media_type != e1000_media_type_copper) 6329 *(uint8_t *)pr_val = 0; 6330 else 6331 *(uint8_t *)pr_val = 6332 ((Adapter->phy_status & MII_SR_100X_FD_CAPS) || 6333 (Adapter->phy_status & MII_SR_100T2_FD_CAPS)) 6334 ? 1 : 0; 6335 break; 6336 case MAC_PROP_ADV_100HDX_CAP: 6337 case MAC_PROP_EN_100HDX_CAP: 6338 if (hw->phy.media_type != e1000_media_type_copper) 6339 *(uint8_t *)pr_val = 0; 6340 else 6341 *(uint8_t *)pr_val = 6342 ((Adapter->phy_status & MII_SR_100X_HD_CAPS) || 6343 (Adapter->phy_status & MII_SR_100T2_HD_CAPS)) 6344 ? 1 : 0; 6345 break; 6346 case MAC_PROP_ADV_10FDX_CAP: 6347 case MAC_PROP_EN_10FDX_CAP: 6348 if (hw->phy.media_type != e1000_media_type_copper) 6349 *(uint8_t *)pr_val = 0; 6350 else 6351 *(uint8_t *)pr_val = 6352 (Adapter->phy_status & MII_SR_10T_FD_CAPS) ? 1 : 0; 6353 break; 6354 case MAC_PROP_ADV_10HDX_CAP: 6355 case MAC_PROP_EN_10HDX_CAP: 6356 if (hw->phy.media_type != e1000_media_type_copper) 6357 *(uint8_t *)pr_val = 0; 6358 else 6359 *(uint8_t *)pr_val = 6360 (Adapter->phy_status & MII_SR_10T_HD_CAPS) ? 1 : 0; 6361 break; 6362 default: 6363 err = ENOTSUP; 6364 break; 6365 } 6366 return (err); 6367 } 6368 6369 /* 6370 * synchronize the adv* and en* parameters. 6371 * 6372 * See comments in <sys/dld.h> for details of the *_en_* 6373 * parameters. The usage of ndd for setting adv parameters will 6374 * synchronize all the en parameters with the e1000g parameters, 6375 * implicitly disabling any settings made via dladm. 6376 */ 6377 static void 6378 e1000g_param_sync(struct e1000g *Adapter) 6379 { 6380 Adapter->param_en_1000fdx = Adapter->param_adv_1000fdx; 6381 Adapter->param_en_1000hdx = Adapter->param_adv_1000hdx; 6382 Adapter->param_en_100fdx = Adapter->param_adv_100fdx; 6383 Adapter->param_en_100hdx = Adapter->param_adv_100hdx; 6384 Adapter->param_en_10fdx = Adapter->param_adv_10fdx; 6385 Adapter->param_en_10hdx = Adapter->param_adv_10hdx; 6386 } 6387 6388 /* 6389 * e1000g_get_driver_control - tell manageability firmware that the driver 6390 * has control. 6391 */ 6392 static void 6393 e1000g_get_driver_control(struct e1000_hw *hw) 6394 { 6395 uint32_t ctrl_ext; 6396 uint32_t swsm; 6397 6398 /* tell manageability firmware the driver has taken over */ 6399 switch (hw->mac.type) { 6400 case e1000_82573: 6401 swsm = E1000_READ_REG(hw, E1000_SWSM); 6402 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_DRV_LOAD); 6403 break; 6404 case e1000_82571: 6405 case e1000_82572: 6406 case e1000_82574: 6407 case e1000_80003es2lan: 6408 case e1000_ich8lan: 6409 case e1000_ich9lan: 6410 case e1000_ich10lan: 6411 case e1000_pchlan: 6412 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6413 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6414 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 6415 break; 6416 default: 6417 /* no manageability firmware: do nothing */ 6418 break; 6419 } 6420 } 6421 6422 /* 6423 * e1000g_release_driver_control - tell manageability firmware that the driver 6424 * has released control. 6425 */ 6426 static void 6427 e1000g_release_driver_control(struct e1000_hw *hw) 6428 { 6429 uint32_t ctrl_ext; 6430 uint32_t swsm; 6431 6432 /* tell manageability firmware the driver has released control */ 6433 switch (hw->mac.type) { 6434 case e1000_82573: 6435 swsm = E1000_READ_REG(hw, E1000_SWSM); 6436 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_DRV_LOAD); 6437 break; 6438 case e1000_82571: 6439 case e1000_82572: 6440 case e1000_82574: 6441 case e1000_80003es2lan: 6442 case e1000_ich8lan: 6443 case e1000_ich9lan: 6444 case e1000_ich10lan: 6445 case e1000_pchlan: 6446 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 6447 E1000_WRITE_REG(hw, E1000_CTRL_EXT, 6448 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 6449 break; 6450 default: 6451 /* no manageability firmware: do nothing */ 6452 break; 6453 } 6454 } 6455 6456 /* 6457 * Restore e1000g promiscuous mode. 6458 */ 6459 static void 6460 e1000g_restore_promisc(struct e1000g *Adapter) 6461 { 6462 if (Adapter->e1000g_promisc) { 6463 uint32_t rctl; 6464 6465 rctl = E1000_READ_REG(&Adapter->shared, E1000_RCTL); 6466 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_BAM); 6467 E1000_WRITE_REG(&Adapter->shared, E1000_RCTL, rctl); 6468 } 6469 } 6470